SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_init_config(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 441 {
 442         ah->hw_version.magic = AR5416_MAGIC;
 443         ah->regulatory.country_code = CTRY_DEFAULT;
 444         ah->hw_version.subvendorid = 0;
 445
 446         ah->ah_flags = 0;
 447         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 448                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 449         if (!AR_SREV_9100(ah))
 450                 ah->ah_flags = AH_USE_EEPROM;
 451
 452         ah->regulatory.power_limit = MAX_RATE_POWER;
 453         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 454         ah->atim_window = 0;
 455         ah->diversity_control = ah->config.diversity_control;
 456         ah->antenna_switch_swap =
 457                 ah->config.antenna_switch_swap;
 458         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 459         ah->beacon_interval = 100;
 460         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 461         ah->slottime = (u32) -1;
 462         ah->acktimeout = (u32) -1;
 463         ah->ctstimeout = (u32) -1;
 464         ah->globaltxtimeout = (u32) -1;
 465
 466         ah->gbeacon_rate = 0;
 467
 468         ah->power_mode = ATH9K_PM_UNDEFINED;
 469 }
 470
 471 static int ath9k_hw_rfattach(struct ath_hw *ah)
 472 {
 473         bool rfStatus = false;
 474         int ecode = 0;
 475
 476         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 477         if (!rfStatus) {
 478                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 479                         "RF setup failed, status: %u\n", ecode);
 480                 return ecode;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 487 {
 488         u32 val;
 489
 490         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 491
 492         val = ath9k_hw_get_radiorev(ah);
 493         switch (val & AR_RADIO_SREV_MAJOR) {
 494         case 0:
 495                 val = AR_RAD5133_SREV_MAJOR;
 496                 break;
 497         case AR_RAD5133_SREV_MAJOR:
 498         case AR_RAD5122_SREV_MAJOR:
 499         case AR_RAD2133_SREV_MAJOR:
 500         case AR_RAD2122_SREV_MAJOR:
 501                 break;
 502         default:
 503                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 504                         "Radio Chip Rev 0x%02X not supported\n",
 505                         val & AR_RADIO_SREV_MAJOR);
 506                 return -EOPNOTSUPP;
 507         }
 508
 509         ah->hw_version.analog5GhzRev = val;
 510
 511         return 0;
 512 }
 513
 514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 515 {
 516         u32 sum;
 517         int i;
 518         u16 eeval;
 519
 520         sum = 0;
 521         for (i = 0; i < 3; i++) {
 522                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 523                 sum += eeval;
 524                 ah->macaddr[2 * i] = eeval >> 8;
 525                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 526         }
 527         if (sum == 0 || sum == 0xffff * 3)
 528                 return -EADDRNOTAVAIL;
 529
 530         return 0;
 531 }
 532
 533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 534 {
 535         u32 rxgain_type;
 536
 537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 538                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 539
 540                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 541                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 542                         ar9280Modes_backoff_13db_rxgain_9280_2,
 543                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 544                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 545                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 546                         ar9280Modes_backoff_23db_rxgain_9280_2,
 547                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 548                 else
 549                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 550                         ar9280Modes_original_rxgain_9280_2,
 551                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 552         } else {
 553                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 554                         ar9280Modes_original_rxgain_9280_2,
 555                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 556         }
 557 }
 558
 559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 560 {
 561         u32 txgain_type;
 562
 563         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 564                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 565
 566                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 567                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 568                         ar9280Modes_high_power_tx_gain_9280_2,
 569                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 570                 else
 571                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                         ar9280Modes_original_tx_gain_9280_2,
 573                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 574         } else {
 575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 576                 ar9280Modes_original_tx_gain_9280_2,
 577                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 578         }
 579 }
 580
 581 static int ath9k_hw_post_init(struct ath_hw *ah)
 582 {
 583         int ecode;
 584
 585         if (!ath9k_hw_chip_test(ah))
 586                 return -ENODEV;
 587
 588         ecode = ath9k_hw_rf_claim(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591
 592         ecode = ath9k_hw_eeprom_init(ah);
 593         if (ecode != 0)
 594                 return ecode;
 595
 596         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 597                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 598
 599         ecode = ath9k_hw_rfattach(ah);
 600         if (ecode != 0)
 601                 return ecode;
 602
 603         if (!AR_SREV_9100(ah)) {
 604                 ath9k_hw_ani_setup(ah);
 605                 ath9k_hw_ani_init(ah);
 606         }
 607
 608         return 0;
 609 }
 610
 611 static bool ath9k_hw_devid_supported(u16 devid)
 612 {
 613         switch (devid) {
 614         case AR5416_DEVID_PCI:
 615         case AR5416_DEVID_PCIE:
 616         case AR5416_AR9100_DEVID:
 617         case AR9160_DEVID_PCI:
 618         case AR9280_DEVID_PCI:
 619         case AR9280_DEVID_PCIE:
 620         case AR9285_DEVID_PCIE:
 621         case AR5416_DEVID_AR9287_PCI:
 622         case AR5416_DEVID_AR9287_PCIE:
 623                 return true;
 624         default:
 625                 break;
 626         }
 627         return false;
 628 }
 629
 630 static bool ath9k_hw_macversion_supported(u32 macversion)
 631 {
 632         switch (macversion) {
 633         case AR_SREV_VERSION_5416_PCI:
 634         case AR_SREV_VERSION_5416_PCIE:
 635         case AR_SREV_VERSION_9160:
 636         case AR_SREV_VERSION_9100:
 637         case AR_SREV_VERSION_9280:
 638         case AR_SREV_VERSION_9285:
 639         case AR_SREV_VERSION_9287:
 640                 return true;
 641         /* Not yet */
 642         case AR_SREV_VERSION_9271:
 643         default:
 644                 break;
 645         }
 646         return false;
 647 }
 648
 649 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 650 {
 651         if (AR_SREV_9160_10_OR_LATER(ah)) {
 652                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 653                         ah->iq_caldata.calData = &iq_cal_single_sample;
 654                         ah->adcgain_caldata.calData =
 655                                 &adc_gain_cal_single_sample;
 656                         ah->adcdc_caldata.calData =
 657                                 &adc_dc_cal_single_sample;
 658                         ah->adcdc_calinitdata.calData =
 659                                 &adc_init_dc_cal;
 660                 } else {
 661                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 662                         ah->adcgain_caldata.calData =
 663                                 &adc_gain_cal_multi_sample;
 664                         ah->adcdc_caldata.calData =
 665                                 &adc_dc_cal_multi_sample;
 666                         ah->adcdc_calinitdata.calData =
 667                                 &adc_init_dc_cal;
 668                 }
 669                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 670         }
 671 }
 672
 673 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 674 {
 675         if (AR_SREV_9271(ah)) {
 676                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
 677                                ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
 678                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
 679                                ARRAY_SIZE(ar9271Common_9271_1_0), 2);
 680                 return;
 681         }
 682
 683         if (AR_SREV_9287_11_OR_LATER(ah)) {
 684                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 685                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 686                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 687                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 688                 if (ah->config.pcie_clock_req)
 689                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 690                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 691                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 692                 else
 693                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 694                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 695                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 696                                         2);
 697         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 698                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 699                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 700                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 701                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 702
 703                 if (ah->config.pcie_clock_req)
 704                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 705                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 706                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 707                 else
 708                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 709                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 710                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 711                                   2);
 712         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 713
 714
 715                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 716                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 717                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 718                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 719
 720                 if (ah->config.pcie_clock_req) {
 721                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 722                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 723                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 724                 } else {
 725                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 726                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 727                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 728                                   2);
 729                 }
 730         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 731                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 732                                ARRAY_SIZE(ar9285Modes_9285), 6);
 733                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 734                                ARRAY_SIZE(ar9285Common_9285), 2);
 735
 736                 if (ah->config.pcie_clock_req) {
 737                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 738                         ar9285PciePhy_clkreq_off_L1_9285,
 739                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 740                 } else {
 741                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 742                         ar9285PciePhy_clkreq_always_on_L1_9285,
 743                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 744                 }
 745         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 746                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 747                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 748                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 749                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 750
 751                 if (ah->config.pcie_clock_req) {
 752                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 753                                ar9280PciePhy_clkreq_off_L1_9280,
 754                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 755                 } else {
 756                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 757                                ar9280PciePhy_clkreq_always_on_L1_9280,
 758                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 759                 }
 760                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 761                                ar9280Modes_fast_clock_9280_2,
 762                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 763         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 764                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 765                                ARRAY_SIZE(ar9280Modes_9280), 6);
 766                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 767                                ARRAY_SIZE(ar9280Common_9280), 2);
 768         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 769                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 770                                ARRAY_SIZE(ar5416Modes_9160), 6);
 771                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 772                                ARRAY_SIZE(ar5416Common_9160), 2);
 773                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 774                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 775                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 776                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 777                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 778                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 779                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 780                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 781                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 782                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 783                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 784                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 785                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 786                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 787                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 788                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 789                 if (AR_SREV_9160_11(ah)) {
 790                         INIT_INI_ARRAY(&ah->iniAddac,
 791                                        ar5416Addac_91601_1,
 792                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 793                 } else {
 794                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 795                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 796                 }
 797         } else if (AR_SREV_9100_OR_LATER(ah)) {
 798                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 799                                ARRAY_SIZE(ar5416Modes_9100), 6);
 800                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 801                                ARRAY_SIZE(ar5416Common_9100), 2);
 802                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 803                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 804                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 805                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 806                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 807                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 808                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 809                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 810                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 811                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 812                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 813                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 814                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 815                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 816                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 817                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 818                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 819                                ARRAY_SIZE(ar5416Addac_9100), 2);
 820         } else {
 821                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 822                                ARRAY_SIZE(ar5416Modes), 6);
 823                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 824                                ARRAY_SIZE(ar5416Common), 2);
 825                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 826                                ARRAY_SIZE(ar5416Bank0), 2);
 827                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 828                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 829                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 830                                ARRAY_SIZE(ar5416Bank1), 2);
 831                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 832                                ARRAY_SIZE(ar5416Bank2), 2);
 833                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 834                                ARRAY_SIZE(ar5416Bank3), 3);
 835                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 836                                ARRAY_SIZE(ar5416Bank6), 3);
 837                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 838                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 839                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 840                                ARRAY_SIZE(ar5416Bank7), 2);
 841                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 842                                ARRAY_SIZE(ar5416Addac), 2);
 843         }
 844 }
 845
 846 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 847 {
 848         if (AR_SREV_9287_11(ah))
 849                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 850                 ar9287Modes_rx_gain_9287_1_1,
 851                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 852         else if (AR_SREV_9287_10(ah))
 853                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 854                 ar9287Modes_rx_gain_9287_1_0,
 855                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 856         else if (AR_SREV_9280_20(ah))
 857                 ath9k_hw_init_rxgain_ini(ah);
 858
 859         if (AR_SREV_9287_11(ah)) {
 860                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 861                 ar9287Modes_tx_gain_9287_1_1,
 862                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 863         } else if (AR_SREV_9287_10(ah)) {
 864                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 865                 ar9287Modes_tx_gain_9287_1_0,
 866                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 867         } else if (AR_SREV_9280_20(ah)) {
 868                 ath9k_hw_init_txgain_ini(ah);
 869         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 870                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 871
 872                 /* txgain table */
 873                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 874                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 875                         ar9285Modes_high_power_tx_gain_9285_1_2,
 876                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 877                 } else {
 878                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 879                         ar9285Modes_original_tx_gain_9285_1_2,
 880                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 881                 }
 882
 883         }
 884 }
 885
 886 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 887 {
 888         u32 i, j;
 889
 890         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 891             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 892
 893                 /* EEPROM Fixup */
 894                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 895                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 896
 897                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 898                                 u32 val = INI_RA(&ah->iniModes, i, j);
 899
 900                                 INI_RA(&ah->iniModes, i, j) =
 901                                         ath9k_hw_ini_fixup(ah,
 902                                                            &ah->eeprom.def,
 903                                                            reg, val);
 904                         }
 905                 }
 906         }
 907 }
 908
 909 int ath9k_hw_init(struct ath_hw *ah)
 910 {
 911         int r = 0;
 912
 913         if (!ath9k_hw_devid_supported(ah->hw_version.devid))
 914                 return -EOPNOTSUPP;
 915
 916         ath9k_hw_init_defaults(ah);
 917         ath9k_hw_init_config(ah);
 918
 919         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 920                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 921                 return -EIO;
 922         }
 923
 924         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 925                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 926                 return -EIO;
 927         }
 928
 929         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 930                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 931                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 932                         ah->config.serialize_regmode =
 933                                 SER_REG_MODE_ON;
 934                 } else {
 935                         ah->config.serialize_regmode =
 936                                 SER_REG_MODE_OFF;
 937                 }
 938         }
 939
 940         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 941                 ah->config.serialize_regmode);
 942
 943         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 944                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 945                         "Mac Chip Rev 0x%02x.%x is not supported by "
 946                         "this driver\n", ah->hw_version.macVersion,
 947                         ah->hw_version.macRev);
 948                 return -EOPNOTSUPP;
 949         }
 950
 951         if (AR_SREV_9100(ah)) {
 952                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 953                 ah->supp_cals = IQ_MISMATCH_CAL;
 954                 ah->is_pciexpress = false;
 955         }
 956
 957         if (AR_SREV_9271(ah))
 958                 ah->is_pciexpress = false;
 959
 960         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 961
 962         ath9k_hw_init_cal_settings(ah);
 963
 964         ah->ani_function = ATH9K_ANI_ALL;
 965         if (AR_SREV_9280_10_OR_LATER(ah))
 966                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 967
 968         ath9k_hw_init_mode_regs(ah);
 969
 970         if (ah->is_pciexpress)
 971                 ath9k_hw_configpcipowersave(ah, 0);
 972         else
 973                 ath9k_hw_disablepcie(ah);
 974
 975         r = ath9k_hw_post_init(ah);
 976         if (r)
 977                 return r;
 978
 979         ath9k_hw_init_mode_gain_regs(ah);
 980         ath9k_hw_fill_cap_info(ah);
 981         ath9k_hw_init_11a_eeprom_fix(ah);
 982
 983         r = ath9k_hw_init_macaddr(ah);
 984         if (r) {
 985                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 986                         "Failed to initialize MAC address\n");
 987                 return r;
 988         }
 989
 990         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 991                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 992         else
 993                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 994
 995         ath9k_init_nfcal_hist_buffer(ah);
 996
 997         return 0;
 998 }
 999
1000 static void ath9k_hw_init_bb(struct ath_hw *ah,
1001                              struct ath9k_channel *chan)
1002 {
1003         u32 synthDelay;
1004
1005         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1006         if (IS_CHAN_B(chan))
1007                 synthDelay = (4 * synthDelay) / 22;
1008         else
1009                 synthDelay /= 10;
1010
1011         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1012
1013         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1014 }
1015
1016 static void ath9k_hw_init_qos(struct ath_hw *ah)
1017 {
1018         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1019         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1020
1021         REG_WRITE(ah, AR_QOS_NO_ACK,
1022                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1023                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1024                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1025
1026         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1027         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1028         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1029         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1030         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1031 }
1032
1033 static void ath9k_hw_init_pll(struct ath_hw *ah,
1034                               struct ath9k_channel *chan)
1035 {
1036         u32 pll;
1037
1038         if (AR_SREV_9100(ah)) {
1039                 if (chan && IS_CHAN_5GHZ(chan))
1040                         pll = 0x1450;
1041                 else
1042                         pll = 0x1458;
1043         } else {
1044                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1045                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1046
1047                         if (chan && IS_CHAN_HALF_RATE(chan))
1048                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1049                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1050                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1051
1052                         if (chan && IS_CHAN_5GHZ(chan)) {
1053                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1054
1055
1056                                 if (AR_SREV_9280_20(ah)) {
1057                                         if (((chan->channel % 20) == 0)
1058                                             || ((chan->channel % 10) == 0))
1059                                                 pll = 0x2850;
1060                                         else
1061                                                 pll = 0x142c;
1062                                 }
1063                         } else {
1064                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1065                         }
1066
1067                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1068
1069                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1070
1071                         if (chan && IS_CHAN_HALF_RATE(chan))
1072                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1073                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1074                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1075
1076                         if (chan && IS_CHAN_5GHZ(chan))
1077                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1078                         else
1079                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1080                 } else {
1081                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1082
1083                         if (chan && IS_CHAN_HALF_RATE(chan))
1084                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1085                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1086                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1087
1088                         if (chan && IS_CHAN_5GHZ(chan))
1089                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1090                         else
1091                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1092                 }
1093         }
1094         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1095
1096         udelay(RTC_PLL_SETTLE_DELAY);
1097
1098         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1099 }
1100
1101 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1102 {
1103         int rx_chainmask, tx_chainmask;
1104
1105         rx_chainmask = ah->rxchainmask;
1106         tx_chainmask = ah->txchainmask;
1107
1108         switch (rx_chainmask) {
1109         case 0x5:
1110                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1111                             AR_PHY_SWAP_ALT_CHAIN);
1112         case 0x3:
1113                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1114                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1115                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1116                         break;
1117                 }
1118         case 0x1:
1119         case 0x2:
1120         case 0x7:
1121                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1122                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1123                 break;
1124         default:
1125                 break;
1126         }
1127
1128         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1129         if (tx_chainmask == 0x5) {
1130                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1131                             AR_PHY_SWAP_ALT_CHAIN);
1132         }
1133         if (AR_SREV_9100(ah))
1134                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1135                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1136 }
1137
1138 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1139                                           enum nl80211_iftype opmode)
1140 {
1141         ah->mask_reg = AR_IMR_TXERR |
1142                 AR_IMR_TXURN |
1143                 AR_IMR_RXERR |
1144                 AR_IMR_RXORN |
1145                 AR_IMR_BCNMISC;
1146
1147         if (ah->config.intr_mitigation)
1148                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1149         else
1150                 ah->mask_reg |= AR_IMR_RXOK;
1151
1152         ah->mask_reg |= AR_IMR_TXOK;
1153
1154         if (opmode == NL80211_IFTYPE_AP)
1155                 ah->mask_reg |= AR_IMR_MIB;
1156
1157         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1158         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1159
1160         if (!AR_SREV_9100(ah)) {
1161                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1162                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1163                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1164         }
1165 }
1166
1167 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1168 {
1169         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1170                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1171                 ah->acktimeout = (u32) -1;
1172                 return false;
1173         } else {
1174                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1175                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1176                 ah->acktimeout = us;
1177                 return true;
1178         }
1179 }
1180
1181 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1182 {
1183         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1184                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1185                 ah->ctstimeout = (u32) -1;
1186                 return false;
1187         } else {
1188                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1189                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1190                 ah->ctstimeout = us;
1191                 return true;
1192         }
1193 }
1194
1195 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1196 {
1197         if (tu > 0xFFFF) {
1198                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1199                         "bad global tx timeout %u\n", tu);
1200                 ah->globaltxtimeout = (u32) -1;
1201                 return false;
1202         } else {
1203                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1204                 ah->globaltxtimeout = tu;
1205                 return true;
1206         }
1207 }
1208
1209 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1210 {
1211         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1212                 ah->misc_mode);
1213
1214         if (ah->misc_mode != 0)
1215                 REG_WRITE(ah, AR_PCU_MISC,
1216                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1217         if (ah->slottime != (u32) -1)
1218                 ath9k_hw_setslottime(ah, ah->slottime);
1219         if (ah->acktimeout != (u32) -1)
1220                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1221         if (ah->ctstimeout != (u32) -1)
1222                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1223         if (ah->globaltxtimeout != (u32) -1)
1224                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1225 }
1226
1227 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1228 {
1229         return vendorid == ATHEROS_VENDOR_ID ?
1230                 ath9k_hw_devname(devid) : NULL;
1231 }
1232
1233 void ath9k_hw_detach(struct ath_hw *ah)
1234 {
1235         if (!AR_SREV_9100(ah))
1236                 ath9k_hw_ani_disable(ah);
1237
1238         ath9k_hw_rf_free(ah);
1239         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1240         kfree(ah);
1241         ah = NULL;
1242 }
1243
1244 /*******/
1245 /* INI */
1246 /*******/
1247
1248 static void ath9k_hw_override_ini(struct ath_hw *ah,
1249                                   struct ath9k_channel *chan)
1250 {
1251         u32 val;
1252
1253         if (AR_SREV_9271(ah)) {
1254                 /*
1255                  * Enable spectral scan to solution for issues with stuck
1256                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1257                  * AR9271 1.1
1258                  */
1259                 if (AR_SREV_9271_10(ah)) {
1260                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1261                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1262                 }
1263                 else if (AR_SREV_9271_11(ah))
1264                         /*
1265                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1266                          * present on AR9271 1.1
1267                          */
1268                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1269                 return;
1270         }
1271
1272         /*
1273          * Set the RX_ABORT and RX_DIS and clear if off only after
1274          * RXE is set for MAC. This prevents frames with corrupted
1275          * descriptor status.
1276          */
1277         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1278
1279
1280         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1281             AR_SREV_9280_10_OR_LATER(ah))
1282                 return;
1283         /*
1284          * Disable BB clock gating
1285          * Necessary to avoid issues on AR5416 2.0
1286          */
1287         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1288 }
1289
1290 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1291                               struct ar5416_eeprom_def *pEepData,
1292                               u32 reg, u32 value)
1293 {
1294         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1295
1296         switch (ah->hw_version.devid) {
1297         case AR9280_DEVID_PCI:
1298                 if (reg == 0x7894) {
1299                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1300                                 "ini VAL: %x  EEPROM: %x\n", value,
1301                                 (pBase->version & 0xff));
1302
1303                         if ((pBase->version & 0xff) > 0x0a) {
1304                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1305                                         "PWDCLKIND: %d\n",
1306                                         pBase->pwdclkind);
1307                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1308                                 value |= AR_AN_TOP2_PWDCLKIND &
1309                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1310                         } else {
1311                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1312                                         "PWDCLKIND Earlier Rev\n");
1313                         }
1314
1315                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1316                                 "final ini VAL: %x\n", value);
1317                 }
1318                 break;
1319         }
1320
1321         return value;
1322 }
1323
1324 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1325                               struct ar5416_eeprom_def *pEepData,
1326                               u32 reg, u32 value)
1327 {
1328         if (ah->eep_map == EEP_MAP_4KBITS)
1329                 return value;
1330         else
1331                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1332 }
1333
1334 static void ath9k_olc_init(struct ath_hw *ah)
1335 {
1336         u32 i;
1337
1338         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1339                 ah->originalGain[i] =
1340                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1341                                         AR_PHY_TX_GAIN);
1342         ah->PDADCdelta = 0;
1343 }
1344
1345 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1346                               struct ath9k_channel *chan)
1347 {
1348         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1349
1350         if (IS_CHAN_B(chan))
1351                 ctl |= CTL_11B;
1352         else if (IS_CHAN_G(chan))
1353                 ctl |= CTL_11G;
1354         else
1355                 ctl |= CTL_11A;
1356
1357         return ctl;
1358 }
1359
1360 static int ath9k_hw_process_ini(struct ath_hw *ah,
1361                                 struct ath9k_channel *chan,
1362                                 enum ath9k_ht_macmode macmode)
1363 {
1364         int i, regWrites = 0;
1365         struct ieee80211_channel *channel = chan->chan;
1366         u32 modesIndex, freqIndex;
1367
1368         switch (chan->chanmode) {
1369         case CHANNEL_A:
1370         case CHANNEL_A_HT20:
1371                 modesIndex = 1;
1372                 freqIndex = 1;
1373                 break;
1374         case CHANNEL_A_HT40PLUS:
1375         case CHANNEL_A_HT40MINUS:
1376                 modesIndex = 2;
1377                 freqIndex = 1;
1378                 break;
1379         case CHANNEL_G:
1380         case CHANNEL_G_HT20:
1381         case CHANNEL_B:
1382                 modesIndex = 4;
1383                 freqIndex = 2;
1384                 break;
1385         case CHANNEL_G_HT40PLUS:
1386         case CHANNEL_G_HT40MINUS:
1387                 modesIndex = 3;
1388                 freqIndex = 2;
1389                 break;
1390
1391         default:
1392                 return -EINVAL;
1393         }
1394
1395         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1396         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1397         ah->eep_ops->set_addac(ah, chan);
1398
1399         if (AR_SREV_5416_22_OR_LATER(ah)) {
1400                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1401         } else {
1402                 struct ar5416IniArray temp;
1403                 u32 addacSize =
1404                         sizeof(u32) * ah->iniAddac.ia_rows *
1405                         ah->iniAddac.ia_columns;
1406
1407                 memcpy(ah->addac5416_21,
1408                        ah->iniAddac.ia_array, addacSize);
1409
1410                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1411
1412                 temp.ia_array = ah->addac5416_21;
1413                 temp.ia_columns = ah->iniAddac.ia_columns;
1414                 temp.ia_rows = ah->iniAddac.ia_rows;
1415                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1416         }
1417
1418         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1419
1420         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1421                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1422                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1423
1424                 REG_WRITE(ah, reg, val);
1425
1426                 if (reg >= 0x7800 && reg < 0x78a0
1427                     && ah->config.analog_shiftreg) {
1428                         udelay(100);
1429                 }
1430
1431                 DO_DELAY(regWrites);
1432         }
1433
1434         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1435                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1436
1437         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1438             AR_SREV_9287_10_OR_LATER(ah))
1439                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1440
1441         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1442                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1443                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1444
1445                 REG_WRITE(ah, reg, val);
1446
1447                 if (reg >= 0x7800 && reg < 0x78a0
1448                     && ah->config.analog_shiftreg) {
1449                         udelay(100);
1450                 }
1451
1452                 DO_DELAY(regWrites);
1453         }
1454
1455         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1456
1457         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1458                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1459                                 regWrites);
1460         }
1461
1462         ath9k_hw_override_ini(ah, chan);
1463         ath9k_hw_set_regs(ah, chan, macmode);
1464         ath9k_hw_init_chain_masks(ah);
1465
1466         if (OLC_FOR_AR9280_20_LATER)
1467                 ath9k_olc_init(ah);
1468
1469         ah->eep_ops->set_txpower(ah, chan,
1470                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1471                                  channel->max_antenna_gain * 2,
1472                                  channel->max_power * 2,
1473                                  min((u32) MAX_RATE_POWER,
1474                                  (u32) ah->regulatory.power_limit));
1475
1476         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1477                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1478                         "ar5416SetRfRegs failed\n");
1479                 return -EIO;
1480         }
1481
1482         return 0;
1483 }
1484
1485 /****************************************/
1486 /* Reset and Channel Switching Routines */
1487 /****************************************/
1488
1489 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1490 {
1491         u32 rfMode = 0;
1492
1493         if (chan == NULL)
1494                 return;
1495
1496         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1497                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1498
1499         if (!AR_SREV_9280_10_OR_LATER(ah))
1500                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1501                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1502
1503         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1504                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1505
1506         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1507 }
1508
1509 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1510 {
1511         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1512 }
1513
1514 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1515 {
1516         u32 regval;
1517
1518         /*
1519          * set AHB_MODE not to do cacheline prefetches
1520         */
1521         regval = REG_READ(ah, AR_AHB_MODE);
1522         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1523
1524         /*
1525          * let mac dma reads be in 128 byte chunks
1526          */
1527         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1528         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1529
1530         /*
1531          * Restore TX Trigger Level to its pre-reset value.
1532          * The initial value depends on whether aggregation is enabled, and is
1533          * adjusted whenever underruns are detected.
1534          */
1535         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1536
1537         /*
1538          * let mac dma writes be in 128 byte chunks
1539          */
1540         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1541         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1542
1543         /*
1544          * Setup receive FIFO threshold to hold off TX activities
1545          */
1546         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1547
1548         /*
1549          * reduce the number of usable entries in PCU TXBUF to avoid
1550          * wrap around issues.
1551          */
1552         if (AR_SREV_9285(ah)) {
1553                 /* For AR9285 the number of Fifos are reduced to half.
1554                  * So set the usable tx buf size also to half to
1555                  * avoid data/delimiter underruns
1556                  */
1557                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1558                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1559         } else if (!AR_SREV_9271(ah)) {
1560                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1561                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1562         }
1563 }
1564
1565 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1566 {
1567         u32 val;
1568
1569         val = REG_READ(ah, AR_STA_ID1);
1570         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1571         switch (opmode) {
1572         case NL80211_IFTYPE_AP:
1573                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1574                           | AR_STA_ID1_KSRCH_MODE);
1575                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1576                 break;
1577         case NL80211_IFTYPE_ADHOC:
1578         case NL80211_IFTYPE_MESH_POINT:
1579                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1580                           | AR_STA_ID1_KSRCH_MODE);
1581                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1582                 break;
1583         case NL80211_IFTYPE_STATION:
1584         case NL80211_IFTYPE_MONITOR:
1585                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1586                 break;
1587         }
1588 }
1589
1590 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1591                                                  u32 coef_scaled,
1592                                                  u32 *coef_mantissa,
1593                                                  u32 *coef_exponent)
1594 {
1595         u32 coef_exp, coef_man;
1596
1597         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1598                 if ((coef_scaled >> coef_exp) & 0x1)
1599                         break;
1600
1601         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1602
1603         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1604
1605         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1606         *coef_exponent = coef_exp - 16;
1607 }
1608
1609 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1610                                      struct ath9k_channel *chan)
1611 {
1612         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1613         u32 clockMhzScaled = 0x64000000;
1614         struct chan_centers centers;
1615
1616         if (IS_CHAN_HALF_RATE(chan))
1617                 clockMhzScaled = clockMhzScaled >> 1;
1618         else if (IS_CHAN_QUARTER_RATE(chan))
1619                 clockMhzScaled = clockMhzScaled >> 2;
1620
1621         ath9k_hw_get_channel_centers(ah, chan, &centers);
1622         coef_scaled = clockMhzScaled / centers.synth_center;
1623
1624         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1625                                       &ds_coef_exp);
1626
1627         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1628                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1629         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1630                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1631
1632         coef_scaled = (9 * coef_scaled) / 10;
1633
1634         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1635                                       &ds_coef_exp);
1636
1637         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1638                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1639         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1640                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1641 }
1642
1643 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1644 {
1645         u32 rst_flags;
1646         u32 tmpReg;
1647
1648         if (AR_SREV_9100(ah)) {
1649                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1650                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1651                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1652                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1653                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1654         }
1655
1656         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1657                   AR_RTC_FORCE_WAKE_ON_INT);
1658
1659         if (AR_SREV_9100(ah)) {
1660                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1661                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1662         } else {
1663                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1664                 if (tmpReg &
1665                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1666                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1667                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1668                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1669                 } else {
1670                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1671                 }
1672
1673                 rst_flags = AR_RTC_RC_MAC_WARM;
1674                 if (type == ATH9K_RESET_COLD)
1675                         rst_flags |= AR_RTC_RC_MAC_COLD;
1676         }
1677
1678         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1679         udelay(50);
1680
1681         REG_WRITE(ah, AR_RTC_RC, 0);
1682         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1683                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1684                         "RTC stuck in MAC reset\n");
1685                 return false;
1686         }
1687
1688         if (!AR_SREV_9100(ah))
1689                 REG_WRITE(ah, AR_RC, 0);
1690
1691         ath9k_hw_init_pll(ah, NULL);
1692
1693         if (AR_SREV_9100(ah))
1694                 udelay(50);
1695
1696         return true;
1697 }
1698
1699 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1700 {
1701         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1702                   AR_RTC_FORCE_WAKE_ON_INT);
1703
1704         REG_WRITE(ah, AR_RTC_RESET, 0);
1705         udelay(2);
1706         REG_WRITE(ah, AR_RTC_RESET, 1);
1707
1708         if (!ath9k_hw_wait(ah,
1709                            AR_RTC_STATUS,
1710                            AR_RTC_STATUS_M,
1711                            AR_RTC_STATUS_ON,
1712                            AH_WAIT_TIMEOUT)) {
1713                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1714                 return false;
1715         }
1716
1717         ath9k_hw_read_revisions(ah);
1718
1719         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1720 }
1721
1722 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1723 {
1724         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1725                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1726
1727         switch (type) {
1728         case ATH9K_RESET_POWER_ON:
1729                 return ath9k_hw_set_reset_power_on(ah);
1730         case ATH9K_RESET_WARM:
1731         case ATH9K_RESET_COLD:
1732                 return ath9k_hw_set_reset(ah, type);
1733         default:
1734                 return false;
1735         }
1736 }
1737
1738 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1739                               enum ath9k_ht_macmode macmode)
1740 {
1741         u32 phymode;
1742         u32 enableDacFifo = 0;
1743
1744         if (AR_SREV_9285_10_OR_LATER(ah))
1745                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1746                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1747
1748         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1749                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1750
1751         if (IS_CHAN_HT40(chan)) {
1752                 phymode |= AR_PHY_FC_DYN2040_EN;
1753
1754                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1755                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1756                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1757
1758                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1759                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1760         }
1761         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1762
1763         ath9k_hw_set11nmac2040(ah, macmode);
1764
1765         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1766         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1767 }
1768
1769 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1770                                 struct ath9k_channel *chan)
1771 {
1772         if (OLC_FOR_AR9280_20_LATER) {
1773                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1774                         return false;
1775         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1776                 return false;
1777
1778         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1779                 return false;
1780
1781         ah->chip_fullsleep = false;
1782         ath9k_hw_init_pll(ah, chan);
1783         ath9k_hw_set_rfmode(ah, chan);
1784
1785         return true;
1786 }
1787
1788 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1789                                     struct ath9k_channel *chan,
1790                                     enum ath9k_ht_macmode macmode)
1791 {
1792         struct ieee80211_channel *channel = chan->chan;
1793         u32 synthDelay, qnum;
1794
1795         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1796                 if (ath9k_hw_numtxpending(ah, qnum)) {
1797                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1798                                 "Transmit frames pending on queue %d\n", qnum);
1799                         return false;
1800                 }
1801         }
1802
1803         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1804         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1805                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1806                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1807                         "Could not kill baseband RX\n");
1808                 return false;
1809         }
1810
1811         ath9k_hw_set_regs(ah, chan, macmode);
1812
1813         if (AR_SREV_9280_10_OR_LATER(ah)) {
1814                 ath9k_hw_ar9280_set_channel(ah, chan);
1815         } else {
1816                 if (!(ath9k_hw_set_channel(ah, chan))) {
1817                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1818                                 "Failed to set channel\n");
1819                         return false;
1820                 }
1821         }
1822
1823         ah->eep_ops->set_txpower(ah, chan,
1824                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1825                              channel->max_antenna_gain * 2,
1826                              channel->max_power * 2,
1827                              min((u32) MAX_RATE_POWER,
1828                              (u32) ah->regulatory.power_limit));
1829
1830         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1831         if (IS_CHAN_B(chan))
1832                 synthDelay = (4 * synthDelay) / 22;
1833         else
1834                 synthDelay /= 10;
1835
1836         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1837
1838         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1839
1840         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1841                 ath9k_hw_set_delta_slope(ah, chan);
1842
1843         if (AR_SREV_9280_10_OR_LATER(ah))
1844                 ath9k_hw_9280_spur_mitigate(ah, chan);
1845         else
1846                 ath9k_hw_spur_mitigate(ah, chan);
1847
1848         if (!chan->oneTimeCalsDone)
1849                 chan->oneTimeCalsDone = true;
1850
1851         return true;
1852 }
1853
1854 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1855 {
1856         int bb_spur = AR_NO_SPUR;
1857         int freq;
1858         int bin, cur_bin;
1859         int bb_spur_off, spur_subchannel_sd;
1860         int spur_freq_sd;
1861         int spur_delta_phase;
1862         int denominator;
1863         int upper, lower, cur_vit_mask;
1864         int tmp, newVal;
1865         int i;
1866         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1867                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1868         };
1869         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1870                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1871         };
1872         int inc[4] = { 0, 100, 0, 0 };
1873         struct chan_centers centers;
1874
1875         int8_t mask_m[123];
1876         int8_t mask_p[123];
1877         int8_t mask_amt;
1878         int tmp_mask;
1879         int cur_bb_spur;
1880         bool is2GHz = IS_CHAN_2GHZ(chan);
1881
1882         memset(&mask_m, 0, sizeof(int8_t) * 123);
1883         memset(&mask_p, 0, sizeof(int8_t) * 123);
1884
1885         ath9k_hw_get_channel_centers(ah, chan, &centers);
1886         freq = centers.synth_center;
1887
1888         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1889         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1890                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1891
1892                 if (is2GHz)
1893                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1894                 else
1895                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1896
1897                 if (AR_NO_SPUR == cur_bb_spur)
1898                         break;
1899                 cur_bb_spur = cur_bb_spur - freq;
1900
1901                 if (IS_CHAN_HT40(chan)) {
1902                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1903                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1904                                 bb_spur = cur_bb_spur;
1905                                 break;
1906                         }
1907                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1908                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1909                         bb_spur = cur_bb_spur;
1910                         break;
1911                 }
1912         }
1913
1914         if (AR_NO_SPUR == bb_spur) {
1915                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1916                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1917                 return;
1918         } else {
1919                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1920                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1921         }
1922
1923         bin = bb_spur * 320;
1924
1925         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1926
1927         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1928                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1929                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1930                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1931         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1932
1933         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1934                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1935                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1936                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1937                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1938         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1939
1940         if (IS_CHAN_HT40(chan)) {
1941                 if (bb_spur < 0) {
1942                         spur_subchannel_sd = 1;
1943                         bb_spur_off = bb_spur + 10;
1944                 } else {
1945                         spur_subchannel_sd = 0;
1946                         bb_spur_off = bb_spur - 10;
1947                 }
1948         } else {
1949                 spur_subchannel_sd = 0;
1950                 bb_spur_off = bb_spur;
1951         }
1952
1953         if (IS_CHAN_HT40(chan))
1954                 spur_delta_phase =
1955                         ((bb_spur * 262144) /
1956                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1957         else
1958                 spur_delta_phase =
1959                         ((bb_spur * 524288) /
1960                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1961
1962         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1963         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1964
1965         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1966                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1967                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1968         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1969
1970         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1971         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1972
1973         cur_bin = -6000;
1974         upper = bin + 100;
1975         lower = bin - 100;
1976
1977         for (i = 0; i < 4; i++) {
1978                 int pilot_mask = 0;
1979                 int chan_mask = 0;
1980                 int bp = 0;
1981                 for (bp = 0; bp < 30; bp++) {
1982                         if ((cur_bin > lower) && (cur_bin < upper)) {
1983                                 pilot_mask = pilot_mask | 0x1 << bp;
1984                                 chan_mask = chan_mask | 0x1 << bp;
1985                         }
1986                         cur_bin += 100;
1987                 }
1988                 cur_bin += inc[i];
1989                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1990                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1991         }
1992
1993         cur_vit_mask = 6100;
1994         upper = bin + 120;
1995         lower = bin - 120;
1996
1997         for (i = 0; i < 123; i++) {
1998                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1999
2000                         /* workaround for gcc bug #37014 */
2001                         volatile int tmp_v = abs(cur_vit_mask - bin);
2002
2003                         if (tmp_v < 75)
2004                                 mask_amt = 1;
2005                         else
2006                                 mask_amt = 0;
2007                         if (cur_vit_mask < 0)
2008                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2009                         else
2010                                 mask_p[cur_vit_mask / 100] = mask_amt;
2011                 }
2012                 cur_vit_mask -= 100;
2013         }
2014
2015         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2016                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2017                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2018                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2019                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2020                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2021                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2022                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2023         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2024         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2025
2026         tmp_mask = (mask_m[31] << 28)
2027                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2028                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2029                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2030                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2031                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2032                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2033                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2034         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2035         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2036
2037         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2038                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2039                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2040                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2041                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2042                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2043                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2044                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2045         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2046         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2047
2048         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2049                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2050                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2051                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2052                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2053                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2054                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2055                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2056         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2057         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2058
2059         tmp_mask = (mask_p[15] << 28)
2060                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2061                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2062                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2063                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2064                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2065                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2066                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2067         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2068         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2069
2070         tmp_mask = (mask_p[30] << 28)
2071                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2072                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2073                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2074                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2075                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2076                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2077                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2078         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2079         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2080
2081         tmp_mask = (mask_p[45] << 28)
2082                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2083                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2084                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2085                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2086                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2087                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2088                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2089         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2090         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2091
2092         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2093                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2094                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2095                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2096                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2097                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2098                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2099                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2100         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2101         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2102 }
2103
2104 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2105 {
2106         int bb_spur = AR_NO_SPUR;
2107         int bin, cur_bin;
2108         int spur_freq_sd;
2109         int spur_delta_phase;
2110         int denominator;
2111         int upper, lower, cur_vit_mask;
2112         int tmp, new;
2113         int i;
2114         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2115                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2116         };
2117         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2118                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2119         };
2120         int inc[4] = { 0, 100, 0, 0 };
2121
2122         int8_t mask_m[123];
2123         int8_t mask_p[123];
2124         int8_t mask_amt;
2125         int tmp_mask;
2126         int cur_bb_spur;
2127         bool is2GHz = IS_CHAN_2GHZ(chan);
2128
2129         memset(&mask_m, 0, sizeof(int8_t) * 123);
2130         memset(&mask_p, 0, sizeof(int8_t) * 123);
2131
2132         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2133                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2134                 if (AR_NO_SPUR == cur_bb_spur)
2135                         break;
2136                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2137                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2138                         bb_spur = cur_bb_spur;
2139                         break;
2140                 }
2141         }
2142
2143         if (AR_NO_SPUR == bb_spur)
2144                 return;
2145
2146         bin = bb_spur * 32;
2147
2148         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2149         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2150                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2151                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2152                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2153
2154         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2155
2156         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2157                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2158                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2159                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2160                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2161         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2162
2163         spur_delta_phase = ((bb_spur * 524288) / 100) &
2164                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2165
2166         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2167         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2168
2169         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2170                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2171                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2172         REG_WRITE(ah, AR_PHY_TIMING11, new);
2173
2174         cur_bin = -6000;
2175         upper = bin + 100;
2176         lower = bin - 100;
2177
2178         for (i = 0; i < 4; i++) {
2179                 int pilot_mask = 0;
2180                 int chan_mask = 0;
2181                 int bp = 0;
2182                 for (bp = 0; bp < 30; bp++) {
2183                         if ((cur_bin > lower) && (cur_bin < upper)) {
2184                                 pilot_mask = pilot_mask | 0x1 << bp;
2185                                 chan_mask = chan_mask | 0x1 << bp;
2186                         }
2187                         cur_bin += 100;
2188                 }
2189                 cur_bin += inc[i];
2190                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2191                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2192         }
2193
2194         cur_vit_mask = 6100;
2195         upper = bin + 120;
2196         lower = bin - 120;
2197
2198         for (i = 0; i < 123; i++) {
2199                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2200
2201                         /* workaround for gcc bug #37014 */
2202                         volatile int tmp_v = abs(cur_vit_mask - bin);
2203
2204                         if (tmp_v < 75)
2205                                 mask_amt = 1;
2206                         else
2207                                 mask_amt = 0;
2208                         if (cur_vit_mask < 0)
2209                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2210                         else
2211                                 mask_p[cur_vit_mask / 100] = mask_amt;
2212                 }
2213                 cur_vit_mask -= 100;
2214         }
2215
2216         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2217                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2218                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2219                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2220                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2221                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2222                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2223                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2224         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2225         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2226
2227         tmp_mask = (mask_m[31] << 28)
2228                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2229                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2230                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2231                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2232                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2233                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2234                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2235         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2236         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2237
2238         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2239                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2240                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2241                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2242                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2243                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2244                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2245                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2246         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2247         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2248
2249         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2250                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2251                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2252                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2253                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2254                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2255                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2256                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2257         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2258         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2259
2260         tmp_mask = (mask_p[15] << 28)
2261                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2262                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2263                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2264                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2265                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2266                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2267                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2268         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2269         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2270
2271         tmp_mask = (mask_p[30] << 28)
2272                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2273                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2274                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2275                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2276                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2277                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2278                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2279         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2280         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2281
2282         tmp_mask = (mask_p[45] << 28)
2283                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2284                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2285                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2286                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2287                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2288                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2289                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2290         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2291         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2292
2293         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2294                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2295                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2296                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2297                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2298                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2299                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2300                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2301         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2302         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2303 }
2304
2305 static void ath9k_enable_rfkill(struct ath_hw *ah)
2306 {
2307         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2308                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2309
2310         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2311                     AR_GPIO_INPUT_MUX2_RFSILENT);
2312
2313         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2314         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2315 }
2316
2317 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2318                     bool bChannelChange)
2319 {
2320         u32 saveLedState;
2321         struct ath_softc *sc = ah->ah_sc;
2322         struct ath9k_channel *curchan = ah->curchan;
2323         u32 saveDefAntenna;
2324         u32 macStaId1;
2325         int i, rx_chainmask, r;
2326
2327         ah->extprotspacing = sc->ht_extprotspacing;
2328         ah->txchainmask = sc->tx_chainmask;
2329         ah->rxchainmask = sc->rx_chainmask;
2330
2331         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2332                 return -EIO;
2333
2334         if (curchan)
2335                 ath9k_hw_getnf(ah, curchan);
2336
2337         if (bChannelChange &&
2338             (ah->chip_fullsleep != true) &&
2339             (ah->curchan != NULL) &&
2340             (chan->channel != ah->curchan->channel) &&
2341             ((chan->channelFlags & CHANNEL_ALL) ==
2342              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2343             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2344                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2345
2346                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2347                         ath9k_hw_loadnf(ah, ah->curchan);
2348                         ath9k_hw_start_nfcal(ah);
2349                         return 0;
2350                 }
2351         }
2352
2353         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2354         if (saveDefAntenna == 0)
2355                 saveDefAntenna = 1;
2356
2357         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2358
2359         saveLedState = REG_READ(ah, AR_CFG_LED) &
2360                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2361                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2362
2363         ath9k_hw_mark_phy_inactive(ah);
2364
2365         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2366                 REG_WRITE(ah,
2367                           AR9271_RESET_POWER_DOWN_CONTROL,
2368                           AR9271_RADIO_RF_RST);
2369                 udelay(50);
2370         }
2371
2372         if (!ath9k_hw_chip_reset(ah, chan)) {
2373                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2374                 return -EINVAL;
2375         }
2376
2377         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2378                 ah->htc_reset_init = false;
2379                 REG_WRITE(ah,
2380                           AR9271_RESET_POWER_DOWN_CONTROL,
2381                           AR9271_GATE_MAC_CTL);
2382                 udelay(50);
2383         }
2384
2385         if (AR_SREV_9280_10_OR_LATER(ah))
2386                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2387
2388         if (AR_SREV_9287_10_OR_LATER(ah)) {
2389                 /* Enable ASYNC FIFO */
2390                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2391                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2392                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2393                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2394                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2395                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2396                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2397         }
2398         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2399         if (r)
2400                 return r;
2401
2402         /* Setup MFP options for CCMP */
2403         if (AR_SREV_9280_20_OR_LATER(ah)) {
2404                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2405                  * frames when constructing CCMP AAD. */
2406                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2407                               0xc7ff);
2408                 ah->sw_mgmt_crypto = false;
2409         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2410                 /* Disable hardware crypto for management frames */
2411                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2412                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2413                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2414                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2415                 ah->sw_mgmt_crypto = true;
2416         } else
2417                 ah->sw_mgmt_crypto = true;
2418
2419         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2420                 ath9k_hw_set_delta_slope(ah, chan);
2421
2422         if (AR_SREV_9280_10_OR_LATER(ah))
2423                 ath9k_hw_9280_spur_mitigate(ah, chan);
2424         else
2425                 ath9k_hw_spur_mitigate(ah, chan);
2426
2427         ah->eep_ops->set_board_values(ah, chan);
2428
2429         ath9k_hw_decrease_chain_power(ah, chan);
2430
2431         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2432         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2433                   | macStaId1
2434                   | AR_STA_ID1_RTS_USE_DEF
2435                   | (ah->config.
2436                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2437                   | ah->sta_id1_defaults);
2438         ath9k_hw_set_operating_mode(ah, ah->opmode);
2439
2440         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2441         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2442
2443         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2444
2445         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2446         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2447                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2448
2449         REG_WRITE(ah, AR_ISR, ~0);
2450
2451         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2452
2453         if (AR_SREV_9280_10_OR_LATER(ah))
2454                 ath9k_hw_ar9280_set_channel(ah, chan);
2455         else
2456                 if (!(ath9k_hw_set_channel(ah, chan)))
2457                         return -EIO;
2458
2459         for (i = 0; i < AR_NUM_DCU; i++)
2460                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2461
2462         ah->intr_txqs = 0;
2463         for (i = 0; i < ah->caps.total_queues; i++)
2464                 ath9k_hw_resettxqueue(ah, i);
2465
2466         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2467         ath9k_hw_init_qos(ah);
2468
2469         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2470                 ath9k_enable_rfkill(ah);
2471
2472         ath9k_hw_init_user_settings(ah);
2473
2474         if (AR_SREV_9287_10_OR_LATER(ah)) {
2475                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2476                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2477                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2478                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2479                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2480                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2481
2482                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2483                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2484
2485                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2486                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2487                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2488                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2489         }
2490         if (AR_SREV_9287_10_OR_LATER(ah)) {
2491                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2492                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2493         }
2494
2495         REG_WRITE(ah, AR_STA_ID1,
2496                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2497
2498         ath9k_hw_set_dma(ah);
2499
2500         REG_WRITE(ah, AR_OBS, 8);
2501
2502         if (ah->config.intr_mitigation) {
2503                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2504                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2505         }
2506
2507         ath9k_hw_init_bb(ah, chan);
2508
2509         if (!ath9k_hw_init_cal(ah, chan))
2510                 return -EIO;
2511
2512         rx_chainmask = ah->rxchainmask;
2513         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2514                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2515                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2516         }
2517
2518         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2519
2520         /*
2521          * For big endian systems turn on swapping for descriptors
2522          */
2523         if (AR_SREV_9100(ah)) {
2524                 u32 mask;
2525                 mask = REG_READ(ah, AR_CFG);
2526                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2527                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2528                                 "CFG Byte Swap Set 0x%x\n", mask);
2529                 } else {
2530                         mask =
2531                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2532                         REG_WRITE(ah, AR_CFG, mask);
2533                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2534                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2535                 }
2536         } else {
2537                 /* Configure AR9271 target WLAN */
2538                 if (AR_SREV_9271(ah))
2539                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2540 #ifdef __BIG_ENDIAN
2541                 else
2542                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2543 #endif
2544         }
2545
2546         return 0;
2547 }
2548
2549 /************************/
2550 /* Key Cache Management */
2551 /************************/
2552
2553 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2554 {
2555         u32 keyType;
2556
2557         if (entry >= ah->caps.keycache_size) {
2558                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2559                         "keychache entry %u out of range\n", entry);
2560                 return false;
2561         }
2562
2563         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2564
2565         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2566         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2567         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2568         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2569         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2570         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2571         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2572         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2573
2574         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2575                 u16 micentry = entry + 64;
2576
2577                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2578                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2579                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2580                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2581
2582         }
2583
2584         return true;
2585 }
2586
2587 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2588 {
2589         u32 macHi, macLo;
2590
2591         if (entry >= ah->caps.keycache_size) {
2592                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2593                         "keychache entry %u out of range\n", entry);
2594                 return false;
2595         }
2596
2597         if (mac != NULL) {
2598                 macHi = (mac[5] << 8) | mac[4];
2599                 macLo = (mac[3] << 24) |
2600                         (mac[2] << 16) |
2601                         (mac[1] << 8) |
2602                         mac[0];
2603                 macLo >>= 1;
2604                 macLo |= (macHi & 1) << 31;
2605                 macHi >>= 1;
2606         } else {
2607                 macLo = macHi = 0;
2608         }
2609         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2610         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2611
2612         return true;
2613 }
2614
2615 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2616                                  const struct ath9k_keyval *k,
2617                                  const u8 *mac)
2618 {
2619         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2620         u32 key0, key1, key2, key3, key4;
2621         u32 keyType;
2622
2623         if (entry >= pCap->keycache_size) {
2624                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2625                         "keycache entry %u out of range\n", entry);
2626                 return false;
2627         }
2628
2629         switch (k->kv_type) {
2630         case ATH9K_CIPHER_AES_OCB:
2631                 keyType = AR_KEYTABLE_TYPE_AES;
2632                 break;
2633         case ATH9K_CIPHER_AES_CCM:
2634                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2635                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2636                                 "AES-CCM not supported by mac rev 0x%x\n",
2637                                 ah->hw_version.macRev);
2638                         return false;
2639                 }
2640                 keyType = AR_KEYTABLE_TYPE_CCM;
2641                 break;
2642         case ATH9K_CIPHER_TKIP:
2643                 keyType = AR_KEYTABLE_TYPE_TKIP;
2644                 if (ATH9K_IS_MIC_ENABLED(ah)
2645                     && entry + 64 >= pCap->keycache_size) {
2646                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2647                                 "entry %u inappropriate for TKIP\n", entry);
2648                         return false;
2649                 }
2650                 break;
2651         case ATH9K_CIPHER_WEP:
2652                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2653                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2654                                 "WEP key length %u too small\n", k->kv_len);
2655                         return false;
2656                 }
2657                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2658                         keyType = AR_KEYTABLE_TYPE_40;
2659                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2660                         keyType = AR_KEYTABLE_TYPE_104;
2661                 else
2662                         keyType = AR_KEYTABLE_TYPE_128;
2663                 break;
2664         case ATH9K_CIPHER_CLR:
2665                 keyType = AR_KEYTABLE_TYPE_CLR;
2666                 break;
2667         default:
2668                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2669                         "cipher %u not supported\n", k->kv_type);
2670                 return false;
2671         }
2672
2673         key0 = get_unaligned_le32(k->kv_val + 0);
2674         key1 = get_unaligned_le16(k->kv_val + 4);
2675         key2 = get_unaligned_le32(k->kv_val + 6);
2676         key3 = get_unaligned_le16(k->kv_val + 10);
2677         key4 = get_unaligned_le32(k->kv_val + 12);
2678         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2679                 key4 &= 0xff;
2680
2681         /*
2682          * Note: Key cache registers access special memory area that requires
2683          * two 32-bit writes to actually update the values in the internal
2684          * memory. Consequently, the exact order and pairs used here must be
2685          * maintained.
2686          */
2687
2688         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2689                 u16 micentry = entry + 64;
2690
2691                 /*
2692                  * Write inverted key[47:0] first to avoid Michael MIC errors
2693                  * on frames that could be sent or received at the same time.
2694                  * The correct key will be written in the end once everything
2695                  * else is ready.
2696                  */
2697                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2698                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2699
2700                 /* Write key[95:48] */
2701                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2702                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2703
2704                 /* Write key[127:96] and key type */
2705                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2706                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2707
2708                 /* Write MAC address for the entry */
2709                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2710
2711                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2712                         /*
2713                          * TKIP uses two key cache entries:
2714                          * Michael MIC TX/RX keys in the same key cache entry
2715                          * (idx = main index + 64):
2716                          * key0 [31:0] = RX key [31:0]
2717                          * key1 [15:0] = TX key [31:16]
2718                          * key1 [31:16] = reserved
2719                          * key2 [31:0] = RX key [63:32]
2720                          * key3 [15:0] = TX key [15:0]
2721                          * key3 [31:16] = reserved
2722                          * key4 [31:0] = TX key [63:32]
2723                          */
2724                         u32 mic0, mic1, mic2, mic3, mic4;
2725
2726                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2727                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2728                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2729                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2730                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2731
2732                         /* Write RX[31:0] and TX[31:16] */
2733                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2734                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2735
2736                         /* Write RX[63:32] and TX[15:0] */
2737                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2738                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2739
2740                         /* Write TX[63:32] and keyType(reserved) */
2741                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2742                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2743                                   AR_KEYTABLE_TYPE_CLR);
2744
2745                 } else {
2746                         /*
2747                          * TKIP uses four key cache entries (two for group
2748                          * keys):
2749                          * Michael MIC TX/RX keys are in different key cache
2750                          * entries (idx = main index + 64 for TX and
2751                          * main index + 32 + 96 for RX):
2752                          * key0 [31:0] = TX/RX MIC key [31:0]
2753                          * key1 [31:0] = reserved
2754                          * key2 [31:0] = TX/RX MIC key [63:32]
2755                          * key3 [31:0] = reserved
2756                          * key4 [31:0] = reserved
2757                          *
2758                          * Upper layer code will call this function separately
2759                          * for TX and RX keys when these registers offsets are
2760                          * used.
2761                          */
2762                         u32 mic0, mic2;
2763
2764                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2765                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2766
2767                         /* Write MIC key[31:0] */
2768                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2769                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2770
2771                         /* Write MIC key[63:32] */
2772                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2773                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2774
2775                         /* Write TX[63:32] and keyType(reserved) */
2776                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2777                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2778                                   AR_KEYTABLE_TYPE_CLR);
2779                 }
2780
2781                 /* MAC address registers are reserved for the MIC entry */
2782                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2783                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2784
2785                 /*
2786                  * Write the correct (un-inverted) key[47:0] last to enable
2787                  * TKIP now that all other registers are set with correct
2788                  * values.
2789                  */
2790                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2791                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2792         } else {
2793                 /* Write key[47:0] */
2794                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2795                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2796
2797                 /* Write key[95:48] */
2798                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2799                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2800
2801                 /* Write key[127:96] and key type */
2802                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2803                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2804
2805                 /* Write MAC address for the entry */
2806                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2807         }
2808
2809         return true;
2810 }
2811
2812 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2813 {
2814         if (entry < ah->caps.keycache_size) {
2815                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2816                 if (val & AR_KEYTABLE_VALID)
2817                         return true;
2818         }
2819         return false;
2820 }
2821
2822 /******************************/
2823 /* Power Management (Chipset) */
2824 /******************************/
2825
2826 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2827 {
2828         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2829         if (setChip) {
2830                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2831                             AR_RTC_FORCE_WAKE_EN);
2832                 if (!AR_SREV_9100(ah))
2833                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2834
2835                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2836                             AR_RTC_RESET_EN);
2837         }
2838 }
2839
2840 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2841 {
2842         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2843         if (setChip) {
2844                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2845
2846                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2847                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2848                                   AR_RTC_FORCE_WAKE_ON_INT);
2849                 } else {
2850                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2851                                     AR_RTC_FORCE_WAKE_EN);
2852                 }
2853         }
2854 }
2855
2856 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2857 {
2858         u32 val;
2859         int i;
2860
2861         if (setChip) {
2862                 if ((REG_READ(ah, AR_RTC_STATUS) &
2863                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2864                         if (ath9k_hw_set_reset_reg(ah,
2865                                            ATH9K_RESET_POWER_ON) != true) {
2866                                 return false;
2867                         }
2868                 }
2869                 if (AR_SREV_9100(ah))
2870                         REG_SET_BIT(ah, AR_RTC_RESET,
2871                                     AR_RTC_RESET_EN);
2872
2873                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2874                             AR_RTC_FORCE_WAKE_EN);
2875                 udelay(50);
2876
2877                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2878                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2879                         if (val == AR_RTC_STATUS_ON)
2880                                 break;
2881                         udelay(50);
2882                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2883                                     AR_RTC_FORCE_WAKE_EN);
2884                 }
2885                 if (i == 0) {
2886                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2887                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2888                         return false;
2889                 }
2890         }
2891
2892         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2893
2894         return true;
2895 }
2896
2897 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2898                                      enum ath9k_power_mode mode)
2899 {
2900         int status = true, setChip = true;
2901         static const char *modes[] = {
2902                 "AWAKE",
2903                 "FULL-SLEEP",
2904                 "NETWORK SLEEP",
2905                 "UNDEFINED"
2906         };
2907
2908         if (ah->power_mode == mode)
2909                 return status;
2910
2911         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2912                 modes[ah->power_mode], modes[mode]);
2913
2914         switch (mode) {
2915         case ATH9K_PM_AWAKE:
2916                 status = ath9k_hw_set_power_awake(ah, setChip);
2917                 break;
2918         case ATH9K_PM_FULL_SLEEP:
2919                 ath9k_set_power_sleep(ah, setChip);
2920                 ah->chip_fullsleep = true;
2921                 break;
2922         case ATH9K_PM_NETWORK_SLEEP:
2923                 ath9k_set_power_network_sleep(ah, setChip);
2924                 break;
2925         default:
2926                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2927                         "Unknown power mode %u\n", mode);
2928                 return false;
2929         }
2930         ah->power_mode = mode;
2931
2932         return status;
2933 }
2934
2935 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2936 {
2937         unsigned long flags;
2938         bool ret;
2939
2940         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2941         ret = ath9k_hw_setpower_nolock(ah, mode);
2942         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2943
2944         return ret;
2945 }
2946
2947 void ath9k_ps_wakeup(struct ath_softc *sc)
2948 {
2949         unsigned long flags;
2950
2951         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2952         if (++sc->ps_usecount != 1)
2953                 goto unlock;
2954
2955         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2956
2957  unlock:
2958         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2959 }
2960
2961 void ath9k_ps_restore(struct ath_softc *sc)
2962 {
2963         unsigned long flags;
2964
2965         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2966         if (--sc->ps_usecount != 0)
2967                 goto unlock;
2968
2969         if (sc->ps_enabled &&
2970             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2971                               SC_OP_WAIT_FOR_CAB |
2972                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2973                               SC_OP_WAIT_FOR_TX_ACK)))
2974                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2975
2976  unlock:
2977         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2978 }
2979
2980 /*
2981  * Helper for ASPM support.
2982  *
2983  * Disable PLL when in L0s as well as receiver clock when in L1.
2984  * This power saving option must be enabled through the SerDes.
2985  *
2986  * Programming the SerDes must go through the same 288 bit serial shift
2987  * register as the other analog registers.  Hence the 9 writes.
2988  */
2989 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2990 {
2991         u8 i;
2992
2993         if (ah->is_pciexpress != true)
2994                 return;
2995
2996         /* Do not touch SerDes registers */
2997         if (ah->config.pcie_powersave_enable == 2)
2998                 return;
2999
3000         /* Nothing to do on restore for 11N */
3001         if (restore)
3002                 return;
3003
3004         if (AR_SREV_9280_20_OR_LATER(ah)) {
3005                 /*
3006                  * AR9280 2.0 or later chips use SerDes values from the
3007                  * initvals.h initialized depending on chipset during
3008                  * ath9k_hw_init()
3009                  */
3010                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3011                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3012                                   INI_RA(&ah->iniPcieSerdes, i, 1));
3013                 }
3014         } else if (AR_SREV_9280(ah) &&
3015                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3016                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3017                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3018
3019                 /* RX shut off when elecidle is asserted */
3020                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3021                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3022                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3023
3024                 /* Shut off CLKREQ active in L1 */
3025                 if (ah->config.pcie_clock_req)
3026                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3027                 else
3028                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3029
3030                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3031                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3032                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3033
3034                 /* Load the new settings */
3035                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3036
3037         } else {
3038                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3039                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3040
3041                 /* RX shut off when elecidle is asserted */
3042                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3043                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3044                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3045
3046                 /*
3047                  * Ignore ah->ah_config.pcie_clock_req setting for
3048                  * pre-AR9280 11n
3049                  */
3050                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3051
3052                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3053                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3054                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3055
3056                 /* Load the new settings */
3057                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3058         }
3059
3060         udelay(1000);
3061
3062         /* set bit 19 to allow forcing of pcie core into L1 state */
3063         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3064
3065         /* Several PCIe massages to ensure proper behaviour */
3066         if (ah->config.pcie_waen) {
3067                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
3068         } else {
3069                 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3070                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
3071                 /*
3072                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
3073                  * otherwise card may disappear.
3074                  */
3075                 else if (AR_SREV_9280(ah))
3076                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3077                 else
3078                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3079         }
3080 }
3081
3082 /**********************/
3083 /* Interrupt Handling */
3084 /**********************/
3085
3086 bool ath9k_hw_intrpend(struct ath_hw *ah)
3087 {
3088         u32 host_isr;
3089
3090         if (AR_SREV_9100(ah))
3091                 return true;
3092
3093         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3094         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3095                 return true;
3096
3097         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3098         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3099             && (host_isr != AR_INTR_SPURIOUS))
3100                 return true;
3101
3102         return false;
3103 }
3104
3105 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3106 {
3107         u32 isr = 0;
3108         u32 mask2 = 0;
3109         struct ath9k_hw_capabilities *pCap = &ah->caps;
3110         u32 sync_cause = 0;
3111         bool fatal_int = false;
3112
3113         if (!AR_SREV_9100(ah)) {
3114                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3115                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3116                             == AR_RTC_STATUS_ON) {
3117                                 isr = REG_READ(ah, AR_ISR);
3118                         }
3119                 }
3120
3121                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3122                         AR_INTR_SYNC_DEFAULT;
3123
3124                 *masked = 0;
3125
3126                 if (!isr && !sync_cause)
3127                         return false;
3128         } else {
3129                 *masked = 0;
3130                 isr = REG_READ(ah, AR_ISR);
3131         }
3132
3133         if (isr) {
3134                 if (isr & AR_ISR_BCNMISC) {
3135                         u32 isr2;
3136                         isr2 = REG_READ(ah, AR_ISR_S2);
3137                         if (isr2 & AR_ISR_S2_TIM)
3138                                 mask2 |= ATH9K_INT_TIM;
3139                         if (isr2 & AR_ISR_S2_DTIM)
3140                                 mask2 |= ATH9K_INT_DTIM;
3141                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3142                                 mask2 |= ATH9K_INT_DTIMSYNC;
3143                         if (isr2 & (AR_ISR_S2_CABEND))
3144                                 mask2 |= ATH9K_INT_CABEND;
3145                         if (isr2 & AR_ISR_S2_GTT)
3146                                 mask2 |= ATH9K_INT_GTT;
3147                         if (isr2 & AR_ISR_S2_CST)
3148                                 mask2 |= ATH9K_INT_CST;
3149                         if (isr2 & AR_ISR_S2_TSFOOR)
3150                                 mask2 |= ATH9K_INT_TSFOOR;
3151                 }
3152
3153                 isr = REG_READ(ah, AR_ISR_RAC);
3154                 if (isr == 0xffffffff) {
3155                         *masked = 0;
3156                         return false;
3157                 }
3158
3159                 *masked = isr & ATH9K_INT_COMMON;
3160
3161                 if (ah->config.intr_mitigation) {
3162                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3163                                 *masked |= ATH9K_INT_RX;
3164                 }
3165
3166                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3167                         *masked |= ATH9K_INT_RX;
3168                 if (isr &
3169                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3170                      AR_ISR_TXEOL)) {
3171                         u32 s0_s, s1_s;
3172
3173                         *masked |= ATH9K_INT_TX;
3174
3175                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3176                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3177                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3178
3179                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3180                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3181                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3182                 }
3183
3184                 if (isr & AR_ISR_RXORN) {
3185                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3186                                 "receive FIFO overrun interrupt\n");
3187                 }
3188
3189                 if (!AR_SREV_9100(ah)) {
3190                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3191                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3192                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3193                                         *masked |= ATH9K_INT_TIM_TIMER;
3194                         }
3195                 }
3196
3197                 *masked |= mask2;
3198         }
3199
3200         if (AR_SREV_9100(ah))
3201                 return true;
3202
3203         if (sync_cause) {
3204                 fatal_int =
3205                         (sync_cause &
3206                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3207                         ? true : false;
3208
3209                 if (fatal_int) {
3210                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3211                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3212                                         "received PCI FATAL interrupt\n");
3213                         }
3214                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3215                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3216                                         "received PCI PERR interrupt\n");
3217                         }
3218                         *masked |= ATH9K_INT_FATAL;
3219                 }
3220                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3221                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3222                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3223                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3224                         REG_WRITE(ah, AR_RC, 0);
3225                         *masked |= ATH9K_INT_FATAL;
3226                 }
3227                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3228                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3229                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3230                 }
3231
3232                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3233                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3234         }
3235
3236         return true;
3237 }
3238
3239 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3240 {
3241         u32 omask = ah->mask_reg;
3242         u32 mask, mask2;
3243         struct ath9k_hw_capabilities *pCap = &ah->caps;
3244
3245         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3246
3247         if (omask & ATH9K_INT_GLOBAL) {
3248                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3249                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3250                 (void) REG_READ(ah, AR_IER);
3251                 if (!AR_SREV_9100(ah)) {
3252                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3253                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3254
3255                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3256                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3257                 }
3258         }
3259
3260         mask = ints & ATH9K_INT_COMMON;
3261         mask2 = 0;
3262
3263         if (ints & ATH9K_INT_TX) {
3264                 if (ah->txok_interrupt_mask)
3265                         mask |= AR_IMR_TXOK;
3266                 if (ah->txdesc_interrupt_mask)
3267                         mask |= AR_IMR_TXDESC;
3268                 if (ah->txerr_interrupt_mask)
3269                         mask |= AR_IMR_TXERR;
3270                 if (ah->txeol_interrupt_mask)
3271                         mask |= AR_IMR_TXEOL;
3272         }
3273         if (ints & ATH9K_INT_RX) {
3274                 mask |= AR_IMR_RXERR;
3275                 if (ah->config.intr_mitigation)
3276                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3277                 else
3278                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3279                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3280                         mask |= AR_IMR_GENTMR;
3281         }
3282
3283         if (ints & (ATH9K_INT_BMISC)) {
3284                 mask |= AR_IMR_BCNMISC;
3285                 if (ints & ATH9K_INT_TIM)
3286                         mask2 |= AR_IMR_S2_TIM;
3287                 if (ints & ATH9K_INT_DTIM)
3288                         mask2 |= AR_IMR_S2_DTIM;
3289                 if (ints & ATH9K_INT_DTIMSYNC)
3290                         mask2 |= AR_IMR_S2_DTIMSYNC;
3291                 if (ints & ATH9K_INT_CABEND)
3292                         mask2 |= AR_IMR_S2_CABEND;
3293                 if (ints & ATH9K_INT_TSFOOR)
3294                         mask2 |= AR_IMR_S2_TSFOOR;
3295         }
3296
3297         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3298                 mask |= AR_IMR_BCNMISC;
3299                 if (ints & ATH9K_INT_GTT)
3300                         mask2 |= AR_IMR_S2_GTT;
3301                 if (ints & ATH9K_INT_CST)
3302                         mask2 |= AR_IMR_S2_CST;
3303         }
3304
3305         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3306         REG_WRITE(ah, AR_IMR, mask);
3307         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3308                                            AR_IMR_S2_DTIM |
3309                                            AR_IMR_S2_DTIMSYNC |
3310                                            AR_IMR_S2_CABEND |
3311                                            AR_IMR_S2_CABTO |
3312                                            AR_IMR_S2_TSFOOR |
3313                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3314         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3315         ah->mask_reg = ints;
3316
3317         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3318                 if (ints & ATH9K_INT_TIM_TIMER)
3319                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3320                 else
3321                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3322         }
3323
3324         if (ints & ATH9K_INT_GLOBAL) {
3325                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3326                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3327                 if (!AR_SREV_9100(ah)) {
3328                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3329                                   AR_INTR_MAC_IRQ);
3330                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3331
3332
3333                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3334                                   AR_INTR_SYNC_DEFAULT);
3335                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3336                                   AR_INTR_SYNC_DEFAULT);
3337                 }
3338                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3339                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3340         }
3341
3342         return omask;
3343 }
3344
3345 /*******************/
3346 /* Beacon Handling */
3347 /*******************/
3348
3349 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3350 {
3351         int flags = 0;
3352
3353         ah->beacon_interval = beacon_period;
3354
3355         switch (ah->opmode) {
3356         case NL80211_IFTYPE_STATION:
3357         case NL80211_IFTYPE_MONITOR:
3358                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3359                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3360                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3361                 flags |= AR_TBTT_TIMER_EN;
3362                 break;
3363         case NL80211_IFTYPE_ADHOC:
3364         case NL80211_IFTYPE_MESH_POINT:
3365                 REG_SET_BIT(ah, AR_TXCFG,
3366                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3367                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3368                           TU_TO_USEC(next_beacon +
3369                                      (ah->atim_window ? ah->
3370                                       atim_window : 1)));
3371                 flags |= AR_NDP_TIMER_EN;
3372         case NL80211_IFTYPE_AP:
3373                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3374                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3375                           TU_TO_USEC(next_beacon -
3376                                      ah->config.
3377                                      dma_beacon_response_time));
3378                 REG_WRITE(ah, AR_NEXT_SWBA,
3379                           TU_TO_USEC(next_beacon -
3380                                      ah->config.
3381                                      sw_beacon_response_time));
3382                 flags |=
3383                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3384                 break;
3385         default:
3386                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3387                         "%s: unsupported opmode: %d\n",
3388                         __func__, ah->opmode);
3389                 return;
3390                 break;
3391         }
3392
3393         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3394         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3395         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3396         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3397
3398         beacon_period &= ~ATH9K_BEACON_ENA;
3399         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3400                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3401                 ath9k_hw_reset_tsf(ah);
3402         }
3403
3404         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3405 }
3406
3407 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3408                                     const struct ath9k_beacon_state *bs)
3409 {
3410         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3411         struct ath9k_hw_capabilities *pCap = &ah->caps;
3412
3413         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3414
3415         REG_WRITE(ah, AR_BEACON_PERIOD,
3416                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3417         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3418                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3419
3420         REG_RMW_FIELD(ah, AR_RSSI_THR,
3421                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3422
3423         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3424
3425         if (bs->bs_sleepduration > beaconintval)
3426                 beaconintval = bs->bs_sleepduration;
3427
3428         dtimperiod = bs->bs_dtimperiod;
3429         if (bs->bs_sleepduration > dtimperiod)
3430                 dtimperiod = bs->bs_sleepduration;
3431
3432         if (beaconintval == dtimperiod)
3433                 nextTbtt = bs->bs_nextdtim;
3434         else
3435                 nextTbtt = bs->bs_nexttbtt;
3436
3437         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3438         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3439         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3440         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3441
3442         REG_WRITE(ah, AR_NEXT_DTIM,
3443                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3444         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3445
3446         REG_WRITE(ah, AR_SLEEP1,
3447                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3448                   | AR_SLEEP1_ASSUME_DTIM);
3449
3450         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3451                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3452         else
3453                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3454
3455         REG_WRITE(ah, AR_SLEEP2,
3456                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3457
3458         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3459         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3460
3461         REG_SET_BIT(ah, AR_TIMER_MODE,
3462                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3463                     AR_DTIM_TIMER_EN);
3464
3465         /* TSF Out of Range Threshold */
3466         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3467 }
3468
3469 /*******************/
3470 /* HW Capabilities */
3471 /*******************/
3472
3473 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3474 {
3475         struct ath9k_hw_capabilities *pCap = &ah->caps;
3476         u16 capField = 0, eeval;
3477
3478         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3479         ah->regulatory.current_rd = eeval;
3480
3481         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3482         if (AR_SREV_9285_10_OR_LATER(ah))
3483                 eeval |= AR9285_RDEXT_DEFAULT;
3484         ah->regulatory.current_rd_ext = eeval;
3485
3486         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3487
3488         if (ah->opmode != NL80211_IFTYPE_AP &&
3489             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3490                 if (ah->regulatory.current_rd == 0x64 ||
3491                     ah->regulatory.current_rd == 0x65)
3492                         ah->regulatory.current_rd += 5;
3493                 else if (ah->regulatory.current_rd == 0x41)
3494                         ah->regulatory.current_rd = 0x43;
3495                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3496                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3497         }
3498
3499         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3500         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3501
3502         if (eeval & AR5416_OPFLAGS_11A) {
3503                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3504                 if (ah->config.ht_enable) {
3505                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3506                                 set_bit(ATH9K_MODE_11NA_HT20,
3507                                         pCap->wireless_modes);
3508                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3509                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3510                                         pCap->wireless_modes);
3511                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3512                                         pCap->wireless_modes);
3513                         }
3514                 }
3515         }
3516
3517         if (eeval & AR5416_OPFLAGS_11G) {
3518                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3519                 if (ah->config.ht_enable) {
3520                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3521                                 set_bit(ATH9K_MODE_11NG_HT20,
3522                                         pCap->wireless_modes);
3523                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3524                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3525                                         pCap->wireless_modes);
3526                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3527                                         pCap->wireless_modes);
3528                         }
3529                 }
3530         }
3531
3532         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3533         /*
3534          * For AR9271 we will temporarilly uses the rx chainmax as read from
3535          * the EEPROM.
3536          */
3537         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3538             !(eeval & AR5416_OPFLAGS_11A) &&
3539             !(AR_SREV_9271(ah)))
3540                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3541                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3542         else
3543                 /* Use rx_chainmask from EEPROM. */
3544                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3545
3546         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3547                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3548
3549         pCap->low_2ghz_chan = 2312;
3550         pCap->high_2ghz_chan = 2732;
3551
3552         pCap->low_5ghz_chan = 4920;
3553         pCap->high_5ghz_chan = 6100;
3554
3555         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3556         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3557         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3558
3559         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3560         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3561         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3562
3563         if (ah->config.ht_enable)
3564                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3565         else
3566                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3567
3568         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3569         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3570         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3571         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3572
3573         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3574                 pCap->total_queues =
3575                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3576         else
3577                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3578
3579         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3580                 pCap->keycache_size =
3581                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3582         else
3583                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3584
3585         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3586         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3587
3588         if (AR_SREV_9285_10_OR_LATER(ah))
3589                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3590         else if (AR_SREV_9280_10_OR_LATER(ah))
3591                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3592         else
3593                 pCap->num_gpio_pins = AR_NUM_GPIO;
3594
3595         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3596                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3597                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3598         } else {
3599                 pCap->rts_aggr_limit = (8 * 1024);
3600         }
3601
3602         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3603
3604 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3605         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3606         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3607                 ah->rfkill_gpio =
3608                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3609                 ah->rfkill_polarity =
3610                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3611
3612                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3613         }
3614 #endif
3615
3616         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3617             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3618             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3619             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3620             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3621             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3622                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3623         else
3624                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3625
3626         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3627                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3628         else
3629                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3630
3631         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3632                 pCap->reg_cap =
3633                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3634                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3635                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3636                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3637         } else {
3638                 pCap->reg_cap =
3639                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3640                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3641         }
3642
3643         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3644
3645         pCap->num_antcfg_5ghz =
3646                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3647         pCap->num_antcfg_2ghz =
3648                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3649
3650         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3651                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3652                 ah->btactive_gpio = 6;
3653                 ah->wlanactive_gpio = 5;
3654         }
3655 }
3656
3657 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3658                             u32 capability, u32 *result)
3659 {
3660         switch (type) {
3661         case ATH9K_CAP_CIPHER:
3662                 switch (capability) {
3663                 case ATH9K_CIPHER_AES_CCM:
3664                 case ATH9K_CIPHER_AES_OCB:
3665                 case ATH9K_CIPHER_TKIP:
3666                 case ATH9K_CIPHER_WEP:
3667                 case ATH9K_CIPHER_MIC:
3668                 case ATH9K_CIPHER_CLR:
3669                         return true;
3670                 default:
3671                         return false;
3672                 }
3673         case ATH9K_CAP_TKIP_MIC:
3674                 switch (capability) {
3675                 case 0:
3676                         return true;
3677                 case 1:
3678                         return (ah->sta_id1_defaults &
3679                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3680                         false;
3681                 }
3682         case ATH9K_CAP_TKIP_SPLIT:
3683                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3684                         false : true;
3685         case ATH9K_CAP_DIVERSITY:
3686                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3687                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3688                         true : false;
3689         case ATH9K_CAP_MCAST_KEYSRCH:
3690                 switch (capability) {
3691                 case 0:
3692                         return true;
3693                 case 1:
3694                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3695                                 return false;
3696                         } else {
3697                                 return (ah->sta_id1_defaults &
3698                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3699                                         false;
3700                         }
3701                 }
3702                 return false;
3703         case ATH9K_CAP_TXPOW:
3704                 switch (capability) {
3705                 case 0:
3706                         return 0;
3707                 case 1:
3708                         *result = ah->regulatory.power_limit;
3709                         return 0;
3710                 case 2:
3711                         *result = ah->regulatory.max_power_level;
3712                         return 0;
3713                 case 3:
3714                         *result = ah->regulatory.tp_scale;
3715                         return 0;
3716                 }
3717                 return false;
3718         case ATH9K_CAP_DS:
3719                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3720                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3721                         ? false : true;
3722         default:
3723                 return false;
3724         }
3725 }
3726
3727 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3728                             u32 capability, u32 setting, int *status)
3729 {
3730         u32 v;
3731
3732         switch (type) {
3733         case ATH9K_CAP_TKIP_MIC:
3734                 if (setting)
3735                         ah->sta_id1_defaults |=
3736                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3737                 else
3738                         ah->sta_id1_defaults &=
3739                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3740                 return true;
3741         case ATH9K_CAP_DIVERSITY:
3742                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3743                 if (setting)
3744                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3745                 else
3746                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3747                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3748                 return true;
3749         case ATH9K_CAP_MCAST_KEYSRCH:
3750                 if (setting)
3751                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3752                 else
3753                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3754                 return true;
3755         default:
3756                 return false;
3757         }
3758 }
3759
3760 /****************************/
3761 /* GPIO / RFKILL / Antennae */
3762 /****************************/
3763
3764 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3765                                          u32 gpio, u32 type)
3766 {
3767         int addr;
3768         u32 gpio_shift, tmp;
3769
3770         if (gpio > 11)
3771                 addr = AR_GPIO_OUTPUT_MUX3;
3772         else if (gpio > 5)
3773                 addr = AR_GPIO_OUTPUT_MUX2;
3774         else
3775                 addr = AR_GPIO_OUTPUT_MUX1;
3776
3777         gpio_shift = (gpio % 6) * 5;
3778
3779         if (AR_SREV_9280_20_OR_LATER(ah)
3780             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3781                 REG_RMW(ah, addr, (type << gpio_shift),
3782                         (0x1f << gpio_shift));
3783         } else {
3784                 tmp = REG_READ(ah, addr);
3785                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3786                 tmp &= ~(0x1f << gpio_shift);
3787                 tmp |= (type << gpio_shift);
3788                 REG_WRITE(ah, addr, tmp);
3789         }
3790 }
3791
3792 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3793 {
3794         u32 gpio_shift;
3795
3796         ASSERT(gpio < ah->caps.num_gpio_pins);
3797
3798         gpio_shift = gpio << 1;
3799
3800         REG_RMW(ah,
3801                 AR_GPIO_OE_OUT,
3802                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3803                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3804 }
3805
3806 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3807 {
3808 #define MS_REG_READ(x, y) \
3809         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3810
3811         if (gpio >= ah->caps.num_gpio_pins)
3812                 return 0xffffffff;
3813
3814         if (AR_SREV_9287_10_OR_LATER(ah))
3815                 return MS_REG_READ(AR9287, gpio) != 0;
3816         else if (AR_SREV_9285_10_OR_LATER(ah))
3817                 return MS_REG_READ(AR9285, gpio) != 0;
3818         else if (AR_SREV_9280_10_OR_LATER(ah))
3819                 return MS_REG_READ(AR928X, gpio) != 0;
3820         else
3821                 return MS_REG_READ(AR, gpio) != 0;
3822 }
3823
3824 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3825                          u32 ah_signal_type)
3826 {
3827         u32 gpio_shift;
3828
3829         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3830
3831         gpio_shift = 2 * gpio;
3832
3833         REG_RMW(ah,
3834                 AR_GPIO_OE_OUT,
3835                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3836                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3837 }
3838
3839 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3840 {
3841         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3842                 AR_GPIO_BIT(gpio));
3843 }
3844
3845 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3846 {
3847         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3848 }
3849
3850 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3851 {
3852         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3853 }
3854
3855 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3856                                enum ath9k_ant_setting settings,
3857                                struct ath9k_channel *chan,
3858                                u8 *tx_chainmask,
3859                                u8 *rx_chainmask,
3860                                u8 *antenna_cfgd)
3861 {
3862         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3863
3864         if (AR_SREV_9280(ah)) {
3865                 if (!tx_chainmask_cfg) {
3866
3867                         tx_chainmask_cfg = *tx_chainmask;
3868                         rx_chainmask_cfg = *rx_chainmask;
3869                 }
3870
3871                 switch (settings) {
3872                 case ATH9K_ANT_FIXED_A:
3873                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3874                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3875                         *antenna_cfgd = true;
3876                         break;
3877                 case ATH9K_ANT_FIXED_B:
3878                         if (ah->caps.tx_chainmask >
3879                             ATH9K_ANTENNA1_CHAINMASK) {
3880                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3881                         }
3882                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3883                         *antenna_cfgd = true;
3884                         break;
3885                 case ATH9K_ANT_VARIABLE:
3886                         *tx_chainmask = tx_chainmask_cfg;
3887                         *rx_chainmask = rx_chainmask_cfg;
3888                         *antenna_cfgd = true;
3889                         break;
3890                 default:
3891                         break;
3892                 }
3893         } else {
3894                 ah->diversity_control = settings;
3895         }
3896
3897         return true;
3898 }
3899
3900 /*********************/
3901 /* General Operation */
3902 /*********************/
3903
3904 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3905 {
3906         u32 bits = REG_READ(ah, AR_RX_FILTER);
3907         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3908
3909         if (phybits & AR_PHY_ERR_RADAR)
3910                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3911         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3912                 bits |= ATH9K_RX_FILTER_PHYERR;
3913
3914         return bits;
3915 }
3916
3917 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3918 {
3919         u32 phybits;
3920
3921         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3922         phybits = 0;
3923         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3924                 phybits |= AR_PHY_ERR_RADAR;
3925         if (bits & ATH9K_RX_FILTER_PHYERR)
3926                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3927         REG_WRITE(ah, AR_PHY_ERR, phybits);
3928
3929         if (phybits)
3930                 REG_WRITE(ah, AR_RXCFG,
3931                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3932         else
3933                 REG_WRITE(ah, AR_RXCFG,
3934                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3935 }
3936
3937 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3938 {
3939         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3940 }
3941
3942 bool ath9k_hw_disable(struct ath_hw *ah)
3943 {
3944         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3945                 return false;
3946
3947         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3948 }
3949
3950 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3951 {
3952         struct ath9k_channel *chan = ah->curchan;
3953         struct ieee80211_channel *channel = chan->chan;
3954
3955         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3956
3957         ah->eep_ops->set_txpower(ah, chan,
3958                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3959                                  channel->max_antenna_gain * 2,
3960                                  channel->max_power * 2,
3961                                  min((u32) MAX_RATE_POWER,
3962                                  (u32) ah->regulatory.power_limit));
3963 }
3964
3965 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3966 {
3967         memcpy(ah->macaddr, mac, ETH_ALEN);
3968 }
3969
3970 void ath9k_hw_setopmode(struct ath_hw *ah)
3971 {
3972         ath9k_hw_set_operating_mode(ah, ah->opmode);
3973 }
3974
3975 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3976 {
3977         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3978         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3979 }
3980
3981 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3982 {
3983         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3984         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3985 }
3986
3987 void ath9k_hw_write_associd(struct ath_softc *sc)
3988 {
3989         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3990         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3991                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3992 }
3993
3994 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3995 {
3996         u64 tsf;
3997
3998         tsf = REG_READ(ah, AR_TSF_U32);
3999         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4000
4001         return tsf;
4002 }
4003
4004 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4005 {
4006         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4007         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4008 }
4009
4010 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4011 {
4012         ath9k_ps_wakeup(ah->ah_sc);
4013         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4014                            AH_TSF_WRITE_TIMEOUT))
4015                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
4016                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4017
4018         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4019         ath9k_ps_restore(ah->ah_sc);
4020 }
4021
4022 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4023 {
4024         if (setting)
4025                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4026         else
4027                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4028 }
4029
4030 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4031 {
4032         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4033                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
4034                 ah->slottime = (u32) -1;
4035                 return false;
4036         } else {
4037                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4038                 ah->slottime = us;
4039                 return true;
4040         }
4041 }
4042
4043 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
4044 {
4045         u32 macmode;
4046
4047         if (mode == ATH9K_HT_MACMODE_2040 &&
4048             !ah->config.cwm_ignore_extcca)
4049                 macmode = AR_2040_JOINED_RX_CLEAR;
4050         else
4051                 macmode = 0;
4052
4053         REG_WRITE(ah, AR_2040_MODE, macmode);
4054 }
4055
4056 /***************************/
4057 /*  Bluetooth Coexistence  */
4058 /***************************/
4059
4060 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
4061 {
4062         /* connect bt_active to baseband */
4063         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
4064                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
4065                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
4066
4067         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
4068                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
4069
4070         /* Set input mux for bt_active to gpio pin */
4071         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
4072                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
4073                         ah->btactive_gpio);
4074
4075         /* Configure the desired gpio port for input */
4076         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
4077
4078         /* Configure the desired GPIO port for TX_FRAME output */
4079         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
4080                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
4081 }