SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static void ath9k_hw_newstate(u16 devid,
 441                               struct ath_hw *ah)
 442 {
 443         ah->hw_version.magic = AR5416_MAGIC;
 444         ah->regulatory.country_code = CTRY_DEFAULT;
 445         ah->hw_version.devid = devid;
 446         ah->hw_version.subvendorid = 0;
 447
 448         ah->ah_flags = 0;
 449         if ((devid == AR5416_AR9100_DEVID))
 450                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 451         if (!AR_SREV_9100(ah))
 452                 ah->ah_flags = AH_USE_EEPROM;
 453
 454         ah->regulatory.power_limit = MAX_RATE_POWER;
 455         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 456         ah->atim_window = 0;
 457         ah->diversity_control = ah->config.diversity_control;
 458         ah->antenna_switch_swap =
 459                 ah->config.antenna_switch_swap;
 460         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 461         ah->beacon_interval = 100;
 462         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 463         ah->slottime = (u32) -1;
 464         ah->acktimeout = (u32) -1;
 465         ah->ctstimeout = (u32) -1;
 466         ah->globaltxtimeout = (u32) -1;
 467
 468         ah->gbeacon_rate = 0;
 469
 470         ah->power_mode = ATH9K_PM_UNDEFINED;
 471 }
 472
 473 static int ath9k_hw_rfattach(struct ath_hw *ah)
 474 {
 475         bool rfStatus = false;
 476         int ecode = 0;
 477
 478         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 479         if (!rfStatus) {
 480                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 481                         "RF setup failed, status: %u\n", ecode);
 482                 return ecode;
 483         }
 484
 485         return 0;
 486 }
 487
 488 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 489 {
 490         u32 val;
 491
 492         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 493
 494         val = ath9k_hw_get_radiorev(ah);
 495         switch (val & AR_RADIO_SREV_MAJOR) {
 496         case 0:
 497                 val = AR_RAD5133_SREV_MAJOR;
 498                 break;
 499         case AR_RAD5133_SREV_MAJOR:
 500         case AR_RAD5122_SREV_MAJOR:
 501         case AR_RAD2133_SREV_MAJOR:
 502         case AR_RAD2122_SREV_MAJOR:
 503                 break;
 504         default:
 505                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 506                         "Radio Chip Rev 0x%02X not supported\n",
 507                         val & AR_RADIO_SREV_MAJOR);
 508                 return -EOPNOTSUPP;
 509         }
 510
 511         ah->hw_version.analog5GhzRev = val;
 512
 513         return 0;
 514 }
 515
 516 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 517 {
 518         u32 sum;
 519         int i;
 520         u16 eeval;
 521
 522         sum = 0;
 523         for (i = 0; i < 3; i++) {
 524                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 525                 sum += eeval;
 526                 ah->macaddr[2 * i] = eeval >> 8;
 527                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 528         }
 529         if (sum == 0 || sum == 0xffff * 3)
 530                 return -EADDRNOTAVAIL;
 531
 532         return 0;
 533 }
 534
 535 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 536 {
 537         u32 rxgain_type;
 538
 539         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 540                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 541
 542                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 543                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 544                         ar9280Modes_backoff_13db_rxgain_9280_2,
 545                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 546                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 547                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 548                         ar9280Modes_backoff_23db_rxgain_9280_2,
 549                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 550                 else
 551                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 552                         ar9280Modes_original_rxgain_9280_2,
 553                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 554         } else {
 555                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 556                         ar9280Modes_original_rxgain_9280_2,
 557                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 558         }
 559 }
 560
 561 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 562 {
 563         u32 txgain_type;
 564
 565         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 566                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 567
 568                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 569                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 570                         ar9280Modes_high_power_tx_gain_9280_2,
 571                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 572                 else
 573                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 574                         ar9280Modes_original_tx_gain_9280_2,
 575                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 576         } else {
 577                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 578                 ar9280Modes_original_tx_gain_9280_2,
 579                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 580         }
 581 }
 582
 583 static int ath9k_hw_post_attach(struct ath_hw *ah)
 584 {
 585         int ecode;
 586
 587         if (!ath9k_hw_chip_test(ah))
 588                 return -ENODEV;
 589
 590         ecode = ath9k_hw_rf_claim(ah);
 591         if (ecode != 0)
 592                 return ecode;
 593
 594         ecode = ath9k_hw_eeprom_attach(ah);
 595         if (ecode != 0)
 596                 return ecode;
 597
 598         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 599                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 600
 601         ecode = ath9k_hw_rfattach(ah);
 602         if (ecode != 0)
 603                 return ecode;
 604
 605         if (!AR_SREV_9100(ah)) {
 606                 ath9k_hw_ani_setup(ah);
 607                 ath9k_hw_ani_attach(ah);
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int ath9k_hw_do_attach(struct ath_hw *ah,
 614                               u16 devid,
 615                               struct ath_softc *sc)
 616 {
 617         int r;
 618         u32 i, j;
 619
 620         ath9k_hw_newstate(devid, ah);
 621         ath9k_hw_set_defaults(ah);
 622
 623         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 624                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 625                 r = -EIO;
 626                 goto bad;
 627         }
 628
 629         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 630                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 631                 r = -EIO;
 632                 goto bad;
 633         }
 634
 635         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 636                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 637                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 638                         ah->config.serialize_regmode =
 639                                 SER_REG_MODE_ON;
 640                 } else {
 641                         ah->config.serialize_regmode =
 642                                 SER_REG_MODE_OFF;
 643                 }
 644         }
 645
 646         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 647                 ah->config.serialize_regmode);
 648
 649         switch (ah->hw_version.macVersion) {
 650         case AR_SREV_VERSION_5416_PCI:
 651         case AR_SREV_VERSION_5416_PCIE:
 652         case AR_SREV_VERSION_9160:
 653         case AR_SREV_VERSION_9100:
 654         case AR_SREV_VERSION_9280:
 655         case AR_SREV_VERSION_9285:
 656         case AR_SREV_VERSION_9287:
 657                 break;
 658         default:
 659                 DPRINTF(sc, ATH_DBG_FATAL,
 660                         "Mac Chip Rev 0x%02x.%x is not supported by "
 661                         "this driver\n", ah->hw_version.macVersion,
 662                         ah->hw_version.macRev);
 663                 r = -EOPNOTSUPP;
 664                 goto bad;
 665         }
 666
 667         if (AR_SREV_9100(ah)) {
 668                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 669                 ah->supp_cals = IQ_MISMATCH_CAL;
 670                 ah->is_pciexpress = false;
 671         }
 672         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 673
 674         if (AR_SREV_9160_10_OR_LATER(ah)) {
 675                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 676                         ah->iq_caldata.calData = &iq_cal_single_sample;
 677                         ah->adcgain_caldata.calData =
 678                                 &adc_gain_cal_single_sample;
 679                         ah->adcdc_caldata.calData =
 680                                 &adc_dc_cal_single_sample;
 681                         ah->adcdc_calinitdata.calData =
 682                                 &adc_init_dc_cal;
 683                 } else {
 684                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 685                         ah->adcgain_caldata.calData =
 686                                 &adc_gain_cal_multi_sample;
 687                         ah->adcdc_caldata.calData =
 688                                 &adc_dc_cal_multi_sample;
 689                         ah->adcdc_calinitdata.calData =
 690                                 &adc_init_dc_cal;
 691                 }
 692                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 693         }
 694
 695         ah->ani_function = ATH9K_ANI_ALL;
 696         if (AR_SREV_9280_10_OR_LATER(ah))
 697                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 698         if (AR_SREV_9287_11_OR_LATER(ah)) {
 699                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 700                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 701                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 702                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 703                 if (ah->config.pcie_clock_req)
 704                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 705                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 706                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 707                 else
 708                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 709                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 710                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 711                                         2);
 712         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 713                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 714                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 715                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 716                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 717
 718                 if (ah->config.pcie_clock_req)
 719                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 720                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 721                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 722                 else
 723                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 724                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 725                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 726                                   2);
 727         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 728
 729
 730                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 731                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 732                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 733                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 734
 735                 if (ah->config.pcie_clock_req) {
 736                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 737                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 738                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 739                 } else {
 740                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 741                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 742                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 743                                   2);
 744                 }
 745         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 746                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 747                                ARRAY_SIZE(ar9285Modes_9285), 6);
 748                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 749                                ARRAY_SIZE(ar9285Common_9285), 2);
 750
 751                 if (ah->config.pcie_clock_req) {
 752                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 753                         ar9285PciePhy_clkreq_off_L1_9285,
 754                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 755                 } else {
 756                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 757                         ar9285PciePhy_clkreq_always_on_L1_9285,
 758                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 759                 }
 760         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 761                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 762                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 763                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 764                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 765
 766                 if (ah->config.pcie_clock_req) {
 767                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 768                                ar9280PciePhy_clkreq_off_L1_9280,
 769                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 770                 } else {
 771                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 772                                ar9280PciePhy_clkreq_always_on_L1_9280,
 773                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 774                 }
 775                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 776                                ar9280Modes_fast_clock_9280_2,
 777                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 778         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 779                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 780                                ARRAY_SIZE(ar9280Modes_9280), 6);
 781                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 782                                ARRAY_SIZE(ar9280Common_9280), 2);
 783         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 784                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 785                                ARRAY_SIZE(ar5416Modes_9160), 6);
 786                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 787                                ARRAY_SIZE(ar5416Common_9160), 2);
 788                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 789                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 790                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 791                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 792                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 793                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 794                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 795                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 796                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 797                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 798                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 799                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 800                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 801                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 802                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 803                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 804                 if (AR_SREV_9160_11(ah)) {
 805                         INIT_INI_ARRAY(&ah->iniAddac,
 806                                        ar5416Addac_91601_1,
 807                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 808                 } else {
 809                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 810                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 811                 }
 812         } else if (AR_SREV_9100_OR_LATER(ah)) {
 813                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 814                                ARRAY_SIZE(ar5416Modes_9100), 6);
 815                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 816                                ARRAY_SIZE(ar5416Common_9100), 2);
 817                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 818                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 819                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 820                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 821                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 822                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 823                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 824                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 825                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 826                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 827                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 828                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 829                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 830                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 831                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 832                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 833                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 834                                ARRAY_SIZE(ar5416Addac_9100), 2);
 835         } else {
 836                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 837                                ARRAY_SIZE(ar5416Modes), 6);
 838                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 839                                ARRAY_SIZE(ar5416Common), 2);
 840                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 841                                ARRAY_SIZE(ar5416Bank0), 2);
 842                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 843                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 844                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 845                                ARRAY_SIZE(ar5416Bank1), 2);
 846                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 847                                ARRAY_SIZE(ar5416Bank2), 2);
 848                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 849                                ARRAY_SIZE(ar5416Bank3), 3);
 850                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 851                                ARRAY_SIZE(ar5416Bank6), 3);
 852                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 853                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 854                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 855                                ARRAY_SIZE(ar5416Bank7), 2);
 856                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 857                                ARRAY_SIZE(ar5416Addac), 2);
 858         }
 859
 860         if (ah->is_pciexpress)
 861                 ath9k_hw_configpcipowersave(ah, 0);
 862         else
 863                 ath9k_hw_disablepcie(ah);
 864
 865         r = ath9k_hw_post_attach(ah);
 866         if (r)
 867                 goto bad;
 868
 869         if (AR_SREV_9287_11(ah))
 870                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 871                 ar9287Modes_rx_gain_9287_1_1,
 872                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 873         else if (AR_SREV_9287_10(ah))
 874                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 875                 ar9287Modes_rx_gain_9287_1_0,
 876                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 877         else if (AR_SREV_9280_20(ah))
 878                 ath9k_hw_init_rxgain_ini(ah);
 879
 880         if (AR_SREV_9287_11(ah)) {
 881                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 882                 ar9287Modes_tx_gain_9287_1_1,
 883                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 884         } else if (AR_SREV_9287_10(ah)) {
 885                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 886                 ar9287Modes_tx_gain_9287_1_0,
 887                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 888         } else if (AR_SREV_9280_20(ah)) {
 889                 ath9k_hw_init_txgain_ini(ah);
 890         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 891                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 892
 893                 /* txgain table */
 894                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 895                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 896                         ar9285Modes_high_power_tx_gain_9285_1_2,
 897                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 898                 } else {
 899                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 900                         ar9285Modes_original_tx_gain_9285_1_2,
 901                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 902                 }
 903
 904         }
 905
 906         ath9k_hw_fill_cap_info(ah);
 907
 908         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 909             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 910
 911                 /* EEPROM Fixup */
 912                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 913                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 914
 915                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 916                                 u32 val = INI_RA(&ah->iniModes, i, j);
 917
 918                                 INI_RA(&ah->iniModes, i, j) =
 919                                         ath9k_hw_ini_fixup(ah,
 920                                                            &ah->eeprom.def,
 921                                                            reg, val);
 922                         }
 923                 }
 924         }
 925
 926         r = ath9k_hw_init_macaddr(ah);
 927         if (r) {
 928                 DPRINTF(sc, ATH_DBG_FATAL,
 929                         "Failed to initialize MAC address\n");
 930                 goto bad;
 931         }
 932
 933         if (AR_SREV_9285(ah))
 934                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 935         else
 936                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 937
 938         ath9k_init_nfcal_hist_buffer(ah);
 939
 940         return 0;
 941 bad:
 942         ath9k_hw_detach(ah);
 943         return r;
 944 }
 945
 946 static void ath9k_hw_init_bb(struct ath_hw *ah,
 947                              struct ath9k_channel *chan)
 948 {
 949         u32 synthDelay;
 950
 951         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 952         if (IS_CHAN_B(chan))
 953                 synthDelay = (4 * synthDelay) / 22;
 954         else
 955                 synthDelay /= 10;
 956
 957         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 958
 959         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 960 }
 961
 962 static void ath9k_hw_init_qos(struct ath_hw *ah)
 963 {
 964         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 965         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 966
 967         REG_WRITE(ah, AR_QOS_NO_ACK,
 968                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 969                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 970                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 971
 972         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 973         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 974         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 975         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 976         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 977 }
 978
 979 static void ath9k_hw_init_pll(struct ath_hw *ah,
 980                               struct ath9k_channel *chan)
 981 {
 982         u32 pll;
 983
 984         if (AR_SREV_9100(ah)) {
 985                 if (chan && IS_CHAN_5GHZ(chan))
 986                         pll = 0x1450;
 987                 else
 988                         pll = 0x1458;
 989         } else {
 990                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 991                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 992
 993                         if (chan && IS_CHAN_HALF_RATE(chan))
 994                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 995                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 996                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 997
 998                         if (chan && IS_CHAN_5GHZ(chan)) {
 999                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1000
1001
1002                                 if (AR_SREV_9280_20(ah)) {
1003                                         if (((chan->channel % 20) == 0)
1004                                             || ((chan->channel % 10) == 0))
1005                                                 pll = 0x2850;
1006                                         else
1007                                                 pll = 0x142c;
1008                                 }
1009                         } else {
1010                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1011                         }
1012
1013                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1014
1015                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1016
1017                         if (chan && IS_CHAN_HALF_RATE(chan))
1018                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1019                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1020                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1021
1022                         if (chan && IS_CHAN_5GHZ(chan))
1023                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1024                         else
1025                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1026                 } else {
1027                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1028
1029                         if (chan && IS_CHAN_HALF_RATE(chan))
1030                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1031                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1032                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1033
1034                         if (chan && IS_CHAN_5GHZ(chan))
1035                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1036                         else
1037                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1038                 }
1039         }
1040         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1041
1042         udelay(RTC_PLL_SETTLE_DELAY);
1043
1044         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1045 }
1046
1047 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1048 {
1049         int rx_chainmask, tx_chainmask;
1050
1051         rx_chainmask = ah->rxchainmask;
1052         tx_chainmask = ah->txchainmask;
1053
1054         switch (rx_chainmask) {
1055         case 0x5:
1056                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1057                             AR_PHY_SWAP_ALT_CHAIN);
1058         case 0x3:
1059                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1060                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1061                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1062                         break;
1063                 }
1064         case 0x1:
1065         case 0x2:
1066         case 0x7:
1067                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1068                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1069                 break;
1070         default:
1071                 break;
1072         }
1073
1074         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1075         if (tx_chainmask == 0x5) {
1076                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1077                             AR_PHY_SWAP_ALT_CHAIN);
1078         }
1079         if (AR_SREV_9100(ah))
1080                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1081                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1082 }
1083
1084 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1085                                           enum nl80211_iftype opmode)
1086 {
1087         ah->mask_reg = AR_IMR_TXERR |
1088                 AR_IMR_TXURN |
1089                 AR_IMR_RXERR |
1090                 AR_IMR_RXORN |
1091                 AR_IMR_BCNMISC;
1092
1093         if (ah->config.intr_mitigation)
1094                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1095         else
1096                 ah->mask_reg |= AR_IMR_RXOK;
1097
1098         ah->mask_reg |= AR_IMR_TXOK;
1099
1100         if (opmode == NL80211_IFTYPE_AP)
1101                 ah->mask_reg |= AR_IMR_MIB;
1102
1103         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1104         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1105
1106         if (!AR_SREV_9100(ah)) {
1107                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1108                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1109                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1110         }
1111 }
1112
1113 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1114 {
1115         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1116                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1117                 ah->acktimeout = (u32) -1;
1118                 return false;
1119         } else {
1120                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1121                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1122                 ah->acktimeout = us;
1123                 return true;
1124         }
1125 }
1126
1127 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1128 {
1129         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1130                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1131                 ah->ctstimeout = (u32) -1;
1132                 return false;
1133         } else {
1134                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1135                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1136                 ah->ctstimeout = us;
1137                 return true;
1138         }
1139 }
1140
1141 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1142 {
1143         if (tu > 0xFFFF) {
1144                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1145                         "bad global tx timeout %u\n", tu);
1146                 ah->globaltxtimeout = (u32) -1;
1147                 return false;
1148         } else {
1149                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1150                 ah->globaltxtimeout = tu;
1151                 return true;
1152         }
1153 }
1154
1155 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1156 {
1157         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1158                 ah->misc_mode);
1159
1160         if (ah->misc_mode != 0)
1161                 REG_WRITE(ah, AR_PCU_MISC,
1162                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1163         if (ah->slottime != (u32) -1)
1164                 ath9k_hw_setslottime(ah, ah->slottime);
1165         if (ah->acktimeout != (u32) -1)
1166                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1167         if (ah->ctstimeout != (u32) -1)
1168                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1169         if (ah->globaltxtimeout != (u32) -1)
1170                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1171 }
1172
1173 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1174 {
1175         return vendorid == ATHEROS_VENDOR_ID ?
1176                 ath9k_hw_devname(devid) : NULL;
1177 }
1178
1179 void ath9k_hw_detach(struct ath_hw *ah)
1180 {
1181         if (!AR_SREV_9100(ah))
1182                 ath9k_hw_ani_detach(ah);
1183
1184         ath9k_hw_rfdetach(ah);
1185         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1186         kfree(ah);
1187 }
1188
1189 int ath9k_hw_attach(struct ath_hw *ah, u16 devid, struct ath_softc *sc)
1190 {
1191         switch (devid) {
1192         case AR5416_DEVID_PCI:
1193         case AR5416_DEVID_PCIE:
1194         case AR5416_AR9100_DEVID:
1195         case AR9160_DEVID_PCI:
1196         case AR9280_DEVID_PCI:
1197         case AR9280_DEVID_PCIE:
1198         case AR9285_DEVID_PCIE:
1199         case AR5416_DEVID_AR9287_PCI:
1200         case AR5416_DEVID_AR9287_PCIE:
1201                 return ath9k_hw_do_attach(ah, devid, sc);
1202         default:
1203                 break;
1204         }
1205         return -EOPNOTSUPP;
1206 }
1207
1208 /*******/
1209 /* INI */
1210 /*******/
1211
1212 static void ath9k_hw_override_ini(struct ath_hw *ah,
1213                                   struct ath9k_channel *chan)
1214 {
1215         /*
1216          * Set the RX_ABORT and RX_DIS and clear if off only after
1217          * RXE is set for MAC. This prevents frames with corrupted
1218          * descriptor status.
1219          */
1220         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1221
1222
1223         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1224             AR_SREV_9280_10_OR_LATER(ah))
1225                 return;
1226
1227         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1228 }
1229
1230 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1231                               struct ar5416_eeprom_def *pEepData,
1232                               u32 reg, u32 value)
1233 {
1234         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1235
1236         switch (ah->hw_version.devid) {
1237         case AR9280_DEVID_PCI:
1238                 if (reg == 0x7894) {
1239                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1240                                 "ini VAL: %x  EEPROM: %x\n", value,
1241                                 (pBase->version & 0xff));
1242
1243                         if ((pBase->version & 0xff) > 0x0a) {
1244                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1245                                         "PWDCLKIND: %d\n",
1246                                         pBase->pwdclkind);
1247                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1248                                 value |= AR_AN_TOP2_PWDCLKIND &
1249                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1250                         } else {
1251                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1252                                         "PWDCLKIND Earlier Rev\n");
1253                         }
1254
1255                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1256                                 "final ini VAL: %x\n", value);
1257                 }
1258                 break;
1259         }
1260
1261         return value;
1262 }
1263
1264 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1265                               struct ar5416_eeprom_def *pEepData,
1266                               u32 reg, u32 value)
1267 {
1268         if (ah->eep_map == EEP_MAP_4KBITS)
1269                 return value;
1270         else
1271                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1272 }
1273
1274 static void ath9k_olc_init(struct ath_hw *ah)
1275 {
1276         u32 i;
1277
1278         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1279                 ah->originalGain[i] =
1280                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1281                                         AR_PHY_TX_GAIN);
1282         ah->PDADCdelta = 0;
1283 }
1284
1285 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1286                               struct ath9k_channel *chan)
1287 {
1288         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1289
1290         if (IS_CHAN_B(chan))
1291                 ctl |= CTL_11B;
1292         else if (IS_CHAN_G(chan))
1293                 ctl |= CTL_11G;
1294         else
1295                 ctl |= CTL_11A;
1296
1297         return ctl;
1298 }
1299
1300 static int ath9k_hw_process_ini(struct ath_hw *ah,
1301                                 struct ath9k_channel *chan,
1302                                 enum ath9k_ht_macmode macmode)
1303 {
1304         int i, regWrites = 0;
1305         struct ieee80211_channel *channel = chan->chan;
1306         u32 modesIndex, freqIndex;
1307
1308         switch (chan->chanmode) {
1309         case CHANNEL_A:
1310         case CHANNEL_A_HT20:
1311                 modesIndex = 1;
1312                 freqIndex = 1;
1313                 break;
1314         case CHANNEL_A_HT40PLUS:
1315         case CHANNEL_A_HT40MINUS:
1316                 modesIndex = 2;
1317                 freqIndex = 1;
1318                 break;
1319         case CHANNEL_G:
1320         case CHANNEL_G_HT20:
1321         case CHANNEL_B:
1322                 modesIndex = 4;
1323                 freqIndex = 2;
1324                 break;
1325         case CHANNEL_G_HT40PLUS:
1326         case CHANNEL_G_HT40MINUS:
1327                 modesIndex = 3;
1328                 freqIndex = 2;
1329                 break;
1330
1331         default:
1332                 return -EINVAL;
1333         }
1334
1335         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1336         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1337         ah->eep_ops->set_addac(ah, chan);
1338
1339         if (AR_SREV_5416_22_OR_LATER(ah)) {
1340                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1341         } else {
1342                 struct ar5416IniArray temp;
1343                 u32 addacSize =
1344                         sizeof(u32) * ah->iniAddac.ia_rows *
1345                         ah->iniAddac.ia_columns;
1346
1347                 memcpy(ah->addac5416_21,
1348                        ah->iniAddac.ia_array, addacSize);
1349
1350                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1351
1352                 temp.ia_array = ah->addac5416_21;
1353                 temp.ia_columns = ah->iniAddac.ia_columns;
1354                 temp.ia_rows = ah->iniAddac.ia_rows;
1355                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1356         }
1357
1358         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1359
1360         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1361                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1362                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1363
1364                 REG_WRITE(ah, reg, val);
1365
1366                 if (reg >= 0x7800 && reg < 0x78a0
1367                     && ah->config.analog_shiftreg) {
1368                         udelay(100);
1369                 }
1370
1371                 DO_DELAY(regWrites);
1372         }
1373
1374         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1375                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1376
1377         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1378             AR_SREV_9287_10_OR_LATER(ah))
1379                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1380
1381         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1382                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1383                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1384
1385                 REG_WRITE(ah, reg, val);
1386
1387                 if (reg >= 0x7800 && reg < 0x78a0
1388                     && ah->config.analog_shiftreg) {
1389                         udelay(100);
1390                 }
1391
1392                 DO_DELAY(regWrites);
1393         }
1394
1395         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1396
1397         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1398                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1399                                 regWrites);
1400         }
1401
1402         ath9k_hw_override_ini(ah, chan);
1403         ath9k_hw_set_regs(ah, chan, macmode);
1404         ath9k_hw_init_chain_masks(ah);
1405
1406         if (OLC_FOR_AR9280_20_LATER)
1407                 ath9k_olc_init(ah);
1408
1409         ah->eep_ops->set_txpower(ah, chan,
1410                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1411                                  channel->max_antenna_gain * 2,
1412                                  channel->max_power * 2,
1413                                  min((u32) MAX_RATE_POWER,
1414                                  (u32) ah->regulatory.power_limit));
1415
1416         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1417                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1418                         "ar5416SetRfRegs failed\n");
1419                 return -EIO;
1420         }
1421
1422         return 0;
1423 }
1424
1425 /****************************************/
1426 /* Reset and Channel Switching Routines */
1427 /****************************************/
1428
1429 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1430 {
1431         u32 rfMode = 0;
1432
1433         if (chan == NULL)
1434                 return;
1435
1436         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1437                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1438
1439         if (!AR_SREV_9280_10_OR_LATER(ah))
1440                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1441                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1442
1443         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1444                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1445
1446         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1447 }
1448
1449 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1450 {
1451         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1452 }
1453
1454 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1455 {
1456         u32 regval;
1457
1458         regval = REG_READ(ah, AR_AHB_MODE);
1459         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1460
1461         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1462         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1463
1464         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1465
1466         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1467         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1468
1469         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1470
1471         if (AR_SREV_9285(ah)) {
1472                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1473                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1474         } else {
1475                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1476                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1477         }
1478 }
1479
1480 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1481 {
1482         u32 val;
1483
1484         val = REG_READ(ah, AR_STA_ID1);
1485         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1486         switch (opmode) {
1487         case NL80211_IFTYPE_AP:
1488                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1489                           | AR_STA_ID1_KSRCH_MODE);
1490                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1491                 break;
1492         case NL80211_IFTYPE_ADHOC:
1493         case NL80211_IFTYPE_MESH_POINT:
1494                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1495                           | AR_STA_ID1_KSRCH_MODE);
1496                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1497                 break;
1498         case NL80211_IFTYPE_STATION:
1499         case NL80211_IFTYPE_MONITOR:
1500                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1501                 break;
1502         }
1503 }
1504
1505 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1506                                                  u32 coef_scaled,
1507                                                  u32 *coef_mantissa,
1508                                                  u32 *coef_exponent)
1509 {
1510         u32 coef_exp, coef_man;
1511
1512         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1513                 if ((coef_scaled >> coef_exp) & 0x1)
1514                         break;
1515
1516         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1517
1518         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1519
1520         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1521         *coef_exponent = coef_exp - 16;
1522 }
1523
1524 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1525                                      struct ath9k_channel *chan)
1526 {
1527         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1528         u32 clockMhzScaled = 0x64000000;
1529         struct chan_centers centers;
1530
1531         if (IS_CHAN_HALF_RATE(chan))
1532                 clockMhzScaled = clockMhzScaled >> 1;
1533         else if (IS_CHAN_QUARTER_RATE(chan))
1534                 clockMhzScaled = clockMhzScaled >> 2;
1535
1536         ath9k_hw_get_channel_centers(ah, chan, &centers);
1537         coef_scaled = clockMhzScaled / centers.synth_center;
1538
1539         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1540                                       &ds_coef_exp);
1541
1542         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1543                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1544         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1545                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1546
1547         coef_scaled = (9 * coef_scaled) / 10;
1548
1549         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1550                                       &ds_coef_exp);
1551
1552         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1553                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1554         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1555                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1556 }
1557
1558 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1559 {
1560         u32 rst_flags;
1561         u32 tmpReg;
1562
1563         if (AR_SREV_9100(ah)) {
1564                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1565                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1566                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1567                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1568                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1569         }
1570
1571         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1572                   AR_RTC_FORCE_WAKE_ON_INT);
1573
1574         if (AR_SREV_9100(ah)) {
1575                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1576                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1577         } else {
1578                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1579                 if (tmpReg &
1580                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1581                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1582                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1583                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1584                 } else {
1585                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1586                 }
1587
1588                 rst_flags = AR_RTC_RC_MAC_WARM;
1589                 if (type == ATH9K_RESET_COLD)
1590                         rst_flags |= AR_RTC_RC_MAC_COLD;
1591         }
1592
1593         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1594         udelay(50);
1595
1596         REG_WRITE(ah, AR_RTC_RC, 0);
1597         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1598                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1599                         "RTC stuck in MAC reset\n");
1600                 return false;
1601         }
1602
1603         if (!AR_SREV_9100(ah))
1604                 REG_WRITE(ah, AR_RC, 0);
1605
1606         ath9k_hw_init_pll(ah, NULL);
1607
1608         if (AR_SREV_9100(ah))
1609                 udelay(50);
1610
1611         return true;
1612 }
1613
1614 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1615 {
1616         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1617                   AR_RTC_FORCE_WAKE_ON_INT);
1618
1619         REG_WRITE(ah, AR_RTC_RESET, 0);
1620         udelay(2);
1621         REG_WRITE(ah, AR_RTC_RESET, 1);
1622
1623         if (!ath9k_hw_wait(ah,
1624                            AR_RTC_STATUS,
1625                            AR_RTC_STATUS_M,
1626                            AR_RTC_STATUS_ON,
1627                            AH_WAIT_TIMEOUT)) {
1628                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1629                 return false;
1630         }
1631
1632         ath9k_hw_read_revisions(ah);
1633
1634         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1635 }
1636
1637 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1638 {
1639         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1640                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1641
1642         switch (type) {
1643         case ATH9K_RESET_POWER_ON:
1644                 return ath9k_hw_set_reset_power_on(ah);
1645         case ATH9K_RESET_WARM:
1646         case ATH9K_RESET_COLD:
1647                 return ath9k_hw_set_reset(ah, type);
1648         default:
1649                 return false;
1650         }
1651 }
1652
1653 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1654                               enum ath9k_ht_macmode macmode)
1655 {
1656         u32 phymode;
1657         u32 enableDacFifo = 0;
1658
1659         if (AR_SREV_9285_10_OR_LATER(ah))
1660                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1661                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1662
1663         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1664                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1665
1666         if (IS_CHAN_HT40(chan)) {
1667                 phymode |= AR_PHY_FC_DYN2040_EN;
1668
1669                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1670                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1671                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1672
1673                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1674                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1675         }
1676         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1677
1678         ath9k_hw_set11nmac2040(ah, macmode);
1679
1680         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1681         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1682 }
1683
1684 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1685                                 struct ath9k_channel *chan)
1686 {
1687         if (OLC_FOR_AR9280_20_LATER) {
1688                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1689                         return false;
1690         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1691                 return false;
1692
1693         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1694                 return false;
1695
1696         ah->chip_fullsleep = false;
1697         ath9k_hw_init_pll(ah, chan);
1698         ath9k_hw_set_rfmode(ah, chan);
1699
1700         return true;
1701 }
1702
1703 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1704                                     struct ath9k_channel *chan,
1705                                     enum ath9k_ht_macmode macmode)
1706 {
1707         struct ieee80211_channel *channel = chan->chan;
1708         u32 synthDelay, qnum;
1709
1710         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1711                 if (ath9k_hw_numtxpending(ah, qnum)) {
1712                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1713                                 "Transmit frames pending on queue %d\n", qnum);
1714                         return false;
1715                 }
1716         }
1717
1718         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1719         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1720                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1721                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1722                         "Could not kill baseband RX\n");
1723                 return false;
1724         }
1725
1726         ath9k_hw_set_regs(ah, chan, macmode);
1727
1728         if (AR_SREV_9280_10_OR_LATER(ah)) {
1729                 ath9k_hw_ar9280_set_channel(ah, chan);
1730         } else {
1731                 if (!(ath9k_hw_set_channel(ah, chan))) {
1732                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1733                                 "Failed to set channel\n");
1734                         return false;
1735                 }
1736         }
1737
1738         ah->eep_ops->set_txpower(ah, chan,
1739                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1740                              channel->max_antenna_gain * 2,
1741                              channel->max_power * 2,
1742                              min((u32) MAX_RATE_POWER,
1743                              (u32) ah->regulatory.power_limit));
1744
1745         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1746         if (IS_CHAN_B(chan))
1747                 synthDelay = (4 * synthDelay) / 22;
1748         else
1749                 synthDelay /= 10;
1750
1751         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1752
1753         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1754
1755         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1756                 ath9k_hw_set_delta_slope(ah, chan);
1757
1758         if (AR_SREV_9280_10_OR_LATER(ah))
1759                 ath9k_hw_9280_spur_mitigate(ah, chan);
1760         else
1761                 ath9k_hw_spur_mitigate(ah, chan);
1762
1763         if (!chan->oneTimeCalsDone)
1764                 chan->oneTimeCalsDone = true;
1765
1766         return true;
1767 }
1768
1769 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1770 {
1771         int bb_spur = AR_NO_SPUR;
1772         int freq;
1773         int bin, cur_bin;
1774         int bb_spur_off, spur_subchannel_sd;
1775         int spur_freq_sd;
1776         int spur_delta_phase;
1777         int denominator;
1778         int upper, lower, cur_vit_mask;
1779         int tmp, newVal;
1780         int i;
1781         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1782                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1783         };
1784         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1785                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1786         };
1787         int inc[4] = { 0, 100, 0, 0 };
1788         struct chan_centers centers;
1789
1790         int8_t mask_m[123];
1791         int8_t mask_p[123];
1792         int8_t mask_amt;
1793         int tmp_mask;
1794         int cur_bb_spur;
1795         bool is2GHz = IS_CHAN_2GHZ(chan);
1796
1797         memset(&mask_m, 0, sizeof(int8_t) * 123);
1798         memset(&mask_p, 0, sizeof(int8_t) * 123);
1799
1800         ath9k_hw_get_channel_centers(ah, chan, &centers);
1801         freq = centers.synth_center;
1802
1803         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1804         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1805                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1806
1807                 if (is2GHz)
1808                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1809                 else
1810                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1811
1812                 if (AR_NO_SPUR == cur_bb_spur)
1813                         break;
1814                 cur_bb_spur = cur_bb_spur - freq;
1815
1816                 if (IS_CHAN_HT40(chan)) {
1817                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1818                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1819                                 bb_spur = cur_bb_spur;
1820                                 break;
1821                         }
1822                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1823                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1824                         bb_spur = cur_bb_spur;
1825                         break;
1826                 }
1827         }
1828
1829         if (AR_NO_SPUR == bb_spur) {
1830                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1831                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1832                 return;
1833         } else {
1834                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1835                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1836         }
1837
1838         bin = bb_spur * 320;
1839
1840         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1841
1842         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1843                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1844                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1845                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1846         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1847
1848         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1849                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1850                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1851                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1852                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1853         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1854
1855         if (IS_CHAN_HT40(chan)) {
1856                 if (bb_spur < 0) {
1857                         spur_subchannel_sd = 1;
1858                         bb_spur_off = bb_spur + 10;
1859                 } else {
1860                         spur_subchannel_sd = 0;
1861                         bb_spur_off = bb_spur - 10;
1862                 }
1863         } else {
1864                 spur_subchannel_sd = 0;
1865                 bb_spur_off = bb_spur;
1866         }
1867
1868         if (IS_CHAN_HT40(chan))
1869                 spur_delta_phase =
1870                         ((bb_spur * 262144) /
1871                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1872         else
1873                 spur_delta_phase =
1874                         ((bb_spur * 524288) /
1875                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1876
1877         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1878         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1879
1880         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1881                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1882                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1883         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1884
1885         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1886         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1887
1888         cur_bin = -6000;
1889         upper = bin + 100;
1890         lower = bin - 100;
1891
1892         for (i = 0; i < 4; i++) {
1893                 int pilot_mask = 0;
1894                 int chan_mask = 0;
1895                 int bp = 0;
1896                 for (bp = 0; bp < 30; bp++) {
1897                         if ((cur_bin > lower) && (cur_bin < upper)) {
1898                                 pilot_mask = pilot_mask | 0x1 << bp;
1899                                 chan_mask = chan_mask | 0x1 << bp;
1900                         }
1901                         cur_bin += 100;
1902                 }
1903                 cur_bin += inc[i];
1904                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1905                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1906         }
1907
1908         cur_vit_mask = 6100;
1909         upper = bin + 120;
1910         lower = bin - 120;
1911
1912         for (i = 0; i < 123; i++) {
1913                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1914
1915                         /* workaround for gcc bug #37014 */
1916                         volatile int tmp_v = abs(cur_vit_mask - bin);
1917
1918                         if (tmp_v < 75)
1919                                 mask_amt = 1;
1920                         else
1921                                 mask_amt = 0;
1922                         if (cur_vit_mask < 0)
1923                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1924                         else
1925                                 mask_p[cur_vit_mask / 100] = mask_amt;
1926                 }
1927                 cur_vit_mask -= 100;
1928         }
1929
1930         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1931                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1932                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1933                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1934                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1935                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1936                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1937                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1938         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1939         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1940
1941         tmp_mask = (mask_m[31] << 28)
1942                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1943                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1944                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1945                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1946                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1947                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1948                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1949         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1950         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1951
1952         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1953                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1954                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1955                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1956                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1957                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1958                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1959                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1960         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1961         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1962
1963         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1964                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1965                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1966                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1967                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1968                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1969                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1970                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1971         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1972         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1973
1974         tmp_mask = (mask_p[15] << 28)
1975                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1976                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1977                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1978                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1979                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1980                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1981                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1982         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1983         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1984
1985         tmp_mask = (mask_p[30] << 28)
1986                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1987                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1988                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1989                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1990                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1991                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1992                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1993         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1994         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1995
1996         tmp_mask = (mask_p[45] << 28)
1997                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1998                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1999                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2000                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2001                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2002                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2003                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2004         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2005         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2006
2007         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2008                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2009                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2010                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2011                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2012                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2013                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2014                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2015         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2016         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2017 }
2018
2019 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2020 {
2021         int bb_spur = AR_NO_SPUR;
2022         int bin, cur_bin;
2023         int spur_freq_sd;
2024         int spur_delta_phase;
2025         int denominator;
2026         int upper, lower, cur_vit_mask;
2027         int tmp, new;
2028         int i;
2029         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2030                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2031         };
2032         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2033                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2034         };
2035         int inc[4] = { 0, 100, 0, 0 };
2036
2037         int8_t mask_m[123];
2038         int8_t mask_p[123];
2039         int8_t mask_amt;
2040         int tmp_mask;
2041         int cur_bb_spur;
2042         bool is2GHz = IS_CHAN_2GHZ(chan);
2043
2044         memset(&mask_m, 0, sizeof(int8_t) * 123);
2045         memset(&mask_p, 0, sizeof(int8_t) * 123);
2046
2047         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2048                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2049                 if (AR_NO_SPUR == cur_bb_spur)
2050                         break;
2051                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2052                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2053                         bb_spur = cur_bb_spur;
2054                         break;
2055                 }
2056         }
2057
2058         if (AR_NO_SPUR == bb_spur)
2059                 return;
2060
2061         bin = bb_spur * 32;
2062
2063         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2064         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2065                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2066                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2067                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2068
2069         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2070
2071         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2072                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2073                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2074                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2075                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2076         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2077
2078         spur_delta_phase = ((bb_spur * 524288) / 100) &
2079                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2080
2081         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2082         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2083
2084         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2085                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2086                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2087         REG_WRITE(ah, AR_PHY_TIMING11, new);
2088
2089         cur_bin = -6000;
2090         upper = bin + 100;
2091         lower = bin - 100;
2092
2093         for (i = 0; i < 4; i++) {
2094                 int pilot_mask = 0;
2095                 int chan_mask = 0;
2096                 int bp = 0;
2097                 for (bp = 0; bp < 30; bp++) {
2098                         if ((cur_bin > lower) && (cur_bin < upper)) {
2099                                 pilot_mask = pilot_mask | 0x1 << bp;
2100                                 chan_mask = chan_mask | 0x1 << bp;
2101                         }
2102                         cur_bin += 100;
2103                 }
2104                 cur_bin += inc[i];
2105                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2106                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2107         }
2108
2109         cur_vit_mask = 6100;
2110         upper = bin + 120;
2111         lower = bin - 120;
2112
2113         for (i = 0; i < 123; i++) {
2114                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2115
2116                         /* workaround for gcc bug #37014 */
2117                         volatile int tmp_v = abs(cur_vit_mask - bin);
2118
2119                         if (tmp_v < 75)
2120                                 mask_amt = 1;
2121                         else
2122                                 mask_amt = 0;
2123                         if (cur_vit_mask < 0)
2124                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2125                         else
2126                                 mask_p[cur_vit_mask / 100] = mask_amt;
2127                 }
2128                 cur_vit_mask -= 100;
2129         }
2130
2131         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2132                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2133                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2134                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2135                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2136                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2137                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2138                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2139         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2140         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2141
2142         tmp_mask = (mask_m[31] << 28)
2143                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2144                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2145                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2146                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2147                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2148                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2149                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2150         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2151         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2152
2153         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2154                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2155                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2156                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2157                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2158                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2159                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2160                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2161         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2162         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2163
2164         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2165                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2166                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2167                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2168                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2169                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2170                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2171                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2172         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2173         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2174
2175         tmp_mask = (mask_p[15] << 28)
2176                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2177                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2178                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2179                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2180                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2181                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2182                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2183         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2184         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2185
2186         tmp_mask = (mask_p[30] << 28)
2187                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2188                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2189                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2190                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2191                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2192                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2193                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2194         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2195         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2196
2197         tmp_mask = (mask_p[45] << 28)
2198                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2199                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2200                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2201                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2202                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2203                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2204                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2205         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2206         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2207
2208         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2209                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2210                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2211                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2212                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2213                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2214                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2215                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2216         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2217         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2218 }
2219
2220 static void ath9k_enable_rfkill(struct ath_hw *ah)
2221 {
2222         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2223                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2224
2225         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2226                     AR_GPIO_INPUT_MUX2_RFSILENT);
2227
2228         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2229         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2230 }
2231
2232 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2233                     bool bChannelChange)
2234 {
2235         u32 saveLedState;
2236         struct ath_softc *sc = ah->ah_sc;
2237         struct ath9k_channel *curchan = ah->curchan;
2238         u32 saveDefAntenna;
2239         u32 macStaId1;
2240         int i, rx_chainmask, r;
2241
2242         ah->extprotspacing = sc->ht_extprotspacing;
2243         ah->txchainmask = sc->tx_chainmask;
2244         ah->rxchainmask = sc->rx_chainmask;
2245
2246         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2247                 return -EIO;
2248
2249         if (curchan)
2250                 ath9k_hw_getnf(ah, curchan);
2251
2252         if (bChannelChange &&
2253             (ah->chip_fullsleep != true) &&
2254             (ah->curchan != NULL) &&
2255             (chan->channel != ah->curchan->channel) &&
2256             ((chan->channelFlags & CHANNEL_ALL) ==
2257              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2258             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2259                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2260
2261                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2262                         ath9k_hw_loadnf(ah, ah->curchan);
2263                         ath9k_hw_start_nfcal(ah);
2264                         return 0;
2265                 }
2266         }
2267
2268         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2269         if (saveDefAntenna == 0)
2270                 saveDefAntenna = 1;
2271
2272         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2273
2274         saveLedState = REG_READ(ah, AR_CFG_LED) &
2275                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2276                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2277
2278         ath9k_hw_mark_phy_inactive(ah);
2279
2280         if (!ath9k_hw_chip_reset(ah, chan)) {
2281                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2282                 return -EINVAL;
2283         }
2284
2285         if (AR_SREV_9280_10_OR_LATER(ah))
2286                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2287
2288         if (AR_SREV_9287_10_OR_LATER(ah)) {
2289                 /* Enable ASYNC FIFO */
2290                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2291                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2292                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2293                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2294                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2295                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2296                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2297         }
2298         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2299         if (r)
2300                 return r;
2301
2302         /* Setup MFP options for CCMP */
2303         if (AR_SREV_9280_20_OR_LATER(ah)) {
2304                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2305                  * frames when constructing CCMP AAD. */
2306                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2307                               0xc7ff);
2308                 ah->sw_mgmt_crypto = false;
2309         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2310                 /* Disable hardware crypto for management frames */
2311                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2312                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2313                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2314                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2315                 ah->sw_mgmt_crypto = true;
2316         } else
2317                 ah->sw_mgmt_crypto = true;
2318
2319         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2320                 ath9k_hw_set_delta_slope(ah, chan);
2321
2322         if (AR_SREV_9280_10_OR_LATER(ah))
2323                 ath9k_hw_9280_spur_mitigate(ah, chan);
2324         else
2325                 ath9k_hw_spur_mitigate(ah, chan);
2326
2327         ah->eep_ops->set_board_values(ah, chan);
2328
2329         ath9k_hw_decrease_chain_power(ah, chan);
2330
2331         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2332         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2333                   | macStaId1
2334                   | AR_STA_ID1_RTS_USE_DEF
2335                   | (ah->config.
2336                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2337                   | ah->sta_id1_defaults);
2338         ath9k_hw_set_operating_mode(ah, ah->opmode);
2339
2340         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2341         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2342
2343         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2344
2345         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2346         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2347                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2348
2349         REG_WRITE(ah, AR_ISR, ~0);
2350
2351         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2352
2353         if (AR_SREV_9280_10_OR_LATER(ah))
2354                 ath9k_hw_ar9280_set_channel(ah, chan);
2355         else
2356                 if (!(ath9k_hw_set_channel(ah, chan)))
2357                         return -EIO;
2358
2359         for (i = 0; i < AR_NUM_DCU; i++)
2360                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2361
2362         ah->intr_txqs = 0;
2363         for (i = 0; i < ah->caps.total_queues; i++)
2364                 ath9k_hw_resettxqueue(ah, i);
2365
2366         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2367         ath9k_hw_init_qos(ah);
2368
2369         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2370                 ath9k_enable_rfkill(ah);
2371
2372         ath9k_hw_init_user_settings(ah);
2373
2374         if (AR_SREV_9287_10_OR_LATER(ah)) {
2375                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2376                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2377                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2378                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2379                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2380                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2381
2382                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2383                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2384
2385                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2386                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2387                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2388                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2389         }
2390         if (AR_SREV_9287_10_OR_LATER(ah)) {
2391                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2392                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2393         }
2394
2395         REG_WRITE(ah, AR_STA_ID1,
2396                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2397
2398         ath9k_hw_set_dma(ah);
2399
2400         REG_WRITE(ah, AR_OBS, 8);
2401
2402         if (ah->config.intr_mitigation) {
2403                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2404                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2405         }
2406
2407         ath9k_hw_init_bb(ah, chan);
2408
2409         if (!ath9k_hw_init_cal(ah, chan))
2410                 return -EIO;
2411
2412         rx_chainmask = ah->rxchainmask;
2413         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2414                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2415                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2416         }
2417
2418         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2419
2420         if (AR_SREV_9100(ah)) {
2421                 u32 mask;
2422                 mask = REG_READ(ah, AR_CFG);
2423                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2424                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2425                                 "CFG Byte Swap Set 0x%x\n", mask);
2426                 } else {
2427                         mask =
2428                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2429                         REG_WRITE(ah, AR_CFG, mask);
2430                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2431                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2432                 }
2433         } else {
2434 #ifdef __BIG_ENDIAN
2435                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2436 #endif
2437         }
2438
2439         return 0;
2440 }
2441
2442 /************************/
2443 /* Key Cache Management */
2444 /************************/
2445
2446 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2447 {
2448         u32 keyType;
2449
2450         if (entry >= ah->caps.keycache_size) {
2451                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2452                         "keychache entry %u out of range\n", entry);
2453                 return false;
2454         }
2455
2456         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2457
2458         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2459         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2460         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2461         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2462         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2463         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2464         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2465         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2466
2467         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2468                 u16 micentry = entry + 64;
2469
2470                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2471                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2472                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2473                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2474
2475         }
2476
2477         if (ah->curchan == NULL)
2478                 return true;
2479
2480         return true;
2481 }
2482
2483 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2484 {
2485         u32 macHi, macLo;
2486
2487         if (entry >= ah->caps.keycache_size) {
2488                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2489                         "keychache entry %u out of range\n", entry);
2490                 return false;
2491         }
2492
2493         if (mac != NULL) {
2494                 macHi = (mac[5] << 8) | mac[4];
2495                 macLo = (mac[3] << 24) |
2496                         (mac[2] << 16) |
2497                         (mac[1] << 8) |
2498                         mac[0];
2499                 macLo >>= 1;
2500                 macLo |= (macHi & 1) << 31;
2501                 macHi >>= 1;
2502         } else {
2503                 macLo = macHi = 0;
2504         }
2505         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2506         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2507
2508         return true;
2509 }
2510
2511 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2512                                  const struct ath9k_keyval *k,
2513                                  const u8 *mac)
2514 {
2515         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2516         u32 key0, key1, key2, key3, key4;
2517         u32 keyType;
2518
2519         if (entry >= pCap->keycache_size) {
2520                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2521                         "keycache entry %u out of range\n", entry);
2522                 return false;
2523         }
2524
2525         switch (k->kv_type) {
2526         case ATH9K_CIPHER_AES_OCB:
2527                 keyType = AR_KEYTABLE_TYPE_AES;
2528                 break;
2529         case ATH9K_CIPHER_AES_CCM:
2530                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2531                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2532                                 "AES-CCM not supported by mac rev 0x%x\n",
2533                                 ah->hw_version.macRev);
2534                         return false;
2535                 }
2536                 keyType = AR_KEYTABLE_TYPE_CCM;
2537                 break;
2538         case ATH9K_CIPHER_TKIP:
2539                 keyType = AR_KEYTABLE_TYPE_TKIP;
2540                 if (ATH9K_IS_MIC_ENABLED(ah)
2541                     && entry + 64 >= pCap->keycache_size) {
2542                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2543                                 "entry %u inappropriate for TKIP\n", entry);
2544                         return false;
2545                 }
2546                 break;
2547         case ATH9K_CIPHER_WEP:
2548                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2549                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2550                                 "WEP key length %u too small\n", k->kv_len);
2551                         return false;
2552                 }
2553                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2554                         keyType = AR_KEYTABLE_TYPE_40;
2555                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2556                         keyType = AR_KEYTABLE_TYPE_104;
2557                 else
2558                         keyType = AR_KEYTABLE_TYPE_128;
2559                 break;
2560         case ATH9K_CIPHER_CLR:
2561                 keyType = AR_KEYTABLE_TYPE_CLR;
2562                 break;
2563         default:
2564                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2565                         "cipher %u not supported\n", k->kv_type);
2566                 return false;
2567         }
2568
2569         key0 = get_unaligned_le32(k->kv_val + 0);
2570         key1 = get_unaligned_le16(k->kv_val + 4);
2571         key2 = get_unaligned_le32(k->kv_val + 6);
2572         key3 = get_unaligned_le16(k->kv_val + 10);
2573         key4 = get_unaligned_le32(k->kv_val + 12);
2574         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2575                 key4 &= 0xff;
2576
2577         /*
2578          * Note: Key cache registers access special memory area that requires
2579          * two 32-bit writes to actually update the values in the internal
2580          * memory. Consequently, the exact order and pairs used here must be
2581          * maintained.
2582          */
2583
2584         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2585                 u16 micentry = entry + 64;
2586
2587                 /*
2588                  * Write inverted key[47:0] first to avoid Michael MIC errors
2589                  * on frames that could be sent or received at the same time.
2590                  * The correct key will be written in the end once everything
2591                  * else is ready.
2592                  */
2593                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2594                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2595
2596                 /* Write key[95:48] */
2597                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2598                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2599
2600                 /* Write key[127:96] and key type */
2601                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2602                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2603
2604                 /* Write MAC address for the entry */
2605                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2606
2607                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2608                         /*
2609                          * TKIP uses two key cache entries:
2610                          * Michael MIC TX/RX keys in the same key cache entry
2611                          * (idx = main index + 64):
2612                          * key0 [31:0] = RX key [31:0]
2613                          * key1 [15:0] = TX key [31:16]
2614                          * key1 [31:16] = reserved
2615                          * key2 [31:0] = RX key [63:32]
2616                          * key3 [15:0] = TX key [15:0]
2617                          * key3 [31:16] = reserved
2618                          * key4 [31:0] = TX key [63:32]
2619                          */
2620                         u32 mic0, mic1, mic2, mic3, mic4;
2621
2622                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2623                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2624                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2625                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2626                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2627
2628                         /* Write RX[31:0] and TX[31:16] */
2629                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2630                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2631
2632                         /* Write RX[63:32] and TX[15:0] */
2633                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2634                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2635
2636                         /* Write TX[63:32] and keyType(reserved) */
2637                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2638                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2639                                   AR_KEYTABLE_TYPE_CLR);
2640
2641                 } else {
2642                         /*
2643                          * TKIP uses four key cache entries (two for group
2644                          * keys):
2645                          * Michael MIC TX/RX keys are in different key cache
2646                          * entries (idx = main index + 64 for TX and
2647                          * main index + 32 + 96 for RX):
2648                          * key0 [31:0] = TX/RX MIC key [31:0]
2649                          * key1 [31:0] = reserved
2650                          * key2 [31:0] = TX/RX MIC key [63:32]
2651                          * key3 [31:0] = reserved
2652                          * key4 [31:0] = reserved
2653                          *
2654                          * Upper layer code will call this function separately
2655                          * for TX and RX keys when these registers offsets are
2656                          * used.
2657                          */
2658                         u32 mic0, mic2;
2659
2660                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2661                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2662
2663                         /* Write MIC key[31:0] */
2664                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2665                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2666
2667                         /* Write MIC key[63:32] */
2668                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2669                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2670
2671                         /* Write TX[63:32] and keyType(reserved) */
2672                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2673                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2674                                   AR_KEYTABLE_TYPE_CLR);
2675                 }
2676
2677                 /* MAC address registers are reserved for the MIC entry */
2678                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2679                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2680
2681                 /*
2682                  * Write the correct (un-inverted) key[47:0] last to enable
2683                  * TKIP now that all other registers are set with correct
2684                  * values.
2685                  */
2686                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2687                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2688         } else {
2689                 /* Write key[47:0] */
2690                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2691                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2692
2693                 /* Write key[95:48] */
2694                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2695                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2696
2697                 /* Write key[127:96] and key type */
2698                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2699                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2700
2701                 /* Write MAC address for the entry */
2702                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2703         }
2704
2705         return true;
2706 }
2707
2708 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2709 {
2710         if (entry < ah->caps.keycache_size) {
2711                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2712                 if (val & AR_KEYTABLE_VALID)
2713                         return true;
2714         }
2715         return false;
2716 }
2717
2718 /******************************/
2719 /* Power Management (Chipset) */
2720 /******************************/
2721
2722 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2723 {
2724         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2725         if (setChip) {
2726                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2727                             AR_RTC_FORCE_WAKE_EN);
2728                 if (!AR_SREV_9100(ah))
2729                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2730
2731                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2732                             AR_RTC_RESET_EN);
2733         }
2734 }
2735
2736 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2737 {
2738         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2739         if (setChip) {
2740                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2741
2742                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2743                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2744                                   AR_RTC_FORCE_WAKE_ON_INT);
2745                 } else {
2746                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2747                                     AR_RTC_FORCE_WAKE_EN);
2748                 }
2749         }
2750 }
2751
2752 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2753 {
2754         u32 val;
2755         int i;
2756
2757         if (setChip) {
2758                 if ((REG_READ(ah, AR_RTC_STATUS) &
2759                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2760                         if (ath9k_hw_set_reset_reg(ah,
2761                                            ATH9K_RESET_POWER_ON) != true) {
2762                                 return false;
2763                         }
2764                 }
2765                 if (AR_SREV_9100(ah))
2766                         REG_SET_BIT(ah, AR_RTC_RESET,
2767                                     AR_RTC_RESET_EN);
2768
2769                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2770                             AR_RTC_FORCE_WAKE_EN);
2771                 udelay(50);
2772
2773                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2774                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2775                         if (val == AR_RTC_STATUS_ON)
2776                                 break;
2777                         udelay(50);
2778                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2779                                     AR_RTC_FORCE_WAKE_EN);
2780                 }
2781                 if (i == 0) {
2782                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2783                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2784                         return false;
2785                 }
2786         }
2787
2788         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2789
2790         return true;
2791 }
2792
2793 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2794                                      enum ath9k_power_mode mode)
2795 {
2796         int status = true, setChip = true;
2797         static const char *modes[] = {
2798                 "AWAKE",
2799                 "FULL-SLEEP",
2800                 "NETWORK SLEEP",
2801                 "UNDEFINED"
2802         };
2803
2804         if (ah->power_mode == mode)
2805                 return status;
2806
2807         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2808                 modes[ah->power_mode], modes[mode]);
2809
2810         switch (mode) {
2811         case ATH9K_PM_AWAKE:
2812                 status = ath9k_hw_set_power_awake(ah, setChip);
2813                 break;
2814         case ATH9K_PM_FULL_SLEEP:
2815                 ath9k_set_power_sleep(ah, setChip);
2816                 ah->chip_fullsleep = true;
2817                 break;
2818         case ATH9K_PM_NETWORK_SLEEP:
2819                 ath9k_set_power_network_sleep(ah, setChip);
2820                 break;
2821         default:
2822                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2823                         "Unknown power mode %u\n", mode);
2824                 return false;
2825         }
2826         ah->power_mode = mode;
2827
2828         return status;
2829 }
2830
2831 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2832 {
2833         unsigned long flags;
2834         bool ret;
2835
2836         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2837         ret = ath9k_hw_setpower_nolock(ah, mode);
2838         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2839
2840         return ret;
2841 }
2842
2843 void ath9k_ps_wakeup(struct ath_softc *sc)
2844 {
2845         unsigned long flags;
2846
2847         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2848         if (++sc->ps_usecount != 1)
2849                 goto unlock;
2850
2851         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2852
2853  unlock:
2854         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2855 }
2856
2857 void ath9k_ps_restore(struct ath_softc *sc)
2858 {
2859         unsigned long flags;
2860
2861         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2862         if (--sc->ps_usecount != 0)
2863                 goto unlock;
2864
2865         if (sc->ps_enabled &&
2866             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2867                               SC_OP_WAIT_FOR_CAB |
2868                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2869                               SC_OP_WAIT_FOR_TX_ACK)))
2870                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2871
2872  unlock:
2873         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2874 }
2875
2876 /*
2877  * Helper for ASPM support.
2878  *
2879  * Disable PLL when in L0s as well as receiver clock when in L1.
2880  * This power saving option must be enabled through the SerDes.
2881  *
2882  * Programming the SerDes must go through the same 288 bit serial shift
2883  * register as the other analog registers.  Hence the 9 writes.
2884  */
2885 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2886 {
2887         u8 i;
2888
2889         if (ah->is_pciexpress != true)
2890                 return;
2891
2892         /* Do not touch SerDes registers */
2893         if (ah->config.pcie_powersave_enable == 2)
2894                 return;
2895
2896         /* Nothing to do on restore for 11N */
2897         if (restore)
2898                 return;
2899
2900         if (AR_SREV_9280_20_OR_LATER(ah)) {
2901                 /*
2902                  * AR9280 2.0 or later chips use SerDes values from the
2903                  * initvals.h initialized depending on chipset during
2904                  * ath9k_hw_do_attach()
2905                  */
2906                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2907                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2908                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2909                 }
2910         } else if (AR_SREV_9280(ah) &&
2911                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2912                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2913                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2914
2915                 /* RX shut off when elecidle is asserted */
2916                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2917                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2918                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2919
2920                 /* Shut off CLKREQ active in L1 */
2921                 if (ah->config.pcie_clock_req)
2922                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2923                 else
2924                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2925
2926                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2927                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2928                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2929
2930                 /* Load the new settings */
2931                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2932
2933         } else {
2934                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2935                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2936
2937                 /* RX shut off when elecidle is asserted */
2938                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2939                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2940                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2941
2942                 /*
2943                  * Ignore ah->ah_config.pcie_clock_req setting for
2944                  * pre-AR9280 11n
2945                  */
2946                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2947
2948                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2949                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2950                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2951
2952                 /* Load the new settings */
2953                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2954         }
2955
2956         udelay(1000);
2957
2958         /* set bit 19 to allow forcing of pcie core into L1 state */
2959         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2960
2961         /* Several PCIe massages to ensure proper behaviour */
2962         if (ah->config.pcie_waen) {
2963                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2964         } else {
2965                 if (AR_SREV_9285(ah))
2966                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2967                 /*
2968                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2969                  * otherwise card may disappear.
2970                  */
2971                 else if (AR_SREV_9280(ah))
2972                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2973                 else
2974                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2975         }
2976 }
2977
2978 /**********************/
2979 /* Interrupt Handling */
2980 /**********************/
2981
2982 bool ath9k_hw_intrpend(struct ath_hw *ah)
2983 {
2984         u32 host_isr;
2985
2986         if (AR_SREV_9100(ah))
2987                 return true;
2988
2989         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2990         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2991                 return true;
2992
2993         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2994         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2995             && (host_isr != AR_INTR_SPURIOUS))
2996                 return true;
2997
2998         return false;
2999 }
3000
3001 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3002 {
3003         u32 isr = 0;
3004         u32 mask2 = 0;
3005         struct ath9k_hw_capabilities *pCap = &ah->caps;
3006         u32 sync_cause = 0;
3007         bool fatal_int = false;
3008
3009         if (!AR_SREV_9100(ah)) {
3010                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3011                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3012                             == AR_RTC_STATUS_ON) {
3013                                 isr = REG_READ(ah, AR_ISR);
3014                         }
3015                 }
3016
3017                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3018                         AR_INTR_SYNC_DEFAULT;
3019
3020                 *masked = 0;
3021
3022                 if (!isr && !sync_cause)
3023                         return false;
3024         } else {
3025                 *masked = 0;
3026                 isr = REG_READ(ah, AR_ISR);
3027         }
3028
3029         if (isr) {
3030                 if (isr & AR_ISR_BCNMISC) {
3031                         u32 isr2;
3032                         isr2 = REG_READ(ah, AR_ISR_S2);
3033                         if (isr2 & AR_ISR_S2_TIM)
3034                                 mask2 |= ATH9K_INT_TIM;
3035                         if (isr2 & AR_ISR_S2_DTIM)
3036                                 mask2 |= ATH9K_INT_DTIM;
3037                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3038                                 mask2 |= ATH9K_INT_DTIMSYNC;
3039                         if (isr2 & (AR_ISR_S2_CABEND))
3040                                 mask2 |= ATH9K_INT_CABEND;
3041                         if (isr2 & AR_ISR_S2_GTT)
3042                                 mask2 |= ATH9K_INT_GTT;
3043                         if (isr2 & AR_ISR_S2_CST)
3044                                 mask2 |= ATH9K_INT_CST;
3045                         if (isr2 & AR_ISR_S2_TSFOOR)
3046                                 mask2 |= ATH9K_INT_TSFOOR;
3047                 }
3048
3049                 isr = REG_READ(ah, AR_ISR_RAC);
3050                 if (isr == 0xffffffff) {
3051                         *masked = 0;
3052                         return false;
3053                 }
3054
3055                 *masked = isr & ATH9K_INT_COMMON;
3056
3057                 if (ah->config.intr_mitigation) {
3058                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3059                                 *masked |= ATH9K_INT_RX;
3060                 }
3061
3062                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3063                         *masked |= ATH9K_INT_RX;
3064                 if (isr &
3065                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3066                      AR_ISR_TXEOL)) {
3067                         u32 s0_s, s1_s;
3068
3069                         *masked |= ATH9K_INT_TX;
3070
3071                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3072                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3073                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3074
3075                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3076                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3077                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3078                 }
3079
3080                 if (isr & AR_ISR_RXORN) {
3081                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3082                                 "receive FIFO overrun interrupt\n");
3083                 }
3084
3085                 if (!AR_SREV_9100(ah)) {
3086                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3087                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3088                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3089                                         *masked |= ATH9K_INT_TIM_TIMER;
3090                         }
3091                 }
3092
3093                 *masked |= mask2;
3094         }
3095
3096         if (AR_SREV_9100(ah))
3097                 return true;
3098
3099         if (sync_cause) {
3100                 fatal_int =
3101                         (sync_cause &
3102                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3103                         ? true : false;
3104
3105                 if (fatal_int) {
3106                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3107                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3108                                         "received PCI FATAL interrupt\n");
3109                         }
3110                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3111                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3112                                         "received PCI PERR interrupt\n");
3113                         }
3114                         *masked |= ATH9K_INT_FATAL;
3115                 }
3116                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3117                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3118                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3119                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3120                         REG_WRITE(ah, AR_RC, 0);
3121                         *masked |= ATH9K_INT_FATAL;
3122                 }
3123                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3124                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3125                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3126                 }
3127
3128                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3129                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3130         }
3131
3132         return true;
3133 }
3134
3135 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3136 {
3137         u32 omask = ah->mask_reg;
3138         u32 mask, mask2;
3139         struct ath9k_hw_capabilities *pCap = &ah->caps;
3140
3141         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3142
3143         if (omask & ATH9K_INT_GLOBAL) {
3144                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3145                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3146                 (void) REG_READ(ah, AR_IER);
3147                 if (!AR_SREV_9100(ah)) {
3148                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3149                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3150
3151                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3152                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3153                 }
3154         }
3155
3156         mask = ints & ATH9K_INT_COMMON;
3157         mask2 = 0;
3158
3159         if (ints & ATH9K_INT_TX) {
3160                 if (ah->txok_interrupt_mask)
3161                         mask |= AR_IMR_TXOK;
3162                 if (ah->txdesc_interrupt_mask)
3163                         mask |= AR_IMR_TXDESC;
3164                 if (ah->txerr_interrupt_mask)
3165                         mask |= AR_IMR_TXERR;
3166                 if (ah->txeol_interrupt_mask)
3167                         mask |= AR_IMR_TXEOL;
3168         }
3169         if (ints & ATH9K_INT_RX) {
3170                 mask |= AR_IMR_RXERR;
3171                 if (ah->config.intr_mitigation)
3172                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3173                 else
3174                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3175                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3176                         mask |= AR_IMR_GENTMR;
3177         }
3178
3179         if (ints & (ATH9K_INT_BMISC)) {
3180                 mask |= AR_IMR_BCNMISC;
3181                 if (ints & ATH9K_INT_TIM)
3182                         mask2 |= AR_IMR_S2_TIM;
3183                 if (ints & ATH9K_INT_DTIM)
3184                         mask2 |= AR_IMR_S2_DTIM;
3185                 if (ints & ATH9K_INT_DTIMSYNC)
3186                         mask2 |= AR_IMR_S2_DTIMSYNC;
3187                 if (ints & ATH9K_INT_CABEND)
3188                         mask2 |= AR_IMR_S2_CABEND;
3189                 if (ints & ATH9K_INT_TSFOOR)
3190                         mask2 |= AR_IMR_S2_TSFOOR;
3191         }
3192
3193         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3194                 mask |= AR_IMR_BCNMISC;
3195                 if (ints & ATH9K_INT_GTT)
3196                         mask2 |= AR_IMR_S2_GTT;
3197                 if (ints & ATH9K_INT_CST)
3198                         mask2 |= AR_IMR_S2_CST;
3199         }
3200
3201         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3202         REG_WRITE(ah, AR_IMR, mask);
3203         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3204                                            AR_IMR_S2_DTIM |
3205                                            AR_IMR_S2_DTIMSYNC |
3206                                            AR_IMR_S2_CABEND |
3207                                            AR_IMR_S2_CABTO |
3208                                            AR_IMR_S2_TSFOOR |
3209                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3210         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3211         ah->mask_reg = ints;
3212
3213         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3214                 if (ints & ATH9K_INT_TIM_TIMER)
3215                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3216                 else
3217                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3218         }
3219
3220         if (ints & ATH9K_INT_GLOBAL) {
3221                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3222                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3223                 if (!AR_SREV_9100(ah)) {
3224                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3225                                   AR_INTR_MAC_IRQ);
3226                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3227
3228
3229                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3230                                   AR_INTR_SYNC_DEFAULT);
3231                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3232                                   AR_INTR_SYNC_DEFAULT);
3233                 }
3234                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3235                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3236         }
3237
3238         return omask;
3239 }
3240
3241 /*******************/
3242 /* Beacon Handling */
3243 /*******************/
3244
3245 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3246 {
3247         int flags = 0;
3248
3249         ah->beacon_interval = beacon_period;
3250
3251         switch (ah->opmode) {
3252         case NL80211_IFTYPE_STATION:
3253         case NL80211_IFTYPE_MONITOR:
3254                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3255                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3256                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3257                 flags |= AR_TBTT_TIMER_EN;
3258                 break;
3259         case NL80211_IFTYPE_ADHOC:
3260         case NL80211_IFTYPE_MESH_POINT:
3261                 REG_SET_BIT(ah, AR_TXCFG,
3262                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3263                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3264                           TU_TO_USEC(next_beacon +
3265                                      (ah->atim_window ? ah->
3266                                       atim_window : 1)));
3267                 flags |= AR_NDP_TIMER_EN;
3268         case NL80211_IFTYPE_AP:
3269                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3270                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3271                           TU_TO_USEC(next_beacon -
3272                                      ah->config.
3273                                      dma_beacon_response_time));
3274                 REG_WRITE(ah, AR_NEXT_SWBA,
3275                           TU_TO_USEC(next_beacon -
3276                                      ah->config.
3277                                      sw_beacon_response_time));
3278                 flags |=
3279                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3280                 break;
3281         default:
3282                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3283                         "%s: unsupported opmode: %d\n",
3284                         __func__, ah->opmode);
3285                 return;
3286                 break;
3287         }
3288
3289         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3290         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3291         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3292         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3293
3294         beacon_period &= ~ATH9K_BEACON_ENA;
3295         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3296                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3297                 ath9k_hw_reset_tsf(ah);
3298         }
3299
3300         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3301 }
3302
3303 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3304                                     const struct ath9k_beacon_state *bs)
3305 {
3306         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3307         struct ath9k_hw_capabilities *pCap = &ah->caps;
3308
3309         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3310
3311         REG_WRITE(ah, AR_BEACON_PERIOD,
3312                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3313         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3314                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3315
3316         REG_RMW_FIELD(ah, AR_RSSI_THR,
3317                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3318
3319         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3320
3321         if (bs->bs_sleepduration > beaconintval)
3322                 beaconintval = bs->bs_sleepduration;
3323
3324         dtimperiod = bs->bs_dtimperiod;
3325         if (bs->bs_sleepduration > dtimperiod)
3326                 dtimperiod = bs->bs_sleepduration;
3327
3328         if (beaconintval == dtimperiod)
3329                 nextTbtt = bs->bs_nextdtim;
3330         else
3331                 nextTbtt = bs->bs_nexttbtt;
3332
3333         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3334         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3335         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3336         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3337
3338         REG_WRITE(ah, AR_NEXT_DTIM,
3339                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3340         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3341
3342         REG_WRITE(ah, AR_SLEEP1,
3343                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3344                   | AR_SLEEP1_ASSUME_DTIM);
3345
3346         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3347                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3348         else
3349                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3350
3351         REG_WRITE(ah, AR_SLEEP2,
3352                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3353
3354         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3355         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3356
3357         REG_SET_BIT(ah, AR_TIMER_MODE,
3358                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3359                     AR_DTIM_TIMER_EN);
3360
3361         /* TSF Out of Range Threshold */
3362         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3363 }
3364
3365 /*******************/
3366 /* HW Capabilities */
3367 /*******************/
3368
3369 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3370 {
3371         struct ath9k_hw_capabilities *pCap = &ah->caps;
3372         u16 capField = 0, eeval;
3373
3374         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3375         ah->regulatory.current_rd = eeval;
3376
3377         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3378         if (AR_SREV_9285_10_OR_LATER(ah))
3379                 eeval |= AR9285_RDEXT_DEFAULT;
3380         ah->regulatory.current_rd_ext = eeval;
3381
3382         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3383
3384         if (ah->opmode != NL80211_IFTYPE_AP &&
3385             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3386                 if (ah->regulatory.current_rd == 0x64 ||
3387                     ah->regulatory.current_rd == 0x65)
3388                         ah->regulatory.current_rd += 5;
3389                 else if (ah->regulatory.current_rd == 0x41)
3390                         ah->regulatory.current_rd = 0x43;
3391                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3392                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3393         }
3394
3395         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3396         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3397
3398         if (eeval & AR5416_OPFLAGS_11A) {
3399                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3400                 if (ah->config.ht_enable) {
3401                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3402                                 set_bit(ATH9K_MODE_11NA_HT20,
3403                                         pCap->wireless_modes);
3404                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3405                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3406                                         pCap->wireless_modes);
3407                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3408                                         pCap->wireless_modes);
3409                         }
3410                 }
3411         }
3412
3413         if (eeval & AR5416_OPFLAGS_11G) {
3414                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3415                 if (ah->config.ht_enable) {
3416                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3417                                 set_bit(ATH9K_MODE_11NG_HT20,
3418                                         pCap->wireless_modes);
3419                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3420                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3421                                         pCap->wireless_modes);
3422                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3423                                         pCap->wireless_modes);
3424                         }
3425                 }
3426         }
3427
3428         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3429         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3430             !(eeval & AR5416_OPFLAGS_11A))
3431                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3432         else
3433                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3434
3435         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3436                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3437
3438         pCap->low_2ghz_chan = 2312;
3439         pCap->high_2ghz_chan = 2732;
3440
3441         pCap->low_5ghz_chan = 4920;
3442         pCap->high_5ghz_chan = 6100;
3443
3444         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3445         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3446         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3447
3448         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3449         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3450         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3451
3452         if (ah->config.ht_enable)
3453                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3454         else
3455                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3456
3457         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3458         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3459         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3460         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3461
3462         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3463                 pCap->total_queues =
3464                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3465         else
3466                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3467
3468         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3469                 pCap->keycache_size =
3470                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3471         else
3472                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3473
3474         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3475         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3476
3477         if (AR_SREV_9285_10_OR_LATER(ah))
3478                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3479         else if (AR_SREV_9280_10_OR_LATER(ah))
3480                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3481         else
3482                 pCap->num_gpio_pins = AR_NUM_GPIO;
3483
3484         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3485                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3486                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3487         } else {
3488                 pCap->rts_aggr_limit = (8 * 1024);
3489         }
3490
3491         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3492
3493 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3494         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3495         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3496                 ah->rfkill_gpio =
3497                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3498                 ah->rfkill_polarity =
3499                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3500
3501                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3502         }
3503 #endif
3504
3505         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3506             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3507             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3508             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3509             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3510             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3511                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3512         else
3513                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3514
3515         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3516                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3517         else
3518                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3519
3520         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3521                 pCap->reg_cap =
3522                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3523                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3524                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3525                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3526         } else {
3527                 pCap->reg_cap =
3528                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3529                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3530         }
3531
3532         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3533
3534         pCap->num_antcfg_5ghz =
3535                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3536         pCap->num_antcfg_2ghz =
3537                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3538
3539         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3540                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3541                 ah->btactive_gpio = 6;
3542                 ah->wlanactive_gpio = 5;
3543         }
3544 }
3545
3546 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3547                             u32 capability, u32 *result)
3548 {
3549         switch (type) {
3550         case ATH9K_CAP_CIPHER:
3551                 switch (capability) {
3552                 case ATH9K_CIPHER_AES_CCM:
3553                 case ATH9K_CIPHER_AES_OCB:
3554                 case ATH9K_CIPHER_TKIP:
3555                 case ATH9K_CIPHER_WEP:
3556                 case ATH9K_CIPHER_MIC:
3557                 case ATH9K_CIPHER_CLR:
3558                         return true;
3559                 default:
3560                         return false;
3561                 }
3562         case ATH9K_CAP_TKIP_MIC:
3563                 switch (capability) {
3564                 case 0:
3565                         return true;
3566                 case 1:
3567                         return (ah->sta_id1_defaults &
3568                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3569                         false;
3570                 }
3571         case ATH9K_CAP_TKIP_SPLIT:
3572                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3573                         false : true;
3574         case ATH9K_CAP_DIVERSITY:
3575                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3576                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3577                         true : false;
3578         case ATH9K_CAP_MCAST_KEYSRCH:
3579                 switch (capability) {
3580                 case 0:
3581                         return true;
3582                 case 1:
3583                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3584                                 return false;
3585                         } else {
3586                                 return (ah->sta_id1_defaults &
3587                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3588                                         false;
3589                         }
3590                 }
3591                 return false;
3592         case ATH9K_CAP_TXPOW:
3593                 switch (capability) {
3594                 case 0:
3595                         return 0;
3596                 case 1:
3597                         *result = ah->regulatory.power_limit;
3598                         return 0;
3599                 case 2:
3600                         *result = ah->regulatory.max_power_level;
3601                         return 0;
3602                 case 3:
3603                         *result = ah->regulatory.tp_scale;
3604                         return 0;
3605                 }
3606                 return false;
3607         case ATH9K_CAP_DS:
3608                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3609                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3610                         ? false : true;
3611         default:
3612                 return false;
3613         }
3614 }
3615
3616 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3617                             u32 capability, u32 setting, int *status)
3618 {
3619         u32 v;
3620
3621         switch (type) {
3622         case ATH9K_CAP_TKIP_MIC:
3623                 if (setting)
3624                         ah->sta_id1_defaults |=
3625                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3626                 else
3627                         ah->sta_id1_defaults &=
3628                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3629                 return true;
3630         case ATH9K_CAP_DIVERSITY:
3631                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3632                 if (setting)
3633                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3634                 else
3635                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3636                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3637                 return true;
3638         case ATH9K_CAP_MCAST_KEYSRCH:
3639                 if (setting)
3640                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3641                 else
3642                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3643                 return true;
3644         default:
3645                 return false;
3646         }
3647 }
3648
3649 /****************************/
3650 /* GPIO / RFKILL / Antennae */
3651 /****************************/
3652
3653 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3654                                          u32 gpio, u32 type)
3655 {
3656         int addr;
3657         u32 gpio_shift, tmp;
3658
3659         if (gpio > 11)
3660                 addr = AR_GPIO_OUTPUT_MUX3;
3661         else if (gpio > 5)
3662                 addr = AR_GPIO_OUTPUT_MUX2;
3663         else
3664                 addr = AR_GPIO_OUTPUT_MUX1;
3665
3666         gpio_shift = (gpio % 6) * 5;
3667
3668         if (AR_SREV_9280_20_OR_LATER(ah)
3669             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3670                 REG_RMW(ah, addr, (type << gpio_shift),
3671                         (0x1f << gpio_shift));
3672         } else {
3673                 tmp = REG_READ(ah, addr);
3674                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3675                 tmp &= ~(0x1f << gpio_shift);
3676                 tmp |= (type << gpio_shift);
3677                 REG_WRITE(ah, addr, tmp);
3678         }
3679 }
3680
3681 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3682 {
3683         u32 gpio_shift;
3684
3685         ASSERT(gpio < ah->caps.num_gpio_pins);
3686
3687         gpio_shift = gpio << 1;
3688
3689         REG_RMW(ah,
3690                 AR_GPIO_OE_OUT,
3691                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3692                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3693 }
3694
3695 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3696 {
3697 #define MS_REG_READ(x, y) \
3698         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3699
3700         if (gpio >= ah->caps.num_gpio_pins)
3701                 return 0xffffffff;
3702
3703         if (AR_SREV_9287_10_OR_LATER(ah))
3704                 return MS_REG_READ(AR9287, gpio) != 0;
3705         else if (AR_SREV_9285_10_OR_LATER(ah))
3706                 return MS_REG_READ(AR9285, gpio) != 0;
3707         else if (AR_SREV_9280_10_OR_LATER(ah))
3708                 return MS_REG_READ(AR928X, gpio) != 0;
3709         else
3710                 return MS_REG_READ(AR, gpio) != 0;
3711 }
3712
3713 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3714                          u32 ah_signal_type)
3715 {
3716         u32 gpio_shift;
3717
3718         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3719
3720         gpio_shift = 2 * gpio;
3721
3722         REG_RMW(ah,
3723                 AR_GPIO_OE_OUT,
3724                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3725                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3726 }
3727
3728 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3729 {
3730         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3731                 AR_GPIO_BIT(gpio));
3732 }
3733
3734 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3735 {
3736         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3737 }
3738
3739 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3740 {
3741         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3742 }
3743
3744 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3745                                enum ath9k_ant_setting settings,
3746                                struct ath9k_channel *chan,
3747                                u8 *tx_chainmask,
3748                                u8 *rx_chainmask,
3749                                u8 *antenna_cfgd)
3750 {
3751         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3752
3753         if (AR_SREV_9280(ah)) {
3754                 if (!tx_chainmask_cfg) {
3755
3756                         tx_chainmask_cfg = *tx_chainmask;
3757                         rx_chainmask_cfg = *rx_chainmask;
3758                 }
3759
3760                 switch (settings) {
3761                 case ATH9K_ANT_FIXED_A:
3762                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3763                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3764                         *antenna_cfgd = true;
3765                         break;
3766                 case ATH9K_ANT_FIXED_B:
3767                         if (ah->caps.tx_chainmask >
3768                             ATH9K_ANTENNA1_CHAINMASK) {
3769                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3770                         }
3771                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3772                         *antenna_cfgd = true;
3773                         break;
3774                 case ATH9K_ANT_VARIABLE:
3775                         *tx_chainmask = tx_chainmask_cfg;
3776                         *rx_chainmask = rx_chainmask_cfg;
3777                         *antenna_cfgd = true;
3778                         break;
3779                 default:
3780                         break;
3781                 }
3782         } else {
3783                 ah->diversity_control = settings;
3784         }
3785
3786         return true;
3787 }
3788
3789 /*********************/
3790 /* General Operation */
3791 /*********************/
3792
3793 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3794 {
3795         u32 bits = REG_READ(ah, AR_RX_FILTER);
3796         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3797
3798         if (phybits & AR_PHY_ERR_RADAR)
3799                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3800         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3801                 bits |= ATH9K_RX_FILTER_PHYERR;
3802
3803         return bits;
3804 }
3805
3806 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3807 {
3808         u32 phybits;
3809
3810         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3811         phybits = 0;
3812         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3813                 phybits |= AR_PHY_ERR_RADAR;
3814         if (bits & ATH9K_RX_FILTER_PHYERR)
3815                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3816         REG_WRITE(ah, AR_PHY_ERR, phybits);
3817
3818         if (phybits)
3819                 REG_WRITE(ah, AR_RXCFG,
3820                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3821         else
3822                 REG_WRITE(ah, AR_RXCFG,
3823                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3824 }
3825
3826 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3827 {
3828         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3829 }
3830
3831 bool ath9k_hw_disable(struct ath_hw *ah)
3832 {
3833         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3834                 return false;
3835
3836         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3837 }
3838
3839 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3840 {
3841         struct ath9k_channel *chan = ah->curchan;
3842         struct ieee80211_channel *channel = chan->chan;
3843
3844         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3845
3846         ah->eep_ops->set_txpower(ah, chan,
3847                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3848                                  channel->max_antenna_gain * 2,
3849                                  channel->max_power * 2,
3850                                  min((u32) MAX_RATE_POWER,
3851                                  (u32) ah->regulatory.power_limit));
3852 }
3853
3854 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3855 {
3856         memcpy(ah->macaddr, mac, ETH_ALEN);
3857 }
3858
3859 void ath9k_hw_setopmode(struct ath_hw *ah)
3860 {
3861         ath9k_hw_set_operating_mode(ah, ah->opmode);
3862 }
3863
3864 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3865 {
3866         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3867         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3868 }
3869
3870 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3871 {
3872         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3873         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3874 }
3875
3876 void ath9k_hw_write_associd(struct ath_softc *sc)
3877 {
3878         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3879         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3880                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3881 }
3882
3883 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3884 {
3885         u64 tsf;
3886
3887         tsf = REG_READ(ah, AR_TSF_U32);
3888         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3889
3890         return tsf;
3891 }
3892
3893 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3894 {
3895         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3896         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3897 }
3898
3899 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3900 {
3901         ath9k_ps_wakeup(ah->ah_sc);
3902         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3903                            AH_TSF_WRITE_TIMEOUT))
3904                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3905                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3906
3907         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3908         ath9k_ps_restore(ah->ah_sc);
3909 }
3910
3911 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3912 {
3913         if (setting)
3914                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3915         else
3916                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3917
3918         return true;
3919 }
3920
3921 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3922 {
3923         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3924                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3925                 ah->slottime = (u32) -1;
3926                 return false;
3927         } else {
3928                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3929                 ah->slottime = us;
3930                 return true;
3931         }
3932 }
3933
3934 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3935 {
3936         u32 macmode;
3937
3938         if (mode == ATH9K_HT_MACMODE_2040 &&
3939             !ah->config.cwm_ignore_extcca)
3940                 macmode = AR_2040_JOINED_RX_CLEAR;
3941         else
3942                 macmode = 0;
3943
3944         REG_WRITE(ah, AR_2040_MODE, macmode);
3945 }
3946
3947 /***************************/
3948 /*  Bluetooth Coexistence  */
3949 /***************************/
3950
3951 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3952 {
3953         /* connect bt_active to baseband */
3954         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3955                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3956                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3957
3958         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3959                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3960
3961         /* Set input mux for bt_active to gpio pin */
3962         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3963                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3964                         ah->btactive_gpio);
3965
3966         /* Configure the desired gpio port for input */
3967         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3968
3969         /* Configure the desired GPIO port for TX_FRAME output */
3970         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3971                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3972 }