SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  34 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  35
  36 /********************/
  37 /* Helper Functions */
  38 /********************/
  39
  40 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  41 {
  42         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  43
  44         if (!ah->curchan) /* should really check for CCK instead */
  45                 return clks / ATH9K_CLOCK_RATE_CCK;
  46         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  47                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  48
  49         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  50 }
  51
  52 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  53 {
  54         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  55
  56         if (conf_is_ht40(conf))
  57                 return ath9k_hw_mac_usec(ah, clks) / 2;
  58         else
  59                 return ath9k_hw_mac_usec(ah, clks);
  60 }
  61
  62 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  63 {
  64         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  65
  66         if (!ah->curchan) /* should really check for CCK instead */
  67                 return usecs *ATH9K_CLOCK_RATE_CCK;
  68         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  69                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  70         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  71 }
  72
  73 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  74 {
  75         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  76
  77         if (conf_is_ht40(conf))
  78                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  79         else
  80                 return ath9k_hw_mac_clks(ah, usecs);
  81 }
  82
  83 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  84 {
  85         int i;
  86
  87         BUG_ON(timeout < AH_TIME_QUANTUM);
  88
  89         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  90                 if ((REG_READ(ah, reg) & mask) == val)
  91                         return true;
  92
  93                 udelay(AH_TIME_QUANTUM);
  94         }
  95
  96         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  97                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  98                   timeout, reg, REG_READ(ah, reg), mask, val);
  99
 100         return false;
 101 }
 102
 103 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 104 {
 105         u32 retval;
 106         int i;
 107
 108         for (i = 0, retval = 0; i < n; i++) {
 109                 retval = (retval << 1) | (val & 1);
 110                 val >>= 1;
 111         }
 112         return retval;
 113 }
 114
 115 bool ath9k_get_channel_edges(struct ath_hw *ah,
 116                              u16 flags, u16 *low,
 117                              u16 *high)
 118 {
 119         struct ath9k_hw_capabilities *pCap = &ah->caps;
 120
 121         if (flags & CHANNEL_5GHZ) {
 122                 *low = pCap->low_5ghz_chan;
 123                 *high = pCap->high_5ghz_chan;
 124                 return true;
 125         }
 126         if ((flags & CHANNEL_2GHZ)) {
 127                 *low = pCap->low_2ghz_chan;
 128                 *high = pCap->high_2ghz_chan;
 129                 return true;
 130         }
 131         return false;
 132 }
 133
 134 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 135                            const struct ath_rate_table *rates,
 136                            u32 frameLen, u16 rateix,
 137                            bool shortPreamble)
 138 {
 139         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 140         u32 kbps;
 141
 142         kbps = rates->info[rateix].ratekbps;
 143
 144         if (kbps == 0)
 145                 return 0;
 146
 147         switch (rates->info[rateix].phy) {
 148         case WLAN_RC_PHY_CCK:
 149                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 150                 if (shortPreamble && rates->info[rateix].short_preamble)
 151                         phyTime >>= 1;
 152                 numBits = frameLen << 3;
 153                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 154                 break;
 155         case WLAN_RC_PHY_OFDM:
 156                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 157                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 158                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 159                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 160                         txTime = OFDM_SIFS_TIME_QUARTER
 161                                 + OFDM_PREAMBLE_TIME_QUARTER
 162                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 163                 } else if (ah->curchan &&
 164                            IS_CHAN_HALF_RATE(ah->curchan)) {
 165                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 166                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 167                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 168                         txTime = OFDM_SIFS_TIME_HALF +
 169                                 OFDM_PREAMBLE_TIME_HALF
 170                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 171                 } else {
 172                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 173                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 174                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 175                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 176                                 + (numSymbols * OFDM_SYMBOL_TIME);
 177                 }
 178                 break;
 179         default:
 180                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 181                           "Unknown phy %u (rate ix %u)\n",
 182                           rates->info[rateix].phy, rateix);
 183                 txTime = 0;
 184                 break;
 185         }
 186
 187         return txTime;
 188 }
 189
 190 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 191                                   struct ath9k_channel *chan,
 192                                   struct chan_centers *centers)
 193 {
 194         int8_t extoff;
 195
 196         if (!IS_CHAN_HT40(chan)) {
 197                 centers->ctl_center = centers->ext_center =
 198                         centers->synth_center = chan->channel;
 199                 return;
 200         }
 201
 202         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 203             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 204                 centers->synth_center =
 205                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 206                 extoff = 1;
 207         } else {
 208                 centers->synth_center =
 209                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 210                 extoff = -1;
 211         }
 212
 213         centers->ctl_center =
 214                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 215         /* 25 MHz spacing is supported by hw but not on upper layers */
 216         centers->ext_center =
 217                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 218 }
 219
 220 /******************/
 221 /* Chip Revisions */
 222 /******************/
 223
 224 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 225 {
 226         u32 val;
 227
 228         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 229
 230         if (val == 0xFF) {
 231                 val = REG_READ(ah, AR_SREV);
 232                 ah->hw_version.macVersion =
 233                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 234                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 235                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 236         } else {
 237                 if (!AR_SREV_9100(ah))
 238                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 239
 240                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 241
 242                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 243                         ah->is_pciexpress = true;
 244         }
 245 }
 246
 247 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 248 {
 249         u32 val;
 250         int i;
 251
 252         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 253
 254         for (i = 0; i < 8; i++)
 255                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 256         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 257         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 258
 259         return ath9k_hw_reverse_bits(val, 8);
 260 }
 261
 262 /************************************/
 263 /* HW Attach, Detach, Init Routines */
 264 /************************************/
 265
 266 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 267 {
 268         if (AR_SREV_9100(ah))
 269                 return;
 270
 271         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 272         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 273         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 274         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 275         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 280
 281         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 282 }
 283
 284 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 285 {
 286         struct ath_common *common = ath9k_hw_common(ah);
 287         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 288         u32 regHold[2];
 289         u32 patternData[4] = { 0x55555555,
 290                                0xaaaaaaaa,
 291                                0x66666666,
 292                                0x99999999 };
 293         int i, j;
 294
 295         for (i = 0; i < 2; i++) {
 296                 u32 addr = regAddr[i];
 297                 u32 wrData, rdData;
 298
 299                 regHold[i] = REG_READ(ah, addr);
 300                 for (j = 0; j < 0x100; j++) {
 301                         wrData = (j << 16) | j;
 302                         REG_WRITE(ah, addr, wrData);
 303                         rdData = REG_READ(ah, addr);
 304                         if (rdData != wrData) {
 305                                 ath_print(common, ATH_DBG_FATAL,
 306                                           "address test failed "
 307                                           "addr: 0x%08x - wr:0x%08x != "
 308                                           "rd:0x%08x\n",
 309                                           addr, wrData, rdData);
 310                                 return false;
 311                         }
 312                 }
 313                 for (j = 0; j < 4; j++) {
 314                         wrData = patternData[j];
 315                         REG_WRITE(ah, addr, wrData);
 316                         rdData = REG_READ(ah, addr);
 317                         if (wrData != rdData) {
 318                                 ath_print(common, ATH_DBG_FATAL,
 319                                           "address test failed "
 320                                           "addr: 0x%08x - wr:0x%08x != "
 321                                           "rd:0x%08x\n",
 322                                           addr, wrData, rdData);
 323                                 return false;
 324                         }
 325                 }
 326                 REG_WRITE(ah, regAddr[i], regHold[i]);
 327         }
 328         udelay(100);
 329
 330         return true;
 331 }
 332
 333 static const char *ath9k_hw_devname(u16 devid)
 334 {
 335         switch (devid) {
 336         case AR5416_DEVID_PCI:
 337                 return "Atheros 5416";
 338         case AR5416_DEVID_PCIE:
 339                 return "Atheros 5418";
 340         case AR9160_DEVID_PCI:
 341                 return "Atheros 9160";
 342         case AR5416_AR9100_DEVID:
 343                 return "Atheros 9100";
 344         case AR9280_DEVID_PCI:
 345         case AR9280_DEVID_PCIE:
 346                 return "Atheros 9280";
 347         case AR9285_DEVID_PCIE:
 348                 return "Atheros 9285";
 349         case AR5416_DEVID_AR9287_PCI:
 350         case AR5416_DEVID_AR9287_PCIE:
 351                 return "Atheros 9287";
 352         }
 353
 354         return NULL;
 355 }
 356
 357 static void ath9k_hw_init_config(struct ath_hw *ah)
 358 {
 359         int i;
 360
 361         ah->config.dma_beacon_response_time = 2;
 362         ah->config.sw_beacon_response_time = 10;
 363         ah->config.additional_swba_backoff = 0;
 364         ah->config.ack_6mb = 0x0;
 365         ah->config.cwm_ignore_extcca = 0;
 366         ah->config.pcie_powersave_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_waen = 0;
 369         ah->config.analog_shiftreg = 1;
 370         ah->config.ht_enable = 1;
 371         ah->config.ofdm_trig_low = 200;
 372         ah->config.ofdm_trig_high = 500;
 373         ah->config.cck_trig_high = 200;
 374         ah->config.cck_trig_low = 100;
 375         ah->config.enable_ani = 1;
 376         ah->config.diversity_control = ATH9K_ANT_VARIABLE;
 377         ah->config.antenna_switch_swap = 0;
 378
 379         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 380                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 381                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 382         }
 383
 384         ah->config.intr_mitigation = true;
 385
 386         /*
 387          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 388          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 389          * This means we use it for all AR5416 devices, and the few
 390          * minor PCI AR9280 devices out there.
 391          *
 392          * Serialization is required because these devices do not handle
 393          * well the case of two concurrent reads/writes due to the latency
 394          * involved. During one read/write another read/write can be issued
 395          * on another CPU while the previous read/write may still be working
 396          * on our hardware, if we hit this case the hardware poops in a loop.
 397          * We prevent this by serializing reads and writes.
 398          *
 399          * This issue is not present on PCI-Express devices or pre-AR5416
 400          * devices (legacy, 802.11abg).
 401          */
 402         if (num_possible_cpus() > 1)
 403                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 404 }
 405
 406 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 407 {
 408         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 409
 410         regulatory->country_code = CTRY_DEFAULT;
 411         regulatory->power_limit = MAX_RATE_POWER;
 412         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 413
 414         ah->hw_version.magic = AR5416_MAGIC;
 415         ah->hw_version.subvendorid = 0;
 416
 417         ah->ah_flags = 0;
 418         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 419                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 420         if (!AR_SREV_9100(ah))
 421                 ah->ah_flags = AH_USE_EEPROM;
 422
 423         ah->atim_window = 0;
 424         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 425         ah->beacon_interval = 100;
 426         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 427         ah->slottime = (u32) -1;
 428         ah->acktimeout = (u32) -1;
 429         ah->ctstimeout = (u32) -1;
 430         ah->globaltxtimeout = (u32) -1;
 431
 432         ah->gbeacon_rate = 0;
 433
 434         ah->power_mode = ATH9K_PM_UNDEFINED;
 435 }
 436
 437 static int ath9k_hw_rfattach(struct ath_hw *ah)
 438 {
 439         bool rfStatus = false;
 440         int ecode = 0;
 441
 442         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 443         if (!rfStatus) {
 444                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 445                           "RF setup failed, status: %u\n", ecode);
 446                 return ecode;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 453 {
 454         u32 val;
 455
 456         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 457
 458         val = ath9k_hw_get_radiorev(ah);
 459         switch (val & AR_RADIO_SREV_MAJOR) {
 460         case 0:
 461                 val = AR_RAD5133_SREV_MAJOR;
 462                 break;
 463         case AR_RAD5133_SREV_MAJOR:
 464         case AR_RAD5122_SREV_MAJOR:
 465         case AR_RAD2133_SREV_MAJOR:
 466         case AR_RAD2122_SREV_MAJOR:
 467                 break;
 468         default:
 469                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 470                           "Radio Chip Rev 0x%02X not supported\n",
 471                           val & AR_RADIO_SREV_MAJOR);
 472                 return -EOPNOTSUPP;
 473         }
 474
 475         ah->hw_version.analog5GhzRev = val;
 476
 477         return 0;
 478 }
 479
 480 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 481 {
 482         struct ath_common *common = ath9k_hw_common(ah);
 483         u32 sum;
 484         int i;
 485         u16 eeval;
 486
 487         sum = 0;
 488         for (i = 0; i < 3; i++) {
 489                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 490                 sum += eeval;
 491                 common->macaddr[2 * i] = eeval >> 8;
 492                 common->macaddr[2 * i + 1] = eeval & 0xff;
 493         }
 494         if (sum == 0 || sum == 0xffff * 3)
 495                 return -EADDRNOTAVAIL;
 496
 497         return 0;
 498 }
 499
 500 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 501 {
 502         u32 rxgain_type;
 503
 504         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 505                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 506
 507                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 508                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 509                         ar9280Modes_backoff_13db_rxgain_9280_2,
 510                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 511                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 512                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 513                         ar9280Modes_backoff_23db_rxgain_9280_2,
 514                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 515                 else
 516                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 517                         ar9280Modes_original_rxgain_9280_2,
 518                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 519         } else {
 520                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 521                         ar9280Modes_original_rxgain_9280_2,
 522                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 523         }
 524 }
 525
 526 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 527 {
 528         u32 txgain_type;
 529
 530         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 531                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 532
 533                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 534                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 535                         ar9280Modes_high_power_tx_gain_9280_2,
 536                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 537                 else
 538                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 539                         ar9280Modes_original_tx_gain_9280_2,
 540                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 541         } else {
 542                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 543                 ar9280Modes_original_tx_gain_9280_2,
 544                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 545         }
 546 }
 547
 548 static int ath9k_hw_post_init(struct ath_hw *ah)
 549 {
 550         int ecode;
 551
 552         if (!ath9k_hw_chip_test(ah))
 553                 return -ENODEV;
 554
 555         ecode = ath9k_hw_rf_claim(ah);
 556         if (ecode != 0)
 557                 return ecode;
 558
 559         ecode = ath9k_hw_eeprom_init(ah);
 560         if (ecode != 0)
 561                 return ecode;
 562
 563         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 564                   "Eeprom VER: %d, REV: %d\n",
 565                   ah->eep_ops->get_eeprom_ver(ah),
 566                   ah->eep_ops->get_eeprom_rev(ah));
 567
 568         ecode = ath9k_hw_rfattach(ah);
 569         if (ecode != 0)
 570                 return ecode;
 571
 572         if (!AR_SREV_9100(ah)) {
 573                 ath9k_hw_ani_setup(ah);
 574                 ath9k_hw_ani_init(ah);
 575         }
 576
 577         return 0;
 578 }
 579
 580 static bool ath9k_hw_devid_supported(u16 devid)
 581 {
 582         switch (devid) {
 583         case AR5416_DEVID_PCI:
 584         case AR5416_DEVID_PCIE:
 585         case AR5416_AR9100_DEVID:
 586         case AR9160_DEVID_PCI:
 587         case AR9280_DEVID_PCI:
 588         case AR9280_DEVID_PCIE:
 589         case AR9285_DEVID_PCIE:
 590         case AR5416_DEVID_AR9287_PCI:
 591         case AR5416_DEVID_AR9287_PCIE:
 592                 return true;
 593         default:
 594                 break;
 595         }
 596         return false;
 597 }
 598
 599 static bool ath9k_hw_macversion_supported(u32 macversion)
 600 {
 601         switch (macversion) {
 602         case AR_SREV_VERSION_5416_PCI:
 603         case AR_SREV_VERSION_5416_PCIE:
 604         case AR_SREV_VERSION_9160:
 605         case AR_SREV_VERSION_9100:
 606         case AR_SREV_VERSION_9280:
 607         case AR_SREV_VERSION_9285:
 608         case AR_SREV_VERSION_9287:
 609                 return true;
 610         /* Not yet */
 611         case AR_SREV_VERSION_9271:
 612         default:
 613                 break;
 614         }
 615         return false;
 616 }
 617
 618 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 619 {
 620         if (AR_SREV_9160_10_OR_LATER(ah)) {
 621                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 622                         ah->iq_caldata.calData = &iq_cal_single_sample;
 623                         ah->adcgain_caldata.calData =
 624                                 &adc_gain_cal_single_sample;
 625                         ah->adcdc_caldata.calData =
 626                                 &adc_dc_cal_single_sample;
 627                         ah->adcdc_calinitdata.calData =
 628                                 &adc_init_dc_cal;
 629                 } else {
 630                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 631                         ah->adcgain_caldata.calData =
 632                                 &adc_gain_cal_multi_sample;
 633                         ah->adcdc_caldata.calData =
 634                                 &adc_dc_cal_multi_sample;
 635                         ah->adcdc_calinitdata.calData =
 636                                 &adc_init_dc_cal;
 637                 }
 638                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 639         }
 640 }
 641
 642 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 643 {
 644         if (AR_SREV_9271(ah)) {
 645                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
 646                                ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
 647                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
 648                                ARRAY_SIZE(ar9271Common_9271_1_0), 2);
 649                 return;
 650         }
 651
 652         if (AR_SREV_9287_11_OR_LATER(ah)) {
 653                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 654                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 655                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 656                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 657                 if (ah->config.pcie_clock_req)
 658                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 659                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 660                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 661                 else
 662                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 663                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 664                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 665                                         2);
 666         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 667                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 668                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 669                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 670                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 671
 672                 if (ah->config.pcie_clock_req)
 673                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 674                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 675                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 676                 else
 677                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 678                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 679                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 680                                   2);
 681         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 682
 683
 684                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 685                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 686                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 687                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 688
 689                 if (ah->config.pcie_clock_req) {
 690                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 691                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 692                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 693                 } else {
 694                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 695                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 696                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 697                                   2);
 698                 }
 699         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 700                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 701                                ARRAY_SIZE(ar9285Modes_9285), 6);
 702                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 703                                ARRAY_SIZE(ar9285Common_9285), 2);
 704
 705                 if (ah->config.pcie_clock_req) {
 706                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 707                         ar9285PciePhy_clkreq_off_L1_9285,
 708                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 709                 } else {
 710                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 711                         ar9285PciePhy_clkreq_always_on_L1_9285,
 712                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 713                 }
 714         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 715                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 716                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 717                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 718                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 719
 720                 if (ah->config.pcie_clock_req) {
 721                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 722                                ar9280PciePhy_clkreq_off_L1_9280,
 723                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 724                 } else {
 725                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 726                                ar9280PciePhy_clkreq_always_on_L1_9280,
 727                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 728                 }
 729                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 730                                ar9280Modes_fast_clock_9280_2,
 731                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 732         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 733                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 734                                ARRAY_SIZE(ar9280Modes_9280), 6);
 735                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 736                                ARRAY_SIZE(ar9280Common_9280), 2);
 737         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 738                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 739                                ARRAY_SIZE(ar5416Modes_9160), 6);
 740                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 741                                ARRAY_SIZE(ar5416Common_9160), 2);
 742                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 743                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 744                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 745                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 746                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 747                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 748                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 749                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 750                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 751                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 752                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 753                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 754                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 755                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 756                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 757                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 758                 if (AR_SREV_9160_11(ah)) {
 759                         INIT_INI_ARRAY(&ah->iniAddac,
 760                                        ar5416Addac_91601_1,
 761                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 762                 } else {
 763                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 764                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 765                 }
 766         } else if (AR_SREV_9100_OR_LATER(ah)) {
 767                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 768                                ARRAY_SIZE(ar5416Modes_9100), 6);
 769                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 770                                ARRAY_SIZE(ar5416Common_9100), 2);
 771                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 772                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 773                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 774                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 775                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 776                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 777                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 778                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 779                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 780                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 781                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 782                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 783                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 784                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 785                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 786                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 787                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 788                                ARRAY_SIZE(ar5416Addac_9100), 2);
 789         } else {
 790                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 791                                ARRAY_SIZE(ar5416Modes), 6);
 792                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 793                                ARRAY_SIZE(ar5416Common), 2);
 794                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 795                                ARRAY_SIZE(ar5416Bank0), 2);
 796                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 797                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 798                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 799                                ARRAY_SIZE(ar5416Bank1), 2);
 800                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 801                                ARRAY_SIZE(ar5416Bank2), 2);
 802                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 803                                ARRAY_SIZE(ar5416Bank3), 3);
 804                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 805                                ARRAY_SIZE(ar5416Bank6), 3);
 806                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 807                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 808                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 809                                ARRAY_SIZE(ar5416Bank7), 2);
 810                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 811                                ARRAY_SIZE(ar5416Addac), 2);
 812         }
 813 }
 814
 815 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 816 {
 817         if (AR_SREV_9287_11_OR_LATER(ah))
 818                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 819                 ar9287Modes_rx_gain_9287_1_1,
 820                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 821         else if (AR_SREV_9287_10(ah))
 822                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 823                 ar9287Modes_rx_gain_9287_1_0,
 824                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 825         else if (AR_SREV_9280_20(ah))
 826                 ath9k_hw_init_rxgain_ini(ah);
 827
 828         if (AR_SREV_9287_11_OR_LATER(ah)) {
 829                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 830                 ar9287Modes_tx_gain_9287_1_1,
 831                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 832         } else if (AR_SREV_9287_10(ah)) {
 833                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 834                 ar9287Modes_tx_gain_9287_1_0,
 835                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 836         } else if (AR_SREV_9280_20(ah)) {
 837                 ath9k_hw_init_txgain_ini(ah);
 838         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 839                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 840
 841                 /* txgain table */
 842                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 843                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 844                         ar9285Modes_high_power_tx_gain_9285_1_2,
 845                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 846                 } else {
 847                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 848                         ar9285Modes_original_tx_gain_9285_1_2,
 849                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 850                 }
 851
 852         }
 853 }
 854
 855 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 856 {
 857         u32 i, j;
 858
 859         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 860             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 861
 862                 /* EEPROM Fixup */
 863                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 864                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 865
 866                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 867                                 u32 val = INI_RA(&ah->iniModes, i, j);
 868
 869                                 INI_RA(&ah->iniModes, i, j) =
 870                                         ath9k_hw_ini_fixup(ah,
 871                                                            &ah->eeprom.def,
 872                                                            reg, val);
 873                         }
 874                 }
 875         }
 876 }
 877
 878 int ath9k_hw_init(struct ath_hw *ah)
 879 {
 880         struct ath_common *common = ath9k_hw_common(ah);
 881         int r = 0;
 882
 883         if (!ath9k_hw_devid_supported(ah->hw_version.devid))
 884                 return -EOPNOTSUPP;
 885
 886         ath9k_hw_init_defaults(ah);
 887         ath9k_hw_init_config(ah);
 888
 889         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 890                 ath_print(common, ATH_DBG_FATAL,
 891                           "Couldn't reset chip\n");
 892                 return -EIO;
 893         }
 894
 895         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 896                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 897                 return -EIO;
 898         }
 899
 900         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 901                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 902                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 903                         ah->config.serialize_regmode =
 904                                 SER_REG_MODE_ON;
 905                 } else {
 906                         ah->config.serialize_regmode =
 907                                 SER_REG_MODE_OFF;
 908                 }
 909         }
 910
 911         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 912                 ah->config.serialize_regmode);
 913
 914         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 915                 ath_print(common, ATH_DBG_FATAL,
 916                           "Mac Chip Rev 0x%02x.%x is not supported by "
 917                           "this driver\n", ah->hw_version.macVersion,
 918                           ah->hw_version.macRev);
 919                 return -EOPNOTSUPP;
 920         }
 921
 922         if (AR_SREV_9100(ah)) {
 923                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 924                 ah->supp_cals = IQ_MISMATCH_CAL;
 925                 ah->is_pciexpress = false;
 926         }
 927
 928         if (AR_SREV_9271(ah))
 929                 ah->is_pciexpress = false;
 930
 931         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 932
 933         ath9k_hw_init_cal_settings(ah);
 934
 935         ah->ani_function = ATH9K_ANI_ALL;
 936         if (AR_SREV_9280_10_OR_LATER(ah))
 937                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 938
 939         ath9k_hw_init_mode_regs(ah);
 940
 941         if (ah->is_pciexpress)
 942                 ath9k_hw_configpcipowersave(ah, 0, 0);
 943         else
 944                 ath9k_hw_disablepcie(ah);
 945
 946         /* Support for Japan ch.14 (2484) spread */
 947         if (AR_SREV_9287_11_OR_LATER(ah)) {
 948                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 949                        ar9287Common_normal_cck_fir_coeff_92871_1,
 950                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 951                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 952                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 953                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 954         }
 955
 956         r = ath9k_hw_post_init(ah);
 957         if (r)
 958                 return r;
 959
 960         ath9k_hw_init_mode_gain_regs(ah);
 961         ath9k_hw_fill_cap_info(ah);
 962         ath9k_hw_init_11a_eeprom_fix(ah);
 963
 964         r = ath9k_hw_init_macaddr(ah);
 965         if (r) {
 966                 ath_print(common, ATH_DBG_FATAL,
 967                           "Failed to initialize MAC address\n");
 968                 return r;
 969         }
 970
 971         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 972                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 973         else
 974                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 975
 976         ath9k_init_nfcal_hist_buffer(ah);
 977
 978         return 0;
 979 }
 980
 981 static void ath9k_hw_init_bb(struct ath_hw *ah,
 982                              struct ath9k_channel *chan)
 983 {
 984         u32 synthDelay;
 985
 986         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 987         if (IS_CHAN_B(chan))
 988                 synthDelay = (4 * synthDelay) / 22;
 989         else
 990                 synthDelay /= 10;
 991
 992         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 993
 994         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 995 }
 996
 997 static void ath9k_hw_init_qos(struct ath_hw *ah)
 998 {
 999         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1000         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1001
1002         REG_WRITE(ah, AR_QOS_NO_ACK,
1003                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1004                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1005                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1006
1007         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1008         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1009         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1010         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1011         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1012 }
1013
1014 static void ath9k_hw_init_pll(struct ath_hw *ah,
1015                               struct ath9k_channel *chan)
1016 {
1017         u32 pll;
1018
1019         if (AR_SREV_9100(ah)) {
1020                 if (chan && IS_CHAN_5GHZ(chan))
1021                         pll = 0x1450;
1022                 else
1023                         pll = 0x1458;
1024         } else {
1025                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1026                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1027
1028                         if (chan && IS_CHAN_HALF_RATE(chan))
1029                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1030                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1031                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1032
1033                         if (chan && IS_CHAN_5GHZ(chan)) {
1034                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1035
1036
1037                                 if (AR_SREV_9280_20(ah)) {
1038                                         if (((chan->channel % 20) == 0)
1039                                             || ((chan->channel % 10) == 0))
1040                                                 pll = 0x2850;
1041                                         else
1042                                                 pll = 0x142c;
1043                                 }
1044                         } else {
1045                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1046                         }
1047
1048                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1049
1050                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1051
1052                         if (chan && IS_CHAN_HALF_RATE(chan))
1053                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1054                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1055                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1056
1057                         if (chan && IS_CHAN_5GHZ(chan))
1058                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1059                         else
1060                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1061                 } else {
1062                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1063
1064                         if (chan && IS_CHAN_HALF_RATE(chan))
1065                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1066                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1067                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1068
1069                         if (chan && IS_CHAN_5GHZ(chan))
1070                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1071                         else
1072                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1073                 }
1074         }
1075         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1076
1077         udelay(RTC_PLL_SETTLE_DELAY);
1078
1079         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1080 }
1081
1082 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1083 {
1084         int rx_chainmask, tx_chainmask;
1085
1086         rx_chainmask = ah->rxchainmask;
1087         tx_chainmask = ah->txchainmask;
1088
1089         switch (rx_chainmask) {
1090         case 0x5:
1091                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1092                             AR_PHY_SWAP_ALT_CHAIN);
1093         case 0x3:
1094                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1095                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1096                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1097                         break;
1098                 }
1099         case 0x1:
1100         case 0x2:
1101         case 0x7:
1102                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1103                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1104                 break;
1105         default:
1106                 break;
1107         }
1108
1109         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1110         if (tx_chainmask == 0x5) {
1111                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1112                             AR_PHY_SWAP_ALT_CHAIN);
1113         }
1114         if (AR_SREV_9100(ah))
1115                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1116                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1117 }
1118
1119 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1120                                           enum nl80211_iftype opmode)
1121 {
1122         ah->mask_reg = AR_IMR_TXERR |
1123                 AR_IMR_TXURN |
1124                 AR_IMR_RXERR |
1125                 AR_IMR_RXORN |
1126                 AR_IMR_BCNMISC;
1127
1128         if (ah->config.intr_mitigation)
1129                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1130         else
1131                 ah->mask_reg |= AR_IMR_RXOK;
1132
1133         ah->mask_reg |= AR_IMR_TXOK;
1134
1135         if (opmode == NL80211_IFTYPE_AP)
1136                 ah->mask_reg |= AR_IMR_MIB;
1137
1138         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1139         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1140
1141         if (!AR_SREV_9100(ah)) {
1142                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1143                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1144                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1145         }
1146 }
1147
1148 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1149 {
1150         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1151                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1152                           "bad ack timeout %u\n", us);
1153                 ah->acktimeout = (u32) -1;
1154                 return false;
1155         } else {
1156                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1157                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1158                 ah->acktimeout = us;
1159                 return true;
1160         }
1161 }
1162
1163 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1164 {
1165         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1166                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1167                           "bad cts timeout %u\n", us);
1168                 ah->ctstimeout = (u32) -1;
1169                 return false;
1170         } else {
1171                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1172                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1173                 ah->ctstimeout = us;
1174                 return true;
1175         }
1176 }
1177
1178 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1179 {
1180         if (tu > 0xFFFF) {
1181                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1182                           "bad global tx timeout %u\n", tu);
1183                 ah->globaltxtimeout = (u32) -1;
1184                 return false;
1185         } else {
1186                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1187                 ah->globaltxtimeout = tu;
1188                 return true;
1189         }
1190 }
1191
1192 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1193 {
1194         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1195                   ah->misc_mode);
1196
1197         if (ah->misc_mode != 0)
1198                 REG_WRITE(ah, AR_PCU_MISC,
1199                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1200         if (ah->slottime != (u32) -1)
1201                 ath9k_hw_setslottime(ah, ah->slottime);
1202         if (ah->acktimeout != (u32) -1)
1203                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1204         if (ah->ctstimeout != (u32) -1)
1205                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1206         if (ah->globaltxtimeout != (u32) -1)
1207                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1208 }
1209
1210 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1211 {
1212         return vendorid == ATHEROS_VENDOR_ID ?
1213                 ath9k_hw_devname(devid) : NULL;
1214 }
1215
1216 void ath9k_hw_detach(struct ath_hw *ah)
1217 {
1218         if (!AR_SREV_9100(ah))
1219                 ath9k_hw_ani_disable(ah);
1220
1221         ath9k_hw_rf_free(ah);
1222         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1223         kfree(ah);
1224         ah = NULL;
1225 }
1226
1227 /*******/
1228 /* INI */
1229 /*******/
1230
1231 static void ath9k_hw_override_ini(struct ath_hw *ah,
1232                                   struct ath9k_channel *chan)
1233 {
1234         u32 val;
1235
1236         if (AR_SREV_9271(ah)) {
1237                 /*
1238                  * Enable spectral scan to solution for issues with stuck
1239                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1240                  * AR9271 1.1
1241                  */
1242                 if (AR_SREV_9271_10(ah)) {
1243                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1244                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1245                 }
1246                 else if (AR_SREV_9271_11(ah))
1247                         /*
1248                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1249                          * present on AR9271 1.1
1250                          */
1251                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1252                 return;
1253         }
1254
1255         /*
1256          * Set the RX_ABORT and RX_DIS and clear if off only after
1257          * RXE is set for MAC. This prevents frames with corrupted
1258          * descriptor status.
1259          */
1260         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1261
1262         if (AR_SREV_9280_10_OR_LATER(ah)) {
1263                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1264                                (~AR_PCU_MISC_MODE2_HWWAR1);
1265
1266                 if (AR_SREV_9287_10_OR_LATER(ah))
1267                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1268
1269                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1270         }
1271
1272         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1273             AR_SREV_9280_10_OR_LATER(ah))
1274                 return;
1275         /*
1276          * Disable BB clock gating
1277          * Necessary to avoid issues on AR5416 2.0
1278          */
1279         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1280 }
1281
1282 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1283                               struct ar5416_eeprom_def *pEepData,
1284                               u32 reg, u32 value)
1285 {
1286         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1287         struct ath_common *common = ath9k_hw_common(ah);
1288
1289         switch (ah->hw_version.devid) {
1290         case AR9280_DEVID_PCI:
1291                 if (reg == 0x7894) {
1292                         ath_print(common, ATH_DBG_EEPROM,
1293                                 "ini VAL: %x  EEPROM: %x\n", value,
1294                                 (pBase->version & 0xff));
1295
1296                         if ((pBase->version & 0xff) > 0x0a) {
1297                                 ath_print(common, ATH_DBG_EEPROM,
1298                                           "PWDCLKIND: %d\n",
1299                                           pBase->pwdclkind);
1300                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1301                                 value |= AR_AN_TOP2_PWDCLKIND &
1302                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1303                         } else {
1304                                 ath_print(common, ATH_DBG_EEPROM,
1305                                           "PWDCLKIND Earlier Rev\n");
1306                         }
1307
1308                         ath_print(common, ATH_DBG_EEPROM,
1309                                   "final ini VAL: %x\n", value);
1310                 }
1311                 break;
1312         }
1313
1314         return value;
1315 }
1316
1317 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1318                               struct ar5416_eeprom_def *pEepData,
1319                               u32 reg, u32 value)
1320 {
1321         if (ah->eep_map == EEP_MAP_4KBITS)
1322                 return value;
1323         else
1324                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1325 }
1326
1327 static void ath9k_olc_init(struct ath_hw *ah)
1328 {
1329         u32 i;
1330
1331         if (OLC_FOR_AR9287_10_LATER) {
1332                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1333                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1334                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1335                                 AR9287_AN_TXPC0_TXPCMODE,
1336                                 AR9287_AN_TXPC0_TXPCMODE_S,
1337                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1338                 udelay(100);
1339         } else {
1340                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1341                         ah->originalGain[i] =
1342                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1343                                                 AR_PHY_TX_GAIN);
1344                 ah->PDADCdelta = 0;
1345         }
1346 }
1347
1348 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1349                               struct ath9k_channel *chan)
1350 {
1351         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1352
1353         if (IS_CHAN_B(chan))
1354                 ctl |= CTL_11B;
1355         else if (IS_CHAN_G(chan))
1356                 ctl |= CTL_11G;
1357         else
1358                 ctl |= CTL_11A;
1359
1360         return ctl;
1361 }
1362
1363 static int ath9k_hw_process_ini(struct ath_hw *ah,
1364                                 struct ath9k_channel *chan)
1365 {
1366         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1367         int i, regWrites = 0;
1368         struct ieee80211_channel *channel = chan->chan;
1369         u32 modesIndex, freqIndex;
1370
1371         switch (chan->chanmode) {
1372         case CHANNEL_A:
1373         case CHANNEL_A_HT20:
1374                 modesIndex = 1;
1375                 freqIndex = 1;
1376                 break;
1377         case CHANNEL_A_HT40PLUS:
1378         case CHANNEL_A_HT40MINUS:
1379                 modesIndex = 2;
1380                 freqIndex = 1;
1381                 break;
1382         case CHANNEL_G:
1383         case CHANNEL_G_HT20:
1384         case CHANNEL_B:
1385                 modesIndex = 4;
1386                 freqIndex = 2;
1387                 break;
1388         case CHANNEL_G_HT40PLUS:
1389         case CHANNEL_G_HT40MINUS:
1390                 modesIndex = 3;
1391                 freqIndex = 2;
1392                 break;
1393
1394         default:
1395                 return -EINVAL;
1396         }
1397
1398         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1399         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1400         ah->eep_ops->set_addac(ah, chan);
1401
1402         if (AR_SREV_5416_22_OR_LATER(ah)) {
1403                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1404         } else {
1405                 struct ar5416IniArray temp;
1406                 u32 addacSize =
1407                         sizeof(u32) * ah->iniAddac.ia_rows *
1408                         ah->iniAddac.ia_columns;
1409
1410                 memcpy(ah->addac5416_21,
1411                        ah->iniAddac.ia_array, addacSize);
1412
1413                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1414
1415                 temp.ia_array = ah->addac5416_21;
1416                 temp.ia_columns = ah->iniAddac.ia_columns;
1417                 temp.ia_rows = ah->iniAddac.ia_rows;
1418                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1419         }
1420
1421         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1422
1423         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1424                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1425                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1426
1427                 REG_WRITE(ah, reg, val);
1428
1429                 if (reg >= 0x7800 && reg < 0x78a0
1430                     && ah->config.analog_shiftreg) {
1431                         udelay(100);
1432                 }
1433
1434                 DO_DELAY(regWrites);
1435         }
1436
1437         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1438                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1439
1440         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1441             AR_SREV_9287_10_OR_LATER(ah))
1442                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1443
1444         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1445                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1446                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1447
1448                 REG_WRITE(ah, reg, val);
1449
1450                 if (reg >= 0x7800 && reg < 0x78a0
1451                     && ah->config.analog_shiftreg) {
1452                         udelay(100);
1453                 }
1454
1455                 DO_DELAY(regWrites);
1456         }
1457
1458         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1459
1460         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1461                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1462                                 regWrites);
1463         }
1464
1465         ath9k_hw_override_ini(ah, chan);
1466         ath9k_hw_set_regs(ah, chan);
1467         ath9k_hw_init_chain_masks(ah);
1468
1469         if (OLC_FOR_AR9280_20_LATER)
1470                 ath9k_olc_init(ah);
1471
1472         ah->eep_ops->set_txpower(ah, chan,
1473                                  ath9k_regd_get_ctl(regulatory, chan),
1474                                  channel->max_antenna_gain * 2,
1475                                  channel->max_power * 2,
1476                                  min((u32) MAX_RATE_POWER,
1477                                  (u32) regulatory->power_limit));
1478
1479         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1480                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1481                           "ar5416SetRfRegs failed\n");
1482                 return -EIO;
1483         }
1484
1485         return 0;
1486 }
1487
1488 /****************************************/
1489 /* Reset and Channel Switching Routines */
1490 /****************************************/
1491
1492 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1493 {
1494         u32 rfMode = 0;
1495
1496         if (chan == NULL)
1497                 return;
1498
1499         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1500                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1501
1502         if (!AR_SREV_9280_10_OR_LATER(ah))
1503                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1504                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1505
1506         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1507                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1508
1509         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1510 }
1511
1512 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1513 {
1514         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1515 }
1516
1517 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1518 {
1519         u32 regval;
1520
1521         /*
1522          * set AHB_MODE not to do cacheline prefetches
1523         */
1524         regval = REG_READ(ah, AR_AHB_MODE);
1525         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1526
1527         /*
1528          * let mac dma reads be in 128 byte chunks
1529          */
1530         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1531         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1532
1533         /*
1534          * Restore TX Trigger Level to its pre-reset value.
1535          * The initial value depends on whether aggregation is enabled, and is
1536          * adjusted whenever underruns are detected.
1537          */
1538         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1539
1540         /*
1541          * let mac dma writes be in 128 byte chunks
1542          */
1543         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1544         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1545
1546         /*
1547          * Setup receive FIFO threshold to hold off TX activities
1548          */
1549         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1550
1551         /*
1552          * reduce the number of usable entries in PCU TXBUF to avoid
1553          * wrap around issues.
1554          */
1555         if (AR_SREV_9285(ah)) {
1556                 /* For AR9285 the number of Fifos are reduced to half.
1557                  * So set the usable tx buf size also to half to
1558                  * avoid data/delimiter underruns
1559                  */
1560                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1561                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1562         } else if (!AR_SREV_9271(ah)) {
1563                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1564                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1565         }
1566 }
1567
1568 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1569 {
1570         u32 val;
1571
1572         val = REG_READ(ah, AR_STA_ID1);
1573         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1574         switch (opmode) {
1575         case NL80211_IFTYPE_AP:
1576                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1577                           | AR_STA_ID1_KSRCH_MODE);
1578                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1579                 break;
1580         case NL80211_IFTYPE_ADHOC:
1581         case NL80211_IFTYPE_MESH_POINT:
1582                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1583                           | AR_STA_ID1_KSRCH_MODE);
1584                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1585                 break;
1586         case NL80211_IFTYPE_STATION:
1587         case NL80211_IFTYPE_MONITOR:
1588                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1589                 break;
1590         }
1591 }
1592
1593 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1594                                                  u32 coef_scaled,
1595                                                  u32 *coef_mantissa,
1596                                                  u32 *coef_exponent)
1597 {
1598         u32 coef_exp, coef_man;
1599
1600         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1601                 if ((coef_scaled >> coef_exp) & 0x1)
1602                         break;
1603
1604         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1605
1606         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1607
1608         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1609         *coef_exponent = coef_exp - 16;
1610 }
1611
1612 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1613                                      struct ath9k_channel *chan)
1614 {
1615         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1616         u32 clockMhzScaled = 0x64000000;
1617         struct chan_centers centers;
1618
1619         if (IS_CHAN_HALF_RATE(chan))
1620                 clockMhzScaled = clockMhzScaled >> 1;
1621         else if (IS_CHAN_QUARTER_RATE(chan))
1622                 clockMhzScaled = clockMhzScaled >> 2;
1623
1624         ath9k_hw_get_channel_centers(ah, chan, &centers);
1625         coef_scaled = clockMhzScaled / centers.synth_center;
1626
1627         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1628                                       &ds_coef_exp);
1629
1630         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1631                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1632         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1633                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1634
1635         coef_scaled = (9 * coef_scaled) / 10;
1636
1637         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1638                                       &ds_coef_exp);
1639
1640         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1641                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1642         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1643                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1644 }
1645
1646 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1647 {
1648         u32 rst_flags;
1649         u32 tmpReg;
1650
1651         if (AR_SREV_9100(ah)) {
1652                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1653                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1654                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1655                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1656                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1657         }
1658
1659         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1660                   AR_RTC_FORCE_WAKE_ON_INT);
1661
1662         if (AR_SREV_9100(ah)) {
1663                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1664                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1665         } else {
1666                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1667                 if (tmpReg &
1668                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1669                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1670                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1671                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1672                 } else {
1673                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1674                 }
1675
1676                 rst_flags = AR_RTC_RC_MAC_WARM;
1677                 if (type == ATH9K_RESET_COLD)
1678                         rst_flags |= AR_RTC_RC_MAC_COLD;
1679         }
1680
1681         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1682         udelay(50);
1683
1684         REG_WRITE(ah, AR_RTC_RC, 0);
1685         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1686                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1687                           "RTC stuck in MAC reset\n");
1688                 return false;
1689         }
1690
1691         if (!AR_SREV_9100(ah))
1692                 REG_WRITE(ah, AR_RC, 0);
1693
1694         ath9k_hw_init_pll(ah, NULL);
1695
1696         if (AR_SREV_9100(ah))
1697                 udelay(50);
1698
1699         return true;
1700 }
1701
1702 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1703 {
1704         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1705                   AR_RTC_FORCE_WAKE_ON_INT);
1706
1707         if (!AR_SREV_9100(ah))
1708                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1709
1710         REG_WRITE(ah, AR_RTC_RESET, 0);
1711         udelay(2);
1712
1713         if (!AR_SREV_9100(ah))
1714                 REG_WRITE(ah, AR_RC, 0);
1715
1716         REG_WRITE(ah, AR_RTC_RESET, 1);
1717
1718         if (!ath9k_hw_wait(ah,
1719                            AR_RTC_STATUS,
1720                            AR_RTC_STATUS_M,
1721                            AR_RTC_STATUS_ON,
1722                            AH_WAIT_TIMEOUT)) {
1723                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1724                           "RTC not waking up\n");
1725                 return false;
1726         }
1727
1728         ath9k_hw_read_revisions(ah);
1729
1730         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1731 }
1732
1733 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1734 {
1735         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1736                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1737
1738         switch (type) {
1739         case ATH9K_RESET_POWER_ON:
1740                 return ath9k_hw_set_reset_power_on(ah);
1741         case ATH9K_RESET_WARM:
1742         case ATH9K_RESET_COLD:
1743                 return ath9k_hw_set_reset(ah, type);
1744         default:
1745                 return false;
1746         }
1747 }
1748
1749 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1750 {
1751         u32 phymode;
1752         u32 enableDacFifo = 0;
1753
1754         if (AR_SREV_9285_10_OR_LATER(ah))
1755                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1756                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1757
1758         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1759                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1760
1761         if (IS_CHAN_HT40(chan)) {
1762                 phymode |= AR_PHY_FC_DYN2040_EN;
1763
1764                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1765                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1766                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1767
1768         }
1769         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1770
1771         ath9k_hw_set11nmac2040(ah);
1772
1773         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1774         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1775 }
1776
1777 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1778                                 struct ath9k_channel *chan)
1779 {
1780         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1781                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1782                         return false;
1783         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1784                 return false;
1785
1786         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1787                 return false;
1788
1789         ah->chip_fullsleep = false;
1790         ath9k_hw_init_pll(ah, chan);
1791         ath9k_hw_set_rfmode(ah, chan);
1792
1793         return true;
1794 }
1795
1796 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1797                                     struct ath9k_channel *chan)
1798 {
1799         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1800         struct ath_common *common = ath9k_hw_common(ah);
1801         struct ieee80211_channel *channel = chan->chan;
1802         u32 synthDelay, qnum;
1803
1804         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1805                 if (ath9k_hw_numtxpending(ah, qnum)) {
1806                         ath_print(common, ATH_DBG_QUEUE,
1807                                   "Transmit frames pending on "
1808                                   "queue %d\n", qnum);
1809                         return false;
1810                 }
1811         }
1812
1813         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1814         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1815                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1816                 ath_print(common, ATH_DBG_FATAL,
1817                           "Could not kill baseband RX\n");
1818                 return false;
1819         }
1820
1821         ath9k_hw_set_regs(ah, chan);
1822
1823         if (AR_SREV_9280_10_OR_LATER(ah)) {
1824                 ath9k_hw_ar9280_set_channel(ah, chan);
1825         } else {
1826                 if (!(ath9k_hw_set_channel(ah, chan))) {
1827                         ath_print(common, ATH_DBG_FATAL,
1828                                   "Failed to set channel\n");
1829                         return false;
1830                 }
1831         }
1832
1833         ah->eep_ops->set_txpower(ah, chan,
1834                              ath9k_regd_get_ctl(regulatory, chan),
1835                              channel->max_antenna_gain * 2,
1836                              channel->max_power * 2,
1837                              min((u32) MAX_RATE_POWER,
1838                              (u32) regulatory->power_limit));
1839
1840         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1841         if (IS_CHAN_B(chan))
1842                 synthDelay = (4 * synthDelay) / 22;
1843         else
1844                 synthDelay /= 10;
1845
1846         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1847
1848         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1849
1850         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1851                 ath9k_hw_set_delta_slope(ah, chan);
1852
1853         if (AR_SREV_9280_10_OR_LATER(ah))
1854                 ath9k_hw_9280_spur_mitigate(ah, chan);
1855         else
1856                 ath9k_hw_spur_mitigate(ah, chan);
1857
1858         if (!chan->oneTimeCalsDone)
1859                 chan->oneTimeCalsDone = true;
1860
1861         return true;
1862 }
1863
1864 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1865 {
1866         int bb_spur = AR_NO_SPUR;
1867         int freq;
1868         int bin, cur_bin;
1869         int bb_spur_off, spur_subchannel_sd;
1870         int spur_freq_sd;
1871         int spur_delta_phase;
1872         int denominator;
1873         int upper, lower, cur_vit_mask;
1874         int tmp, newVal;
1875         int i;
1876         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1877                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1878         };
1879         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1880                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1881         };
1882         int inc[4] = { 0, 100, 0, 0 };
1883         struct chan_centers centers;
1884
1885         int8_t mask_m[123];
1886         int8_t mask_p[123];
1887         int8_t mask_amt;
1888         int tmp_mask;
1889         int cur_bb_spur;
1890         bool is2GHz = IS_CHAN_2GHZ(chan);
1891
1892         memset(&mask_m, 0, sizeof(int8_t) * 123);
1893         memset(&mask_p, 0, sizeof(int8_t) * 123);
1894
1895         ath9k_hw_get_channel_centers(ah, chan, &centers);
1896         freq = centers.synth_center;
1897
1898         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1899         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1900                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1901
1902                 if (is2GHz)
1903                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1904                 else
1905                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1906
1907                 if (AR_NO_SPUR == cur_bb_spur)
1908                         break;
1909                 cur_bb_spur = cur_bb_spur - freq;
1910
1911                 if (IS_CHAN_HT40(chan)) {
1912                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1913                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1914                                 bb_spur = cur_bb_spur;
1915                                 break;
1916                         }
1917                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1918                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1919                         bb_spur = cur_bb_spur;
1920                         break;
1921                 }
1922         }
1923
1924         if (AR_NO_SPUR == bb_spur) {
1925                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1926                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1927                 return;
1928         } else {
1929                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1930                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1931         }
1932
1933         bin = bb_spur * 320;
1934
1935         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1936
1937         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1938                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1939                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1940                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1941         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1942
1943         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1944                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1945                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1946                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1947                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1948         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1949
1950         if (IS_CHAN_HT40(chan)) {
1951                 if (bb_spur < 0) {
1952                         spur_subchannel_sd = 1;
1953                         bb_spur_off = bb_spur + 10;
1954                 } else {
1955                         spur_subchannel_sd = 0;
1956                         bb_spur_off = bb_spur - 10;
1957                 }
1958         } else {
1959                 spur_subchannel_sd = 0;
1960                 bb_spur_off = bb_spur;
1961         }
1962
1963         if (IS_CHAN_HT40(chan))
1964                 spur_delta_phase =
1965                         ((bb_spur * 262144) /
1966                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1967         else
1968                 spur_delta_phase =
1969                         ((bb_spur * 524288) /
1970                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1971
1972         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1973         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1974
1975         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1976                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1977                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1978         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1979
1980         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1981         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1982
1983         cur_bin = -6000;
1984         upper = bin + 100;
1985         lower = bin - 100;
1986
1987         for (i = 0; i < 4; i++) {
1988                 int pilot_mask = 0;
1989                 int chan_mask = 0;
1990                 int bp = 0;
1991                 for (bp = 0; bp < 30; bp++) {
1992                         if ((cur_bin > lower) && (cur_bin < upper)) {
1993                                 pilot_mask = pilot_mask | 0x1 << bp;
1994                                 chan_mask = chan_mask | 0x1 << bp;
1995                         }
1996                         cur_bin += 100;
1997                 }
1998                 cur_bin += inc[i];
1999                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2000                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2001         }
2002
2003         cur_vit_mask = 6100;
2004         upper = bin + 120;
2005         lower = bin - 120;
2006
2007         for (i = 0; i < 123; i++) {
2008                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2009
2010                         /* workaround for gcc bug #37014 */
2011                         volatile int tmp_v = abs(cur_vit_mask - bin);
2012
2013                         if (tmp_v < 75)
2014                                 mask_amt = 1;
2015                         else
2016                                 mask_amt = 0;
2017                         if (cur_vit_mask < 0)
2018                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2019                         else
2020                                 mask_p[cur_vit_mask / 100] = mask_amt;
2021                 }
2022                 cur_vit_mask -= 100;
2023         }
2024
2025         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2026                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2027                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2028                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2029                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2030                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2031                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2032                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2033         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2034         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2035
2036         tmp_mask = (mask_m[31] << 28)
2037                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2038                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2039                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2040                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2041                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2042                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2043                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2044         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2045         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2046
2047         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2048                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2049                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2050                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2051                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2052                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2053                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2054                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2055         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2056         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2057
2058         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2059                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2060                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2061                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2062                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2063                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2064                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2065                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2066         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2067         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2068
2069         tmp_mask = (mask_p[15] << 28)
2070                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2071                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2072                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2073                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2074                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2075                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2076                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2077         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2078         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2079
2080         tmp_mask = (mask_p[30] << 28)
2081                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2082                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2083                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2084                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2085                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2086                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2087                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2088         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2089         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2090
2091         tmp_mask = (mask_p[45] << 28)
2092                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2093                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2094                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2095                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2096                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2097                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2098                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2099         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2100         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2101
2102         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2103                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2104                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2105                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2106                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2107                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2108                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2109                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2110         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2111         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2112 }
2113
2114 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2115 {
2116         int bb_spur = AR_NO_SPUR;
2117         int bin, cur_bin;
2118         int spur_freq_sd;
2119         int spur_delta_phase;
2120         int denominator;
2121         int upper, lower, cur_vit_mask;
2122         int tmp, new;
2123         int i;
2124         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2125                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2126         };
2127         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2128                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2129         };
2130         int inc[4] = { 0, 100, 0, 0 };
2131
2132         int8_t mask_m[123];
2133         int8_t mask_p[123];
2134         int8_t mask_amt;
2135         int tmp_mask;
2136         int cur_bb_spur;
2137         bool is2GHz = IS_CHAN_2GHZ(chan);
2138
2139         memset(&mask_m, 0, sizeof(int8_t) * 123);
2140         memset(&mask_p, 0, sizeof(int8_t) * 123);
2141
2142         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2143                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2144                 if (AR_NO_SPUR == cur_bb_spur)
2145                         break;
2146                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2147                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2148                         bb_spur = cur_bb_spur;
2149                         break;
2150                 }
2151         }
2152
2153         if (AR_NO_SPUR == bb_spur)
2154                 return;
2155
2156         bin = bb_spur * 32;
2157
2158         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2159         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2160                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2161                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2162                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2163
2164         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2165
2166         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2167                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2168                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2169                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2170                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2171         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2172
2173         spur_delta_phase = ((bb_spur * 524288) / 100) &
2174                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2175
2176         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2177         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2178
2179         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2180                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2181                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2182         REG_WRITE(ah, AR_PHY_TIMING11, new);
2183
2184         cur_bin = -6000;
2185         upper = bin + 100;
2186         lower = bin - 100;
2187
2188         for (i = 0; i < 4; i++) {
2189                 int pilot_mask = 0;
2190                 int chan_mask = 0;
2191                 int bp = 0;
2192                 for (bp = 0; bp < 30; bp++) {
2193                         if ((cur_bin > lower) && (cur_bin < upper)) {
2194                                 pilot_mask = pilot_mask | 0x1 << bp;
2195                                 chan_mask = chan_mask | 0x1 << bp;
2196                         }
2197                         cur_bin += 100;
2198                 }
2199                 cur_bin += inc[i];
2200                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2201                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2202         }
2203
2204         cur_vit_mask = 6100;
2205         upper = bin + 120;
2206         lower = bin - 120;
2207
2208         for (i = 0; i < 123; i++) {
2209                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2210
2211                         /* workaround for gcc bug #37014 */
2212                         volatile int tmp_v = abs(cur_vit_mask - bin);
2213
2214                         if (tmp_v < 75)
2215                                 mask_amt = 1;
2216                         else
2217                                 mask_amt = 0;
2218                         if (cur_vit_mask < 0)
2219                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2220                         else
2221                                 mask_p[cur_vit_mask / 100] = mask_amt;
2222                 }
2223                 cur_vit_mask -= 100;
2224         }
2225
2226         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2227                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2228                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2229                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2230                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2231                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2232                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2233                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2234         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2235         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2236
2237         tmp_mask = (mask_m[31] << 28)
2238                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2239                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2240                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2241                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2242                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2243                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2244                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2245         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2246         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2247
2248         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2249                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2250                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2251                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2252                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2253                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2254                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2255                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2256         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2257         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2258
2259         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2260                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2261                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2262                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2263                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2264                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2265                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2266                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2267         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2268         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2269
2270         tmp_mask = (mask_p[15] << 28)
2271                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2272                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2273                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2274                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2275                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2276                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2277                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2278         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2279         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2280
2281         tmp_mask = (mask_p[30] << 28)
2282                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2283                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2284                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2285                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2286                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2287                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2288                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2289         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2290         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2291
2292         tmp_mask = (mask_p[45] << 28)
2293                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2294                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2295                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2296                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2297                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2298                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2299                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2300         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2301         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2302
2303         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2304                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2305                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2306                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2307                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2308                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2309                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2310                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2311         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2312         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2313 }
2314
2315 static void ath9k_enable_rfkill(struct ath_hw *ah)
2316 {
2317         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2318                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2319
2320         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2321                     AR_GPIO_INPUT_MUX2_RFSILENT);
2322
2323         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2324         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2325 }
2326
2327 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2328                     bool bChannelChange)
2329 {
2330         struct ath_common *common = ath9k_hw_common(ah);
2331         u32 saveLedState;
2332         struct ath9k_channel *curchan = ah->curchan;
2333         u32 saveDefAntenna;
2334         u32 macStaId1;
2335         u64 tsf = 0;
2336         int i, rx_chainmask, r;
2337
2338         ah->txchainmask = common->tx_chainmask;
2339         ah->rxchainmask = common->rx_chainmask;
2340
2341         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2342                 return -EIO;
2343
2344         if (curchan && !ah->chip_fullsleep)
2345                 ath9k_hw_getnf(ah, curchan);
2346
2347         if (bChannelChange &&
2348             (ah->chip_fullsleep != true) &&
2349             (ah->curchan != NULL) &&
2350             (chan->channel != ah->curchan->channel) &&
2351             ((chan->channelFlags & CHANNEL_ALL) ==
2352              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2353              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2354              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2355
2356                 if (ath9k_hw_channel_change(ah, chan)) {
2357                         ath9k_hw_loadnf(ah, ah->curchan);
2358                         ath9k_hw_start_nfcal(ah);
2359                         return 0;
2360                 }
2361         }
2362
2363         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2364         if (saveDefAntenna == 0)
2365                 saveDefAntenna = 1;
2366
2367         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2368
2369         /* For chips on which RTC reset is done, save TSF before it gets cleared */
2370         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2371                 tsf = ath9k_hw_gettsf64(ah);
2372
2373         saveLedState = REG_READ(ah, AR_CFG_LED) &
2374                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2375                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2376
2377         ath9k_hw_mark_phy_inactive(ah);
2378
2379         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2380                 REG_WRITE(ah,
2381                           AR9271_RESET_POWER_DOWN_CONTROL,
2382                           AR9271_RADIO_RF_RST);
2383                 udelay(50);
2384         }
2385
2386         if (!ath9k_hw_chip_reset(ah, chan)) {
2387                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2388                 return -EINVAL;
2389         }
2390
2391         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2392                 ah->htc_reset_init = false;
2393                 REG_WRITE(ah,
2394                           AR9271_RESET_POWER_DOWN_CONTROL,
2395                           AR9271_GATE_MAC_CTL);
2396                 udelay(50);
2397         }
2398
2399         /* Restore TSF */
2400         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2401                 ath9k_hw_settsf64(ah, tsf);
2402
2403         if (AR_SREV_9280_10_OR_LATER(ah))
2404                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2405
2406         if (AR_SREV_9287_12_OR_LATER(ah)) {
2407                 /* Enable ASYNC FIFO */
2408                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2409                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2410                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2411                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2412                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2413                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2414                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2415         }
2416         r = ath9k_hw_process_ini(ah, chan);
2417         if (r)
2418                 return r;
2419
2420         /* Setup MFP options for CCMP */
2421         if (AR_SREV_9280_20_OR_LATER(ah)) {
2422                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2423                  * frames when constructing CCMP AAD. */
2424                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2425                               0xc7ff);
2426                 ah->sw_mgmt_crypto = false;
2427         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2428                 /* Disable hardware crypto for management frames */
2429                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2430                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2431                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2432                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2433                 ah->sw_mgmt_crypto = true;
2434         } else
2435                 ah->sw_mgmt_crypto = true;
2436
2437         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2438                 ath9k_hw_set_delta_slope(ah, chan);
2439
2440         if (AR_SREV_9280_10_OR_LATER(ah))
2441                 ath9k_hw_9280_spur_mitigate(ah, chan);
2442         else
2443                 ath9k_hw_spur_mitigate(ah, chan);
2444
2445         ah->eep_ops->set_board_values(ah, chan);
2446
2447         ath9k_hw_decrease_chain_power(ah, chan);
2448
2449         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2450         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2451                   | macStaId1
2452                   | AR_STA_ID1_RTS_USE_DEF
2453                   | (ah->config.
2454                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2455                   | ah->sta_id1_defaults);
2456         ath9k_hw_set_operating_mode(ah, ah->opmode);
2457
2458         ath_hw_setbssidmask(common);
2459
2460         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2461
2462         ath9k_hw_write_associd(ah);
2463
2464         REG_WRITE(ah, AR_ISR, ~0);
2465
2466         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2467
2468         if (AR_SREV_9280_10_OR_LATER(ah))
2469                 ath9k_hw_ar9280_set_channel(ah, chan);
2470         else
2471                 if (!(ath9k_hw_set_channel(ah, chan)))
2472                         return -EIO;
2473
2474         for (i = 0; i < AR_NUM_DCU; i++)
2475                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2476
2477         ah->intr_txqs = 0;
2478         for (i = 0; i < ah->caps.total_queues; i++)
2479                 ath9k_hw_resettxqueue(ah, i);
2480
2481         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2482         ath9k_hw_init_qos(ah);
2483
2484         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2485                 ath9k_enable_rfkill(ah);
2486
2487         ath9k_hw_init_user_settings(ah);
2488
2489         if (AR_SREV_9287_12_OR_LATER(ah)) {
2490                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2491                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2492                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2493                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2494                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2495                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2496
2497                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2498                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2499
2500                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2501                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2502                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2503                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2504         }
2505         if (AR_SREV_9287_12_OR_LATER(ah)) {
2506                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2507                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2508         }
2509
2510         REG_WRITE(ah, AR_STA_ID1,
2511                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2512
2513         ath9k_hw_set_dma(ah);
2514
2515         REG_WRITE(ah, AR_OBS, 8);
2516
2517         if (ah->config.intr_mitigation) {
2518                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2519                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2520         }
2521
2522         ath9k_hw_init_bb(ah, chan);
2523
2524         if (!ath9k_hw_init_cal(ah, chan))
2525                 return -EIO;
2526
2527         rx_chainmask = ah->rxchainmask;
2528         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2529                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2530                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2531         }
2532
2533         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2534
2535         /*
2536          * For big endian systems turn on swapping for descriptors
2537          */
2538         if (AR_SREV_9100(ah)) {
2539                 u32 mask;
2540                 mask = REG_READ(ah, AR_CFG);
2541                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2542                         ath_print(common, ATH_DBG_RESET,
2543                                 "CFG Byte Swap Set 0x%x\n", mask);
2544                 } else {
2545                         mask =
2546                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2547                         REG_WRITE(ah, AR_CFG, mask);
2548                         ath_print(common, ATH_DBG_RESET,
2549                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2550                 }
2551         } else {
2552                 /* Configure AR9271 target WLAN */
2553                 if (AR_SREV_9271(ah))
2554                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2555 #ifdef __BIG_ENDIAN
2556                 else
2557                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2558 #endif
2559         }
2560
2561         if (ah->btcoex_hw.enabled)
2562                 ath9k_hw_btcoex_enable(ah);
2563
2564         return 0;
2565 }
2566
2567 /************************/
2568 /* Key Cache Management */
2569 /************************/
2570
2571 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2572 {
2573         u32 keyType;
2574
2575         if (entry >= ah->caps.keycache_size) {
2576                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2577                           "keychache entry %u out of range\n", entry);
2578                 return false;
2579         }
2580
2581         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2582
2583         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2584         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2585         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2586         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2587         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2588         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2589         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2590         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2591
2592         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2593                 u16 micentry = entry + 64;
2594
2595                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2596                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2597                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2598                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2599
2600         }
2601
2602         return true;
2603 }
2604
2605 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2606 {
2607         u32 macHi, macLo;
2608
2609         if (entry >= ah->caps.keycache_size) {
2610                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2611                           "keychache entry %u out of range\n", entry);
2612                 return false;
2613         }
2614
2615         if (mac != NULL) {
2616                 macHi = (mac[5] << 8) | mac[4];
2617                 macLo = (mac[3] << 24) |
2618                         (mac[2] << 16) |
2619                         (mac[1] << 8) |
2620                         mac[0];
2621                 macLo >>= 1;
2622                 macLo |= (macHi & 1) << 31;
2623                 macHi >>= 1;
2624         } else {
2625                 macLo = macHi = 0;
2626         }
2627         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2628         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2629
2630         return true;
2631 }
2632
2633 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2634                                  const struct ath9k_keyval *k,
2635                                  const u8 *mac)
2636 {
2637         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2638         struct ath_common *common = ath9k_hw_common(ah);
2639         u32 key0, key1, key2, key3, key4;
2640         u32 keyType;
2641
2642         if (entry >= pCap->keycache_size) {
2643                 ath_print(common, ATH_DBG_FATAL,
2644                           "keycache entry %u out of range\n", entry);
2645                 return false;
2646         }
2647
2648         switch (k->kv_type) {
2649         case ATH9K_CIPHER_AES_OCB:
2650                 keyType = AR_KEYTABLE_TYPE_AES;
2651                 break;
2652         case ATH9K_CIPHER_AES_CCM:
2653                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2654                         ath_print(common, ATH_DBG_ANY,
2655                                   "AES-CCM not supported by mac rev 0x%x\n",
2656                                   ah->hw_version.macRev);
2657                         return false;
2658                 }
2659                 keyType = AR_KEYTABLE_TYPE_CCM;
2660                 break;
2661         case ATH9K_CIPHER_TKIP:
2662                 keyType = AR_KEYTABLE_TYPE_TKIP;
2663                 if (ATH9K_IS_MIC_ENABLED(ah)
2664                     && entry + 64 >= pCap->keycache_size) {
2665                         ath_print(common, ATH_DBG_ANY,
2666                                   "entry %u inappropriate for TKIP\n", entry);
2667                         return false;
2668                 }
2669                 break;
2670         case ATH9K_CIPHER_WEP:
2671                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2672                         ath_print(common, ATH_DBG_ANY,
2673                                   "WEP key length %u too small\n", k->kv_len);
2674                         return false;
2675                 }
2676                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2677                         keyType = AR_KEYTABLE_TYPE_40;
2678                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2679                         keyType = AR_KEYTABLE_TYPE_104;
2680                 else
2681                         keyType = AR_KEYTABLE_TYPE_128;
2682                 break;
2683         case ATH9K_CIPHER_CLR:
2684                 keyType = AR_KEYTABLE_TYPE_CLR;
2685                 break;
2686         default:
2687                 ath_print(common, ATH_DBG_FATAL,
2688                           "cipher %u not supported\n", k->kv_type);
2689                 return false;
2690         }
2691
2692         key0 = get_unaligned_le32(k->kv_val + 0);
2693         key1 = get_unaligned_le16(k->kv_val + 4);
2694         key2 = get_unaligned_le32(k->kv_val + 6);
2695         key3 = get_unaligned_le16(k->kv_val + 10);
2696         key4 = get_unaligned_le32(k->kv_val + 12);
2697         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2698                 key4 &= 0xff;
2699
2700         /*
2701          * Note: Key cache registers access special memory area that requires
2702          * two 32-bit writes to actually update the values in the internal
2703          * memory. Consequently, the exact order and pairs used here must be
2704          * maintained.
2705          */
2706
2707         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2708                 u16 micentry = entry + 64;
2709
2710                 /*
2711                  * Write inverted key[47:0] first to avoid Michael MIC errors
2712                  * on frames that could be sent or received at the same time.
2713                  * The correct key will be written in the end once everything
2714                  * else is ready.
2715                  */
2716                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2717                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2718
2719                 /* Write key[95:48] */
2720                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2721                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2722
2723                 /* Write key[127:96] and key type */
2724                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2725                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2726
2727                 /* Write MAC address for the entry */
2728                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2729
2730                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2731                         /*
2732                          * TKIP uses two key cache entries:
2733                          * Michael MIC TX/RX keys in the same key cache entry
2734                          * (idx = main index + 64):
2735                          * key0 [31:0] = RX key [31:0]
2736                          * key1 [15:0] = TX key [31:16]
2737                          * key1 [31:16] = reserved
2738                          * key2 [31:0] = RX key [63:32]
2739                          * key3 [15:0] = TX key [15:0]
2740                          * key3 [31:16] = reserved
2741                          * key4 [31:0] = TX key [63:32]
2742                          */
2743                         u32 mic0, mic1, mic2, mic3, mic4;
2744
2745                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2746                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2747                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2748                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2749                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2750
2751                         /* Write RX[31:0] and TX[31:16] */
2752                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2753                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2754
2755                         /* Write RX[63:32] and TX[15:0] */
2756                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2757                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2758
2759                         /* Write TX[63:32] and keyType(reserved) */
2760                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2761                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2762                                   AR_KEYTABLE_TYPE_CLR);
2763
2764                 } else {
2765                         /*
2766                          * TKIP uses four key cache entries (two for group
2767                          * keys):
2768                          * Michael MIC TX/RX keys are in different key cache
2769                          * entries (idx = main index + 64 for TX and
2770                          * main index + 32 + 96 for RX):
2771                          * key0 [31:0] = TX/RX MIC key [31:0]
2772                          * key1 [31:0] = reserved
2773                          * key2 [31:0] = TX/RX MIC key [63:32]
2774                          * key3 [31:0] = reserved
2775                          * key4 [31:0] = reserved
2776                          *
2777                          * Upper layer code will call this function separately
2778                          * for TX and RX keys when these registers offsets are
2779                          * used.
2780                          */
2781                         u32 mic0, mic2;
2782
2783                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2784                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2785
2786                         /* Write MIC key[31:0] */
2787                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2788                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2789
2790                         /* Write MIC key[63:32] */
2791                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2792                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2793
2794                         /* Write TX[63:32] and keyType(reserved) */
2795                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2796                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2797                                   AR_KEYTABLE_TYPE_CLR);
2798                 }
2799
2800                 /* MAC address registers are reserved for the MIC entry */
2801                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2802                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2803
2804                 /*
2805                  * Write the correct (un-inverted) key[47:0] last to enable
2806                  * TKIP now that all other registers are set with correct
2807                  * values.
2808                  */
2809                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2810                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2811         } else {
2812                 /* Write key[47:0] */
2813                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2814                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2815
2816                 /* Write key[95:48] */
2817                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2818                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2819
2820                 /* Write key[127:96] and key type */
2821                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2822                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2823
2824                 /* Write MAC address for the entry */
2825                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2826         }
2827
2828         return true;
2829 }
2830
2831 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2832 {
2833         if (entry < ah->caps.keycache_size) {
2834                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2835                 if (val & AR_KEYTABLE_VALID)
2836                         return true;
2837         }
2838         return false;
2839 }
2840
2841 /******************************/
2842 /* Power Management (Chipset) */
2843 /******************************/
2844
2845 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2846 {
2847         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2848         if (setChip) {
2849                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2850                             AR_RTC_FORCE_WAKE_EN);
2851                 if (!AR_SREV_9100(ah))
2852                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2853
2854                 if(!AR_SREV_5416(ah))
2855                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2856                                     AR_RTC_RESET_EN);
2857         }
2858 }
2859
2860 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2861 {
2862         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2863         if (setChip) {
2864                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2865
2866                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2867                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2868                                   AR_RTC_FORCE_WAKE_ON_INT);
2869                 } else {
2870                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2871                                     AR_RTC_FORCE_WAKE_EN);
2872                 }
2873         }
2874 }
2875
2876 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2877 {
2878         u32 val;
2879         int i;
2880
2881         if (setChip) {
2882                 if ((REG_READ(ah, AR_RTC_STATUS) &
2883                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2884                         if (ath9k_hw_set_reset_reg(ah,
2885                                            ATH9K_RESET_POWER_ON) != true) {
2886                                 return false;
2887                         }
2888                 }
2889                 if (AR_SREV_9100(ah))
2890                         REG_SET_BIT(ah, AR_RTC_RESET,
2891                                     AR_RTC_RESET_EN);
2892
2893                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2894                             AR_RTC_FORCE_WAKE_EN);
2895                 udelay(50);
2896
2897                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2898                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2899                         if (val == AR_RTC_STATUS_ON)
2900                                 break;
2901                         udelay(50);
2902                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2903                                     AR_RTC_FORCE_WAKE_EN);
2904                 }
2905                 if (i == 0) {
2906                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2907                                   "Failed to wakeup in %uus\n",
2908                                   POWER_UP_TIME / 20);
2909                         return false;
2910                 }
2911         }
2912
2913         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2914
2915         return true;
2916 }
2917
2918 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2919 {
2920         struct ath_common *common = ath9k_hw_common(ah);
2921         int status = true, setChip = true;
2922         static const char *modes[] = {
2923                 "AWAKE",
2924                 "FULL-SLEEP",
2925                 "NETWORK SLEEP",
2926                 "UNDEFINED"
2927         };
2928
2929         if (ah->power_mode == mode)
2930                 return status;
2931
2932         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2933                   modes[ah->power_mode], modes[mode]);
2934
2935         switch (mode) {
2936         case ATH9K_PM_AWAKE:
2937                 status = ath9k_hw_set_power_awake(ah, setChip);
2938                 break;
2939         case ATH9K_PM_FULL_SLEEP:
2940                 ath9k_set_power_sleep(ah, setChip);
2941                 ah->chip_fullsleep = true;
2942                 break;
2943         case ATH9K_PM_NETWORK_SLEEP:
2944                 ath9k_set_power_network_sleep(ah, setChip);
2945                 break;
2946         default:
2947                 ath_print(common, ATH_DBG_FATAL,
2948                           "Unknown power mode %u\n", mode);
2949                 return false;
2950         }
2951         ah->power_mode = mode;
2952
2953         return status;
2954 }
2955
2956 /*
2957  * Helper for ASPM support.
2958  *
2959  * Disable PLL when in L0s as well as receiver clock when in L1.
2960  * This power saving option must be enabled through the SerDes.
2961  *
2962  * Programming the SerDes must go through the same 288 bit serial shift
2963  * register as the other analog registers.  Hence the 9 writes.
2964  */
2965 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2966 {
2967         u8 i;
2968         u32 val;
2969
2970         if (ah->is_pciexpress != true)
2971                 return;
2972
2973         /* Do not touch SerDes registers */
2974         if (ah->config.pcie_powersave_enable == 2)
2975                 return;
2976
2977         /* Nothing to do on restore for 11N */
2978         if (!restore) {
2979                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2980                         /*
2981                          * AR9280 2.0 or later chips use SerDes values from the
2982                          * initvals.h initialized depending on chipset during
2983                          * ath9k_hw_init()
2984                          */
2985                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2986                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2987                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2988                         }
2989                 } else if (AR_SREV_9280(ah) &&
2990                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2991                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2992                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2993
2994                         /* RX shut off when elecidle is asserted */
2995                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2996                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2997                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2998
2999                         /* Shut off CLKREQ active in L1 */
3000                         if (ah->config.pcie_clock_req)
3001                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3002                         else
3003                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3004
3005                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3006                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3007                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3008
3009                         /* Load the new settings */
3010                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3011
3012                 } else {
3013                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3014                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3015
3016                         /* RX shut off when elecidle is asserted */
3017                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3018                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3019                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3020
3021                         /*
3022                          * Ignore ah->ah_config.pcie_clock_req setting for
3023                          * pre-AR9280 11n
3024                          */
3025                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3026
3027                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3028                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3029                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3030
3031                         /* Load the new settings */
3032                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3033                 }
3034
3035                 udelay(1000);
3036
3037                 /* set bit 19 to allow forcing of pcie core into L1 state */
3038                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3039
3040                 /* Several PCIe massages to ensure proper behaviour */
3041                 if (ah->config.pcie_waen) {
3042                         val = ah->config.pcie_waen;
3043                         if (!power_off)
3044                                 val &= (~AR_WA_D3_L1_DISABLE);
3045                 } else {
3046                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3047                             AR_SREV_9287(ah)) {
3048                                 val = AR9285_WA_DEFAULT;
3049                                 if (!power_off)
3050                                         val &= (~AR_WA_D3_L1_DISABLE);
3051                         } else if (AR_SREV_9280(ah)) {
3052                                 /*
3053                                  * On AR9280 chips bit 22 of 0x4004 needs to be
3054                                  * set otherwise card may disappear.
3055                                  */
3056                                 val = AR9280_WA_DEFAULT;
3057                                 if (!power_off)
3058                                         val &= (~AR_WA_D3_L1_DISABLE);
3059                         } else
3060                                 val = AR_WA_DEFAULT;
3061                 }
3062
3063                 REG_WRITE(ah, AR_WA, val);
3064         }
3065
3066         if (power_off) {
3067                 /*
3068                  * Set PCIe workaround bits
3069                  * bit 14 in WA register (disable L1) should only
3070                  * be set when device enters D3 and be cleared
3071                  * when device comes back to D0.
3072                  */
3073                 if (ah->config.pcie_waen) {
3074                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3075                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3076                 } else {
3077                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3078                               AR_SREV_9287(ah)) &&
3079                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3080                             (AR_SREV_9280(ah) &&
3081                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3082                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3083                         }
3084                 }
3085         }
3086 }
3087
3088 /**********************/
3089 /* Interrupt Handling */
3090 /**********************/
3091
3092 bool ath9k_hw_intrpend(struct ath_hw *ah)
3093 {
3094         u32 host_isr;
3095
3096         if (AR_SREV_9100(ah))
3097                 return true;
3098
3099         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3100         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3101                 return true;
3102
3103         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3104         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3105             && (host_isr != AR_INTR_SPURIOUS))
3106                 return true;
3107
3108         return false;
3109 }
3110
3111 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3112 {
3113         u32 isr = 0;
3114         u32 mask2 = 0;
3115         struct ath9k_hw_capabilities *pCap = &ah->caps;
3116         u32 sync_cause = 0;
3117         bool fatal_int = false;
3118         struct ath_common *common = ath9k_hw_common(ah);
3119
3120         if (!AR_SREV_9100(ah)) {
3121                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3122                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3123                             == AR_RTC_STATUS_ON) {
3124                                 isr = REG_READ(ah, AR_ISR);
3125                         }
3126                 }
3127
3128                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3129                         AR_INTR_SYNC_DEFAULT;
3130
3131                 *masked = 0;
3132
3133                 if (!isr && !sync_cause)
3134                         return false;
3135         } else {
3136                 *masked = 0;
3137                 isr = REG_READ(ah, AR_ISR);
3138         }
3139
3140         if (isr) {
3141                 if (isr & AR_ISR_BCNMISC) {
3142                         u32 isr2;
3143                         isr2 = REG_READ(ah, AR_ISR_S2);
3144                         if (isr2 & AR_ISR_S2_TIM)
3145                                 mask2 |= ATH9K_INT_TIM;
3146                         if (isr2 & AR_ISR_S2_DTIM)
3147                                 mask2 |= ATH9K_INT_DTIM;
3148                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3149                                 mask2 |= ATH9K_INT_DTIMSYNC;
3150                         if (isr2 & (AR_ISR_S2_CABEND))
3151                                 mask2 |= ATH9K_INT_CABEND;
3152                         if (isr2 & AR_ISR_S2_GTT)
3153                                 mask2 |= ATH9K_INT_GTT;
3154                         if (isr2 & AR_ISR_S2_CST)
3155                                 mask2 |= ATH9K_INT_CST;
3156                         if (isr2 & AR_ISR_S2_TSFOOR)
3157                                 mask2 |= ATH9K_INT_TSFOOR;
3158                 }
3159
3160                 isr = REG_READ(ah, AR_ISR_RAC);
3161                 if (isr == 0xffffffff) {
3162                         *masked = 0;
3163                         return false;
3164                 }
3165
3166                 *masked = isr & ATH9K_INT_COMMON;
3167
3168                 if (ah->config.intr_mitigation) {
3169                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3170                                 *masked |= ATH9K_INT_RX;
3171                 }
3172
3173                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3174                         *masked |= ATH9K_INT_RX;
3175                 if (isr &
3176                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3177                      AR_ISR_TXEOL)) {
3178                         u32 s0_s, s1_s;
3179
3180                         *masked |= ATH9K_INT_TX;
3181
3182                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3183                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3184                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3185
3186                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3187                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3188                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3189                 }
3190
3191                 if (isr & AR_ISR_RXORN) {
3192                         ath_print(common, ATH_DBG_INTERRUPT,
3193                                   "receive FIFO overrun interrupt\n");
3194                 }
3195
3196                 if (!AR_SREV_9100(ah)) {
3197                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3198                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3199                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3200                                         *masked |= ATH9K_INT_TIM_TIMER;
3201                         }
3202                 }
3203
3204                 *masked |= mask2;
3205         }
3206
3207         if (AR_SREV_9100(ah))
3208                 return true;
3209
3210         if (isr & AR_ISR_GENTMR) {
3211                 u32 s5_s;
3212
3213                 s5_s = REG_READ(ah, AR_ISR_S5_S);
3214                 if (isr & AR_ISR_GENTMR) {
3215                         ah->intr_gen_timer_trigger =
3216                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3217
3218                         ah->intr_gen_timer_thresh =
3219                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3220
3221                         if (ah->intr_gen_timer_trigger)
3222                                 *masked |= ATH9K_INT_GENTIMER;
3223
3224                 }
3225         }
3226
3227         if (sync_cause) {
3228                 fatal_int =
3229                         (sync_cause &
3230                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3231                         ? true : false;
3232
3233                 if (fatal_int) {
3234                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3235                                 ath_print(common, ATH_DBG_ANY,
3236                                           "received PCI FATAL interrupt\n");
3237                         }
3238                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3239                                 ath_print(common, ATH_DBG_ANY,
3240                                           "received PCI PERR interrupt\n");
3241                         }
3242                         *masked |= ATH9K_INT_FATAL;
3243                 }
3244                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3245                         ath_print(common, ATH_DBG_INTERRUPT,
3246                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3247                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3248                         REG_WRITE(ah, AR_RC, 0);
3249                         *masked |= ATH9K_INT_FATAL;
3250                 }
3251                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3252                         ath_print(common, ATH_DBG_INTERRUPT,
3253                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3254                 }
3255
3256                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3257                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3258         }
3259
3260         return true;
3261 }
3262
3263 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3264 {
3265         u32 omask = ah->mask_reg;
3266         u32 mask, mask2;
3267         struct ath9k_hw_capabilities *pCap = &ah->caps;
3268         struct ath_common *common = ath9k_hw_common(ah);
3269
3270         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3271
3272         if (omask & ATH9K_INT_GLOBAL) {
3273                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3274                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3275                 (void) REG_READ(ah, AR_IER);
3276                 if (!AR_SREV_9100(ah)) {
3277                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3278                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3279
3280                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3281                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3282                 }
3283         }
3284
3285         mask = ints & ATH9K_INT_COMMON;
3286         mask2 = 0;
3287
3288         if (ints & ATH9K_INT_TX) {
3289                 if (ah->txok_interrupt_mask)
3290                         mask |= AR_IMR_TXOK;
3291                 if (ah->txdesc_interrupt_mask)
3292                         mask |= AR_IMR_TXDESC;
3293                 if (ah->txerr_interrupt_mask)
3294                         mask |= AR_IMR_TXERR;
3295                 if (ah->txeol_interrupt_mask)
3296                         mask |= AR_IMR_TXEOL;
3297         }
3298         if (ints & ATH9K_INT_RX) {
3299                 mask |= AR_IMR_RXERR;
3300                 if (ah->config.intr_mitigation)
3301                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3302                 else
3303                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3304                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3305                         mask |= AR_IMR_GENTMR;
3306         }
3307
3308         if (ints & (ATH9K_INT_BMISC)) {
3309                 mask |= AR_IMR_BCNMISC;
3310                 if (ints & ATH9K_INT_TIM)
3311                         mask2 |= AR_IMR_S2_TIM;
3312                 if (ints & ATH9K_INT_DTIM)
3313                         mask2 |= AR_IMR_S2_DTIM;
3314                 if (ints & ATH9K_INT_DTIMSYNC)
3315                         mask2 |= AR_IMR_S2_DTIMSYNC;
3316                 if (ints & ATH9K_INT_CABEND)
3317                         mask2 |= AR_IMR_S2_CABEND;
3318                 if (ints & ATH9K_INT_TSFOOR)
3319                         mask2 |= AR_IMR_S2_TSFOOR;
3320         }
3321
3322         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3323                 mask |= AR_IMR_BCNMISC;
3324                 if (ints & ATH9K_INT_GTT)
3325                         mask2 |= AR_IMR_S2_GTT;
3326                 if (ints & ATH9K_INT_CST)
3327                         mask2 |= AR_IMR_S2_CST;
3328         }
3329
3330         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3331         REG_WRITE(ah, AR_IMR, mask);
3332         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3333                                            AR_IMR_S2_DTIM |
3334                                            AR_IMR_S2_DTIMSYNC |
3335                                            AR_IMR_S2_CABEND |
3336                                            AR_IMR_S2_CABTO |
3337                                            AR_IMR_S2_TSFOOR |
3338                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3339         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3340         ah->mask_reg = ints;
3341
3342         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3343                 if (ints & ATH9K_INT_TIM_TIMER)
3344                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3345                 else
3346                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3347         }
3348
3349         if (ints & ATH9K_INT_GLOBAL) {
3350                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3351                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3352                 if (!AR_SREV_9100(ah)) {
3353                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3354                                   AR_INTR_MAC_IRQ);
3355                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3356
3357
3358                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3359                                   AR_INTR_SYNC_DEFAULT);
3360                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3361                                   AR_INTR_SYNC_DEFAULT);
3362                 }
3363                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3364                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3365         }
3366
3367         return omask;
3368 }
3369
3370 /*******************/
3371 /* Beacon Handling */
3372 /*******************/
3373
3374 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3375 {
3376         int flags = 0;
3377
3378         ah->beacon_interval = beacon_period;
3379
3380         switch (ah->opmode) {
3381         case NL80211_IFTYPE_STATION:
3382         case NL80211_IFTYPE_MONITOR:
3383                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3384                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3385                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3386                 flags |= AR_TBTT_TIMER_EN;
3387                 break;
3388         case NL80211_IFTYPE_ADHOC:
3389         case NL80211_IFTYPE_MESH_POINT:
3390                 REG_SET_BIT(ah, AR_TXCFG,
3391                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3392                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3393                           TU_TO_USEC(next_beacon +
3394                                      (ah->atim_window ? ah->
3395                                       atim_window : 1)));
3396                 flags |= AR_NDP_TIMER_EN;
3397         case NL80211_IFTYPE_AP:
3398                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3399                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3400                           TU_TO_USEC(next_beacon -
3401                                      ah->config.
3402                                      dma_beacon_response_time));
3403                 REG_WRITE(ah, AR_NEXT_SWBA,
3404                           TU_TO_USEC(next_beacon -
3405                                      ah->config.
3406                                      sw_beacon_response_time));
3407                 flags |=
3408                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3409                 break;
3410         default:
3411                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3412                           "%s: unsupported opmode: %d\n",
3413                           __func__, ah->opmode);
3414                 return;
3415                 break;
3416         }
3417
3418         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3419         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3420         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3421         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3422
3423         beacon_period &= ~ATH9K_BEACON_ENA;
3424         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3425                 ath9k_hw_reset_tsf(ah);
3426         }
3427
3428         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3429 }
3430
3431 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3432                                     const struct ath9k_beacon_state *bs)
3433 {
3434         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3435         struct ath9k_hw_capabilities *pCap = &ah->caps;
3436         struct ath_common *common = ath9k_hw_common(ah);
3437
3438         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3439
3440         REG_WRITE(ah, AR_BEACON_PERIOD,
3441                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3442         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3443                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3444
3445         REG_RMW_FIELD(ah, AR_RSSI_THR,
3446                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3447
3448         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3449
3450         if (bs->bs_sleepduration > beaconintval)
3451                 beaconintval = bs->bs_sleepduration;
3452
3453         dtimperiod = bs->bs_dtimperiod;
3454         if (bs->bs_sleepduration > dtimperiod)
3455                 dtimperiod = bs->bs_sleepduration;
3456
3457         if (beaconintval == dtimperiod)
3458                 nextTbtt = bs->bs_nextdtim;
3459         else
3460                 nextTbtt = bs->bs_nexttbtt;
3461
3462         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3463         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3464         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3465         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3466
3467         REG_WRITE(ah, AR_NEXT_DTIM,
3468                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3469         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3470
3471         REG_WRITE(ah, AR_SLEEP1,
3472                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3473                   | AR_SLEEP1_ASSUME_DTIM);
3474
3475         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3476                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3477         else
3478                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3479
3480         REG_WRITE(ah, AR_SLEEP2,
3481                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3482
3483         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3484         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3485
3486         REG_SET_BIT(ah, AR_TIMER_MODE,
3487                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3488                     AR_DTIM_TIMER_EN);
3489
3490         /* TSF Out of Range Threshold */
3491         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3492 }
3493
3494 /*******************/
3495 /* HW Capabilities */
3496 /*******************/
3497
3498 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3499 {
3500         struct ath9k_hw_capabilities *pCap = &ah->caps;
3501         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3502         struct ath_common *common = ath9k_hw_common(ah);
3503         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3504
3505         u16 capField = 0, eeval;
3506
3507         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3508         regulatory->current_rd = eeval;
3509
3510         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3511         if (AR_SREV_9285_10_OR_LATER(ah))
3512                 eeval |= AR9285_RDEXT_DEFAULT;
3513         regulatory->current_rd_ext = eeval;
3514
3515         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3516
3517         if (ah->opmode != NL80211_IFTYPE_AP &&
3518             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3519                 if (regulatory->current_rd == 0x64 ||
3520                     regulatory->current_rd == 0x65)
3521                         regulatory->current_rd += 5;
3522                 else if (regulatory->current_rd == 0x41)
3523                         regulatory->current_rd = 0x43;
3524                 ath_print(common, ATH_DBG_REGULATORY,
3525                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3526         }
3527
3528         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3529         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3530
3531         if (eeval & AR5416_OPFLAGS_11A) {
3532                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3533                 if (ah->config.ht_enable) {
3534                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3535                                 set_bit(ATH9K_MODE_11NA_HT20,
3536                                         pCap->wireless_modes);
3537                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3538                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3539                                         pCap->wireless_modes);
3540                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3541                                         pCap->wireless_modes);
3542                         }
3543                 }
3544         }
3545
3546         if (eeval & AR5416_OPFLAGS_11G) {
3547                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3548                 if (ah->config.ht_enable) {
3549                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3550                                 set_bit(ATH9K_MODE_11NG_HT20,
3551                                         pCap->wireless_modes);
3552                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3553                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3554                                         pCap->wireless_modes);
3555                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3556                                         pCap->wireless_modes);
3557                         }
3558                 }
3559         }
3560
3561         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3562         /*
3563          * For AR9271 we will temporarilly uses the rx chainmax as read from
3564          * the EEPROM.
3565          */
3566         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3567             !(eeval & AR5416_OPFLAGS_11A) &&
3568             !(AR_SREV_9271(ah)))
3569                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3570                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3571         else
3572                 /* Use rx_chainmask from EEPROM. */
3573                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3574
3575         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3576                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3577
3578         pCap->low_2ghz_chan = 2312;
3579         pCap->high_2ghz_chan = 2732;
3580
3581         pCap->low_5ghz_chan = 4920;
3582         pCap->high_5ghz_chan = 6100;
3583
3584         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3585         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3586         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3587
3588         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3589         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3590         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3591
3592         if (ah->config.ht_enable)
3593                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3594         else
3595                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3596
3597         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3598         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3599         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3600         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3601
3602         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3603                 pCap->total_queues =
3604                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3605         else
3606                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3607
3608         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3609                 pCap->keycache_size =
3610                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3611         else
3612                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3613
3614         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3615         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3616
3617         if (AR_SREV_9285_10_OR_LATER(ah))
3618                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3619         else if (AR_SREV_9280_10_OR_LATER(ah))
3620                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3621         else
3622                 pCap->num_gpio_pins = AR_NUM_GPIO;
3623
3624         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3625                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3626                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3627         } else {
3628                 pCap->rts_aggr_limit = (8 * 1024);
3629         }
3630
3631         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3632
3633 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3634         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3635         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3636                 ah->rfkill_gpio =
3637                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3638                 ah->rfkill_polarity =
3639                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3640
3641                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3642         }
3643 #endif
3644
3645         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3646
3647         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3648                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3649         else
3650                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3651
3652         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3653                 pCap->reg_cap =
3654                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3655                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3656                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3657                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3658         } else {
3659                 pCap->reg_cap =
3660                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3661                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3662         }
3663
3664         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3665
3666         pCap->num_antcfg_5ghz =
3667                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3668         pCap->num_antcfg_2ghz =
3669                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3670
3671         if (AR_SREV_9280_10_OR_LATER(ah) &&
3672             ath9k_hw_btcoex_supported(ah)) {
3673                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3674                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3675
3676                 if (AR_SREV_9285(ah)) {
3677                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3678                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3679                 } else {
3680                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3681                 }
3682         } else {
3683                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3684         }
3685 }
3686
3687 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3688                             u32 capability, u32 *result)
3689 {
3690         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3691         switch (type) {
3692         case ATH9K_CAP_CIPHER:
3693                 switch (capability) {
3694                 case ATH9K_CIPHER_AES_CCM:
3695                 case ATH9K_CIPHER_AES_OCB:
3696                 case ATH9K_CIPHER_TKIP:
3697                 case ATH9K_CIPHER_WEP:
3698                 case ATH9K_CIPHER_MIC:
3699                 case ATH9K_CIPHER_CLR:
3700                         return true;
3701                 default:
3702                         return false;
3703                 }
3704         case ATH9K_CAP_TKIP_MIC:
3705                 switch (capability) {
3706                 case 0:
3707                         return true;
3708                 case 1:
3709                         return (ah->sta_id1_defaults &
3710                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3711                         false;
3712                 }
3713         case ATH9K_CAP_TKIP_SPLIT:
3714                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3715                         false : true;
3716         case ATH9K_CAP_DIVERSITY:
3717                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3718                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3719                         true : false;
3720         case ATH9K_CAP_MCAST_KEYSRCH:
3721                 switch (capability) {
3722                 case 0:
3723                         return true;
3724                 case 1:
3725                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3726                                 return false;
3727                         } else {
3728                                 return (ah->sta_id1_defaults &
3729                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3730                                         false;
3731                         }
3732                 }
3733                 return false;
3734         case ATH9K_CAP_TXPOW:
3735                 switch (capability) {
3736                 case 0:
3737                         return 0;
3738                 case 1:
3739                         *result = regulatory->power_limit;
3740                         return 0;
3741                 case 2:
3742                         *result = regulatory->max_power_level;
3743                         return 0;
3744                 case 3:
3745                         *result = regulatory->tp_scale;
3746                         return 0;
3747                 }
3748                 return false;
3749         case ATH9K_CAP_DS:
3750                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3751                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3752                         ? false : true;
3753         default:
3754                 return false;
3755         }
3756 }
3757
3758 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3759                             u32 capability, u32 setting, int *status)
3760 {
3761         u32 v;
3762
3763         switch (type) {
3764         case ATH9K_CAP_TKIP_MIC:
3765                 if (setting)
3766                         ah->sta_id1_defaults |=
3767                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3768                 else
3769                         ah->sta_id1_defaults &=
3770                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3771                 return true;
3772         case ATH9K_CAP_DIVERSITY:
3773                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3774                 if (setting)
3775                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3776                 else
3777                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3778                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3779                 return true;
3780         case ATH9K_CAP_MCAST_KEYSRCH:
3781                 if (setting)
3782                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3783                 else
3784                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3785                 return true;
3786         default:
3787                 return false;
3788         }
3789 }
3790
3791 /****************************/
3792 /* GPIO / RFKILL / Antennae */
3793 /****************************/
3794
3795 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3796                                          u32 gpio, u32 type)
3797 {
3798         int addr;
3799         u32 gpio_shift, tmp;
3800
3801         if (gpio > 11)
3802                 addr = AR_GPIO_OUTPUT_MUX3;
3803         else if (gpio > 5)
3804                 addr = AR_GPIO_OUTPUT_MUX2;
3805         else
3806                 addr = AR_GPIO_OUTPUT_MUX1;
3807
3808         gpio_shift = (gpio % 6) * 5;
3809
3810         if (AR_SREV_9280_20_OR_LATER(ah)
3811             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3812                 REG_RMW(ah, addr, (type << gpio_shift),
3813                         (0x1f << gpio_shift));
3814         } else {
3815                 tmp = REG_READ(ah, addr);
3816                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3817                 tmp &= ~(0x1f << gpio_shift);
3818                 tmp |= (type << gpio_shift);
3819                 REG_WRITE(ah, addr, tmp);
3820         }
3821 }
3822
3823 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3824 {
3825         u32 gpio_shift;
3826
3827         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3828
3829         gpio_shift = gpio << 1;
3830
3831         REG_RMW(ah,
3832                 AR_GPIO_OE_OUT,
3833                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3834                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3835 }
3836
3837 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3838 {
3839 #define MS_REG_READ(x, y) \
3840         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3841
3842         if (gpio >= ah->caps.num_gpio_pins)
3843                 return 0xffffffff;
3844
3845         if (AR_SREV_9287_10_OR_LATER(ah))
3846                 return MS_REG_READ(AR9287, gpio) != 0;
3847         else if (AR_SREV_9285_10_OR_LATER(ah))
3848                 return MS_REG_READ(AR9285, gpio) != 0;
3849         else if (AR_SREV_9280_10_OR_LATER(ah))
3850                 return MS_REG_READ(AR928X, gpio) != 0;
3851         else
3852                 return MS_REG_READ(AR, gpio) != 0;
3853 }
3854
3855 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3856                          u32 ah_signal_type)
3857 {
3858         u32 gpio_shift;
3859
3860         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3861
3862         gpio_shift = 2 * gpio;
3863
3864         REG_RMW(ah,
3865                 AR_GPIO_OE_OUT,
3866                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3867                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3868 }
3869
3870 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3871 {
3872         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3873                 AR_GPIO_BIT(gpio));
3874 }
3875
3876 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3877 {
3878         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3879 }
3880
3881 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3882 {
3883         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3884 }
3885
3886 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3887                                enum ath9k_ant_setting settings,
3888                                struct ath9k_channel *chan,
3889                                u8 *tx_chainmask,
3890                                u8 *rx_chainmask,
3891                                u8 *antenna_cfgd)
3892 {
3893         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3894
3895         if (AR_SREV_9280(ah)) {
3896                 if (!tx_chainmask_cfg) {
3897
3898                         tx_chainmask_cfg = *tx_chainmask;
3899                         rx_chainmask_cfg = *rx_chainmask;
3900                 }
3901
3902                 switch (settings) {
3903                 case ATH9K_ANT_FIXED_A:
3904                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3905                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3906                         *antenna_cfgd = true;
3907                         break;
3908                 case ATH9K_ANT_FIXED_B:
3909                         if (ah->caps.tx_chainmask >
3910                             ATH9K_ANTENNA1_CHAINMASK) {
3911                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3912                         }
3913                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3914                         *antenna_cfgd = true;
3915                         break;
3916                 case ATH9K_ANT_VARIABLE:
3917                         *tx_chainmask = tx_chainmask_cfg;
3918                         *rx_chainmask = rx_chainmask_cfg;
3919                         *antenna_cfgd = true;
3920                         break;
3921                 default:
3922                         break;
3923                 }
3924         } else {
3925                 ah->config.diversity_control = settings;
3926         }
3927
3928         return true;
3929 }
3930
3931 /*********************/
3932 /* General Operation */
3933 /*********************/
3934
3935 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3936 {
3937         u32 bits = REG_READ(ah, AR_RX_FILTER);
3938         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3939
3940         if (phybits & AR_PHY_ERR_RADAR)
3941                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3942         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3943                 bits |= ATH9K_RX_FILTER_PHYERR;
3944
3945         return bits;
3946 }
3947
3948 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3949 {
3950         u32 phybits;
3951
3952         REG_WRITE(ah, AR_RX_FILTER, bits);
3953
3954         phybits = 0;
3955         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3956                 phybits |= AR_PHY_ERR_RADAR;
3957         if (bits & ATH9K_RX_FILTER_PHYERR)
3958                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3959         REG_WRITE(ah, AR_PHY_ERR, phybits);
3960
3961         if (phybits)
3962                 REG_WRITE(ah, AR_RXCFG,
3963                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3964         else
3965                 REG_WRITE(ah, AR_RXCFG,
3966                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3967 }
3968
3969 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3970 {
3971         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3972 }
3973
3974 bool ath9k_hw_disable(struct ath_hw *ah)
3975 {
3976         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3977                 return false;
3978
3979         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3980 }
3981
3982 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3983 {
3984         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3985         struct ath9k_channel *chan = ah->curchan;
3986         struct ieee80211_channel *channel = chan->chan;
3987
3988         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3989
3990         ah->eep_ops->set_txpower(ah, chan,
3991                                  ath9k_regd_get_ctl(regulatory, chan),
3992                                  channel->max_antenna_gain * 2,
3993                                  channel->max_power * 2,
3994                                  min((u32) MAX_RATE_POWER,
3995                                  (u32) regulatory->power_limit));
3996 }
3997
3998 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3999 {
4000         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4001 }
4002
4003 void ath9k_hw_setopmode(struct ath_hw *ah)
4004 {
4005         ath9k_hw_set_operating_mode(ah, ah->opmode);
4006 }
4007
4008 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4009 {
4010         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4011         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4012 }
4013
4014 void ath9k_hw_write_associd(struct ath_hw *ah)
4015 {
4016         struct ath_common *common = ath9k_hw_common(ah);
4017
4018         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4019         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4020                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4021 }
4022
4023 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4024 {
4025         u64 tsf;
4026
4027         tsf = REG_READ(ah, AR_TSF_U32);
4028         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4029
4030         return tsf;
4031 }
4032
4033 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4034 {
4035         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4036         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4037 }
4038
4039 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4040 {
4041         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4042                            AH_TSF_WRITE_TIMEOUT))
4043                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4044                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4045
4046         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4047 }
4048
4049 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4050 {
4051         if (setting)
4052                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4053         else
4054                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4055 }
4056
4057 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4058 {
4059         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4060                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4061                           "bad slot time %u\n", us);
4062                 ah->slottime = (u32) -1;
4063                 return false;
4064         } else {
4065                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4066                 ah->slottime = us;
4067                 return true;
4068         }
4069 }
4070
4071 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
4072 {
4073         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
4074         u32 macmode;
4075
4076         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
4077                 macmode = AR_2040_JOINED_RX_CLEAR;
4078         else
4079                 macmode = 0;
4080
4081         REG_WRITE(ah, AR_2040_MODE, macmode);
4082 }
4083
4084 /* HW Generic timers configuration */
4085
4086 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4087 {
4088         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4089         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4090         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4091         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4092         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4093         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4094         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4095         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4096         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4097         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4098                                 AR_NDP2_TIMER_MODE, 0x0002},
4099         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4100                                 AR_NDP2_TIMER_MODE, 0x0004},
4101         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4102                                 AR_NDP2_TIMER_MODE, 0x0008},
4103         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4104                                 AR_NDP2_TIMER_MODE, 0x0010},
4105         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4106                                 AR_NDP2_TIMER_MODE, 0x0020},
4107         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4108                                 AR_NDP2_TIMER_MODE, 0x0040},
4109         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4110                                 AR_NDP2_TIMER_MODE, 0x0080}
4111 };
4112
4113 /* HW generic timer primitives */
4114
4115 /* compute and clear index of rightmost 1 */
4116 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4117 {
4118         u32 b;
4119
4120         b = *mask;
4121         b &= (0-b);
4122         *mask &= ~b;
4123         b *= debruijn32;
4124         b >>= 27;
4125
4126         return timer_table->gen_timer_index[b];
4127 }
4128
4129 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4130 {
4131         return REG_READ(ah, AR_TSF_L32);
4132 }
4133
4134 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4135                                           void (*trigger)(void *),
4136                                           void (*overflow)(void *),
4137                                           void *arg,
4138                                           u8 timer_index)
4139 {
4140         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4141         struct ath_gen_timer *timer;
4142
4143         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4144
4145         if (timer == NULL) {
4146                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4147                           "Failed to allocate memory"
4148                           "for hw timer[%d]\n", timer_index);
4149                 return NULL;
4150         }
4151
4152         /* allocate a hardware generic timer slot */
4153         timer_table->timers[timer_index] = timer;
4154         timer->index = timer_index;
4155         timer->trigger = trigger;
4156         timer->overflow = overflow;
4157         timer->arg = arg;
4158
4159         return timer;
4160 }
4161
4162 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4163                               struct ath_gen_timer *timer,
4164                               u32 timer_next,
4165                               u32 timer_period)
4166 {
4167         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4168         u32 tsf;
4169
4170         BUG_ON(!timer_period);
4171
4172         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4173
4174         tsf = ath9k_hw_gettsf32(ah);
4175
4176         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4177                   "curent tsf %x period %x"
4178                   "timer_next %x\n", tsf, timer_period, timer_next);
4179
4180         /*
4181          * Pull timer_next forward if the current TSF already passed it
4182          * because of software latency
4183          */
4184         if (timer_next < tsf)
4185                 timer_next = tsf + timer_period;
4186
4187         /*
4188          * Program generic timer registers
4189          */
4190         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4191                  timer_next);
4192         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4193                   timer_period);
4194         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4195                     gen_tmr_configuration[timer->index].mode_mask);
4196
4197         /* Enable both trigger and thresh interrupt masks */
4198         REG_SET_BIT(ah, AR_IMR_S5,
4199                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4200                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4201 }
4202
4203 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4204 {
4205         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4206
4207         if ((timer->index < AR_FIRST_NDP_TIMER) ||
4208                 (timer->index >= ATH_MAX_GEN_TIMER)) {
4209                 return;
4210         }
4211
4212         /* Clear generic timer enable bits. */
4213         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4214                         gen_tmr_configuration[timer->index].mode_mask);
4215
4216         /* Disable both trigger and thresh interrupt masks */
4217         REG_CLR_BIT(ah, AR_IMR_S5,
4218                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4219                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4220
4221         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4222 }
4223
4224 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4225 {
4226         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4227
4228         /* free the hardware generic timer slot */
4229         timer_table->timers[timer->index] = NULL;
4230         kfree(timer);
4231 }
4232
4233 /*
4234  * Generic Timer Interrupts handling
4235  */
4236 void ath_gen_timer_isr(struct ath_hw *ah)
4237 {
4238         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4239         struct ath_gen_timer *timer;
4240         struct ath_common *common = ath9k_hw_common(ah);
4241         u32 trigger_mask, thresh_mask, index;
4242
4243         /* get hardware generic timer interrupt status */
4244         trigger_mask = ah->intr_gen_timer_trigger;
4245         thresh_mask = ah->intr_gen_timer_thresh;
4246         trigger_mask &= timer_table->timer_mask.val;
4247         thresh_mask &= timer_table->timer_mask.val;
4248
4249         trigger_mask &= ~thresh_mask;
4250
4251         while (thresh_mask) {
4252                 index = rightmost_index(timer_table, &thresh_mask);
4253                 timer = timer_table->timers[index];
4254                 BUG_ON(!timer);
4255                 ath_print(common, ATH_DBG_HWTIMER,
4256                           "TSF overflow for Gen timer %d\n", index);
4257                 timer->overflow(timer->arg);
4258         }
4259
4260         while (trigger_mask) {
4261                 index = rightmost_index(timer_table, &trigger_mask);
4262                 timer = timer_table->timers[index];
4263                 BUG_ON(!timer);
4264                 ath_print(common, ATH_DBG_HWTIMER,
4265                           "Gen timer[%d] trigger\n", index);
4266                 timer->trigger(timer->arg);
4267         }
4268 }