2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
200 static int ath5k_pci_resume(struct pci_dev *pdev);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static void ath5k_configure_filter(struct ieee80211_hw *hw,
233 unsigned int changed_flags,
234 unsigned int *new_flags,
235 int mc_count, struct dev_mc_list *mclist);
236 static int ath5k_set_key(struct ieee80211_hw *hw,
237 enum set_key_cmd cmd,
238 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
239 struct ieee80211_key_conf *key);
240 static int ath5k_get_stats(struct ieee80211_hw *hw,
241 struct ieee80211_low_level_stats *stats);
242 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
243 struct ieee80211_tx_queue_stats *stats);
244 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
245 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
246 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
247 static int ath5k_beacon_update(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif);
249 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif,
251 struct ieee80211_bss_conf *bss_conf,
253 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
254 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
256 static const struct ieee80211_ops ath5k_hw_ops = {
258 .start = ath5k_start,
260 .add_interface = ath5k_add_interface,
261 .remove_interface = ath5k_remove_interface,
262 .config = ath5k_config,
263 .configure_filter = ath5k_configure_filter,
264 .set_key = ath5k_set_key,
265 .get_stats = ath5k_get_stats,
267 .get_tx_stats = ath5k_get_tx_stats,
268 .get_tsf = ath5k_get_tsf,
269 .set_tsf = ath5k_set_tsf,
270 .reset_tsf = ath5k_reset_tsf,
271 .bss_info_changed = ath5k_bss_info_changed,
272 .sw_scan_start = ath5k_sw_scan_start,
273 .sw_scan_complete = ath5k_sw_scan_complete,
277 * Prototypes - Internal functions
280 static int ath5k_attach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282 static void ath5k_detach(struct pci_dev *pdev,
283 struct ieee80211_hw *hw);
284 /* Channel/mode setup */
285 static inline short ath5k_ieee2mhz(short chan);
286 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
287 struct ieee80211_channel *channels,
290 static int ath5k_setup_bands(struct ieee80211_hw *hw);
291 static int ath5k_chan_set(struct ath5k_softc *sc,
292 struct ieee80211_channel *chan);
293 static void ath5k_setcurmode(struct ath5k_softc *sc,
295 static void ath5k_mode_setup(struct ath5k_softc *sc);
297 /* Descriptor setup */
298 static int ath5k_desc_alloc(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
300 static void ath5k_desc_free(struct ath5k_softc *sc,
301 struct pci_dev *pdev);
303 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
304 struct ath5k_buf *bf);
305 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
306 struct ath5k_buf *bf,
307 struct ath5k_txq *txq);
308 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
309 struct ath5k_buf *bf)
314 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
316 dev_kfree_skb_any(bf->skb);
320 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
321 struct ath5k_buf *bf)
326 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
328 dev_kfree_skb_any(bf->skb);
334 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
335 int qtype, int subtype);
336 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
337 static int ath5k_beaconq_config(struct ath5k_softc *sc);
338 static void ath5k_txq_drainq(struct ath5k_softc *sc,
339 struct ath5k_txq *txq);
340 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
341 static void ath5k_txq_release(struct ath5k_softc *sc);
343 static int ath5k_rx_start(struct ath5k_softc *sc);
344 static void ath5k_rx_stop(struct ath5k_softc *sc);
345 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
346 struct ath5k_desc *ds,
348 struct ath5k_rx_status *rs);
349 static void ath5k_tasklet_rx(unsigned long data);
351 static void ath5k_tx_processq(struct ath5k_softc *sc,
352 struct ath5k_txq *txq);
353 static void ath5k_tasklet_tx(unsigned long data);
354 /* Beacon handling */
355 static int ath5k_beacon_setup(struct ath5k_softc *sc,
356 struct ath5k_buf *bf);
357 static void ath5k_beacon_send(struct ath5k_softc *sc);
358 static void ath5k_beacon_config(struct ath5k_softc *sc);
359 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
360 static void ath5k_tasklet_beacon(unsigned long data);
362 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
364 u64 tsf = ath5k_hw_get_tsf64(ah);
366 if ((tsf & 0x7fff) < rstamp)
369 return (tsf & ~0x7fff) | rstamp;
372 /* Interrupt handling */
373 static int ath5k_init(struct ath5k_softc *sc);
374 static int ath5k_stop_locked(struct ath5k_softc *sc);
375 static int ath5k_stop_hw(struct ath5k_softc *sc);
376 static irqreturn_t ath5k_intr(int irq, void *dev_id);
377 static void ath5k_tasklet_reset(unsigned long data);
379 static void ath5k_calibrate(unsigned long data);
382 * Module init/exit functions
391 ret = pci_register_driver(&ath5k_pci_driver);
393 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
403 pci_unregister_driver(&ath5k_pci_driver);
405 ath5k_debug_finish();
408 module_init(init_ath5k_pci);
409 module_exit(exit_ath5k_pci);
412 /********************\
413 * PCI Initialization *
414 \********************/
417 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
419 const char *name = "xxxxx";
422 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
423 if (srev_names[i].sr_type != type)
426 if ((val & 0xf0) == srev_names[i].sr_val)
427 name = srev_names[i].sr_name;
429 if ((val & 0xff) == srev_names[i].sr_val) {
430 name = srev_names[i].sr_name;
439 ath5k_pci_probe(struct pci_dev *pdev,
440 const struct pci_device_id *id)
443 struct ath5k_softc *sc;
444 struct ieee80211_hw *hw;
448 ret = pci_enable_device(pdev);
450 dev_err(&pdev->dev, "can't enable device\n");
454 /* XXX 32-bit addressing only */
455 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
457 dev_err(&pdev->dev, "32-bit DMA not available\n");
462 * Cache line size is used to size and align various
463 * structures used to communicate with the hardware.
465 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
468 * Linux 2.4.18 (at least) writes the cache line size
469 * register as a 16-bit wide register which is wrong.
470 * We must have this setup properly for rx buffer
471 * DMA to work so force a reasonable value here if it
474 csz = L1_CACHE_BYTES / sizeof(u32);
475 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
478 * The default setting of latency timer yields poor results,
479 * set it to the value used by other systems. It may be worth
480 * tweaking this setting more.
482 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
484 /* Enable bus mastering */
485 pci_set_master(pdev);
488 * Disable the RETRY_TIMEOUT register (0x41) to keep
489 * PCI Tx retries from interfering with C3 CPU state.
491 pci_write_config_byte(pdev, 0x41, 0);
493 ret = pci_request_region(pdev, 0, "ath5k");
495 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
499 mem = pci_iomap(pdev, 0, 0);
501 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
507 * Allocate hw (mac80211 main struct)
508 * and hw->priv (driver private data)
510 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
512 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
517 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
519 /* Initialize driver private data */
520 SET_IEEE80211_DEV(hw, &pdev->dev);
521 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
522 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
523 IEEE80211_HW_SIGNAL_DBM |
524 IEEE80211_HW_NOISE_DBM;
526 hw->wiphy->interface_modes =
527 BIT(NL80211_IFTYPE_AP) |
528 BIT(NL80211_IFTYPE_STATION) |
529 BIT(NL80211_IFTYPE_ADHOC) |
530 BIT(NL80211_IFTYPE_MESH_POINT);
532 hw->extra_tx_headroom = 2;
533 hw->channel_change_time = 5000;
538 ath5k_debug_init_device(sc);
541 * Mark the device as detached to avoid processing
542 * interrupts until setup is complete.
544 __set_bit(ATH_STAT_INVALID, sc->status);
546 sc->iobase = mem; /* So we can unmap it on detach */
547 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
548 sc->opmode = NL80211_IFTYPE_STATION;
550 mutex_init(&sc->lock);
551 spin_lock_init(&sc->rxbuflock);
552 spin_lock_init(&sc->txbuflock);
553 spin_lock_init(&sc->block);
555 /* Set private data */
556 pci_set_drvdata(pdev, hw);
558 /* Setup interrupt handler */
559 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
561 ATH5K_ERR(sc, "request_irq failed\n");
565 /* Initialize device */
566 sc->ah = ath5k_hw_attach(sc, id->driver_data);
567 if (IS_ERR(sc->ah)) {
568 ret = PTR_ERR(sc->ah);
572 /* set up multi-rate retry capabilities */
573 if (sc->ah->ah_version == AR5K_AR5212) {
575 hw->max_rate_tries = 11;
578 /* Finish private driver data initialization */
579 ret = ath5k_attach(pdev, hw);
583 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
584 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
586 sc->ah->ah_phy_revision);
588 if (!sc->ah->ah_single_chip) {
589 /* Single chip radio (!RF5111) */
590 if (sc->ah->ah_radio_5ghz_revision &&
591 !sc->ah->ah_radio_2ghz_revision) {
592 /* No 5GHz support -> report 2GHz radio */
593 if (!test_bit(AR5K_MODE_11A,
594 sc->ah->ah_capabilities.cap_mode)) {
595 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
596 ath5k_chip_name(AR5K_VERSION_RAD,
597 sc->ah->ah_radio_5ghz_revision),
598 sc->ah->ah_radio_5ghz_revision);
599 /* No 2GHz support (5110 and some
600 * 5Ghz only cards) -> report 5Ghz radio */
601 } else if (!test_bit(AR5K_MODE_11B,
602 sc->ah->ah_capabilities.cap_mode)) {
603 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_5ghz_revision),
606 sc->ah->ah_radio_5ghz_revision);
607 /* Multiband radio */
609 ATH5K_INFO(sc, "RF%s multiband radio found"
611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
616 /* Multi chip radio (RF5111 - RF2111) ->
617 * report both 2GHz/5GHz radios */
618 else if (sc->ah->ah_radio_5ghz_revision &&
619 sc->ah->ah_radio_2ghz_revision){
620 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
621 ath5k_chip_name(AR5K_VERSION_RAD,
622 sc->ah->ah_radio_5ghz_revision),
623 sc->ah->ah_radio_5ghz_revision);
624 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
625 ath5k_chip_name(AR5K_VERSION_RAD,
626 sc->ah->ah_radio_2ghz_revision),
627 sc->ah->ah_radio_2ghz_revision);
632 /* ready to process interrupts */
633 __clear_bit(ATH_STAT_INVALID, sc->status);
637 ath5k_hw_detach(sc->ah);
639 free_irq(pdev->irq, sc);
641 ieee80211_free_hw(hw);
643 pci_iounmap(pdev, mem);
645 pci_release_region(pdev, 0);
647 pci_disable_device(pdev);
652 static void __devexit
653 ath5k_pci_remove(struct pci_dev *pdev)
655 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
656 struct ath5k_softc *sc = hw->priv;
658 ath5k_debug_finish_device(sc);
659 ath5k_detach(pdev, hw);
660 ath5k_hw_detach(sc->ah);
661 free_irq(pdev->irq, sc);
662 pci_iounmap(pdev, sc->iobase);
663 pci_release_region(pdev, 0);
664 pci_disable_device(pdev);
665 ieee80211_free_hw(hw);
670 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
672 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
673 struct ath5k_softc *sc = hw->priv;
677 free_irq(pdev->irq, sc);
678 pci_save_state(pdev);
679 pci_disable_device(pdev);
680 pci_set_power_state(pdev, PCI_D3hot);
686 ath5k_pci_resume(struct pci_dev *pdev)
688 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
689 struct ath5k_softc *sc = hw->priv;
692 pci_restore_state(pdev);
694 err = pci_enable_device(pdev);
699 * Suspend/Resume resets the PCI configuration space, so we have to
700 * re-disable the RETRY_TIMEOUT register (0x41) to keep
701 * PCI Tx retries from interfering with C3 CPU state
703 pci_write_config_byte(pdev, 0x41, 0);
705 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
707 ATH5K_ERR(sc, "request_irq failed\n");
711 ath5k_led_enable(sc);
715 pci_disable_device(pdev);
718 #endif /* CONFIG_PM */
721 /***********************\
722 * Driver Initialization *
723 \***********************/
725 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
727 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
728 struct ath5k_softc *sc = hw->priv;
729 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
731 return ath_reg_notifier_apply(wiphy, request, reg);
735 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
737 struct ath5k_softc *sc = hw->priv;
738 struct ath5k_hw *ah = sc->ah;
739 u8 mac[ETH_ALEN] = {};
742 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
745 * Check if the MAC has multi-rate retry support.
746 * We do this by trying to setup a fake extended
747 * descriptor. MAC's that don't have support will
748 * return false w/o doing anything. MAC's that do
749 * support it will return true w/o doing anything.
751 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
755 __set_bit(ATH_STAT_MRRETRY, sc->status);
758 * Collect the channel list. The 802.11 layer
759 * is resposible for filtering this list based
760 * on settings like the phy mode and regulatory
761 * domain restrictions.
763 ret = ath5k_setup_bands(hw);
765 ATH5K_ERR(sc, "can't get channels\n");
769 /* NB: setup here so ath5k_rate_update is happy */
770 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
771 ath5k_setcurmode(sc, AR5K_MODE_11A);
773 ath5k_setcurmode(sc, AR5K_MODE_11B);
776 * Allocate tx+rx descriptors and populate the lists.
778 ret = ath5k_desc_alloc(sc, pdev);
780 ATH5K_ERR(sc, "can't allocate descriptors\n");
785 * Allocate hardware transmit queues: one queue for
786 * beacon frames and one data queue for each QoS
787 * priority. Note that hw functions handle reseting
788 * these queues at the needed time.
790 ret = ath5k_beaconq_setup(ah);
792 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
796 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
797 if (IS_ERR(sc->cabq)) {
798 ATH5K_ERR(sc, "can't setup cab queue\n");
799 ret = PTR_ERR(sc->cabq);
803 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
804 if (IS_ERR(sc->txq)) {
805 ATH5K_ERR(sc, "can't setup xmit queue\n");
806 ret = PTR_ERR(sc->txq);
810 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
811 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
812 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
813 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
814 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
816 ret = ath5k_eeprom_read_mac(ah, mac);
818 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
823 SET_IEEE80211_PERM_ADDR(hw, mac);
824 /* All MAC address bits matter for ACKs */
825 memset(sc->bssidmask, 0xff, ETH_ALEN);
826 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
828 ah->ah_regulatory.current_rd =
829 ah->ah_capabilities.cap_eeprom.ee_regdomain;
830 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
832 ATH5K_ERR(sc, "can't initialize regulatory system\n");
836 ret = ieee80211_register_hw(hw);
838 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
842 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
843 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
849 ath5k_txq_release(sc);
851 ath5k_hw_release_tx_queue(ah, sc->bhalq);
853 ath5k_desc_free(sc, pdev);
859 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
861 struct ath5k_softc *sc = hw->priv;
864 * NB: the order of these is important:
865 * o call the 802.11 layer before detaching ath5k_hw to
866 * insure callbacks into the driver to delete global
867 * key cache entries can be handled
868 * o reclaim the tx queue data structures after calling
869 * the 802.11 layer as we'll get called back to reclaim
870 * node state and potentially want to use them
871 * o to cleanup the tx queues the hal is called, so detach
873 * XXX: ??? detach ath5k_hw ???
874 * Other than that, it's straightforward...
876 ieee80211_unregister_hw(hw);
877 ath5k_desc_free(sc, pdev);
878 ath5k_txq_release(sc);
879 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
880 ath5k_unregister_leds(sc);
883 * NB: can't reclaim these until after ieee80211_ifdetach
884 * returns because we'll get called back to reclaim node
885 * state and potentially want to use them.
892 /********************\
893 * Channel/mode setup *
894 \********************/
897 * Convert IEEE channel number to MHz frequency.
900 ath5k_ieee2mhz(short chan)
902 if (chan <= 14 || chan >= 27)
903 return ieee80211chan2mhz(chan);
905 return 2212 + chan * 20;
909 * Returns true for the channel numbers used without all_channels modparam.
911 static bool ath5k_is_standard_channel(short chan)
913 return ((chan <= 14) ||
915 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
917 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
919 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
923 ath5k_copy_channels(struct ath5k_hw *ah,
924 struct ieee80211_channel *channels,
928 unsigned int i, count, size, chfreq, freq, ch;
930 if (!test_bit(mode, ah->ah_modes))
935 case AR5K_MODE_11A_TURBO:
936 /* 1..220, but 2GHz frequencies are filtered by check_channel */
938 chfreq = CHANNEL_5GHZ;
942 case AR5K_MODE_11G_TURBO:
944 chfreq = CHANNEL_2GHZ;
947 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
951 for (i = 0, count = 0; i < size && max > 0; i++) {
953 freq = ath5k_ieee2mhz(ch);
955 /* Check if channel is supported by the chipset */
956 if (!ath5k_channel_ok(ah, freq, chfreq))
959 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
962 /* Write channel info and increment counter */
963 channels[count].center_freq = freq;
964 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
965 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
969 channels[count].hw_value = chfreq | CHANNEL_OFDM;
971 case AR5K_MODE_11A_TURBO:
972 case AR5K_MODE_11G_TURBO:
973 channels[count].hw_value = chfreq |
974 CHANNEL_OFDM | CHANNEL_TURBO;
977 channels[count].hw_value = CHANNEL_B;
988 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
992 for (i = 0; i < AR5K_MAX_RATES; i++)
993 sc->rate_idx[b->band][i] = -1;
995 for (i = 0; i < b->n_bitrates; i++) {
996 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
997 if (b->bitrates[i].hw_value_short)
998 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1003 ath5k_setup_bands(struct ieee80211_hw *hw)
1005 struct ath5k_softc *sc = hw->priv;
1006 struct ath5k_hw *ah = sc->ah;
1007 struct ieee80211_supported_band *sband;
1008 int max_c, count_c = 0;
1011 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1012 max_c = ARRAY_SIZE(sc->channels);
1015 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1016 sband->band = IEEE80211_BAND_2GHZ;
1017 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1019 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1021 memcpy(sband->bitrates, &ath5k_rates[0],
1022 sizeof(struct ieee80211_rate) * 12);
1023 sband->n_bitrates = 12;
1025 sband->channels = sc->channels;
1026 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1027 AR5K_MODE_11G, max_c);
1029 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1030 count_c = sband->n_channels;
1032 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1034 memcpy(sband->bitrates, &ath5k_rates[0],
1035 sizeof(struct ieee80211_rate) * 4);
1036 sband->n_bitrates = 4;
1038 /* 5211 only supports B rates and uses 4bit rate codes
1039 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1042 if (ah->ah_version == AR5K_AR5211) {
1043 for (i = 0; i < 4; i++) {
1044 sband->bitrates[i].hw_value =
1045 sband->bitrates[i].hw_value & 0xF;
1046 sband->bitrates[i].hw_value_short =
1047 sband->bitrates[i].hw_value_short & 0xF;
1051 sband->channels = sc->channels;
1052 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1053 AR5K_MODE_11B, max_c);
1055 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1056 count_c = sband->n_channels;
1059 ath5k_setup_rate_idx(sc, sband);
1061 /* 5GHz band, A mode */
1062 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1063 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1064 sband->band = IEEE80211_BAND_5GHZ;
1065 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1067 memcpy(sband->bitrates, &ath5k_rates[4],
1068 sizeof(struct ieee80211_rate) * 8);
1069 sband->n_bitrates = 8;
1071 sband->channels = &sc->channels[count_c];
1072 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1073 AR5K_MODE_11A, max_c);
1075 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1077 ath5k_setup_rate_idx(sc, sband);
1079 ath5k_debug_dump_bands(sc);
1085 * Set/change channels. If the channel is really being changed,
1086 * it's done by reseting the chip. To accomplish this we must
1087 * first cleanup any pending DMA, then restart stuff after a la
1090 * Called with sc->lock.
1093 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1095 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1096 sc->curchan->center_freq, chan->center_freq);
1098 if (chan->center_freq != sc->curchan->center_freq ||
1099 chan->hw_value != sc->curchan->hw_value) {
1102 * To switch channels clear any pending DMA operations;
1103 * wait long enough for the RX fifo to drain, reset the
1104 * hardware at the new frequency, and then re-enable
1105 * the relevant bits of the h/w.
1107 return ath5k_reset(sc, chan);
1114 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1118 if (mode == AR5K_MODE_11A) {
1119 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1121 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1126 ath5k_mode_setup(struct ath5k_softc *sc)
1128 struct ath5k_hw *ah = sc->ah;
1131 /* configure rx filter */
1132 rfilt = sc->filter_flags;
1133 ath5k_hw_set_rx_filter(ah, rfilt);
1135 if (ath5k_hw_hasbssidmask(ah))
1136 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1138 /* configure operational mode */
1139 ath5k_hw_set_opmode(ah);
1141 ath5k_hw_set_mcast_filter(ah, 0, 0);
1142 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1146 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1150 /* return base rate on errors */
1151 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1152 "hw_rix out of bounds: %x\n", hw_rix))
1155 rix = sc->rate_idx[sc->curband->band][hw_rix];
1156 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1167 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1169 struct sk_buff *skb;
1173 * Allocate buffer with headroom_needed space for the
1174 * fake physical layer header at the start.
1176 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1179 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1180 sc->rxbufsize + sc->cachelsz - 1);
1184 * Cache-line-align. This is important (for the
1185 * 5210 at least) as not doing so causes bogus data
1188 off = ((unsigned long)skb->data) % sc->cachelsz;
1190 skb_reserve(skb, sc->cachelsz - off);
1192 *skb_addr = pci_map_single(sc->pdev,
1193 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1194 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1195 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1203 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1205 struct ath5k_hw *ah = sc->ah;
1206 struct sk_buff *skb = bf->skb;
1207 struct ath5k_desc *ds;
1210 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1217 * Setup descriptors. For receive we always terminate
1218 * the descriptor list with a self-linked entry so we'll
1219 * not get overrun under high load (as can happen with a
1220 * 5212 when ANI processing enables PHY error frames).
1222 * To insure the last descriptor is self-linked we create
1223 * each descriptor as self-linked and add it to the end. As
1224 * each additional descriptor is added the previous self-linked
1225 * entry is ``fixed'' naturally. This should be safe even
1226 * if DMA is happening. When processing RX interrupts we
1227 * never remove/process the last, self-linked, entry on the
1228 * descriptor list. This insures the hardware always has
1229 * someplace to write a new frame.
1232 ds->ds_link = bf->daddr; /* link to self */
1233 ds->ds_data = bf->skbaddr;
1234 ah->ah_setup_rx_desc(ah, ds,
1235 skb_tailroom(skb), /* buffer size */
1238 if (sc->rxlink != NULL)
1239 *sc->rxlink = bf->daddr;
1240 sc->rxlink = &ds->ds_link;
1245 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1246 struct ath5k_txq *txq)
1248 struct ath5k_hw *ah = sc->ah;
1249 struct ath5k_desc *ds = bf->desc;
1250 struct sk_buff *skb = bf->skb;
1251 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1252 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1253 struct ieee80211_rate *rate;
1254 unsigned int mrr_rate[3], mrr_tries[3];
1261 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1263 /* XXX endianness */
1264 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1267 rate = ieee80211_get_tx_rate(sc->hw, info);
1269 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1270 flags |= AR5K_TXDESC_NOACK;
1272 rc_flags = info->control.rates[0].flags;
1273 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1274 rate->hw_value_short : rate->hw_value;
1278 /* FIXME: If we are in g mode and rate is a CCK rate
1279 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1280 * from tx power (value is in dB units already) */
1281 if (info->control.hw_key) {
1282 keyidx = info->control.hw_key->hw_key_idx;
1283 pktlen += info->control.hw_key->icv_len;
1285 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1286 flags |= AR5K_TXDESC_RTSENA;
1287 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1288 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1289 sc->vif, pktlen, info));
1291 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1292 flags |= AR5K_TXDESC_CTSENA;
1293 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1294 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1295 sc->vif, pktlen, info));
1297 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1298 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1299 (sc->power_level * 2),
1301 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1302 cts_rate, duration);
1306 memset(mrr_rate, 0, sizeof(mrr_rate));
1307 memset(mrr_tries, 0, sizeof(mrr_tries));
1308 for (i = 0; i < 3; i++) {
1309 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1313 mrr_rate[i] = rate->hw_value;
1314 mrr_tries[i] = info->control.rates[i + 1].count;
1317 ah->ah_setup_mrr_tx_desc(ah, ds,
1318 mrr_rate[0], mrr_tries[0],
1319 mrr_rate[1], mrr_tries[1],
1320 mrr_rate[2], mrr_tries[2]);
1323 ds->ds_data = bf->skbaddr;
1325 spin_lock_bh(&txq->lock);
1326 list_add_tail(&bf->list, &txq->q);
1327 sc->tx_stats[txq->qnum].len++;
1328 if (txq->link == NULL) /* is this first packet? */
1329 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1330 else /* no, so only link it */
1331 *txq->link = bf->daddr;
1333 txq->link = &ds->ds_link;
1334 ath5k_hw_start_tx_dma(ah, txq->qnum);
1336 spin_unlock_bh(&txq->lock);
1340 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1344 /*******************\
1345 * Descriptors setup *
1346 \*******************/
1349 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1351 struct ath5k_desc *ds;
1352 struct ath5k_buf *bf;
1357 /* allocate descriptors */
1358 sc->desc_len = sizeof(struct ath5k_desc) *
1359 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1360 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1361 if (sc->desc == NULL) {
1362 ATH5K_ERR(sc, "can't allocate descriptors\n");
1367 da = sc->desc_daddr;
1368 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1369 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1371 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1372 sizeof(struct ath5k_buf), GFP_KERNEL);
1374 ATH5K_ERR(sc, "can't allocate bufptr\n");
1380 INIT_LIST_HEAD(&sc->rxbuf);
1381 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1384 list_add_tail(&bf->list, &sc->rxbuf);
1387 INIT_LIST_HEAD(&sc->txbuf);
1388 sc->txbuf_len = ATH_TXBUF;
1389 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1390 da += sizeof(*ds)) {
1393 list_add_tail(&bf->list, &sc->txbuf);
1403 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1410 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1412 struct ath5k_buf *bf;
1414 ath5k_txbuf_free(sc, sc->bbuf);
1415 list_for_each_entry(bf, &sc->txbuf, list)
1416 ath5k_txbuf_free(sc, bf);
1417 list_for_each_entry(bf, &sc->rxbuf, list)
1418 ath5k_rxbuf_free(sc, bf);
1420 /* Free memory associated with all descriptors */
1421 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1435 static struct ath5k_txq *
1436 ath5k_txq_setup(struct ath5k_softc *sc,
1437 int qtype, int subtype)
1439 struct ath5k_hw *ah = sc->ah;
1440 struct ath5k_txq *txq;
1441 struct ath5k_txq_info qi = {
1442 .tqi_subtype = subtype,
1443 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1444 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1445 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1450 * Enable interrupts only for EOL and DESC conditions.
1451 * We mark tx descriptors to receive a DESC interrupt
1452 * when a tx queue gets deep; otherwise waiting for the
1453 * EOL to reap descriptors. Note that this is done to
1454 * reduce interrupt load and this only defers reaping
1455 * descriptors, never transmitting frames. Aside from
1456 * reducing interrupts this also permits more concurrency.
1457 * The only potential downside is if the tx queue backs
1458 * up in which case the top half of the kernel may backup
1459 * due to a lack of tx descriptors.
1461 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1462 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1463 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1466 * NB: don't print a message, this happens
1467 * normally on parts with too few tx queues
1469 return ERR_PTR(qnum);
1471 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1472 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1473 qnum, ARRAY_SIZE(sc->txqs));
1474 ath5k_hw_release_tx_queue(ah, qnum);
1475 return ERR_PTR(-EINVAL);
1477 txq = &sc->txqs[qnum];
1481 INIT_LIST_HEAD(&txq->q);
1482 spin_lock_init(&txq->lock);
1485 return &sc->txqs[qnum];
1489 ath5k_beaconq_setup(struct ath5k_hw *ah)
1491 struct ath5k_txq_info qi = {
1492 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1493 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1494 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1495 /* NB: for dynamic turbo, don't enable any other interrupts */
1496 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1499 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1503 ath5k_beaconq_config(struct ath5k_softc *sc)
1505 struct ath5k_hw *ah = sc->ah;
1506 struct ath5k_txq_info qi;
1509 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1512 if (sc->opmode == NL80211_IFTYPE_AP ||
1513 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1515 * Always burst out beacon and CAB traffic
1516 * (aifs = cwmin = cwmax = 0)
1521 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1523 * Adhoc mode; backoff between 0 and (2 * cw_min).
1527 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1530 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1531 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1532 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1534 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1536 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1537 "hardware queue!\n", __func__);
1541 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1545 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1547 struct ath5k_buf *bf, *bf0;
1550 * NB: this assumes output has been stopped and
1551 * we do not need to block ath5k_tx_tasklet
1553 spin_lock_bh(&txq->lock);
1554 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1555 ath5k_debug_printtxbuf(sc, bf);
1557 ath5k_txbuf_free(sc, bf);
1559 spin_lock_bh(&sc->txbuflock);
1560 sc->tx_stats[txq->qnum].len--;
1561 list_move_tail(&bf->list, &sc->txbuf);
1563 spin_unlock_bh(&sc->txbuflock);
1566 spin_unlock_bh(&txq->lock);
1570 * Drain the transmit queues and reclaim resources.
1573 ath5k_txq_cleanup(struct ath5k_softc *sc)
1575 struct ath5k_hw *ah = sc->ah;
1578 /* XXX return value */
1579 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1580 /* don't touch the hardware if marked invalid */
1581 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1582 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1583 ath5k_hw_get_txdp(ah, sc->bhalq));
1584 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1585 if (sc->txqs[i].setup) {
1586 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1587 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1590 ath5k_hw_get_txdp(ah,
1595 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1597 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1598 if (sc->txqs[i].setup)
1599 ath5k_txq_drainq(sc, &sc->txqs[i]);
1603 ath5k_txq_release(struct ath5k_softc *sc)
1605 struct ath5k_txq *txq = sc->txqs;
1608 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1610 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1623 * Enable the receive h/w following a reset.
1626 ath5k_rx_start(struct ath5k_softc *sc)
1628 struct ath5k_hw *ah = sc->ah;
1629 struct ath5k_buf *bf;
1632 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1634 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1635 sc->cachelsz, sc->rxbufsize);
1637 spin_lock_bh(&sc->rxbuflock);
1639 list_for_each_entry(bf, &sc->rxbuf, list) {
1640 ret = ath5k_rxbuf_setup(sc, bf);
1642 spin_unlock_bh(&sc->rxbuflock);
1646 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1647 ath5k_hw_set_rxdp(ah, bf->daddr);
1648 spin_unlock_bh(&sc->rxbuflock);
1650 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1651 ath5k_mode_setup(sc); /* set filters, etc. */
1652 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1660 * Disable the receive h/w in preparation for a reset.
1663 ath5k_rx_stop(struct ath5k_softc *sc)
1665 struct ath5k_hw *ah = sc->ah;
1667 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1668 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1669 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1671 ath5k_debug_printrxbuffs(sc, ah);
1673 sc->rxlink = NULL; /* just in case */
1677 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1678 struct sk_buff *skb, struct ath5k_rx_status *rs)
1680 struct ieee80211_hdr *hdr = (void *)skb->data;
1681 unsigned int keyix, hlen;
1683 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1684 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1685 return RX_FLAG_DECRYPTED;
1687 /* Apparently when a default key is used to decrypt the packet
1688 the hw does not set the index used to decrypt. In such cases
1689 get the index from the packet. */
1690 hlen = ieee80211_hdrlen(hdr->frame_control);
1691 if (ieee80211_has_protected(hdr->frame_control) &&
1692 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1693 skb->len >= hlen + 4) {
1694 keyix = skb->data[hlen + 3] >> 6;
1696 if (test_bit(keyix, sc->keymap))
1697 return RX_FLAG_DECRYPTED;
1705 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1706 struct ieee80211_rx_status *rxs)
1710 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1712 if (ieee80211_is_beacon(mgmt->frame_control) &&
1713 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1714 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1716 * Received an IBSS beacon with the same BSSID. Hardware *must*
1717 * have updated the local TSF. We have to work around various
1718 * hardware bugs, though...
1720 tsf = ath5k_hw_get_tsf64(sc->ah);
1721 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1722 hw_tu = TSF_TO_TU(tsf);
1724 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1725 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1726 (unsigned long long)bc_tstamp,
1727 (unsigned long long)rxs->mactime,
1728 (unsigned long long)(rxs->mactime - bc_tstamp),
1729 (unsigned long long)tsf);
1732 * Sometimes the HW will give us a wrong tstamp in the rx
1733 * status, causing the timestamp extension to go wrong.
1734 * (This seems to happen especially with beacon frames bigger
1735 * than 78 byte (incl. FCS))
1736 * But we know that the receive timestamp must be later than the
1737 * timestamp of the beacon since HW must have synced to that.
1739 * NOTE: here we assume mactime to be after the frame was
1740 * received, not like mac80211 which defines it at the start.
1742 if (bc_tstamp > rxs->mactime) {
1743 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1744 "fixing mactime from %llx to %llx\n",
1745 (unsigned long long)rxs->mactime,
1746 (unsigned long long)tsf);
1751 * Local TSF might have moved higher than our beacon timers,
1752 * in that case we have to update them to continue sending
1753 * beacons. This also takes care of synchronizing beacon sending
1754 * times with other stations.
1756 if (hw_tu >= sc->nexttbtt)
1757 ath5k_beacon_update_timers(sc, bc_tstamp);
1762 ath5k_tasklet_rx(unsigned long data)
1764 struct ieee80211_rx_status rxs = {};
1765 struct ath5k_rx_status rs = {};
1766 struct sk_buff *skb, *next_skb;
1767 dma_addr_t next_skb_addr;
1768 struct ath5k_softc *sc = (void *)data;
1769 struct ath5k_buf *bf;
1770 struct ath5k_desc *ds;
1775 spin_lock(&sc->rxbuflock);
1776 if (list_empty(&sc->rxbuf)) {
1777 ATH5K_WARN(sc, "empty rx buf pool\n");
1783 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1784 BUG_ON(bf->skb == NULL);
1788 /* bail if HW is still using self-linked descriptor */
1789 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1792 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1793 if (unlikely(ret == -EINPROGRESS))
1795 else if (unlikely(ret)) {
1796 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1797 spin_unlock(&sc->rxbuflock);
1801 if (unlikely(rs.rs_more)) {
1802 ATH5K_WARN(sc, "unsupported jumbo\n");
1806 if (unlikely(rs.rs_status)) {
1807 if (rs.rs_status & AR5K_RXERR_PHY)
1809 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1811 * Decrypt error. If the error occurred
1812 * because there was no hardware key, then
1813 * let the frame through so the upper layers
1814 * can process it. This is necessary for 5210
1815 * parts which have no way to setup a ``clear''
1818 * XXX do key cache faulting
1820 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1821 !(rs.rs_status & AR5K_RXERR_CRC))
1824 if (rs.rs_status & AR5K_RXERR_MIC) {
1825 rxs.flag |= RX_FLAG_MMIC_ERROR;
1829 /* let crypto-error packets fall through in MNTR */
1831 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1832 sc->opmode != NL80211_IFTYPE_MONITOR)
1836 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1839 * If we can't replace bf->skb with a new skb under memory
1840 * pressure, just skip this packet
1845 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1846 PCI_DMA_FROMDEVICE);
1847 skb_put(skb, rs.rs_datalen);
1849 /* The MAC header is padded to have 32-bit boundary if the
1850 * packet payload is non-zero. The general calculation for
1851 * padsize would take into account odd header lengths:
1852 * padsize = (4 - hdrlen % 4) % 4; However, since only
1853 * even-length headers are used, padding can only be 0 or 2
1854 * bytes and we can optimize this a bit. In addition, we must
1855 * not try to remove padding from short control frames that do
1856 * not have payload. */
1857 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1858 padsize = ath5k_pad_size(hdrlen);
1860 memmove(skb->data + padsize, skb->data, hdrlen);
1861 skb_pull(skb, padsize);
1865 * always extend the mac timestamp, since this information is
1866 * also needed for proper IBSS merging.
1868 * XXX: it might be too late to do it here, since rs_tstamp is
1869 * 15bit only. that means TSF extension has to be done within
1870 * 32768usec (about 32ms). it might be necessary to move this to
1871 * the interrupt handler, like it is done in madwifi.
1873 * Unfortunately we don't know when the hardware takes the rx
1874 * timestamp (beginning of phy frame, data frame, end of rx?).
1875 * The only thing we know is that it is hardware specific...
1876 * On AR5213 it seems the rx timestamp is at the end of the
1877 * frame, but i'm not sure.
1879 * NOTE: mac80211 defines mactime at the beginning of the first
1880 * data symbol. Since we don't have any time references it's
1881 * impossible to comply to that. This affects IBSS merge only
1882 * right now, so it's not too bad...
1884 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1885 rxs.flag |= RX_FLAG_TSFT;
1887 rxs.freq = sc->curchan->center_freq;
1888 rxs.band = sc->curband->band;
1890 rxs.noise = sc->ah->ah_noise_floor;
1891 rxs.signal = rxs.noise + rs.rs_rssi;
1893 /* An rssi of 35 indicates you should be able use
1894 * 54 Mbps reliably. A more elaborate scheme can be used
1895 * here but it requires a map of SNR/throughput for each
1896 * possible mode used */
1897 rxs.qual = rs.rs_rssi * 100 / 35;
1899 /* rssi can be more than 35 though, anything above that
1900 * should be considered at 100% */
1904 rxs.antenna = rs.rs_antenna;
1905 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1906 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1908 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1909 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1910 rxs.flag |= RX_FLAG_SHORTPRE;
1912 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1914 /* check beacons in IBSS mode */
1915 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1916 ath5k_check_ibss_tsf(sc, skb, &rxs);
1918 memcpy(IEEE80211_SKB_RXCB(skb), &rxs, sizeof(rxs));
1919 ieee80211_rx(sc->hw, skb);
1922 bf->skbaddr = next_skb_addr;
1924 list_move_tail(&bf->list, &sc->rxbuf);
1925 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1927 spin_unlock(&sc->rxbuflock);
1938 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1940 struct ath5k_tx_status ts = {};
1941 struct ath5k_buf *bf, *bf0;
1942 struct ath5k_desc *ds;
1943 struct sk_buff *skb;
1944 struct ieee80211_tx_info *info;
1947 spin_lock(&txq->lock);
1948 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1951 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1952 if (unlikely(ret == -EINPROGRESS))
1954 else if (unlikely(ret)) {
1955 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1961 info = IEEE80211_SKB_CB(skb);
1964 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1967 ieee80211_tx_info_clear_status(info);
1968 for (i = 0; i < 4; i++) {
1969 struct ieee80211_tx_rate *r =
1970 &info->status.rates[i];
1972 if (ts.ts_rate[i]) {
1973 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1974 r->count = ts.ts_retry[i];
1981 /* count the successful attempt as well */
1982 info->status.rates[ts.ts_final_idx].count++;
1984 if (unlikely(ts.ts_status)) {
1985 sc->ll_stats.dot11ACKFailureCount++;
1986 if (ts.ts_status & AR5K_TXERR_FILT)
1987 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1989 info->flags |= IEEE80211_TX_STAT_ACK;
1990 info->status.ack_signal = ts.ts_rssi;
1993 ieee80211_tx_status(sc->hw, skb);
1994 sc->tx_stats[txq->qnum].count++;
1996 spin_lock(&sc->txbuflock);
1997 sc->tx_stats[txq->qnum].len--;
1998 list_move_tail(&bf->list, &sc->txbuf);
2000 spin_unlock(&sc->txbuflock);
2002 if (likely(list_empty(&txq->q)))
2004 spin_unlock(&txq->lock);
2005 if (sc->txbuf_len > ATH_TXBUF / 5)
2006 ieee80211_wake_queues(sc->hw);
2010 ath5k_tasklet_tx(unsigned long data)
2012 struct ath5k_softc *sc = (void *)data;
2014 ath5k_tx_processq(sc, sc->txq);
2023 * Setup the beacon frame for transmit.
2026 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2028 struct sk_buff *skb = bf->skb;
2029 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2030 struct ath5k_hw *ah = sc->ah;
2031 struct ath5k_desc *ds;
2036 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2038 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2039 "skbaddr %llx\n", skb, skb->data, skb->len,
2040 (unsigned long long)bf->skbaddr);
2041 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2042 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2047 antenna = ah->ah_tx_ant;
2049 flags = AR5K_TXDESC_NOACK;
2050 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2051 ds->ds_link = bf->daddr; /* self-linked */
2052 flags |= AR5K_TXDESC_VEOL;
2057 * If we use multiple antennas on AP and use
2058 * the Sectored AP scenario, switch antenna every
2059 * 4 beacons to make sure everybody hears our AP.
2060 * When a client tries to associate, hw will keep
2061 * track of the tx antenna to be used for this client
2062 * automaticaly, based on ACKed packets.
2064 * Note: AP still listens and transmits RTS on the
2065 * default antenna which is supposed to be an omni.
2067 * Note2: On sectored scenarios it's possible to have
2068 * multiple antennas (1omni -the default- and 14 sectors)
2069 * so if we choose to actually support this mode we need
2070 * to allow user to set how many antennas we have and tweak
2071 * the code below to send beacons on all of them.
2073 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2074 antenna = sc->bsent & 4 ? 2 : 1;
2077 /* FIXME: If we are in g mode and rate is a CCK rate
2078 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2079 * from tx power (value is in dB units already) */
2080 ds->ds_data = bf->skbaddr;
2081 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2082 ieee80211_get_hdrlen_from_skb(skb),
2083 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2084 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2085 1, AR5K_TXKEYIX_INVALID,
2086 antenna, flags, 0, 0);
2092 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2096 static void ath5k_beacon_disable(struct ath5k_softc *sc)
2098 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2099 ath5k_hw_set_imr(sc->ah, sc->imask);
2100 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2104 * Transmit a beacon frame at SWBA. Dynamic updates to the
2105 * frame contents are done as needed and the slot time is
2106 * also adjusted based on current state.
2108 * This is called from software irq context (beacontq or restq
2109 * tasklets) or user context from ath5k_beacon_config.
2112 ath5k_beacon_send(struct ath5k_softc *sc)
2114 struct ath5k_buf *bf = sc->bbuf;
2115 struct ath5k_hw *ah = sc->ah;
2116 struct sk_buff *skb;
2118 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2120 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2121 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2122 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2126 * Check if the previous beacon has gone out. If
2127 * not don't don't try to post another, skip this
2128 * period and wait for the next. Missed beacons
2129 * indicate a problem and should not occur. If we
2130 * miss too many consecutive beacons reset the device.
2132 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2134 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2135 "missed %u consecutive beacons\n", sc->bmisscount);
2136 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2137 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2138 "stuck beacon time (%u missed)\n",
2140 tasklet_schedule(&sc->restq);
2144 if (unlikely(sc->bmisscount != 0)) {
2145 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2146 "resume beacon xmit after %u misses\n",
2152 * Stop any current dma and put the new frame on the queue.
2153 * This should never fail since we check above that no frames
2154 * are still pending on the queue.
2156 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2157 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2158 /* NB: hw still stops DMA, so proceed */
2161 /* refresh the beacon for AP mode */
2162 if (sc->opmode == NL80211_IFTYPE_AP)
2163 ath5k_beacon_update(sc->hw, sc->vif);
2165 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2166 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2167 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2168 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2170 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2172 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2173 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2181 * ath5k_beacon_update_timers - update beacon timers
2183 * @sc: struct ath5k_softc pointer we are operating on
2184 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2185 * beacon timer update based on the current HW TSF.
2187 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2188 * of a received beacon or the current local hardware TSF and write it to the
2189 * beacon timer registers.
2191 * This is called in a variety of situations, e.g. when a beacon is received,
2192 * when a TSF update has been detected, but also when an new IBSS is created or
2193 * when we otherwise know we have to update the timers, but we keep it in this
2194 * function to have it all together in one place.
2197 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2199 struct ath5k_hw *ah = sc->ah;
2200 u32 nexttbtt, intval, hw_tu, bc_tu;
2203 intval = sc->bintval & AR5K_BEACON_PERIOD;
2204 if (WARN_ON(!intval))
2207 /* beacon TSF converted to TU */
2208 bc_tu = TSF_TO_TU(bc_tsf);
2210 /* current TSF converted to TU */
2211 hw_tsf = ath5k_hw_get_tsf64(ah);
2212 hw_tu = TSF_TO_TU(hw_tsf);
2215 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2218 * no beacons received, called internally.
2219 * just need to refresh timers based on HW TSF.
2221 nexttbtt = roundup(hw_tu + FUDGE, intval);
2222 } else if (bc_tsf == 0) {
2224 * no beacon received, probably called by ath5k_reset_tsf().
2225 * reset TSF to start with 0.
2228 intval |= AR5K_BEACON_RESET_TSF;
2229 } else if (bc_tsf > hw_tsf) {
2231 * beacon received, SW merge happend but HW TSF not yet updated.
2232 * not possible to reconfigure timers yet, but next time we
2233 * receive a beacon with the same BSSID, the hardware will
2234 * automatically update the TSF and then we need to reconfigure
2237 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2238 "need to wait for HW TSF sync\n");
2242 * most important case for beacon synchronization between STA.
2244 * beacon received and HW TSF has been already updated by HW.
2245 * update next TBTT based on the TSF of the beacon, but make
2246 * sure it is ahead of our local TSF timer.
2248 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2252 sc->nexttbtt = nexttbtt;
2254 intval |= AR5K_BEACON_ENA;
2255 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2258 * debugging output last in order to preserve the time critical aspect
2262 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2263 "reconfigured timers based on HW TSF\n");
2264 else if (bc_tsf == 0)
2265 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2266 "reset HW TSF and timers\n");
2268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2269 "updated timers based on beacon TSF\n");
2271 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2272 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2273 (unsigned long long) bc_tsf,
2274 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2275 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2276 intval & AR5K_BEACON_PERIOD,
2277 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2278 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2283 * ath5k_beacon_config - Configure the beacon queues and interrupts
2285 * @sc: struct ath5k_softc pointer we are operating on
2287 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2288 * interrupts to detect TSF updates only.
2291 ath5k_beacon_config(struct ath5k_softc *sc)
2293 struct ath5k_hw *ah = sc->ah;
2294 unsigned long flags;
2296 ath5k_hw_set_imr(ah, 0);
2298 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2300 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2301 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2302 sc->opmode == NL80211_IFTYPE_AP) {
2304 * In IBSS mode we use a self-linked tx descriptor and let the
2305 * hardware send the beacons automatically. We have to load it
2307 * We use the SWBA interrupt only to keep track of the beacon
2308 * timers in order to detect automatic TSF updates.
2310 ath5k_beaconq_config(sc);
2312 sc->imask |= AR5K_INT_SWBA;
2314 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2315 if (ath5k_hw_hasveol(ah)) {
2316 spin_lock_irqsave(&sc->block, flags);
2317 ath5k_beacon_send(sc);
2318 spin_unlock_irqrestore(&sc->block, flags);
2321 ath5k_beacon_update_timers(sc, -1);
2324 ath5k_hw_set_imr(ah, sc->imask);
2327 static void ath5k_tasklet_beacon(unsigned long data)
2329 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2332 * Software beacon alert--time to send a beacon.
2334 * In IBSS mode we use this interrupt just to
2335 * keep track of the next TBTT (target beacon
2336 * transmission time) in order to detect wether
2337 * automatic TSF updates happened.
2339 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2340 /* XXX: only if VEOL suppported */
2341 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2342 sc->nexttbtt += sc->bintval;
2343 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2344 "SWBA nexttbtt: %x hw_tu: %x "
2348 (unsigned long long) tsf);
2350 spin_lock(&sc->block);
2351 ath5k_beacon_send(sc);
2352 spin_unlock(&sc->block);
2357 /********************\
2358 * Interrupt handling *
2359 \********************/
2362 ath5k_init(struct ath5k_softc *sc)
2364 struct ath5k_hw *ah = sc->ah;
2367 mutex_lock(&sc->lock);
2369 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2372 * Stop anything previously setup. This is safe
2373 * no matter this is the first time through or not.
2375 ath5k_stop_locked(sc);
2378 * The basic interface to setting the hardware in a good
2379 * state is ``reset''. On return the hardware is known to
2380 * be powered up and with interrupts disabled. This must
2381 * be followed by initialization of the appropriate bits
2382 * and then setup of the interrupt mask.
2384 sc->curchan = sc->hw->conf.channel;
2385 sc->curband = &sc->sbands[sc->curchan->band];
2386 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2387 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2388 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2389 ret = ath5k_reset(sc, NULL);
2393 ath5k_rfkill_hw_start(ah);
2396 * Reset the key cache since some parts do not reset the
2397 * contents on initial power up or resume from suspend.
2399 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2400 ath5k_hw_reset_key(ah, i);
2402 /* Set ack to be sent at low bit-rates */
2403 ath5k_hw_set_ack_bitrate_high(ah, false);
2405 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2406 msecs_to_jiffies(ath5k_calinterval * 1000)));
2411 mutex_unlock(&sc->lock);
2416 ath5k_stop_locked(struct ath5k_softc *sc)
2418 struct ath5k_hw *ah = sc->ah;
2420 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2421 test_bit(ATH_STAT_INVALID, sc->status));
2424 * Shutdown the hardware and driver:
2425 * stop output from above
2426 * disable interrupts
2428 * turn off the radio
2429 * clear transmit machinery
2430 * clear receive machinery
2431 * drain and release tx queues
2432 * reclaim beacon resources
2433 * power down hardware
2435 * Note that some of this work is not possible if the
2436 * hardware is gone (invalid).
2438 ieee80211_stop_queues(sc->hw);
2440 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2442 ath5k_hw_set_imr(ah, 0);
2443 synchronize_irq(sc->pdev->irq);
2445 ath5k_txq_cleanup(sc);
2446 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2448 ath5k_hw_phy_disable(ah);
2456 * Stop the device, grabbing the top-level lock to protect
2457 * against concurrent entry through ath5k_init (which can happen
2458 * if another thread does a system call and the thread doing the
2459 * stop is preempted).
2462 ath5k_stop_hw(struct ath5k_softc *sc)
2466 mutex_lock(&sc->lock);
2467 ret = ath5k_stop_locked(sc);
2468 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2470 * Set the chip in full sleep mode. Note that we are
2471 * careful to do this only when bringing the interface
2472 * completely to a stop. When the chip is in this state
2473 * it must be carefully woken up or references to
2474 * registers in the PCI clock domain may freeze the bus
2475 * (and system). This varies by chip and is mostly an
2476 * issue with newer parts that go to sleep more quickly.
2478 if (sc->ah->ah_mac_srev >= 0x78) {
2481 * don't put newer MAC revisions > 7.8 to sleep because
2482 * of the above mentioned problems
2484 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2485 "not putting device to sleep\n");
2487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2488 "putting device to full sleep\n");
2489 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2492 ath5k_txbuf_free(sc, sc->bbuf);
2495 mutex_unlock(&sc->lock);
2497 del_timer_sync(&sc->calib_tim);
2498 tasklet_kill(&sc->rxtq);
2499 tasklet_kill(&sc->txtq);
2500 tasklet_kill(&sc->restq);
2501 tasklet_kill(&sc->beacontq);
2503 ath5k_rfkill_hw_stop(sc->ah);
2509 ath5k_intr(int irq, void *dev_id)
2511 struct ath5k_softc *sc = dev_id;
2512 struct ath5k_hw *ah = sc->ah;
2513 enum ath5k_int status;
2514 unsigned int counter = 1000;
2516 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2517 !ath5k_hw_is_intr_pending(ah)))
2521 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2522 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2524 if (unlikely(status & AR5K_INT_FATAL)) {
2526 * Fatal errors are unrecoverable.
2527 * Typically these are caused by DMA errors.
2529 tasklet_schedule(&sc->restq);
2530 } else if (unlikely(status & AR5K_INT_RXORN)) {
2531 tasklet_schedule(&sc->restq);
2533 if (status & AR5K_INT_SWBA) {
2534 tasklet_hi_schedule(&sc->beacontq);
2536 if (status & AR5K_INT_RXEOL) {
2538 * NB: the hardware should re-read the link when
2539 * RXE bit is written, but it doesn't work at
2540 * least on older hardware revs.
2544 if (status & AR5K_INT_TXURN) {
2545 /* bump tx trigger level */
2546 ath5k_hw_update_tx_triglevel(ah, true);
2548 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2549 tasklet_schedule(&sc->rxtq);
2550 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2551 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2552 tasklet_schedule(&sc->txtq);
2553 if (status & AR5K_INT_BMISS) {
2556 if (status & AR5K_INT_MIB) {
2558 * These stats are also used for ANI i think
2559 * so how about updating them more often ?
2561 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2563 if (status & AR5K_INT_GPIO)
2564 tasklet_schedule(&sc->rf_kill.toggleq);
2567 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2569 if (unlikely(!counter))
2570 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2576 ath5k_tasklet_reset(unsigned long data)
2578 struct ath5k_softc *sc = (void *)data;
2580 ath5k_reset_wake(sc);
2584 * Periodically recalibrate the PHY to account
2585 * for temperature/environment changes.
2588 ath5k_calibrate(unsigned long data)
2590 struct ath5k_softc *sc = (void *)data;
2591 struct ath5k_hw *ah = sc->ah;
2593 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2594 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2595 sc->curchan->hw_value);
2597 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2599 * Rfgain is out of bounds, reset the chip
2600 * to load new gain values.
2602 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2603 ath5k_reset_wake(sc);
2605 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2606 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2607 ieee80211_frequency_to_channel(
2608 sc->curchan->center_freq));
2610 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2611 msecs_to_jiffies(ath5k_calinterval * 1000)));
2615 /********************\
2616 * Mac80211 functions *
2617 \********************/
2620 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2622 struct ath5k_softc *sc = hw->priv;
2624 return ath5k_tx_queue(hw, skb, sc->txq);
2627 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2628 struct ath5k_txq *txq)
2630 struct ath5k_softc *sc = hw->priv;
2631 struct ath5k_buf *bf;
2632 unsigned long flags;
2636 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2638 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2639 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2642 * the hardware expects the header padded to 4 byte boundaries
2643 * if this is not the case we add the padding after the header
2645 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2646 padsize = ath5k_pad_size(hdrlen);
2649 if (skb_headroom(skb) < padsize) {
2650 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2651 " headroom to pad %d\n", hdrlen, padsize);
2654 skb_push(skb, padsize);
2655 memmove(skb->data, skb->data+padsize, hdrlen);
2658 spin_lock_irqsave(&sc->txbuflock, flags);
2659 if (list_empty(&sc->txbuf)) {
2660 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2661 spin_unlock_irqrestore(&sc->txbuflock, flags);
2662 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2665 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2666 list_del(&bf->list);
2668 if (list_empty(&sc->txbuf))
2669 ieee80211_stop_queues(hw);
2670 spin_unlock_irqrestore(&sc->txbuflock, flags);
2674 if (ath5k_txbuf_setup(sc, bf, txq)) {
2676 spin_lock_irqsave(&sc->txbuflock, flags);
2677 list_add_tail(&bf->list, &sc->txbuf);
2679 spin_unlock_irqrestore(&sc->txbuflock, flags);
2682 return NETDEV_TX_OK;
2685 dev_kfree_skb_any(skb);
2686 return NETDEV_TX_OK;
2690 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2691 * and change to the given channel.
2694 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2696 struct ath5k_hw *ah = sc->ah;
2699 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2702 ath5k_hw_set_imr(ah, 0);
2703 ath5k_txq_cleanup(sc);
2707 sc->curband = &sc->sbands[chan->band];
2709 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2711 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2715 ret = ath5k_rx_start(sc);
2717 ATH5K_ERR(sc, "can't start recv logic\n");
2722 * Change channels and update the h/w rate map if we're switching;
2723 * e.g. 11a to 11b/g.
2725 * We may be doing a reset in response to an ioctl that changes the
2726 * channel so update any state that might change as a result.
2730 /* ath5k_chan_change(sc, c); */
2732 ath5k_beacon_config(sc);
2733 /* intrs are enabled by ath5k_beacon_config */
2741 ath5k_reset_wake(struct ath5k_softc *sc)
2745 ret = ath5k_reset(sc, sc->curchan);
2747 ieee80211_wake_queues(sc->hw);
2752 static int ath5k_start(struct ieee80211_hw *hw)
2754 return ath5k_init(hw->priv);
2757 static void ath5k_stop(struct ieee80211_hw *hw)
2759 ath5k_stop_hw(hw->priv);
2762 static int ath5k_add_interface(struct ieee80211_hw *hw,
2763 struct ieee80211_if_init_conf *conf)
2765 struct ath5k_softc *sc = hw->priv;
2768 mutex_lock(&sc->lock);
2774 sc->vif = conf->vif;
2776 switch (conf->type) {
2777 case NL80211_IFTYPE_AP:
2778 case NL80211_IFTYPE_STATION:
2779 case NL80211_IFTYPE_ADHOC:
2780 case NL80211_IFTYPE_MESH_POINT:
2781 case NL80211_IFTYPE_MONITOR:
2782 sc->opmode = conf->type;
2789 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2793 mutex_unlock(&sc->lock);
2798 ath5k_remove_interface(struct ieee80211_hw *hw,
2799 struct ieee80211_if_init_conf *conf)
2801 struct ath5k_softc *sc = hw->priv;
2802 u8 mac[ETH_ALEN] = {};
2804 mutex_lock(&sc->lock);
2805 if (sc->vif != conf->vif)
2808 ath5k_hw_set_lladdr(sc->ah, mac);
2809 ath5k_beacon_disable(sc);
2812 mutex_unlock(&sc->lock);
2816 * TODO: Phy disable/diversity etc
2819 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2821 struct ath5k_softc *sc = hw->priv;
2822 struct ath5k_hw *ah = sc->ah;
2823 struct ieee80211_conf *conf = &hw->conf;
2826 mutex_lock(&sc->lock);
2828 ret = ath5k_chan_set(sc, conf->channel);
2832 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2833 (sc->power_level != conf->power_level)) {
2834 sc->power_level = conf->power_level;
2837 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2841 * 1) Move this on config_interface and handle each case
2842 * separately eg. when we have only one STA vif, use
2843 * AR5K_ANTMODE_SINGLE_AP
2845 * 2) Allow the user to change antenna mode eg. when only
2846 * one antenna is present
2848 * 3) Allow the user to set default/tx antenna when possible
2850 * 4) Default mode should handle 90% of the cases, together
2851 * with fixed a/b and single AP modes we should be able to
2852 * handle 99%. Sectored modes are extreme cases and i still
2853 * haven't found a usage for them. If we decide to support them,
2854 * then we must allow the user to set how many tx antennas we
2857 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2860 mutex_unlock(&sc->lock);
2864 #define SUPPORTED_FIF_FLAGS \
2865 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2866 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2867 FIF_BCN_PRBRESP_PROMISC
2869 * o always accept unicast, broadcast, and multicast traffic
2870 * o multicast traffic for all BSSIDs will be enabled if mac80211
2872 * o maintain current state of phy ofdm or phy cck error reception.
2873 * If the hardware detects any of these type of errors then
2874 * ath5k_hw_get_rx_filter() will pass to us the respective
2875 * hardware filters to be able to receive these type of frames.
2876 * o probe request frames are accepted only when operating in
2877 * hostap, adhoc, or monitor modes
2878 * o enable promiscuous mode according to the interface state
2880 * - when operating in adhoc mode so the 802.11 layer creates
2881 * node table entries for peers,
2882 * - when operating in station mode for collecting rssi data when
2883 * the station is otherwise quiet, or
2886 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2887 unsigned int changed_flags,
2888 unsigned int *new_flags,
2889 int mc_count, struct dev_mc_list *mclist)
2891 struct ath5k_softc *sc = hw->priv;
2892 struct ath5k_hw *ah = sc->ah;
2893 u32 mfilt[2], val, rfilt;
2900 /* Only deal with supported flags */
2901 changed_flags &= SUPPORTED_FIF_FLAGS;
2902 *new_flags &= SUPPORTED_FIF_FLAGS;
2904 /* If HW detects any phy or radar errors, leave those filters on.
2905 * Also, always enable Unicast, Broadcasts and Multicast
2906 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2907 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2908 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2909 AR5K_RX_FILTER_MCAST);
2911 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2912 if (*new_flags & FIF_PROMISC_IN_BSS) {
2913 rfilt |= AR5K_RX_FILTER_PROM;
2914 __set_bit(ATH_STAT_PROMISC, sc->status);
2916 __clear_bit(ATH_STAT_PROMISC, sc->status);
2920 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2921 if (*new_flags & FIF_ALLMULTI) {
2925 for (i = 0; i < mc_count; i++) {
2928 /* calculate XOR of eight 6-bit values */
2929 val = get_unaligned_le32(mclist->dmi_addr + 0);
2930 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2931 val = get_unaligned_le32(mclist->dmi_addr + 3);
2932 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2934 mfilt[pos / 32] |= (1 << (pos % 32));
2935 /* XXX: we might be able to just do this instead,
2936 * but not sure, needs testing, if we do use this we'd
2937 * neet to inform below to not reset the mcast */
2938 /* ath5k_hw_set_mcast_filterindex(ah,
2939 * mclist->dmi_addr[5]); */
2940 mclist = mclist->next;
2944 /* This is the best we can do */
2945 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2946 rfilt |= AR5K_RX_FILTER_PHYERR;
2948 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2949 * and probes for any BSSID, this needs testing */
2950 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2951 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2953 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2954 * set we should only pass on control frames for this
2955 * station. This needs testing. I believe right now this
2956 * enables *all* control frames, which is OK.. but
2957 * but we should see if we can improve on granularity */
2958 if (*new_flags & FIF_CONTROL)
2959 rfilt |= AR5K_RX_FILTER_CONTROL;
2961 /* Additional settings per mode -- this is per ath5k */
2963 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2965 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2966 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2967 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2968 if (sc->opmode != NL80211_IFTYPE_STATION)
2969 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2970 if (sc->opmode != NL80211_IFTYPE_AP &&
2971 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2972 test_bit(ATH_STAT_PROMISC, sc->status))
2973 rfilt |= AR5K_RX_FILTER_PROM;
2974 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2975 sc->opmode == NL80211_IFTYPE_ADHOC ||
2976 sc->opmode == NL80211_IFTYPE_AP)
2977 rfilt |= AR5K_RX_FILTER_BEACON;
2978 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2979 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2980 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2983 ath5k_hw_set_rx_filter(ah, rfilt);
2985 /* Set multicast bits */
2986 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2987 /* Set the cached hw filter flags, this will alter actually
2989 sc->filter_flags = rfilt;
2993 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2994 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2995 struct ieee80211_key_conf *key)
2997 struct ath5k_softc *sc = hw->priv;
3000 if (modparam_nohwcrypt)
3014 mutex_lock(&sc->lock);
3018 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3019 sta ? sta->addr : NULL);
3021 ATH5K_ERR(sc, "can't set the key\n");
3024 __set_bit(key->keyidx, sc->keymap);
3025 key->hw_key_idx = key->keyidx;
3026 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3027 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3030 ath5k_hw_reset_key(sc->ah, key->keyidx);
3031 __clear_bit(key->keyidx, sc->keymap);
3040 mutex_unlock(&sc->lock);
3045 ath5k_get_stats(struct ieee80211_hw *hw,
3046 struct ieee80211_low_level_stats *stats)
3048 struct ath5k_softc *sc = hw->priv;
3049 struct ath5k_hw *ah = sc->ah;
3052 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3054 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3060 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3061 struct ieee80211_tx_queue_stats *stats)
3063 struct ath5k_softc *sc = hw->priv;
3065 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3071 ath5k_get_tsf(struct ieee80211_hw *hw)
3073 struct ath5k_softc *sc = hw->priv;
3075 return ath5k_hw_get_tsf64(sc->ah);
3079 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3081 struct ath5k_softc *sc = hw->priv;
3083 ath5k_hw_set_tsf64(sc->ah, tsf);
3087 ath5k_reset_tsf(struct ieee80211_hw *hw)
3089 struct ath5k_softc *sc = hw->priv;
3092 * in IBSS mode we need to update the beacon timers too.
3093 * this will also reset the TSF if we call it with 0
3095 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3096 ath5k_beacon_update_timers(sc, 0);
3098 ath5k_hw_reset_tsf(sc->ah);
3102 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3103 * this is called only once at config_bss time, for AP we do it every
3104 * SWBA interrupt so that the TIM will reflect buffered frames.
3106 * Called with the beacon lock.
3109 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3112 struct ath5k_softc *sc = hw->priv;
3113 struct sk_buff *skb;
3115 if (WARN_ON(!vif)) {
3120 skb = ieee80211_beacon_get(hw, vif);
3127 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3129 ath5k_txbuf_free(sc, sc->bbuf);
3130 sc->bbuf->skb = skb;
3131 ret = ath5k_beacon_setup(sc, sc->bbuf);
3133 sc->bbuf->skb = NULL;
3139 * Update the beacon and reconfigure the beacon queues.
3142 ath5k_beacon_reconfig(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3145 unsigned long flags;
3146 struct ath5k_softc *sc = hw->priv;
3148 spin_lock_irqsave(&sc->block, flags);
3149 ret = ath5k_beacon_update(hw, vif);
3150 spin_unlock_irqrestore(&sc->block, flags);
3152 ath5k_beacon_config(sc);
3158 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3160 struct ath5k_softc *sc = hw->priv;
3161 struct ath5k_hw *ah = sc->ah;
3163 rfilt = ath5k_hw_get_rx_filter(ah);
3165 rfilt |= AR5K_RX_FILTER_BEACON;
3167 rfilt &= ~AR5K_RX_FILTER_BEACON;
3168 ath5k_hw_set_rx_filter(ah, rfilt);
3169 sc->filter_flags = rfilt;
3172 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3173 struct ieee80211_vif *vif,
3174 struct ieee80211_bss_conf *bss_conf,
3177 struct ath5k_softc *sc = hw->priv;
3178 struct ath5k_hw *ah = sc->ah;
3180 mutex_lock(&sc->lock);
3181 if (WARN_ON(sc->vif != vif))
3184 if (changes & BSS_CHANGED_BSSID) {
3185 /* Cache for later use during resets */
3186 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3187 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3188 * a clean way of letting us retrieve this yet. */
3189 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3193 if (changes & BSS_CHANGED_BEACON_INT)
3194 sc->bintval = bss_conf->beacon_int;
3196 if (changes & BSS_CHANGED_ASSOC) {
3197 sc->assoc = bss_conf->assoc;
3198 if (sc->opmode == NL80211_IFTYPE_STATION)
3199 set_beacon_filter(hw, sc->assoc);
3200 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3201 AR5K_LED_ASSOC : AR5K_LED_INIT);
3204 if (changes & BSS_CHANGED_BEACON &&
3205 (vif->type == NL80211_IFTYPE_ADHOC ||
3206 vif->type == NL80211_IFTYPE_MESH_POINT ||
3207 vif->type == NL80211_IFTYPE_AP)) {
3208 ath5k_beacon_reconfig(hw, vif);
3212 mutex_unlock(&sc->lock);
3215 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3217 struct ath5k_softc *sc = hw->priv;
3219 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3222 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3224 struct ath5k_softc *sc = hw->priv;
3225 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3226 AR5K_LED_ASSOC : AR5K_LED_INIT);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob