2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
200 static int ath5k_pci_resume(struct pci_dev *pdev);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static const struct ieee80211_ops ath5k_hw_ops = {
260 .start = ath5k_start,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
265 .prepare_multicast = ath5k_prepare_multicast,
266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
270 .get_tx_stats = ath5k_get_tx_stats,
271 .get_tsf = ath5k_get_tsf,
272 .set_tsf = ath5k_set_tsf,
273 .reset_tsf = ath5k_reset_tsf,
274 .bss_info_changed = ath5k_bss_info_changed,
275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
280 * Prototypes - Internal functions
283 static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285 static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287 /* Channel/mode setup */
288 static inline short ath5k_ieee2mhz(short chan);
289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
293 static int ath5k_setup_bands(struct ieee80211_hw *hw);
294 static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296 static void ath5k_setcurmode(struct ath5k_softc *sc,
298 static void ath5k_mode_setup(struct ath5k_softc *sc);
300 /* Descriptor setup */
301 static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303 static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
319 dev_kfree_skb_any(bf->skb);
323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
329 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
331 dev_kfree_skb_any(bf->skb);
337 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
338 int qtype, int subtype);
339 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
340 static int ath5k_beaconq_config(struct ath5k_softc *sc);
341 static void ath5k_txq_drainq(struct ath5k_softc *sc,
342 struct ath5k_txq *txq);
343 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
344 static void ath5k_txq_release(struct ath5k_softc *sc);
346 static int ath5k_rx_start(struct ath5k_softc *sc);
347 static void ath5k_rx_stop(struct ath5k_softc *sc);
348 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
349 struct ath5k_desc *ds,
351 struct ath5k_rx_status *rs);
352 static void ath5k_tasklet_rx(unsigned long data);
354 static void ath5k_tx_processq(struct ath5k_softc *sc,
355 struct ath5k_txq *txq);
356 static void ath5k_tasklet_tx(unsigned long data);
357 /* Beacon handling */
358 static int ath5k_beacon_setup(struct ath5k_softc *sc,
359 struct ath5k_buf *bf);
360 static void ath5k_beacon_send(struct ath5k_softc *sc);
361 static void ath5k_beacon_config(struct ath5k_softc *sc);
362 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
363 static void ath5k_tasklet_beacon(unsigned long data);
365 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
367 u64 tsf = ath5k_hw_get_tsf64(ah);
369 if ((tsf & 0x7fff) < rstamp)
372 return (tsf & ~0x7fff) | rstamp;
375 /* Interrupt handling */
376 static int ath5k_init(struct ath5k_softc *sc);
377 static int ath5k_stop_locked(struct ath5k_softc *sc);
378 static int ath5k_stop_hw(struct ath5k_softc *sc);
379 static irqreturn_t ath5k_intr(int irq, void *dev_id);
380 static void ath5k_tasklet_reset(unsigned long data);
382 static void ath5k_tasklet_calibrate(unsigned long data);
385 * Module init/exit functions
394 ret = pci_register_driver(&ath5k_pci_driver);
396 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
406 pci_unregister_driver(&ath5k_pci_driver);
408 ath5k_debug_finish();
411 module_init(init_ath5k_pci);
412 module_exit(exit_ath5k_pci);
415 /********************\
416 * PCI Initialization *
417 \********************/
420 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
422 const char *name = "xxxxx";
425 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
426 if (srev_names[i].sr_type != type)
429 if ((val & 0xf0) == srev_names[i].sr_val)
430 name = srev_names[i].sr_name;
432 if ((val & 0xff) == srev_names[i].sr_val) {
433 name = srev_names[i].sr_name;
442 ath5k_pci_probe(struct pci_dev *pdev,
443 const struct pci_device_id *id)
446 struct ath5k_softc *sc;
447 struct ath_common *common;
448 struct ieee80211_hw *hw;
452 ret = pci_enable_device(pdev);
454 dev_err(&pdev->dev, "can't enable device\n");
458 /* XXX 32-bit addressing only */
459 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
461 dev_err(&pdev->dev, "32-bit DMA not available\n");
466 * Cache line size is used to size and align various
467 * structures used to communicate with the hardware.
469 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
472 * Linux 2.4.18 (at least) writes the cache line size
473 * register as a 16-bit wide register which is wrong.
474 * We must have this setup properly for rx buffer
475 * DMA to work so force a reasonable value here if it
478 csz = L1_CACHE_BYTES >> 2;
479 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
482 * The default setting of latency timer yields poor results,
483 * set it to the value used by other systems. It may be worth
484 * tweaking this setting more.
486 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
488 /* Enable bus mastering */
489 pci_set_master(pdev);
492 * Disable the RETRY_TIMEOUT register (0x41) to keep
493 * PCI Tx retries from interfering with C3 CPU state.
495 pci_write_config_byte(pdev, 0x41, 0);
497 ret = pci_request_region(pdev, 0, "ath5k");
499 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
503 mem = pci_iomap(pdev, 0, 0);
505 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
511 * Allocate hw (mac80211 main struct)
512 * and hw->priv (driver private data)
514 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
516 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
521 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
523 /* Initialize driver private data */
524 SET_IEEE80211_DEV(hw, &pdev->dev);
525 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
526 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
527 IEEE80211_HW_SIGNAL_DBM |
528 IEEE80211_HW_NOISE_DBM;
530 hw->wiphy->interface_modes =
531 BIT(NL80211_IFTYPE_AP) |
532 BIT(NL80211_IFTYPE_STATION) |
533 BIT(NL80211_IFTYPE_ADHOC) |
534 BIT(NL80211_IFTYPE_MESH_POINT);
536 hw->extra_tx_headroom = 2;
537 hw->channel_change_time = 5000;
542 ath5k_debug_init_device(sc);
545 * Mark the device as detached to avoid processing
546 * interrupts until setup is complete.
548 __set_bit(ATH_STAT_INVALID, sc->status);
550 sc->iobase = mem; /* So we can unmap it on detach */
551 sc->opmode = NL80211_IFTYPE_STATION;
553 mutex_init(&sc->lock);
554 spin_lock_init(&sc->rxbuflock);
555 spin_lock_init(&sc->txbuflock);
556 spin_lock_init(&sc->block);
558 /* Set private data */
559 pci_set_drvdata(pdev, hw);
561 /* Setup interrupt handler */
562 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
564 ATH5K_ERR(sc, "request_irq failed\n");
568 /*If we passed the test malloc a ath5k_hw struct*/
569 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
572 ATH5K_ERR(sc, "out of memory\n");
577 sc->ah->ah_iobase = sc->iobase;
578 common = ath5k_hw_common(sc->ah);
579 common->cachelsz = csz << 2; /* convert to bytes */
581 /* Initialize device */
582 ret = ath5k_hw_attach(sc);
587 /* set up multi-rate retry capabilities */
588 if (sc->ah->ah_version == AR5K_AR5212) {
590 hw->max_rate_tries = 11;
593 /* Finish private driver data initialization */
594 ret = ath5k_attach(pdev, hw);
598 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
599 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
601 sc->ah->ah_phy_revision);
603 if (!sc->ah->ah_single_chip) {
604 /* Single chip radio (!RF5111) */
605 if (sc->ah->ah_radio_5ghz_revision &&
606 !sc->ah->ah_radio_2ghz_revision) {
607 /* No 5GHz support -> report 2GHz radio */
608 if (!test_bit(AR5K_MODE_11A,
609 sc->ah->ah_capabilities.cap_mode)) {
610 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
614 /* No 2GHz support (5110 and some
615 * 5Ghz only cards) -> report 5Ghz radio */
616 } else if (!test_bit(AR5K_MODE_11B,
617 sc->ah->ah_capabilities.cap_mode)) {
618 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
619 ath5k_chip_name(AR5K_VERSION_RAD,
620 sc->ah->ah_radio_5ghz_revision),
621 sc->ah->ah_radio_5ghz_revision);
622 /* Multiband radio */
624 ATH5K_INFO(sc, "RF%s multiband radio found"
626 ath5k_chip_name(AR5K_VERSION_RAD,
627 sc->ah->ah_radio_5ghz_revision),
628 sc->ah->ah_radio_5ghz_revision);
631 /* Multi chip radio (RF5111 - RF2111) ->
632 * report both 2GHz/5GHz radios */
633 else if (sc->ah->ah_radio_5ghz_revision &&
634 sc->ah->ah_radio_2ghz_revision){
635 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
636 ath5k_chip_name(AR5K_VERSION_RAD,
637 sc->ah->ah_radio_5ghz_revision),
638 sc->ah->ah_radio_5ghz_revision);
639 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
640 ath5k_chip_name(AR5K_VERSION_RAD,
641 sc->ah->ah_radio_2ghz_revision),
642 sc->ah->ah_radio_2ghz_revision);
647 /* ready to process interrupts */
648 __clear_bit(ATH_STAT_INVALID, sc->status);
652 ath5k_hw_detach(sc->ah);
654 free_irq(pdev->irq, sc);
658 ieee80211_free_hw(hw);
660 pci_iounmap(pdev, mem);
662 pci_release_region(pdev, 0);
664 pci_disable_device(pdev);
669 static void __devexit
670 ath5k_pci_remove(struct pci_dev *pdev)
672 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
673 struct ath5k_softc *sc = hw->priv;
675 ath5k_debug_finish_device(sc);
676 ath5k_detach(pdev, hw);
677 ath5k_hw_detach(sc->ah);
679 free_irq(pdev->irq, sc);
680 pci_iounmap(pdev, sc->iobase);
681 pci_release_region(pdev, 0);
682 pci_disable_device(pdev);
683 ieee80211_free_hw(hw);
688 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
690 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
691 struct ath5k_softc *sc = hw->priv;
695 pci_save_state(pdev);
696 pci_disable_device(pdev);
697 pci_set_power_state(pdev, PCI_D3hot);
703 ath5k_pci_resume(struct pci_dev *pdev)
705 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
706 struct ath5k_softc *sc = hw->priv;
709 pci_restore_state(pdev);
711 err = pci_enable_device(pdev);
716 * Suspend/Resume resets the PCI configuration space, so we have to
717 * re-disable the RETRY_TIMEOUT register (0x41) to keep
718 * PCI Tx retries from interfering with C3 CPU state
720 pci_write_config_byte(pdev, 0x41, 0);
722 ath5k_led_enable(sc);
725 #endif /* CONFIG_PM */
728 /***********************\
729 * Driver Initialization *
730 \***********************/
732 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
734 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
735 struct ath5k_softc *sc = hw->priv;
736 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
738 return ath_reg_notifier_apply(wiphy, request, regulatory);
742 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
744 struct ath5k_softc *sc = hw->priv;
745 struct ath5k_hw *ah = sc->ah;
746 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
747 u8 mac[ETH_ALEN] = {};
750 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
753 * Check if the MAC has multi-rate retry support.
754 * We do this by trying to setup a fake extended
755 * descriptor. MAC's that don't have support will
756 * return false w/o doing anything. MAC's that do
757 * support it will return true w/o doing anything.
759 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
763 __set_bit(ATH_STAT_MRRETRY, sc->status);
766 * Collect the channel list. The 802.11 layer
767 * is resposible for filtering this list based
768 * on settings like the phy mode and regulatory
769 * domain restrictions.
771 ret = ath5k_setup_bands(hw);
773 ATH5K_ERR(sc, "can't get channels\n");
777 /* NB: setup here so ath5k_rate_update is happy */
778 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
779 ath5k_setcurmode(sc, AR5K_MODE_11A);
781 ath5k_setcurmode(sc, AR5K_MODE_11B);
784 * Allocate tx+rx descriptors and populate the lists.
786 ret = ath5k_desc_alloc(sc, pdev);
788 ATH5K_ERR(sc, "can't allocate descriptors\n");
793 * Allocate hardware transmit queues: one queue for
794 * beacon frames and one data queue for each QoS
795 * priority. Note that hw functions handle reseting
796 * these queues at the needed time.
798 ret = ath5k_beaconq_setup(ah);
800 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
804 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
805 if (IS_ERR(sc->cabq)) {
806 ATH5K_ERR(sc, "can't setup cab queue\n");
807 ret = PTR_ERR(sc->cabq);
811 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
812 if (IS_ERR(sc->txq)) {
813 ATH5K_ERR(sc, "can't setup xmit queue\n");
814 ret = PTR_ERR(sc->txq);
818 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
819 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
820 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
821 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
822 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
824 ret = ath5k_eeprom_read_mac(ah, mac);
826 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
831 SET_IEEE80211_PERM_ADDR(hw, mac);
832 /* All MAC address bits matter for ACKs */
833 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
834 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
836 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
837 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
839 ATH5K_ERR(sc, "can't initialize regulatory system\n");
843 ret = ieee80211_register_hw(hw);
845 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
849 if (!ath_is_world_regd(regulatory))
850 regulatory_hint(hw->wiphy, regulatory->alpha2);
856 ath5k_txq_release(sc);
858 ath5k_hw_release_tx_queue(ah, sc->bhalq);
860 ath5k_desc_free(sc, pdev);
866 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
868 struct ath5k_softc *sc = hw->priv;
871 * NB: the order of these is important:
872 * o call the 802.11 layer before detaching ath5k_hw to
873 * insure callbacks into the driver to delete global
874 * key cache entries can be handled
875 * o reclaim the tx queue data structures after calling
876 * the 802.11 layer as we'll get called back to reclaim
877 * node state and potentially want to use them
878 * o to cleanup the tx queues the hal is called, so detach
880 * XXX: ??? detach ath5k_hw ???
881 * Other than that, it's straightforward...
883 ieee80211_unregister_hw(hw);
884 ath5k_desc_free(sc, pdev);
885 ath5k_txq_release(sc);
886 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
887 ath5k_unregister_leds(sc);
890 * NB: can't reclaim these until after ieee80211_ifdetach
891 * returns because we'll get called back to reclaim node
892 * state and potentially want to use them.
899 /********************\
900 * Channel/mode setup *
901 \********************/
904 * Convert IEEE channel number to MHz frequency.
907 ath5k_ieee2mhz(short chan)
909 if (chan <= 14 || chan >= 27)
910 return ieee80211chan2mhz(chan);
912 return 2212 + chan * 20;
916 * Returns true for the channel numbers used without all_channels modparam.
918 static bool ath5k_is_standard_channel(short chan)
920 return ((chan <= 14) ||
922 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
924 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
926 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
930 ath5k_copy_channels(struct ath5k_hw *ah,
931 struct ieee80211_channel *channels,
935 unsigned int i, count, size, chfreq, freq, ch;
937 if (!test_bit(mode, ah->ah_modes))
942 case AR5K_MODE_11A_TURBO:
943 /* 1..220, but 2GHz frequencies are filtered by check_channel */
945 chfreq = CHANNEL_5GHZ;
949 case AR5K_MODE_11G_TURBO:
951 chfreq = CHANNEL_2GHZ;
954 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
958 for (i = 0, count = 0; i < size && max > 0; i++) {
960 freq = ath5k_ieee2mhz(ch);
962 /* Check if channel is supported by the chipset */
963 if (!ath5k_channel_ok(ah, freq, chfreq))
966 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
969 /* Write channel info and increment counter */
970 channels[count].center_freq = freq;
971 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
972 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
976 channels[count].hw_value = chfreq | CHANNEL_OFDM;
978 case AR5K_MODE_11A_TURBO:
979 case AR5K_MODE_11G_TURBO:
980 channels[count].hw_value = chfreq |
981 CHANNEL_OFDM | CHANNEL_TURBO;
984 channels[count].hw_value = CHANNEL_B;
995 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
999 for (i = 0; i < AR5K_MAX_RATES; i++)
1000 sc->rate_idx[b->band][i] = -1;
1002 for (i = 0; i < b->n_bitrates; i++) {
1003 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1004 if (b->bitrates[i].hw_value_short)
1005 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1010 ath5k_setup_bands(struct ieee80211_hw *hw)
1012 struct ath5k_softc *sc = hw->priv;
1013 struct ath5k_hw *ah = sc->ah;
1014 struct ieee80211_supported_band *sband;
1015 int max_c, count_c = 0;
1018 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1019 max_c = ARRAY_SIZE(sc->channels);
1022 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1023 sband->band = IEEE80211_BAND_2GHZ;
1024 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1026 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1028 memcpy(sband->bitrates, &ath5k_rates[0],
1029 sizeof(struct ieee80211_rate) * 12);
1030 sband->n_bitrates = 12;
1032 sband->channels = sc->channels;
1033 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1034 AR5K_MODE_11G, max_c);
1036 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1037 count_c = sband->n_channels;
1039 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1041 memcpy(sband->bitrates, &ath5k_rates[0],
1042 sizeof(struct ieee80211_rate) * 4);
1043 sband->n_bitrates = 4;
1045 /* 5211 only supports B rates and uses 4bit rate codes
1046 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1049 if (ah->ah_version == AR5K_AR5211) {
1050 for (i = 0; i < 4; i++) {
1051 sband->bitrates[i].hw_value =
1052 sband->bitrates[i].hw_value & 0xF;
1053 sband->bitrates[i].hw_value_short =
1054 sband->bitrates[i].hw_value_short & 0xF;
1058 sband->channels = sc->channels;
1059 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1060 AR5K_MODE_11B, max_c);
1062 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1063 count_c = sband->n_channels;
1066 ath5k_setup_rate_idx(sc, sband);
1068 /* 5GHz band, A mode */
1069 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1070 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1071 sband->band = IEEE80211_BAND_5GHZ;
1072 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1074 memcpy(sband->bitrates, &ath5k_rates[4],
1075 sizeof(struct ieee80211_rate) * 8);
1076 sband->n_bitrates = 8;
1078 sband->channels = &sc->channels[count_c];
1079 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1080 AR5K_MODE_11A, max_c);
1082 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1084 ath5k_setup_rate_idx(sc, sband);
1086 ath5k_debug_dump_bands(sc);
1092 * Set/change channels. We always reset the chip.
1093 * To accomplish this we must first cleanup any pending DMA,
1094 * then restart stuff after a la ath5k_init.
1096 * Called with sc->lock.
1099 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1101 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1102 sc->curchan->center_freq, chan->center_freq);
1105 * To switch channels clear any pending DMA operations;
1106 * wait long enough for the RX fifo to drain, reset the
1107 * hardware at the new frequency, and then re-enable
1108 * the relevant bits of the h/w.
1110 return ath5k_reset(sc, chan);
1114 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1118 if (mode == AR5K_MODE_11A) {
1119 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1121 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1126 ath5k_mode_setup(struct ath5k_softc *sc)
1128 struct ath5k_hw *ah = sc->ah;
1131 ah->ah_op_mode = sc->opmode;
1133 /* configure rx filter */
1134 rfilt = sc->filter_flags;
1135 ath5k_hw_set_rx_filter(ah, rfilt);
1137 if (ath5k_hw_hasbssidmask(ah))
1138 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1140 /* configure operational mode */
1141 ath5k_hw_set_opmode(ah);
1143 ath5k_hw_set_mcast_filter(ah, 0, 0);
1144 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1148 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1152 /* return base rate on errors */
1153 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1154 "hw_rix out of bounds: %x\n", hw_rix))
1157 rix = sc->rate_idx[sc->curband->band][hw_rix];
1158 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1169 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1171 struct ath_common *common = ath5k_hw_common(sc->ah);
1172 struct sk_buff *skb;
1175 * Allocate buffer with headroom_needed space for the
1176 * fake physical layer header at the start.
1178 skb = ath_rxbuf_alloc(common,
1179 sc->rxbufsize + common->cachelsz - 1,
1183 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1184 sc->rxbufsize + common->cachelsz - 1);
1188 *skb_addr = pci_map_single(sc->pdev,
1189 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1190 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1191 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1199 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1201 struct ath5k_hw *ah = sc->ah;
1202 struct sk_buff *skb = bf->skb;
1203 struct ath5k_desc *ds;
1206 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1213 * Setup descriptors. For receive we always terminate
1214 * the descriptor list with a self-linked entry so we'll
1215 * not get overrun under high load (as can happen with a
1216 * 5212 when ANI processing enables PHY error frames).
1218 * To insure the last descriptor is self-linked we create
1219 * each descriptor as self-linked and add it to the end. As
1220 * each additional descriptor is added the previous self-linked
1221 * entry is ``fixed'' naturally. This should be safe even
1222 * if DMA is happening. When processing RX interrupts we
1223 * never remove/process the last, self-linked, entry on the
1224 * descriptor list. This insures the hardware always has
1225 * someplace to write a new frame.
1228 ds->ds_link = bf->daddr; /* link to self */
1229 ds->ds_data = bf->skbaddr;
1230 ah->ah_setup_rx_desc(ah, ds,
1231 skb_tailroom(skb), /* buffer size */
1234 if (sc->rxlink != NULL)
1235 *sc->rxlink = bf->daddr;
1236 sc->rxlink = &ds->ds_link;
1241 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1242 struct ath5k_txq *txq)
1244 struct ath5k_hw *ah = sc->ah;
1245 struct ath5k_desc *ds = bf->desc;
1246 struct sk_buff *skb = bf->skb;
1247 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1248 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1249 struct ieee80211_rate *rate;
1250 unsigned int mrr_rate[3], mrr_tries[3];
1257 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1259 /* XXX endianness */
1260 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1263 rate = ieee80211_get_tx_rate(sc->hw, info);
1265 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1266 flags |= AR5K_TXDESC_NOACK;
1268 rc_flags = info->control.rates[0].flags;
1269 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1270 rate->hw_value_short : rate->hw_value;
1274 /* FIXME: If we are in g mode and rate is a CCK rate
1275 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1276 * from tx power (value is in dB units already) */
1277 if (info->control.hw_key) {
1278 keyidx = info->control.hw_key->hw_key_idx;
1279 pktlen += info->control.hw_key->icv_len;
1281 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1282 flags |= AR5K_TXDESC_RTSENA;
1283 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1284 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1285 sc->vif, pktlen, info));
1287 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1288 flags |= AR5K_TXDESC_CTSENA;
1289 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1290 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1291 sc->vif, pktlen, info));
1293 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1294 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1295 (sc->power_level * 2),
1297 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1298 cts_rate, duration);
1302 memset(mrr_rate, 0, sizeof(mrr_rate));
1303 memset(mrr_tries, 0, sizeof(mrr_tries));
1304 for (i = 0; i < 3; i++) {
1305 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1309 mrr_rate[i] = rate->hw_value;
1310 mrr_tries[i] = info->control.rates[i + 1].count;
1313 ah->ah_setup_mrr_tx_desc(ah, ds,
1314 mrr_rate[0], mrr_tries[0],
1315 mrr_rate[1], mrr_tries[1],
1316 mrr_rate[2], mrr_tries[2]);
1319 ds->ds_data = bf->skbaddr;
1321 spin_lock_bh(&txq->lock);
1322 list_add_tail(&bf->list, &txq->q);
1323 sc->tx_stats[txq->qnum].len++;
1324 if (txq->link == NULL) /* is this first packet? */
1325 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1326 else /* no, so only link it */
1327 *txq->link = bf->daddr;
1329 txq->link = &ds->ds_link;
1330 ath5k_hw_start_tx_dma(ah, txq->qnum);
1332 spin_unlock_bh(&txq->lock);
1336 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1340 /*******************\
1341 * Descriptors setup *
1342 \*******************/
1345 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1347 struct ath5k_desc *ds;
1348 struct ath5k_buf *bf;
1353 /* allocate descriptors */
1354 sc->desc_len = sizeof(struct ath5k_desc) *
1355 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1356 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1357 if (sc->desc == NULL) {
1358 ATH5K_ERR(sc, "can't allocate descriptors\n");
1363 da = sc->desc_daddr;
1364 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1365 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1367 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1368 sizeof(struct ath5k_buf), GFP_KERNEL);
1370 ATH5K_ERR(sc, "can't allocate bufptr\n");
1376 INIT_LIST_HEAD(&sc->rxbuf);
1377 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1380 list_add_tail(&bf->list, &sc->rxbuf);
1383 INIT_LIST_HEAD(&sc->txbuf);
1384 sc->txbuf_len = ATH_TXBUF;
1385 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1386 da += sizeof(*ds)) {
1389 list_add_tail(&bf->list, &sc->txbuf);
1399 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1406 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1408 struct ath5k_buf *bf;
1410 ath5k_txbuf_free(sc, sc->bbuf);
1411 list_for_each_entry(bf, &sc->txbuf, list)
1412 ath5k_txbuf_free(sc, bf);
1413 list_for_each_entry(bf, &sc->rxbuf, list)
1414 ath5k_rxbuf_free(sc, bf);
1416 /* Free memory associated with all descriptors */
1417 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1431 static struct ath5k_txq *
1432 ath5k_txq_setup(struct ath5k_softc *sc,
1433 int qtype, int subtype)
1435 struct ath5k_hw *ah = sc->ah;
1436 struct ath5k_txq *txq;
1437 struct ath5k_txq_info qi = {
1438 .tqi_subtype = subtype,
1439 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1440 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1441 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1446 * Enable interrupts only for EOL and DESC conditions.
1447 * We mark tx descriptors to receive a DESC interrupt
1448 * when a tx queue gets deep; otherwise waiting for the
1449 * EOL to reap descriptors. Note that this is done to
1450 * reduce interrupt load and this only defers reaping
1451 * descriptors, never transmitting frames. Aside from
1452 * reducing interrupts this also permits more concurrency.
1453 * The only potential downside is if the tx queue backs
1454 * up in which case the top half of the kernel may backup
1455 * due to a lack of tx descriptors.
1457 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1458 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1459 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1462 * NB: don't print a message, this happens
1463 * normally on parts with too few tx queues
1465 return ERR_PTR(qnum);
1467 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1468 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1469 qnum, ARRAY_SIZE(sc->txqs));
1470 ath5k_hw_release_tx_queue(ah, qnum);
1471 return ERR_PTR(-EINVAL);
1473 txq = &sc->txqs[qnum];
1477 INIT_LIST_HEAD(&txq->q);
1478 spin_lock_init(&txq->lock);
1481 return &sc->txqs[qnum];
1485 ath5k_beaconq_setup(struct ath5k_hw *ah)
1487 struct ath5k_txq_info qi = {
1488 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1489 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1490 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1491 /* NB: for dynamic turbo, don't enable any other interrupts */
1492 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1495 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1499 ath5k_beaconq_config(struct ath5k_softc *sc)
1501 struct ath5k_hw *ah = sc->ah;
1502 struct ath5k_txq_info qi;
1505 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1508 if (sc->opmode == NL80211_IFTYPE_AP ||
1509 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1511 * Always burst out beacon and CAB traffic
1512 * (aifs = cwmin = cwmax = 0)
1517 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1519 * Adhoc mode; backoff between 0 and (2 * cw_min).
1523 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1526 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1527 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1528 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1530 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1532 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1533 "hardware queue!\n", __func__);
1537 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1541 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1543 struct ath5k_buf *bf, *bf0;
1546 * NB: this assumes output has been stopped and
1547 * we do not need to block ath5k_tx_tasklet
1549 spin_lock_bh(&txq->lock);
1550 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1551 ath5k_debug_printtxbuf(sc, bf);
1553 ath5k_txbuf_free(sc, bf);
1555 spin_lock_bh(&sc->txbuflock);
1556 sc->tx_stats[txq->qnum].len--;
1557 list_move_tail(&bf->list, &sc->txbuf);
1559 spin_unlock_bh(&sc->txbuflock);
1562 spin_unlock_bh(&txq->lock);
1566 * Drain the transmit queues and reclaim resources.
1569 ath5k_txq_cleanup(struct ath5k_softc *sc)
1571 struct ath5k_hw *ah = sc->ah;
1574 /* XXX return value */
1575 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1576 /* don't touch the hardware if marked invalid */
1577 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1578 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1579 ath5k_hw_get_txdp(ah, sc->bhalq));
1580 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1581 if (sc->txqs[i].setup) {
1582 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1583 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1586 ath5k_hw_get_txdp(ah,
1591 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1593 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1594 if (sc->txqs[i].setup)
1595 ath5k_txq_drainq(sc, &sc->txqs[i]);
1599 ath5k_txq_release(struct ath5k_softc *sc)
1601 struct ath5k_txq *txq = sc->txqs;
1604 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1606 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1619 * Enable the receive h/w following a reset.
1622 ath5k_rx_start(struct ath5k_softc *sc)
1624 struct ath5k_hw *ah = sc->ah;
1625 struct ath_common *common = ath5k_hw_common(ah);
1626 struct ath5k_buf *bf;
1629 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1631 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1632 common->cachelsz, sc->rxbufsize);
1634 spin_lock_bh(&sc->rxbuflock);
1636 list_for_each_entry(bf, &sc->rxbuf, list) {
1637 ret = ath5k_rxbuf_setup(sc, bf);
1639 spin_unlock_bh(&sc->rxbuflock);
1643 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1644 ath5k_hw_set_rxdp(ah, bf->daddr);
1645 spin_unlock_bh(&sc->rxbuflock);
1647 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1648 ath5k_mode_setup(sc); /* set filters, etc. */
1649 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1657 * Disable the receive h/w in preparation for a reset.
1660 ath5k_rx_stop(struct ath5k_softc *sc)
1662 struct ath5k_hw *ah = sc->ah;
1664 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1665 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1666 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1668 ath5k_debug_printrxbuffs(sc, ah);
1670 sc->rxlink = NULL; /* just in case */
1674 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1675 struct sk_buff *skb, struct ath5k_rx_status *rs)
1677 struct ieee80211_hdr *hdr = (void *)skb->data;
1678 unsigned int keyix, hlen;
1680 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1681 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1682 return RX_FLAG_DECRYPTED;
1684 /* Apparently when a default key is used to decrypt the packet
1685 the hw does not set the index used to decrypt. In such cases
1686 get the index from the packet. */
1687 hlen = ieee80211_hdrlen(hdr->frame_control);
1688 if (ieee80211_has_protected(hdr->frame_control) &&
1689 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1690 skb->len >= hlen + 4) {
1691 keyix = skb->data[hlen + 3] >> 6;
1693 if (test_bit(keyix, sc->keymap))
1694 return RX_FLAG_DECRYPTED;
1702 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1703 struct ieee80211_rx_status *rxs)
1705 struct ath_common *common = ath5k_hw_common(sc->ah);
1708 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1710 if (ieee80211_is_beacon(mgmt->frame_control) &&
1711 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1712 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1714 * Received an IBSS beacon with the same BSSID. Hardware *must*
1715 * have updated the local TSF. We have to work around various
1716 * hardware bugs, though...
1718 tsf = ath5k_hw_get_tsf64(sc->ah);
1719 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1720 hw_tu = TSF_TO_TU(tsf);
1722 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1723 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1724 (unsigned long long)bc_tstamp,
1725 (unsigned long long)rxs->mactime,
1726 (unsigned long long)(rxs->mactime - bc_tstamp),
1727 (unsigned long long)tsf);
1730 * Sometimes the HW will give us a wrong tstamp in the rx
1731 * status, causing the timestamp extension to go wrong.
1732 * (This seems to happen especially with beacon frames bigger
1733 * than 78 byte (incl. FCS))
1734 * But we know that the receive timestamp must be later than the
1735 * timestamp of the beacon since HW must have synced to that.
1737 * NOTE: here we assume mactime to be after the frame was
1738 * received, not like mac80211 which defines it at the start.
1740 if (bc_tstamp > rxs->mactime) {
1741 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1742 "fixing mactime from %llx to %llx\n",
1743 (unsigned long long)rxs->mactime,
1744 (unsigned long long)tsf);
1749 * Local TSF might have moved higher than our beacon timers,
1750 * in that case we have to update them to continue sending
1751 * beacons. This also takes care of synchronizing beacon sending
1752 * times with other stations.
1754 if (hw_tu >= sc->nexttbtt)
1755 ath5k_beacon_update_timers(sc, bc_tstamp);
1760 ath5k_tasklet_rx(unsigned long data)
1762 struct ieee80211_rx_status *rxs;
1763 struct ath5k_rx_status rs = {};
1764 struct sk_buff *skb, *next_skb;
1765 dma_addr_t next_skb_addr;
1766 struct ath5k_softc *sc = (void *)data;
1767 struct ath5k_buf *bf;
1768 struct ath5k_desc *ds;
1774 spin_lock(&sc->rxbuflock);
1775 if (list_empty(&sc->rxbuf)) {
1776 ATH5K_WARN(sc, "empty rx buf pool\n");
1782 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1783 BUG_ON(bf->skb == NULL);
1787 /* bail if HW is still using self-linked descriptor */
1788 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1791 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1792 if (unlikely(ret == -EINPROGRESS))
1794 else if (unlikely(ret)) {
1795 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1796 spin_unlock(&sc->rxbuflock);
1800 if (unlikely(rs.rs_more)) {
1801 ATH5K_WARN(sc, "unsupported jumbo\n");
1805 if (unlikely(rs.rs_status)) {
1806 if (rs.rs_status & AR5K_RXERR_PHY)
1808 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1810 * Decrypt error. If the error occurred
1811 * because there was no hardware key, then
1812 * let the frame through so the upper layers
1813 * can process it. This is necessary for 5210
1814 * parts which have no way to setup a ``clear''
1817 * XXX do key cache faulting
1819 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1820 !(rs.rs_status & AR5K_RXERR_CRC))
1823 if (rs.rs_status & AR5K_RXERR_MIC) {
1824 rx_flag |= RX_FLAG_MMIC_ERROR;
1828 /* let crypto-error packets fall through in MNTR */
1830 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1831 sc->opmode != NL80211_IFTYPE_MONITOR)
1835 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1838 * If we can't replace bf->skb with a new skb under memory
1839 * pressure, just skip this packet
1844 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1845 PCI_DMA_FROMDEVICE);
1846 skb_put(skb, rs.rs_datalen);
1848 /* The MAC header is padded to have 32-bit boundary if the
1849 * packet payload is non-zero. The general calculation for
1850 * padsize would take into account odd header lengths:
1851 * padsize = (4 - hdrlen % 4) % 4; However, since only
1852 * even-length headers are used, padding can only be 0 or 2
1853 * bytes and we can optimize this a bit. In addition, we must
1854 * not try to remove padding from short control frames that do
1855 * not have payload. */
1856 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1857 padsize = ath5k_pad_size(hdrlen);
1859 memmove(skb->data + padsize, skb->data, hdrlen);
1860 skb_pull(skb, padsize);
1862 rxs = IEEE80211_SKB_RXCB(skb);
1865 * always extend the mac timestamp, since this information is
1866 * also needed for proper IBSS merging.
1868 * XXX: it might be too late to do it here, since rs_tstamp is
1869 * 15bit only. that means TSF extension has to be done within
1870 * 32768usec (about 32ms). it might be necessary to move this to
1871 * the interrupt handler, like it is done in madwifi.
1873 * Unfortunately we don't know when the hardware takes the rx
1874 * timestamp (beginning of phy frame, data frame, end of rx?).
1875 * The only thing we know is that it is hardware specific...
1876 * On AR5213 it seems the rx timestamp is at the end of the
1877 * frame, but i'm not sure.
1879 * NOTE: mac80211 defines mactime at the beginning of the first
1880 * data symbol. Since we don't have any time references it's
1881 * impossible to comply to that. This affects IBSS merge only
1882 * right now, so it's not too bad...
1884 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1885 rxs->flag = rx_flag | RX_FLAG_TSFT;
1887 rxs->freq = sc->curchan->center_freq;
1888 rxs->band = sc->curband->band;
1890 rxs->noise = sc->ah->ah_noise_floor;
1891 rxs->signal = rxs->noise + rs.rs_rssi;
1893 /* An rssi of 35 indicates you should be able use
1894 * 54 Mbps reliably. A more elaborate scheme can be used
1895 * here but it requires a map of SNR/throughput for each
1896 * possible mode used */
1897 rxs->qual = rs.rs_rssi * 100 / 35;
1899 /* rssi can be more than 35 though, anything above that
1900 * should be considered at 100% */
1901 if (rxs->qual > 100)
1904 rxs->antenna = rs.rs_antenna;
1905 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1906 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1908 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1909 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1910 rxs->flag |= RX_FLAG_SHORTPRE;
1912 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1914 /* check beacons in IBSS mode */
1915 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1916 ath5k_check_ibss_tsf(sc, skb, rxs);
1918 ieee80211_rx(sc->hw, skb);
1921 bf->skbaddr = next_skb_addr;
1923 list_move_tail(&bf->list, &sc->rxbuf);
1924 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1926 spin_unlock(&sc->rxbuflock);
1937 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1939 struct ath5k_tx_status ts = {};
1940 struct ath5k_buf *bf, *bf0;
1941 struct ath5k_desc *ds;
1942 struct sk_buff *skb;
1943 struct ieee80211_tx_info *info;
1946 spin_lock(&txq->lock);
1947 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1950 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1951 if (unlikely(ret == -EINPROGRESS))
1953 else if (unlikely(ret)) {
1954 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1960 info = IEEE80211_SKB_CB(skb);
1963 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1966 ieee80211_tx_info_clear_status(info);
1967 for (i = 0; i < 4; i++) {
1968 struct ieee80211_tx_rate *r =
1969 &info->status.rates[i];
1971 if (ts.ts_rate[i]) {
1972 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1973 r->count = ts.ts_retry[i];
1980 /* count the successful attempt as well */
1981 info->status.rates[ts.ts_final_idx].count++;
1983 if (unlikely(ts.ts_status)) {
1984 sc->ll_stats.dot11ACKFailureCount++;
1985 if (ts.ts_status & AR5K_TXERR_FILT)
1986 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1988 info->flags |= IEEE80211_TX_STAT_ACK;
1989 info->status.ack_signal = ts.ts_rssi;
1992 ieee80211_tx_status(sc->hw, skb);
1993 sc->tx_stats[txq->qnum].count++;
1995 spin_lock(&sc->txbuflock);
1996 sc->tx_stats[txq->qnum].len--;
1997 list_move_tail(&bf->list, &sc->txbuf);
1999 spin_unlock(&sc->txbuflock);
2001 if (likely(list_empty(&txq->q)))
2003 spin_unlock(&txq->lock);
2004 if (sc->txbuf_len > ATH_TXBUF / 5)
2005 ieee80211_wake_queues(sc->hw);
2009 ath5k_tasklet_tx(unsigned long data)
2012 struct ath5k_softc *sc = (void *)data;
2014 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2015 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2016 ath5k_tx_processq(sc, &sc->txqs[i]);
2025 * Setup the beacon frame for transmit.
2028 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2030 struct sk_buff *skb = bf->skb;
2031 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2032 struct ath5k_hw *ah = sc->ah;
2033 struct ath5k_desc *ds;
2038 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2040 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2041 "skbaddr %llx\n", skb, skb->data, skb->len,
2042 (unsigned long long)bf->skbaddr);
2043 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2044 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2049 antenna = ah->ah_tx_ant;
2051 flags = AR5K_TXDESC_NOACK;
2052 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2053 ds->ds_link = bf->daddr; /* self-linked */
2054 flags |= AR5K_TXDESC_VEOL;
2059 * If we use multiple antennas on AP and use
2060 * the Sectored AP scenario, switch antenna every
2061 * 4 beacons to make sure everybody hears our AP.
2062 * When a client tries to associate, hw will keep
2063 * track of the tx antenna to be used for this client
2064 * automaticaly, based on ACKed packets.
2066 * Note: AP still listens and transmits RTS on the
2067 * default antenna which is supposed to be an omni.
2069 * Note2: On sectored scenarios it's possible to have
2070 * multiple antennas (1omni -the default- and 14 sectors)
2071 * so if we choose to actually support this mode we need
2072 * to allow user to set how many antennas we have and tweak
2073 * the code below to send beacons on all of them.
2075 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2076 antenna = sc->bsent & 4 ? 2 : 1;
2079 /* FIXME: If we are in g mode and rate is a CCK rate
2080 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2081 * from tx power (value is in dB units already) */
2082 ds->ds_data = bf->skbaddr;
2083 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2084 ieee80211_get_hdrlen_from_skb(skb),
2085 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2086 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2087 1, AR5K_TXKEYIX_INVALID,
2088 antenna, flags, 0, 0);
2094 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2099 * Transmit a beacon frame at SWBA. Dynamic updates to the
2100 * frame contents are done as needed and the slot time is
2101 * also adjusted based on current state.
2103 * This is called from software irq context (beacontq or restq
2104 * tasklets) or user context from ath5k_beacon_config.
2107 ath5k_beacon_send(struct ath5k_softc *sc)
2109 struct ath5k_buf *bf = sc->bbuf;
2110 struct ath5k_hw *ah = sc->ah;
2111 struct sk_buff *skb;
2113 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2115 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2116 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2117 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2121 * Check if the previous beacon has gone out. If
2122 * not don't don't try to post another, skip this
2123 * period and wait for the next. Missed beacons
2124 * indicate a problem and should not occur. If we
2125 * miss too many consecutive beacons reset the device.
2127 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2129 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2130 "missed %u consecutive beacons\n", sc->bmisscount);
2131 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2132 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2133 "stuck beacon time (%u missed)\n",
2135 tasklet_schedule(&sc->restq);
2139 if (unlikely(sc->bmisscount != 0)) {
2140 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2141 "resume beacon xmit after %u misses\n",
2147 * Stop any current dma and put the new frame on the queue.
2148 * This should never fail since we check above that no frames
2149 * are still pending on the queue.
2151 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2152 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2153 /* NB: hw still stops DMA, so proceed */
2156 /* refresh the beacon for AP mode */
2157 if (sc->opmode == NL80211_IFTYPE_AP)
2158 ath5k_beacon_update(sc->hw, sc->vif);
2160 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2161 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2162 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2163 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2165 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2167 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2168 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2176 * ath5k_beacon_update_timers - update beacon timers
2178 * @sc: struct ath5k_softc pointer we are operating on
2179 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2180 * beacon timer update based on the current HW TSF.
2182 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2183 * of a received beacon or the current local hardware TSF and write it to the
2184 * beacon timer registers.
2186 * This is called in a variety of situations, e.g. when a beacon is received,
2187 * when a TSF update has been detected, but also when an new IBSS is created or
2188 * when we otherwise know we have to update the timers, but we keep it in this
2189 * function to have it all together in one place.
2192 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2194 struct ath5k_hw *ah = sc->ah;
2195 u32 nexttbtt, intval, hw_tu, bc_tu;
2198 intval = sc->bintval & AR5K_BEACON_PERIOD;
2199 if (WARN_ON(!intval))
2202 /* beacon TSF converted to TU */
2203 bc_tu = TSF_TO_TU(bc_tsf);
2205 /* current TSF converted to TU */
2206 hw_tsf = ath5k_hw_get_tsf64(ah);
2207 hw_tu = TSF_TO_TU(hw_tsf);
2210 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2213 * no beacons received, called internally.
2214 * just need to refresh timers based on HW TSF.
2216 nexttbtt = roundup(hw_tu + FUDGE, intval);
2217 } else if (bc_tsf == 0) {
2219 * no beacon received, probably called by ath5k_reset_tsf().
2220 * reset TSF to start with 0.
2223 intval |= AR5K_BEACON_RESET_TSF;
2224 } else if (bc_tsf > hw_tsf) {
2226 * beacon received, SW merge happend but HW TSF not yet updated.
2227 * not possible to reconfigure timers yet, but next time we
2228 * receive a beacon with the same BSSID, the hardware will
2229 * automatically update the TSF and then we need to reconfigure
2232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2233 "need to wait for HW TSF sync\n");
2237 * most important case for beacon synchronization between STA.
2239 * beacon received and HW TSF has been already updated by HW.
2240 * update next TBTT based on the TSF of the beacon, but make
2241 * sure it is ahead of our local TSF timer.
2243 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2247 sc->nexttbtt = nexttbtt;
2249 intval |= AR5K_BEACON_ENA;
2250 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2253 * debugging output last in order to preserve the time critical aspect
2257 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2258 "reconfigured timers based on HW TSF\n");
2259 else if (bc_tsf == 0)
2260 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2261 "reset HW TSF and timers\n");
2263 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2264 "updated timers based on beacon TSF\n");
2266 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2267 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2268 (unsigned long long) bc_tsf,
2269 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2270 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2271 intval & AR5K_BEACON_PERIOD,
2272 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2273 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2278 * ath5k_beacon_config - Configure the beacon queues and interrupts
2280 * @sc: struct ath5k_softc pointer we are operating on
2282 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2283 * interrupts to detect TSF updates only.
2286 ath5k_beacon_config(struct ath5k_softc *sc)
2288 struct ath5k_hw *ah = sc->ah;
2289 unsigned long flags;
2291 spin_lock_irqsave(&sc->block, flags);
2293 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2295 if (sc->enable_beacon) {
2297 * In IBSS mode we use a self-linked tx descriptor and let the
2298 * hardware send the beacons automatically. We have to load it
2300 * We use the SWBA interrupt only to keep track of the beacon
2301 * timers in order to detect automatic TSF updates.
2303 ath5k_beaconq_config(sc);
2305 sc->imask |= AR5K_INT_SWBA;
2307 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2308 if (ath5k_hw_hasveol(ah))
2309 ath5k_beacon_send(sc);
2311 ath5k_beacon_update_timers(sc, -1);
2313 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2316 ath5k_hw_set_imr(ah, sc->imask);
2318 spin_unlock_irqrestore(&sc->block, flags);
2321 static void ath5k_tasklet_beacon(unsigned long data)
2323 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2326 * Software beacon alert--time to send a beacon.
2328 * In IBSS mode we use this interrupt just to
2329 * keep track of the next TBTT (target beacon
2330 * transmission time) in order to detect wether
2331 * automatic TSF updates happened.
2333 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2334 /* XXX: only if VEOL suppported */
2335 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2336 sc->nexttbtt += sc->bintval;
2337 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2338 "SWBA nexttbtt: %x hw_tu: %x "
2342 (unsigned long long) tsf);
2344 spin_lock(&sc->block);
2345 ath5k_beacon_send(sc);
2346 spin_unlock(&sc->block);
2351 /********************\
2352 * Interrupt handling *
2353 \********************/
2356 ath5k_init(struct ath5k_softc *sc)
2358 struct ath5k_hw *ah = sc->ah;
2361 mutex_lock(&sc->lock);
2363 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2366 * Stop anything previously setup. This is safe
2367 * no matter this is the first time through or not.
2369 ath5k_stop_locked(sc);
2372 * The basic interface to setting the hardware in a good
2373 * state is ``reset''. On return the hardware is known to
2374 * be powered up and with interrupts disabled. This must
2375 * be followed by initialization of the appropriate bits
2376 * and then setup of the interrupt mask.
2378 sc->curchan = sc->hw->conf.channel;
2379 sc->curband = &sc->sbands[sc->curchan->band];
2380 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2381 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2382 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2383 ret = ath5k_reset(sc, NULL);
2387 ath5k_rfkill_hw_start(ah);
2390 * Reset the key cache since some parts do not reset the
2391 * contents on initial power up or resume from suspend.
2393 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2394 ath5k_hw_reset_key(ah, i);
2396 /* Set ack to be sent at low bit-rates */
2397 ath5k_hw_set_ack_bitrate_high(ah, false);
2399 /* Set PHY calibration inteval */
2400 ah->ah_cal_intval = ath5k_calinterval;
2405 mutex_unlock(&sc->lock);
2410 ath5k_stop_locked(struct ath5k_softc *sc)
2412 struct ath5k_hw *ah = sc->ah;
2414 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2415 test_bit(ATH_STAT_INVALID, sc->status));
2418 * Shutdown the hardware and driver:
2419 * stop output from above
2420 * disable interrupts
2422 * turn off the radio
2423 * clear transmit machinery
2424 * clear receive machinery
2425 * drain and release tx queues
2426 * reclaim beacon resources
2427 * power down hardware
2429 * Note that some of this work is not possible if the
2430 * hardware is gone (invalid).
2432 ieee80211_stop_queues(sc->hw);
2434 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2436 ath5k_hw_set_imr(ah, 0);
2437 synchronize_irq(sc->pdev->irq);
2439 ath5k_txq_cleanup(sc);
2440 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2442 ath5k_hw_phy_disable(ah);
2450 * Stop the device, grabbing the top-level lock to protect
2451 * against concurrent entry through ath5k_init (which can happen
2452 * if another thread does a system call and the thread doing the
2453 * stop is preempted).
2456 ath5k_stop_hw(struct ath5k_softc *sc)
2460 mutex_lock(&sc->lock);
2461 ret = ath5k_stop_locked(sc);
2462 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2464 * Don't set the card in full sleep mode!
2466 * a) When the device is in this state it must be carefully
2467 * woken up or references to registers in the PCI clock
2468 * domain may freeze the bus (and system). This varies
2469 * by chip and is mostly an issue with newer parts
2470 * (madwifi sources mentioned srev >= 0x78) that go to
2471 * sleep more quickly.
2473 * b) On older chips full sleep results a weird behaviour
2474 * during wakeup. I tested various cards with srev < 0x78
2475 * and they don't wake up after module reload, a second
2476 * module reload is needed to bring the card up again.
2478 * Until we figure out what's going on don't enable
2479 * full chip reset on any chip (this is what Legacy HAL
2480 * and Sam's HAL do anyway). Instead Perform a full reset
2481 * on the device (same as initial state after attach) and
2482 * leave it idle (keep MAC/BB on warm reset) */
2483 ret = ath5k_hw_on_hold(sc->ah);
2485 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2486 "putting device to sleep\n");
2488 ath5k_txbuf_free(sc, sc->bbuf);
2491 mutex_unlock(&sc->lock);
2493 tasklet_kill(&sc->rxtq);
2494 tasklet_kill(&sc->txtq);
2495 tasklet_kill(&sc->restq);
2496 tasklet_kill(&sc->calib);
2497 tasklet_kill(&sc->beacontq);
2499 ath5k_rfkill_hw_stop(sc->ah);
2505 ath5k_intr(int irq, void *dev_id)
2507 struct ath5k_softc *sc = dev_id;
2508 struct ath5k_hw *ah = sc->ah;
2509 enum ath5k_int status;
2510 unsigned int counter = 1000;
2512 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2513 !ath5k_hw_is_intr_pending(ah)))
2517 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2518 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2520 if (unlikely(status & AR5K_INT_FATAL)) {
2522 * Fatal errors are unrecoverable.
2523 * Typically these are caused by DMA errors.
2525 tasklet_schedule(&sc->restq);
2526 } else if (unlikely(status & AR5K_INT_RXORN)) {
2527 tasklet_schedule(&sc->restq);
2529 if (status & AR5K_INT_SWBA) {
2530 tasklet_hi_schedule(&sc->beacontq);
2532 if (status & AR5K_INT_RXEOL) {
2534 * NB: the hardware should re-read the link when
2535 * RXE bit is written, but it doesn't work at
2536 * least on older hardware revs.
2540 if (status & AR5K_INT_TXURN) {
2541 /* bump tx trigger level */
2542 ath5k_hw_update_tx_triglevel(ah, true);
2544 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2545 tasklet_schedule(&sc->rxtq);
2546 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2547 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2548 tasklet_schedule(&sc->txtq);
2549 if (status & AR5K_INT_BMISS) {
2552 if (status & AR5K_INT_SWI) {
2553 tasklet_schedule(&sc->calib);
2555 if (status & AR5K_INT_MIB) {
2557 * These stats are also used for ANI i think
2558 * so how about updating them more often ?
2560 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2562 if (status & AR5K_INT_GPIO)
2563 tasklet_schedule(&sc->rf_kill.toggleq);
2566 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2568 if (unlikely(!counter))
2569 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2571 ath5k_hw_calibration_poll(ah);
2577 ath5k_tasklet_reset(unsigned long data)
2579 struct ath5k_softc *sc = (void *)data;
2581 ath5k_reset_wake(sc);
2585 * Periodically recalibrate the PHY to account
2586 * for temperature/environment changes.
2589 ath5k_tasklet_calibrate(unsigned long data)
2591 struct ath5k_softc *sc = (void *)data;
2592 struct ath5k_hw *ah = sc->ah;
2594 /* Only full calibration for now */
2595 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2598 /* Stop queues so that calibration
2599 * doesn't interfere with tx */
2600 ieee80211_stop_queues(sc->hw);
2602 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2603 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2604 sc->curchan->hw_value);
2606 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2608 * Rfgain is out of bounds, reset the chip
2609 * to load new gain values.
2611 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2612 ath5k_reset_wake(sc);
2614 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2615 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2616 ieee80211_frequency_to_channel(
2617 sc->curchan->center_freq));
2619 ah->ah_swi_mask = 0;
2622 ieee80211_wake_queues(sc->hw);
2627 /********************\
2628 * Mac80211 functions *
2629 \********************/
2632 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2634 struct ath5k_softc *sc = hw->priv;
2636 return ath5k_tx_queue(hw, skb, sc->txq);
2639 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2640 struct ath5k_txq *txq)
2642 struct ath5k_softc *sc = hw->priv;
2643 struct ath5k_buf *bf;
2644 unsigned long flags;
2648 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2650 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2651 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2654 * the hardware expects the header padded to 4 byte boundaries
2655 * if this is not the case we add the padding after the header
2657 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2658 padsize = ath5k_pad_size(hdrlen);
2661 if (skb_headroom(skb) < padsize) {
2662 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2663 " headroom to pad %d\n", hdrlen, padsize);
2666 skb_push(skb, padsize);
2667 memmove(skb->data, skb->data+padsize, hdrlen);
2670 spin_lock_irqsave(&sc->txbuflock, flags);
2671 if (list_empty(&sc->txbuf)) {
2672 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2673 spin_unlock_irqrestore(&sc->txbuflock, flags);
2674 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2677 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2678 list_del(&bf->list);
2680 if (list_empty(&sc->txbuf))
2681 ieee80211_stop_queues(hw);
2682 spin_unlock_irqrestore(&sc->txbuflock, flags);
2686 if (ath5k_txbuf_setup(sc, bf, txq)) {
2688 spin_lock_irqsave(&sc->txbuflock, flags);
2689 list_add_tail(&bf->list, &sc->txbuf);
2691 spin_unlock_irqrestore(&sc->txbuflock, flags);
2694 return NETDEV_TX_OK;
2697 dev_kfree_skb_any(skb);
2698 return NETDEV_TX_OK;
2702 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2703 * and change to the given channel.
2706 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2708 struct ath5k_hw *ah = sc->ah;
2711 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2714 ath5k_hw_set_imr(ah, 0);
2715 ath5k_txq_cleanup(sc);
2719 sc->curband = &sc->sbands[chan->band];
2721 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2723 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2727 ret = ath5k_rx_start(sc);
2729 ATH5K_ERR(sc, "can't start recv logic\n");
2734 * Change channels and update the h/w rate map if we're switching;
2735 * e.g. 11a to 11b/g.
2737 * We may be doing a reset in response to an ioctl that changes the
2738 * channel so update any state that might change as a result.
2742 /* ath5k_chan_change(sc, c); */
2744 ath5k_beacon_config(sc);
2745 /* intrs are enabled by ath5k_beacon_config */
2753 ath5k_reset_wake(struct ath5k_softc *sc)
2757 ret = ath5k_reset(sc, sc->curchan);
2759 ieee80211_wake_queues(sc->hw);
2764 static int ath5k_start(struct ieee80211_hw *hw)
2766 return ath5k_init(hw->priv);
2769 static void ath5k_stop(struct ieee80211_hw *hw)
2771 ath5k_stop_hw(hw->priv);
2774 static int ath5k_add_interface(struct ieee80211_hw *hw,
2775 struct ieee80211_if_init_conf *conf)
2777 struct ath5k_softc *sc = hw->priv;
2780 mutex_lock(&sc->lock);
2786 sc->vif = conf->vif;
2788 switch (conf->type) {
2789 case NL80211_IFTYPE_AP:
2790 case NL80211_IFTYPE_STATION:
2791 case NL80211_IFTYPE_ADHOC:
2792 case NL80211_IFTYPE_MESH_POINT:
2793 case NL80211_IFTYPE_MONITOR:
2794 sc->opmode = conf->type;
2801 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2802 ath5k_mode_setup(sc);
2806 mutex_unlock(&sc->lock);
2811 ath5k_remove_interface(struct ieee80211_hw *hw,
2812 struct ieee80211_if_init_conf *conf)
2814 struct ath5k_softc *sc = hw->priv;
2815 u8 mac[ETH_ALEN] = {};
2817 mutex_lock(&sc->lock);
2818 if (sc->vif != conf->vif)
2821 ath5k_hw_set_lladdr(sc->ah, mac);
2824 mutex_unlock(&sc->lock);
2828 * TODO: Phy disable/diversity etc
2831 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2833 struct ath5k_softc *sc = hw->priv;
2834 struct ath5k_hw *ah = sc->ah;
2835 struct ieee80211_conf *conf = &hw->conf;
2838 mutex_lock(&sc->lock);
2840 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2841 ret = ath5k_chan_set(sc, conf->channel);
2846 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2847 (sc->power_level != conf->power_level)) {
2848 sc->power_level = conf->power_level;
2851 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2855 * 1) Move this on config_interface and handle each case
2856 * separately eg. when we have only one STA vif, use
2857 * AR5K_ANTMODE_SINGLE_AP
2859 * 2) Allow the user to change antenna mode eg. when only
2860 * one antenna is present
2862 * 3) Allow the user to set default/tx antenna when possible
2864 * 4) Default mode should handle 90% of the cases, together
2865 * with fixed a/b and single AP modes we should be able to
2866 * handle 99%. Sectored modes are extreme cases and i still
2867 * haven't found a usage for them. If we decide to support them,
2868 * then we must allow the user to set how many tx antennas we
2871 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2874 mutex_unlock(&sc->lock);
2878 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2879 int mc_count, struct dev_addr_list *mclist)
2888 for (i = 0; i < mc_count; i++) {
2891 /* calculate XOR of eight 6-bit values */
2892 val = get_unaligned_le32(mclist->dmi_addr + 0);
2893 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2894 val = get_unaligned_le32(mclist->dmi_addr + 3);
2895 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2897 mfilt[pos / 32] |= (1 << (pos % 32));
2898 /* XXX: we might be able to just do this instead,
2899 * but not sure, needs testing, if we do use this we'd
2900 * neet to inform below to not reset the mcast */
2901 /* ath5k_hw_set_mcast_filterindex(ah,
2902 * mclist->dmi_addr[5]); */
2903 mclist = mclist->next;
2906 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2909 #define SUPPORTED_FIF_FLAGS \
2910 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2911 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2912 FIF_BCN_PRBRESP_PROMISC
2914 * o always accept unicast, broadcast, and multicast traffic
2915 * o multicast traffic for all BSSIDs will be enabled if mac80211
2917 * o maintain current state of phy ofdm or phy cck error reception.
2918 * If the hardware detects any of these type of errors then
2919 * ath5k_hw_get_rx_filter() will pass to us the respective
2920 * hardware filters to be able to receive these type of frames.
2921 * o probe request frames are accepted only when operating in
2922 * hostap, adhoc, or monitor modes
2923 * o enable promiscuous mode according to the interface state
2925 * - when operating in adhoc mode so the 802.11 layer creates
2926 * node table entries for peers,
2927 * - when operating in station mode for collecting rssi data when
2928 * the station is otherwise quiet, or
2931 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2932 unsigned int changed_flags,
2933 unsigned int *new_flags,
2936 struct ath5k_softc *sc = hw->priv;
2937 struct ath5k_hw *ah = sc->ah;
2938 u32 mfilt[2], rfilt;
2940 mutex_lock(&sc->lock);
2942 mfilt[0] = multicast;
2943 mfilt[1] = multicast >> 32;
2945 /* Only deal with supported flags */
2946 changed_flags &= SUPPORTED_FIF_FLAGS;
2947 *new_flags &= SUPPORTED_FIF_FLAGS;
2949 /* If HW detects any phy or radar errors, leave those filters on.
2950 * Also, always enable Unicast, Broadcasts and Multicast
2951 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2952 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2953 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2954 AR5K_RX_FILTER_MCAST);
2956 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2957 if (*new_flags & FIF_PROMISC_IN_BSS) {
2958 rfilt |= AR5K_RX_FILTER_PROM;
2959 __set_bit(ATH_STAT_PROMISC, sc->status);
2961 __clear_bit(ATH_STAT_PROMISC, sc->status);
2965 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2966 if (*new_flags & FIF_ALLMULTI) {
2971 /* This is the best we can do */
2972 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2973 rfilt |= AR5K_RX_FILTER_PHYERR;
2975 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2976 * and probes for any BSSID, this needs testing */
2977 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2978 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2980 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2981 * set we should only pass on control frames for this
2982 * station. This needs testing. I believe right now this
2983 * enables *all* control frames, which is OK.. but
2984 * but we should see if we can improve on granularity */
2985 if (*new_flags & FIF_CONTROL)
2986 rfilt |= AR5K_RX_FILTER_CONTROL;
2988 /* Additional settings per mode -- this is per ath5k */
2990 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2992 switch (sc->opmode) {
2993 case NL80211_IFTYPE_MESH_POINT:
2994 case NL80211_IFTYPE_MONITOR:
2995 rfilt |= AR5K_RX_FILTER_CONTROL |
2996 AR5K_RX_FILTER_BEACON |
2997 AR5K_RX_FILTER_PROBEREQ |
2998 AR5K_RX_FILTER_PROM;
3000 case NL80211_IFTYPE_AP:
3001 case NL80211_IFTYPE_ADHOC:
3002 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3003 AR5K_RX_FILTER_BEACON;
3005 case NL80211_IFTYPE_STATION:
3007 rfilt |= AR5K_RX_FILTER_BEACON;
3013 ath5k_hw_set_rx_filter(ah, rfilt);
3015 /* Set multicast bits */
3016 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3017 /* Set the cached hw filter flags, this will alter actually
3019 sc->filter_flags = rfilt;
3021 mutex_unlock(&sc->lock);
3025 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3026 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3027 struct ieee80211_key_conf *key)
3029 struct ath5k_softc *sc = hw->priv;
3032 if (modparam_nohwcrypt)
3035 if (sc->opmode == NL80211_IFTYPE_AP)
3043 if (sc->ah->ah_aes_support)
3052 mutex_lock(&sc->lock);
3056 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3057 sta ? sta->addr : NULL);
3059 ATH5K_ERR(sc, "can't set the key\n");
3062 __set_bit(key->keyidx, sc->keymap);
3063 key->hw_key_idx = key->keyidx;
3064 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3065 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3068 ath5k_hw_reset_key(sc->ah, key->keyidx);
3069 __clear_bit(key->keyidx, sc->keymap);
3078 mutex_unlock(&sc->lock);
3083 ath5k_get_stats(struct ieee80211_hw *hw,
3084 struct ieee80211_low_level_stats *stats)
3086 struct ath5k_softc *sc = hw->priv;
3087 struct ath5k_hw *ah = sc->ah;
3090 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3092 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3098 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3099 struct ieee80211_tx_queue_stats *stats)
3101 struct ath5k_softc *sc = hw->priv;
3103 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3109 ath5k_get_tsf(struct ieee80211_hw *hw)
3111 struct ath5k_softc *sc = hw->priv;
3113 return ath5k_hw_get_tsf64(sc->ah);
3117 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3119 struct ath5k_softc *sc = hw->priv;
3121 ath5k_hw_set_tsf64(sc->ah, tsf);
3125 ath5k_reset_tsf(struct ieee80211_hw *hw)
3127 struct ath5k_softc *sc = hw->priv;
3130 * in IBSS mode we need to update the beacon timers too.
3131 * this will also reset the TSF if we call it with 0
3133 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3134 ath5k_beacon_update_timers(sc, 0);
3136 ath5k_hw_reset_tsf(sc->ah);
3140 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3141 * this is called only once at config_bss time, for AP we do it every
3142 * SWBA interrupt so that the TIM will reflect buffered frames.
3144 * Called with the beacon lock.
3147 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3150 struct ath5k_softc *sc = hw->priv;
3151 struct sk_buff *skb;
3153 if (WARN_ON(!vif)) {
3158 skb = ieee80211_beacon_get(hw, vif);
3165 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3167 ath5k_txbuf_free(sc, sc->bbuf);
3168 sc->bbuf->skb = skb;
3169 ret = ath5k_beacon_setup(sc, sc->bbuf);
3171 sc->bbuf->skb = NULL;
3177 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3179 struct ath5k_softc *sc = hw->priv;
3180 struct ath5k_hw *ah = sc->ah;
3182 rfilt = ath5k_hw_get_rx_filter(ah);
3184 rfilt |= AR5K_RX_FILTER_BEACON;
3186 rfilt &= ~AR5K_RX_FILTER_BEACON;
3187 ath5k_hw_set_rx_filter(ah, rfilt);
3188 sc->filter_flags = rfilt;
3191 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3192 struct ieee80211_vif *vif,
3193 struct ieee80211_bss_conf *bss_conf,
3196 struct ath5k_softc *sc = hw->priv;
3197 struct ath5k_hw *ah = sc->ah;
3198 struct ath_common *common = ath5k_hw_common(ah);
3199 unsigned long flags;
3201 mutex_lock(&sc->lock);
3202 if (WARN_ON(sc->vif != vif))
3205 if (changes & BSS_CHANGED_BSSID) {
3206 /* Cache for later use during resets */
3207 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3208 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3209 * a clean way of letting us retrieve this yet. */
3210 ath5k_hw_set_associd(ah, common->curbssid, 0);
3214 if (changes & BSS_CHANGED_BEACON_INT)
3215 sc->bintval = bss_conf->beacon_int;
3217 if (changes & BSS_CHANGED_ASSOC) {
3218 sc->assoc = bss_conf->assoc;
3219 if (sc->opmode == NL80211_IFTYPE_STATION)
3220 set_beacon_filter(hw, sc->assoc);
3221 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3222 AR5K_LED_ASSOC : AR5K_LED_INIT);
3225 if (changes & BSS_CHANGED_BEACON) {
3226 spin_lock_irqsave(&sc->block, flags);
3227 ath5k_beacon_update(hw, vif);
3228 spin_unlock_irqrestore(&sc->block, flags);
3231 if (changes & BSS_CHANGED_BEACON_ENABLED)
3232 sc->enable_beacon = bss_conf->enable_beacon;
3234 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3235 BSS_CHANGED_BEACON_INT))
3236 ath5k_beacon_config(sc);
3239 mutex_unlock(&sc->lock);
3242 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3244 struct ath5k_softc *sc = hw->priv;
3246 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3249 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3251 struct ath5k_softc *sc = hw->priv;
3252 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3253 AR5K_LED_ASSOC : AR5K_LED_INIT);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob