2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
200 static int ath5k_pci_resume(struct pci_dev *pdev);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static const struct ieee80211_ops ath5k_hw_ops = {
260 .start = ath5k_start,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
265 .prepare_multicast = ath5k_prepare_multicast,
266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
270 .get_tx_stats = ath5k_get_tx_stats,
271 .get_tsf = ath5k_get_tsf,
272 .set_tsf = ath5k_set_tsf,
273 .reset_tsf = ath5k_reset_tsf,
274 .bss_info_changed = ath5k_bss_info_changed,
275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
280 * Prototypes - Internal functions
283 static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285 static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287 /* Channel/mode setup */
288 static inline short ath5k_ieee2mhz(short chan);
289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
293 static int ath5k_setup_bands(struct ieee80211_hw *hw);
294 static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296 static void ath5k_setcurmode(struct ath5k_softc *sc,
298 static void ath5k_mode_setup(struct ath5k_softc *sc);
300 /* Descriptor setup */
301 static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303 static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
319 dev_kfree_skb_any(bf->skb);
323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
329 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
331 dev_kfree_skb_any(bf->skb);
337 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
338 int qtype, int subtype);
339 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
340 static int ath5k_beaconq_config(struct ath5k_softc *sc);
341 static void ath5k_txq_drainq(struct ath5k_softc *sc,
342 struct ath5k_txq *txq);
343 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
344 static void ath5k_txq_release(struct ath5k_softc *sc);
346 static int ath5k_rx_start(struct ath5k_softc *sc);
347 static void ath5k_rx_stop(struct ath5k_softc *sc);
348 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
349 struct ath5k_desc *ds,
351 struct ath5k_rx_status *rs);
352 static void ath5k_tasklet_rx(unsigned long data);
354 static void ath5k_tx_processq(struct ath5k_softc *sc,
355 struct ath5k_txq *txq);
356 static void ath5k_tasklet_tx(unsigned long data);
357 /* Beacon handling */
358 static int ath5k_beacon_setup(struct ath5k_softc *sc,
359 struct ath5k_buf *bf);
360 static void ath5k_beacon_send(struct ath5k_softc *sc);
361 static void ath5k_beacon_config(struct ath5k_softc *sc);
362 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
363 static void ath5k_tasklet_beacon(unsigned long data);
365 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
367 u64 tsf = ath5k_hw_get_tsf64(ah);
369 if ((tsf & 0x7fff) < rstamp)
372 return (tsf & ~0x7fff) | rstamp;
375 /* Interrupt handling */
376 static int ath5k_init(struct ath5k_softc *sc);
377 static int ath5k_stop_locked(struct ath5k_softc *sc);
378 static int ath5k_stop_hw(struct ath5k_softc *sc);
379 static irqreturn_t ath5k_intr(int irq, void *dev_id);
380 static void ath5k_tasklet_reset(unsigned long data);
382 static void ath5k_tasklet_calibrate(unsigned long data);
385 * Module init/exit functions
394 ret = pci_register_driver(&ath5k_pci_driver);
396 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
406 pci_unregister_driver(&ath5k_pci_driver);
408 ath5k_debug_finish();
411 module_init(init_ath5k_pci);
412 module_exit(exit_ath5k_pci);
415 /********************\
416 * PCI Initialization *
417 \********************/
420 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
422 const char *name = "xxxxx";
425 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
426 if (srev_names[i].sr_type != type)
429 if ((val & 0xf0) == srev_names[i].sr_val)
430 name = srev_names[i].sr_name;
432 if ((val & 0xff) == srev_names[i].sr_val) {
433 name = srev_names[i].sr_name;
440 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
442 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
443 return ath5k_hw_reg_read(ah, reg_offset);
446 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
448 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
449 ath5k_hw_reg_write(ah, val, reg_offset);
452 static const struct ath_ops ath5k_common_ops = {
453 .read = ath5k_ioread32,
454 .write = ath5k_iowrite32,
458 ath5k_pci_probe(struct pci_dev *pdev,
459 const struct pci_device_id *id)
462 struct ath5k_softc *sc;
463 struct ath_common *common;
464 struct ieee80211_hw *hw;
468 ret = pci_enable_device(pdev);
470 dev_err(&pdev->dev, "can't enable device\n");
474 /* XXX 32-bit addressing only */
475 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
477 dev_err(&pdev->dev, "32-bit DMA not available\n");
482 * Cache line size is used to size and align various
483 * structures used to communicate with the hardware.
485 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
488 * Linux 2.4.18 (at least) writes the cache line size
489 * register as a 16-bit wide register which is wrong.
490 * We must have this setup properly for rx buffer
491 * DMA to work so force a reasonable value here if it
494 csz = L1_CACHE_BYTES >> 2;
495 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
498 * The default setting of latency timer yields poor results,
499 * set it to the value used by other systems. It may be worth
500 * tweaking this setting more.
502 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
504 /* Enable bus mastering */
505 pci_set_master(pdev);
508 * Disable the RETRY_TIMEOUT register (0x41) to keep
509 * PCI Tx retries from interfering with C3 CPU state.
511 pci_write_config_byte(pdev, 0x41, 0);
513 ret = pci_request_region(pdev, 0, "ath5k");
515 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
519 mem = pci_iomap(pdev, 0, 0);
521 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
527 * Allocate hw (mac80211 main struct)
528 * and hw->priv (driver private data)
530 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
532 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
537 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
539 /* Initialize driver private data */
540 SET_IEEE80211_DEV(hw, &pdev->dev);
541 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
542 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
543 IEEE80211_HW_SIGNAL_DBM |
544 IEEE80211_HW_NOISE_DBM;
546 hw->wiphy->interface_modes =
547 BIT(NL80211_IFTYPE_AP) |
548 BIT(NL80211_IFTYPE_STATION) |
549 BIT(NL80211_IFTYPE_ADHOC) |
550 BIT(NL80211_IFTYPE_MESH_POINT);
552 hw->extra_tx_headroom = 2;
553 hw->channel_change_time = 5000;
558 ath5k_debug_init_device(sc);
561 * Mark the device as detached to avoid processing
562 * interrupts until setup is complete.
564 __set_bit(ATH_STAT_INVALID, sc->status);
566 sc->iobase = mem; /* So we can unmap it on detach */
567 sc->opmode = NL80211_IFTYPE_STATION;
569 mutex_init(&sc->lock);
570 spin_lock_init(&sc->rxbuflock);
571 spin_lock_init(&sc->txbuflock);
572 spin_lock_init(&sc->block);
574 /* Set private data */
575 pci_set_drvdata(pdev, hw);
577 /* Setup interrupt handler */
578 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
580 ATH5K_ERR(sc, "request_irq failed\n");
584 /*If we passed the test malloc a ath5k_hw struct*/
585 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
588 ATH5K_ERR(sc, "out of memory\n");
593 sc->ah->ah_iobase = sc->iobase;
594 common = ath5k_hw_common(sc->ah);
595 common->ops = &ath5k_common_ops;
597 common->cachelsz = csz << 2; /* convert to bytes */
599 /* Initialize device */
600 ret = ath5k_hw_attach(sc);
605 /* set up multi-rate retry capabilities */
606 if (sc->ah->ah_version == AR5K_AR5212) {
608 hw->max_rate_tries = 11;
611 /* Finish private driver data initialization */
612 ret = ath5k_attach(pdev, hw);
616 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
617 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
619 sc->ah->ah_phy_revision);
621 if (!sc->ah->ah_single_chip) {
622 /* Single chip radio (!RF5111) */
623 if (sc->ah->ah_radio_5ghz_revision &&
624 !sc->ah->ah_radio_2ghz_revision) {
625 /* No 5GHz support -> report 2GHz radio */
626 if (!test_bit(AR5K_MODE_11A,
627 sc->ah->ah_capabilities.cap_mode)) {
628 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
629 ath5k_chip_name(AR5K_VERSION_RAD,
630 sc->ah->ah_radio_5ghz_revision),
631 sc->ah->ah_radio_5ghz_revision);
632 /* No 2GHz support (5110 and some
633 * 5Ghz only cards) -> report 5Ghz radio */
634 } else if (!test_bit(AR5K_MODE_11B,
635 sc->ah->ah_capabilities.cap_mode)) {
636 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
637 ath5k_chip_name(AR5K_VERSION_RAD,
638 sc->ah->ah_radio_5ghz_revision),
639 sc->ah->ah_radio_5ghz_revision);
640 /* Multiband radio */
642 ATH5K_INFO(sc, "RF%s multiband radio found"
644 ath5k_chip_name(AR5K_VERSION_RAD,
645 sc->ah->ah_radio_5ghz_revision),
646 sc->ah->ah_radio_5ghz_revision);
649 /* Multi chip radio (RF5111 - RF2111) ->
650 * report both 2GHz/5GHz radios */
651 else if (sc->ah->ah_radio_5ghz_revision &&
652 sc->ah->ah_radio_2ghz_revision){
653 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
654 ath5k_chip_name(AR5K_VERSION_RAD,
655 sc->ah->ah_radio_5ghz_revision),
656 sc->ah->ah_radio_5ghz_revision);
657 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
658 ath5k_chip_name(AR5K_VERSION_RAD,
659 sc->ah->ah_radio_2ghz_revision),
660 sc->ah->ah_radio_2ghz_revision);
665 /* ready to process interrupts */
666 __clear_bit(ATH_STAT_INVALID, sc->status);
670 ath5k_hw_detach(sc->ah);
672 free_irq(pdev->irq, sc);
676 ieee80211_free_hw(hw);
678 pci_iounmap(pdev, mem);
680 pci_release_region(pdev, 0);
682 pci_disable_device(pdev);
687 static void __devexit
688 ath5k_pci_remove(struct pci_dev *pdev)
690 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
691 struct ath5k_softc *sc = hw->priv;
693 ath5k_debug_finish_device(sc);
694 ath5k_detach(pdev, hw);
695 ath5k_hw_detach(sc->ah);
697 free_irq(pdev->irq, sc);
698 pci_iounmap(pdev, sc->iobase);
699 pci_release_region(pdev, 0);
700 pci_disable_device(pdev);
701 ieee80211_free_hw(hw);
706 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
708 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
709 struct ath5k_softc *sc = hw->priv;
713 pci_save_state(pdev);
714 pci_disable_device(pdev);
715 pci_set_power_state(pdev, PCI_D3hot);
721 ath5k_pci_resume(struct pci_dev *pdev)
723 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
724 struct ath5k_softc *sc = hw->priv;
727 pci_restore_state(pdev);
729 err = pci_enable_device(pdev);
734 * Suspend/Resume resets the PCI configuration space, so we have to
735 * re-disable the RETRY_TIMEOUT register (0x41) to keep
736 * PCI Tx retries from interfering with C3 CPU state
738 pci_write_config_byte(pdev, 0x41, 0);
740 ath5k_led_enable(sc);
743 #endif /* CONFIG_PM */
746 /***********************\
747 * Driver Initialization *
748 \***********************/
750 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
752 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
753 struct ath5k_softc *sc = hw->priv;
754 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
756 return ath_reg_notifier_apply(wiphy, request, regulatory);
760 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
762 struct ath5k_softc *sc = hw->priv;
763 struct ath5k_hw *ah = sc->ah;
764 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
765 u8 mac[ETH_ALEN] = {};
768 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
771 * Check if the MAC has multi-rate retry support.
772 * We do this by trying to setup a fake extended
773 * descriptor. MAC's that don't have support will
774 * return false w/o doing anything. MAC's that do
775 * support it will return true w/o doing anything.
777 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
781 __set_bit(ATH_STAT_MRRETRY, sc->status);
784 * Collect the channel list. The 802.11 layer
785 * is resposible for filtering this list based
786 * on settings like the phy mode and regulatory
787 * domain restrictions.
789 ret = ath5k_setup_bands(hw);
791 ATH5K_ERR(sc, "can't get channels\n");
795 /* NB: setup here so ath5k_rate_update is happy */
796 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
797 ath5k_setcurmode(sc, AR5K_MODE_11A);
799 ath5k_setcurmode(sc, AR5K_MODE_11B);
802 * Allocate tx+rx descriptors and populate the lists.
804 ret = ath5k_desc_alloc(sc, pdev);
806 ATH5K_ERR(sc, "can't allocate descriptors\n");
811 * Allocate hardware transmit queues: one queue for
812 * beacon frames and one data queue for each QoS
813 * priority. Note that hw functions handle reseting
814 * these queues at the needed time.
816 ret = ath5k_beaconq_setup(ah);
818 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
822 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
823 if (IS_ERR(sc->cabq)) {
824 ATH5K_ERR(sc, "can't setup cab queue\n");
825 ret = PTR_ERR(sc->cabq);
829 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
830 if (IS_ERR(sc->txq)) {
831 ATH5K_ERR(sc, "can't setup xmit queue\n");
832 ret = PTR_ERR(sc->txq);
836 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
837 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
838 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
839 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
840 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
842 ret = ath5k_eeprom_read_mac(ah, mac);
844 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
849 SET_IEEE80211_PERM_ADDR(hw, mac);
850 /* All MAC address bits matter for ACKs */
851 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
852 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
854 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
855 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
857 ATH5K_ERR(sc, "can't initialize regulatory system\n");
861 ret = ieee80211_register_hw(hw);
863 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
867 if (!ath_is_world_regd(regulatory))
868 regulatory_hint(hw->wiphy, regulatory->alpha2);
874 ath5k_txq_release(sc);
876 ath5k_hw_release_tx_queue(ah, sc->bhalq);
878 ath5k_desc_free(sc, pdev);
884 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
886 struct ath5k_softc *sc = hw->priv;
889 * NB: the order of these is important:
890 * o call the 802.11 layer before detaching ath5k_hw to
891 * insure callbacks into the driver to delete global
892 * key cache entries can be handled
893 * o reclaim the tx queue data structures after calling
894 * the 802.11 layer as we'll get called back to reclaim
895 * node state and potentially want to use them
896 * o to cleanup the tx queues the hal is called, so detach
898 * XXX: ??? detach ath5k_hw ???
899 * Other than that, it's straightforward...
901 ieee80211_unregister_hw(hw);
902 ath5k_desc_free(sc, pdev);
903 ath5k_txq_release(sc);
904 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
905 ath5k_unregister_leds(sc);
908 * NB: can't reclaim these until after ieee80211_ifdetach
909 * returns because we'll get called back to reclaim node
910 * state and potentially want to use them.
917 /********************\
918 * Channel/mode setup *
919 \********************/
922 * Convert IEEE channel number to MHz frequency.
925 ath5k_ieee2mhz(short chan)
927 if (chan <= 14 || chan >= 27)
928 return ieee80211chan2mhz(chan);
930 return 2212 + chan * 20;
934 * Returns true for the channel numbers used without all_channels modparam.
936 static bool ath5k_is_standard_channel(short chan)
938 return ((chan <= 14) ||
940 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
942 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
944 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
948 ath5k_copy_channels(struct ath5k_hw *ah,
949 struct ieee80211_channel *channels,
953 unsigned int i, count, size, chfreq, freq, ch;
955 if (!test_bit(mode, ah->ah_modes))
960 case AR5K_MODE_11A_TURBO:
961 /* 1..220, but 2GHz frequencies are filtered by check_channel */
963 chfreq = CHANNEL_5GHZ;
967 case AR5K_MODE_11G_TURBO:
969 chfreq = CHANNEL_2GHZ;
972 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
976 for (i = 0, count = 0; i < size && max > 0; i++) {
978 freq = ath5k_ieee2mhz(ch);
980 /* Check if channel is supported by the chipset */
981 if (!ath5k_channel_ok(ah, freq, chfreq))
984 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
987 /* Write channel info and increment counter */
988 channels[count].center_freq = freq;
989 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
990 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
994 channels[count].hw_value = chfreq | CHANNEL_OFDM;
996 case AR5K_MODE_11A_TURBO:
997 case AR5K_MODE_11G_TURBO:
998 channels[count].hw_value = chfreq |
999 CHANNEL_OFDM | CHANNEL_TURBO;
1002 channels[count].hw_value = CHANNEL_B;
1013 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1017 for (i = 0; i < AR5K_MAX_RATES; i++)
1018 sc->rate_idx[b->band][i] = -1;
1020 for (i = 0; i < b->n_bitrates; i++) {
1021 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1022 if (b->bitrates[i].hw_value_short)
1023 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1028 ath5k_setup_bands(struct ieee80211_hw *hw)
1030 struct ath5k_softc *sc = hw->priv;
1031 struct ath5k_hw *ah = sc->ah;
1032 struct ieee80211_supported_band *sband;
1033 int max_c, count_c = 0;
1036 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1037 max_c = ARRAY_SIZE(sc->channels);
1040 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1041 sband->band = IEEE80211_BAND_2GHZ;
1042 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1044 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1046 memcpy(sband->bitrates, &ath5k_rates[0],
1047 sizeof(struct ieee80211_rate) * 12);
1048 sband->n_bitrates = 12;
1050 sband->channels = sc->channels;
1051 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1052 AR5K_MODE_11G, max_c);
1054 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1055 count_c = sband->n_channels;
1057 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1059 memcpy(sband->bitrates, &ath5k_rates[0],
1060 sizeof(struct ieee80211_rate) * 4);
1061 sband->n_bitrates = 4;
1063 /* 5211 only supports B rates and uses 4bit rate codes
1064 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1067 if (ah->ah_version == AR5K_AR5211) {
1068 for (i = 0; i < 4; i++) {
1069 sband->bitrates[i].hw_value =
1070 sband->bitrates[i].hw_value & 0xF;
1071 sband->bitrates[i].hw_value_short =
1072 sband->bitrates[i].hw_value_short & 0xF;
1076 sband->channels = sc->channels;
1077 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1078 AR5K_MODE_11B, max_c);
1080 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1081 count_c = sband->n_channels;
1084 ath5k_setup_rate_idx(sc, sband);
1086 /* 5GHz band, A mode */
1087 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1088 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1089 sband->band = IEEE80211_BAND_5GHZ;
1090 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1092 memcpy(sband->bitrates, &ath5k_rates[4],
1093 sizeof(struct ieee80211_rate) * 8);
1094 sband->n_bitrates = 8;
1096 sband->channels = &sc->channels[count_c];
1097 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1098 AR5K_MODE_11A, max_c);
1100 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1102 ath5k_setup_rate_idx(sc, sband);
1104 ath5k_debug_dump_bands(sc);
1110 * Set/change channels. We always reset the chip.
1111 * To accomplish this we must first cleanup any pending DMA,
1112 * then restart stuff after a la ath5k_init.
1114 * Called with sc->lock.
1117 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1119 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1120 sc->curchan->center_freq, chan->center_freq);
1123 * To switch channels clear any pending DMA operations;
1124 * wait long enough for the RX fifo to drain, reset the
1125 * hardware at the new frequency, and then re-enable
1126 * the relevant bits of the h/w.
1128 return ath5k_reset(sc, chan);
1132 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1136 if (mode == AR5K_MODE_11A) {
1137 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1139 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1144 ath5k_mode_setup(struct ath5k_softc *sc)
1146 struct ath5k_hw *ah = sc->ah;
1149 ah->ah_op_mode = sc->opmode;
1151 /* configure rx filter */
1152 rfilt = sc->filter_flags;
1153 ath5k_hw_set_rx_filter(ah, rfilt);
1155 if (ath5k_hw_hasbssidmask(ah))
1156 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1158 /* configure operational mode */
1159 ath5k_hw_set_opmode(ah);
1161 ath5k_hw_set_mcast_filter(ah, 0, 0);
1162 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1166 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1170 /* return base rate on errors */
1171 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1172 "hw_rix out of bounds: %x\n", hw_rix))
1175 rix = sc->rate_idx[sc->curband->band][hw_rix];
1176 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1187 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1189 struct ath_common *common = ath5k_hw_common(sc->ah);
1190 struct sk_buff *skb;
1193 * Allocate buffer with headroom_needed space for the
1194 * fake physical layer header at the start.
1196 skb = ath_rxbuf_alloc(common,
1197 sc->rxbufsize + common->cachelsz - 1,
1201 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1202 sc->rxbufsize + common->cachelsz - 1);
1206 *skb_addr = pci_map_single(sc->pdev,
1207 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1208 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1209 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1217 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1219 struct ath5k_hw *ah = sc->ah;
1220 struct sk_buff *skb = bf->skb;
1221 struct ath5k_desc *ds;
1224 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1231 * Setup descriptors. For receive we always terminate
1232 * the descriptor list with a self-linked entry so we'll
1233 * not get overrun under high load (as can happen with a
1234 * 5212 when ANI processing enables PHY error frames).
1236 * To insure the last descriptor is self-linked we create
1237 * each descriptor as self-linked and add it to the end. As
1238 * each additional descriptor is added the previous self-linked
1239 * entry is ``fixed'' naturally. This should be safe even
1240 * if DMA is happening. When processing RX interrupts we
1241 * never remove/process the last, self-linked, entry on the
1242 * descriptor list. This insures the hardware always has
1243 * someplace to write a new frame.
1246 ds->ds_link = bf->daddr; /* link to self */
1247 ds->ds_data = bf->skbaddr;
1248 ah->ah_setup_rx_desc(ah, ds,
1249 skb_tailroom(skb), /* buffer size */
1252 if (sc->rxlink != NULL)
1253 *sc->rxlink = bf->daddr;
1254 sc->rxlink = &ds->ds_link;
1259 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1260 struct ath5k_txq *txq)
1262 struct ath5k_hw *ah = sc->ah;
1263 struct ath5k_desc *ds = bf->desc;
1264 struct sk_buff *skb = bf->skb;
1265 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1266 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1267 struct ieee80211_rate *rate;
1268 unsigned int mrr_rate[3], mrr_tries[3];
1275 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1277 /* XXX endianness */
1278 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1281 rate = ieee80211_get_tx_rate(sc->hw, info);
1283 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1284 flags |= AR5K_TXDESC_NOACK;
1286 rc_flags = info->control.rates[0].flags;
1287 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1288 rate->hw_value_short : rate->hw_value;
1292 /* FIXME: If we are in g mode and rate is a CCK rate
1293 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1294 * from tx power (value is in dB units already) */
1295 if (info->control.hw_key) {
1296 keyidx = info->control.hw_key->hw_key_idx;
1297 pktlen += info->control.hw_key->icv_len;
1299 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1300 flags |= AR5K_TXDESC_RTSENA;
1301 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1302 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1303 sc->vif, pktlen, info));
1305 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1306 flags |= AR5K_TXDESC_CTSENA;
1307 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1308 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1309 sc->vif, pktlen, info));
1311 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1312 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1313 (sc->power_level * 2),
1315 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1316 cts_rate, duration);
1320 memset(mrr_rate, 0, sizeof(mrr_rate));
1321 memset(mrr_tries, 0, sizeof(mrr_tries));
1322 for (i = 0; i < 3; i++) {
1323 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1327 mrr_rate[i] = rate->hw_value;
1328 mrr_tries[i] = info->control.rates[i + 1].count;
1331 ah->ah_setup_mrr_tx_desc(ah, ds,
1332 mrr_rate[0], mrr_tries[0],
1333 mrr_rate[1], mrr_tries[1],
1334 mrr_rate[2], mrr_tries[2]);
1337 ds->ds_data = bf->skbaddr;
1339 spin_lock_bh(&txq->lock);
1340 list_add_tail(&bf->list, &txq->q);
1341 sc->tx_stats[txq->qnum].len++;
1342 if (txq->link == NULL) /* is this first packet? */
1343 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1344 else /* no, so only link it */
1345 *txq->link = bf->daddr;
1347 txq->link = &ds->ds_link;
1348 ath5k_hw_start_tx_dma(ah, txq->qnum);
1350 spin_unlock_bh(&txq->lock);
1354 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1358 /*******************\
1359 * Descriptors setup *
1360 \*******************/
1363 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1365 struct ath5k_desc *ds;
1366 struct ath5k_buf *bf;
1371 /* allocate descriptors */
1372 sc->desc_len = sizeof(struct ath5k_desc) *
1373 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1374 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1375 if (sc->desc == NULL) {
1376 ATH5K_ERR(sc, "can't allocate descriptors\n");
1381 da = sc->desc_daddr;
1382 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1383 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1385 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1386 sizeof(struct ath5k_buf), GFP_KERNEL);
1388 ATH5K_ERR(sc, "can't allocate bufptr\n");
1394 INIT_LIST_HEAD(&sc->rxbuf);
1395 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1398 list_add_tail(&bf->list, &sc->rxbuf);
1401 INIT_LIST_HEAD(&sc->txbuf);
1402 sc->txbuf_len = ATH_TXBUF;
1403 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1404 da += sizeof(*ds)) {
1407 list_add_tail(&bf->list, &sc->txbuf);
1417 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1424 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1426 struct ath5k_buf *bf;
1428 ath5k_txbuf_free(sc, sc->bbuf);
1429 list_for_each_entry(bf, &sc->txbuf, list)
1430 ath5k_txbuf_free(sc, bf);
1431 list_for_each_entry(bf, &sc->rxbuf, list)
1432 ath5k_rxbuf_free(sc, bf);
1434 /* Free memory associated with all descriptors */
1435 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1449 static struct ath5k_txq *
1450 ath5k_txq_setup(struct ath5k_softc *sc,
1451 int qtype, int subtype)
1453 struct ath5k_hw *ah = sc->ah;
1454 struct ath5k_txq *txq;
1455 struct ath5k_txq_info qi = {
1456 .tqi_subtype = subtype,
1457 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1458 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1459 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1464 * Enable interrupts only for EOL and DESC conditions.
1465 * We mark tx descriptors to receive a DESC interrupt
1466 * when a tx queue gets deep; otherwise waiting for the
1467 * EOL to reap descriptors. Note that this is done to
1468 * reduce interrupt load and this only defers reaping
1469 * descriptors, never transmitting frames. Aside from
1470 * reducing interrupts this also permits more concurrency.
1471 * The only potential downside is if the tx queue backs
1472 * up in which case the top half of the kernel may backup
1473 * due to a lack of tx descriptors.
1475 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1476 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1477 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1480 * NB: don't print a message, this happens
1481 * normally on parts with too few tx queues
1483 return ERR_PTR(qnum);
1485 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1486 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1487 qnum, ARRAY_SIZE(sc->txqs));
1488 ath5k_hw_release_tx_queue(ah, qnum);
1489 return ERR_PTR(-EINVAL);
1491 txq = &sc->txqs[qnum];
1495 INIT_LIST_HEAD(&txq->q);
1496 spin_lock_init(&txq->lock);
1499 return &sc->txqs[qnum];
1503 ath5k_beaconq_setup(struct ath5k_hw *ah)
1505 struct ath5k_txq_info qi = {
1506 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1507 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1508 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1509 /* NB: for dynamic turbo, don't enable any other interrupts */
1510 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1513 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1517 ath5k_beaconq_config(struct ath5k_softc *sc)
1519 struct ath5k_hw *ah = sc->ah;
1520 struct ath5k_txq_info qi;
1523 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1526 if (sc->opmode == NL80211_IFTYPE_AP ||
1527 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1529 * Always burst out beacon and CAB traffic
1530 * (aifs = cwmin = cwmax = 0)
1535 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1537 * Adhoc mode; backoff between 0 and (2 * cw_min).
1541 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1544 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1545 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1546 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1548 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1550 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1551 "hardware queue!\n", __func__);
1555 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1559 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1561 struct ath5k_buf *bf, *bf0;
1564 * NB: this assumes output has been stopped and
1565 * we do not need to block ath5k_tx_tasklet
1567 spin_lock_bh(&txq->lock);
1568 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1569 ath5k_debug_printtxbuf(sc, bf);
1571 ath5k_txbuf_free(sc, bf);
1573 spin_lock_bh(&sc->txbuflock);
1574 sc->tx_stats[txq->qnum].len--;
1575 list_move_tail(&bf->list, &sc->txbuf);
1577 spin_unlock_bh(&sc->txbuflock);
1580 spin_unlock_bh(&txq->lock);
1584 * Drain the transmit queues and reclaim resources.
1587 ath5k_txq_cleanup(struct ath5k_softc *sc)
1589 struct ath5k_hw *ah = sc->ah;
1592 /* XXX return value */
1593 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1594 /* don't touch the hardware if marked invalid */
1595 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1596 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1597 ath5k_hw_get_txdp(ah, sc->bhalq));
1598 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1599 if (sc->txqs[i].setup) {
1600 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1601 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1604 ath5k_hw_get_txdp(ah,
1609 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1611 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1612 if (sc->txqs[i].setup)
1613 ath5k_txq_drainq(sc, &sc->txqs[i]);
1617 ath5k_txq_release(struct ath5k_softc *sc)
1619 struct ath5k_txq *txq = sc->txqs;
1622 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1624 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1637 * Enable the receive h/w following a reset.
1640 ath5k_rx_start(struct ath5k_softc *sc)
1642 struct ath5k_hw *ah = sc->ah;
1643 struct ath_common *common = ath5k_hw_common(ah);
1644 struct ath5k_buf *bf;
1647 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1649 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1650 common->cachelsz, sc->rxbufsize);
1652 spin_lock_bh(&sc->rxbuflock);
1654 list_for_each_entry(bf, &sc->rxbuf, list) {
1655 ret = ath5k_rxbuf_setup(sc, bf);
1657 spin_unlock_bh(&sc->rxbuflock);
1661 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1662 ath5k_hw_set_rxdp(ah, bf->daddr);
1663 spin_unlock_bh(&sc->rxbuflock);
1665 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1666 ath5k_mode_setup(sc); /* set filters, etc. */
1667 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1675 * Disable the receive h/w in preparation for a reset.
1678 ath5k_rx_stop(struct ath5k_softc *sc)
1680 struct ath5k_hw *ah = sc->ah;
1682 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1683 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1684 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1686 ath5k_debug_printrxbuffs(sc, ah);
1688 sc->rxlink = NULL; /* just in case */
1692 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1693 struct sk_buff *skb, struct ath5k_rx_status *rs)
1695 struct ieee80211_hdr *hdr = (void *)skb->data;
1696 unsigned int keyix, hlen;
1698 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1699 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1700 return RX_FLAG_DECRYPTED;
1702 /* Apparently when a default key is used to decrypt the packet
1703 the hw does not set the index used to decrypt. In such cases
1704 get the index from the packet. */
1705 hlen = ieee80211_hdrlen(hdr->frame_control);
1706 if (ieee80211_has_protected(hdr->frame_control) &&
1707 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1708 skb->len >= hlen + 4) {
1709 keyix = skb->data[hlen + 3] >> 6;
1711 if (test_bit(keyix, sc->keymap))
1712 return RX_FLAG_DECRYPTED;
1720 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1721 struct ieee80211_rx_status *rxs)
1723 struct ath_common *common = ath5k_hw_common(sc->ah);
1726 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1728 if (ieee80211_is_beacon(mgmt->frame_control) &&
1729 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1730 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1732 * Received an IBSS beacon with the same BSSID. Hardware *must*
1733 * have updated the local TSF. We have to work around various
1734 * hardware bugs, though...
1736 tsf = ath5k_hw_get_tsf64(sc->ah);
1737 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1738 hw_tu = TSF_TO_TU(tsf);
1740 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1741 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1742 (unsigned long long)bc_tstamp,
1743 (unsigned long long)rxs->mactime,
1744 (unsigned long long)(rxs->mactime - bc_tstamp),
1745 (unsigned long long)tsf);
1748 * Sometimes the HW will give us a wrong tstamp in the rx
1749 * status, causing the timestamp extension to go wrong.
1750 * (This seems to happen especially with beacon frames bigger
1751 * than 78 byte (incl. FCS))
1752 * But we know that the receive timestamp must be later than the
1753 * timestamp of the beacon since HW must have synced to that.
1755 * NOTE: here we assume mactime to be after the frame was
1756 * received, not like mac80211 which defines it at the start.
1758 if (bc_tstamp > rxs->mactime) {
1759 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1760 "fixing mactime from %llx to %llx\n",
1761 (unsigned long long)rxs->mactime,
1762 (unsigned long long)tsf);
1767 * Local TSF might have moved higher than our beacon timers,
1768 * in that case we have to update them to continue sending
1769 * beacons. This also takes care of synchronizing beacon sending
1770 * times with other stations.
1772 if (hw_tu >= sc->nexttbtt)
1773 ath5k_beacon_update_timers(sc, bc_tstamp);
1778 ath5k_tasklet_rx(unsigned long data)
1780 struct ieee80211_rx_status *rxs;
1781 struct ath5k_rx_status rs = {};
1782 struct sk_buff *skb, *next_skb;
1783 dma_addr_t next_skb_addr;
1784 struct ath5k_softc *sc = (void *)data;
1785 struct ath5k_buf *bf;
1786 struct ath5k_desc *ds;
1792 spin_lock(&sc->rxbuflock);
1793 if (list_empty(&sc->rxbuf)) {
1794 ATH5K_WARN(sc, "empty rx buf pool\n");
1800 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1801 BUG_ON(bf->skb == NULL);
1805 /* bail if HW is still using self-linked descriptor */
1806 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1809 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1810 if (unlikely(ret == -EINPROGRESS))
1812 else if (unlikely(ret)) {
1813 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1814 spin_unlock(&sc->rxbuflock);
1818 if (unlikely(rs.rs_more)) {
1819 ATH5K_WARN(sc, "unsupported jumbo\n");
1823 if (unlikely(rs.rs_status)) {
1824 if (rs.rs_status & AR5K_RXERR_PHY)
1826 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1828 * Decrypt error. If the error occurred
1829 * because there was no hardware key, then
1830 * let the frame through so the upper layers
1831 * can process it. This is necessary for 5210
1832 * parts which have no way to setup a ``clear''
1835 * XXX do key cache faulting
1837 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1838 !(rs.rs_status & AR5K_RXERR_CRC))
1841 if (rs.rs_status & AR5K_RXERR_MIC) {
1842 rx_flag |= RX_FLAG_MMIC_ERROR;
1846 /* let crypto-error packets fall through in MNTR */
1848 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1849 sc->opmode != NL80211_IFTYPE_MONITOR)
1853 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1856 * If we can't replace bf->skb with a new skb under memory
1857 * pressure, just skip this packet
1862 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1863 PCI_DMA_FROMDEVICE);
1864 skb_put(skb, rs.rs_datalen);
1866 /* The MAC header is padded to have 32-bit boundary if the
1867 * packet payload is non-zero. The general calculation for
1868 * padsize would take into account odd header lengths:
1869 * padsize = (4 - hdrlen % 4) % 4; However, since only
1870 * even-length headers are used, padding can only be 0 or 2
1871 * bytes and we can optimize this a bit. In addition, we must
1872 * not try to remove padding from short control frames that do
1873 * not have payload. */
1874 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1875 padsize = ath5k_pad_size(hdrlen);
1877 memmove(skb->data + padsize, skb->data, hdrlen);
1878 skb_pull(skb, padsize);
1880 rxs = IEEE80211_SKB_RXCB(skb);
1883 * always extend the mac timestamp, since this information is
1884 * also needed for proper IBSS merging.
1886 * XXX: it might be too late to do it here, since rs_tstamp is
1887 * 15bit only. that means TSF extension has to be done within
1888 * 32768usec (about 32ms). it might be necessary to move this to
1889 * the interrupt handler, like it is done in madwifi.
1891 * Unfortunately we don't know when the hardware takes the rx
1892 * timestamp (beginning of phy frame, data frame, end of rx?).
1893 * The only thing we know is that it is hardware specific...
1894 * On AR5213 it seems the rx timestamp is at the end of the
1895 * frame, but i'm not sure.
1897 * NOTE: mac80211 defines mactime at the beginning of the first
1898 * data symbol. Since we don't have any time references it's
1899 * impossible to comply to that. This affects IBSS merge only
1900 * right now, so it's not too bad...
1902 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1903 rxs->flag = rx_flag | RX_FLAG_TSFT;
1905 rxs->freq = sc->curchan->center_freq;
1906 rxs->band = sc->curband->band;
1908 rxs->noise = sc->ah->ah_noise_floor;
1909 rxs->signal = rxs->noise + rs.rs_rssi;
1911 /* An rssi of 35 indicates you should be able use
1912 * 54 Mbps reliably. A more elaborate scheme can be used
1913 * here but it requires a map of SNR/throughput for each
1914 * possible mode used */
1915 rxs->qual = rs.rs_rssi * 100 / 35;
1917 /* rssi can be more than 35 though, anything above that
1918 * should be considered at 100% */
1919 if (rxs->qual > 100)
1922 rxs->antenna = rs.rs_antenna;
1923 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1924 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1926 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1927 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1928 rxs->flag |= RX_FLAG_SHORTPRE;
1930 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1932 /* check beacons in IBSS mode */
1933 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1934 ath5k_check_ibss_tsf(sc, skb, rxs);
1936 ieee80211_rx(sc->hw, skb);
1939 bf->skbaddr = next_skb_addr;
1941 list_move_tail(&bf->list, &sc->rxbuf);
1942 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1944 spin_unlock(&sc->rxbuflock);
1955 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1957 struct ath5k_tx_status ts = {};
1958 struct ath5k_buf *bf, *bf0;
1959 struct ath5k_desc *ds;
1960 struct sk_buff *skb;
1961 struct ieee80211_tx_info *info;
1964 spin_lock(&txq->lock);
1965 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1968 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1969 if (unlikely(ret == -EINPROGRESS))
1971 else if (unlikely(ret)) {
1972 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1978 info = IEEE80211_SKB_CB(skb);
1981 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1984 ieee80211_tx_info_clear_status(info);
1985 for (i = 0; i < 4; i++) {
1986 struct ieee80211_tx_rate *r =
1987 &info->status.rates[i];
1989 if (ts.ts_rate[i]) {
1990 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1991 r->count = ts.ts_retry[i];
1998 /* count the successful attempt as well */
1999 info->status.rates[ts.ts_final_idx].count++;
2001 if (unlikely(ts.ts_status)) {
2002 sc->ll_stats.dot11ACKFailureCount++;
2003 if (ts.ts_status & AR5K_TXERR_FILT)
2004 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2006 info->flags |= IEEE80211_TX_STAT_ACK;
2007 info->status.ack_signal = ts.ts_rssi;
2010 ieee80211_tx_status(sc->hw, skb);
2011 sc->tx_stats[txq->qnum].count++;
2013 spin_lock(&sc->txbuflock);
2014 sc->tx_stats[txq->qnum].len--;
2015 list_move_tail(&bf->list, &sc->txbuf);
2017 spin_unlock(&sc->txbuflock);
2019 if (likely(list_empty(&txq->q)))
2021 spin_unlock(&txq->lock);
2022 if (sc->txbuf_len > ATH_TXBUF / 5)
2023 ieee80211_wake_queues(sc->hw);
2027 ath5k_tasklet_tx(unsigned long data)
2030 struct ath5k_softc *sc = (void *)data;
2032 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2033 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2034 ath5k_tx_processq(sc, &sc->txqs[i]);
2043 * Setup the beacon frame for transmit.
2046 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2048 struct sk_buff *skb = bf->skb;
2049 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2050 struct ath5k_hw *ah = sc->ah;
2051 struct ath5k_desc *ds;
2056 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2058 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2059 "skbaddr %llx\n", skb, skb->data, skb->len,
2060 (unsigned long long)bf->skbaddr);
2061 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2062 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2067 antenna = ah->ah_tx_ant;
2069 flags = AR5K_TXDESC_NOACK;
2070 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2071 ds->ds_link = bf->daddr; /* self-linked */
2072 flags |= AR5K_TXDESC_VEOL;
2077 * If we use multiple antennas on AP and use
2078 * the Sectored AP scenario, switch antenna every
2079 * 4 beacons to make sure everybody hears our AP.
2080 * When a client tries to associate, hw will keep
2081 * track of the tx antenna to be used for this client
2082 * automaticaly, based on ACKed packets.
2084 * Note: AP still listens and transmits RTS on the
2085 * default antenna which is supposed to be an omni.
2087 * Note2: On sectored scenarios it's possible to have
2088 * multiple antennas (1omni -the default- and 14 sectors)
2089 * so if we choose to actually support this mode we need
2090 * to allow user to set how many antennas we have and tweak
2091 * the code below to send beacons on all of them.
2093 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2094 antenna = sc->bsent & 4 ? 2 : 1;
2097 /* FIXME: If we are in g mode and rate is a CCK rate
2098 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2099 * from tx power (value is in dB units already) */
2100 ds->ds_data = bf->skbaddr;
2101 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2102 ieee80211_get_hdrlen_from_skb(skb),
2103 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2104 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2105 1, AR5K_TXKEYIX_INVALID,
2106 antenna, flags, 0, 0);
2112 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2117 * Transmit a beacon frame at SWBA. Dynamic updates to the
2118 * frame contents are done as needed and the slot time is
2119 * also adjusted based on current state.
2121 * This is called from software irq context (beacontq or restq
2122 * tasklets) or user context from ath5k_beacon_config.
2125 ath5k_beacon_send(struct ath5k_softc *sc)
2127 struct ath5k_buf *bf = sc->bbuf;
2128 struct ath5k_hw *ah = sc->ah;
2129 struct sk_buff *skb;
2131 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2133 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2134 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2135 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2139 * Check if the previous beacon has gone out. If
2140 * not don't don't try to post another, skip this
2141 * period and wait for the next. Missed beacons
2142 * indicate a problem and should not occur. If we
2143 * miss too many consecutive beacons reset the device.
2145 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2147 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2148 "missed %u consecutive beacons\n", sc->bmisscount);
2149 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2150 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2151 "stuck beacon time (%u missed)\n",
2153 tasklet_schedule(&sc->restq);
2157 if (unlikely(sc->bmisscount != 0)) {
2158 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2159 "resume beacon xmit after %u misses\n",
2165 * Stop any current dma and put the new frame on the queue.
2166 * This should never fail since we check above that no frames
2167 * are still pending on the queue.
2169 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2170 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2171 /* NB: hw still stops DMA, so proceed */
2174 /* refresh the beacon for AP mode */
2175 if (sc->opmode == NL80211_IFTYPE_AP)
2176 ath5k_beacon_update(sc->hw, sc->vif);
2178 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2179 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2180 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2181 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2183 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2185 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2186 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2194 * ath5k_beacon_update_timers - update beacon timers
2196 * @sc: struct ath5k_softc pointer we are operating on
2197 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2198 * beacon timer update based on the current HW TSF.
2200 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2201 * of a received beacon or the current local hardware TSF and write it to the
2202 * beacon timer registers.
2204 * This is called in a variety of situations, e.g. when a beacon is received,
2205 * when a TSF update has been detected, but also when an new IBSS is created or
2206 * when we otherwise know we have to update the timers, but we keep it in this
2207 * function to have it all together in one place.
2210 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2212 struct ath5k_hw *ah = sc->ah;
2213 u32 nexttbtt, intval, hw_tu, bc_tu;
2216 intval = sc->bintval & AR5K_BEACON_PERIOD;
2217 if (WARN_ON(!intval))
2220 /* beacon TSF converted to TU */
2221 bc_tu = TSF_TO_TU(bc_tsf);
2223 /* current TSF converted to TU */
2224 hw_tsf = ath5k_hw_get_tsf64(ah);
2225 hw_tu = TSF_TO_TU(hw_tsf);
2228 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2231 * no beacons received, called internally.
2232 * just need to refresh timers based on HW TSF.
2234 nexttbtt = roundup(hw_tu + FUDGE, intval);
2235 } else if (bc_tsf == 0) {
2237 * no beacon received, probably called by ath5k_reset_tsf().
2238 * reset TSF to start with 0.
2241 intval |= AR5K_BEACON_RESET_TSF;
2242 } else if (bc_tsf > hw_tsf) {
2244 * beacon received, SW merge happend but HW TSF not yet updated.
2245 * not possible to reconfigure timers yet, but next time we
2246 * receive a beacon with the same BSSID, the hardware will
2247 * automatically update the TSF and then we need to reconfigure
2250 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2251 "need to wait for HW TSF sync\n");
2255 * most important case for beacon synchronization between STA.
2257 * beacon received and HW TSF has been already updated by HW.
2258 * update next TBTT based on the TSF of the beacon, but make
2259 * sure it is ahead of our local TSF timer.
2261 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2265 sc->nexttbtt = nexttbtt;
2267 intval |= AR5K_BEACON_ENA;
2268 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2271 * debugging output last in order to preserve the time critical aspect
2275 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2276 "reconfigured timers based on HW TSF\n");
2277 else if (bc_tsf == 0)
2278 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2279 "reset HW TSF and timers\n");
2281 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2282 "updated timers based on beacon TSF\n");
2284 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2285 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2286 (unsigned long long) bc_tsf,
2287 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2288 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2289 intval & AR5K_BEACON_PERIOD,
2290 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2291 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2296 * ath5k_beacon_config - Configure the beacon queues and interrupts
2298 * @sc: struct ath5k_softc pointer we are operating on
2300 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2301 * interrupts to detect TSF updates only.
2304 ath5k_beacon_config(struct ath5k_softc *sc)
2306 struct ath5k_hw *ah = sc->ah;
2307 unsigned long flags;
2309 spin_lock_irqsave(&sc->block, flags);
2311 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2313 if (sc->enable_beacon) {
2315 * In IBSS mode we use a self-linked tx descriptor and let the
2316 * hardware send the beacons automatically. We have to load it
2318 * We use the SWBA interrupt only to keep track of the beacon
2319 * timers in order to detect automatic TSF updates.
2321 ath5k_beaconq_config(sc);
2323 sc->imask |= AR5K_INT_SWBA;
2325 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2326 if (ath5k_hw_hasveol(ah))
2327 ath5k_beacon_send(sc);
2329 ath5k_beacon_update_timers(sc, -1);
2331 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2334 ath5k_hw_set_imr(ah, sc->imask);
2336 spin_unlock_irqrestore(&sc->block, flags);
2339 static void ath5k_tasklet_beacon(unsigned long data)
2341 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2344 * Software beacon alert--time to send a beacon.
2346 * In IBSS mode we use this interrupt just to
2347 * keep track of the next TBTT (target beacon
2348 * transmission time) in order to detect wether
2349 * automatic TSF updates happened.
2351 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2352 /* XXX: only if VEOL suppported */
2353 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2354 sc->nexttbtt += sc->bintval;
2355 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2356 "SWBA nexttbtt: %x hw_tu: %x "
2360 (unsigned long long) tsf);
2362 spin_lock(&sc->block);
2363 ath5k_beacon_send(sc);
2364 spin_unlock(&sc->block);
2369 /********************\
2370 * Interrupt handling *
2371 \********************/
2374 ath5k_init(struct ath5k_softc *sc)
2376 struct ath5k_hw *ah = sc->ah;
2379 mutex_lock(&sc->lock);
2381 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2384 * Stop anything previously setup. This is safe
2385 * no matter this is the first time through or not.
2387 ath5k_stop_locked(sc);
2390 * The basic interface to setting the hardware in a good
2391 * state is ``reset''. On return the hardware is known to
2392 * be powered up and with interrupts disabled. This must
2393 * be followed by initialization of the appropriate bits
2394 * and then setup of the interrupt mask.
2396 sc->curchan = sc->hw->conf.channel;
2397 sc->curband = &sc->sbands[sc->curchan->band];
2398 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2399 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2400 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2401 ret = ath5k_reset(sc, NULL);
2405 ath5k_rfkill_hw_start(ah);
2408 * Reset the key cache since some parts do not reset the
2409 * contents on initial power up or resume from suspend.
2411 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2412 ath5k_hw_reset_key(ah, i);
2414 /* Set ack to be sent at low bit-rates */
2415 ath5k_hw_set_ack_bitrate_high(ah, false);
2417 /* Set PHY calibration inteval */
2418 ah->ah_cal_intval = ath5k_calinterval;
2423 mutex_unlock(&sc->lock);
2428 ath5k_stop_locked(struct ath5k_softc *sc)
2430 struct ath5k_hw *ah = sc->ah;
2432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2433 test_bit(ATH_STAT_INVALID, sc->status));
2436 * Shutdown the hardware and driver:
2437 * stop output from above
2438 * disable interrupts
2440 * turn off the radio
2441 * clear transmit machinery
2442 * clear receive machinery
2443 * drain and release tx queues
2444 * reclaim beacon resources
2445 * power down hardware
2447 * Note that some of this work is not possible if the
2448 * hardware is gone (invalid).
2450 ieee80211_stop_queues(sc->hw);
2452 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2454 ath5k_hw_set_imr(ah, 0);
2455 synchronize_irq(sc->pdev->irq);
2457 ath5k_txq_cleanup(sc);
2458 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2460 ath5k_hw_phy_disable(ah);
2468 * Stop the device, grabbing the top-level lock to protect
2469 * against concurrent entry through ath5k_init (which can happen
2470 * if another thread does a system call and the thread doing the
2471 * stop is preempted).
2474 ath5k_stop_hw(struct ath5k_softc *sc)
2478 mutex_lock(&sc->lock);
2479 ret = ath5k_stop_locked(sc);
2480 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2482 * Don't set the card in full sleep mode!
2484 * a) When the device is in this state it must be carefully
2485 * woken up or references to registers in the PCI clock
2486 * domain may freeze the bus (and system). This varies
2487 * by chip and is mostly an issue with newer parts
2488 * (madwifi sources mentioned srev >= 0x78) that go to
2489 * sleep more quickly.
2491 * b) On older chips full sleep results a weird behaviour
2492 * during wakeup. I tested various cards with srev < 0x78
2493 * and they don't wake up after module reload, a second
2494 * module reload is needed to bring the card up again.
2496 * Until we figure out what's going on don't enable
2497 * full chip reset on any chip (this is what Legacy HAL
2498 * and Sam's HAL do anyway). Instead Perform a full reset
2499 * on the device (same as initial state after attach) and
2500 * leave it idle (keep MAC/BB on warm reset) */
2501 ret = ath5k_hw_on_hold(sc->ah);
2503 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2504 "putting device to sleep\n");
2506 ath5k_txbuf_free(sc, sc->bbuf);
2509 mutex_unlock(&sc->lock);
2511 tasklet_kill(&sc->rxtq);
2512 tasklet_kill(&sc->txtq);
2513 tasklet_kill(&sc->restq);
2514 tasklet_kill(&sc->calib);
2515 tasklet_kill(&sc->beacontq);
2517 ath5k_rfkill_hw_stop(sc->ah);
2523 ath5k_intr(int irq, void *dev_id)
2525 struct ath5k_softc *sc = dev_id;
2526 struct ath5k_hw *ah = sc->ah;
2527 enum ath5k_int status;
2528 unsigned int counter = 1000;
2530 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2531 !ath5k_hw_is_intr_pending(ah)))
2535 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2536 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2538 if (unlikely(status & AR5K_INT_FATAL)) {
2540 * Fatal errors are unrecoverable.
2541 * Typically these are caused by DMA errors.
2543 tasklet_schedule(&sc->restq);
2544 } else if (unlikely(status & AR5K_INT_RXORN)) {
2545 tasklet_schedule(&sc->restq);
2547 if (status & AR5K_INT_SWBA) {
2548 tasklet_hi_schedule(&sc->beacontq);
2550 if (status & AR5K_INT_RXEOL) {
2552 * NB: the hardware should re-read the link when
2553 * RXE bit is written, but it doesn't work at
2554 * least on older hardware revs.
2558 if (status & AR5K_INT_TXURN) {
2559 /* bump tx trigger level */
2560 ath5k_hw_update_tx_triglevel(ah, true);
2562 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2563 tasklet_schedule(&sc->rxtq);
2564 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2565 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2566 tasklet_schedule(&sc->txtq);
2567 if (status & AR5K_INT_BMISS) {
2570 if (status & AR5K_INT_SWI) {
2571 tasklet_schedule(&sc->calib);
2573 if (status & AR5K_INT_MIB) {
2575 * These stats are also used for ANI i think
2576 * so how about updating them more often ?
2578 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2580 if (status & AR5K_INT_GPIO)
2581 tasklet_schedule(&sc->rf_kill.toggleq);
2584 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2586 if (unlikely(!counter))
2587 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2589 ath5k_hw_calibration_poll(ah);
2595 ath5k_tasklet_reset(unsigned long data)
2597 struct ath5k_softc *sc = (void *)data;
2599 ath5k_reset_wake(sc);
2603 * Periodically recalibrate the PHY to account
2604 * for temperature/environment changes.
2607 ath5k_tasklet_calibrate(unsigned long data)
2609 struct ath5k_softc *sc = (void *)data;
2610 struct ath5k_hw *ah = sc->ah;
2612 /* Only full calibration for now */
2613 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2616 /* Stop queues so that calibration
2617 * doesn't interfere with tx */
2618 ieee80211_stop_queues(sc->hw);
2620 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2621 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2622 sc->curchan->hw_value);
2624 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2626 * Rfgain is out of bounds, reset the chip
2627 * to load new gain values.
2629 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2630 ath5k_reset_wake(sc);
2632 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2633 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2634 ieee80211_frequency_to_channel(
2635 sc->curchan->center_freq));
2637 ah->ah_swi_mask = 0;
2640 ieee80211_wake_queues(sc->hw);
2645 /********************\
2646 * Mac80211 functions *
2647 \********************/
2650 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2652 struct ath5k_softc *sc = hw->priv;
2654 return ath5k_tx_queue(hw, skb, sc->txq);
2657 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2658 struct ath5k_txq *txq)
2660 struct ath5k_softc *sc = hw->priv;
2661 struct ath5k_buf *bf;
2662 unsigned long flags;
2666 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2668 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2669 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2672 * the hardware expects the header padded to 4 byte boundaries
2673 * if this is not the case we add the padding after the header
2675 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2676 padsize = ath5k_pad_size(hdrlen);
2679 if (skb_headroom(skb) < padsize) {
2680 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2681 " headroom to pad %d\n", hdrlen, padsize);
2684 skb_push(skb, padsize);
2685 memmove(skb->data, skb->data+padsize, hdrlen);
2688 spin_lock_irqsave(&sc->txbuflock, flags);
2689 if (list_empty(&sc->txbuf)) {
2690 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2691 spin_unlock_irqrestore(&sc->txbuflock, flags);
2692 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2695 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2696 list_del(&bf->list);
2698 if (list_empty(&sc->txbuf))
2699 ieee80211_stop_queues(hw);
2700 spin_unlock_irqrestore(&sc->txbuflock, flags);
2704 if (ath5k_txbuf_setup(sc, bf, txq)) {
2706 spin_lock_irqsave(&sc->txbuflock, flags);
2707 list_add_tail(&bf->list, &sc->txbuf);
2709 spin_unlock_irqrestore(&sc->txbuflock, flags);
2712 return NETDEV_TX_OK;
2715 dev_kfree_skb_any(skb);
2716 return NETDEV_TX_OK;
2720 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2721 * and change to the given channel.
2724 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2726 struct ath5k_hw *ah = sc->ah;
2729 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2732 ath5k_hw_set_imr(ah, 0);
2733 ath5k_txq_cleanup(sc);
2737 sc->curband = &sc->sbands[chan->band];
2739 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2741 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2745 ret = ath5k_rx_start(sc);
2747 ATH5K_ERR(sc, "can't start recv logic\n");
2752 * Change channels and update the h/w rate map if we're switching;
2753 * e.g. 11a to 11b/g.
2755 * We may be doing a reset in response to an ioctl that changes the
2756 * channel so update any state that might change as a result.
2760 /* ath5k_chan_change(sc, c); */
2762 ath5k_beacon_config(sc);
2763 /* intrs are enabled by ath5k_beacon_config */
2771 ath5k_reset_wake(struct ath5k_softc *sc)
2775 ret = ath5k_reset(sc, sc->curchan);
2777 ieee80211_wake_queues(sc->hw);
2782 static int ath5k_start(struct ieee80211_hw *hw)
2784 return ath5k_init(hw->priv);
2787 static void ath5k_stop(struct ieee80211_hw *hw)
2789 ath5k_stop_hw(hw->priv);
2792 static int ath5k_add_interface(struct ieee80211_hw *hw,
2793 struct ieee80211_if_init_conf *conf)
2795 struct ath5k_softc *sc = hw->priv;
2798 mutex_lock(&sc->lock);
2804 sc->vif = conf->vif;
2806 switch (conf->type) {
2807 case NL80211_IFTYPE_AP:
2808 case NL80211_IFTYPE_STATION:
2809 case NL80211_IFTYPE_ADHOC:
2810 case NL80211_IFTYPE_MESH_POINT:
2811 case NL80211_IFTYPE_MONITOR:
2812 sc->opmode = conf->type;
2819 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2820 ath5k_mode_setup(sc);
2824 mutex_unlock(&sc->lock);
2829 ath5k_remove_interface(struct ieee80211_hw *hw,
2830 struct ieee80211_if_init_conf *conf)
2832 struct ath5k_softc *sc = hw->priv;
2833 u8 mac[ETH_ALEN] = {};
2835 mutex_lock(&sc->lock);
2836 if (sc->vif != conf->vif)
2839 ath5k_hw_set_lladdr(sc->ah, mac);
2842 mutex_unlock(&sc->lock);
2846 * TODO: Phy disable/diversity etc
2849 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2851 struct ath5k_softc *sc = hw->priv;
2852 struct ath5k_hw *ah = sc->ah;
2853 struct ieee80211_conf *conf = &hw->conf;
2856 mutex_lock(&sc->lock);
2858 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2859 ret = ath5k_chan_set(sc, conf->channel);
2864 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2865 (sc->power_level != conf->power_level)) {
2866 sc->power_level = conf->power_level;
2869 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2873 * 1) Move this on config_interface and handle each case
2874 * separately eg. when we have only one STA vif, use
2875 * AR5K_ANTMODE_SINGLE_AP
2877 * 2) Allow the user to change antenna mode eg. when only
2878 * one antenna is present
2880 * 3) Allow the user to set default/tx antenna when possible
2882 * 4) Default mode should handle 90% of the cases, together
2883 * with fixed a/b and single AP modes we should be able to
2884 * handle 99%. Sectored modes are extreme cases and i still
2885 * haven't found a usage for them. If we decide to support them,
2886 * then we must allow the user to set how many tx antennas we
2889 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2892 mutex_unlock(&sc->lock);
2896 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2897 int mc_count, struct dev_addr_list *mclist)
2906 for (i = 0; i < mc_count; i++) {
2909 /* calculate XOR of eight 6-bit values */
2910 val = get_unaligned_le32(mclist->dmi_addr + 0);
2911 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2912 val = get_unaligned_le32(mclist->dmi_addr + 3);
2913 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2915 mfilt[pos / 32] |= (1 << (pos % 32));
2916 /* XXX: we might be able to just do this instead,
2917 * but not sure, needs testing, if we do use this we'd
2918 * neet to inform below to not reset the mcast */
2919 /* ath5k_hw_set_mcast_filterindex(ah,
2920 * mclist->dmi_addr[5]); */
2921 mclist = mclist->next;
2924 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2927 #define SUPPORTED_FIF_FLAGS \
2928 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2929 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2930 FIF_BCN_PRBRESP_PROMISC
2932 * o always accept unicast, broadcast, and multicast traffic
2933 * o multicast traffic for all BSSIDs will be enabled if mac80211
2935 * o maintain current state of phy ofdm or phy cck error reception.
2936 * If the hardware detects any of these type of errors then
2937 * ath5k_hw_get_rx_filter() will pass to us the respective
2938 * hardware filters to be able to receive these type of frames.
2939 * o probe request frames are accepted only when operating in
2940 * hostap, adhoc, or monitor modes
2941 * o enable promiscuous mode according to the interface state
2943 * - when operating in adhoc mode so the 802.11 layer creates
2944 * node table entries for peers,
2945 * - when operating in station mode for collecting rssi data when
2946 * the station is otherwise quiet, or
2949 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2950 unsigned int changed_flags,
2951 unsigned int *new_flags,
2954 struct ath5k_softc *sc = hw->priv;
2955 struct ath5k_hw *ah = sc->ah;
2956 u32 mfilt[2], rfilt;
2958 mutex_lock(&sc->lock);
2960 mfilt[0] = multicast;
2961 mfilt[1] = multicast >> 32;
2963 /* Only deal with supported flags */
2964 changed_flags &= SUPPORTED_FIF_FLAGS;
2965 *new_flags &= SUPPORTED_FIF_FLAGS;
2967 /* If HW detects any phy or radar errors, leave those filters on.
2968 * Also, always enable Unicast, Broadcasts and Multicast
2969 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2970 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2971 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2972 AR5K_RX_FILTER_MCAST);
2974 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2975 if (*new_flags & FIF_PROMISC_IN_BSS) {
2976 rfilt |= AR5K_RX_FILTER_PROM;
2977 __set_bit(ATH_STAT_PROMISC, sc->status);
2979 __clear_bit(ATH_STAT_PROMISC, sc->status);
2983 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2984 if (*new_flags & FIF_ALLMULTI) {
2989 /* This is the best we can do */
2990 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2991 rfilt |= AR5K_RX_FILTER_PHYERR;
2993 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2994 * and probes for any BSSID, this needs testing */
2995 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2996 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2998 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2999 * set we should only pass on control frames for this
3000 * station. This needs testing. I believe right now this
3001 * enables *all* control frames, which is OK.. but
3002 * but we should see if we can improve on granularity */
3003 if (*new_flags & FIF_CONTROL)
3004 rfilt |= AR5K_RX_FILTER_CONTROL;
3006 /* Additional settings per mode -- this is per ath5k */
3008 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3010 switch (sc->opmode) {
3011 case NL80211_IFTYPE_MESH_POINT:
3012 case NL80211_IFTYPE_MONITOR:
3013 rfilt |= AR5K_RX_FILTER_CONTROL |
3014 AR5K_RX_FILTER_BEACON |
3015 AR5K_RX_FILTER_PROBEREQ |
3016 AR5K_RX_FILTER_PROM;
3018 case NL80211_IFTYPE_AP:
3019 case NL80211_IFTYPE_ADHOC:
3020 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3021 AR5K_RX_FILTER_BEACON;
3023 case NL80211_IFTYPE_STATION:
3025 rfilt |= AR5K_RX_FILTER_BEACON;
3031 ath5k_hw_set_rx_filter(ah, rfilt);
3033 /* Set multicast bits */
3034 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3035 /* Set the cached hw filter flags, this will alter actually
3037 sc->filter_flags = rfilt;
3039 mutex_unlock(&sc->lock);
3043 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3044 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3045 struct ieee80211_key_conf *key)
3047 struct ath5k_softc *sc = hw->priv;
3050 if (modparam_nohwcrypt)
3053 if (sc->opmode == NL80211_IFTYPE_AP)
3061 if (sc->ah->ah_aes_support)
3070 mutex_lock(&sc->lock);
3074 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3075 sta ? sta->addr : NULL);
3077 ATH5K_ERR(sc, "can't set the key\n");
3080 __set_bit(key->keyidx, sc->keymap);
3081 key->hw_key_idx = key->keyidx;
3082 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3083 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3086 ath5k_hw_reset_key(sc->ah, key->keyidx);
3087 __clear_bit(key->keyidx, sc->keymap);
3096 mutex_unlock(&sc->lock);
3101 ath5k_get_stats(struct ieee80211_hw *hw,
3102 struct ieee80211_low_level_stats *stats)
3104 struct ath5k_softc *sc = hw->priv;
3105 struct ath5k_hw *ah = sc->ah;
3108 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3110 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3116 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3117 struct ieee80211_tx_queue_stats *stats)
3119 struct ath5k_softc *sc = hw->priv;
3121 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3127 ath5k_get_tsf(struct ieee80211_hw *hw)
3129 struct ath5k_softc *sc = hw->priv;
3131 return ath5k_hw_get_tsf64(sc->ah);
3135 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3137 struct ath5k_softc *sc = hw->priv;
3139 ath5k_hw_set_tsf64(sc->ah, tsf);
3143 ath5k_reset_tsf(struct ieee80211_hw *hw)
3145 struct ath5k_softc *sc = hw->priv;
3148 * in IBSS mode we need to update the beacon timers too.
3149 * this will also reset the TSF if we call it with 0
3151 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3152 ath5k_beacon_update_timers(sc, 0);
3154 ath5k_hw_reset_tsf(sc->ah);
3158 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3159 * this is called only once at config_bss time, for AP we do it every
3160 * SWBA interrupt so that the TIM will reflect buffered frames.
3162 * Called with the beacon lock.
3165 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3168 struct ath5k_softc *sc = hw->priv;
3169 struct sk_buff *skb;
3171 if (WARN_ON(!vif)) {
3176 skb = ieee80211_beacon_get(hw, vif);
3183 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3185 ath5k_txbuf_free(sc, sc->bbuf);
3186 sc->bbuf->skb = skb;
3187 ret = ath5k_beacon_setup(sc, sc->bbuf);
3189 sc->bbuf->skb = NULL;
3195 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3197 struct ath5k_softc *sc = hw->priv;
3198 struct ath5k_hw *ah = sc->ah;
3200 rfilt = ath5k_hw_get_rx_filter(ah);
3202 rfilt |= AR5K_RX_FILTER_BEACON;
3204 rfilt &= ~AR5K_RX_FILTER_BEACON;
3205 ath5k_hw_set_rx_filter(ah, rfilt);
3206 sc->filter_flags = rfilt;
3209 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3210 struct ieee80211_vif *vif,
3211 struct ieee80211_bss_conf *bss_conf,
3214 struct ath5k_softc *sc = hw->priv;
3215 struct ath5k_hw *ah = sc->ah;
3216 struct ath_common *common = ath5k_hw_common(ah);
3217 unsigned long flags;
3219 mutex_lock(&sc->lock);
3220 if (WARN_ON(sc->vif != vif))
3223 if (changes & BSS_CHANGED_BSSID) {
3224 /* Cache for later use during resets */
3225 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3226 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3227 * a clean way of letting us retrieve this yet. */
3228 ath5k_hw_set_associd(ah, common->curbssid, 0);
3232 if (changes & BSS_CHANGED_BEACON_INT)
3233 sc->bintval = bss_conf->beacon_int;
3235 if (changes & BSS_CHANGED_ASSOC) {
3236 sc->assoc = bss_conf->assoc;
3237 if (sc->opmode == NL80211_IFTYPE_STATION)
3238 set_beacon_filter(hw, sc->assoc);
3239 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3240 AR5K_LED_ASSOC : AR5K_LED_INIT);
3243 if (changes & BSS_CHANGED_BEACON) {
3244 spin_lock_irqsave(&sc->block, flags);
3245 ath5k_beacon_update(hw, vif);
3246 spin_unlock_irqrestore(&sc->block, flags);
3249 if (changes & BSS_CHANGED_BEACON_ENABLED)
3250 sc->enable_beacon = bss_conf->enable_beacon;
3252 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3253 BSS_CHANGED_BEACON_INT))
3254 ath5k_beacon_config(sc);
3257 mutex_unlock(&sc->lock);
3260 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3262 struct ath5k_softc *sc = hw->priv;
3264 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3267 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3269 struct ath5k_softc *sc = hw->priv;
3270 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3271 AR5K_LED_ASSOC : AR5K_LED_INIT);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob