2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions.
4 * Author: Ivan Passos <ivan@cyclades.com>
6 * Copyright: (c) 1999-2002 Cyclades Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 * Revision 3.12 2002/03/07 14:17:09 henrique
17 * Revision 3.11 2002/01/28 21:09:39 daniela
18 * Included ';' after pc300hw.bus.
20 * Revision 3.10 2002/01/17 17:58:52 ivan
21 * Support for PC300-TE/M (PMC).
23 * Revision 3.9 2001/09/28 13:30:53 daniela
24 * Renamed dma_start routine to rx_dma_start.
26 * Revision 3.8 2001/09/24 13:03:45 daniela
27 * Fixed BOF interrupt treatment. Created dma_start routine.
29 * Revision 3.7 2001/08/10 17:19:58 daniela
30 * Fixed IOCTLs defines.
32 * Revision 3.6 2001/07/18 19:24:42 daniela
33 * Included kernel version.
35 * Revision 3.5 2001/07/05 18:38:08 daniela
36 * DMA transmission bug fix.
38 * Revision 3.4 2001/06/26 17:10:40 daniela
39 * New configuration parameters (line code, CRC calculation and clock).
41 * Revision 3.3 2001/06/22 13:13:02 regina
42 * MLPPP implementation
44 * Revision 3.2 2001/06/18 17:56:09 daniela
45 * Increased DEF_MTU and TX_QUEUE_LEN.
47 * Revision 3.1 2001/06/15 12:41:10 regina
48 * upping major version number
50 * Revision 1.1.1.1 2001/06/13 20:25:06 daniela
51 * PC300 initial CVS version (3.4.0-pre1)
53 * Revision 2.3 2001/03/05 daniela
54 * Created struct pc300conf, to provide the hardware information to pc300util.
55 * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
57 * Revision 2.2 2000/12/22 daniela
58 * Structures and defines to support pc300util: statistics, status,
59 * loopback tests, trace.
61 * Revision 2.1 2000/09/28 ivan
62 * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
63 * allow release of I/O region at module unload.
64 * Changed location of include files.
66 * Revision 2.0 2000/03/27 ivan
67 * Added support for the PC300/TE cards.
69 * Revision 1.1 2000/01/31 ivan
70 * Replaced 'pc300[drv|sca].h' former PC300 driver include files.
72 * Revision 1.0 1999/12/16 ivan
73 * First official release.
74 * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
75 * number of ports per card.
76 * Inclusion of 'if_ptr' field on structure 'pc300dev'.
78 * Revision 0.6 1999/11/17 ivan
79 * Changed X.25-specific function names to comply with adopted convention.
81 * Revision 0.5 1999/11/16 Daniela Squassoni
84 * Revision 0.4 1999/11/15 ivan
85 * Inclusion of 'clock' field on structure 'pc300hw'.
87 * Revision 0.3 1999/11/10 ivan
88 * IOCTL name changing.
89 * Inclusion of driver function prototypes.
91 * Revision 0.2 1999/11/03 ivan
92 * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
94 * Revision 0.1 1999/01/15 ivan
102 #include <linux/hdlc.h>
104 #include "pc300-falc-lh.h"
108 typedef __u64 ucdouble; /* 64 bits, unsigned */
109 typedef __u32 uclong; /* 32 bits, unsigned */
110 typedef __u16 ucshort; /* 16 bits, unsigned */
111 typedef __u8 ucchar; /* 8 bits, unsigned */
112 #endif /* CY_TYPES */
114 #define PC300_PROTO_MLPPP 1
116 #define PC300_MAXCHAN 2 /* Number of channels per card */
118 #define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
119 #define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
121 #define PC300_OSC_CLOCK 24576000
122 #define PC300_PCI_CLOCK 33000000
124 #define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */
125 #define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */
126 #define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */
128 #define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */
129 #define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */
131 /* DMA Buffer Offsets */
132 #define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
133 PC300_MAXCHAN * sizeof(pcsca_bd_t))
134 #define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
136 /* DMA Descriptor Offsets */
137 #define DMA_TX_BD_BASE 0x0000
138 #define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
139 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
141 /* DMA Descriptor Macros */
142 #define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
143 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
144 #define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
145 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
147 /* Macro to access the FALC registers (TE only) */
148 #define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
150 /***************************************
151 * Memory access functions/macros *
152 * (required to support Alpha systems) *
153 ***************************************/
154 #define cpc_writeb(port,val) {writeb((ucchar)(val),(port)); mb();}
155 #define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
156 #define cpc_writel(port,val) {writel((uclong)(val),(port)); mb();}
158 #define cpc_readb(port) readb(port)
159 #define cpc_readw(port) readw(port)
160 #define cpc_readl(port) readl(port)
162 /****** Data Structures *****************************************************/
165 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
166 * registers. This structure can be used to access the 9050 registers
169 struct RUNTIME_9050 {
170 uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
171 uclong loc_rom_range; /* 10h : Local ROM Range */
172 uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
173 uclong loc_rom_base; /* 24h : Local ROM Base */
174 uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
175 uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */
176 uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
177 uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
178 uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
181 #define PLX_9050_LINT1_ENABLE 0x01
182 #define PLX_9050_LINT1_POL 0x02
183 #define PLX_9050_LINT1_STATUS 0x04
184 #define PLX_9050_LINT2_ENABLE 0x08
185 #define PLX_9050_LINT2_POL 0x10
186 #define PLX_9050_LINT2_STATUS 0x20
187 #define PLX_9050_INTR_ENABLE 0x40
188 #define PLX_9050_SW_INTR 0x80
190 /* Masks to access the init_ctrl PLX register */
191 #define PC300_CLKSEL_MASK (0x00000004UL)
192 #define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
193 #define PC300_CTYPE_MASK (0x00000800UL)
195 /* CPLD Registers (base addr = falcbase, TE only) */
197 #define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */
198 #define CPLD_REG2 0x144 /* Clock enable , LED control */
199 /* CPLD v. 2 or higher */
200 #define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */
201 #define CPLD_V2_REG2 0x104 /* Clock enable , LED control */
202 #define CPLD_ID_REG 0x108 /* CPLD version */
204 /* CPLD Register bit description: for the FALC bits, they should always be
205 set based on the channel (use (bit<<(2*ch)) to access the correct bit for
207 #define CPLD_REG1_FALC_RESET 0x01
208 #define CPLD_REG1_SCA_RESET 0x02
209 #define CPLD_REG1_GLOBAL_CLK 0x08
210 #define CPLD_REG1_FALC_DCD 0x10
211 #define CPLD_REG1_FALC_CTS 0x20
213 #define CPLD_REG2_FALC_TX_CLK 0x01
214 #define CPLD_REG2_FALC_RX_CLK 0x02
215 #define CPLD_REG2_FALC_LED1 0x10
216 #define CPLD_REG2_FALC_LED2 0x20
218 /* Structure with FALC-related fields (TE only) */
219 #define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
221 typedef struct falc {
222 ucchar sync; /* If true FALC is synchronized */
223 ucchar active; /* if TRUE then already active */
224 ucchar loop_active; /* if TRUE a line loopback UP was received */
225 ucchar loop_gen; /* if TRUE a line loopback UP was issued */
228 ucchar offset; /* 1 for T1, 0 for E1 */
229 ucchar full_bandwidth;
232 ucchar multiframe_mode;
235 ucshort pden; /* Pulse Density violation count */
236 ucshort los; /* Loss of Signal count */
237 ucshort losr; /* Loss of Signal recovery count */
238 ucshort lfa; /* Loss of frame alignment count */
239 ucshort farec; /* Frame Alignment Recovery count */
240 ucshort lmfa; /* Loss of multiframe alignment count */
241 ucshort ais; /* Remote Alarm indication Signal count */
242 ucshort sec; /* One-second timer */
243 ucshort es; /* Errored second */
244 ucshort rai; /* remote alarm received */
260 typedef struct falc_status {
261 ucchar sync; /* If true FALC is synchronized */
270 typedef struct rsv_x21_status {
278 typedef struct pc300stats {
282 struct net_device_stats gen_stats;
286 typedef struct pc300status {
288 rsv_x21_status_t gen_status;
289 falc_status_t te_status;
292 typedef struct pc300loopback {
297 typedef struct pc300patterntst {
298 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
302 typedef struct pc300dev {
303 struct pc300ch *chan;
305 uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
308 struct net_device *dev;
309 #ifdef CONFIG_PC300_MLPPP
310 void *cpc_tty; /* information to PC300 TTY driver */
314 typedef struct pc300hw {
315 int type; /* RSV, X21, etc. */
316 int bus; /* Bus (PCI, PMC, etc.) */
317 int nchan; /* number of channels */
318 int irq; /* interrupt request level */
319 uclong clock; /* Board clock */
320 ucchar cpld_id; /* CPLD ID (TE only) */
321 ucshort cpld_reg1; /* CPLD reg 1 (TE only) */
322 ucshort cpld_reg2; /* CPLD reg 2 (TE only) */
323 ucshort gpioc_reg; /* PLX GPIOC reg */
324 ucshort intctl_reg; /* PLX Int Ctrl/Status reg */
325 uclong iophys; /* PLX registers I/O base */
326 uclong iosize; /* PLX registers I/O size */
327 uclong plxphys; /* PLX registers MMIO base (physical) */
328 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
329 uclong plxsize; /* PLX registers MMIO size */
330 uclong scaphys; /* SCA registers MMIO base (physical) */
331 void __iomem * scabase; /* SCA registers MMIO base (virtual) */
332 uclong scasize; /* SCA registers MMIO size */
333 uclong ramphys; /* On-board RAM MMIO base (physical) */
334 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
335 uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
336 uclong ramsize; /* On-board RAM MMIO size */
337 uclong falcphys; /* FALC registers MMIO base (physical) */
338 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
339 uclong falcsize; /* FALC registers MMIO size */
342 typedef struct pc300chconf {
343 sync_serial_settings phys_settings; /* Clock type/rate (in bps),
345 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
346 uclong media; /* HW media (RS232, V.35, etc.) */
347 uclong proto; /* Protocol (PPP, X.25, etc.) */
348 ucchar monitor; /* Monitor mode (0 = off, !0 = on) */
350 /* TE-specific parameters */
351 ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */
352 ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */
353 ucchar lbo; /* Line Build Out */
354 ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */
355 uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
358 typedef struct pc300ch {
363 ucchar tx_first_bd; /* First TX DMA block descr. w/ data */
364 ucchar tx_next_bd; /* Next free TX DMA block descriptor */
365 ucchar rx_first_bd; /* First free RX DMA block descriptor */
366 ucchar rx_last_bd; /* Last free RX DMA block descriptor */
367 ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */
368 falc_t falc; /* FALC structure (TE only) */
371 typedef struct pc300 {
372 pc300hw_t hw; /* hardware config. */
373 pc300ch_t chan[PC300_MAXCHAN];
374 spinlock_t card_lock;
377 typedef struct pc300conf {
382 /* DEV ioctl() commands */
383 #define N_SPPP_IOCTLS 2
385 enum pc300_ioctl_cmds {
386 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
390 SIOCGPC300FALCSTATUS,
392 SIOCGPC300UTILSTATUS,
395 SIOCSPC300PATTERNTEST,
398 /* Loopback types - PC300/TE boards */
399 enum pc300_loopback_cmds {
407 /* Control Constant Definitions */
408 #define PC300_RSV 0x01
409 #define PC300_X21 0x02
410 #define PC300_TE 0x03
412 #define PC300_PCI 0x00
413 #define PC300_PMC 0x01
415 #define PC300_LC_AMI 0x01
416 #define PC300_LC_B8ZS 0x02
417 #define PC300_LC_NRZ 0x03
418 #define PC300_LC_HDB3 0x04
421 #define PC300_FR_ESF 0x01
422 #define PC300_FR_D4 0x02
423 #define PC300_FR_ESF_JAPAN 0x03
426 #define PC300_FR_MF_CRC4 0x04
427 #define PC300_FR_MF_NON_CRC4 0x05
428 #define PC300_FR_UNFRAMED 0x06
430 #define PC300_LBO_0_DB 0x00
431 #define PC300_LBO_7_5_DB 0x01
432 #define PC300_LBO_15_DB 0x02
433 #define PC300_LBO_22_5_DB 0x03
435 #define PC300_RX_SENS_SH 0x01
436 #define PC300_RX_SENS_LH 0x02
438 #define PC300_TX_TIMEOUT (2*HZ)
439 #define PC300_TX_QUEUE_LEN 100
440 #define PC300_DEF_MTU 1600
442 /* Function Prototypes */
443 void tx_dma_start(pc300_t *, int);
444 int cpc_open(struct net_device *dev);
445 int cpc_set_media(hdlc_device *, int);
447 #endif /* _PC300_H */