2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux
4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * Source of information: HD64572 SCA-II User's Manual
12 * We use the following SCA memory map:
14 * Packet buffer descriptor rings - starting from winbase or win0base:
15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
20 * Packet data buffers - starting from winbase + buff_offset:
21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers
22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers
23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used)
24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used)
27 #include <linux/bitops.h>
28 #include <linux/errno.h>
29 #include <linux/fcntl.h>
30 #include <linux/hdlc.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/jiffies.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/types.h>
44 #include <asm/system.h>
45 #include <asm/uaccess.h>
48 #define NAPI_WEIGHT 16
50 #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET)
51 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
52 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
54 #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01)
55 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
56 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
58 static int sca_poll(struct napi_struct *napi, int budget);
60 static inline struct net_device *port_to_dev(port_t *port)
65 static inline int sca_intr_status(card_t *card)
68 u32 isr0 = sca_inl(ISR0, card);
70 if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0);
71 if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0);
72 if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1);
73 if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1);
74 if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0);
75 if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1);
77 if (!(result & SCA_INTR_DMAC_TX(0)))
78 if (sca_in(DSR_TX(0), card) & DSR_EOM)
79 result |= SCA_INTR_DMAC_TX(0);
80 if (!(result & SCA_INTR_DMAC_TX(1)))
81 if (sca_in(DSR_TX(1), card) & DSR_EOM)
82 result |= SCA_INTR_DMAC_TX(1);
87 static inline port_t* dev_to_port(struct net_device *dev)
89 return dev_to_hdlc(dev)->priv;
92 static inline void enable_intr(port_t *port)
94 /* DMA & MSCI IRQ enable */
95 /* IR0_TXINT | IR0_RXINTA | IR0_DMIB* | IR0_DMIA* */
96 sca_outl(sca_inl(IER0, port->card) |
97 (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, port->card);
100 static inline void disable_intr(port_t *port)
102 sca_outl(sca_inl(IER0, port->card) &
103 (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, port->card);
106 static inline u16 next_desc(port_t *port, u16 desc, int transmit)
108 return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
109 : port_to_card(port)->rx_ring_buffers);
113 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
115 u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
116 u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
118 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
119 return log_node(port) * (rx_buffs + tx_buffs) +
120 transmit * rx_buffs + desc;
124 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
126 /* Descriptor offset always fits in 16 bytes */
127 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
131 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
134 return (pkt_desc __iomem *)(winbase(port_to_card(port))
135 + desc_offset(port, desc, transmit));
139 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
141 return port_to_card(port)->buff_offset +
142 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
146 static inline void sca_set_carrier(port_t *port)
148 if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
150 printk(KERN_DEBUG "%s: sca_set_carrier on\n",
151 port_to_dev(port)->name);
153 netif_carrier_on(port_to_dev(port));
156 printk(KERN_DEBUG "%s: sca_set_carrier off\n",
157 port_to_dev(port)->name);
159 netif_carrier_off(port_to_dev(port));
164 static void sca_init_port(port_t *port)
166 card_t *card = port_to_card(port);
173 for (transmit = 0; transmit < 2; transmit++) {
174 u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
175 u16 buffs = transmit ? card->tx_ring_buffers
176 : card->rx_ring_buffers;
178 for (i = 0; i < buffs; i++) {
179 pkt_desc __iomem *desc = desc_address(port, i, transmit);
180 u16 chain_off = desc_offset(port, i + 1, transmit);
181 u32 buff_off = buffer_offset(port, i, transmit);
183 writel(chain_off, &desc->cp);
184 writel(buff_off, &desc->bp);
185 writew(0, &desc->len);
186 writeb(0, &desc->stat);
189 /* DMA disable - to halt state */
190 sca_out(0, transmit ? DSR_TX(phy_node(port)) :
191 DSR_RX(phy_node(port)), card);
192 /* software ABORT - to initial state */
193 sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
194 DCR_RX(phy_node(port)), card);
196 /* current desc addr */
197 sca_outl(desc_offset(port, 0, transmit), dmac + CDAL, card);
199 sca_outl(desc_offset(port, buffs - 1, transmit),
202 sca_outl(desc_offset(port, 0, transmit), dmac + EDAL,
205 /* clear frame end interrupt counter */
206 sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
207 DCR_RX(phy_node(port)), card);
209 if (!transmit) { /* Receive */
210 /* set buffer length */
211 sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
212 /* Chain mode, Multi-frame */
213 sca_out(0x14, DMR_RX(phy_node(port)), card);
214 sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
217 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
218 } else { /* Transmit */
219 /* Chain mode, Multi-frame */
220 sca_out(0x14, DMR_TX(phy_node(port)), card);
221 /* enable underflow interrupts */
222 sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
225 sca_set_carrier(port);
226 netif_napi_add(port_to_dev(port), &port->napi, sca_poll, NAPI_WEIGHT);
230 /* MSCI interrupt service */
231 static inline void sca_msci_intr(port_t *port)
233 u16 msci = get_msci(port);
234 card_t* card = port_to_card(port);
236 if (sca_in(msci + ST1, card) & ST1_CDCD) {
237 /* Reset MSCI CDCD status bit */
238 sca_out(ST1_CDCD, msci + ST1, card);
239 sca_set_carrier(port);
244 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
247 struct net_device *dev = port_to_dev(port);
252 len = readw(&desc->len);
253 skb = dev_alloc_skb(len);
255 dev->stats.rx_dropped++;
259 buff = buffer_offset(port, rxin, 0);
260 memcpy_fromio(skb->data, winbase(card) + buff, len);
264 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
267 dev->stats.rx_packets++;
268 dev->stats.rx_bytes += skb->len;
269 skb->protocol = hdlc_type_trans(skb, dev);
270 netif_receive_skb(skb);
274 /* Receive DMA service */
275 static inline int sca_rx_done(port_t *port, int budget)
277 struct net_device *dev = port_to_dev(port);
278 u16 dmac = get_dmac_rx(port);
279 card_t *card = port_to_card(port);
280 u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
283 /* Reset DSR status bits */
284 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
285 DSR_RX(phy_node(port)), card);
288 /* Dropped one or more frames */
289 dev->stats.rx_over_errors++;
291 while (received < budget) {
292 u32 desc_off = desc_offset(port, port->rxin, 0);
293 pkt_desc __iomem *desc;
294 u32 cda = sca_inl(dmac + CDAL, card);
296 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc)))
297 break; /* No frame received */
299 desc = desc_address(port, port->rxin, 0);
300 stat = readb(&desc->stat);
301 if (!(stat & ST_RX_EOM))
302 port->rxpart = 1; /* partial frame received */
303 else if ((stat & ST_ERROR_MASK) || port->rxpart) {
304 dev->stats.rx_errors++;
305 if (stat & ST_RX_OVERRUN)
306 dev->stats.rx_fifo_errors++;
307 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
308 ST_RX_RESBIT)) || port->rxpart)
309 dev->stats.rx_frame_errors++;
310 else if (stat & ST_RX_CRC)
311 dev->stats.rx_crc_errors++;
312 if (stat & ST_RX_EOM)
313 port->rxpart = 0; /* received last fragment */
315 sca_rx(card, port, desc, port->rxin);
319 /* Set new error descriptor address */
320 sca_outl(desc_off, dmac + EDAL, card);
321 port->rxin = next_desc(port, port->rxin, 0);
324 /* make sure RX DMA is enabled */
325 sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
330 /* Transmit DMA service */
331 static inline void sca_tx_done(port_t *port)
333 struct net_device *dev = port_to_dev(port);
334 card_t* card = port_to_card(port);
337 spin_lock(&port->lock);
339 stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
341 /* Reset DSR status bits */
342 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
343 DSR_TX(phy_node(port)), card);
346 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1);
347 u8 stat = readb(&desc->stat);
349 if (!(stat & ST_TX_OWNRSHP))
350 break; /* not yet transmitted */
351 if (stat & ST_TX_UNDRRUN) {
352 dev->stats.tx_errors++;
353 dev->stats.tx_fifo_errors++;
355 dev->stats.tx_packets++;
356 dev->stats.tx_bytes += readw(&desc->len);
358 writeb(0, &desc->stat); /* Free descriptor */
359 port->txlast = next_desc(port, port->txlast, 1);
362 netif_wake_queue(dev);
363 spin_unlock(&port->lock);
367 static int sca_poll(struct napi_struct *napi, int budget)
369 port_t *port = container_of(napi, port_t, napi);
370 u8 stat = sca_intr_status(port->card);
373 if (stat & SCA_INTR_MSCI(port->phy_node))
376 if (stat & SCA_INTR_DMAC_TX(port->phy_node))
379 if (stat & SCA_INTR_DMAC_RX(port->phy_node))
380 received = sca_rx_done(port, budget);
382 if (received < budget) {
383 netif_rx_complete(port->dev, napi);
390 static irqreturn_t sca_intr(int irq, void* dev_id)
392 card_t *card = dev_id;
394 u8 stat = sca_intr_status(card);
397 for (i = 0; i < 2; i++) {
398 port_t *port = get_port(card, i);
399 if (port && (stat & (SCA_INTR_MSCI(i) | SCA_INTR_DMAC_RX(i) |
400 SCA_INTR_DMAC_TX(i)))) {
403 netif_rx_schedule(port->dev, &port->napi);
407 return IRQ_RETVAL(handled);
411 static void sca_set_port(port_t *port)
413 card_t* card = port_to_card(port);
414 u16 msci = get_msci(port);
415 u8 md2 = sca_in(msci + MD2, card);
416 unsigned int tmc, br = 10, brv = 1024;
419 if (port->settings.clock_rate > 0) {
420 /* Try lower br for better accuracy*/
423 brv >>= 1; /* brv = 2^9 = 512 max in specs */
425 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
426 tmc = CLOCK_BASE / brv / port->settings.clock_rate;
427 }while (br > 1 && tmc <= 128);
431 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
433 } else if (tmc > 255)
434 tmc = 256; /* tmc=0 means 256 - low baud rates */
436 port->settings.clock_rate = CLOCK_BASE / brv / tmc;
438 br = 9; /* Minimum clock rate */
439 tmc = 256; /* 8bit = 0 */
440 port->settings.clock_rate = CLOCK_BASE / (256 * 512);
443 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
444 port->txs = (port->txs & ~CLK_BRG_MASK) | br;
447 /* baud divisor - time constant*/
448 sca_out(port->tmc, msci + TMCR, card);
449 sca_out(port->tmc, msci + TMCT, card);
452 sca_out(port->rxs, msci + RXS, card);
453 sca_out(port->txs, msci + TXS, card);
455 if (port->settings.loopback)
458 md2 &= ~MD2_LOOPBACK;
460 sca_out(md2, msci + MD2, card);
465 static void sca_open(struct net_device *dev)
467 port_t *port = dev_to_port(dev);
468 card_t* card = port_to_card(port);
469 u16 msci = get_msci(port);
472 switch(port->encoding) {
473 case ENCODING_NRZ: md2 = MD2_NRZ; break;
474 case ENCODING_NRZI: md2 = MD2_NRZI; break;
475 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break;
476 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break;
477 default: md2 = MD2_MANCHESTER;
480 if (port->settings.loopback)
483 switch(port->parity) {
484 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break;
485 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break;
486 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break;
487 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break;
488 default: md0 = MD0_HDLC | MD0_CRC_NONE;
491 sca_out(CMD_RESET, msci + CMD, card);
492 sca_out(md0, msci + MD0, card);
493 sca_out(0x00, msci + MD1, card); /* no address field check */
494 sca_out(md2, msci + MD2, card);
495 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
496 /* Skip the rest of underrun frame */
497 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card);
498 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */
499 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */
500 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */
501 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */
502 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/
504 /* We're using the following interrupts:
505 - TXINT (DMAC completed all transmissions and DCD changes)
508 /* MSCI TXINT and RXINTA interrupt enable */
509 sca_outl(IE0_TXINT | IE0_RXINTA | IE0_CDCD, msci + IE0, card);
511 sca_out(port->tmc, msci + TMCR, card);
512 sca_out(port->tmc, msci + TMCT, card);
513 sca_out(port->rxs, msci + RXS, card);
514 sca_out(port->txs, msci + TXS, card);
515 sca_out(CMD_TX_ENABLE, msci + CMD, card);
516 sca_out(CMD_RX_ENABLE, msci + CMD, card);
518 sca_set_carrier(port);
520 napi_enable(&port->napi);
521 netif_start_queue(dev);
525 static void sca_close(struct net_device *dev)
527 port_t *port = dev_to_port(dev);
530 sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
532 napi_disable(&port->napi);
533 netif_stop_queue(dev);
537 static int sca_attach(struct net_device *dev, unsigned short encoding,
538 unsigned short parity)
540 if (encoding != ENCODING_NRZ &&
541 encoding != ENCODING_NRZI &&
542 encoding != ENCODING_FM_MARK &&
543 encoding != ENCODING_FM_SPACE &&
544 encoding != ENCODING_MANCHESTER)
547 if (parity != PARITY_NONE &&
548 parity != PARITY_CRC16_PR0 &&
549 parity != PARITY_CRC16_PR1 &&
550 parity != PARITY_CRC32_PR1_CCITT &&
551 parity != PARITY_CRC16_PR1_CCITT)
554 dev_to_port(dev)->encoding = encoding;
555 dev_to_port(dev)->parity = parity;
561 static void sca_dump_rings(struct net_device *dev)
563 port_t *port = dev_to_port(dev);
564 card_t *card = port_to_card(port);
567 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
568 sca_inl(get_dmac_rx(port) + CDAL, card),
569 sca_inl(get_dmac_rx(port) + EDAL, card),
570 sca_in(DSR_RX(phy_node(port)), card), port->rxin,
571 sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
572 for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
573 printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
575 printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
577 sca_inl(get_dmac_tx(port) + CDAL, card),
578 sca_inl(get_dmac_tx(port) + EDAL, card),
579 sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
580 sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
582 for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
583 printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
586 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x,"
587 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n",
588 sca_in(get_msci(port) + MD0, card),
589 sca_in(get_msci(port) + MD1, card),
590 sca_in(get_msci(port) + MD2, card),
591 sca_in(get_msci(port) + ST0, card),
592 sca_in(get_msci(port) + ST1, card),
593 sca_in(get_msci(port) + ST2, card),
594 sca_in(get_msci(port) + ST3, card),
595 sca_in(get_msci(port) + ST4, card),
596 sca_in(get_msci(port) + FST, card),
597 sca_in(get_msci(port) + CST0, card),
598 sca_in(get_msci(port) + CST1, card));
600 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card),
601 sca_inl(ISR0, card), sca_inl(ISR1, card));
603 #endif /* DEBUG_RINGS */
606 static int sca_xmit(struct sk_buff *skb, struct net_device *dev)
608 port_t *port = dev_to_port(dev);
609 card_t *card = port_to_card(port);
610 pkt_desc __iomem *desc;
613 spin_lock_irq(&port->lock);
615 desc = desc_address(port, port->txin + 1, 1);
616 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
619 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
623 desc = desc_address(port, port->txin, 1);
624 buff = buffer_offset(port, port->txin, 1);
626 memcpy_toio(winbase(card) + buff, skb->data, len);
628 writew(len, &desc->len);
629 writeb(ST_TX_EOM, &desc->stat);
630 dev->trans_start = jiffies;
632 port->txin = next_desc(port, port->txin, 1);
633 sca_outl(desc_offset(port, port->txin, 1),
634 get_dmac_tx(port) + EDAL, card);
636 sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
638 desc = desc_address(port, port->txin + 1, 1);
639 if (readb(&desc->stat)) /* allow 1 packet gap */
640 netif_stop_queue(dev);
642 spin_unlock_irq(&port->lock);
649 static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase,
652 /* Round RAM size to 32 bits, fill from end to start */
653 u32 i = ramsize &= ~3;
657 writel(i ^ 0x12345678, rambase + i);
660 for (i = 0; i < ramsize ; i += 4) {
661 if (readl(rambase + i) != (i ^ 0x12345678))
669 static void __devinit sca_init(card_t *card, int wait_states)
671 sca_out(wait_states, WCRL, card); /* Wait Control */
672 sca_out(wait_states, WCRM, card);
673 sca_out(wait_states, WCRH, card);
675 sca_out(0, DMER, card); /* DMA Master disable */
676 sca_out(0x03, PCR, card); /* DMA priority */
677 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
678 sca_out(0, DSR_TX(0), card);
679 sca_out(0, DSR_RX(1), card);
680 sca_out(0, DSR_TX(1), card);
681 sca_out(DMER_DME, DMER, card); /* DMA Master enable */