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   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.100"
  72 #define DRV_MODULE_RELDATE      "August 25, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 #define TG3_RAW_IP_ALIGN 2
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 #define FIRMWARE_TG3            "tigon/tg3.bin"
 142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 144
 145 static char version[] __devinitdata =
 146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 147
 148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 150 MODULE_LICENSE("GPL");
 151 MODULE_VERSION(DRV_MODULE_VERSION);
 152 MODULE_FIRMWARE(FIRMWARE_TG3);
 153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 155
 156
 157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 158 module_param(tg3_debug, int, 0);
 159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 160
 161 static struct pci_device_id tg3_pci_tbl[] = {
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 235         {}
 236 };
 237
 238 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 239
 240 static const struct {
 241         const char string[ETH_GSTRING_LEN];
 242 } ethtool_stats_keys[TG3_NUM_STATS] = {
 243         { "rx_octets" },
 244         { "rx_fragments" },
 245         { "rx_ucast_packets" },
 246         { "rx_mcast_packets" },
 247         { "rx_bcast_packets" },
 248         { "rx_fcs_errors" },
 249         { "rx_align_errors" },
 250         { "rx_xon_pause_rcvd" },
 251         { "rx_xoff_pause_rcvd" },
 252         { "rx_mac_ctrl_rcvd" },
 253         { "rx_xoff_entered" },
 254         { "rx_frame_too_long_errors" },
 255         { "rx_jabbers" },
 256         { "rx_undersize_packets" },
 257         { "rx_in_length_errors" },
 258         { "rx_out_length_errors" },
 259         { "rx_64_or_less_octet_packets" },
 260         { "rx_65_to_127_octet_packets" },
 261         { "rx_128_to_255_octet_packets" },
 262         { "rx_256_to_511_octet_packets" },
 263         { "rx_512_to_1023_octet_packets" },
 264         { "rx_1024_to_1522_octet_packets" },
 265         { "rx_1523_to_2047_octet_packets" },
 266         { "rx_2048_to_4095_octet_packets" },
 267         { "rx_4096_to_8191_octet_packets" },
 268         { "rx_8192_to_9022_octet_packets" },
 269
 270         { "tx_octets" },
 271         { "tx_collisions" },
 272
 273         { "tx_xon_sent" },
 274         { "tx_xoff_sent" },
 275         { "tx_flow_control" },
 276         { "tx_mac_errors" },
 277         { "tx_single_collisions" },
 278         { "tx_mult_collisions" },
 279         { "tx_deferred" },
 280         { "tx_excessive_collisions" },
 281         { "tx_late_collisions" },
 282         { "tx_collide_2times" },
 283         { "tx_collide_3times" },
 284         { "tx_collide_4times" },
 285         { "tx_collide_5times" },
 286         { "tx_collide_6times" },
 287         { "tx_collide_7times" },
 288         { "tx_collide_8times" },
 289         { "tx_collide_9times" },
 290         { "tx_collide_10times" },
 291         { "tx_collide_11times" },
 292         { "tx_collide_12times" },
 293         { "tx_collide_13times" },
 294         { "tx_collide_14times" },
 295         { "tx_collide_15times" },
 296         { "tx_ucast_packets" },
 297         { "tx_mcast_packets" },
 298         { "tx_bcast_packets" },
 299         { "tx_carrier_sense_errors" },
 300         { "tx_discards" },
 301         { "tx_errors" },
 302
 303         { "dma_writeq_full" },
 304         { "dma_write_prioq_full" },
 305         { "rxbds_empty" },
 306         { "rx_discards" },
 307         { "rx_errors" },
 308         { "rx_threshold_hit" },
 309
 310         { "dma_readq_full" },
 311         { "dma_read_prioq_full" },
 312         { "tx_comp_queue_full" },
 313
 314         { "ring_set_send_prod_index" },
 315         { "ring_status_update" },
 316         { "nic_irqs" },
 317         { "nic_avoided_irqs" },
 318         { "nic_tx_threshold_hit" }
 319 };
 320
 321 static const struct {
 322         const char string[ETH_GSTRING_LEN];
 323 } ethtool_test_keys[TG3_NUM_TEST] = {
 324         { "nvram test     (online) " },
 325         { "link test      (online) " },
 326         { "register test  (offline)" },
 327         { "memory test    (offline)" },
 328         { "loopback test  (offline)" },
 329         { "interrupt test (offline)" },
 330 };
 331
 332 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 333 {
 334         writel(val, tp->regs + off);
 335 }
 336
 337 static u32 tg3_read32(struct tg3 *tp, u32 off)
 338 {
 339         return (readl(tp->regs + off));
 340 }
 341
 342 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 343 {
 344         writel(val, tp->aperegs + off);
 345 }
 346
 347 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 348 {
 349         return (readl(tp->aperegs + off));
 350 }
 351
 352 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 353 {
 354         unsigned long flags;
 355
 356         spin_lock_irqsave(&tp->indirect_lock, flags);
 357         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 358         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 359         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 360 }
 361
 362 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 363 {
 364         writel(val, tp->regs + off);
 365         readl(tp->regs + off);
 366 }
 367
 368 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 369 {
 370         unsigned long flags;
 371         u32 val;
 372
 373         spin_lock_irqsave(&tp->indirect_lock, flags);
 374         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 375         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 376         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 377         return val;
 378 }
 379
 380 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 381 {
 382         unsigned long flags;
 383
 384         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 385                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 386                                        TG3_64BIT_REG_LOW, val);
 387                 return;
 388         }
 389         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 390                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 391                                        TG3_64BIT_REG_LOW, val);
 392                 return;
 393         }
 394
 395         spin_lock_irqsave(&tp->indirect_lock, flags);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 398         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 399
 400         /* In indirect mode when disabling interrupts, we also need
 401          * to clear the interrupt bit in the GRC local ctrl register.
 402          */
 403         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 404             (val == 0x1)) {
 405                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 406                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 407         }
 408 }
 409
 410 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 411 {
 412         unsigned long flags;
 413         u32 val;
 414
 415         spin_lock_irqsave(&tp->indirect_lock, flags);
 416         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 417         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 418         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 419         return val;
 420 }
 421
 422 /* usec_wait specifies the wait time in usec when writing to certain registers
 423  * where it is unsafe to read back the register without some delay.
 424  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 425  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 426  */
 427 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 428 {
 429         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 430             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 431                 /* Non-posted methods */
 432                 tp->write32(tp, off, val);
 433         else {
 434                 /* Posted method */
 435                 tg3_write32(tp, off, val);
 436                 if (usec_wait)
 437                         udelay(usec_wait);
 438                 tp->read32(tp, off);
 439         }
 440         /* Wait again after the read for the posted method to guarantee that
 441          * the wait time is met.
 442          */
 443         if (usec_wait)
 444                 udelay(usec_wait);
 445 }
 446
 447 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 448 {
 449         tp->write32_mbox(tp, off, val);
 450         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 451             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 452                 tp->read32_mbox(tp, off);
 453 }
 454
 455 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 456 {
 457         void __iomem *mbox = tp->regs + off;
 458         writel(val, mbox);
 459         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 460                 writel(val, mbox);
 461         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 462                 readl(mbox);
 463 }
 464
 465 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 466 {
 467         return (readl(tp->regs + off + GRCMBOX_BASE));
 468 }
 469
 470 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 471 {
 472         writel(val, tp->regs + off + GRCMBOX_BASE);
 473 }
 474
 475 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 476 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 477 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 478 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 479 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 480
 481 #define tw32(reg,val)           tp->write32(tp, reg, val)
 482 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 483 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 484 #define tr32(reg)               tp->read32(tp, reg)
 485
 486 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 487 {
 488         unsigned long flags;
 489
 490         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 491             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 492                 return;
 493
 494         spin_lock_irqsave(&tp->indirect_lock, flags);
 495         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 497                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 498
 499                 /* Always leave this as zero. */
 500                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 501         } else {
 502                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 503                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 504
 505                 /* Always leave this as zero. */
 506                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 507         }
 508         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 509 }
 510
 511 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 512 {
 513         unsigned long flags;
 514
 515         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 516             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 517                 *val = 0;
 518                 return;
 519         }
 520
 521         spin_lock_irqsave(&tp->indirect_lock, flags);
 522         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 523                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 524                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 525
 526                 /* Always leave this as zero. */
 527                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 528         } else {
 529                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 530                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 531
 532                 /* Always leave this as zero. */
 533                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 534         }
 535         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 536 }
 537
 538 static void tg3_ape_lock_init(struct tg3 *tp)
 539 {
 540         int i;
 541
 542         /* Make sure the driver hasn't any stale locks. */
 543         for (i = 0; i < 8; i++)
 544                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 545                                 APE_LOCK_GRANT_DRIVER);
 546 }
 547
 548 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 549 {
 550         int i, off;
 551         int ret = 0;
 552         u32 status;
 553
 554         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 555                 return 0;
 556
 557         switch (locknum) {
 558                 case TG3_APE_LOCK_GRC:
 559                 case TG3_APE_LOCK_MEM:
 560                         break;
 561                 default:
 562                         return -EINVAL;
 563         }
 564
 565         off = 4 * locknum;
 566
 567         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 568
 569         /* Wait for up to 1 millisecond to acquire lock. */
 570         for (i = 0; i < 100; i++) {
 571                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 572                 if (status == APE_LOCK_GRANT_DRIVER)
 573                         break;
 574                 udelay(10);
 575         }
 576
 577         if (status != APE_LOCK_GRANT_DRIVER) {
 578                 /* Revoke the lock request. */
 579                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 580                                 APE_LOCK_GRANT_DRIVER);
 581
 582                 ret = -EBUSY;
 583         }
 584
 585         return ret;
 586 }
 587
 588 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 589 {
 590         int off;
 591
 592         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 593                 return;
 594
 595         switch (locknum) {
 596                 case TG3_APE_LOCK_GRC:
 597                 case TG3_APE_LOCK_MEM:
 598                         break;
 599                 default:
 600                         return;
 601         }
 602
 603         off = 4 * locknum;
 604         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 605 }
 606
 607 static void tg3_disable_ints(struct tg3 *tp)
 608 {
 609         tw32(TG3PCI_MISC_HOST_CTRL,
 610              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 611         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 612 }
 613
 614 static inline void tg3_cond_int(struct tg3 *tp)
 615 {
 616         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 617             (tp->hw_status->status & SD_STATUS_UPDATED))
 618                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 619         else
 620                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 621                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 622 }
 623
 624 static void tg3_enable_ints(struct tg3 *tp)
 625 {
 626         tp->irq_sync = 0;
 627         wmb();
 628
 629         tw32(TG3PCI_MISC_HOST_CTRL,
 630              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 631         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 632                        (tp->last_tag << 24));
 633         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 634                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 635                                (tp->last_tag << 24));
 636         tg3_cond_int(tp);
 637 }
 638
 639 static inline unsigned int tg3_has_work(struct tg3 *tp)
 640 {
 641         struct tg3_hw_status *sblk = tp->hw_status;
 642         unsigned int work_exists = 0;
 643
 644         /* check for phy events */
 645         if (!(tp->tg3_flags &
 646               (TG3_FLAG_USE_LINKCHG_REG |
 647                TG3_FLAG_POLL_SERDES))) {
 648                 if (sblk->status & SD_STATUS_LINK_CHG)
 649                         work_exists = 1;
 650         }
 651         /* check for RX/TX work to do */
 652         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 653             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 654                 work_exists = 1;
 655
 656         return work_exists;
 657 }
 658
 659 /* tg3_restart_ints
 660  *  similar to tg3_enable_ints, but it accurately determines whether there
 661  *  is new work pending and can return without flushing the PIO write
 662  *  which reenables interrupts
 663  */
 664 static void tg3_restart_ints(struct tg3 *tp)
 665 {
 666         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 667                      tp->last_tag << 24);
 668         mmiowb();
 669
 670         /* When doing tagged status, this work check is unnecessary.
 671          * The last_tag we write above tells the chip which piece of
 672          * work we've completed.
 673          */
 674         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 675             tg3_has_work(tp))
 676                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 677                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 678 }
 679
 680 static inline void tg3_netif_stop(struct tg3 *tp)
 681 {
 682         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 683         napi_disable(&tp->napi);
 684         netif_tx_disable(tp->dev);
 685 }
 686
 687 static inline void tg3_netif_start(struct tg3 *tp)
 688 {
 689         netif_wake_queue(tp->dev);
 690         /* NOTE: unconditional netif_wake_queue is only appropriate
 691          * so long as all callers are assured to have free tx slots
 692          * (such as after tg3_init_hw)
 693          */
 694         napi_enable(&tp->napi);
 695         tp->hw_status->status |= SD_STATUS_UPDATED;
 696         tg3_enable_ints(tp);
 697 }
 698
 699 static void tg3_switch_clocks(struct tg3 *tp)
 700 {
 701         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 702         u32 orig_clock_ctrl;
 703
 704         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 705             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 706                 return;
 707
 708         orig_clock_ctrl = clock_ctrl;
 709         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 710                        CLOCK_CTRL_CLKRUN_OENABLE |
 711                        0x1f);
 712         tp->pci_clock_ctrl = clock_ctrl;
 713
 714         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 715                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 716                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 717                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 718                 }
 719         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 720                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 721                             clock_ctrl |
 722                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 723                             40);
 724                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 725                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 726                             40);
 727         }
 728         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 729 }
 730
 731 #define PHY_BUSY_LOOPS  5000
 732
 733 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 734 {
 735         u32 frame_val;
 736         unsigned int loops;
 737         int ret;
 738
 739         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 740                 tw32_f(MAC_MI_MODE,
 741                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 742                 udelay(80);
 743         }
 744
 745         *val = 0x0;
 746
 747         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 748                       MI_COM_PHY_ADDR_MASK);
 749         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 750                       MI_COM_REG_ADDR_MASK);
 751         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 752
 753         tw32_f(MAC_MI_COM, frame_val);
 754
 755         loops = PHY_BUSY_LOOPS;
 756         while (loops != 0) {
 757                 udelay(10);
 758                 frame_val = tr32(MAC_MI_COM);
 759
 760                 if ((frame_val & MI_COM_BUSY) == 0) {
 761                         udelay(5);
 762                         frame_val = tr32(MAC_MI_COM);
 763                         break;
 764                 }
 765                 loops -= 1;
 766         }
 767
 768         ret = -EBUSY;
 769         if (loops != 0) {
 770                 *val = frame_val & MI_COM_DATA_MASK;
 771                 ret = 0;
 772         }
 773
 774         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 775                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 776                 udelay(80);
 777         }
 778
 779         return ret;
 780 }
 781
 782 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 783 {
 784         u32 frame_val;
 785         unsigned int loops;
 786         int ret;
 787
 788         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 789             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 790                 return 0;
 791
 792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 793                 tw32_f(MAC_MI_MODE,
 794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 795                 udelay(80);
 796         }
 797
 798         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 799                       MI_COM_PHY_ADDR_MASK);
 800         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 801                       MI_COM_REG_ADDR_MASK);
 802         frame_val |= (val & MI_COM_DATA_MASK);
 803         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 804
 805         tw32_f(MAC_MI_COM, frame_val);
 806
 807         loops = PHY_BUSY_LOOPS;
 808         while (loops != 0) {
 809                 udelay(10);
 810                 frame_val = tr32(MAC_MI_COM);
 811                 if ((frame_val & MI_COM_BUSY) == 0) {
 812                         udelay(5);
 813                         frame_val = tr32(MAC_MI_COM);
 814                         break;
 815                 }
 816                 loops -= 1;
 817         }
 818
 819         ret = -EBUSY;
 820         if (loops != 0)
 821                 ret = 0;
 822
 823         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 824                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 825                 udelay(80);
 826         }
 827
 828         return ret;
 829 }
 830
 831 static int tg3_bmcr_reset(struct tg3 *tp)
 832 {
 833         u32 phy_control;
 834         int limit, err;
 835
 836         /* OK, reset it, and poll the BMCR_RESET bit until it
 837          * clears or we time out.
 838          */
 839         phy_control = BMCR_RESET;
 840         err = tg3_writephy(tp, MII_BMCR, phy_control);
 841         if (err != 0)
 842                 return -EBUSY;
 843
 844         limit = 5000;
 845         while (limit--) {
 846                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 847                 if (err != 0)
 848                         return -EBUSY;
 849
 850                 if ((phy_control & BMCR_RESET) == 0) {
 851                         udelay(40);
 852                         break;
 853                 }
 854                 udelay(10);
 855         }
 856         if (limit < 0)
 857                 return -EBUSY;
 858
 859         return 0;
 860 }
 861
 862 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 863 {
 864         struct tg3 *tp = bp->priv;
 865         u32 val;
 866
 867         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 868                 return -EAGAIN;
 869
 870         if (tg3_readphy(tp, reg, &val))
 871                 return -EIO;
 872
 873         return val;
 874 }
 875
 876 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 877 {
 878         struct tg3 *tp = bp->priv;
 879
 880         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 881                 return -EAGAIN;
 882
 883         if (tg3_writephy(tp, reg, val))
 884                 return -EIO;
 885
 886         return 0;
 887 }
 888
 889 static int tg3_mdio_reset(struct mii_bus *bp)
 890 {
 891         return 0;
 892 }
 893
 894 static void tg3_mdio_config_5785(struct tg3 *tp)
 895 {
 896         u32 val;
 897         struct phy_device *phydev;
 898
 899         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 900         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 901         case TG3_PHY_ID_BCM50610:
 902                 val = MAC_PHYCFG2_50610_LED_MODES;
 903                 break;
 904         case TG3_PHY_ID_BCMAC131:
 905                 val = MAC_PHYCFG2_AC131_LED_MODES;
 906                 break;
 907         case TG3_PHY_ID_RTL8211C:
 908                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 909                 break;
 910         case TG3_PHY_ID_RTL8201E:
 911                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 912                 break;
 913         default:
 914                 return;
 915         }
 916
 917         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 918                 tw32(MAC_PHYCFG2, val);
 919
 920                 val = tr32(MAC_PHYCFG1);
 921                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 922                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 923                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 924                 tw32(MAC_PHYCFG1, val);
 925
 926                 return;
 927         }
 928
 929         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 930                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 931                        MAC_PHYCFG2_FMODE_MASK_MASK |
 932                        MAC_PHYCFG2_GMODE_MASK_MASK |
 933                        MAC_PHYCFG2_ACT_MASK_MASK   |
 934                        MAC_PHYCFG2_QUAL_MASK_MASK |
 935                        MAC_PHYCFG2_INBAND_ENABLE;
 936
 937         tw32(MAC_PHYCFG2, val);
 938
 939         val = tr32(MAC_PHYCFG1);
 940         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 941                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 942         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 943                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 944                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 945                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 946                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 947         }
 948         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 949                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 950         tw32(MAC_PHYCFG1, val);
 951
 952         val = tr32(MAC_EXT_RGMII_MODE);
 953         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 954                  MAC_RGMII_MODE_RX_QUALITY |
 955                  MAC_RGMII_MODE_RX_ACTIVITY |
 956                  MAC_RGMII_MODE_RX_ENG_DET |
 957                  MAC_RGMII_MODE_TX_ENABLE |
 958                  MAC_RGMII_MODE_TX_LOWPWR |
 959                  MAC_RGMII_MODE_TX_RESET);
 960         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 961                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 962                         val |= MAC_RGMII_MODE_RX_INT_B |
 963                                MAC_RGMII_MODE_RX_QUALITY |
 964                                MAC_RGMII_MODE_RX_ACTIVITY |
 965                                MAC_RGMII_MODE_RX_ENG_DET;
 966                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 967                         val |= MAC_RGMII_MODE_TX_ENABLE |
 968                                MAC_RGMII_MODE_TX_LOWPWR |
 969                                MAC_RGMII_MODE_TX_RESET;
 970         }
 971         tw32(MAC_EXT_RGMII_MODE, val);
 972 }
 973
 974 static void tg3_mdio_start(struct tg3 *tp)
 975 {
 976         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 977                 mutex_lock(&tp->mdio_bus->mdio_lock);
 978                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 979                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 980         }
 981
 982         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 983         tw32_f(MAC_MI_MODE, tp->mi_mode);
 984         udelay(80);
 985
 986         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 987             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 988                 tg3_mdio_config_5785(tp);
 989 }
 990
 991 static void tg3_mdio_stop(struct tg3 *tp)
 992 {
 993         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 994                 mutex_lock(&tp->mdio_bus->mdio_lock);
 995                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 996                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 997         }
 998 }
 999
1000 static int tg3_mdio_init(struct tg3 *tp)
1001 {
1002         int i;
1003         u32 reg;
1004         struct phy_device *phydev;
1005
1006         tg3_mdio_start(tp);
1007
1008         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1009             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1010                 return 0;
1011
1012         tp->mdio_bus = mdiobus_alloc();
1013         if (tp->mdio_bus == NULL)
1014                 return -ENOMEM;
1015
1016         tp->mdio_bus->name     = "tg3 mdio bus";
1017         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1018                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1019         tp->mdio_bus->priv     = tp;
1020         tp->mdio_bus->parent   = &tp->pdev->dev;
1021         tp->mdio_bus->read     = &tg3_mdio_read;
1022         tp->mdio_bus->write    = &tg3_mdio_write;
1023         tp->mdio_bus->reset    = &tg3_mdio_reset;
1024         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1025         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1026
1027         for (i = 0; i < PHY_MAX_ADDR; i++)
1028                 tp->mdio_bus->irq[i] = PHY_POLL;
1029
1030         /* The bus registration will look for all the PHYs on the mdio bus.
1031          * Unfortunately, it does not ensure the PHY is powered up before
1032          * accessing the PHY ID registers.  A chip reset is the
1033          * quickest way to bring the device back to an operational state..
1034          */
1035         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1036                 tg3_bmcr_reset(tp);
1037
1038         i = mdiobus_register(tp->mdio_bus);
1039         if (i) {
1040                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1041                         tp->dev->name, i);
1042                 mdiobus_free(tp->mdio_bus);
1043                 return i;
1044         }
1045
1046         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1047
1048         if (!phydev || !phydev->drv) {
1049                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1050                 mdiobus_unregister(tp->mdio_bus);
1051                 mdiobus_free(tp->mdio_bus);
1052                 return -ENODEV;
1053         }
1054
1055         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1056         case TG3_PHY_ID_BCM57780:
1057                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1058                 break;
1059         case TG3_PHY_ID_BCM50610:
1060                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1061                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1062                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1063                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1066                 /* fallthru */
1067         case TG3_PHY_ID_RTL8211C:
1068                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1069                 break;
1070         case TG3_PHY_ID_RTL8201E:
1071         case TG3_PHY_ID_BCMAC131:
1072                 phydev->interface = PHY_INTERFACE_MODE_MII;
1073                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1074                 break;
1075         }
1076
1077         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1078
1079         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081
1082         return 0;
1083 }
1084
1085 static void tg3_mdio_fini(struct tg3 *tp)
1086 {
1087         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1088                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1089                 mdiobus_unregister(tp->mdio_bus);
1090                 mdiobus_free(tp->mdio_bus);
1091                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1092         }
1093 }
1094
1095 /* tp->lock is held. */
1096 static inline void tg3_generate_fw_event(struct tg3 *tp)
1097 {
1098         u32 val;
1099
1100         val = tr32(GRC_RX_CPU_EVENT);
1101         val |= GRC_RX_CPU_DRIVER_EVENT;
1102         tw32_f(GRC_RX_CPU_EVENT, val);
1103
1104         tp->last_event_jiffies = jiffies;
1105 }
1106
1107 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1108
1109 /* tp->lock is held. */
1110 static void tg3_wait_for_event_ack(struct tg3 *tp)
1111 {
1112         int i;
1113         unsigned int delay_cnt;
1114         long time_remain;
1115
1116         /* If enough time has passed, no wait is necessary. */
1117         time_remain = (long)(tp->last_event_jiffies + 1 +
1118                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1119                       (long)jiffies;
1120         if (time_remain < 0)
1121                 return;
1122
1123         /* Check if we can shorten the wait time. */
1124         delay_cnt = jiffies_to_usecs(time_remain);
1125         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1126                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1127         delay_cnt = (delay_cnt >> 3) + 1;
1128
1129         for (i = 0; i < delay_cnt; i++) {
1130                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1131                         break;
1132                 udelay(8);
1133         }
1134 }
1135
1136 /* tp->lock is held. */
1137 static void tg3_ump_link_report(struct tg3 *tp)
1138 {
1139         u32 reg;
1140         u32 val;
1141
1142         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1143             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1144                 return;
1145
1146         tg3_wait_for_event_ack(tp);
1147
1148         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1149
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_BMCR, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_BMSR, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1158
1159         val = 0;
1160         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1161                 val = reg << 16;
1162         if (!tg3_readphy(tp, MII_LPA, &reg))
1163                 val |= (reg & 0xffff);
1164         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1165
1166         val = 0;
1167         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1168                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1169                         val = reg << 16;
1170                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1171                         val |= (reg & 0xffff);
1172         }
1173         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1174
1175         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1176                 val = reg << 16;
1177         else
1178                 val = 0;
1179         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1180
1181         tg3_generate_fw_event(tp);
1182 }
1183
1184 static void tg3_link_report(struct tg3 *tp)
1185 {
1186         if (!netif_carrier_ok(tp->dev)) {
1187                 if (netif_msg_link(tp))
1188                         printk(KERN_INFO PFX "%s: Link is down.\n",
1189                                tp->dev->name);
1190                 tg3_ump_link_report(tp);
1191         } else if (netif_msg_link(tp)) {
1192                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1193                        tp->dev->name,
1194                        (tp->link_config.active_speed == SPEED_1000 ?
1195                         1000 :
1196                         (tp->link_config.active_speed == SPEED_100 ?
1197                          100 : 10)),
1198                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1199                         "full" : "half"));
1200
1201                 printk(KERN_INFO PFX
1202                        "%s: Flow control is %s for TX and %s for RX.\n",
1203                        tp->dev->name,
1204                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1205                        "on" : "off",
1206                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1207                        "on" : "off");
1208                 tg3_ump_link_report(tp);
1209         }
1210 }
1211
1212 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1213 {
1214         u16 miireg;
1215
1216         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1217                 miireg = ADVERTISE_PAUSE_CAP;
1218         else if (flow_ctrl & FLOW_CTRL_TX)
1219                 miireg = ADVERTISE_PAUSE_ASYM;
1220         else if (flow_ctrl & FLOW_CTRL_RX)
1221                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1222         else
1223                 miireg = 0;
1224
1225         return miireg;
1226 }
1227
1228 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1229 {
1230         u16 miireg;
1231
1232         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1233                 miireg = ADVERTISE_1000XPAUSE;
1234         else if (flow_ctrl & FLOW_CTRL_TX)
1235                 miireg = ADVERTISE_1000XPSE_ASYM;
1236         else if (flow_ctrl & FLOW_CTRL_RX)
1237                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1238         else
1239                 miireg = 0;
1240
1241         return miireg;
1242 }
1243
1244 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1245 {
1246         u8 cap = 0;
1247
1248         if (lcladv & ADVERTISE_1000XPAUSE) {
1249                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1250                         if (rmtadv & LPA_1000XPAUSE)
1251                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1252                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1253                                 cap = FLOW_CTRL_RX;
1254                 } else {
1255                         if (rmtadv & LPA_1000XPAUSE)
1256                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1257                 }
1258         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1260                         cap = FLOW_CTRL_TX;
1261         }
1262
1263         return cap;
1264 }
1265
1266 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1267 {
1268         u8 autoneg;
1269         u8 flowctrl = 0;
1270         u32 old_rx_mode = tp->rx_mode;
1271         u32 old_tx_mode = tp->tx_mode;
1272
1273         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1274                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1275         else
1276                 autoneg = tp->link_config.autoneg;
1277
1278         if (autoneg == AUTONEG_ENABLE &&
1279             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1280                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1281                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1282                 else
1283                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1284         } else
1285                 flowctrl = tp->link_config.flowctrl;
1286
1287         tp->link_config.active_flowctrl = flowctrl;
1288
1289         if (flowctrl & FLOW_CTRL_RX)
1290                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1291         else
1292                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1293
1294         if (old_rx_mode != tp->rx_mode)
1295                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1296
1297         if (flowctrl & FLOW_CTRL_TX)
1298                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1299         else
1300                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1301
1302         if (old_tx_mode != tp->tx_mode)
1303                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1304 }
1305
1306 static void tg3_adjust_link(struct net_device *dev)
1307 {
1308         u8 oldflowctrl, linkmesg = 0;
1309         u32 mac_mode, lcl_adv, rmt_adv;
1310         struct tg3 *tp = netdev_priv(dev);
1311         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1312
1313         spin_lock(&tp->lock);
1314
1315         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1316                                     MAC_MODE_HALF_DUPLEX);
1317
1318         oldflowctrl = tp->link_config.active_flowctrl;
1319
1320         if (phydev->link) {
1321                 lcl_adv = 0;
1322                 rmt_adv = 0;
1323
1324                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1325                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1326                 else
1327                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1328
1329                 if (phydev->duplex == DUPLEX_HALF)
1330                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1331                 else {
1332                         lcl_adv = tg3_advert_flowctrl_1000T(
1333                                   tp->link_config.flowctrl);
1334
1335                         if (phydev->pause)
1336                                 rmt_adv = LPA_PAUSE_CAP;
1337                         if (phydev->asym_pause)
1338                                 rmt_adv |= LPA_PAUSE_ASYM;
1339                 }
1340
1341                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1342         } else
1343                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1344
1345         if (mac_mode != tp->mac_mode) {
1346                 tp->mac_mode = mac_mode;
1347                 tw32_f(MAC_MODE, tp->mac_mode);
1348                 udelay(40);
1349         }
1350
1351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1352                 if (phydev->speed == SPEED_10)
1353                         tw32(MAC_MI_STAT,
1354                              MAC_MI_STAT_10MBPS_MODE |
1355                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1356                 else
1357                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1358         }
1359
1360         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1361                 tw32(MAC_TX_LENGTHS,
1362                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1363                       (6 << TX_LENGTHS_IPG_SHIFT) |
1364                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1365         else
1366                 tw32(MAC_TX_LENGTHS,
1367                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1368                       (6 << TX_LENGTHS_IPG_SHIFT) |
1369                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1370
1371         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1372             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1373             phydev->speed != tp->link_config.active_speed ||
1374             phydev->duplex != tp->link_config.active_duplex ||
1375             oldflowctrl != tp->link_config.active_flowctrl)
1376             linkmesg = 1;
1377
1378         tp->link_config.active_speed = phydev->speed;
1379         tp->link_config.active_duplex = phydev->duplex;
1380
1381         spin_unlock(&tp->lock);
1382
1383         if (linkmesg)
1384                 tg3_link_report(tp);
1385 }
1386
1387 static int tg3_phy_init(struct tg3 *tp)
1388 {
1389         struct phy_device *phydev;
1390
1391         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1392                 return 0;
1393
1394         /* Bring the PHY back to a known state. */
1395         tg3_bmcr_reset(tp);
1396
1397         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1398
1399         /* Attach the MAC to the PHY. */
1400         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1401                              phydev->dev_flags, phydev->interface);
1402         if (IS_ERR(phydev)) {
1403                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1404                 return PTR_ERR(phydev);
1405         }
1406
1407         /* Mask with MAC supported features. */
1408         switch (phydev->interface) {
1409         case PHY_INTERFACE_MODE_GMII:
1410         case PHY_INTERFACE_MODE_RGMII:
1411                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1412                         phydev->supported &= (PHY_GBIT_FEATURES |
1413                                               SUPPORTED_Pause |
1414                                               SUPPORTED_Asym_Pause);
1415                         break;
1416                 }
1417                 /* fallthru */
1418         case PHY_INTERFACE_MODE_MII:
1419                 phydev->supported &= (PHY_BASIC_FEATURES |
1420                                       SUPPORTED_Pause |
1421                                       SUPPORTED_Asym_Pause);
1422                 break;
1423         default:
1424                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1425                 return -EINVAL;
1426         }
1427
1428         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1429
1430         phydev->advertising = phydev->supported;
1431
1432         return 0;
1433 }
1434
1435 static void tg3_phy_start(struct tg3 *tp)
1436 {
1437         struct phy_device *phydev;
1438
1439         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1440                 return;
1441
1442         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1443
1444         if (tp->link_config.phy_is_low_power) {
1445                 tp->link_config.phy_is_low_power = 0;
1446                 phydev->speed = tp->link_config.orig_speed;
1447                 phydev->duplex = tp->link_config.orig_duplex;
1448                 phydev->autoneg = tp->link_config.orig_autoneg;
1449                 phydev->advertising = tp->link_config.orig_advertising;
1450         }
1451
1452         phy_start(phydev);
1453
1454         phy_start_aneg(phydev);
1455 }
1456
1457 static void tg3_phy_stop(struct tg3 *tp)
1458 {
1459         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1460                 return;
1461
1462         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1463 }
1464
1465 static void tg3_phy_fini(struct tg3 *tp)
1466 {
1467         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1468                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1469                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1470         }
1471 }
1472
1473 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1474 {
1475         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1476         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1477 }
1478
1479 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1480 {
1481         u32 phytest;
1482
1483         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1484                 u32 phy;
1485
1486                 tg3_writephy(tp, MII_TG3_FET_TEST,
1487                              phytest | MII_TG3_FET_SHADOW_EN);
1488                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1489                         if (enable)
1490                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1491                         else
1492                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1493                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1494                 }
1495                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1496         }
1497 }
1498
1499 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1500 {
1501         u32 reg;
1502
1503         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1504                 return;
1505
1506         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1507                 tg3_phy_fet_toggle_apd(tp, enable);
1508                 return;
1509         }
1510
1511         reg = MII_TG3_MISC_SHDW_WREN |
1512               MII_TG3_MISC_SHDW_SCR5_SEL |
1513               MII_TG3_MISC_SHDW_SCR5_LPED |
1514               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1515               MII_TG3_MISC_SHDW_SCR5_SDTL |
1516               MII_TG3_MISC_SHDW_SCR5_C125OE;
1517         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1518                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1519
1520         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1521
1522
1523         reg = MII_TG3_MISC_SHDW_WREN |
1524               MII_TG3_MISC_SHDW_APD_SEL |
1525               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1526         if (enable)
1527                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1528
1529         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1530 }
1531
1532 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1533 {
1534         u32 phy;
1535
1536         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1537             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1538                 return;
1539
1540         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1541                 u32 ephy;
1542
1543                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1544                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1545
1546                         tg3_writephy(tp, MII_TG3_FET_TEST,
1547                                      ephy | MII_TG3_FET_SHADOW_EN);
1548                         if (!tg3_readphy(tp, reg, &phy)) {
1549                                 if (enable)
1550                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1551                                 else
1552                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1553                                 tg3_writephy(tp, reg, phy);
1554                         }
1555                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1556                 }
1557         } else {
1558                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1559                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1560                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1561                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1562                         if (enable)
1563                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1564                         else
1565                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1566                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1567                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1568                 }
1569         }
1570 }
1571
1572 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1573 {
1574         u32 val;
1575
1576         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1577                 return;
1578
1579         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1580             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1581                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1582                              (val | (1 << 15) | (1 << 4)));
1583 }
1584
1585 static void tg3_phy_apply_otp(struct tg3 *tp)
1586 {
1587         u32 otp, phy;
1588
1589         if (!tp->phy_otp)
1590                 return;
1591
1592         otp = tp->phy_otp;
1593
1594         /* Enable SM_DSP clock and tx 6dB coding. */
1595         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1596               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1597               MII_TG3_AUXCTL_ACTL_TX_6DB;
1598         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1599
1600         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1601         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1602         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1603
1604         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1605               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1606         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1607
1608         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1609         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1610         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1611
1612         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1613         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1614
1615         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1616         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1617
1618         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1619               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1620         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1621
1622         /* Turn off SM_DSP clock. */
1623         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1624               MII_TG3_AUXCTL_ACTL_TX_6DB;
1625         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1626 }
1627
1628 static int tg3_wait_macro_done(struct tg3 *tp)
1629 {
1630         int limit = 100;
1631
1632         while (limit--) {
1633                 u32 tmp32;
1634
1635                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1636                         if ((tmp32 & 0x1000) == 0)
1637                                 break;
1638                 }
1639         }
1640         if (limit < 0)
1641                 return -EBUSY;
1642
1643         return 0;
1644 }
1645
1646 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1647 {
1648         static const u32 test_pat[4][6] = {
1649         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1650         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1651         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1652         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1653         };
1654         int chan;
1655
1656         for (chan = 0; chan < 4; chan++) {
1657                 int i;
1658
1659                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1660                              (chan * 0x2000) | 0x0200);
1661                 tg3_writephy(tp, 0x16, 0x0002);
1662
1663                 for (i = 0; i < 6; i++)
1664                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1665                                      test_pat[chan][i]);
1666
1667                 tg3_writephy(tp, 0x16, 0x0202);
1668                 if (tg3_wait_macro_done(tp)) {
1669                         *resetp = 1;
1670                         return -EBUSY;
1671                 }
1672
1673                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1674                              (chan * 0x2000) | 0x0200);
1675                 tg3_writephy(tp, 0x16, 0x0082);
1676                 if (tg3_wait_macro_done(tp)) {
1677                         *resetp = 1;
1678                         return -EBUSY;
1679                 }
1680
1681                 tg3_writephy(tp, 0x16, 0x0802);
1682                 if (tg3_wait_macro_done(tp)) {
1683                         *resetp = 1;
1684                         return -EBUSY;
1685                 }
1686
1687                 for (i = 0; i < 6; i += 2) {
1688                         u32 low, high;
1689
1690                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1691                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1692                             tg3_wait_macro_done(tp)) {
1693                                 *resetp = 1;
1694                                 return -EBUSY;
1695                         }
1696                         low &= 0x7fff;
1697                         high &= 0x000f;
1698                         if (low != test_pat[chan][i] ||
1699                             high != test_pat[chan][i+1]) {
1700                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1701                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1702                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1703
1704                                 return -EBUSY;
1705                         }
1706                 }
1707         }
1708
1709         return 0;
1710 }
1711
1712 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1713 {
1714         int chan;
1715
1716         for (chan = 0; chan < 4; chan++) {
1717                 int i;
1718
1719                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720                              (chan * 0x2000) | 0x0200);
1721                 tg3_writephy(tp, 0x16, 0x0002);
1722                 for (i = 0; i < 6; i++)
1723                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1724                 tg3_writephy(tp, 0x16, 0x0202);
1725                 if (tg3_wait_macro_done(tp))
1726                         return -EBUSY;
1727         }
1728
1729         return 0;
1730 }
1731
1732 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1733 {
1734         u32 reg32, phy9_orig;
1735         int retries, do_phy_reset, err;
1736
1737         retries = 10;
1738         do_phy_reset = 1;
1739         do {
1740                 if (do_phy_reset) {
1741                         err = tg3_bmcr_reset(tp);
1742                         if (err)
1743                                 return err;
1744                         do_phy_reset = 0;
1745                 }
1746
1747                 /* Disable transmitter and interrupt.  */
1748                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1749                         continue;
1750
1751                 reg32 |= 0x3000;
1752                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1753
1754                 /* Set full-duplex, 1000 mbps.  */
1755                 tg3_writephy(tp, MII_BMCR,
1756                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1757
1758                 /* Set to master mode.  */
1759                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1760                         continue;
1761
1762                 tg3_writephy(tp, MII_TG3_CTRL,
1763                              (MII_TG3_CTRL_AS_MASTER |
1764                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1765
1766                 /* Enable SM_DSP_CLOCK and 6dB.  */
1767                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1768
1769                 /* Block the PHY control access.  */
1770                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1771                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1772
1773                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1774                 if (!err)
1775                         break;
1776         } while (--retries);
1777
1778         err = tg3_phy_reset_chanpat(tp);
1779         if (err)
1780                 return err;
1781
1782         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1783         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1784
1785         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1786         tg3_writephy(tp, 0x16, 0x0000);
1787
1788         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1789             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1790                 /* Set Extended packet length bit for jumbo frames */
1791                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1792         }
1793         else {
1794                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1795         }
1796
1797         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1798
1799         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1800                 reg32 &= ~0x3000;
1801                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1802         } else if (!err)
1803                 err = -EBUSY;
1804
1805         return err;
1806 }
1807
1808 /* This will reset the tigon3 PHY if there is no valid
1809  * link unless the FORCE argument is non-zero.
1810  */
1811 static int tg3_phy_reset(struct tg3 *tp)
1812 {
1813         u32 cpmuctrl;
1814         u32 phy_status;
1815         int err;
1816
1817         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1818                 u32 val;
1819
1820                 val = tr32(GRC_MISC_CFG);
1821                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1822                 udelay(40);
1823         }
1824         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1825         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1826         if (err != 0)
1827                 return -EBUSY;
1828
1829         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1830                 netif_carrier_off(tp->dev);
1831                 tg3_link_report(tp);
1832         }
1833
1834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1835             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1836             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1837                 err = tg3_phy_reset_5703_4_5(tp);
1838                 if (err)
1839                         return err;
1840                 goto out;
1841         }
1842
1843         cpmuctrl = 0;
1844         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1845             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1846                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1847                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1848                         tw32(TG3_CPMU_CTRL,
1849                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1850         }
1851
1852         err = tg3_bmcr_reset(tp);
1853         if (err)
1854                 return err;
1855
1856         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1857                 u32 phy;
1858
1859                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1860                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1861
1862                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1863         }
1864
1865         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1866             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1867                 u32 val;
1868
1869                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1870                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1871                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1872                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1873                         udelay(40);
1874                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1875                 }
1876         }
1877
1878         tg3_phy_apply_otp(tp);
1879
1880         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1881                 tg3_phy_toggle_apd(tp, true);
1882         else
1883                 tg3_phy_toggle_apd(tp, false);
1884
1885 out:
1886         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1887                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1889                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1890                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1891                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1892                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1893         }
1894         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1895                 tg3_writephy(tp, 0x1c, 0x8d68);
1896                 tg3_writephy(tp, 0x1c, 0x8d68);
1897         }
1898         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1900                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1901                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1902                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1903                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1904                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1905                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1906                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1907         }
1908         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1909                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1911                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1912                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1913                         tg3_writephy(tp, MII_TG3_TEST1,
1914                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1915                 } else
1916                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1917                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1918         }
1919         /* Set Extended packet length bit (bit 14) on all chips that */
1920         /* support jumbo frames */
1921         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1922                 /* Cannot do read-modify-write on 5401 */
1923                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1924         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1925                 u32 phy_reg;
1926
1927                 /* Set bit 14 with read-modify-write to preserve other bits */
1928                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1929                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1930                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1931         }
1932
1933         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1934          * jumbo frames transmission.
1935          */
1936         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1937                 u32 phy_reg;
1938
1939                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1940                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1941                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1942         }
1943
1944         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1945                 /* adjust output voltage */
1946                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1947         }
1948
1949         tg3_phy_toggle_automdix(tp, 1);
1950         tg3_phy_set_wirespeed(tp);
1951         return 0;
1952 }
1953
1954 static void tg3_frob_aux_power(struct tg3 *tp)
1955 {
1956         struct tg3 *tp_peer = tp;
1957
1958         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1959                 return;
1960
1961         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1962             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1963                 struct net_device *dev_peer;
1964
1965                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1966                 /* remove_one() may have been run on the peer. */
1967                 if (!dev_peer)
1968                         tp_peer = tp;
1969                 else
1970                         tp_peer = netdev_priv(dev_peer);
1971         }
1972
1973         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1974             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1975             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1976             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1977                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1978                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1979                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1980                                     (GRC_LCLCTRL_GPIO_OE0 |
1981                                      GRC_LCLCTRL_GPIO_OE1 |
1982                                      GRC_LCLCTRL_GPIO_OE2 |
1983                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1984                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1985                                     100);
1986                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1987                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1988                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1989                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1990                                              GRC_LCLCTRL_GPIO_OE1 |
1991                                              GRC_LCLCTRL_GPIO_OE2 |
1992                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1993                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1994                                              tp->grc_local_ctrl;
1995                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1996
1997                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1998                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1999
2000                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2001                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2002                 } else {
2003                         u32 no_gpio2;
2004                         u32 grc_local_ctrl = 0;
2005
2006                         if (tp_peer != tp &&
2007                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2008                                 return;
2009
2010                         /* Workaround to prevent overdrawing Amps. */
2011                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2012                             ASIC_REV_5714) {
2013                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2014                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2015                                             grc_local_ctrl, 100);
2016                         }
2017
2018                         /* On 5753 and variants, GPIO2 cannot be used. */
2019                         no_gpio2 = tp->nic_sram_data_cfg &
2020                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2021
2022                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2023                                          GRC_LCLCTRL_GPIO_OE1 |
2024                                          GRC_LCLCTRL_GPIO_OE2 |
2025                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2026                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2027                         if (no_gpio2) {
2028                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2029                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2030                         }
2031                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2032                                                     grc_local_ctrl, 100);
2033
2034                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2035
2036                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2037                                                     grc_local_ctrl, 100);
2038
2039                         if (!no_gpio2) {
2040                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2041                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042                                             grc_local_ctrl, 100);
2043                         }
2044                 }
2045         } else {
2046                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2047                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2048                         if (tp_peer != tp &&
2049                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2050                                 return;
2051
2052                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2053                                     (GRC_LCLCTRL_GPIO_OE1 |
2054                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2055
2056                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2057                                     GRC_LCLCTRL_GPIO_OE1, 100);
2058
2059                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060                                     (GRC_LCLCTRL_GPIO_OE1 |
2061                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2062                 }
2063         }
2064 }
2065
2066 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2067 {
2068         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2069                 return 1;
2070         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2071                 if (speed != SPEED_10)
2072                         return 1;
2073         } else if (speed == SPEED_10)
2074                 return 1;
2075
2076         return 0;
2077 }
2078
2079 static int tg3_setup_phy(struct tg3 *, int);
2080
2081 #define RESET_KIND_SHUTDOWN     0
2082 #define RESET_KIND_INIT         1
2083 #define RESET_KIND_SUSPEND      2
2084
2085 static void tg3_write_sig_post_reset(struct tg3 *, int);
2086 static int tg3_halt_cpu(struct tg3 *, u32);
2087
2088 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2089 {
2090         u32 val;
2091
2092         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2094                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2095                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2096
2097                         sg_dig_ctrl |=
2098                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2099                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2100                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2101                 }
2102                 return;
2103         }
2104
2105         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2106                 tg3_bmcr_reset(tp);
2107                 val = tr32(GRC_MISC_CFG);
2108                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2109                 udelay(40);
2110                 return;
2111         } else if (do_low_power) {
2112                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2113                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2114
2115                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2116                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2117                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2118                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2119                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2120         }
2121
2122         /* The PHY should not be powered down on some chips because
2123          * of bugs.
2124          */
2125         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2126             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2127             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2128              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2129                 return;
2130
2131         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2132             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2133                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2134                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2135                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2136                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2137         }
2138
2139         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2140 }
2141
2142 /* tp->lock is held. */
2143 static int tg3_nvram_lock(struct tg3 *tp)
2144 {
2145         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2146                 int i;
2147
2148                 if (tp->nvram_lock_cnt == 0) {
2149                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2150                         for (i = 0; i < 8000; i++) {
2151                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2152                                         break;
2153                                 udelay(20);
2154                         }
2155                         if (i == 8000) {
2156                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2157                                 return -ENODEV;
2158                         }
2159                 }
2160                 tp->nvram_lock_cnt++;
2161         }
2162         return 0;
2163 }
2164
2165 /* tp->lock is held. */
2166 static void tg3_nvram_unlock(struct tg3 *tp)
2167 {
2168         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2169                 if (tp->nvram_lock_cnt > 0)
2170                         tp->nvram_lock_cnt--;
2171                 if (tp->nvram_lock_cnt == 0)
2172                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2173         }
2174 }
2175
2176 /* tp->lock is held. */
2177 static void tg3_enable_nvram_access(struct tg3 *tp)
2178 {
2179         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2180             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2181                 u32 nvaccess = tr32(NVRAM_ACCESS);
2182
2183                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2184         }
2185 }
2186
2187 /* tp->lock is held. */
2188 static void tg3_disable_nvram_access(struct tg3 *tp)
2189 {
2190         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2191             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2192                 u32 nvaccess = tr32(NVRAM_ACCESS);
2193
2194                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2195         }
2196 }
2197
2198 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2199                                         u32 offset, u32 *val)
2200 {
2201         u32 tmp;
2202         int i;
2203
2204         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2205                 return -EINVAL;
2206
2207         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2208                                         EEPROM_ADDR_DEVID_MASK |
2209                                         EEPROM_ADDR_READ);
2210         tw32(GRC_EEPROM_ADDR,
2211              tmp |
2212              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2213              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2214               EEPROM_ADDR_ADDR_MASK) |
2215              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2216
2217         for (i = 0; i < 1000; i++) {
2218                 tmp = tr32(GRC_EEPROM_ADDR);
2219
2220                 if (tmp & EEPROM_ADDR_COMPLETE)
2221                         break;
2222                 msleep(1);
2223         }
2224         if (!(tmp & EEPROM_ADDR_COMPLETE))
2225                 return -EBUSY;
2226
2227         tmp = tr32(GRC_EEPROM_DATA);
2228
2229         /*
2230          * The data will always be opposite the native endian
2231          * format.  Perform a blind byteswap to compensate.
2232          */
2233         *val = swab32(tmp);
2234
2235         return 0;
2236 }
2237
2238 #define NVRAM_CMD_TIMEOUT 10000
2239
2240 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2241 {
2242         int i;
2243
2244         tw32(NVRAM_CMD, nvram_cmd);
2245         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2246                 udelay(10);
2247                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2248                         udelay(10);
2249                         break;
2250                 }
2251         }
2252
2253         if (i == NVRAM_CMD_TIMEOUT)
2254                 return -EBUSY;
2255
2256         return 0;
2257 }
2258
2259 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2260 {
2261         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2262             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2263             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2264            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2265             (tp->nvram_jedecnum == JEDEC_ATMEL))
2266
2267                 addr = ((addr / tp->nvram_pagesize) <<
2268                         ATMEL_AT45DB0X1B_PAGE_POS) +
2269                        (addr % tp->nvram_pagesize);
2270
2271         return addr;
2272 }
2273
2274 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2275 {
2276         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2277             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2278             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2279            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2280             (tp->nvram_jedecnum == JEDEC_ATMEL))
2281
2282                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2283                         tp->nvram_pagesize) +
2284                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2285
2286         return addr;
2287 }
2288
2289 /* NOTE: Data read in from NVRAM is byteswapped according to
2290  * the byteswapping settings for all other register accesses.
2291  * tg3 devices are BE devices, so on a BE machine, the data
2292  * returned will be exactly as it is seen in NVRAM.  On a LE
2293  * machine, the 32-bit value will be byteswapped.
2294  */
2295 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2296 {
2297         int ret;
2298
2299         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2300                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2301
2302         offset = tg3_nvram_phys_addr(tp, offset);
2303
2304         if (offset > NVRAM_ADDR_MSK)
2305                 return -EINVAL;
2306
2307         ret = tg3_nvram_lock(tp);
2308         if (ret)
2309                 return ret;
2310
2311         tg3_enable_nvram_access(tp);
2312
2313         tw32(NVRAM_ADDR, offset);
2314         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2315                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2316
2317         if (ret == 0)
2318                 *val = tr32(NVRAM_RDDATA);
2319
2320         tg3_disable_nvram_access(tp);
2321
2322         tg3_nvram_unlock(tp);
2323
2324         return ret;
2325 }
2326
2327 /* Ensures NVRAM data is in bytestream format. */
2328 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2329 {
2330         u32 v;
2331         int res = tg3_nvram_read(tp, offset, &v);
2332         if (!res)
2333                 *val = cpu_to_be32(v);
2334         return res;
2335 }
2336
2337 /* tp->lock is held. */
2338 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2339 {
2340         u32 addr_high, addr_low;
2341         int i;
2342
2343         addr_high = ((tp->dev->dev_addr[0] << 8) |
2344                      tp->dev->dev_addr[1]);
2345         addr_low = ((tp->dev->dev_addr[2] << 24) |
2346                     (tp->dev->dev_addr[3] << 16) |
2347                     (tp->dev->dev_addr[4] <<  8) |
2348                     (tp->dev->dev_addr[5] <<  0));
2349         for (i = 0; i < 4; i++) {
2350                 if (i == 1 && skip_mac_1)
2351                         continue;
2352                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2353                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2354         }
2355
2356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2357             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2358                 for (i = 0; i < 12; i++) {
2359                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2360                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2361                 }
2362         }
2363
2364         addr_high = (tp->dev->dev_addr[0] +
2365                      tp->dev->dev_addr[1] +
2366                      tp->dev->dev_addr[2] +
2367                      tp->dev->dev_addr[3] +
2368                      tp->dev->dev_addr[4] +
2369                      tp->dev->dev_addr[5]) &
2370                 TX_BACKOFF_SEED_MASK;
2371         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2372 }
2373
2374 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2375 {
2376         u32 misc_host_ctrl;
2377         bool device_should_wake, do_low_power;
2378
2379         /* Make sure register accesses (indirect or otherwise)
2380          * will function correctly.
2381          */
2382         pci_write_config_dword(tp->pdev,
2383                                TG3PCI_MISC_HOST_CTRL,
2384                                tp->misc_host_ctrl);
2385
2386         switch (state) {
2387         case PCI_D0:
2388                 pci_enable_wake(tp->pdev, state, false);
2389                 pci_set_power_state(tp->pdev, PCI_D0);
2390
2391                 /* Switch out of Vaux if it is a NIC */
2392                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2393                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2394
2395                 return 0;
2396
2397         case PCI_D1:
2398         case PCI_D2:
2399         case PCI_D3hot:
2400                 break;
2401
2402         default:
2403                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2404                         tp->dev->name, state);
2405                 return -EINVAL;
2406         }
2407
2408         /* Restore the CLKREQ setting. */
2409         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2410                 u16 lnkctl;
2411
2412                 pci_read_config_word(tp->pdev,
2413                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2414                                      &lnkctl);
2415                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2416                 pci_write_config_word(tp->pdev,
2417                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2418                                       lnkctl);
2419         }
2420
2421         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2422         tw32(TG3PCI_MISC_HOST_CTRL,
2423              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2424
2425         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2426                              device_may_wakeup(&tp->pdev->dev) &&
2427                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2428
2429         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2430                 do_low_power = false;
2431                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2432                     !tp->link_config.phy_is_low_power) {
2433                         struct phy_device *phydev;
2434                         u32 phyid, advertising;
2435
2436                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2437
2438                         tp->link_config.phy_is_low_power = 1;
2439
2440                         tp->link_config.orig_speed = phydev->speed;
2441                         tp->link_config.orig_duplex = phydev->duplex;
2442                         tp->link_config.orig_autoneg = phydev->autoneg;
2443                         tp->link_config.orig_advertising = phydev->advertising;
2444
2445                         advertising = ADVERTISED_TP |
2446                                       ADVERTISED_Pause |
2447                                       ADVERTISED_Autoneg |
2448                                       ADVERTISED_10baseT_Half;
2449
2450                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2451                             device_should_wake) {
2452                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2453                                         advertising |=
2454                                                 ADVERTISED_100baseT_Half |
2455                                                 ADVERTISED_100baseT_Full |
2456                                                 ADVERTISED_10baseT_Full;
2457                                 else
2458                                         advertising |= ADVERTISED_10baseT_Full;
2459                         }
2460
2461                         phydev->advertising = advertising;
2462
2463                         phy_start_aneg(phydev);
2464
2465                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2466                         if (phyid != TG3_PHY_ID_BCMAC131) {
2467                                 phyid &= TG3_PHY_OUI_MASK;
2468                                 if (phyid == TG3_PHY_OUI_1 ||
2469                                     phyid == TG3_PHY_OUI_2 ||
2470                                     phyid == TG3_PHY_OUI_3)
2471                                         do_low_power = true;
2472                         }
2473                 }
2474         } else {
2475                 do_low_power = true;
2476
2477                 if (tp->link_config.phy_is_low_power == 0) {
2478                         tp->link_config.phy_is_low_power = 1;
2479                         tp->link_config.orig_speed = tp->link_config.speed;
2480                         tp->link_config.orig_duplex = tp->link_config.duplex;
2481                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2482                 }
2483
2484                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2485                         tp->link_config.speed = SPEED_10;
2486                         tp->link_config.duplex = DUPLEX_HALF;
2487                         tp->link_config.autoneg = AUTONEG_ENABLE;
2488                         tg3_setup_phy(tp, 0);
2489                 }
2490         }
2491
2492         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2493                 u32 val;
2494
2495                 val = tr32(GRC_VCPU_EXT_CTRL);
2496                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2497         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2498                 int i;
2499                 u32 val;
2500
2501                 for (i = 0; i < 200; i++) {
2502                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2503                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2504                                 break;
2505                         msleep(1);
2506                 }
2507         }
2508         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2509                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2510                                                      WOL_DRV_STATE_SHUTDOWN |
2511                                                      WOL_DRV_WOL |
2512                                                      WOL_SET_MAGIC_PKT);
2513
2514         if (device_should_wake) {
2515                 u32 mac_mode;
2516
2517                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2518                         if (do_low_power) {
2519                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2520                                 udelay(40);
2521                         }
2522
2523                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2524                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2525                         else
2526                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2527
2528                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2529                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2530                             ASIC_REV_5700) {
2531                                 u32 speed = (tp->tg3_flags &
2532                                              TG3_FLAG_WOL_SPEED_100MB) ?
2533                                              SPEED_100 : SPEED_10;
2534                                 if (tg3_5700_link_polarity(tp, speed))
2535                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2536                                 else
2537                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2538                         }
2539                 } else {
2540                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2541                 }
2542
2543                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2544                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2545
2546                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2547                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2548                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2549                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2550                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2551                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2552
2553                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2554                         mac_mode |= tp->mac_mode &
2555                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2556                         if (mac_mode & MAC_MODE_APE_TX_EN)
2557                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2558                 }
2559
2560                 tw32_f(MAC_MODE, mac_mode);
2561                 udelay(100);
2562
2563                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2564                 udelay(10);
2565         }
2566
2567         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2568             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2569              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2570                 u32 base_val;
2571
2572                 base_val = tp->pci_clock_ctrl;
2573                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2574                              CLOCK_CTRL_TXCLK_DISABLE);
2575
2576                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2577                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2578         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2579                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2580                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2581                 /* do nothing */
2582         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2583                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2584                 u32 newbits1, newbits2;
2585
2586                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2587                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2588                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2589                                     CLOCK_CTRL_TXCLK_DISABLE |
2590                                     CLOCK_CTRL_ALTCLK);
2591                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2592                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2593                         newbits1 = CLOCK_CTRL_625_CORE;
2594                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2595                 } else {
2596                         newbits1 = CLOCK_CTRL_ALTCLK;
2597                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2598                 }
2599
2600                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2601                             40);
2602
2603                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2604                             40);
2605
2606                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2607                         u32 newbits3;
2608
2609                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2610                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2611                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2612                                             CLOCK_CTRL_TXCLK_DISABLE |
2613                                             CLOCK_CTRL_44MHZ_CORE);
2614                         } else {
2615                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2616                         }
2617
2618                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2619                                     tp->pci_clock_ctrl | newbits3, 40);
2620                 }
2621         }
2622
2623         if (!(device_should_wake) &&
2624             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2625                 tg3_power_down_phy(tp, do_low_power);
2626
2627         tg3_frob_aux_power(tp);
2628
2629         /* Workaround for unstable PLL clock */
2630         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2631             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2632                 u32 val = tr32(0x7d00);
2633
2634                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2635                 tw32(0x7d00, val);
2636                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2637                         int err;
2638
2639                         err = tg3_nvram_lock(tp);
2640                         tg3_halt_cpu(tp, RX_CPU_BASE);
2641                         if (!err)
2642                                 tg3_nvram_unlock(tp);
2643                 }
2644         }
2645
2646         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2647
2648         if (device_should_wake)
2649                 pci_enable_wake(tp->pdev, state, true);
2650
2651         /* Finally, set the new power state. */
2652         pci_set_power_state(tp->pdev, state);
2653
2654         return 0;
2655 }
2656
2657 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2658 {
2659         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2660         case MII_TG3_AUX_STAT_10HALF:
2661                 *speed = SPEED_10;
2662                 *duplex = DUPLEX_HALF;
2663                 break;
2664
2665         case MII_TG3_AUX_STAT_10FULL:
2666                 *speed = SPEED_10;
2667                 *duplex = DUPLEX_FULL;
2668                 break;
2669
2670         case MII_TG3_AUX_STAT_100HALF:
2671                 *speed = SPEED_100;
2672                 *duplex = DUPLEX_HALF;
2673                 break;
2674
2675         case MII_TG3_AUX_STAT_100FULL:
2676                 *speed = SPEED_100;
2677                 *duplex = DUPLEX_FULL;
2678                 break;
2679
2680         case MII_TG3_AUX_STAT_1000HALF:
2681                 *speed = SPEED_1000;
2682                 *duplex = DUPLEX_HALF;
2683                 break;
2684
2685         case MII_TG3_AUX_STAT_1000FULL:
2686                 *speed = SPEED_1000;
2687                 *duplex = DUPLEX_FULL;
2688                 break;
2689
2690         default:
2691                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2692                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2693                                  SPEED_10;
2694                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2695                                   DUPLEX_HALF;
2696                         break;
2697                 }
2698                 *speed = SPEED_INVALID;
2699                 *duplex = DUPLEX_INVALID;
2700                 break;
2701         }
2702 }
2703
2704 static void tg3_phy_copper_begin(struct tg3 *tp)
2705 {
2706         u32 new_adv;
2707         int i;
2708
2709         if (tp->link_config.phy_is_low_power) {
2710                 /* Entering low power mode.  Disable gigabit and
2711                  * 100baseT advertisements.
2712                  */
2713                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2714
2715                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2716                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2717                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2718                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2719
2720                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2721         } else if (tp->link_config.speed == SPEED_INVALID) {
2722                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2723                         tp->link_config.advertising &=
2724                                 ~(ADVERTISED_1000baseT_Half |
2725                                   ADVERTISED_1000baseT_Full);
2726
2727                 new_adv = ADVERTISE_CSMA;
2728                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2729                         new_adv |= ADVERTISE_10HALF;
2730                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2731                         new_adv |= ADVERTISE_10FULL;
2732                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2733                         new_adv |= ADVERTISE_100HALF;
2734                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2735                         new_adv |= ADVERTISE_100FULL;
2736
2737                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2738
2739                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2740
2741                 if (tp->link_config.advertising &
2742                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2743                         new_adv = 0;
2744                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2745                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2746                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2747                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2748                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2749                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2750                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2751                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2752                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2753                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2754                 } else {
2755                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2756                 }
2757         } else {
2758                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2759                 new_adv |= ADVERTISE_CSMA;
2760
2761                 /* Asking for a specific link mode. */
2762                 if (tp->link_config.speed == SPEED_1000) {
2763                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2764
2765                         if (tp->link_config.duplex == DUPLEX_FULL)
2766                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2767                         else
2768                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2769                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2770                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2771                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2772                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2773                 } else {
2774                         if (tp->link_config.speed == SPEED_100) {
2775                                 if (tp->link_config.duplex == DUPLEX_FULL)
2776                                         new_adv |= ADVERTISE_100FULL;
2777                                 else
2778                                         new_adv |= ADVERTISE_100HALF;
2779                         } else {
2780                                 if (tp->link_config.duplex == DUPLEX_FULL)
2781                                         new_adv |= ADVERTISE_10FULL;
2782                                 else
2783                                         new_adv |= ADVERTISE_10HALF;
2784                         }
2785                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2786
2787                         new_adv = 0;
2788                 }
2789
2790                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2791         }
2792
2793         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2794             tp->link_config.speed != SPEED_INVALID) {
2795                 u32 bmcr, orig_bmcr;
2796
2797                 tp->link_config.active_speed = tp->link_config.speed;
2798                 tp->link_config.active_duplex = tp->link_config.duplex;
2799
2800                 bmcr = 0;
2801                 switch (tp->link_config.speed) {
2802                 default:
2803                 case SPEED_10:
2804                         break;
2805
2806                 case SPEED_100:
2807                         bmcr |= BMCR_SPEED100;
2808                         break;
2809
2810                 case SPEED_1000:
2811                         bmcr |= TG3_BMCR_SPEED1000;
2812                         break;
2813                 }
2814
2815                 if (tp->link_config.duplex == DUPLEX_FULL)
2816                         bmcr |= BMCR_FULLDPLX;
2817
2818                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2819                     (bmcr != orig_bmcr)) {
2820                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2821                         for (i = 0; i < 1500; i++) {
2822                                 u32 tmp;
2823
2824                                 udelay(10);
2825                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2826                                     tg3_readphy(tp, MII_BMSR, &tmp))
2827                                         continue;
2828                                 if (!(tmp & BMSR_LSTATUS)) {
2829                                         udelay(40);
2830                                         break;
2831                                 }
2832                         }
2833                         tg3_writephy(tp, MII_BMCR, bmcr);
2834                         udelay(40);
2835                 }
2836         } else {
2837                 tg3_writephy(tp, MII_BMCR,
2838                              BMCR_ANENABLE | BMCR_ANRESTART);
2839         }
2840 }
2841
2842 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2843 {
2844         int err;
2845
2846         /* Turn off tap power management. */
2847         /* Set Extended packet length bit */
2848         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2849
2850         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2851         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2852
2853         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2854         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2855
2856         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2857         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2858
2859         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2860         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2861
2862         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2863         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2864
2865         udelay(40);
2866
2867         return err;
2868 }
2869
2870 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2871 {
2872         u32 adv_reg, all_mask = 0;
2873
2874         if (mask & ADVERTISED_10baseT_Half)
2875                 all_mask |= ADVERTISE_10HALF;
2876         if (mask & ADVERTISED_10baseT_Full)
2877                 all_mask |= ADVERTISE_10FULL;
2878         if (mask & ADVERTISED_100baseT_Half)
2879                 all_mask |= ADVERTISE_100HALF;
2880         if (mask & ADVERTISED_100baseT_Full)
2881                 all_mask |= ADVERTISE_100FULL;
2882
2883         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2884                 return 0;
2885
2886         if ((adv_reg & all_mask) != all_mask)
2887                 return 0;
2888         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2889                 u32 tg3_ctrl;
2890
2891                 all_mask = 0;
2892                 if (mask & ADVERTISED_1000baseT_Half)
2893                         all_mask |= ADVERTISE_1000HALF;
2894                 if (mask & ADVERTISED_1000baseT_Full)
2895                         all_mask |= ADVERTISE_1000FULL;
2896
2897                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2898                         return 0;
2899
2900                 if ((tg3_ctrl & all_mask) != all_mask)
2901                         return 0;
2902         }
2903         return 1;
2904 }
2905
2906 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2907 {
2908         u32 curadv, reqadv;
2909
2910         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2911                 return 1;
2912
2913         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2914         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2915
2916         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2917                 if (curadv != reqadv)
2918                         return 0;
2919
2920                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2921                         tg3_readphy(tp, MII_LPA, rmtadv);
2922         } else {
2923                 /* Reprogram the advertisement register, even if it
2924                  * does not affect the current link.  If the link
2925                  * gets renegotiated in the future, we can save an
2926                  * additional renegotiation cycle by advertising
2927                  * it correctly in the first place.
2928                  */
2929                 if (curadv != reqadv) {
2930                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2931                                      ADVERTISE_PAUSE_ASYM);
2932                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2933                 }
2934         }
2935
2936         return 1;
2937 }
2938
2939 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2940 {
2941         int current_link_up;
2942         u32 bmsr, dummy;
2943         u32 lcl_adv, rmt_adv;
2944         u16 current_speed;
2945         u8 current_duplex;
2946         int i, err;
2947
2948         tw32(MAC_EVENT, 0);
2949
2950         tw32_f(MAC_STATUS,
2951              (MAC_STATUS_SYNC_CHANGED |
2952               MAC_STATUS_CFG_CHANGED |
2953               MAC_STATUS_MI_COMPLETION |
2954               MAC_STATUS_LNKSTATE_CHANGED));
2955         udelay(40);
2956
2957         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2958                 tw32_f(MAC_MI_MODE,
2959                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2960                 udelay(80);
2961         }
2962
2963         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2964
2965         /* Some third-party PHYs need to be reset on link going
2966          * down.
2967          */
2968         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2969              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2970              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2971             netif_carrier_ok(tp->dev)) {
2972                 tg3_readphy(tp, MII_BMSR, &bmsr);
2973                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2974                     !(bmsr & BMSR_LSTATUS))
2975                         force_reset = 1;
2976         }
2977         if (force_reset)
2978                 tg3_phy_reset(tp);
2979
2980         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2981                 tg3_readphy(tp, MII_BMSR, &bmsr);
2982                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2983                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2984                         bmsr = 0;
2985
2986                 if (!(bmsr & BMSR_LSTATUS)) {
2987                         err = tg3_init_5401phy_dsp(tp);
2988                         if (err)
2989                                 return err;
2990
2991                         tg3_readphy(tp, MII_BMSR, &bmsr);
2992                         for (i = 0; i < 1000; i++) {
2993                                 udelay(10);
2994                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2995                                     (bmsr & BMSR_LSTATUS)) {
2996                                         udelay(40);
2997                                         break;
2998                                 }
2999                         }
3000
3001                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3002                             !(bmsr & BMSR_LSTATUS) &&
3003                             tp->link_config.active_speed == SPEED_1000) {
3004                                 err = tg3_phy_reset(tp);
3005                                 if (!err)
3006                                         err = tg3_init_5401phy_dsp(tp);
3007                                 if (err)
3008                                         return err;
3009                         }
3010                 }
3011         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3012                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3013                 /* 5701 {A0,B0} CRC bug workaround */
3014                 tg3_writephy(tp, 0x15, 0x0a75);
3015                 tg3_writephy(tp, 0x1c, 0x8c68);
3016                 tg3_writephy(tp, 0x1c, 0x8d68);
3017                 tg3_writephy(tp, 0x1c, 0x8c68);
3018         }
3019
3020         /* Clear pending interrupts... */
3021         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3022         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3023
3024         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3025                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3026         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3027                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3028
3029         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3031                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3032                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3033                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3034                 else
3035                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3036         }
3037
3038         current_link_up = 0;
3039         current_speed = SPEED_INVALID;
3040         current_duplex = DUPLEX_INVALID;
3041
3042         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3043                 u32 val;
3044
3045                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3046                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3047                 if (!(val & (1 << 10))) {
3048                         val |= (1 << 10);
3049                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3050                         goto relink;
3051                 }
3052         }
3053
3054         bmsr = 0;
3055         for (i = 0; i < 100; i++) {
3056                 tg3_readphy(tp, MII_BMSR, &bmsr);
3057                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3058                     (bmsr & BMSR_LSTATUS))
3059                         break;
3060                 udelay(40);
3061         }
3062
3063         if (bmsr & BMSR_LSTATUS) {
3064                 u32 aux_stat, bmcr;
3065
3066                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3067                 for (i = 0; i < 2000; i++) {
3068                         udelay(10);
3069                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3070                             aux_stat)
3071                                 break;
3072                 }
3073
3074                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3075                                              &current_speed,
3076                                              &current_duplex);
3077
3078                 bmcr = 0;
3079                 for (i = 0; i < 200; i++) {
3080                         tg3_readphy(tp, MII_BMCR, &bmcr);
3081                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3082                                 continue;
3083                         if (bmcr && bmcr != 0x7fff)
3084                                 break;
3085                         udelay(10);
3086                 }
3087
3088                 lcl_adv = 0;
3089                 rmt_adv = 0;
3090
3091                 tp->link_config.active_speed = current_speed;
3092                 tp->link_config.active_duplex = current_duplex;
3093
3094                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3095                         if ((bmcr & BMCR_ANENABLE) &&
3096                             tg3_copper_is_advertising_all(tp,
3097                                                 tp->link_config.advertising)) {
3098                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3099                                                                   &rmt_adv))
3100                                         current_link_up = 1;
3101                         }
3102                 } else {
3103                         if (!(bmcr & BMCR_ANENABLE) &&
3104                             tp->link_config.speed == current_speed &&
3105                             tp->link_config.duplex == current_duplex &&
3106                             tp->link_config.flowctrl ==
3107                             tp->link_config.active_flowctrl) {
3108                                 current_link_up = 1;
3109                         }
3110                 }
3111
3112                 if (current_link_up == 1 &&
3113                     tp->link_config.active_duplex == DUPLEX_FULL)
3114                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3115         }
3116
3117 relink:
3118         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3119                 u32 tmp;
3120
3121                 tg3_phy_copper_begin(tp);
3122
3123                 tg3_readphy(tp, MII_BMSR, &tmp);
3124                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3125                     (tmp & BMSR_LSTATUS))
3126                         current_link_up = 1;
3127         }
3128
3129         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3130         if (current_link_up == 1) {
3131                 if (tp->link_config.active_speed == SPEED_100 ||
3132                     tp->link_config.active_speed == SPEED_10)
3133                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3134                 else
3135                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3136         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3137                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3138         else
3139                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3140
3141         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3142         if (tp->link_config.active_duplex == DUPLEX_HALF)
3143                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3144
3145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3146                 if (current_link_up == 1 &&
3147                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3148                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3149                 else
3150                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3151         }
3152
3153         /* ??? Without this setting Netgear GA302T PHY does not
3154          * ??? send/receive packets...
3155          */
3156         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3157             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3158                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3159                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3160                 udelay(80);
3161         }
3162
3163         tw32_f(MAC_MODE, tp->mac_mode);
3164         udelay(40);
3165
3166         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3167                 /* Polled via timer. */
3168                 tw32_f(MAC_EVENT, 0);
3169         } else {
3170                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3171         }
3172         udelay(40);
3173
3174         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3175             current_link_up == 1 &&
3176             tp->link_config.active_speed == SPEED_1000 &&
3177             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3178              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3179                 udelay(120);
3180                 tw32_f(MAC_STATUS,
3181                      (MAC_STATUS_SYNC_CHANGED |
3182                       MAC_STATUS_CFG_CHANGED));
3183                 udelay(40);
3184                 tg3_write_mem(tp,
3185                               NIC_SRAM_FIRMWARE_MBOX,
3186                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3187         }
3188
3189         /* Prevent send BD corruption. */
3190         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3191                 u16 oldlnkctl, newlnkctl;
3192
3193                 pci_read_config_word(tp->pdev,
3194                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3195                                      &oldlnkctl);
3196                 if (tp->link_config.active_speed == SPEED_100 ||
3197                     tp->link_config.active_speed == SPEED_10)
3198                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3199                 else
3200                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3201                 if (newlnkctl != oldlnkctl)
3202                         pci_write_config_word(tp->pdev,
3203                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3204                                               newlnkctl);
3205         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3206                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3207                 if (tp->link_config.active_speed == SPEED_100 ||
3208                     tp->link_config.active_speed == SPEED_10)
3209                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3210                 else
3211                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3212                 if (newreg != oldreg)
3213                         tw32(TG3_PCIE_LNKCTL, newreg);
3214         }
3215
3216         if (current_link_up != netif_carrier_ok(tp->dev)) {
3217                 if (current_link_up)
3218                         netif_carrier_on(tp->dev);
3219                 else
3220                         netif_carrier_off(tp->dev);
3221                 tg3_link_report(tp);
3222         }
3223
3224         return 0;
3225 }
3226
3227 struct tg3_fiber_aneginfo {
3228         int state;
3229 #define ANEG_STATE_UNKNOWN              0
3230 #define ANEG_STATE_AN_ENABLE            1
3231 #define ANEG_STATE_RESTART_INIT         2
3232 #define ANEG_STATE_RESTART              3
3233 #define ANEG_STATE_DISABLE_LINK_OK      4
3234 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3235 #define ANEG_STATE_ABILITY_DETECT       6
3236 #define ANEG_STATE_ACK_DETECT_INIT      7
3237 #define ANEG_STATE_ACK_DETECT           8
3238 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3239 #define ANEG_STATE_COMPLETE_ACK         10
3240 #define ANEG_STATE_IDLE_DETECT_INIT     11
3241 #define ANEG_STATE_IDLE_DETECT          12
3242 #define ANEG_STATE_LINK_OK              13
3243 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3244 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3245
3246         u32 flags;
3247 #define MR_AN_ENABLE            0x00000001
3248 #define MR_RESTART_AN           0x00000002
3249 #define MR_AN_COMPLETE          0x00000004
3250 #define MR_PAGE_RX              0x00000008
3251 #define MR_NP_LOADED            0x00000010
3252 #define MR_TOGGLE_TX            0x00000020
3253 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3254 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3255 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3256 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3257 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3258 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3259 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3260 #define MR_TOGGLE_RX            0x00002000
3261 #define MR_NP_RX                0x00004000
3262
3263 #define MR_LINK_OK              0x80000000
3264
3265         unsigned long link_time, cur_time;
3266
3267         u32 ability_match_cfg;
3268         int ability_match_count;
3269
3270         char ability_match, idle_match, ack_match;
3271
3272         u32 txconfig, rxconfig;
3273 #define ANEG_CFG_NP             0x00000080
3274 #define ANEG_CFG_ACK            0x00000040
3275 #define ANEG_CFG_RF2            0x00000020
3276 #define ANEG_CFG_RF1            0x00000010
3277 #define ANEG_CFG_PS2            0x00000001
3278 #define ANEG_CFG_PS1            0x00008000
3279 #define ANEG_CFG_HD             0x00004000
3280 #define ANEG_CFG_FD             0x00002000
3281 #define ANEG_CFG_INVAL          0x00001f06
3282
3283 };
3284 #define ANEG_OK         0
3285 #define ANEG_DONE       1
3286 #define ANEG_TIMER_ENAB 2
3287 #define ANEG_FAILED     -1
3288
3289 #define ANEG_STATE_SETTLE_TIME  10000
3290
3291 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3292                                    struct tg3_fiber_aneginfo *ap)
3293 {
3294         u16 flowctrl;
3295         unsigned long delta;
3296         u32 rx_cfg_reg;
3297         int ret;
3298
3299         if (ap->state == ANEG_STATE_UNKNOWN) {
3300                 ap->rxconfig = 0;
3301                 ap->link_time = 0;
3302                 ap->cur_time = 0;
3303                 ap->ability_match_cfg = 0;
3304                 ap->ability_match_count = 0;
3305                 ap->ability_match = 0;
3306                 ap->idle_match = 0;
3307                 ap->ack_match = 0;
3308         }
3309         ap->cur_time++;
3310
3311         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3312                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3313
3314                 if (rx_cfg_reg != ap->ability_match_cfg) {
3315                         ap->ability_match_cfg = rx_cfg_reg;
3316                         ap->ability_match = 0;
3317                         ap->ability_match_count = 0;
3318                 } else {
3319                         if (++ap->ability_match_count > 1) {
3320                                 ap->ability_match = 1;
3321                                 ap->ability_match_cfg = rx_cfg_reg;
3322                         }
3323                 }
3324                 if (rx_cfg_reg & ANEG_CFG_ACK)
3325                         ap->ack_match = 1;
3326                 else
3327                         ap->ack_match = 0;
3328
3329                 ap->idle_match = 0;
3330         } else {
3331                 ap->idle_match = 1;
3332                 ap->ability_match_cfg = 0;
3333                 ap->ability_match_count = 0;
3334                 ap->ability_match = 0;
3335                 ap->ack_match = 0;
3336
3337                 rx_cfg_reg = 0;
3338         }
3339
3340         ap->rxconfig = rx_cfg_reg;
3341         ret = ANEG_OK;
3342
3343         switch(ap->state) {
3344         case ANEG_STATE_UNKNOWN:
3345                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3346                         ap->state = ANEG_STATE_AN_ENABLE;
3347
3348                 /* fallthru */
3349         case ANEG_STATE_AN_ENABLE:
3350                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3351                 if (ap->flags & MR_AN_ENABLE) {
3352                         ap->link_time = 0;
3353                         ap->cur_time = 0;
3354                         ap->ability_match_cfg = 0;
3355                         ap->ability_match_count = 0;
3356                         ap->ability_match = 0;
3357                         ap->idle_match = 0;
3358                         ap->ack_match = 0;
3359
3360                         ap->state = ANEG_STATE_RESTART_INIT;
3361                 } else {
3362                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3363                 }
3364                 break;
3365
3366         case ANEG_STATE_RESTART_INIT:
3367                 ap->link_time = ap->cur_time;
3368                 ap->flags &= ~(MR_NP_LOADED);
3369                 ap->txconfig = 0;
3370                 tw32(MAC_TX_AUTO_NEG, 0);
3371                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3372                 tw32_f(MAC_MODE, tp->mac_mode);
3373                 udelay(40);
3374
3375                 ret = ANEG_TIMER_ENAB;
3376                 ap->state = ANEG_STATE_RESTART;
3377
3378                 /* fallthru */
3379         case ANEG_STATE_RESTART:
3380                 delta = ap->cur_time - ap->link_time;
3381                 if (delta > ANEG_STATE_SETTLE_TIME) {
3382                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3383                 } else {
3384                         ret = ANEG_TIMER_ENAB;
3385                 }
3386                 break;
3387
3388         case ANEG_STATE_DISABLE_LINK_OK:
3389                 ret = ANEG_DONE;
3390                 break;
3391
3392         case ANEG_STATE_ABILITY_DETECT_INIT:
3393                 ap->flags &= ~(MR_TOGGLE_TX);
3394                 ap->txconfig = ANEG_CFG_FD;
3395                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3396                 if (flowctrl & ADVERTISE_1000XPAUSE)
3397                         ap->txconfig |= ANEG_CFG_PS1;
3398                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3399                         ap->txconfig |= ANEG_CFG_PS2;
3400                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3401                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3402                 tw32_f(MAC_MODE, tp->mac_mode);
3403                 udelay(40);
3404
3405                 ap->state = ANEG_STATE_ABILITY_DETECT;
3406                 break;
3407
3408         case ANEG_STATE_ABILITY_DETECT:
3409                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3410                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3411                 }
3412                 break;
3413
3414         case ANEG_STATE_ACK_DETECT_INIT:
3415                 ap->txconfig |= ANEG_CFG_ACK;
3416                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3417                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3418                 tw32_f(MAC_MODE, tp->mac_mode);
3419                 udelay(40);
3420
3421                 ap->state = ANEG_STATE_ACK_DETECT;
3422
3423                 /* fallthru */
3424         case ANEG_STATE_ACK_DETECT:
3425                 if (ap->ack_match != 0) {
3426                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3427                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3428                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3429                         } else {
3430                                 ap->state = ANEG_STATE_AN_ENABLE;
3431                         }
3432                 } else if (ap->ability_match != 0 &&
3433                            ap->rxconfig == 0) {
3434                         ap->state = ANEG_STATE_AN_ENABLE;
3435                 }
3436                 break;
3437
3438         case ANEG_STATE_COMPLETE_ACK_INIT:
3439                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3440                         ret = ANEG_FAILED;
3441                         break;
3442                 }
3443                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3444                                MR_LP_ADV_HALF_DUPLEX |
3445                                MR_LP_ADV_SYM_PAUSE |
3446                                MR_LP_ADV_ASYM_PAUSE |
3447                                MR_LP_ADV_REMOTE_FAULT1 |
3448                                MR_LP_ADV_REMOTE_FAULT2 |
3449                                MR_LP_ADV_NEXT_PAGE |
3450                                MR_TOGGLE_RX |
3451                                MR_NP_RX);
3452                 if (ap->rxconfig & ANEG_CFG_FD)
3453                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3454                 if (ap->rxconfig & ANEG_CFG_HD)
3455                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3456                 if (ap->rxconfig & ANEG_CFG_PS1)
3457                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3458                 if (ap->rxconfig & ANEG_CFG_PS2)
3459                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3460                 if (ap->rxconfig & ANEG_CFG_RF1)
3461                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3462                 if (ap->rxconfig & ANEG_CFG_RF2)
3463                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3464                 if (ap->rxconfig & ANEG_CFG_NP)
3465                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3466
3467                 ap->link_time = ap->cur_time;
3468
3469                 ap->flags ^= (MR_TOGGLE_TX);
3470                 if (ap->rxconfig & 0x0008)
3471                         ap->flags |= MR_TOGGLE_RX;
3472                 if (ap->rxconfig & ANEG_CFG_NP)
3473                         ap->flags |= MR_NP_RX;
3474                 ap->flags |= MR_PAGE_RX;
3475
3476                 ap->state = ANEG_STATE_COMPLETE_ACK;
3477                 ret = ANEG_TIMER_ENAB;
3478                 break;
3479
3480         case ANEG_STATE_COMPLETE_ACK:
3481                 if (ap->ability_match != 0 &&
3482                     ap->rxconfig == 0) {
3483                         ap->state = ANEG_STATE_AN_ENABLE;
3484                         break;
3485                 }
3486                 delta = ap->cur_time - ap->link_time;
3487                 if (delta > ANEG_STATE_SETTLE_TIME) {
3488                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3489                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3490                         } else {
3491                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3492                                     !(ap->flags & MR_NP_RX)) {
3493                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3494                                 } else {
3495                                         ret = ANEG_FAILED;
3496                                 }
3497                         }
3498                 }
3499                 break;
3500
3501         case ANEG_STATE_IDLE_DETECT_INIT:
3502                 ap->link_time = ap->cur_time;
3503                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3504                 tw32_f(MAC_MODE, tp->mac_mode);
3505                 udelay(40);
3506
3507                 ap->state = ANEG_STATE_IDLE_DETECT;
3508                 ret = ANEG_TIMER_ENAB;
3509                 break;
3510
3511         case ANEG_STATE_IDLE_DETECT:
3512                 if (ap->ability_match != 0 &&
3513                     ap->rxconfig == 0) {
3514                         ap->state = ANEG_STATE_AN_ENABLE;
3515                         break;
3516                 }
3517                 delta = ap->cur_time - ap->link_time;
3518                 if (delta > ANEG_STATE_SETTLE_TIME) {
3519                         /* XXX another gem from the Broadcom driver :( */
3520                         ap->state = ANEG_STATE_LINK_OK;
3521                 }
3522                 break;
3523
3524         case ANEG_STATE_LINK_OK:
3525                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3526                 ret = ANEG_DONE;
3527                 break;
3528
3529         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3530                 /* ??? unimplemented */
3531                 break;
3532
3533         case ANEG_STATE_NEXT_PAGE_WAIT:
3534                 /* ??? unimplemented */
3535                 break;
3536
3537         default:
3538                 ret = ANEG_FAILED;
3539                 break;
3540         }
3541
3542         return ret;
3543 }
3544
3545 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3546 {
3547         int res = 0;
3548         struct tg3_fiber_aneginfo aninfo;
3549         int status = ANEG_FAILED;
3550         unsigned int tick;
3551         u32 tmp;
3552
3553         tw32_f(MAC_TX_AUTO_NEG, 0);
3554
3555         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3556         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3557         udelay(40);
3558
3559         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3560         udelay(40);
3561
3562         memset(&aninfo, 0, sizeof(aninfo));
3563         aninfo.flags |= MR_AN_ENABLE;
3564         aninfo.state = ANEG_STATE_UNKNOWN;
3565         aninfo.cur_time = 0;
3566         tick = 0;
3567         while (++tick < 195000) {
3568                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3569                 if (status == ANEG_DONE || status == ANEG_FAILED)
3570                         break;
3571
3572                 udelay(1);
3573         }
3574
3575         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576         tw32_f(MAC_MODE, tp->mac_mode);
3577         udelay(40);
3578
3579         *txflags = aninfo.txconfig;
3580         *rxflags = aninfo.flags;
3581
3582         if (status == ANEG_DONE &&
3583             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3584                              MR_LP_ADV_FULL_DUPLEX)))
3585                 res = 1;
3586
3587         return res;
3588 }
3589
3590 static void tg3_init_bcm8002(struct tg3 *tp)
3591 {
3592         u32 mac_status = tr32(MAC_STATUS);
3593         int i;
3594
3595         /* Reset when initting first time or we have a link. */
3596         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3597             !(mac_status & MAC_STATUS_PCS_SYNCED))
3598                 return;
3599
3600         /* Set PLL lock range. */
3601         tg3_writephy(tp, 0x16, 0x8007);
3602
3603         /* SW reset */
3604         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3605
3606         /* Wait for reset to complete. */
3607         /* XXX schedule_timeout() ... */
3608         for (i = 0; i < 500; i++)
3609                 udelay(10);
3610
3611         /* Config mode; select PMA/Ch 1 regs. */
3612         tg3_writephy(tp, 0x10, 0x8411);
3613
3614         /* Enable auto-lock and comdet, select txclk for tx. */
3615         tg3_writephy(tp, 0x11, 0x0a10);
3616
3617         tg3_writephy(tp, 0x18, 0x00a0);
3618         tg3_writephy(tp, 0x16, 0x41ff);
3619
3620         /* Assert and deassert POR. */
3621         tg3_writephy(tp, 0x13, 0x0400);
3622         udelay(40);
3623         tg3_writephy(tp, 0x13, 0x0000);
3624
3625         tg3_writephy(tp, 0x11, 0x0a50);
3626         udelay(40);
3627         tg3_writephy(tp, 0x11, 0x0a10);
3628
3629         /* Wait for signal to stabilize */
3630         /* XXX schedule_timeout() ... */
3631         for (i = 0; i < 15000; i++)
3632                 udelay(10);
3633
3634         /* Deselect the channel register so we can read the PHYID
3635          * later.
3636          */
3637         tg3_writephy(tp, 0x10, 0x8011);
3638 }
3639
3640 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3641 {
3642         u16 flowctrl;
3643         u32 sg_dig_ctrl, sg_dig_status;
3644         u32 serdes_cfg, expected_sg_dig_ctrl;
3645         int workaround, port_a;
3646         int current_link_up;
3647
3648         serdes_cfg = 0;
3649         expected_sg_dig_ctrl = 0;
3650         workaround = 0;
3651         port_a = 1;
3652         current_link_up = 0;
3653
3654         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3655             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3656                 workaround = 1;
3657                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3658                         port_a = 0;
3659
3660                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3661                 /* preserve bits 20-23 for voltage regulator */
3662                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3663         }
3664
3665         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3666
3667         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3668                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3669                         if (workaround) {
3670                                 u32 val = serdes_cfg;
3671
3672                                 if (port_a)
3673                                         val |= 0xc010000;
3674                                 else
3675                                         val |= 0x4010000;
3676                                 tw32_f(MAC_SERDES_CFG, val);
3677                         }
3678
3679                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3680                 }
3681                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3682                         tg3_setup_flow_control(tp, 0, 0);
3683                         current_link_up = 1;
3684                 }
3685                 goto out;
3686         }
3687
3688         /* Want auto-negotiation.  */
3689         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3690
3691         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3692         if (flowctrl & ADVERTISE_1000XPAUSE)
3693                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3694         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3695                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3696
3697         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3698                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3699                     tp->serdes_counter &&
3700                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3701                                     MAC_STATUS_RCVD_CFG)) ==
3702                      MAC_STATUS_PCS_SYNCED)) {
3703                         tp->serdes_counter--;
3704                         current_link_up = 1;
3705                         goto out;
3706                 }
3707 restart_autoneg:
3708                 if (workaround)
3709                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3710                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3711                 udelay(5);
3712                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3713
3714                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3715                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3716         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3717                                  MAC_STATUS_SIGNAL_DET)) {
3718                 sg_dig_status = tr32(SG_DIG_STATUS);
3719                 mac_status = tr32(MAC_STATUS);
3720
3721                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3722                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3723                         u32 local_adv = 0, remote_adv = 0;
3724
3725                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3726                                 local_adv |= ADVERTISE_1000XPAUSE;
3727                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3728                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3729
3730                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3731                                 remote_adv |= LPA_1000XPAUSE;
3732                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3733                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3734
3735                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3736                         current_link_up = 1;
3737                         tp->serdes_counter = 0;
3738                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3739                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3740                         if (tp->serdes_counter)
3741                                 tp->serdes_counter--;
3742                         else {
3743                                 if (workaround) {
3744                                         u32 val = serdes_cfg;
3745
3746                                         if (port_a)
3747                                                 val |= 0xc010000;
3748                                         else
3749                                                 val |= 0x4010000;
3750
3751                                         tw32_f(MAC_SERDES_CFG, val);
3752                                 }
3753
3754                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3755                                 udelay(40);
3756
3757                                 /* Link parallel detection - link is up */
3758                                 /* only if we have PCS_SYNC and not */
3759                                 /* receiving config code words */
3760                                 mac_status = tr32(MAC_STATUS);
3761                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3762                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3763                                         tg3_setup_flow_control(tp, 0, 0);
3764                                         current_link_up = 1;
3765                                         tp->tg3_flags2 |=
3766                                                 TG3_FLG2_PARALLEL_DETECT;
3767                                         tp->serdes_counter =
3768                                                 SERDES_PARALLEL_DET_TIMEOUT;
3769                                 } else
3770                                         goto restart_autoneg;
3771                         }
3772                 }
3773         } else {
3774                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3775                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3776         }
3777
3778 out:
3779         return current_link_up;
3780 }
3781
3782 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3783 {
3784         int current_link_up = 0;
3785
3786         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3787                 goto out;
3788
3789         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3790                 u32 txflags, rxflags;
3791                 int i;
3792
3793                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3794                         u32 local_adv = 0, remote_adv = 0;
3795
3796                         if (txflags & ANEG_CFG_PS1)
3797                                 local_adv |= ADVERTISE_1000XPAUSE;
3798                         if (txflags & ANEG_CFG_PS2)
3799                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3800
3801                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3802                                 remote_adv |= LPA_1000XPAUSE;
3803                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3804                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3805
3806                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3807
3808                         current_link_up = 1;
3809                 }
3810                 for (i = 0; i < 30; i++) {
3811                         udelay(20);
3812                         tw32_f(MAC_STATUS,
3813                                (MAC_STATUS_SYNC_CHANGED |
3814                                 MAC_STATUS_CFG_CHANGED));
3815                         udelay(40);
3816                         if ((tr32(MAC_STATUS) &
3817                              (MAC_STATUS_SYNC_CHANGED |
3818                               MAC_STATUS_CFG_CHANGED)) == 0)
3819                                 break;
3820                 }
3821
3822                 mac_status = tr32(MAC_STATUS);
3823                 if (current_link_up == 0 &&
3824                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3825                     !(mac_status & MAC_STATUS_RCVD_CFG))
3826                         current_link_up = 1;
3827         } else {
3828                 tg3_setup_flow_control(tp, 0, 0);
3829
3830                 /* Forcing 1000FD link up. */
3831                 current_link_up = 1;
3832
3833                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3834                 udelay(40);
3835
3836                 tw32_f(MAC_MODE, tp->mac_mode);
3837                 udelay(40);
3838         }
3839
3840 out:
3841         return current_link_up;
3842 }
3843
3844 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3845 {
3846         u32 orig_pause_cfg;
3847         u16 orig_active_speed;
3848         u8 orig_active_duplex;
3849         u32 mac_status;
3850         int current_link_up;
3851         int i;
3852
3853         orig_pause_cfg = tp->link_config.active_flowctrl;
3854         orig_active_speed = tp->link_config.active_speed;
3855         orig_active_duplex = tp->link_config.active_duplex;
3856
3857         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3858             netif_carrier_ok(tp->dev) &&
3859             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3860                 mac_status = tr32(MAC_STATUS);
3861                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3862                                MAC_STATUS_SIGNAL_DET |
3863                                MAC_STATUS_CFG_CHANGED |
3864                                MAC_STATUS_RCVD_CFG);
3865                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3866                                    MAC_STATUS_SIGNAL_DET)) {
3867                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3868                                             MAC_STATUS_CFG_CHANGED));
3869                         return 0;
3870                 }
3871         }
3872
3873         tw32_f(MAC_TX_AUTO_NEG, 0);
3874
3875         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3876         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3877         tw32_f(MAC_MODE, tp->mac_mode);
3878         udelay(40);
3879
3880         if (tp->phy_id == PHY_ID_BCM8002)
3881                 tg3_init_bcm8002(tp);
3882
3883         /* Enable link change event even when serdes polling.  */
3884         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3885         udelay(40);
3886
3887         current_link_up = 0;
3888         mac_status = tr32(MAC_STATUS);
3889
3890         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3891                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3892         else
3893                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3894
3895         tp->hw_status->status =
3896                 (SD_STATUS_UPDATED |
3897                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3898
3899         for (i = 0; i < 100; i++) {
3900                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3901                                     MAC_STATUS_CFG_CHANGED));
3902                 udelay(5);
3903                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3904                                          MAC_STATUS_CFG_CHANGED |
3905                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3906                         break;
3907         }
3908
3909         mac_status = tr32(MAC_STATUS);
3910         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3911                 current_link_up = 0;
3912                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3913                     tp->serdes_counter == 0) {
3914                         tw32_f(MAC_MODE, (tp->mac_mode |
3915                                           MAC_MODE_SEND_CONFIGS));
3916                         udelay(1);
3917                         tw32_f(MAC_MODE, tp->mac_mode);
3918                 }
3919         }
3920
3921         if (current_link_up == 1) {
3922                 tp->link_config.active_speed = SPEED_1000;
3923                 tp->link_config.active_duplex = DUPLEX_FULL;
3924                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3925                                     LED_CTRL_LNKLED_OVERRIDE |
3926                                     LED_CTRL_1000MBPS_ON));
3927         } else {
3928                 tp->link_config.active_speed = SPEED_INVALID;
3929                 tp->link_config.active_duplex = DUPLEX_INVALID;
3930                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3931                                     LED_CTRL_LNKLED_OVERRIDE |
3932                                     LED_CTRL_TRAFFIC_OVERRIDE));
3933         }
3934
3935         if (current_link_up != netif_carrier_ok(tp->dev)) {
3936                 if (current_link_up)
3937                         netif_carrier_on(tp->dev);
3938                 else
3939                         netif_carrier_off(tp->dev);
3940                 tg3_link_report(tp);
3941         } else {
3942                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3943                 if (orig_pause_cfg != now_pause_cfg ||
3944                     orig_active_speed != tp->link_config.active_speed ||
3945                     orig_active_duplex != tp->link_config.active_duplex)
3946                         tg3_link_report(tp);
3947         }
3948
3949         return 0;
3950 }
3951
3952 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3953 {
3954         int current_link_up, err = 0;
3955         u32 bmsr, bmcr;
3956         u16 current_speed;
3957         u8 current_duplex;
3958         u32 local_adv, remote_adv;
3959
3960         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3961         tw32_f(MAC_MODE, tp->mac_mode);
3962         udelay(40);
3963
3964         tw32(MAC_EVENT, 0);
3965
3966         tw32_f(MAC_STATUS,
3967              (MAC_STATUS_SYNC_CHANGED |
3968               MAC_STATUS_CFG_CHANGED |
3969               MAC_STATUS_MI_COMPLETION |
3970               MAC_STATUS_LNKSTATE_CHANGED));
3971         udelay(40);
3972
3973         if (force_reset)
3974                 tg3_phy_reset(tp);
3975
3976         current_link_up = 0;
3977         current_speed = SPEED_INVALID;
3978         current_duplex = DUPLEX_INVALID;
3979
3980         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3981         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3983                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3984                         bmsr |= BMSR_LSTATUS;
3985                 else
3986                         bmsr &= ~BMSR_LSTATUS;
3987         }
3988
3989         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3990
3991         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3992             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3993                 /* do nothing, just check for link up at the end */
3994         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3995                 u32 adv, new_adv;
3996
3997                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3998                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3999                                   ADVERTISE_1000XPAUSE |
4000                                   ADVERTISE_1000XPSE_ASYM |
4001                                   ADVERTISE_SLCT);
4002
4003                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4004
4005                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4006                         new_adv |= ADVERTISE_1000XHALF;
4007                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4008                         new_adv |= ADVERTISE_1000XFULL;
4009
4010                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4011                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4012                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4013                         tg3_writephy(tp, MII_BMCR, bmcr);
4014
4015                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4016                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4017                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4018
4019                         return err;
4020                 }
4021         } else {
4022                 u32 new_bmcr;
4023
4024                 bmcr &= ~BMCR_SPEED1000;
4025                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4026
4027                 if (tp->link_config.duplex == DUPLEX_FULL)
4028                         new_bmcr |= BMCR_FULLDPLX;
4029
4030                 if (new_bmcr != bmcr) {
4031                         /* BMCR_SPEED1000 is a reserved bit that needs
4032                          * to be set on write.
4033                          */
4034                         new_bmcr |= BMCR_SPEED1000;
4035
4036                         /* Force a linkdown */
4037                         if (netif_carrier_ok(tp->dev)) {
4038                                 u32 adv;
4039
4040                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4041                                 adv &= ~(ADVERTISE_1000XFULL |
4042                                          ADVERTISE_1000XHALF |
4043                                          ADVERTISE_SLCT);
4044                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4045                                 tg3_writephy(tp, MII_BMCR, bmcr |
4046                                                            BMCR_ANRESTART |
4047                                                            BMCR_ANENABLE);
4048                                 udelay(10);
4049                                 netif_carrier_off(tp->dev);
4050                         }
4051                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4052                         bmcr = new_bmcr;
4053                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4055                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4056                             ASIC_REV_5714) {
4057                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4058                                         bmsr |= BMSR_LSTATUS;
4059                                 else
4060                                         bmsr &= ~BMSR_LSTATUS;
4061                         }
4062                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4063                 }
4064         }
4065
4066         if (bmsr & BMSR_LSTATUS) {
4067                 current_speed = SPEED_1000;
4068                 current_link_up = 1;
4069                 if (bmcr & BMCR_FULLDPLX)
4070                         current_duplex = DUPLEX_FULL;
4071                 else
4072                         current_duplex = DUPLEX_HALF;
4073
4074                 local_adv = 0;
4075                 remote_adv = 0;
4076
4077                 if (bmcr & BMCR_ANENABLE) {
4078                         u32 common;
4079
4080                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4081                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4082                         common = local_adv & remote_adv;
4083                         if (common & (ADVERTISE_1000XHALF |
4084                                       ADVERTISE_1000XFULL)) {
4085                                 if (common & ADVERTISE_1000XFULL)
4086                                         current_duplex = DUPLEX_FULL;
4087                                 else
4088                                         current_duplex = DUPLEX_HALF;
4089                         }
4090                         else
4091                                 current_link_up = 0;
4092                 }
4093         }
4094
4095         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4096                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4097
4098         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4099         if (tp->link_config.active_duplex == DUPLEX_HALF)
4100                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4101
4102         tw32_f(MAC_MODE, tp->mac_mode);
4103         udelay(40);
4104
4105         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4106
4107         tp->link_config.active_speed = current_speed;
4108         tp->link_config.active_duplex = current_duplex;
4109
4110         if (current_link_up != netif_carrier_ok(tp->dev)) {
4111                 if (current_link_up)
4112                         netif_carrier_on(tp->dev);
4113                 else {
4114                         netif_carrier_off(tp->dev);
4115                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4116                 }
4117                 tg3_link_report(tp);
4118         }
4119         return err;
4120 }
4121
4122 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4123 {
4124         if (tp->serdes_counter) {
4125                 /* Give autoneg time to complete. */
4126                 tp->serdes_counter--;
4127                 return;
4128         }
4129         if (!netif_carrier_ok(tp->dev) &&
4130             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4131                 u32 bmcr;
4132
4133                 tg3_readphy(tp, MII_BMCR, &bmcr);
4134                 if (bmcr & BMCR_ANENABLE) {
4135                         u32 phy1, phy2;
4136
4137                         /* Select shadow register 0x1f */
4138                         tg3_writephy(tp, 0x1c, 0x7c00);
4139                         tg3_readphy(tp, 0x1c, &phy1);
4140
4141                         /* Select expansion interrupt status register */
4142                         tg3_writephy(tp, 0x17, 0x0f01);
4143                         tg3_readphy(tp, 0x15, &phy2);
4144                         tg3_readphy(tp, 0x15, &phy2);
4145
4146                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4147                                 /* We have signal detect and not receiving
4148                                  * config code words, link is up by parallel
4149                                  * detection.
4150                                  */
4151
4152                                 bmcr &= ~BMCR_ANENABLE;
4153                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4154                                 tg3_writephy(tp, MII_BMCR, bmcr);
4155                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4156                         }
4157                 }
4158         }
4159         else if (netif_carrier_ok(tp->dev) &&
4160                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4161                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4162                 u32 phy2;
4163
4164                 /* Select expansion interrupt status register */
4165                 tg3_writephy(tp, 0x17, 0x0f01);
4166                 tg3_readphy(tp, 0x15, &phy2);
4167                 if (phy2 & 0x20) {
4168                         u32 bmcr;
4169
4170                         /* Config code words received, turn on autoneg. */
4171                         tg3_readphy(tp, MII_BMCR, &bmcr);
4172                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4173
4174                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4175
4176                 }
4177         }
4178 }
4179
4180 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4181 {
4182         int err;
4183
4184         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4185                 err = tg3_setup_fiber_phy(tp, force_reset);
4186         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4187                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4188         } else {
4189                 err = tg3_setup_copper_phy(tp, force_reset);
4190         }
4191
4192         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4193                 u32 val, scale;
4194
4195                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4196                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4197                         scale = 65;
4198                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4199                         scale = 6;
4200                 else
4201                         scale = 12;
4202
4203                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4204                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4205                 tw32(GRC_MISC_CFG, val);
4206         }
4207
4208         if (tp->link_config.active_speed == SPEED_1000 &&
4209             tp->link_config.active_duplex == DUPLEX_HALF)
4210                 tw32(MAC_TX_LENGTHS,
4211                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4212                       (6 << TX_LENGTHS_IPG_SHIFT) |
4213                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4214         else
4215                 tw32(MAC_TX_LENGTHS,
4216                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4217                       (6 << TX_LENGTHS_IPG_SHIFT) |
4218                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4219
4220         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4221                 if (netif_carrier_ok(tp->dev)) {
4222                         tw32(HOSTCC_STAT_COAL_TICKS,
4223                              tp->coal.stats_block_coalesce_usecs);
4224                 } else {
4225                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4226                 }
4227         }
4228
4229         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4230                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4231                 if (!netif_carrier_ok(tp->dev))
4232                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4233                               tp->pwrmgmt_thresh;
4234                 else
4235                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4236                 tw32(PCIE_PWR_MGMT_THRESH, val);
4237         }
4238
4239         return err;
4240 }
4241
4242 /* This is called whenever we suspect that the system chipset is re-
4243  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4244  * is bogus tx completions. We try to recover by setting the
4245  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4246  * in the workqueue.
4247  */
4248 static void tg3_tx_recover(struct tg3 *tp)
4249 {
4250         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4251                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4252
4253         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4254                "mapped I/O cycles to the network device, attempting to "
4255                "recover. Please report the problem to the driver maintainer "
4256                "and include system chipset information.\n", tp->dev->name);
4257
4258         spin_lock(&tp->lock);
4259         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4260         spin_unlock(&tp->lock);
4261 }
4262
4263 static inline u32 tg3_tx_avail(struct tg3 *tp)
4264 {
4265         smp_mb();
4266         return (tp->tx_pending -
4267                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4268 }
4269
4270 /* Tigon3 never reports partial packet sends.  So we do not
4271  * need special logic to handle SKBs that have not had all
4272  * of their frags sent yet, like SunGEM does.
4273  */
4274 static void tg3_tx(struct tg3 *tp)
4275 {
4276         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4277         u32 sw_idx = tp->tx_cons;
4278
4279         while (sw_idx != hw_idx) {
4280                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4281                 struct sk_buff *skb = ri->skb;
4282                 int i, tx_bug = 0;
4283
4284                 if (unlikely(skb == NULL)) {
4285                         tg3_tx_recover(tp);
4286                         return;
4287                 }
4288
4289                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4290
4291                 ri->skb = NULL;
4292
4293                 sw_idx = NEXT_TX(sw_idx);
4294
4295                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4296                         ri = &tp->tx_buffers[sw_idx];
4297                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4298                                 tx_bug = 1;
4299                         sw_idx = NEXT_TX(sw_idx);
4300                 }
4301
4302                 dev_kfree_skb(skb);
4303
4304                 if (unlikely(tx_bug)) {
4305                         tg3_tx_recover(tp);
4306                         return;
4307                 }
4308         }
4309
4310         tp->tx_cons = sw_idx;
4311
4312         /* Need to make the tx_cons update visible to tg3_start_xmit()
4313          * before checking for netif_queue_stopped().  Without the
4314          * memory barrier, there is a small possibility that tg3_start_xmit()
4315          * will miss it and cause the queue to be stopped forever.
4316          */
4317         smp_mb();
4318
4319         if (unlikely(netif_queue_stopped(tp->dev) &&
4320                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4321                 netif_tx_lock(tp->dev);
4322                 if (netif_queue_stopped(tp->dev) &&
4323                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4324                         netif_wake_queue(tp->dev);
4325                 netif_tx_unlock(tp->dev);
4326         }
4327 }
4328
4329 /* Returns size of skb allocated or < 0 on error.
4330  *
4331  * We only need to fill in the address because the other members
4332  * of the RX descriptor are invariant, see tg3_init_rings.
4333  *
4334  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4335  * posting buffers we only dirty the first cache line of the RX
4336  * descriptor (containing the address).  Whereas for the RX status
4337  * buffers the cpu only reads the last cacheline of the RX descriptor
4338  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4339  */
4340 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4341                             int src_idx, u32 dest_idx_unmasked)
4342 {
4343         struct tg3_rx_buffer_desc *desc;
4344         struct ring_info *map, *src_map;
4345         struct sk_buff *skb;
4346         dma_addr_t mapping;
4347         int skb_size, dest_idx;
4348
4349         src_map = NULL;
4350         switch (opaque_key) {
4351         case RXD_OPAQUE_RING_STD:
4352                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4353                 desc = &tp->rx_std[dest_idx];
4354                 map = &tp->rx_std_buffers[dest_idx];
4355                 if (src_idx >= 0)
4356                         src_map = &tp->rx_std_buffers[src_idx];
4357                 skb_size = tp->rx_pkt_buf_sz;
4358                 break;
4359
4360         case RXD_OPAQUE_RING_JUMBO:
4361                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4362                 desc = &tp->rx_jumbo[dest_idx];
4363                 map = &tp->rx_jumbo_buffers[dest_idx];
4364                 if (src_idx >= 0)
4365                         src_map = &tp->rx_jumbo_buffers[src_idx];
4366                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4367                 break;
4368
4369         default:
4370                 return -EINVAL;
4371         }
4372
4373         /* Do not overwrite any of the map or rp information
4374          * until we are sure we can commit to a new buffer.
4375          *
4376          * Callers depend upon this behavior and assume that
4377          * we leave everything unchanged if we fail.
4378          */
4379         skb = netdev_alloc_skb(tp->dev, skb_size);
4380         if (skb == NULL)
4381                 return -ENOMEM;
4382
4383         skb_reserve(skb, tp->rx_offset);
4384
4385         mapping = pci_map_single(tp->pdev, skb->data,
4386                                  skb_size - tp->rx_offset,
4387                                  PCI_DMA_FROMDEVICE);
4388
4389         map->skb = skb;
4390         pci_unmap_addr_set(map, mapping, mapping);
4391
4392         if (src_map != NULL)
4393                 src_map->skb = NULL;
4394
4395         desc->addr_hi = ((u64)mapping >> 32);
4396         desc->addr_lo = ((u64)mapping & 0xffffffff);
4397
4398         return skb_size;
4399 }
4400
4401 /* We only need to move over in the address because the other
4402  * members of the RX descriptor are invariant.  See notes above
4403  * tg3_alloc_rx_skb for full details.
4404  */
4405 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4406                            int src_idx, u32 dest_idx_unmasked)
4407 {
4408         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4409         struct ring_info *src_map, *dest_map;
4410         int dest_idx;
4411
4412         switch (opaque_key) {
4413         case RXD_OPAQUE_RING_STD:
4414                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4415                 dest_desc = &tp->rx_std[dest_idx];
4416                 dest_map = &tp->rx_std_buffers[dest_idx];
4417                 src_desc = &tp->rx_std[src_idx];
4418                 src_map = &tp->rx_std_buffers[src_idx];
4419                 break;
4420
4421         case RXD_OPAQUE_RING_JUMBO:
4422                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4423                 dest_desc = &tp->rx_jumbo[dest_idx];
4424                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4425                 src_desc = &tp->rx_jumbo[src_idx];
4426                 src_map = &tp->rx_jumbo_buffers[src_idx];
4427                 break;
4428
4429         default:
4430                 return;
4431         }
4432
4433         dest_map->skb = src_map->skb;
4434         pci_unmap_addr_set(dest_map, mapping,
4435                            pci_unmap_addr(src_map, mapping));
4436         dest_desc->addr_hi = src_desc->addr_hi;
4437         dest_desc->addr_lo = src_desc->addr_lo;
4438
4439         src_map->skb = NULL;
4440 }
4441
4442 #if TG3_VLAN_TAG_USED
4443 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4444 {
4445         return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4446 }
4447 #endif
4448
4449 /* The RX ring scheme is composed of multiple rings which post fresh
4450  * buffers to the chip, and one special ring the chip uses to report
4451  * status back to the host.
4452  *
4453  * The special ring reports the status of received packets to the
4454  * host.  The chip does not write into the original descriptor the
4455  * RX buffer was obtained from.  The chip simply takes the original
4456  * descriptor as provided by the host, updates the status and length
4457  * field, then writes this into the next status ring entry.
4458  *
4459  * Each ring the host uses to post buffers to the chip is described
4460  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4461  * it is first placed into the on-chip ram.  When the packet's length
4462  * is known, it walks down the TG3_BDINFO entries to select the ring.
4463  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4464  * which is within the range of the new packet's length is chosen.
4465  *
4466  * The "separate ring for rx status" scheme may sound queer, but it makes
4467  * sense from a cache coherency perspective.  If only the host writes
4468  * to the buffer post rings, and only the chip writes to the rx status
4469  * rings, then cache lines never move beyond shared-modified state.
4470  * If both the host and chip were to write into the same ring, cache line
4471  * eviction could occur since both entities want it in an exclusive state.
4472  */
4473 static int tg3_rx(struct tg3 *tp, int budget)
4474 {
4475         u32 work_mask, rx_std_posted = 0;
4476         u32 sw_idx = tp->rx_rcb_ptr;
4477         u16 hw_idx;
4478         int received;
4479
4480         hw_idx = tp->hw_status->idx[0].rx_producer;
4481         /*
4482          * We need to order the read of hw_idx and the read of
4483          * the opaque cookie.
4484          */
4485         rmb();
4486         work_mask = 0;
4487         received = 0;
4488         while (sw_idx != hw_idx && budget > 0) {
4489                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4490                 unsigned int len;
4491                 struct sk_buff *skb;
4492                 dma_addr_t dma_addr;
4493                 u32 opaque_key, desc_idx, *post_ptr;
4494
4495                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4496                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4497                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4498                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4499                                                   mapping);
4500                         skb = tp->rx_std_buffers[desc_idx].skb;
4501                         post_ptr = &tp->rx_std_ptr;
4502                         rx_std_posted++;
4503                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4504                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4505                                                   mapping);
4506                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4507                         post_ptr = &tp->rx_jumbo_ptr;
4508                 }
4509                 else {
4510                         goto next_pkt_nopost;
4511                 }
4512
4513                 work_mask |= opaque_key;
4514
4515                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4516                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4517                 drop_it:
4518                         tg3_recycle_rx(tp, opaque_key,
4519                                        desc_idx, *post_ptr);
4520                 drop_it_no_recycle:
4521                         /* Other statistics kept track of by card. */
4522                         tp->net_stats.rx_dropped++;
4523                         goto next_pkt;
4524                 }
4525
4526                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4527                       ETH_FCS_LEN;
4528
4529                 if (len > RX_COPY_THRESHOLD
4530                         && tp->rx_offset == NET_IP_ALIGN
4531                         /* rx_offset will likely not equal NET_IP_ALIGN
4532                          * if this is a 5701 card running in PCI-X mode
4533                          * [see tg3_get_invariants()]
4534                          */
4535                 ) {
4536                         int skb_size;
4537
4538                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4539                                                     desc_idx, *post_ptr);
4540                         if (skb_size < 0)
4541                                 goto drop_it;
4542
4543                         pci_unmap_single(tp->pdev, dma_addr,
4544                                          skb_size - tp->rx_offset,
4545                                          PCI_DMA_FROMDEVICE);
4546
4547                         skb_put(skb, len);
4548                 } else {
4549                         struct sk_buff *copy_skb;
4550
4551                         tg3_recycle_rx(tp, opaque_key,
4552                                        desc_idx, *post_ptr);
4553
4554                         copy_skb = netdev_alloc_skb(tp->dev,
4555                                                     len + TG3_RAW_IP_ALIGN);
4556                         if (copy_skb == NULL)
4557                                 goto drop_it_no_recycle;
4558
4559                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4560                         skb_put(copy_skb, len);
4561                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4562                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4563                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4564
4565                         /* We'll reuse the original ring buffer. */
4566                         skb = copy_skb;
4567                 }
4568
4569                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4570                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4571                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4572                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4573                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4574                 else
4575                         skb->ip_summed = CHECKSUM_NONE;
4576
4577                 skb->protocol = eth_type_trans(skb, tp->dev);
4578
4579                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4580                     skb->protocol != htons(ETH_P_8021Q)) {
4581                         dev_kfree_skb(skb);
4582                         goto next_pkt;
4583                 }
4584
4585 #if TG3_VLAN_TAG_USED
4586                 if (tp->vlgrp != NULL &&
4587                     desc->type_flags & RXD_FLAG_VLAN) {
4588                         tg3_vlan_rx(tp, skb,
4589                                     desc->err_vlan & RXD_VLAN_MASK);
4590                 } else
4591 #endif
4592                         napi_gro_receive(&tp->napi, skb);
4593
4594                 received++;
4595                 budget--;
4596
4597 next_pkt:
4598                 (*post_ptr)++;
4599
4600                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4601                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4602
4603                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4604                                      TG3_64BIT_REG_LOW, idx);
4605                         work_mask &= ~RXD_OPAQUE_RING_STD;
4606                         rx_std_posted = 0;
4607                 }
4608 next_pkt_nopost:
4609                 sw_idx++;
4610                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4611
4612                 /* Refresh hw_idx to see if there is new work */
4613                 if (sw_idx == hw_idx) {
4614                         hw_idx = tp->hw_status->idx[0].rx_producer;
4615                         rmb();
4616                 }
4617         }
4618
4619         /* ACK the status ring. */
4620         tp->rx_rcb_ptr = sw_idx;
4621         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4622
4623         /* Refill RX ring(s). */
4624         if (work_mask & RXD_OPAQUE_RING_STD) {
4625                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4626                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4627                              sw_idx);
4628         }
4629         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4630                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4631                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4632                              sw_idx);
4633         }
4634         mmiowb();
4635
4636         return received;
4637 }
4638
4639 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4640 {
4641         struct tg3_hw_status *sblk = tp->hw_status;
4642
4643         /* handle link change and other phy events */
4644         if (!(tp->tg3_flags &
4645               (TG3_FLAG_USE_LINKCHG_REG |
4646                TG3_FLAG_POLL_SERDES))) {
4647                 if (sblk->status & SD_STATUS_LINK_CHG) {
4648                         sblk->status = SD_STATUS_UPDATED |
4649                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4650                         spin_lock(&tp->lock);
4651                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4652                                 tw32_f(MAC_STATUS,
4653                                      (MAC_STATUS_SYNC_CHANGED |
4654                                       MAC_STATUS_CFG_CHANGED |
4655                                       MAC_STATUS_MI_COMPLETION |
4656                                       MAC_STATUS_LNKSTATE_CHANGED));
4657                                 udelay(40);
4658                         } else
4659                                 tg3_setup_phy(tp, 0);
4660                         spin_unlock(&tp->lock);
4661                 }
4662         }
4663
4664         /* run TX completion thread */
4665         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4666                 tg3_tx(tp);
4667                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4668                         return work_done;
4669         }
4670
4671         /* run RX thread, within the bounds set by NAPI.
4672          * All RX "locking" is done by ensuring outside
4673          * code synchronizes with tg3->napi.poll()
4674          */
4675         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4676                 work_done += tg3_rx(tp, budget - work_done);
4677
4678         return work_done;
4679 }
4680
4681 static int tg3_poll(struct napi_struct *napi, int budget)
4682 {
4683         struct tg3 *tp = container_of(napi, struct tg3, napi);
4684         int work_done = 0;
4685         struct tg3_hw_status *sblk = tp->hw_status;
4686
4687         while (1) {
4688                 work_done = tg3_poll_work(tp, work_done, budget);
4689
4690                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4691                         goto tx_recovery;
4692
4693                 if (unlikely(work_done >= budget))
4694                         break;
4695
4696                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4697                         /* tp->last_tag is used in tg3_restart_ints() below
4698                          * to tell the hw how much work has been processed,
4699                          * so we must read it before checking for more work.
4700                          */
4701                         tp->last_tag = sblk->status_tag;
4702                         tp->last_irq_tag = tp->last_tag;
4703                         rmb();
4704                 } else
4705                         sblk->status &= ~SD_STATUS_UPDATED;
4706
4707                 if (likely(!tg3_has_work(tp))) {
4708                         napi_complete(napi);
4709                         tg3_restart_ints(tp);
4710                         break;
4711                 }
4712         }
4713
4714         return work_done;
4715
4716 tx_recovery:
4717         /* work_done is guaranteed to be less than budget. */
4718         napi_complete(napi);
4719         schedule_work(&tp->reset_task);
4720         return work_done;
4721 }
4722
4723 static void tg3_irq_quiesce(struct tg3 *tp)
4724 {
4725         BUG_ON(tp->irq_sync);
4726
4727         tp->irq_sync = 1;
4728         smp_mb();
4729
4730         synchronize_irq(tp->pdev->irq);
4731 }
4732
4733 static inline int tg3_irq_sync(struct tg3 *tp)
4734 {
4735         return tp->irq_sync;
4736 }
4737
4738 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4739  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4740  * with as well.  Most of the time, this is not necessary except when
4741  * shutting down the device.
4742  */
4743 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4744 {
4745         spin_lock_bh(&tp->lock);
4746         if (irq_sync)
4747                 tg3_irq_quiesce(tp);
4748 }
4749
4750 static inline void tg3_full_unlock(struct tg3 *tp)
4751 {
4752         spin_unlock_bh(&tp->lock);
4753 }
4754
4755 /* One-shot MSI handler - Chip automatically disables interrupt
4756  * after sending MSI so driver doesn't have to do it.
4757  */
4758 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4759 {
4760         struct net_device *dev = dev_id;
4761         struct tg3 *tp = netdev_priv(dev);
4762
4763         prefetch(tp->hw_status);
4764         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4765
4766         if (likely(!tg3_irq_sync(tp)))
4767                 napi_schedule(&tp->napi);
4768
4769         return IRQ_HANDLED;
4770 }
4771
4772 /* MSI ISR - No need to check for interrupt sharing and no need to
4773  * flush status block and interrupt mailbox. PCI ordering rules
4774  * guarantee that MSI will arrive after the status block.
4775  */
4776 static irqreturn_t tg3_msi(int irq, void *dev_id)
4777 {
4778         struct net_device *dev = dev_id;
4779         struct tg3 *tp = netdev_priv(dev);
4780
4781         prefetch(tp->hw_status);
4782         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4783         /*
4784          * Writing any value to intr-mbox-0 clears PCI INTA# and
4785          * chip-internal interrupt pending events.
4786          * Writing non-zero to intr-mbox-0 additional tells the
4787          * NIC to stop sending us irqs, engaging "in-intr-handler"
4788          * event coalescing.
4789          */
4790         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4791         if (likely(!tg3_irq_sync(tp)))
4792                 napi_schedule(&tp->napi);
4793
4794         return IRQ_RETVAL(1);
4795 }
4796
4797 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4798 {
4799         struct net_device *dev = dev_id;
4800         struct tg3 *tp = netdev_priv(dev);
4801         struct tg3_hw_status *sblk = tp->hw_status;
4802         unsigned int handled = 1;
4803
4804         /* In INTx mode, it is possible for the interrupt to arrive at
4805          * the CPU before the status block posted prior to the interrupt.
4806          * Reading the PCI State register will confirm whether the
4807          * interrupt is ours and will flush the status block.
4808          */
4809         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4810                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4811                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4812                         handled = 0;
4813                         goto out;
4814                 }
4815         }
4816
4817         /*
4818          * Writing any value to intr-mbox-0 clears PCI INTA# and
4819          * chip-internal interrupt pending events.
4820          * Writing non-zero to intr-mbox-0 additional tells the
4821          * NIC to stop sending us irqs, engaging "in-intr-handler"
4822          * event coalescing.
4823          *
4824          * Flush the mailbox to de-assert the IRQ immediately to prevent
4825          * spurious interrupts.  The flush impacts performance but
4826          * excessive spurious interrupts can be worse in some cases.
4827          */
4828         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4829         if (tg3_irq_sync(tp))
4830                 goto out;
4831         sblk->status &= ~SD_STATUS_UPDATED;
4832         if (likely(tg3_has_work(tp))) {
4833                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4834                 napi_schedule(&tp->napi);
4835         } else {
4836                 /* No work, shared interrupt perhaps?  re-enable
4837                  * interrupts, and flush that PCI write
4838                  */
4839                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4840                                0x00000000);
4841         }
4842 out:
4843         return IRQ_RETVAL(handled);
4844 }
4845
4846 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4847 {
4848         struct net_device *dev = dev_id;
4849         struct tg3 *tp = netdev_priv(dev);
4850         struct tg3_hw_status *sblk = tp->hw_status;
4851         unsigned int handled = 1;
4852
4853         /* In INTx mode, it is possible for the interrupt to arrive at
4854          * the CPU before the status block posted prior to the interrupt.
4855          * Reading the PCI State register will confirm whether the
4856          * interrupt is ours and will flush the status block.
4857          */
4858         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4859                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4860                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4861                         handled = 0;
4862                         goto out;
4863                 }
4864         }
4865
4866         /*
4867          * writing any value to intr-mbox-0 clears PCI INTA# and
4868          * chip-internal interrupt pending events.
4869          * writing non-zero to intr-mbox-0 additional tells the
4870          * NIC to stop sending us irqs, engaging "in-intr-handler"
4871          * event coalescing.
4872          *
4873          * Flush the mailbox to de-assert the IRQ immediately to prevent
4874          * spurious interrupts.  The flush impacts performance but
4875          * excessive spurious interrupts can be worse in some cases.
4876          */
4877         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4878
4879         /*
4880          * In a shared interrupt configuration, sometimes other devices'
4881          * interrupts will scream.  We record the current status tag here
4882          * so that the above check can report that the screaming interrupts
4883          * are unhandled.  Eventually they will be silenced.
4884          */
4885         tp->last_irq_tag = sblk->status_tag;
4886
4887         if (tg3_irq_sync(tp))
4888                 goto out;
4889
4890         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4891
4892         napi_schedule(&tp->napi);
4893
4894 out:
4895         return IRQ_RETVAL(handled);
4896 }
4897
4898 /* ISR for interrupt test */
4899 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4900 {
4901         struct net_device *dev = dev_id;
4902         struct tg3 *tp = netdev_priv(dev);
4903         struct tg3_hw_status *sblk = tp->hw_status;
4904
4905         if ((sblk->status & SD_STATUS_UPDATED) ||
4906             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4907                 tg3_disable_ints(tp);
4908                 return IRQ_RETVAL(1);
4909         }
4910         return IRQ_RETVAL(0);
4911 }
4912
4913 static int tg3_init_hw(struct tg3 *, int);
4914 static int tg3_halt(struct tg3 *, int, int);
4915
4916 /* Restart hardware after configuration changes, self-test, etc.
4917  * Invoked with tp->lock held.
4918  */
4919 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4920         __releases(tp->lock)
4921         __acquires(tp->lock)
4922 {
4923         int err;
4924
4925         err = tg3_init_hw(tp, reset_phy);
4926         if (err) {
4927                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4928                        "aborting.\n", tp->dev->name);
4929                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4930                 tg3_full_unlock(tp);
4931                 del_timer_sync(&tp->timer);
4932                 tp->irq_sync = 0;
4933                 napi_enable(&tp->napi);
4934                 dev_close(tp->dev);
4935                 tg3_full_lock(tp, 0);
4936         }
4937         return err;
4938 }
4939
4940 #ifdef CONFIG_NET_POLL_CONTROLLER
4941 static void tg3_poll_controller(struct net_device *dev)
4942 {
4943         struct tg3 *tp = netdev_priv(dev);
4944
4945         tg3_interrupt(tp->pdev->irq, dev);
4946 }
4947 #endif
4948
4949 static void tg3_reset_task(struct work_struct *work)
4950 {
4951         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4952         int err;
4953         unsigned int restart_timer;
4954
4955         tg3_full_lock(tp, 0);
4956
4957         if (!netif_running(tp->dev)) {
4958                 tg3_full_unlock(tp);
4959                 return;
4960         }
4961
4962         tg3_full_unlock(tp);
4963
4964         tg3_phy_stop(tp);
4965
4966         tg3_netif_stop(tp);
4967
4968         tg3_full_lock(tp, 1);
4969
4970         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4971         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4972
4973         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4974                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4975                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4976                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4977                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4978         }
4979
4980         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4981         err = tg3_init_hw(tp, 1);
4982         if (err)
4983                 goto out;
4984
4985         tg3_netif_start(tp);
4986
4987         if (restart_timer)
4988                 mod_timer(&tp->timer, jiffies + 1);
4989
4990 out:
4991         tg3_full_unlock(tp);
4992
4993         if (!err)
4994                 tg3_phy_start(tp);
4995 }
4996
4997 static void tg3_dump_short_state(struct tg3 *tp)
4998 {
4999         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5000                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5001         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5002                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5003 }
5004
5005 static void tg3_tx_timeout(struct net_device *dev)
5006 {
5007         struct tg3 *tp = netdev_priv(dev);
5008
5009         if (netif_msg_tx_err(tp)) {
5010                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5011                        dev->name);
5012                 tg3_dump_short_state(tp);
5013         }
5014
5015         schedule_work(&tp->reset_task);
5016 }
5017
5018 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5019 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5020 {
5021         u32 base = (u32) mapping & 0xffffffff;
5022
5023         return ((base > 0xffffdcc0) &&
5024                 (base + len + 8 < base));
5025 }
5026
5027 /* Test for DMA addresses > 40-bit */
5028 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5029                                           int len)
5030 {
5031 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5032         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5033                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5034         return 0;
5035 #else
5036         return 0;
5037 #endif
5038 }
5039
5040 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5041
5042 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5043 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5044                                        u32 last_plus_one, u32 *start,
5045                                        u32 base_flags, u32 mss)
5046 {
5047         struct sk_buff *new_skb;
5048         dma_addr_t new_addr = 0;
5049         u32 entry = *start;
5050         int i, ret = 0;
5051
5052         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5053                 new_skb = skb_copy(skb, GFP_ATOMIC);
5054         else {
5055                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5056
5057                 new_skb = skb_copy_expand(skb,
5058                                           skb_headroom(skb) + more_headroom,
5059                                           skb_tailroom(skb), GFP_ATOMIC);
5060         }
5061
5062         if (!new_skb) {
5063                 ret = -1;
5064         } else {
5065                 /* New SKB is guaranteed to be linear. */
5066                 entry = *start;
5067                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5068                 new_addr = skb_shinfo(new_skb)->dma_head;
5069
5070                 /* Make sure new skb does not cross any 4G boundaries.
5071                  * Drop the packet if it does.
5072                  */
5073                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5074                         if (!ret)
5075                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5076                                               DMA_TO_DEVICE);
5077                         ret = -1;
5078                         dev_kfree_skb(new_skb);
5079                         new_skb = NULL;
5080                 } else {
5081                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5082                                     base_flags, 1 | (mss << 1));
5083                         *start = NEXT_TX(entry);
5084                 }
5085         }
5086
5087         /* Now clean up the sw ring entries. */
5088         i = 0;
5089         while (entry != last_plus_one) {
5090                 if (i == 0) {
5091                         tp->tx_buffers[entry].skb = new_skb;
5092                 } else {
5093                         tp->tx_buffers[entry].skb = NULL;
5094                 }
5095                 entry = NEXT_TX(entry);
5096                 i++;
5097         }
5098
5099         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5100         dev_kfree_skb(skb);
5101
5102         return ret;
5103 }
5104
5105 static void tg3_set_txd(struct tg3 *tp, int entry,
5106                         dma_addr_t mapping, int len, u32 flags,
5107                         u32 mss_and_is_end)
5108 {
5109         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5110         int is_end = (mss_and_is_end & 0x1);
5111         u32 mss = (mss_and_is_end >> 1);
5112         u32 vlan_tag = 0;
5113
5114         if (is_end)
5115                 flags |= TXD_FLAG_END;
5116         if (flags & TXD_FLAG_VLAN) {
5117                 vlan_tag = flags >> 16;
5118                 flags &= 0xffff;
5119         }
5120         vlan_tag |= (mss << TXD_MSS_SHIFT);
5121
5122         txd->addr_hi = ((u64) mapping >> 32);
5123         txd->addr_lo = ((u64) mapping & 0xffffffff);
5124         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5125         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5126 }
5127
5128 /* hard_start_xmit for devices that don't have any bugs and
5129  * support TG3_FLG2_HW_TSO_2 only.
5130  */
5131 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5132 {
5133         struct tg3 *tp = netdev_priv(dev);
5134         u32 len, entry, base_flags, mss;
5135         struct skb_shared_info *sp;
5136         dma_addr_t mapping;
5137
5138         len = skb_headlen(skb);
5139
5140         /* We are running in BH disabled context with netif_tx_lock
5141          * and TX reclaim runs via tp->napi.poll inside of a software
5142          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5143          * no IRQ context deadlocks to worry about either.  Rejoice!
5144          */
5145         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5146                 if (!netif_queue_stopped(dev)) {
5147                         netif_stop_queue(dev);
5148
5149                         /* This is a hard error, log it. */
5150                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5151                                "queue awake!\n", dev->name);
5152                 }
5153                 return NETDEV_TX_BUSY;
5154         }
5155
5156         entry = tp->tx_prod;
5157         base_flags = 0;
5158         mss = 0;
5159         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5160                 int tcp_opt_len, ip_tcp_len;
5161
5162                 if (skb_header_cloned(skb) &&
5163                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5164                         dev_kfree_skb(skb);
5165                         goto out_unlock;
5166                 }
5167
5168                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5169                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5170                 else {
5171                         struct iphdr *iph = ip_hdr(skb);
5172
5173                         tcp_opt_len = tcp_optlen(skb);
5174                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5175
5176                         iph->check = 0;
5177                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5178                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5179                 }
5180
5181                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5182                                TXD_FLAG_CPU_POST_DMA);
5183
5184                 tcp_hdr(skb)->check = 0;
5185
5186         }
5187         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5188                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5189 #if TG3_VLAN_TAG_USED
5190         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5191                 base_flags |= (TXD_FLAG_VLAN |
5192                                (vlan_tx_tag_get(skb) << 16));
5193 #endif
5194
5195         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5196                 dev_kfree_skb(skb);
5197                 goto out_unlock;
5198         }
5199
5200         sp = skb_shinfo(skb);
5201
5202         mapping = sp->dma_head;
5203
5204         tp->tx_buffers[entry].skb = skb;
5205
5206         tg3_set_txd(tp, entry, mapping, len, base_flags,
5207                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5208
5209         entry = NEXT_TX(entry);
5210
5211         /* Now loop through additional data fragments, and queue them. */
5212         if (skb_shinfo(skb)->nr_frags > 0) {
5213                 unsigned int i, last;
5214
5215                 last = skb_shinfo(skb)->nr_frags - 1;
5216                 for (i = 0; i <= last; i++) {
5217                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5218
5219                         len = frag->size;
5220                         mapping = sp->dma_maps[i];
5221                         tp->tx_buffers[entry].skb = NULL;
5222
5223                         tg3_set_txd(tp, entry, mapping, len,
5224                                     base_flags, (i == last) | (mss << 1));
5225
5226                         entry = NEXT_TX(entry);
5227                 }
5228         }
5229
5230         /* Packets are ready, update Tx producer idx local and on card. */
5231         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5232
5233         tp->tx_prod = entry;
5234         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5235                 netif_stop_queue(dev);
5236                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5237                         netif_wake_queue(tp->dev);
5238         }
5239
5240 out_unlock:
5241         mmiowb();
5242
5243         return NETDEV_TX_OK;
5244 }
5245
5246 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5247
5248 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5249  * TSO header is greater than 80 bytes.
5250  */
5251 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5252 {
5253         struct sk_buff *segs, *nskb;
5254
5255         /* Estimate the number of fragments in the worst case */
5256         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5257                 netif_stop_queue(tp->dev);
5258                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5259                         return NETDEV_TX_BUSY;
5260
5261                 netif_wake_queue(tp->dev);
5262         }
5263
5264         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5265         if (IS_ERR(segs))
5266                 goto tg3_tso_bug_end;
5267
5268         do {
5269                 nskb = segs;
5270                 segs = segs->next;
5271                 nskb->next = NULL;
5272                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5273         } while (segs);
5274
5275 tg3_tso_bug_end:
5276         dev_kfree_skb(skb);
5277
5278         return NETDEV_TX_OK;
5279 }
5280
5281 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5282  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5283  */
5284 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5285 {
5286         struct tg3 *tp = netdev_priv(dev);
5287         u32 len, entry, base_flags, mss;
5288         struct skb_shared_info *sp;
5289         int would_hit_hwbug;
5290         dma_addr_t mapping;
5291
5292         len = skb_headlen(skb);
5293
5294         /* We are running in BH disabled context with netif_tx_lock
5295          * and TX reclaim runs via tp->napi.poll inside of a software
5296          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5297          * no IRQ context deadlocks to worry about either.  Rejoice!
5298          */
5299         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5300                 if (!netif_queue_stopped(dev)) {
5301                         netif_stop_queue(dev);
5302
5303                         /* This is a hard error, log it. */
5304                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5305                                "queue awake!\n", dev->name);
5306                 }
5307                 return NETDEV_TX_BUSY;
5308         }
5309
5310         entry = tp->tx_prod;
5311         base_flags = 0;
5312         if (skb->ip_summed == CHECKSUM_PARTIAL)
5313                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5314         mss = 0;
5315         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5316                 struct iphdr *iph;
5317                 int tcp_opt_len, ip_tcp_len, hdr_len;
5318
5319                 if (skb_header_cloned(skb) &&
5320                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5321                         dev_kfree_skb(skb);
5322                         goto out_unlock;
5323                 }
5324
5325                 tcp_opt_len = tcp_optlen(skb);
5326                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5327
5328                 hdr_len = ip_tcp_len + tcp_opt_len;
5329                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5330                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5331                         return (tg3_tso_bug(tp, skb));
5332
5333                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5334                                TXD_FLAG_CPU_POST_DMA);
5335
5336                 iph = ip_hdr(skb);
5337                 iph->check = 0;
5338                 iph->tot_len = htons(mss + hdr_len);
5339                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5340                         tcp_hdr(skb)->check = 0;
5341                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5342                 } else
5343                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5344                                                                  iph->daddr, 0,
5345                                                                  IPPROTO_TCP,
5346                                                                  0);
5347
5348                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5349                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5350                         if (tcp_opt_len || iph->ihl > 5) {
5351                                 int tsflags;
5352
5353                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5354                                 mss |= (tsflags << 11);
5355                         }
5356                 } else {
5357                         if (tcp_opt_len || iph->ihl > 5) {
5358                                 int tsflags;
5359
5360                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5361                                 base_flags |= tsflags << 12;
5362                         }
5363                 }
5364         }
5365 #if TG3_VLAN_TAG_USED
5366         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5367                 base_flags |= (TXD_FLAG_VLAN |
5368                                (vlan_tx_tag_get(skb) << 16));
5369 #endif
5370
5371         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5372                 dev_kfree_skb(skb);
5373                 goto out_unlock;
5374         }
5375
5376         sp = skb_shinfo(skb);
5377
5378         mapping = sp->dma_head;
5379
5380         tp->tx_buffers[entry].skb = skb;
5381
5382         would_hit_hwbug = 0;
5383
5384         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5385                 would_hit_hwbug = 1;
5386         else if (tg3_4g_overflow_test(mapping, len))
5387                 would_hit_hwbug = 1;
5388
5389         tg3_set_txd(tp, entry, mapping, len, base_flags,
5390                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5391
5392         entry = NEXT_TX(entry);
5393
5394         /* Now loop through additional data fragments, and queue them. */
5395         if (skb_shinfo(skb)->nr_frags > 0) {
5396                 unsigned int i, last;
5397
5398                 last = skb_shinfo(skb)->nr_frags - 1;
5399                 for (i = 0; i <= last; i++) {
5400                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5401
5402                         len = frag->size;
5403                         mapping = sp->dma_maps[i];
5404
5405                         tp->tx_buffers[entry].skb = NULL;
5406
5407                         if (tg3_4g_overflow_test(mapping, len))
5408                                 would_hit_hwbug = 1;
5409
5410                         if (tg3_40bit_overflow_test(tp, mapping, len))
5411                                 would_hit_hwbug = 1;
5412
5413                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5414                                 tg3_set_txd(tp, entry, mapping, len,
5415                                             base_flags, (i == last)|(mss << 1));
5416                         else
5417                                 tg3_set_txd(tp, entry, mapping, len,
5418                                             base_flags, (i == last));
5419
5420                         entry = NEXT_TX(entry);
5421                 }
5422         }
5423
5424         if (would_hit_hwbug) {
5425                 u32 last_plus_one = entry;
5426                 u32 start;
5427
5428                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5429                 start &= (TG3_TX_RING_SIZE - 1);
5430
5431                 /* If the workaround fails due to memory/mapping
5432                  * failure, silently drop this packet.
5433                  */
5434                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5435                                                 &start, base_flags, mss))
5436                         goto out_unlock;
5437
5438                 entry = start;
5439         }
5440
5441         /* Packets are ready, update Tx producer idx local and on card. */
5442         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5443
5444         tp->tx_prod = entry;
5445         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5446                 netif_stop_queue(dev);
5447                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5448                         netif_wake_queue(tp->dev);
5449         }
5450
5451 out_unlock:
5452         mmiowb();
5453
5454         return NETDEV_TX_OK;
5455 }
5456
5457 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5458                                int new_mtu)
5459 {
5460         dev->mtu = new_mtu;
5461
5462         if (new_mtu > ETH_DATA_LEN) {
5463                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5464                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5465                         ethtool_op_set_tso(dev, 0);
5466                 }
5467                 else
5468                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5469         } else {
5470                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5471                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5472                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5473         }
5474 }
5475
5476 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5477 {
5478         struct tg3 *tp = netdev_priv(dev);
5479         int err;
5480
5481         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5482                 return -EINVAL;
5483
5484         if (!netif_running(dev)) {
5485                 /* We'll just catch it later when the
5486                  * device is up'd.
5487                  */
5488                 tg3_set_mtu(dev, tp, new_mtu);
5489                 return 0;
5490         }
5491
5492         tg3_phy_stop(tp);
5493
5494         tg3_netif_stop(tp);
5495
5496         tg3_full_lock(tp, 1);
5497
5498         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5499
5500         tg3_set_mtu(dev, tp, new_mtu);
5501
5502         err = tg3_restart_hw(tp, 0);
5503
5504         if (!err)
5505                 tg3_netif_start(tp);
5506
5507         tg3_full_unlock(tp);
5508
5509         if (!err)
5510                 tg3_phy_start(tp);
5511
5512         return err;
5513 }
5514
5515 /* Free up pending packets in all rx/tx rings.
5516  *
5517  * The chip has been shut down and the driver detached from
5518  * the networking, so no interrupts or new tx packets will
5519  * end up in the driver.  tp->{tx,}lock is not held and we are not
5520  * in an interrupt context and thus may sleep.
5521  */
5522 static void tg3_free_rings(struct tg3 *tp)
5523 {
5524         struct ring_info *rxp;
5525         int i;
5526
5527         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5528                 rxp = &tp->rx_std_buffers[i];
5529
5530                 if (rxp->skb == NULL)
5531                         continue;
5532                 pci_unmap_single(tp->pdev,
5533                                  pci_unmap_addr(rxp, mapping),
5534                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5535                                  PCI_DMA_FROMDEVICE);
5536                 dev_kfree_skb_any(rxp->skb);
5537                 rxp->skb = NULL;
5538         }
5539
5540         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5541                 rxp = &tp->rx_jumbo_buffers[i];
5542
5543                 if (rxp->skb == NULL)
5544                         continue;
5545                 pci_unmap_single(tp->pdev,
5546                                  pci_unmap_addr(rxp, mapping),
5547                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5548                                  PCI_DMA_FROMDEVICE);
5549                 dev_kfree_skb_any(rxp->skb);
5550                 rxp->skb = NULL;
5551         }
5552
5553         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5554                 struct tx_ring_info *txp;
5555                 struct sk_buff *skb;
5556
5557                 txp = &tp->tx_buffers[i];
5558                 skb = txp->skb;
5559
5560                 if (skb == NULL) {
5561                         i++;
5562                         continue;
5563                 }
5564
5565                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5566
5567                 txp->skb = NULL;
5568
5569                 i += skb_shinfo(skb)->nr_frags + 1;
5570
5571                 dev_kfree_skb_any(skb);
5572         }
5573 }
5574
5575 /* Initialize tx/rx rings for packet processing.
5576  *
5577  * The chip has been shut down and the driver detached from
5578  * the networking, so no interrupts or new tx packets will
5579  * end up in the driver.  tp->{tx,}lock are held and thus
5580  * we may not sleep.
5581  */
5582 static int tg3_init_rings(struct tg3 *tp)
5583 {
5584         u32 i;
5585
5586         /* Free up all the SKBs. */
5587         tg3_free_rings(tp);
5588
5589         /* Zero out all descriptors. */
5590         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5591         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5592         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5593         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5594
5595         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5596         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5597             (tp->dev->mtu > ETH_DATA_LEN))
5598                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5599
5600         /* Initialize invariants of the rings, we only set this
5601          * stuff once.  This works because the card does not
5602          * write into the rx buffer posting rings.
5603          */
5604         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5605                 struct tg3_rx_buffer_desc *rxd;
5606
5607                 rxd = &tp->rx_std[i];
5608                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5609                         << RXD_LEN_SHIFT;
5610                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5611                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5612                                (i << RXD_OPAQUE_INDEX_SHIFT));
5613         }
5614
5615         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5616                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5617                         struct tg3_rx_buffer_desc *rxd;
5618
5619                         rxd = &tp->rx_jumbo[i];
5620                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5621                                 << RXD_LEN_SHIFT;
5622                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5623                                 RXD_FLAG_JUMBO;
5624                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5625                                (i << RXD_OPAQUE_INDEX_SHIFT));
5626                 }
5627         }
5628
5629         /* Now allocate fresh SKBs for each rx ring. */
5630         for (i = 0; i < tp->rx_pending; i++) {
5631                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5632                         printk(KERN_WARNING PFX
5633                                "%s: Using a smaller RX standard ring, "
5634                                "only %d out of %d buffers were allocated "
5635                                "successfully.\n",
5636                                tp->dev->name, i, tp->rx_pending);
5637                         if (i == 0)
5638                                 return -ENOMEM;
5639                         tp->rx_pending = i;
5640                         break;
5641                 }
5642         }
5643
5644         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5645                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5646                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5647                                              -1, i) < 0) {
5648                                 printk(KERN_WARNING PFX
5649                                        "%s: Using a smaller RX jumbo ring, "
5650                                        "only %d out of %d buffers were "
5651                                        "allocated successfully.\n",
5652                                        tp->dev->name, i, tp->rx_jumbo_pending);
5653                                 if (i == 0) {
5654                                         tg3_free_rings(tp);
5655                                         return -ENOMEM;
5656                                 }
5657                                 tp->rx_jumbo_pending = i;
5658                                 break;
5659                         }
5660                 }
5661         }
5662         return 0;
5663 }
5664
5665 /*
5666  * Must not be invoked with interrupt sources disabled and
5667  * the hardware shutdown down.
5668  */
5669 static void tg3_free_consistent(struct tg3 *tp)
5670 {
5671         kfree(tp->rx_std_buffers);
5672         tp->rx_std_buffers = NULL;
5673         if (tp->rx_std) {
5674                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5675                                     tp->rx_std, tp->rx_std_mapping);
5676                 tp->rx_std = NULL;
5677         }
5678         if (tp->rx_jumbo) {
5679                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5680                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5681                 tp->rx_jumbo = NULL;
5682         }
5683         if (tp->rx_rcb) {
5684                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5685                                     tp->rx_rcb, tp->rx_rcb_mapping);
5686                 tp->rx_rcb = NULL;
5687         }
5688         if (tp->tx_ring) {
5689                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5690                         tp->tx_ring, tp->tx_desc_mapping);
5691                 tp->tx_ring = NULL;
5692         }
5693         if (tp->hw_status) {
5694                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5695                                     tp->hw_status, tp->status_mapping);
5696                 tp->hw_status = NULL;
5697         }
5698         if (tp->hw_stats) {
5699                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5700                                     tp->hw_stats, tp->stats_mapping);
5701                 tp->hw_stats = NULL;
5702         }
5703 }
5704
5705 /*
5706  * Must not be invoked with interrupt sources disabled and
5707  * the hardware shutdown down.  Can sleep.
5708  */
5709 static int tg3_alloc_consistent(struct tg3 *tp)
5710 {
5711         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5712                                       (TG3_RX_RING_SIZE +
5713                                        TG3_RX_JUMBO_RING_SIZE)) +
5714                                      (sizeof(struct tx_ring_info) *
5715                                       TG3_TX_RING_SIZE),
5716                                      GFP_KERNEL);
5717         if (!tp->rx_std_buffers)
5718                 return -ENOMEM;
5719
5720         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5721         tp->tx_buffers = (struct tx_ring_info *)
5722                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5723
5724         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5725                                           &tp->rx_std_mapping);
5726         if (!tp->rx_std)
5727                 goto err_out;
5728
5729         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5730                                             &tp->rx_jumbo_mapping);
5731
5732         if (!tp->rx_jumbo)
5733                 goto err_out;
5734
5735         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5736                                           &tp->rx_rcb_mapping);
5737         if (!tp->rx_rcb)
5738                 goto err_out;
5739
5740         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5741                                            &tp->tx_desc_mapping);
5742         if (!tp->tx_ring)
5743                 goto err_out;
5744
5745         tp->hw_status = pci_alloc_consistent(tp->pdev,
5746                                              TG3_HW_STATUS_SIZE,
5747                                              &tp->status_mapping);
5748         if (!tp->hw_status)
5749                 goto err_out;
5750
5751         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5752                                             sizeof(struct tg3_hw_stats),
5753                                             &tp->stats_mapping);
5754         if (!tp->hw_stats)
5755                 goto err_out;
5756
5757         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5758         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5759
5760         return 0;
5761
5762 err_out:
5763         tg3_free_consistent(tp);
5764         return -ENOMEM;
5765 }
5766
5767 #define MAX_WAIT_CNT 1000
5768
5769 /* To stop a block, clear the enable bit and poll till it
5770  * clears.  tp->lock is held.
5771  */
5772 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5773 {
5774         unsigned int i;
5775         u32 val;
5776
5777         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5778                 switch (ofs) {
5779                 case RCVLSC_MODE:
5780                 case DMAC_MODE:
5781                 case MBFREE_MODE:
5782                 case BUFMGR_MODE:
5783                 case MEMARB_MODE:
5784                         /* We can't enable/disable these bits of the
5785                          * 5705/5750, just say success.
5786                          */
5787                         return 0;
5788
5789                 default:
5790                         break;
5791                 }
5792         }
5793
5794         val = tr32(ofs);
5795         val &= ~enable_bit;
5796         tw32_f(ofs, val);
5797
5798         for (i = 0; i < MAX_WAIT_CNT; i++) {
5799                 udelay(100);
5800                 val = tr32(ofs);
5801                 if ((val & enable_bit) == 0)
5802                         break;
5803         }
5804
5805         if (i == MAX_WAIT_CNT && !silent) {
5806                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5807                        "ofs=%lx enable_bit=%x\n",
5808                        ofs, enable_bit);
5809                 return -ENODEV;
5810         }
5811
5812         return 0;
5813 }
5814
5815 /* tp->lock is held. */
5816 static int tg3_abort_hw(struct tg3 *tp, int silent)
5817 {
5818         int i, err;
5819
5820         tg3_disable_ints(tp);
5821
5822         tp->rx_mode &= ~RX_MODE_ENABLE;
5823         tw32_f(MAC_RX_MODE, tp->rx_mode);
5824         udelay(10);
5825
5826         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5827         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5828         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5829         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5830         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5831         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5832
5833         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5834         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5835         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5836         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5837         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5838         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5839         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5840
5841         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5842         tw32_f(MAC_MODE, tp->mac_mode);
5843         udelay(40);
5844
5845         tp->tx_mode &= ~TX_MODE_ENABLE;
5846         tw32_f(MAC_TX_MODE, tp->tx_mode);
5847
5848         for (i = 0; i < MAX_WAIT_CNT; i++) {
5849                 udelay(100);
5850                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5851                         break;
5852         }
5853         if (i >= MAX_WAIT_CNT) {
5854                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5855                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5856                        tp->dev->name, tr32(MAC_TX_MODE));
5857                 err |= -ENODEV;
5858         }
5859
5860         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5861         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5862         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5863
5864         tw32(FTQ_RESET, 0xffffffff);
5865         tw32(FTQ_RESET, 0x00000000);
5866
5867         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5868         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5869
5870         if (tp->hw_status)
5871                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5872         if (tp->hw_stats)
5873                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5874
5875         return err;
5876 }
5877
5878 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5879 {
5880         int i;
5881         u32 apedata;
5882
5883         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5884         if (apedata != APE_SEG_SIG_MAGIC)
5885                 return;
5886
5887         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5888         if (!(apedata & APE_FW_STATUS_READY))
5889                 return;
5890
5891         /* Wait for up to 1 millisecond for APE to service previous event. */
5892         for (i = 0; i < 10; i++) {
5893                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5894                         return;
5895
5896                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5897
5898                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5899                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5900                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5901
5902                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5903
5904                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5905                         break;
5906
5907                 udelay(100);
5908         }
5909
5910         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5911                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5912 }
5913
5914 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5915 {
5916         u32 event;
5917         u32 apedata;
5918
5919         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5920                 return;
5921
5922         switch (kind) {
5923                 case RESET_KIND_INIT:
5924                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5925                                         APE_HOST_SEG_SIG_MAGIC);
5926                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5927                                         APE_HOST_SEG_LEN_MAGIC);
5928                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5929                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5930                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5931                                         APE_HOST_DRIVER_ID_MAGIC);
5932                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5933                                         APE_HOST_BEHAV_NO_PHYLOCK);
5934
5935                         event = APE_EVENT_STATUS_STATE_START;
5936                         break;
5937                 case RESET_KIND_SHUTDOWN:
5938                         /* With the interface we are currently using,
5939                          * APE does not track driver state.  Wiping
5940                          * out the HOST SEGMENT SIGNATURE forces
5941                          * the APE to assume OS absent status.
5942                          */
5943                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5944
5945                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5946                         break;
5947                 case RESET_KIND_SUSPEND:
5948                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5949                         break;
5950                 default:
5951                         return;
5952         }
5953
5954         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5955
5956         tg3_ape_send_event(tp, event);
5957 }
5958
5959 /* tp->lock is held. */
5960 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5961 {
5962         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5963                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5964
5965         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5966                 switch (kind) {
5967                 case RESET_KIND_INIT:
5968                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5969                                       DRV_STATE_START);
5970                         break;
5971
5972                 case RESET_KIND_SHUTDOWN:
5973                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5974                                       DRV_STATE_UNLOAD);
5975                         break;
5976
5977                 case RESET_KIND_SUSPEND:
5978                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5979                                       DRV_STATE_SUSPEND);
5980                         break;
5981
5982                 default:
5983                         break;
5984                 }
5985         }
5986
5987         if (kind == RESET_KIND_INIT ||
5988             kind == RESET_KIND_SUSPEND)
5989                 tg3_ape_driver_state_change(tp, kind);
5990 }
5991
5992 /* tp->lock is held. */
5993 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5994 {
5995         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5996                 switch (kind) {
5997                 case RESET_KIND_INIT:
5998                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5999                                       DRV_STATE_START_DONE);
6000                         break;
6001
6002                 case RESET_KIND_SHUTDOWN:
6003                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6004                                       DRV_STATE_UNLOAD_DONE);
6005                         break;
6006
6007                 default:
6008                         break;
6009                 }
6010         }
6011
6012         if (kind == RESET_KIND_SHUTDOWN)
6013                 tg3_ape_driver_state_change(tp, kind);
6014 }
6015
6016 /* tp->lock is held. */
6017 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6018 {
6019         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6020                 switch (kind) {
6021                 case RESET_KIND_INIT:
6022                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6023                                       DRV_STATE_START);
6024                         break;
6025
6026                 case RESET_KIND_SHUTDOWN:
6027                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6028                                       DRV_STATE_UNLOAD);
6029                         break;
6030
6031                 case RESET_KIND_SUSPEND:
6032                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6033                                       DRV_STATE_SUSPEND);
6034                         break;
6035
6036                 default:
6037                         break;
6038                 }
6039         }
6040 }
6041
6042 static int tg3_poll_fw(struct tg3 *tp)
6043 {
6044         int i;
6045         u32 val;
6046
6047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6048                 /* Wait up to 20ms for init done. */
6049                 for (i = 0; i < 200; i++) {
6050                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6051                                 return 0;
6052                         udelay(100);
6053                 }
6054                 return -ENODEV;
6055         }
6056
6057         /* Wait for firmware initialization to complete. */
6058         for (i = 0; i < 100000; i++) {
6059                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6060                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6061                         break;
6062                 udelay(10);
6063         }
6064
6065         /* Chip might not be fitted with firmware.  Some Sun onboard
6066          * parts are configured like that.  So don't signal the timeout
6067          * of the above loop as an error, but do report the lack of
6068          * running firmware once.
6069          */
6070         if (i >= 100000 &&
6071             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6072                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6073
6074                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6075                        tp->dev->name);
6076         }
6077
6078         return 0;
6079 }
6080
6081 /* Save PCI command register before chip reset */
6082 static void tg3_save_pci_state(struct tg3 *tp)
6083 {
6084         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6085 }
6086
6087 /* Restore PCI state after chip reset */
6088 static void tg3_restore_pci_state(struct tg3 *tp)
6089 {
6090         u32 val;
6091
6092         /* Re-enable indirect register accesses. */
6093         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6094                                tp->misc_host_ctrl);
6095
6096         /* Set MAX PCI retry to zero. */
6097         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6098         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6099             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6100                 val |= PCISTATE_RETRY_SAME_DMA;
6101         /* Allow reads and writes to the APE register and memory space. */
6102         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6103                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6104                        PCISTATE_ALLOW_APE_SHMEM_WR;
6105         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6106
6107         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6108
6109         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6110                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6111                         pcie_set_readrq(tp->pdev, 4096);
6112                 else {
6113                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6114                                               tp->pci_cacheline_sz);
6115                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6116                                               tp->pci_lat_timer);
6117                 }
6118         }
6119
6120         /* Make sure PCI-X relaxed ordering bit is clear. */
6121         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6122                 u16 pcix_cmd;
6123
6124                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6125                                      &pcix_cmd);
6126                 pcix_cmd &= ~PCI_X_CMD_ERO;
6127                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6128                                       pcix_cmd);
6129         }
6130
6131         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6132
6133                 /* Chip reset on 5780 will reset MSI enable bit,
6134                  * so need to restore it.
6135                  */
6136                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6137                         u16 ctrl;
6138
6139                         pci_read_config_word(tp->pdev,
6140                                              tp->msi_cap + PCI_MSI_FLAGS,
6141                                              &ctrl);
6142                         pci_write_config_word(tp->pdev,
6143                                               tp->msi_cap + PCI_MSI_FLAGS,
6144                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6145                         val = tr32(MSGINT_MODE);
6146                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6147                 }
6148         }
6149 }
6150
6151 static void tg3_stop_fw(struct tg3 *);
6152
6153 /* tp->lock is held. */
6154 static int tg3_chip_reset(struct tg3 *tp)
6155 {
6156         u32 val;
6157         void (*write_op)(struct tg3 *, u32, u32);
6158         int err;
6159
6160         tg3_nvram_lock(tp);
6161
6162         tg3_mdio_stop(tp);
6163
6164         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6165
6166         /* No matching tg3_nvram_unlock() after this because
6167          * chip reset below will undo the nvram lock.
6168          */
6169         tp->nvram_lock_cnt = 0;
6170
6171         /* GRC_MISC_CFG core clock reset will clear the memory
6172          * enable bit in PCI register 4 and the MSI enable bit
6173          * on some chips, so we save relevant registers here.
6174          */
6175         tg3_save_pci_state(tp);
6176
6177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6178             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6179                 tw32(GRC_FASTBOOT_PC, 0);
6180
6181         /*
6182          * We must avoid the readl() that normally takes place.
6183          * It locks machines, causes machine checks, and other
6184          * fun things.  So, temporarily disable the 5701
6185          * hardware workaround, while we do the reset.
6186          */
6187         write_op = tp->write32;
6188         if (write_op == tg3_write_flush_reg32)
6189                 tp->write32 = tg3_write32;
6190
6191         /* Prevent the irq handler from reading or writing PCI registers
6192          * during chip reset when the memory enable bit in the PCI command
6193          * register may be cleared.  The chip does not generate interrupt
6194          * at this time, but the irq handler may still be called due to irq
6195          * sharing or irqpoll.
6196          */
6197         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6198         if (tp->hw_status) {
6199                 tp->hw_status->status = 0;
6200                 tp->hw_status->status_tag = 0;
6201         }
6202         tp->last_tag = 0;
6203         tp->last_irq_tag = 0;
6204         smp_mb();
6205         synchronize_irq(tp->pdev->irq);
6206
6207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6208                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6209                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6210         }
6211
6212         /* do the reset */
6213         val = GRC_MISC_CFG_CORECLK_RESET;
6214
6215         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6216                 if (tr32(0x7e2c) == 0x60) {
6217                         tw32(0x7e2c, 0x20);
6218                 }
6219                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6220                         tw32(GRC_MISC_CFG, (1 << 29));
6221                         val |= (1 << 29);
6222                 }
6223         }
6224
6225         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6226                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6227                 tw32(GRC_VCPU_EXT_CTRL,
6228                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6229         }
6230
6231         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6232                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6233         tw32(GRC_MISC_CFG, val);
6234
6235         /* restore 5701 hardware bug workaround write method */
6236         tp->write32 = write_op;
6237
6238         /* Unfortunately, we have to delay before the PCI read back.
6239          * Some 575X chips even will not respond to a PCI cfg access
6240          * when the reset command is given to the chip.
6241          *
6242          * How do these hardware designers expect things to work
6243          * properly if the PCI write is posted for a long period
6244          * of time?  It is always necessary to have some method by
6245          * which a register read back can occur to push the write
6246          * out which does the reset.
6247          *
6248          * For most tg3 variants the trick below was working.
6249          * Ho hum...
6250          */
6251         udelay(120);
6252
6253         /* Flush PCI posted writes.  The normal MMIO registers
6254          * are inaccessible at this time so this is the only
6255          * way to make this reliably (actually, this is no longer
6256          * the case, see above).  I tried to use indirect
6257          * register read/write but this upset some 5701 variants.
6258          */
6259         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6260
6261         udelay(120);
6262
6263         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6264                 u16 val16;
6265
6266                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6267                         int i;
6268                         u32 cfg_val;
6269
6270                         /* Wait for link training to complete.  */
6271                         for (i = 0; i < 5000; i++)
6272                                 udelay(100);
6273
6274                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6275                         pci_write_config_dword(tp->pdev, 0xc4,
6276                                                cfg_val | (1 << 15));
6277                 }
6278
6279                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6280                 pci_read_config_word(tp->pdev,
6281                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6282                                      &val16);
6283                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6284                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6285                 /*
6286                  * Older PCIe devices only support the 128 byte
6287                  * MPS setting.  Enforce the restriction.
6288                  */
6289                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6290                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6291                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6292                 pci_write_config_word(tp->pdev,
6293                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6294                                       val16);
6295
6296                 pcie_set_readrq(tp->pdev, 4096);
6297
6298                 /* Clear error status */
6299                 pci_write_config_word(tp->pdev,
6300                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6301                                       PCI_EXP_DEVSTA_CED |
6302                                       PCI_EXP_DEVSTA_NFED |
6303                                       PCI_EXP_DEVSTA_FED |
6304                                       PCI_EXP_DEVSTA_URD);
6305         }
6306
6307         tg3_restore_pci_state(tp);
6308
6309         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6310
6311         val = 0;
6312         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6313                 val = tr32(MEMARB_MODE);
6314         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6315
6316         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6317                 tg3_stop_fw(tp);
6318                 tw32(0x5000, 0x400);
6319         }
6320
6321         tw32(GRC_MODE, tp->grc_mode);
6322
6323         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6324                 val = tr32(0xc4);
6325
6326                 tw32(0xc4, val | (1 << 15));
6327         }
6328
6329         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6330             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6331                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6332                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6333                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6334                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6335         }
6336
6337         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6338                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6339                 tw32_f(MAC_MODE, tp->mac_mode);
6340         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6341                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6342                 tw32_f(MAC_MODE, tp->mac_mode);
6343         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6344                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6345                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6346                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6347                 tw32_f(MAC_MODE, tp->mac_mode);
6348         } else
6349                 tw32_f(MAC_MODE, 0);
6350         udelay(40);
6351
6352         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6353
6354         err = tg3_poll_fw(tp);
6355         if (err)
6356                 return err;
6357
6358         tg3_mdio_start(tp);
6359
6360         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6361             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6362                 val = tr32(0x7c00);
6363
6364                 tw32(0x7c00, val | (1 << 25));
6365         }
6366
6367         /* Reprobe ASF enable state.  */
6368         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6369         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6370         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6371         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6372                 u32 nic_cfg;
6373
6374                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6375                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6376                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6377                         tp->last_event_jiffies = jiffies;
6378                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6379                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6380                 }
6381         }
6382
6383         return 0;
6384 }
6385
6386 /* tp->lock is held. */
6387 static void tg3_stop_fw(struct tg3 *tp)
6388 {
6389         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6390            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6391                 /* Wait for RX cpu to ACK the previous event. */
6392                 tg3_wait_for_event_ack(tp);
6393
6394                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6395
6396                 tg3_generate_fw_event(tp);
6397
6398                 /* Wait for RX cpu to ACK this event. */
6399                 tg3_wait_for_event_ack(tp);
6400         }
6401 }
6402
6403 /* tp->lock is held. */
6404 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6405 {
6406         int err;
6407
6408         tg3_stop_fw(tp);
6409
6410         tg3_write_sig_pre_reset(tp, kind);
6411
6412         tg3_abort_hw(tp, silent);
6413         err = tg3_chip_reset(tp);
6414
6415         __tg3_set_mac_addr(tp, 0);
6416
6417         tg3_write_sig_legacy(tp, kind);
6418         tg3_write_sig_post_reset(tp, kind);
6419
6420         if (err)
6421                 return err;
6422
6423         return 0;
6424 }
6425
6426 #define RX_CPU_SCRATCH_BASE     0x30000
6427 #define RX_CPU_SCRATCH_SIZE     0x04000
6428 #define TX_CPU_SCRATCH_BASE     0x34000
6429 #define TX_CPU_SCRATCH_SIZE     0x04000
6430
6431 /* tp->lock is held. */
6432 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6433 {
6434         int i;
6435
6436         BUG_ON(offset == TX_CPU_BASE &&
6437             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6438
6439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6440                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6441
6442                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6443                 return 0;
6444         }
6445         if (offset == RX_CPU_BASE) {
6446                 for (i = 0; i < 10000; i++) {
6447                         tw32(offset + CPU_STATE, 0xffffffff);
6448                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6449                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6450                                 break;
6451                 }
6452
6453                 tw32(offset + CPU_STATE, 0xffffffff);
6454                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6455                 udelay(10);
6456         } else {
6457                 for (i = 0; i < 10000; i++) {
6458                         tw32(offset + CPU_STATE, 0xffffffff);
6459                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6460                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6461                                 break;
6462                 }
6463         }
6464
6465         if (i >= 10000) {
6466                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6467                        "and %s CPU\n",
6468                        tp->dev->name,
6469                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6470                 return -ENODEV;
6471         }
6472
6473         /* Clear firmware's nvram arbitration. */
6474         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6475                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6476         return 0;
6477 }
6478
6479 struct fw_info {
6480         unsigned int fw_base;
6481         unsigned int fw_len;
6482         const __be32 *fw_data;
6483 };
6484
6485 /* tp->lock is held. */
6486 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6487                                  int cpu_scratch_size, struct fw_info *info)
6488 {
6489         int err, lock_err, i;
6490         void (*write_op)(struct tg3 *, u32, u32);
6491
6492         if (cpu_base == TX_CPU_BASE &&
6493             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6494                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6495                        "TX cpu firmware on %s which is 5705.\n",
6496                        tp->dev->name);
6497                 return -EINVAL;
6498         }
6499
6500         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6501                 write_op = tg3_write_mem;
6502         else
6503                 write_op = tg3_write_indirect_reg32;
6504
6505         /* It is possible that bootcode is still loading at this point.
6506          * Get the nvram lock first before halting the cpu.
6507          */
6508         lock_err = tg3_nvram_lock(tp);
6509         err = tg3_halt_cpu(tp, cpu_base);
6510         if (!lock_err)
6511                 tg3_nvram_unlock(tp);
6512         if (err)
6513                 goto out;
6514
6515         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6516                 write_op(tp, cpu_scratch_base + i, 0);
6517         tw32(cpu_base + CPU_STATE, 0xffffffff);
6518         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6519         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6520                 write_op(tp, (cpu_scratch_base +
6521                               (info->fw_base & 0xffff) +
6522                               (i * sizeof(u32))),
6523                               be32_to_cpu(info->fw_data[i]));
6524
6525         err = 0;
6526
6527 out:
6528         return err;
6529 }
6530
6531 /* tp->lock is held. */
6532 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6533 {
6534         struct fw_info info;
6535         const __be32 *fw_data;
6536         int err, i;
6537
6538         fw_data = (void *)tp->fw->data;
6539
6540         /* Firmware blob starts with version numbers, followed by
6541            start address and length. We are setting complete length.
6542            length = end_address_of_bss - start_address_of_text.
6543            Remainder is the blob to be loaded contiguously
6544            from start address. */
6545
6546         info.fw_base = be32_to_cpu(fw_data[1]);
6547         info.fw_len = tp->fw->size - 12;
6548         info.fw_data = &fw_data[3];
6549
6550         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6551                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6552                                     &info);
6553         if (err)
6554                 return err;
6555
6556         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6557                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6558                                     &info);
6559         if (err)
6560                 return err;
6561
6562         /* Now startup only the RX cpu. */
6563         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6564         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6565
6566         for (i = 0; i < 5; i++) {
6567                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6568                         break;
6569                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6570                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6571                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6572                 udelay(1000);
6573         }
6574         if (i >= 5) {
6575                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6576                        "to set RX CPU PC, is %08x should be %08x\n",
6577                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6578                        info.fw_base);
6579                 return -ENODEV;
6580         }
6581         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6582         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6583
6584         return 0;
6585 }
6586
6587 /* 5705 needs a special version of the TSO firmware.  */
6588
6589 /* tp->lock is held. */
6590 static int tg3_load_tso_firmware(struct tg3 *tp)
6591 {
6592         struct fw_info info;
6593         const __be32 *fw_data;
6594         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6595         int err, i;
6596
6597         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6598                 return 0;
6599
6600         fw_data = (void *)tp->fw->data;
6601
6602         /* Firmware blob starts with version numbers, followed by
6603            start address and length. We are setting complete length.
6604            length = end_address_of_bss - start_address_of_text.
6605            Remainder is the blob to be loaded contiguously
6606            from start address. */
6607
6608         info.fw_base = be32_to_cpu(fw_data[1]);
6609         cpu_scratch_size = tp->fw_len;
6610         info.fw_len = tp->fw->size - 12;
6611         info.fw_data = &fw_data[3];
6612
6613         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6614                 cpu_base = RX_CPU_BASE;
6615                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6616         } else {
6617                 cpu_base = TX_CPU_BASE;
6618                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6619                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6620         }
6621
6622         err = tg3_load_firmware_cpu(tp, cpu_base,
6623                                     cpu_scratch_base, cpu_scratch_size,
6624                                     &info);
6625         if (err)
6626                 return err;
6627
6628         /* Now startup the cpu. */
6629         tw32(cpu_base + CPU_STATE, 0xffffffff);
6630         tw32_f(cpu_base + CPU_PC, info.fw_base);
6631
6632         for (i = 0; i < 5; i++) {
6633                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6634                         break;
6635                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6636                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6637                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6638                 udelay(1000);
6639         }
6640         if (i >= 5) {
6641                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6642                        "to set CPU PC, is %08x should be %08x\n",
6643                        tp->dev->name, tr32(cpu_base + CPU_PC),
6644                        info.fw_base);
6645                 return -ENODEV;
6646         }
6647         tw32(cpu_base + CPU_STATE, 0xffffffff);
6648         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6649         return 0;
6650 }
6651
6652
6653 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6654 {
6655         struct tg3 *tp = netdev_priv(dev);
6656         struct sockaddr *addr = p;
6657         int err = 0, skip_mac_1 = 0;
6658
6659         if (!is_valid_ether_addr(addr->sa_data))
6660                 return -EINVAL;
6661
6662         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6663
6664         if (!netif_running(dev))
6665                 return 0;
6666
6667         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6668                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6669
6670                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6671                 addr0_low = tr32(MAC_ADDR_0_LOW);
6672                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6673                 addr1_low = tr32(MAC_ADDR_1_LOW);
6674
6675                 /* Skip MAC addr 1 if ASF is using it. */
6676                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6677                     !(addr1_high == 0 && addr1_low == 0))
6678                         skip_mac_1 = 1;
6679         }
6680         spin_lock_bh(&tp->lock);
6681         __tg3_set_mac_addr(tp, skip_mac_1);
6682         spin_unlock_bh(&tp->lock);
6683
6684         return err;
6685 }
6686
6687 /* tp->lock is held. */
6688 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6689                            dma_addr_t mapping, u32 maxlen_flags,
6690                            u32 nic_addr)
6691 {
6692         tg3_write_mem(tp,
6693                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6694                       ((u64) mapping >> 32));
6695         tg3_write_mem(tp,
6696                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6697                       ((u64) mapping & 0xffffffff));
6698         tg3_write_mem(tp,
6699                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6700                        maxlen_flags);
6701
6702         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6703                 tg3_write_mem(tp,
6704                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6705                               nic_addr);
6706 }
6707
6708 static void __tg3_set_rx_mode(struct net_device *);
6709 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6710 {
6711         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6712         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6713         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6714         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6715         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6716                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6717                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6718         }
6719         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6720         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6721         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6722                 u32 val = ec->stats_block_coalesce_usecs;
6723
6724                 if (!netif_carrier_ok(tp->dev))
6725                         val = 0;
6726
6727                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6728         }
6729 }
6730
6731 /* tp->lock is held. */
6732 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6733 {
6734         u32 val, rdmac_mode;
6735         int i, err, limit;
6736
6737         tg3_disable_ints(tp);
6738
6739         tg3_stop_fw(tp);
6740
6741         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6742
6743         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6744                 tg3_abort_hw(tp, 1);
6745         }
6746
6747         if (reset_phy &&
6748             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6749                 tg3_phy_reset(tp);
6750
6751         err = tg3_chip_reset(tp);
6752         if (err)
6753                 return err;
6754
6755         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6756
6757         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6758                 val = tr32(TG3_CPMU_CTRL);
6759                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6760                 tw32(TG3_CPMU_CTRL, val);
6761
6762                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6763                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6764                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6765                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6766
6767                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6768                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6769                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6770                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6771
6772                 val = tr32(TG3_CPMU_HST_ACC);
6773                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6774                 val |= CPMU_HST_ACC_MACCLK_6_25;
6775                 tw32(TG3_CPMU_HST_ACC, val);
6776         }
6777
6778         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6779                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6780                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6781                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6782                 tw32(PCIE_PWR_MGMT_THRESH, val);
6783
6784                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6785                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6786
6787                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6788         }
6789
6790         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6791                 val = tr32(TG3_PCIE_LNKCTL);
6792                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6793                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6794                 else
6795                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6796                 tw32(TG3_PCIE_LNKCTL, val);
6797         }
6798
6799         /* This works around an issue with Athlon chipsets on
6800          * B3 tigon3 silicon.  This bit has no effect on any
6801          * other revision.  But do not set this on PCI Express
6802          * chips and don't even touch the clocks if the CPMU is present.
6803          */
6804         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6805                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6806                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6807                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6808         }
6809
6810         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6811             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6812                 val = tr32(TG3PCI_PCISTATE);
6813                 val |= PCISTATE_RETRY_SAME_DMA;
6814                 tw32(TG3PCI_PCISTATE, val);
6815         }
6816
6817         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6818                 /* Allow reads and writes to the
6819                  * APE register and memory space.
6820                  */
6821                 val = tr32(TG3PCI_PCISTATE);
6822                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6823                        PCISTATE_ALLOW_APE_SHMEM_WR;
6824                 tw32(TG3PCI_PCISTATE, val);
6825         }
6826
6827         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6828                 /* Enable some hw fixes.  */
6829                 val = tr32(TG3PCI_MSI_DATA);
6830                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6831                 tw32(TG3PCI_MSI_DATA, val);
6832         }
6833
6834         /* Descriptor ring init may make accesses to the
6835          * NIC SRAM area to setup the TX descriptors, so we
6836          * can only do this after the hardware has been
6837          * successfully reset.
6838          */
6839         err = tg3_init_rings(tp);
6840         if (err)
6841                 return err;
6842
6843         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6844             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6845                 /* This value is determined during the probe time DMA
6846                  * engine test, tg3_test_dma.
6847                  */
6848                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6849         }
6850
6851         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6852                           GRC_MODE_4X_NIC_SEND_RINGS |
6853                           GRC_MODE_NO_TX_PHDR_CSUM |
6854                           GRC_MODE_NO_RX_PHDR_CSUM);
6855         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6856
6857         /* Pseudo-header checksum is done by hardware logic and not
6858          * the offload processers, so make the chip do the pseudo-
6859          * header checksums on receive.  For transmit it is more
6860          * convenient to do the pseudo-header checksum in software
6861          * as Linux does that on transmit for us in all cases.
6862          */
6863         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6864
6865         tw32(GRC_MODE,
6866              tp->grc_mode |
6867              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6868
6869         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6870         val = tr32(GRC_MISC_CFG);
6871         val &= ~0xff;
6872         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6873         tw32(GRC_MISC_CFG, val);
6874
6875         /* Initialize MBUF/DESC pool. */
6876         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6877                 /* Do nothing.  */
6878         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6879                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6880                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6881                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6882                 else
6883                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6884                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6885                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6886         }
6887         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6888                 int fw_len;
6889
6890                 fw_len = tp->fw_len;
6891                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6892                 tw32(BUFMGR_MB_POOL_ADDR,
6893                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6894                 tw32(BUFMGR_MB_POOL_SIZE,
6895                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6896         }
6897
6898         if (tp->dev->mtu <= ETH_DATA_LEN) {
6899                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6900                      tp->bufmgr_config.mbuf_read_dma_low_water);
6901                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6902                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6903                 tw32(BUFMGR_MB_HIGH_WATER,
6904                      tp->bufmgr_config.mbuf_high_water);
6905         } else {
6906                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6907                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6908                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6909                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6910                 tw32(BUFMGR_MB_HIGH_WATER,
6911                      tp->bufmgr_config.mbuf_high_water_jumbo);
6912         }
6913         tw32(BUFMGR_DMA_LOW_WATER,
6914              tp->bufmgr_config.dma_low_water);
6915         tw32(BUFMGR_DMA_HIGH_WATER,
6916              tp->bufmgr_config.dma_high_water);
6917
6918         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6919         for (i = 0; i < 2000; i++) {
6920                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6921                         break;
6922                 udelay(10);
6923         }
6924         if (i >= 2000) {
6925                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6926                        tp->dev->name);
6927                 return -ENODEV;
6928         }
6929
6930         /* Setup replenish threshold. */
6931         val = tp->rx_pending / 8;
6932         if (val == 0)
6933                 val = 1;
6934         else if (val > tp->rx_std_max_post)
6935                 val = tp->rx_std_max_post;
6936         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6937                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6938                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6939
6940                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6941                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6942         }
6943
6944         tw32(RCVBDI_STD_THRESH, val);
6945
6946         /* Initialize TG3_BDINFO's at:
6947          *  RCVDBDI_STD_BD:     standard eth size rx ring
6948          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6949          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6950          *
6951          * like so:
6952          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6953          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6954          *                              ring attribute flags
6955          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6956          *
6957          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6958          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6959          *
6960          * The size of each ring is fixed in the firmware, but the location is
6961          * configurable.
6962          */
6963         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6964              ((u64) tp->rx_std_mapping >> 32));
6965         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6966              ((u64) tp->rx_std_mapping & 0xffffffff));
6967         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6968              NIC_SRAM_RX_BUFFER_DESC);
6969
6970         /* Disable the mini ring */
6971         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6972                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6973                      BDINFO_FLAGS_DISABLED);
6974
6975         /* Program the jumbo buffer descriptor ring control
6976          * blocks on those devices that have them.
6977          */
6978         if ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) &&
6979             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6980                 /* Setup replenish threshold. */
6981                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6982
6983                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6984                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6985                              ((u64) tp->rx_jumbo_mapping >> 32));
6986                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6987                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6988                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6989                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6990                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6991                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6992                 } else {
6993                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6994                              BDINFO_FLAGS_DISABLED);
6995                 }
6996
6997                 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
6998         } else
6999                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7000
7001         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7002
7003         /* There is only one send ring on 5705/5750, no need to explicitly
7004          * disable the others.
7005          */
7006         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7007                 /* Clear out send RCB ring in SRAM. */
7008                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7009                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7010                                       BDINFO_FLAGS_DISABLED);
7011         }
7012
7013         tp->tx_prod = 0;
7014         tp->tx_cons = 0;
7015         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7016         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7017
7018         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7019                        tp->tx_desc_mapping,
7020                        (TG3_TX_RING_SIZE <<
7021                         BDINFO_FLAGS_MAXLEN_SHIFT),
7022                        NIC_SRAM_TX_BUFFER_DESC);
7023
7024         /* There is only one receive return ring on 5705/5750, no need
7025          * to explicitly disable the others.
7026          */
7027         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7028                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7029                      i += TG3_BDINFO_SIZE) {
7030                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7031                                       BDINFO_FLAGS_DISABLED);
7032                 }
7033         }
7034
7035         tp->rx_rcb_ptr = 0;
7036         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7037
7038         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7039                        tp->rx_rcb_mapping,
7040                        (TG3_RX_RCB_RING_SIZE(tp) <<
7041                         BDINFO_FLAGS_MAXLEN_SHIFT),
7042                        0);
7043
7044         tp->rx_std_ptr = tp->rx_pending;
7045         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7046                      tp->rx_std_ptr);
7047
7048         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7049                                                 tp->rx_jumbo_pending : 0;
7050         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7051                      tp->rx_jumbo_ptr);
7052
7053         /* Initialize MAC address and backoff seed. */
7054         __tg3_set_mac_addr(tp, 0);
7055
7056         /* MTU + ethernet header + FCS + optional VLAN tag */
7057         tw32(MAC_RX_MTU_SIZE,
7058              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7059
7060         /* The slot time is changed by tg3_setup_phy if we
7061          * run at gigabit with half duplex.
7062          */
7063         tw32(MAC_TX_LENGTHS,
7064              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7065              (6 << TX_LENGTHS_IPG_SHIFT) |
7066              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7067
7068         /* Receive rules. */
7069         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7070         tw32(RCVLPC_CONFIG, 0x0181);
7071
7072         /* Calculate RDMAC_MODE setting early, we need it to determine
7073          * the RCVLPC_STATE_ENABLE mask.
7074          */
7075         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7076                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7077                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7078                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7079                       RDMAC_MODE_LNGREAD_ENAB);
7080
7081         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7082             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7083             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7084                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7085                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7086                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7087
7088         /* If statement applies to 5705 and 5750 PCI devices only */
7089         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7090              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7091             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7092                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7094                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7095                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7096                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7097                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7098                 }
7099         }
7100
7101         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7102                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7103
7104         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7105                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7106
7107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7109                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7110
7111         /* Receive/send statistics. */
7112         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7113                 val = tr32(RCVLPC_STATS_ENABLE);
7114                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7115                 tw32(RCVLPC_STATS_ENABLE, val);
7116         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7117                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7118                 val = tr32(RCVLPC_STATS_ENABLE);
7119                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7120                 tw32(RCVLPC_STATS_ENABLE, val);
7121         } else {
7122                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7123         }
7124         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7125         tw32(SNDDATAI_STATSENAB, 0xffffff);
7126         tw32(SNDDATAI_STATSCTRL,
7127              (SNDDATAI_SCTRL_ENABLE |
7128               SNDDATAI_SCTRL_FASTUPD));
7129
7130         /* Setup host coalescing engine. */
7131         tw32(HOSTCC_MODE, 0);
7132         for (i = 0; i < 2000; i++) {
7133                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7134                         break;
7135                 udelay(10);
7136         }
7137
7138         __tg3_set_coalesce(tp, &tp->coal);
7139
7140         /* set status block DMA address */
7141         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7142              ((u64) tp->status_mapping >> 32));
7143         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7144              ((u64) tp->status_mapping & 0xffffffff));
7145
7146         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7147                 /* Status/statistics block address.  See tg3_timer,
7148                  * the tg3_periodic_fetch_stats call there, and
7149                  * tg3_get_stats to see how this works for 5705/5750 chips.
7150                  */
7151                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7152                      ((u64) tp->stats_mapping >> 32));
7153                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7154                      ((u64) tp->stats_mapping & 0xffffffff));
7155                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7156                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7157         }
7158
7159         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7160
7161         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7162         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7163         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7164                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7165
7166         /* Clear statistics/status block in chip, and status block in ram. */
7167         for (i = NIC_SRAM_STATS_BLK;
7168              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7169              i += sizeof(u32)) {
7170                 tg3_write_mem(tp, i, 0);
7171                 udelay(40);
7172         }
7173         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7174
7175         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7176                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7177                 /* reset to prevent losing 1st rx packet intermittently */
7178                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7179                 udelay(10);
7180         }
7181
7182         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7183                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7184         else
7185                 tp->mac_mode = 0;
7186         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7187                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7188         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7189             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7190             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7191                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7192         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7193         udelay(40);
7194
7195         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7196          * If TG3_FLG2_IS_NIC is zero, we should read the
7197          * register to preserve the GPIO settings for LOMs. The GPIOs,
7198          * whether used as inputs or outputs, are set by boot code after
7199          * reset.
7200          */
7201         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7202                 u32 gpio_mask;
7203
7204                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7205                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7206                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7207
7208                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7209                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7210                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7211
7212                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7213                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7214
7215                 tp->grc_local_ctrl &= ~gpio_mask;
7216                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7217
7218                 /* GPIO1 must be driven high for eeprom write protect */
7219                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7220                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7221                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7222         }
7223         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7224         udelay(100);
7225
7226         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7227
7228         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7229                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7230                 udelay(40);
7231         }
7232
7233         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7234                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7235                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7236                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7237                WDMAC_MODE_LNGREAD_ENAB);
7238
7239         /* If statement applies to 5705 and 5750 PCI devices only */
7240         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7241              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7242             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7243                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7244                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7245                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7246                         /* nothing */
7247                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7248                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7249                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7250                         val |= WDMAC_MODE_RX_ACCEL;
7251                 }
7252         }
7253
7254         /* Enable host coalescing bug fix */
7255         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7256                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7257
7258         tw32_f(WDMAC_MODE, val);
7259         udelay(40);
7260
7261         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7262                 u16 pcix_cmd;
7263
7264                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7265                                      &pcix_cmd);
7266                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7267                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7268                         pcix_cmd |= PCI_X_CMD_READ_2K;
7269                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7270                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7271                         pcix_cmd |= PCI_X_CMD_READ_2K;
7272                 }
7273                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7274                                       pcix_cmd);
7275         }
7276
7277         tw32_f(RDMAC_MODE, rdmac_mode);
7278         udelay(40);
7279
7280         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7281         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7282                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7283
7284         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7285                 tw32(SNDDATAC_MODE,
7286                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7287         else
7288                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7289
7290         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7291         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7292         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7293         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7294         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7295                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7296         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7297         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7298
7299         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7300                 err = tg3_load_5701_a0_firmware_fix(tp);
7301                 if (err)
7302                         return err;
7303         }
7304
7305         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7306                 err = tg3_load_tso_firmware(tp);
7307                 if (err)
7308                         return err;
7309         }
7310
7311         tp->tx_mode = TX_MODE_ENABLE;
7312         tw32_f(MAC_TX_MODE, tp->tx_mode);
7313         udelay(100);
7314
7315         tp->rx_mode = RX_MODE_ENABLE;
7316         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7317                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7318
7319         tw32_f(MAC_RX_MODE, tp->rx_mode);
7320         udelay(10);
7321
7322         tw32(MAC_LED_CTRL, tp->led_ctrl);
7323
7324         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7325         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7326                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7327                 udelay(10);
7328         }
7329         tw32_f(MAC_RX_MODE, tp->rx_mode);
7330         udelay(10);
7331
7332         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7333                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7334                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7335                         /* Set drive transmission level to 1.2V  */
7336                         /* only if the signal pre-emphasis bit is not set  */
7337                         val = tr32(MAC_SERDES_CFG);
7338                         val &= 0xfffff000;
7339                         val |= 0x880;
7340                         tw32(MAC_SERDES_CFG, val);
7341                 }
7342                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7343                         tw32(MAC_SERDES_CFG, 0x616000);
7344         }
7345
7346         /* Prevent chip from dropping frames when flow control
7347          * is enabled.
7348          */
7349         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7350
7351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7352             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7353                 /* Use hardware link auto-negotiation */
7354                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7355         }
7356
7357         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7358             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7359                 u32 tmp;
7360
7361                 tmp = tr32(SERDES_RX_CTRL);
7362                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7363                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7364                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7365                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7366         }
7367
7368         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7369                 if (tp->link_config.phy_is_low_power) {
7370                         tp->link_config.phy_is_low_power = 0;
7371                         tp->link_config.speed = tp->link_config.orig_speed;
7372                         tp->link_config.duplex = tp->link_config.orig_duplex;
7373                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7374                 }
7375
7376                 err = tg3_setup_phy(tp, 0);
7377                 if (err)
7378                         return err;
7379
7380                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7381                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7382                         u32 tmp;
7383
7384                         /* Clear CRC stats. */
7385                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7386                                 tg3_writephy(tp, MII_TG3_TEST1,
7387                                              tmp | MII_TG3_TEST1_CRC_EN);
7388                                 tg3_readphy(tp, 0x14, &tmp);
7389                         }
7390                 }
7391         }
7392
7393         __tg3_set_rx_mode(tp->dev);
7394
7395         /* Initialize receive rules. */
7396         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7397         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7398         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7399         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7400
7401         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7402             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7403                 limit = 8;
7404         else
7405                 limit = 16;
7406         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7407                 limit -= 4;
7408         switch (limit) {
7409         case 16:
7410                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7411         case 15:
7412                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7413         case 14:
7414                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7415         case 13:
7416                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7417         case 12:
7418                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7419         case 11:
7420                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7421         case 10:
7422                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7423         case 9:
7424                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7425         case 8:
7426                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7427         case 7:
7428                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7429         case 6:
7430                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7431         case 5:
7432                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7433         case 4:
7434                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7435         case 3:
7436                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7437         case 2:
7438         case 1:
7439
7440         default:
7441                 break;
7442         }
7443
7444         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7445                 /* Write our heartbeat update interval to APE. */
7446                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7447                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7448
7449         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7450
7451         return 0;
7452 }
7453
7454 /* Called at device open time to get the chip ready for
7455  * packet processing.  Invoked with tp->lock held.
7456  */
7457 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7458 {
7459         tg3_switch_clocks(tp);
7460
7461         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7462
7463         return tg3_reset_hw(tp, reset_phy);
7464 }
7465
7466 #define TG3_STAT_ADD32(PSTAT, REG) \
7467 do {    u32 __val = tr32(REG); \
7468         (PSTAT)->low += __val; \
7469         if ((PSTAT)->low < __val) \
7470                 (PSTAT)->high += 1; \
7471 } while (0)
7472
7473 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7474 {
7475         struct tg3_hw_stats *sp = tp->hw_stats;
7476
7477         if (!netif_carrier_ok(tp->dev))
7478                 return;
7479
7480         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7481         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7482         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7483         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7484         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7485         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7486         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7487         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7488         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7489         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7490         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7491         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7492         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7493
7494         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7495         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7496         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7497         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7498         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7499         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7500         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7501         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7502         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7503         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7504         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7505         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7506         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7507         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7508
7509         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7510         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7511         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7512 }
7513
7514 static void tg3_timer(unsigned long __opaque)
7515 {
7516         struct tg3 *tp = (struct tg3 *) __opaque;
7517
7518         if (tp->irq_sync)
7519                 goto restart_timer;
7520
7521         spin_lock(&tp->lock);
7522
7523         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7524                 /* All of this garbage is because when using non-tagged
7525                  * IRQ status the mailbox/status_block protocol the chip
7526                  * uses with the cpu is race prone.
7527                  */
7528                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7529                         tw32(GRC_LOCAL_CTRL,
7530                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7531                 } else {
7532                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7533                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7534                 }
7535
7536                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7537                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7538                         spin_unlock(&tp->lock);
7539                         schedule_work(&tp->reset_task);
7540                         return;
7541                 }
7542         }
7543
7544         /* This part only runs once per second. */
7545         if (!--tp->timer_counter) {
7546                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7547                         tg3_periodic_fetch_stats(tp);
7548
7549                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7550                         u32 mac_stat;
7551                         int phy_event;
7552
7553                         mac_stat = tr32(MAC_STATUS);
7554
7555                         phy_event = 0;
7556                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7557                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7558                                         phy_event = 1;
7559                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7560                                 phy_event = 1;
7561
7562                         if (phy_event)
7563                                 tg3_setup_phy(tp, 0);
7564                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7565                         u32 mac_stat = tr32(MAC_STATUS);
7566                         int need_setup = 0;
7567
7568                         if (netif_carrier_ok(tp->dev) &&
7569                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7570                                 need_setup = 1;
7571                         }
7572                         if (! netif_carrier_ok(tp->dev) &&
7573                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7574                                          MAC_STATUS_SIGNAL_DET))) {
7575                                 need_setup = 1;
7576                         }
7577                         if (need_setup) {
7578                                 if (!tp->serdes_counter) {
7579                                         tw32_f(MAC_MODE,
7580                                              (tp->mac_mode &
7581                                               ~MAC_MODE_PORT_MODE_MASK));
7582                                         udelay(40);
7583                                         tw32_f(MAC_MODE, tp->mac_mode);
7584                                         udelay(40);
7585                                 }
7586                                 tg3_setup_phy(tp, 0);
7587                         }
7588                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7589                         tg3_serdes_parallel_detect(tp);
7590
7591                 tp->timer_counter = tp->timer_multiplier;
7592         }
7593
7594         /* Heartbeat is only sent once every 2 seconds.
7595          *
7596          * The heartbeat is to tell the ASF firmware that the host
7597          * driver is still alive.  In the event that the OS crashes,
7598          * ASF needs to reset the hardware to free up the FIFO space
7599          * that may be filled with rx packets destined for the host.
7600          * If the FIFO is full, ASF will no longer function properly.
7601          *
7602          * Unintended resets have been reported on real time kernels
7603          * where the timer doesn't run on time.  Netpoll will also have
7604          * same problem.
7605          *
7606          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7607          * to check the ring condition when the heartbeat is expiring
7608          * before doing the reset.  This will prevent most unintended
7609          * resets.
7610          */
7611         if (!--tp->asf_counter) {
7612                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7613                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7614                         tg3_wait_for_event_ack(tp);
7615
7616                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7617                                       FWCMD_NICDRV_ALIVE3);
7618                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7619                         /* 5 seconds timeout */
7620                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7621
7622                         tg3_generate_fw_event(tp);
7623                 }
7624                 tp->asf_counter = tp->asf_multiplier;
7625         }
7626
7627         spin_unlock(&tp->lock);
7628
7629 restart_timer:
7630         tp->timer.expires = jiffies + tp->timer_offset;
7631         add_timer(&tp->timer);
7632 }
7633
7634 static int tg3_request_irq(struct tg3 *tp)
7635 {
7636         irq_handler_t fn;
7637         unsigned long flags;
7638         struct net_device *dev = tp->dev;
7639
7640         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7641                 fn = tg3_msi;
7642                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7643                         fn = tg3_msi_1shot;
7644                 flags = IRQF_SAMPLE_RANDOM;
7645         } else {
7646                 fn = tg3_interrupt;
7647                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7648                         fn = tg3_interrupt_tagged;
7649                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7650         }
7651         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7652 }
7653
7654 static int tg3_test_interrupt(struct tg3 *tp)
7655 {
7656         struct net_device *dev = tp->dev;
7657         int err, i, intr_ok = 0;
7658
7659         if (!netif_running(dev))
7660                 return -ENODEV;
7661
7662         tg3_disable_ints(tp);
7663
7664         free_irq(tp->pdev->irq, dev);
7665
7666         err = request_irq(tp->pdev->irq, tg3_test_isr,
7667                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7668         if (err)
7669                 return err;
7670
7671         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7672         tg3_enable_ints(tp);
7673
7674         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7675                HOSTCC_MODE_NOW);
7676
7677         for (i = 0; i < 5; i++) {
7678                 u32 int_mbox, misc_host_ctrl;
7679
7680                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7681                                         TG3_64BIT_REG_LOW);
7682                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7683
7684                 if ((int_mbox != 0) ||
7685                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7686                         intr_ok = 1;
7687                         break;
7688                 }
7689
7690                 msleep(10);
7691         }
7692
7693         tg3_disable_ints(tp);
7694
7695         free_irq(tp->pdev->irq, dev);
7696
7697         err = tg3_request_irq(tp);
7698
7699         if (err)
7700                 return err;
7701
7702         if (intr_ok)
7703                 return 0;
7704
7705         return -EIO;
7706 }
7707
7708 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7709  * successfully restored
7710  */
7711 static int tg3_test_msi(struct tg3 *tp)
7712 {
7713         struct net_device *dev = tp->dev;
7714         int err;
7715         u16 pci_cmd;
7716
7717         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7718                 return 0;
7719
7720         /* Turn off SERR reporting in case MSI terminates with Master
7721          * Abort.
7722          */
7723         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7724         pci_write_config_word(tp->pdev, PCI_COMMAND,
7725                               pci_cmd & ~PCI_COMMAND_SERR);
7726
7727         err = tg3_test_interrupt(tp);
7728
7729         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7730
7731         if (!err)
7732                 return 0;
7733
7734         /* other failures */
7735         if (err != -EIO)
7736                 return err;
7737
7738         /* MSI test failed, go back to INTx mode */
7739         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7740                "switching to INTx mode. Please report this failure to "
7741                "the PCI maintainer and include system chipset information.\n",
7742                        tp->dev->name);
7743
7744         free_irq(tp->pdev->irq, dev);
7745         pci_disable_msi(tp->pdev);
7746
7747         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7748
7749         err = tg3_request_irq(tp);
7750         if (err)
7751                 return err;
7752
7753         /* Need to reset the chip because the MSI cycle may have terminated
7754          * with Master Abort.
7755          */
7756         tg3_full_lock(tp, 1);
7757
7758         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7759         err = tg3_init_hw(tp, 1);
7760
7761         tg3_full_unlock(tp);
7762
7763         if (err)
7764                 free_irq(tp->pdev->irq, dev);
7765
7766         return err;
7767 }
7768
7769 static int tg3_request_firmware(struct tg3 *tp)
7770 {
7771         const __be32 *fw_data;
7772
7773         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7774                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7775                        tp->dev->name, tp->fw_needed);
7776                 return -ENOENT;
7777         }
7778
7779         fw_data = (void *)tp->fw->data;
7780
7781         /* Firmware blob starts with version numbers, followed by
7782          * start address and _full_ length including BSS sections
7783          * (which must be longer than the actual data, of course
7784          */
7785
7786         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7787         if (tp->fw_len < (tp->fw->size - 12)) {
7788                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7789                        tp->dev->name, tp->fw_len, tp->fw_needed);
7790                 release_firmware(tp->fw);
7791                 tp->fw = NULL;
7792                 return -EINVAL;
7793         }
7794
7795         /* We no longer need firmware; we have it. */
7796         tp->fw_needed = NULL;
7797         return 0;
7798 }
7799
7800 static int tg3_open(struct net_device *dev)
7801 {
7802         struct tg3 *tp = netdev_priv(dev);
7803         int err;
7804
7805         if (tp->fw_needed) {
7806                 err = tg3_request_firmware(tp);
7807                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7808                         if (err)
7809                                 return err;
7810                 } else if (err) {
7811                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7812                                tp->dev->name);
7813                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7814                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7815                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7816                                tp->dev->name);
7817                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7818                 }
7819         }
7820
7821         netif_carrier_off(tp->dev);
7822
7823         err = tg3_set_power_state(tp, PCI_D0);
7824         if (err)
7825                 return err;
7826
7827         tg3_full_lock(tp, 0);
7828
7829         tg3_disable_ints(tp);
7830         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7831
7832         tg3_full_unlock(tp);
7833
7834         /* The placement of this call is tied
7835          * to the setup and use of Host TX descriptors.
7836          */
7837         err = tg3_alloc_consistent(tp);
7838         if (err)
7839                 return err;
7840
7841         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7842                 /* All MSI supporting chips should support tagged
7843                  * status.  Assert that this is the case.
7844                  */
7845                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7846                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7847                                "Not using MSI.\n", tp->dev->name);
7848                 } else if (pci_enable_msi(tp->pdev) == 0) {
7849                         u32 msi_mode;
7850
7851                         msi_mode = tr32(MSGINT_MODE);
7852                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7853                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7854                 }
7855         }
7856         err = tg3_request_irq(tp);
7857
7858         if (err) {
7859                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7860                         pci_disable_msi(tp->pdev);
7861                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7862                 }
7863                 tg3_free_consistent(tp);
7864                 return err;
7865         }
7866
7867         napi_enable(&tp->napi);
7868
7869         tg3_full_lock(tp, 0);
7870
7871         err = tg3_init_hw(tp, 1);
7872         if (err) {
7873                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7874                 tg3_free_rings(tp);
7875         } else {
7876                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7877                         tp->timer_offset = HZ;
7878                 else
7879                         tp->timer_offset = HZ / 10;
7880
7881                 BUG_ON(tp->timer_offset > HZ);
7882                 tp->timer_counter = tp->timer_multiplier =
7883                         (HZ / tp->timer_offset);
7884                 tp->asf_counter = tp->asf_multiplier =
7885                         ((HZ / tp->timer_offset) * 2);
7886
7887                 init_timer(&tp->timer);
7888                 tp->timer.expires = jiffies + tp->timer_offset;
7889                 tp->timer.data = (unsigned long) tp;
7890                 tp->timer.function = tg3_timer;
7891         }
7892
7893         tg3_full_unlock(tp);
7894
7895         if (err) {
7896                 napi_disable(&tp->napi);
7897                 free_irq(tp->pdev->irq, dev);
7898                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7899                         pci_disable_msi(tp->pdev);
7900                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7901                 }
7902                 tg3_free_consistent(tp);
7903                 return err;
7904         }
7905
7906         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7907                 err = tg3_test_msi(tp);
7908
7909                 if (err) {
7910                         tg3_full_lock(tp, 0);
7911
7912                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7913                                 pci_disable_msi(tp->pdev);
7914                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7915                         }
7916                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7917                         tg3_free_rings(tp);
7918                         tg3_free_consistent(tp);
7919
7920                         tg3_full_unlock(tp);
7921
7922                         napi_disable(&tp->napi);
7923
7924                         return err;
7925                 }
7926
7927                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7928                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7929                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7930
7931                                 tw32(PCIE_TRANSACTION_CFG,
7932                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7933                         }
7934                 }
7935         }
7936
7937         tg3_phy_start(tp);
7938
7939         tg3_full_lock(tp, 0);
7940
7941         add_timer(&tp->timer);
7942         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7943         tg3_enable_ints(tp);
7944
7945         tg3_full_unlock(tp);
7946
7947         netif_start_queue(dev);
7948
7949         return 0;
7950 }
7951
7952 #if 0
7953 /*static*/ void tg3_dump_state(struct tg3 *tp)
7954 {
7955         u32 val32, val32_2, val32_3, val32_4, val32_5;
7956         u16 val16;
7957         int i;
7958
7959         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7960         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7961         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7962                val16, val32);
7963
7964         /* MAC block */
7965         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7966                tr32(MAC_MODE), tr32(MAC_STATUS));
7967         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7968                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7969         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7970                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7971         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7972                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7973
7974         /* Send data initiator control block */
7975         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7976                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7977         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7978                tr32(SNDDATAI_STATSCTRL));
7979
7980         /* Send data completion control block */
7981         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7982
7983         /* Send BD ring selector block */
7984         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7985                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7986
7987         /* Send BD initiator control block */
7988         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7989                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7990
7991         /* Send BD completion control block */
7992         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7993
7994         /* Receive list placement control block */
7995         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7996                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7997         printk("       RCVLPC_STATSCTRL[%08x]\n",
7998                tr32(RCVLPC_STATSCTRL));
7999
8000         /* Receive data and receive BD initiator control block */
8001         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8002                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8003
8004         /* Receive data completion control block */
8005         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8006                tr32(RCVDCC_MODE));
8007
8008         /* Receive BD initiator control block */
8009         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8010                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8011
8012         /* Receive BD completion control block */
8013         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8014                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8015
8016         /* Receive list selector control block */
8017         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8018                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8019
8020         /* Mbuf cluster free block */
8021         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8022                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8023
8024         /* Host coalescing control block */
8025         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8026                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8027         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8028                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8029                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8030         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8031                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8032                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8033         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8034                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8035         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8036                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8037
8038         /* Memory arbiter control block */
8039         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8040                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8041
8042         /* Buffer manager control block */
8043         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8044                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8045         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8046                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8047         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8048                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8049                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8050                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8051
8052         /* Read DMA control block */
8053         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8054                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8055
8056         /* Write DMA control block */
8057         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8058                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8059
8060         /* DMA completion block */
8061         printk("DEBUG: DMAC_MODE[%08x]\n",
8062                tr32(DMAC_MODE));
8063
8064         /* GRC block */
8065         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8066                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8067         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8068                tr32(GRC_LOCAL_CTRL));
8069
8070         /* TG3_BDINFOs */
8071         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8072                tr32(RCVDBDI_JUMBO_BD + 0x0),
8073                tr32(RCVDBDI_JUMBO_BD + 0x4),
8074                tr32(RCVDBDI_JUMBO_BD + 0x8),
8075                tr32(RCVDBDI_JUMBO_BD + 0xc));
8076         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8077                tr32(RCVDBDI_STD_BD + 0x0),
8078                tr32(RCVDBDI_STD_BD + 0x4),
8079                tr32(RCVDBDI_STD_BD + 0x8),
8080                tr32(RCVDBDI_STD_BD + 0xc));
8081         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8082                tr32(RCVDBDI_MINI_BD + 0x0),
8083                tr32(RCVDBDI_MINI_BD + 0x4),
8084                tr32(RCVDBDI_MINI_BD + 0x8),
8085                tr32(RCVDBDI_MINI_BD + 0xc));
8086
8087         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8088         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8089         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8090         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8091         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8092                val32, val32_2, val32_3, val32_4);
8093
8094         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8095         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8096         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8097         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8098         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8099                val32, val32_2, val32_3, val32_4);
8100
8101         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8102         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8103         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8104         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8105         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8106         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8107                val32, val32_2, val32_3, val32_4, val32_5);
8108
8109         /* SW status block */
8110         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8111                tp->hw_status->status,
8112                tp->hw_status->status_tag,
8113                tp->hw_status->rx_jumbo_consumer,
8114                tp->hw_status->rx_consumer,
8115                tp->hw_status->rx_mini_consumer,
8116                tp->hw_status->idx[0].rx_producer,
8117                tp->hw_status->idx[0].tx_consumer);
8118
8119         /* SW statistics block */
8120         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8121                ((u32 *)tp->hw_stats)[0],
8122                ((u32 *)tp->hw_stats)[1],
8123                ((u32 *)tp->hw_stats)[2],
8124                ((u32 *)tp->hw_stats)[3]);
8125
8126         /* Mailboxes */
8127         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8128                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8129                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8130                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8131                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8132
8133         /* NIC side send descriptors. */
8134         for (i = 0; i < 6; i++) {
8135                 unsigned long txd;
8136
8137                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8138                         + (i * sizeof(struct tg3_tx_buffer_desc));
8139                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8140                        i,
8141                        readl(txd + 0x0), readl(txd + 0x4),
8142                        readl(txd + 0x8), readl(txd + 0xc));
8143         }
8144
8145         /* NIC side RX descriptors. */
8146         for (i = 0; i < 6; i++) {
8147                 unsigned long rxd;
8148
8149                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8150                         + (i * sizeof(struct tg3_rx_buffer_desc));
8151                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8152                        i,
8153                        readl(rxd + 0x0), readl(rxd + 0x4),
8154                        readl(rxd + 0x8), readl(rxd + 0xc));
8155                 rxd += (4 * sizeof(u32));
8156                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8157                        i,
8158                        readl(rxd + 0x0), readl(rxd + 0x4),
8159                        readl(rxd + 0x8), readl(rxd + 0xc));
8160         }
8161
8162         for (i = 0; i < 6; i++) {
8163                 unsigned long rxd;
8164
8165                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8166                         + (i * sizeof(struct tg3_rx_buffer_desc));
8167                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8168                        i,
8169                        readl(rxd + 0x0), readl(rxd + 0x4),
8170                        readl(rxd + 0x8), readl(rxd + 0xc));
8171                 rxd += (4 * sizeof(u32));
8172                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8173                        i,
8174                        readl(rxd + 0x0), readl(rxd + 0x4),
8175                        readl(rxd + 0x8), readl(rxd + 0xc));
8176         }
8177 }
8178 #endif
8179
8180 static struct net_device_stats *tg3_get_stats(struct net_device *);
8181 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8182
8183 static int tg3_close(struct net_device *dev)
8184 {
8185         struct tg3 *tp = netdev_priv(dev);
8186
8187         napi_disable(&tp->napi);
8188         cancel_work_sync(&tp->reset_task);
8189
8190         netif_stop_queue(dev);
8191
8192         del_timer_sync(&tp->timer);
8193
8194         tg3_full_lock(tp, 1);
8195 #if 0
8196         tg3_dump_state(tp);
8197 #endif
8198
8199         tg3_disable_ints(tp);
8200
8201         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8202         tg3_free_rings(tp);
8203         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8204
8205         tg3_full_unlock(tp);
8206
8207         free_irq(tp->pdev->irq, dev);
8208         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8209                 pci_disable_msi(tp->pdev);
8210                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8211         }
8212
8213         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8214                sizeof(tp->net_stats_prev));
8215         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8216                sizeof(tp->estats_prev));
8217
8218         tg3_free_consistent(tp);
8219
8220         tg3_set_power_state(tp, PCI_D3hot);
8221
8222         netif_carrier_off(tp->dev);
8223
8224         return 0;
8225 }
8226
8227 static inline unsigned long get_stat64(tg3_stat64_t *val)
8228 {
8229         unsigned long ret;
8230
8231 #if (BITS_PER_LONG == 32)
8232         ret = val->low;
8233 #else
8234         ret = ((u64)val->high << 32) | ((u64)val->low);
8235 #endif
8236         return ret;
8237 }
8238
8239 static inline u64 get_estat64(tg3_stat64_t *val)
8240 {
8241        return ((u64)val->high << 32) | ((u64)val->low);
8242 }
8243
8244 static unsigned long calc_crc_errors(struct tg3 *tp)
8245 {
8246         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8247
8248         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8249             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8250              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8251                 u32 val;
8252
8253                 spin_lock_bh(&tp->lock);
8254                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8255                         tg3_writephy(tp, MII_TG3_TEST1,
8256                                      val | MII_TG3_TEST1_CRC_EN);
8257                         tg3_readphy(tp, 0x14, &val);
8258                 } else
8259                         val = 0;
8260                 spin_unlock_bh(&tp->lock);
8261
8262                 tp->phy_crc_errors += val;
8263
8264                 return tp->phy_crc_errors;
8265         }
8266
8267         return get_stat64(&hw_stats->rx_fcs_errors);
8268 }
8269
8270 #define ESTAT_ADD(member) \
8271         estats->member =        old_estats->member + \
8272                                 get_estat64(&hw_stats->member)
8273
8274 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8275 {
8276         struct tg3_ethtool_stats *estats = &tp->estats;
8277         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8278         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8279
8280         if (!hw_stats)
8281                 return old_estats;
8282
8283         ESTAT_ADD(rx_octets);
8284         ESTAT_ADD(rx_fragments);
8285         ESTAT_ADD(rx_ucast_packets);
8286         ESTAT_ADD(rx_mcast_packets);
8287         ESTAT_ADD(rx_bcast_packets);
8288         ESTAT_ADD(rx_fcs_errors);
8289         ESTAT_ADD(rx_align_errors);
8290         ESTAT_ADD(rx_xon_pause_rcvd);
8291         ESTAT_ADD(rx_xoff_pause_rcvd);
8292         ESTAT_ADD(rx_mac_ctrl_rcvd);
8293         ESTAT_ADD(rx_xoff_entered);
8294         ESTAT_ADD(rx_frame_too_long_errors);
8295         ESTAT_ADD(rx_jabbers);
8296         ESTAT_ADD(rx_undersize_packets);
8297         ESTAT_ADD(rx_in_length_errors);
8298         ESTAT_ADD(rx_out_length_errors);
8299         ESTAT_ADD(rx_64_or_less_octet_packets);
8300         ESTAT_ADD(rx_65_to_127_octet_packets);
8301         ESTAT_ADD(rx_128_to_255_octet_packets);
8302         ESTAT_ADD(rx_256_to_511_octet_packets);
8303         ESTAT_ADD(rx_512_to_1023_octet_packets);
8304         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8305         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8306         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8307         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8308         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8309
8310         ESTAT_ADD(tx_octets);
8311         ESTAT_ADD(tx_collisions);
8312         ESTAT_ADD(tx_xon_sent);
8313         ESTAT_ADD(tx_xoff_sent);
8314         ESTAT_ADD(tx_flow_control);
8315         ESTAT_ADD(tx_mac_errors);
8316         ESTAT_ADD(tx_single_collisions);
8317         ESTAT_ADD(tx_mult_collisions);
8318         ESTAT_ADD(tx_deferred);
8319         ESTAT_ADD(tx_excessive_collisions);
8320         ESTAT_ADD(tx_late_collisions);
8321         ESTAT_ADD(tx_collide_2times);
8322         ESTAT_ADD(tx_collide_3times);
8323         ESTAT_ADD(tx_collide_4times);
8324         ESTAT_ADD(tx_collide_5times);
8325         ESTAT_ADD(tx_collide_6times);
8326         ESTAT_ADD(tx_collide_7times);
8327         ESTAT_ADD(tx_collide_8times);
8328         ESTAT_ADD(tx_collide_9times);
8329         ESTAT_ADD(tx_collide_10times);
8330         ESTAT_ADD(tx_collide_11times);
8331         ESTAT_ADD(tx_collide_12times);
8332         ESTAT_ADD(tx_collide_13times);
8333         ESTAT_ADD(tx_collide_14times);
8334         ESTAT_ADD(tx_collide_15times);
8335         ESTAT_ADD(tx_ucast_packets);
8336         ESTAT_ADD(tx_mcast_packets);
8337         ESTAT_ADD(tx_bcast_packets);
8338         ESTAT_ADD(tx_carrier_sense_errors);
8339         ESTAT_ADD(tx_discards);
8340         ESTAT_ADD(tx_errors);
8341
8342         ESTAT_ADD(dma_writeq_full);
8343         ESTAT_ADD(dma_write_prioq_full);
8344         ESTAT_ADD(rxbds_empty);
8345         ESTAT_ADD(rx_discards);
8346         ESTAT_ADD(rx_errors);
8347         ESTAT_ADD(rx_threshold_hit);
8348
8349         ESTAT_ADD(dma_readq_full);
8350         ESTAT_ADD(dma_read_prioq_full);
8351         ESTAT_ADD(tx_comp_queue_full);
8352
8353         ESTAT_ADD(ring_set_send_prod_index);
8354         ESTAT_ADD(ring_status_update);
8355         ESTAT_ADD(nic_irqs);
8356         ESTAT_ADD(nic_avoided_irqs);
8357         ESTAT_ADD(nic_tx_threshold_hit);
8358
8359         return estats;
8360 }
8361
8362 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8363 {
8364         struct tg3 *tp = netdev_priv(dev);
8365         struct net_device_stats *stats = &tp->net_stats;
8366         struct net_device_stats *old_stats = &tp->net_stats_prev;
8367         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8368
8369         if (!hw_stats)
8370                 return old_stats;
8371
8372         stats->rx_packets = old_stats->rx_packets +
8373                 get_stat64(&hw_stats->rx_ucast_packets) +
8374                 get_stat64(&hw_stats->rx_mcast_packets) +
8375                 get_stat64(&hw_stats->rx_bcast_packets);
8376
8377         stats->tx_packets = old_stats->tx_packets +
8378                 get_stat64(&hw_stats->tx_ucast_packets) +
8379                 get_stat64(&hw_stats->tx_mcast_packets) +
8380                 get_stat64(&hw_stats->tx_bcast_packets);
8381
8382         stats->rx_bytes = old_stats->rx_bytes +
8383                 get_stat64(&hw_stats->rx_octets);
8384         stats->tx_bytes = old_stats->tx_bytes +
8385                 get_stat64(&hw_stats->tx_octets);
8386
8387         stats->rx_errors = old_stats->rx_errors +
8388                 get_stat64(&hw_stats->rx_errors);
8389         stats->tx_errors = old_stats->tx_errors +
8390                 get_stat64(&hw_stats->tx_errors) +
8391                 get_stat64(&hw_stats->tx_mac_errors) +
8392                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8393                 get_stat64(&hw_stats->tx_discards);
8394
8395         stats->multicast = old_stats->multicast +
8396                 get_stat64(&hw_stats->rx_mcast_packets);
8397         stats->collisions = old_stats->collisions +
8398                 get_stat64(&hw_stats->tx_collisions);
8399
8400         stats->rx_length_errors = old_stats->rx_length_errors +
8401                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8402                 get_stat64(&hw_stats->rx_undersize_packets);
8403
8404         stats->rx_over_errors = old_stats->rx_over_errors +
8405                 get_stat64(&hw_stats->rxbds_empty);
8406         stats->rx_frame_errors = old_stats->rx_frame_errors +
8407                 get_stat64(&hw_stats->rx_align_errors);
8408         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8409                 get_stat64(&hw_stats->tx_discards);
8410         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8411                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8412
8413         stats->rx_crc_errors = old_stats->rx_crc_errors +
8414                 calc_crc_errors(tp);
8415
8416         stats->rx_missed_errors = old_stats->rx_missed_errors +
8417                 get_stat64(&hw_stats->rx_discards);
8418
8419         return stats;
8420 }
8421
8422 static inline u32 calc_crc(unsigned char *buf, int len)
8423 {
8424         u32 reg;
8425         u32 tmp;
8426         int j, k;
8427
8428         reg = 0xffffffff;
8429
8430         for (j = 0; j < len; j++) {
8431                 reg ^= buf[j];
8432
8433                 for (k = 0; k < 8; k++) {
8434                         tmp = reg & 0x01;
8435
8436                         reg >>= 1;
8437
8438                         if (tmp) {
8439                                 reg ^= 0xedb88320;
8440                         }
8441                 }
8442         }
8443
8444         return ~reg;
8445 }
8446
8447 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8448 {
8449         /* accept or reject all multicast frames */
8450         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8451         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8452         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8453         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8454 }
8455
8456 static void __tg3_set_rx_mode(struct net_device *dev)
8457 {
8458         struct tg3 *tp = netdev_priv(dev);
8459         u32 rx_mode;
8460
8461         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8462                                   RX_MODE_KEEP_VLAN_TAG);
8463
8464         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8465          * flag clear.
8466          */
8467 #if TG3_VLAN_TAG_USED
8468         if (!tp->vlgrp &&
8469             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8470                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8471 #else
8472         /* By definition, VLAN is disabled always in this
8473          * case.
8474          */
8475         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8476                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8477 #endif
8478
8479         if (dev->flags & IFF_PROMISC) {
8480                 /* Promiscuous mode. */
8481                 rx_mode |= RX_MODE_PROMISC;
8482         } else if (dev->flags & IFF_ALLMULTI) {
8483                 /* Accept all multicast. */
8484                 tg3_set_multi (tp, 1);
8485         } else if (dev->mc_count < 1) {
8486                 /* Reject all multicast. */
8487                 tg3_set_multi (tp, 0);
8488         } else {
8489                 /* Accept one or more multicast(s). */
8490                 struct dev_mc_list *mclist;
8491                 unsigned int i;
8492                 u32 mc_filter[4] = { 0, };
8493                 u32 regidx;
8494                 u32 bit;
8495                 u32 crc;
8496
8497                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8498                      i++, mclist = mclist->next) {
8499
8500                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8501                         bit = ~crc & 0x7f;
8502                         regidx = (bit & 0x60) >> 5;
8503                         bit &= 0x1f;
8504                         mc_filter[regidx] |= (1 << bit);
8505                 }
8506
8507                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8508                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8509                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8510                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8511         }
8512
8513         if (rx_mode != tp->rx_mode) {
8514                 tp->rx_mode = rx_mode;
8515                 tw32_f(MAC_RX_MODE, rx_mode);
8516                 udelay(10);
8517         }
8518 }
8519
8520 static void tg3_set_rx_mode(struct net_device *dev)
8521 {
8522         struct tg3 *tp = netdev_priv(dev);
8523
8524         if (!netif_running(dev))
8525                 return;
8526
8527         tg3_full_lock(tp, 0);
8528         __tg3_set_rx_mode(dev);
8529         tg3_full_unlock(tp);
8530 }
8531
8532 #define TG3_REGDUMP_LEN         (32 * 1024)
8533
8534 static int tg3_get_regs_len(struct net_device *dev)
8535 {
8536         return TG3_REGDUMP_LEN;
8537 }
8538
8539 static void tg3_get_regs(struct net_device *dev,
8540                 struct ethtool_regs *regs, void *_p)
8541 {
8542         u32 *p = _p;
8543         struct tg3 *tp = netdev_priv(dev);
8544         u8 *orig_p = _p;
8545         int i;
8546
8547         regs->version = 0;
8548
8549         memset(p, 0, TG3_REGDUMP_LEN);
8550
8551         if (tp->link_config.phy_is_low_power)
8552                 return;
8553
8554         tg3_full_lock(tp, 0);
8555
8556 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8557 #define GET_REG32_LOOP(base,len)                \
8558 do {    p = (u32 *)(orig_p + (base));           \
8559         for (i = 0; i < len; i += 4)            \
8560                 __GET_REG32((base) + i);        \
8561 } while (0)
8562 #define GET_REG32_1(reg)                        \
8563 do {    p = (u32 *)(orig_p + (reg));            \
8564         __GET_REG32((reg));                     \
8565 } while (0)
8566
8567         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8568         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8569         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8570         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8571         GET_REG32_1(SNDDATAC_MODE);
8572         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8573         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8574         GET_REG32_1(SNDBDC_MODE);
8575         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8576         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8577         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8578         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8579         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8580         GET_REG32_1(RCVDCC_MODE);
8581         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8582         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8583         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8584         GET_REG32_1(MBFREE_MODE);
8585         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8586         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8587         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8588         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8589         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8590         GET_REG32_1(RX_CPU_MODE);
8591         GET_REG32_1(RX_CPU_STATE);
8592         GET_REG32_1(RX_CPU_PGMCTR);
8593         GET_REG32_1(RX_CPU_HWBKPT);
8594         GET_REG32_1(TX_CPU_MODE);
8595         GET_REG32_1(TX_CPU_STATE);
8596         GET_REG32_1(TX_CPU_PGMCTR);
8597         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8598         GET_REG32_LOOP(FTQ_RESET, 0x120);
8599         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8600         GET_REG32_1(DMAC_MODE);
8601         GET_REG32_LOOP(GRC_MODE, 0x4c);
8602         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8603                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8604
8605 #undef __GET_REG32
8606 #undef GET_REG32_LOOP
8607 #undef GET_REG32_1
8608
8609         tg3_full_unlock(tp);
8610 }
8611
8612 static int tg3_get_eeprom_len(struct net_device *dev)
8613 {
8614         struct tg3 *tp = netdev_priv(dev);
8615
8616         return tp->nvram_size;
8617 }
8618
8619 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8620 {
8621         struct tg3 *tp = netdev_priv(dev);
8622         int ret;
8623         u8  *pd;
8624         u32 i, offset, len, b_offset, b_count;
8625         __be32 val;
8626
8627         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8628                 return -EINVAL;
8629
8630         if (tp->link_config.phy_is_low_power)
8631                 return -EAGAIN;
8632
8633         offset = eeprom->offset;
8634         len = eeprom->len;
8635         eeprom->len = 0;
8636
8637         eeprom->magic = TG3_EEPROM_MAGIC;
8638
8639         if (offset & 3) {
8640                 /* adjustments to start on required 4 byte boundary */
8641                 b_offset = offset & 3;
8642                 b_count = 4 - b_offset;
8643                 if (b_count > len) {
8644                         /* i.e. offset=1 len=2 */
8645                         b_count = len;
8646                 }
8647                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8648                 if (ret)
8649                         return ret;
8650                 memcpy(data, ((char*)&val) + b_offset, b_count);
8651                 len -= b_count;
8652                 offset += b_count;
8653                 eeprom->len += b_count;
8654         }
8655
8656         /* read bytes upto the last 4 byte boundary */
8657         pd = &data[eeprom->len];
8658         for (i = 0; i < (len - (len & 3)); i += 4) {
8659                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8660                 if (ret) {
8661                         eeprom->len += i;
8662                         return ret;
8663                 }
8664                 memcpy(pd + i, &val, 4);
8665         }
8666         eeprom->len += i;
8667
8668         if (len & 3) {
8669                 /* read last bytes not ending on 4 byte boundary */
8670                 pd = &data[eeprom->len];
8671                 b_count = len & 3;
8672                 b_offset = offset + len - b_count;
8673                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8674                 if (ret)
8675                         return ret;
8676                 memcpy(pd, &val, b_count);
8677                 eeprom->len += b_count;
8678         }
8679         return 0;
8680 }
8681
8682 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8683
8684 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8685 {
8686         struct tg3 *tp = netdev_priv(dev);
8687         int ret;
8688         u32 offset, len, b_offset, odd_len;
8689         u8 *buf;
8690         __be32 start, end;
8691
8692         if (tp->link_config.phy_is_low_power)
8693                 return -EAGAIN;
8694
8695         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8696             eeprom->magic != TG3_EEPROM_MAGIC)
8697                 return -EINVAL;
8698
8699         offset = eeprom->offset;
8700         len = eeprom->len;
8701
8702         if ((b_offset = (offset & 3))) {
8703                 /* adjustments to start on required 4 byte boundary */
8704                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8705                 if (ret)
8706                         return ret;
8707                 len += b_offset;
8708                 offset &= ~3;
8709                 if (len < 4)
8710                         len = 4;
8711         }
8712
8713         odd_len = 0;
8714         if (len & 3) {
8715                 /* adjustments to end on required 4 byte boundary */
8716                 odd_len = 1;
8717                 len = (len + 3) & ~3;
8718                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8719                 if (ret)
8720                         return ret;
8721         }
8722
8723         buf = data;
8724         if (b_offset || odd_len) {
8725                 buf = kmalloc(len, GFP_KERNEL);
8726                 if (!buf)
8727                         return -ENOMEM;
8728                 if (b_offset)
8729                         memcpy(buf, &start, 4);
8730                 if (odd_len)
8731                         memcpy(buf+len-4, &end, 4);
8732                 memcpy(buf + b_offset, data, eeprom->len);
8733         }
8734
8735         ret = tg3_nvram_write_block(tp, offset, len, buf);
8736
8737         if (buf != data)
8738                 kfree(buf);
8739
8740         return ret;
8741 }
8742
8743 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8744 {
8745         struct tg3 *tp = netdev_priv(dev);
8746
8747         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8748                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8749                         return -EAGAIN;
8750                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8751         }
8752
8753         cmd->supported = (SUPPORTED_Autoneg);
8754
8755         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8756                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8757                                    SUPPORTED_1000baseT_Full);
8758
8759         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8760                 cmd->supported |= (SUPPORTED_100baseT_Half |
8761                                   SUPPORTED_100baseT_Full |
8762                                   SUPPORTED_10baseT_Half |
8763                                   SUPPORTED_10baseT_Full |
8764                                   SUPPORTED_TP);
8765                 cmd->port = PORT_TP;
8766         } else {
8767                 cmd->supported |= SUPPORTED_FIBRE;
8768                 cmd->port = PORT_FIBRE;
8769         }
8770
8771         cmd->advertising = tp->link_config.advertising;
8772         if (netif_running(dev)) {
8773                 cmd->speed = tp->link_config.active_speed;
8774                 cmd->duplex = tp->link_config.active_duplex;
8775         }
8776         cmd->phy_address = PHY_ADDR;
8777         cmd->transceiver = XCVR_INTERNAL;
8778         cmd->autoneg = tp->link_config.autoneg;
8779         cmd->maxtxpkt = 0;
8780         cmd->maxrxpkt = 0;
8781         return 0;
8782 }
8783
8784 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8785 {
8786         struct tg3 *tp = netdev_priv(dev);
8787
8788         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8789                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8790                         return -EAGAIN;
8791                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8792         }
8793
8794         if (cmd->autoneg != AUTONEG_ENABLE &&
8795             cmd->autoneg != AUTONEG_DISABLE)
8796                 return -EINVAL;
8797
8798         if (cmd->autoneg == AUTONEG_DISABLE &&
8799             cmd->duplex != DUPLEX_FULL &&
8800             cmd->duplex != DUPLEX_HALF)
8801                 return -EINVAL;
8802
8803         if (cmd->autoneg == AUTONEG_ENABLE) {
8804                 u32 mask = ADVERTISED_Autoneg |
8805                            ADVERTISED_Pause |
8806                            ADVERTISED_Asym_Pause;
8807
8808                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8809                         mask |= ADVERTISED_1000baseT_Half |
8810                                 ADVERTISED_1000baseT_Full;
8811
8812                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8813                         mask |= ADVERTISED_100baseT_Half |
8814                                 ADVERTISED_100baseT_Full |
8815                                 ADVERTISED_10baseT_Half |
8816                                 ADVERTISED_10baseT_Full |
8817                                 ADVERTISED_TP;
8818                 else
8819                         mask |= ADVERTISED_FIBRE;
8820
8821                 if (cmd->advertising & ~mask)
8822                         return -EINVAL;
8823
8824                 mask &= (ADVERTISED_1000baseT_Half |
8825                          ADVERTISED_1000baseT_Full |
8826                          ADVERTISED_100baseT_Half |
8827                          ADVERTISED_100baseT_Full |
8828                          ADVERTISED_10baseT_Half |
8829                          ADVERTISED_10baseT_Full);
8830
8831                 cmd->advertising &= mask;
8832         } else {
8833                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8834                         if (cmd->speed != SPEED_1000)
8835                                 return -EINVAL;
8836
8837                         if (cmd->duplex != DUPLEX_FULL)
8838                                 return -EINVAL;
8839                 } else {
8840                         if (cmd->speed != SPEED_100 &&
8841                             cmd->speed != SPEED_10)
8842                                 return -EINVAL;
8843                 }
8844         }
8845
8846         tg3_full_lock(tp, 0);
8847
8848         tp->link_config.autoneg = cmd->autoneg;
8849         if (cmd->autoneg == AUTONEG_ENABLE) {
8850                 tp->link_config.advertising = (cmd->advertising |
8851                                               ADVERTISED_Autoneg);
8852                 tp->link_config.speed = SPEED_INVALID;
8853                 tp->link_config.duplex = DUPLEX_INVALID;
8854         } else {
8855                 tp->link_config.advertising = 0;
8856                 tp->link_config.speed = cmd->speed;
8857                 tp->link_config.duplex = cmd->duplex;
8858         }
8859
8860         tp->link_config.orig_speed = tp->link_config.speed;
8861         tp->link_config.orig_duplex = tp->link_config.duplex;
8862         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8863
8864         if (netif_running(dev))
8865                 tg3_setup_phy(tp, 1);
8866
8867         tg3_full_unlock(tp);
8868
8869         return 0;
8870 }
8871
8872 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8873 {
8874         struct tg3 *tp = netdev_priv(dev);
8875
8876         strcpy(info->driver, DRV_MODULE_NAME);
8877         strcpy(info->version, DRV_MODULE_VERSION);
8878         strcpy(info->fw_version, tp->fw_ver);
8879         strcpy(info->bus_info, pci_name(tp->pdev));
8880 }
8881
8882 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8883 {
8884         struct tg3 *tp = netdev_priv(dev);
8885
8886         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8887             device_can_wakeup(&tp->pdev->dev))
8888                 wol->supported = WAKE_MAGIC;
8889         else
8890                 wol->supported = 0;
8891         wol->wolopts = 0;
8892         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8893             device_can_wakeup(&tp->pdev->dev))
8894                 wol->wolopts = WAKE_MAGIC;
8895         memset(&wol->sopass, 0, sizeof(wol->sopass));
8896 }
8897
8898 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8899 {
8900         struct tg3 *tp = netdev_priv(dev);
8901         struct device *dp = &tp->pdev->dev;
8902
8903         if (wol->wolopts & ~WAKE_MAGIC)
8904                 return -EINVAL;
8905         if ((wol->wolopts & WAKE_MAGIC) &&
8906             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8907                 return -EINVAL;
8908
8909         spin_lock_bh(&tp->lock);
8910         if (wol->wolopts & WAKE_MAGIC) {
8911                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8912                 device_set_wakeup_enable(dp, true);
8913         } else {
8914                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8915                 device_set_wakeup_enable(dp, false);
8916         }
8917         spin_unlock_bh(&tp->lock);
8918
8919         return 0;
8920 }
8921
8922 static u32 tg3_get_msglevel(struct net_device *dev)
8923 {
8924         struct tg3 *tp = netdev_priv(dev);
8925         return tp->msg_enable;
8926 }
8927
8928 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8929 {
8930         struct tg3 *tp = netdev_priv(dev);
8931         tp->msg_enable = value;
8932 }
8933
8934 static int tg3_set_tso(struct net_device *dev, u32 value)
8935 {
8936         struct tg3 *tp = netdev_priv(dev);
8937
8938         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8939                 if (value)
8940                         return -EINVAL;
8941                 return 0;
8942         }
8943         if ((dev->features & NETIF_F_IPV6_CSUM) &&
8944             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8945                 if (value) {
8946                         dev->features |= NETIF_F_TSO6;
8947                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8948                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8949                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8950                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8951                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8952                                 dev->features |= NETIF_F_TSO_ECN;
8953                 } else
8954                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8955         }
8956         return ethtool_op_set_tso(dev, value);
8957 }
8958
8959 static int tg3_nway_reset(struct net_device *dev)
8960 {
8961         struct tg3 *tp = netdev_priv(dev);
8962         int r;
8963
8964         if (!netif_running(dev))
8965                 return -EAGAIN;
8966
8967         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8968                 return -EINVAL;
8969
8970         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8971                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8972                         return -EAGAIN;
8973                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8974         } else {
8975                 u32 bmcr;
8976
8977                 spin_lock_bh(&tp->lock);
8978                 r = -EINVAL;
8979                 tg3_readphy(tp, MII_BMCR, &bmcr);
8980                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8981                     ((bmcr & BMCR_ANENABLE) ||
8982                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8983                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8984                                                    BMCR_ANENABLE);
8985                         r = 0;
8986                 }
8987                 spin_unlock_bh(&tp->lock);
8988         }
8989
8990         return r;
8991 }
8992
8993 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8994 {
8995         struct tg3 *tp = netdev_priv(dev);
8996
8997         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8998         ering->rx_mini_max_pending = 0;
8999         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9000                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9001         else
9002                 ering->rx_jumbo_max_pending = 0;
9003
9004         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9005
9006         ering->rx_pending = tp->rx_pending;
9007         ering->rx_mini_pending = 0;
9008         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9009                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9010         else
9011                 ering->rx_jumbo_pending = 0;
9012
9013         ering->tx_pending = tp->tx_pending;
9014 }
9015
9016 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9017 {
9018         struct tg3 *tp = netdev_priv(dev);
9019         int irq_sync = 0, err = 0;
9020
9021         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9022             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9023             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9024             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9025             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9026              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9027                 return -EINVAL;
9028
9029         if (netif_running(dev)) {
9030                 tg3_phy_stop(tp);
9031                 tg3_netif_stop(tp);
9032                 irq_sync = 1;
9033         }
9034
9035         tg3_full_lock(tp, irq_sync);
9036
9037         tp->rx_pending = ering->rx_pending;
9038
9039         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9040             tp->rx_pending > 63)
9041                 tp->rx_pending = 63;
9042         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9043         tp->tx_pending = ering->tx_pending;
9044
9045         if (netif_running(dev)) {
9046                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9047                 err = tg3_restart_hw(tp, 1);
9048                 if (!err)
9049                         tg3_netif_start(tp);
9050         }
9051
9052         tg3_full_unlock(tp);
9053
9054         if (irq_sync && !err)
9055                 tg3_phy_start(tp);
9056
9057         return err;
9058 }
9059
9060 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9061 {
9062         struct tg3 *tp = netdev_priv(dev);
9063
9064         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9065
9066         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9067                 epause->rx_pause = 1;
9068         else
9069                 epause->rx_pause = 0;
9070
9071         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9072                 epause->tx_pause = 1;
9073         else
9074                 epause->tx_pause = 0;
9075 }
9076
9077 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9078 {
9079         struct tg3 *tp = netdev_priv(dev);
9080         int err = 0;
9081
9082         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9083                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9084                         return -EAGAIN;
9085
9086                 if (epause->autoneg) {
9087                         u32 newadv;
9088                         struct phy_device *phydev;
9089
9090                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9091
9092                         if (epause->rx_pause) {
9093                                 if (epause->tx_pause)
9094                                         newadv = ADVERTISED_Pause;
9095                                 else
9096                                         newadv = ADVERTISED_Pause |
9097                                                  ADVERTISED_Asym_Pause;
9098                         } else if (epause->tx_pause) {
9099                                 newadv = ADVERTISED_Asym_Pause;
9100                         } else
9101                                 newadv = 0;
9102
9103                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9104                                 u32 oldadv = phydev->advertising &
9105                                              (ADVERTISED_Pause |
9106                                               ADVERTISED_Asym_Pause);
9107                                 if (oldadv != newadv) {
9108                                         phydev->advertising &=
9109                                                 ~(ADVERTISED_Pause |
9110                                                   ADVERTISED_Asym_Pause);
9111                                         phydev->advertising |= newadv;
9112                                         err = phy_start_aneg(phydev);
9113                                 }
9114                         } else {
9115                                 tp->link_config.advertising &=
9116                                                 ~(ADVERTISED_Pause |
9117                                                   ADVERTISED_Asym_Pause);
9118                                 tp->link_config.advertising |= newadv;
9119                         }
9120                 } else {
9121                         if (epause->rx_pause)
9122                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9123                         else
9124                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9125
9126                         if (epause->tx_pause)
9127                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9128                         else
9129                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9130
9131                         if (netif_running(dev))
9132                                 tg3_setup_flow_control(tp, 0, 0);
9133                 }
9134         } else {
9135                 int irq_sync = 0;
9136
9137                 if (netif_running(dev)) {
9138                         tg3_netif_stop(tp);
9139                         irq_sync = 1;
9140                 }
9141
9142                 tg3_full_lock(tp, irq_sync);
9143
9144                 if (epause->autoneg)
9145                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9146                 else
9147                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9148                 if (epause->rx_pause)
9149                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9150                 else
9151                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9152                 if (epause->tx_pause)
9153                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9154                 else
9155                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9156
9157                 if (netif_running(dev)) {
9158                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9159                         err = tg3_restart_hw(tp, 1);
9160                         if (!err)
9161                                 tg3_netif_start(tp);
9162                 }
9163
9164                 tg3_full_unlock(tp);
9165         }
9166
9167         return err;
9168 }
9169
9170 static u32 tg3_get_rx_csum(struct net_device *dev)
9171 {
9172         struct tg3 *tp = netdev_priv(dev);
9173         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9174 }
9175
9176 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9177 {
9178         struct tg3 *tp = netdev_priv(dev);
9179
9180         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9181                 if (data != 0)
9182                         return -EINVAL;
9183                 return 0;
9184         }
9185
9186         spin_lock_bh(&tp->lock);
9187         if (data)
9188                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9189         else
9190                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9191         spin_unlock_bh(&tp->lock);
9192
9193         return 0;
9194 }
9195
9196 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9197 {
9198         struct tg3 *tp = netdev_priv(dev);
9199
9200         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9201                 if (data != 0)
9202                         return -EINVAL;
9203                 return 0;
9204         }
9205
9206         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9207                 ethtool_op_set_tx_ipv6_csum(dev, data);
9208         else
9209                 ethtool_op_set_tx_csum(dev, data);
9210
9211         return 0;
9212 }
9213
9214 static int tg3_get_sset_count (struct net_device *dev, int sset)
9215 {
9216         switch (sset) {
9217         case ETH_SS_TEST:
9218                 return TG3_NUM_TEST;
9219         case ETH_SS_STATS:
9220                 return TG3_NUM_STATS;
9221         default:
9222                 return -EOPNOTSUPP;
9223         }
9224 }
9225
9226 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9227 {
9228         switch (stringset) {
9229         case ETH_SS_STATS:
9230                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9231                 break;
9232         case ETH_SS_TEST:
9233                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9234                 break;
9235         default:
9236                 WARN_ON(1);     /* we need a WARN() */
9237                 break;
9238         }
9239 }
9240
9241 static int tg3_phys_id(struct net_device *dev, u32 data)
9242 {
9243         struct tg3 *tp = netdev_priv(dev);
9244         int i;
9245
9246         if (!netif_running(tp->dev))
9247                 return -EAGAIN;
9248
9249         if (data == 0)
9250                 data = UINT_MAX / 2;
9251
9252         for (i = 0; i < (data * 2); i++) {
9253                 if ((i % 2) == 0)
9254                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9255                                            LED_CTRL_1000MBPS_ON |
9256                                            LED_CTRL_100MBPS_ON |
9257                                            LED_CTRL_10MBPS_ON |
9258                                            LED_CTRL_TRAFFIC_OVERRIDE |
9259                                            LED_CTRL_TRAFFIC_BLINK |
9260                                            LED_CTRL_TRAFFIC_LED);
9261
9262                 else
9263                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9264                                            LED_CTRL_TRAFFIC_OVERRIDE);
9265
9266                 if (msleep_interruptible(500))
9267                         break;
9268         }
9269         tw32(MAC_LED_CTRL, tp->led_ctrl);
9270         return 0;
9271 }
9272
9273 static void tg3_get_ethtool_stats (struct net_device *dev,
9274                                    struct ethtool_stats *estats, u64 *tmp_stats)
9275 {
9276         struct tg3 *tp = netdev_priv(dev);
9277         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9278 }
9279
9280 #define NVRAM_TEST_SIZE 0x100
9281 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9282 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9283 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9284 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9285 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9286
9287 static int tg3_test_nvram(struct tg3 *tp)
9288 {
9289         u32 csum, magic;
9290         __be32 *buf;
9291         int i, j, k, err = 0, size;
9292
9293         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9294                 return 0;
9295
9296         if (tg3_nvram_read(tp, 0, &magic) != 0)
9297                 return -EIO;
9298
9299         if (magic == TG3_EEPROM_MAGIC)
9300                 size = NVRAM_TEST_SIZE;
9301         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9302                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9303                     TG3_EEPROM_SB_FORMAT_1) {
9304                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9305                         case TG3_EEPROM_SB_REVISION_0:
9306                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9307                                 break;
9308                         case TG3_EEPROM_SB_REVISION_2:
9309                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9310                                 break;
9311                         case TG3_EEPROM_SB_REVISION_3:
9312                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9313                                 break;
9314                         default:
9315                                 return 0;
9316                         }
9317                 } else
9318                         return 0;
9319         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9320                 size = NVRAM_SELFBOOT_HW_SIZE;
9321         else
9322                 return -EIO;
9323
9324         buf = kmalloc(size, GFP_KERNEL);
9325         if (buf == NULL)
9326                 return -ENOMEM;
9327
9328         err = -EIO;
9329         for (i = 0, j = 0; i < size; i += 4, j++) {
9330                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9331                 if (err)
9332                         break;
9333         }
9334         if (i < size)
9335                 goto out;
9336
9337         /* Selfboot format */
9338         magic = be32_to_cpu(buf[0]);
9339         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9340             TG3_EEPROM_MAGIC_FW) {
9341                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9342
9343                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9344                     TG3_EEPROM_SB_REVISION_2) {
9345                         /* For rev 2, the csum doesn't include the MBA. */
9346                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9347                                 csum8 += buf8[i];
9348                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9349                                 csum8 += buf8[i];
9350                 } else {
9351                         for (i = 0; i < size; i++)
9352                                 csum8 += buf8[i];
9353                 }
9354
9355                 if (csum8 == 0) {
9356                         err = 0;
9357                         goto out;
9358                 }
9359
9360                 err = -EIO;
9361                 goto out;
9362         }
9363
9364         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9365             TG3_EEPROM_MAGIC_HW) {
9366                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9367                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9368                 u8 *buf8 = (u8 *) buf;
9369
9370                 /* Separate the parity bits and the data bytes.  */
9371                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9372                         if ((i == 0) || (i == 8)) {
9373                                 int l;
9374                                 u8 msk;
9375
9376                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9377                                         parity[k++] = buf8[i] & msk;
9378                                 i++;
9379                         }
9380                         else if (i == 16) {
9381                                 int l;
9382                                 u8 msk;
9383
9384                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9385                                         parity[k++] = buf8[i] & msk;
9386                                 i++;
9387
9388                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9389                                         parity[k++] = buf8[i] & msk;
9390                                 i++;
9391                         }
9392                         data[j++] = buf8[i];
9393                 }
9394
9395                 err = -EIO;
9396                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9397                         u8 hw8 = hweight8(data[i]);
9398
9399                         if ((hw8 & 0x1) && parity[i])
9400                                 goto out;
9401                         else if (!(hw8 & 0x1) && !parity[i])
9402                                 goto out;
9403                 }
9404                 err = 0;
9405                 goto out;
9406         }
9407
9408         /* Bootstrap checksum at offset 0x10 */
9409         csum = calc_crc((unsigned char *) buf, 0x10);
9410         if (csum != be32_to_cpu(buf[0x10/4]))
9411                 goto out;
9412
9413         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9414         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9415         if (csum != be32_to_cpu(buf[0xfc/4]))
9416                 goto out;
9417
9418         err = 0;
9419
9420 out:
9421         kfree(buf);
9422         return err;
9423 }
9424
9425 #define TG3_SERDES_TIMEOUT_SEC  2
9426 #define TG3_COPPER_TIMEOUT_SEC  6
9427
9428 static int tg3_test_link(struct tg3 *tp)
9429 {
9430         int i, max;
9431
9432         if (!netif_running(tp->dev))
9433                 return -ENODEV;
9434
9435         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9436                 max = TG3_SERDES_TIMEOUT_SEC;
9437         else
9438                 max = TG3_COPPER_TIMEOUT_SEC;
9439
9440         for (i = 0; i < max; i++) {
9441                 if (netif_carrier_ok(tp->dev))
9442                         return 0;
9443
9444                 if (msleep_interruptible(1000))
9445                         break;
9446         }
9447
9448         return -EIO;
9449 }
9450
9451 /* Only test the commonly used registers */
9452 static int tg3_test_registers(struct tg3 *tp)
9453 {
9454         int i, is_5705, is_5750;
9455         u32 offset, read_mask, write_mask, val, save_val, read_val;
9456         static struct {
9457                 u16 offset;
9458                 u16 flags;
9459 #define TG3_FL_5705     0x1
9460 #define TG3_FL_NOT_5705 0x2
9461 #define TG3_FL_NOT_5788 0x4
9462 #define TG3_FL_NOT_5750 0x8
9463                 u32 read_mask;
9464                 u32 write_mask;
9465         } reg_tbl[] = {
9466                 /* MAC Control Registers */
9467                 { MAC_MODE, TG3_FL_NOT_5705,
9468                         0x00000000, 0x00ef6f8c },
9469                 { MAC_MODE, TG3_FL_5705,
9470                         0x00000000, 0x01ef6b8c },
9471                 { MAC_STATUS, TG3_FL_NOT_5705,
9472                         0x03800107, 0x00000000 },
9473                 { MAC_STATUS, TG3_FL_5705,
9474                         0x03800100, 0x00000000 },
9475                 { MAC_ADDR_0_HIGH, 0x0000,
9476                         0x00000000, 0x0000ffff },
9477                 { MAC_ADDR_0_LOW, 0x0000,
9478                         0x00000000, 0xffffffff },
9479                 { MAC_RX_MTU_SIZE, 0x0000,
9480                         0x00000000, 0x0000ffff },
9481                 { MAC_TX_MODE, 0x0000,
9482                         0x00000000, 0x00000070 },
9483                 { MAC_TX_LENGTHS, 0x0000,
9484                         0x00000000, 0x00003fff },
9485                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9486                         0x00000000, 0x000007fc },
9487                 { MAC_RX_MODE, TG3_FL_5705,
9488                         0x00000000, 0x000007dc },
9489                 { MAC_HASH_REG_0, 0x0000,
9490                         0x00000000, 0xffffffff },
9491                 { MAC_HASH_REG_1, 0x0000,
9492                         0x00000000, 0xffffffff },
9493                 { MAC_HASH_REG_2, 0x0000,
9494                         0x00000000, 0xffffffff },
9495                 { MAC_HASH_REG_3, 0x0000,
9496                         0x00000000, 0xffffffff },
9497
9498                 /* Receive Data and Receive BD Initiator Control Registers. */
9499                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9500                         0x00000000, 0xffffffff },
9501                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9502                         0x00000000, 0xffffffff },
9503                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9504                         0x00000000, 0x00000003 },
9505                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9506                         0x00000000, 0xffffffff },
9507                 { RCVDBDI_STD_BD+0, 0x0000,
9508                         0x00000000, 0xffffffff },
9509                 { RCVDBDI_STD_BD+4, 0x0000,
9510                         0x00000000, 0xffffffff },
9511                 { RCVDBDI_STD_BD+8, 0x0000,
9512                         0x00000000, 0xffff0002 },
9513                 { RCVDBDI_STD_BD+0xc, 0x0000,
9514                         0x00000000, 0xffffffff },
9515
9516                 /* Receive BD Initiator Control Registers. */
9517                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9518                         0x00000000, 0xffffffff },
9519                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9520                         0x00000000, 0x000003ff },
9521                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9522                         0x00000000, 0xffffffff },
9523
9524                 /* Host Coalescing Control Registers. */
9525                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9526                         0x00000000, 0x00000004 },
9527                 { HOSTCC_MODE, TG3_FL_5705,
9528                         0x00000000, 0x000000f6 },
9529                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9530                         0x00000000, 0xffffffff },
9531                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9532                         0x00000000, 0x000003ff },
9533                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9534                         0x00000000, 0xffffffff },
9535                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9536                         0x00000000, 0x000003ff },
9537                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9538                         0x00000000, 0xffffffff },
9539                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9540                         0x00000000, 0x000000ff },
9541                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9542                         0x00000000, 0xffffffff },
9543                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9544                         0x00000000, 0x000000ff },
9545                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9546                         0x00000000, 0xffffffff },
9547                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9548                         0x00000000, 0xffffffff },
9549                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9550                         0x00000000, 0xffffffff },
9551                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9552                         0x00000000, 0x000000ff },
9553                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9554                         0x00000000, 0xffffffff },
9555                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9556                         0x00000000, 0x000000ff },
9557                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9558                         0x00000000, 0xffffffff },
9559                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9560                         0x00000000, 0xffffffff },
9561                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9562                         0x00000000, 0xffffffff },
9563                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9564                         0x00000000, 0xffffffff },
9565                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9566                         0x00000000, 0xffffffff },
9567                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9568                         0xffffffff, 0x00000000 },
9569                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9570                         0xffffffff, 0x00000000 },
9571
9572                 /* Buffer Manager Control Registers. */
9573                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9574                         0x00000000, 0x007fff80 },
9575                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9576                         0x00000000, 0x007fffff },
9577                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9578                         0x00000000, 0x0000003f },
9579                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9580                         0x00000000, 0x000001ff },
9581                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9582                         0x00000000, 0x000001ff },
9583                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9584                         0xffffffff, 0x00000000 },
9585                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9586                         0xffffffff, 0x00000000 },
9587
9588                 /* Mailbox Registers */
9589                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9590                         0x00000000, 0x000001ff },
9591                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9592                         0x00000000, 0x000001ff },
9593                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9594                         0x00000000, 0x000007ff },
9595                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9596                         0x00000000, 0x000001ff },
9597
9598                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9599         };
9600
9601         is_5705 = is_5750 = 0;
9602         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9603                 is_5705 = 1;
9604                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9605                         is_5750 = 1;
9606         }
9607
9608         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9609                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9610                         continue;
9611
9612                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9613                         continue;
9614
9615                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9616                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9617                         continue;
9618
9619                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9620                         continue;
9621
9622                 offset = (u32) reg_tbl[i].offset;
9623                 read_mask = reg_tbl[i].read_mask;
9624                 write_mask = reg_tbl[i].write_mask;
9625
9626                 /* Save the original register content */
9627                 save_val = tr32(offset);
9628
9629                 /* Determine the read-only value. */
9630                 read_val = save_val & read_mask;
9631
9632                 /* Write zero to the register, then make sure the read-only bits
9633                  * are not changed and the read/write bits are all zeros.
9634                  */
9635                 tw32(offset, 0);
9636
9637                 val = tr32(offset);
9638
9639                 /* Test the read-only and read/write bits. */
9640                 if (((val & read_mask) != read_val) || (val & write_mask))
9641                         goto out;
9642
9643                 /* Write ones to all the bits defined by RdMask and WrMask, then
9644                  * make sure the read-only bits are not changed and the
9645                  * read/write bits are all ones.
9646                  */
9647                 tw32(offset, read_mask | write_mask);
9648
9649                 val = tr32(offset);
9650
9651                 /* Test the read-only bits. */
9652                 if ((val & read_mask) != read_val)
9653                         goto out;
9654
9655                 /* Test the read/write bits. */
9656                 if ((val & write_mask) != write_mask)
9657                         goto out;
9658
9659                 tw32(offset, save_val);
9660         }
9661
9662         return 0;
9663
9664 out:
9665         if (netif_msg_hw(tp))
9666                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9667                        offset);
9668         tw32(offset, save_val);
9669         return -EIO;
9670 }
9671
9672 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9673 {
9674         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9675         int i;
9676         u32 j;
9677
9678         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9679                 for (j = 0; j < len; j += 4) {
9680                         u32 val;
9681
9682                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9683                         tg3_read_mem(tp, offset + j, &val);
9684                         if (val != test_pattern[i])
9685                                 return -EIO;
9686                 }
9687         }
9688         return 0;
9689 }
9690
9691 static int tg3_test_memory(struct tg3 *tp)
9692 {
9693         static struct mem_entry {
9694                 u32 offset;
9695                 u32 len;
9696         } mem_tbl_570x[] = {
9697                 { 0x00000000, 0x00b50},
9698                 { 0x00002000, 0x1c000},
9699                 { 0xffffffff, 0x00000}
9700         }, mem_tbl_5705[] = {
9701                 { 0x00000100, 0x0000c},
9702                 { 0x00000200, 0x00008},
9703                 { 0x00004000, 0x00800},
9704                 { 0x00006000, 0x01000},
9705                 { 0x00008000, 0x02000},
9706                 { 0x00010000, 0x0e000},
9707                 { 0xffffffff, 0x00000}
9708         }, mem_tbl_5755[] = {
9709                 { 0x00000200, 0x00008},
9710                 { 0x00004000, 0x00800},
9711                 { 0x00006000, 0x00800},
9712                 { 0x00008000, 0x02000},
9713                 { 0x00010000, 0x0c000},
9714                 { 0xffffffff, 0x00000}
9715         }, mem_tbl_5906[] = {
9716                 { 0x00000200, 0x00008},
9717                 { 0x00004000, 0x00400},
9718                 { 0x00006000, 0x00400},
9719                 { 0x00008000, 0x01000},
9720                 { 0x00010000, 0x01000},
9721                 { 0xffffffff, 0x00000}
9722         };
9723         struct mem_entry *mem_tbl;
9724         int err = 0;
9725         int i;
9726
9727         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9728                 mem_tbl = mem_tbl_5755;
9729         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9730                 mem_tbl = mem_tbl_5906;
9731         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9732                 mem_tbl = mem_tbl_5705;
9733         else
9734                 mem_tbl = mem_tbl_570x;
9735
9736         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9737                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9738                     mem_tbl[i].len)) != 0)
9739                         break;
9740         }
9741
9742         return err;
9743 }
9744
9745 #define TG3_MAC_LOOPBACK        0
9746 #define TG3_PHY_LOOPBACK        1
9747
9748 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9749 {
9750         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9751         u32 desc_idx;
9752         struct sk_buff *skb, *rx_skb;
9753         u8 *tx_data;
9754         dma_addr_t map;
9755         int num_pkts, tx_len, rx_len, i, err;
9756         struct tg3_rx_buffer_desc *desc;
9757
9758         if (loopback_mode == TG3_MAC_LOOPBACK) {
9759                 /* HW errata - mac loopback fails in some cases on 5780.
9760                  * Normal traffic and PHY loopback are not affected by
9761                  * errata.
9762                  */
9763                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9764                         return 0;
9765
9766                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9767                            MAC_MODE_PORT_INT_LPBACK;
9768                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9769                         mac_mode |= MAC_MODE_LINK_POLARITY;
9770                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9771                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9772                 else
9773                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9774                 tw32(MAC_MODE, mac_mode);
9775         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9776                 u32 val;
9777
9778                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9779                         tg3_phy_fet_toggle_apd(tp, false);
9780                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9781                 } else
9782                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9783
9784                 tg3_phy_toggle_automdix(tp, 0);
9785
9786                 tg3_writephy(tp, MII_BMCR, val);
9787                 udelay(40);
9788
9789                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9790                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9791                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9792                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9793                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9794                 } else
9795                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9796
9797                 /* reset to prevent losing 1st rx packet intermittently */
9798                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9799                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9800                         udelay(10);
9801                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9802                 }
9803                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9804                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9805                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9806                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9807                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9808                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9809                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9810                 }
9811                 tw32(MAC_MODE, mac_mode);
9812         }
9813         else
9814                 return -EINVAL;
9815
9816         err = -EIO;
9817
9818         tx_len = 1514;
9819         skb = netdev_alloc_skb(tp->dev, tx_len);
9820         if (!skb)
9821                 return -ENOMEM;
9822
9823         tx_data = skb_put(skb, tx_len);
9824         memcpy(tx_data, tp->dev->dev_addr, 6);
9825         memset(tx_data + 6, 0x0, 8);
9826
9827         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9828
9829         for (i = 14; i < tx_len; i++)
9830                 tx_data[i] = (u8) (i & 0xff);
9831
9832         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9833
9834         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9835              HOSTCC_MODE_NOW);
9836
9837         udelay(10);
9838
9839         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9840
9841         num_pkts = 0;
9842
9843         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9844
9845         tp->tx_prod++;
9846         num_pkts++;
9847
9848         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9849                      tp->tx_prod);
9850         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9851
9852         udelay(10);
9853
9854         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9855         for (i = 0; i < 25; i++) {
9856                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9857                        HOSTCC_MODE_NOW);
9858
9859                 udelay(10);
9860
9861                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9862                 rx_idx = tp->hw_status->idx[0].rx_producer;
9863                 if ((tx_idx == tp->tx_prod) &&
9864                     (rx_idx == (rx_start_idx + num_pkts)))
9865                         break;
9866         }
9867
9868         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9869         dev_kfree_skb(skb);
9870
9871         if (tx_idx != tp->tx_prod)
9872                 goto out;
9873
9874         if (rx_idx != rx_start_idx + num_pkts)
9875                 goto out;
9876
9877         desc = &tp->rx_rcb[rx_start_idx];
9878         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9879         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9880         if (opaque_key != RXD_OPAQUE_RING_STD)
9881                 goto out;
9882
9883         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9884             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9885                 goto out;
9886
9887         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9888         if (rx_len != tx_len)
9889                 goto out;
9890
9891         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9892
9893         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9894         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9895
9896         for (i = 14; i < tx_len; i++) {
9897                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9898                         goto out;
9899         }
9900         err = 0;
9901
9902         /* tg3_free_rings will unmap and free the rx_skb */
9903 out:
9904         return err;
9905 }
9906
9907 #define TG3_MAC_LOOPBACK_FAILED         1
9908 #define TG3_PHY_LOOPBACK_FAILED         2
9909 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9910                                          TG3_PHY_LOOPBACK_FAILED)
9911
9912 static int tg3_test_loopback(struct tg3 *tp)
9913 {
9914         int err = 0;
9915         u32 cpmuctrl = 0;
9916
9917         if (!netif_running(tp->dev))
9918                 return TG3_LOOPBACK_FAILED;
9919
9920         err = tg3_reset_hw(tp, 1);
9921         if (err)
9922                 return TG3_LOOPBACK_FAILED;
9923
9924         /* Turn off gphy autopowerdown. */
9925         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9926                 tg3_phy_toggle_apd(tp, false);
9927
9928         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9929                 int i;
9930                 u32 status;
9931
9932                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9933
9934                 /* Wait for up to 40 microseconds to acquire lock. */
9935                 for (i = 0; i < 4; i++) {
9936                         status = tr32(TG3_CPMU_MUTEX_GNT);
9937                         if (status == CPMU_MUTEX_GNT_DRIVER)
9938                                 break;
9939                         udelay(10);
9940                 }
9941
9942                 if (status != CPMU_MUTEX_GNT_DRIVER)
9943                         return TG3_LOOPBACK_FAILED;
9944
9945                 /* Turn off link-based power management. */
9946                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9947                 tw32(TG3_CPMU_CTRL,
9948                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9949                                   CPMU_CTRL_LINK_AWARE_MODE));
9950         }
9951
9952         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9953                 err |= TG3_MAC_LOOPBACK_FAILED;
9954
9955         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9956                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9957
9958                 /* Release the mutex */
9959                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9960         }
9961
9962         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9963             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9964                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9965                         err |= TG3_PHY_LOOPBACK_FAILED;
9966         }
9967
9968         /* Re-enable gphy autopowerdown. */
9969         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9970                 tg3_phy_toggle_apd(tp, true);
9971
9972         return err;
9973 }
9974
9975 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9976                           u64 *data)
9977 {
9978         struct tg3 *tp = netdev_priv(dev);
9979
9980         if (tp->link_config.phy_is_low_power)
9981                 tg3_set_power_state(tp, PCI_D0);
9982
9983         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9984
9985         if (tg3_test_nvram(tp) != 0) {
9986                 etest->flags |= ETH_TEST_FL_FAILED;
9987                 data[0] = 1;
9988         }
9989         if (tg3_test_link(tp) != 0) {
9990                 etest->flags |= ETH_TEST_FL_FAILED;
9991                 data[1] = 1;
9992         }
9993         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9994                 int err, err2 = 0, irq_sync = 0;
9995
9996                 if (netif_running(dev)) {
9997                         tg3_phy_stop(tp);
9998                         tg3_netif_stop(tp);
9999                         irq_sync = 1;
10000                 }
10001
10002                 tg3_full_lock(tp, irq_sync);
10003
10004                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10005                 err = tg3_nvram_lock(tp);
10006                 tg3_halt_cpu(tp, RX_CPU_BASE);
10007                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10008                         tg3_halt_cpu(tp, TX_CPU_BASE);
10009                 if (!err)
10010                         tg3_nvram_unlock(tp);
10011
10012                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10013                         tg3_phy_reset(tp);
10014
10015                 if (tg3_test_registers(tp) != 0) {
10016                         etest->flags |= ETH_TEST_FL_FAILED;
10017                         data[2] = 1;
10018                 }
10019                 if (tg3_test_memory(tp) != 0) {
10020                         etest->flags |= ETH_TEST_FL_FAILED;
10021                         data[3] = 1;
10022                 }
10023                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10024                         etest->flags |= ETH_TEST_FL_FAILED;
10025
10026                 tg3_full_unlock(tp);
10027
10028                 if (tg3_test_interrupt(tp) != 0) {
10029                         etest->flags |= ETH_TEST_FL_FAILED;
10030                         data[5] = 1;
10031                 }
10032
10033                 tg3_full_lock(tp, 0);
10034
10035                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10036                 if (netif_running(dev)) {
10037                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10038                         err2 = tg3_restart_hw(tp, 1);
10039                         if (!err2)
10040                                 tg3_netif_start(tp);
10041                 }
10042
10043                 tg3_full_unlock(tp);
10044
10045                 if (irq_sync && !err2)
10046                         tg3_phy_start(tp);
10047         }
10048         if (tp->link_config.phy_is_low_power)
10049                 tg3_set_power_state(tp, PCI_D3hot);
10050
10051 }
10052
10053 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10054 {
10055         struct mii_ioctl_data *data = if_mii(ifr);
10056         struct tg3 *tp = netdev_priv(dev);
10057         int err;
10058
10059         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10060                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10061                         return -EAGAIN;
10062                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10063         }
10064
10065         switch(cmd) {
10066         case SIOCGMIIPHY:
10067                 data->phy_id = PHY_ADDR;
10068
10069                 /* fallthru */
10070         case SIOCGMIIREG: {
10071                 u32 mii_regval;
10072
10073                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10074                         break;                  /* We have no PHY */
10075
10076                 if (tp->link_config.phy_is_low_power)
10077                         return -EAGAIN;
10078
10079                 spin_lock_bh(&tp->lock);
10080                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10081                 spin_unlock_bh(&tp->lock);
10082
10083                 data->val_out = mii_regval;
10084
10085                 return err;
10086         }
10087
10088         case SIOCSMIIREG:
10089                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10090                         break;                  /* We have no PHY */
10091
10092                 if (!capable(CAP_NET_ADMIN))
10093                         return -EPERM;
10094
10095                 if (tp->link_config.phy_is_low_power)
10096                         return -EAGAIN;
10097
10098                 spin_lock_bh(&tp->lock);
10099                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10100                 spin_unlock_bh(&tp->lock);
10101
10102                 return err;
10103
10104         default:
10105                 /* do nothing */
10106                 break;
10107         }
10108         return -EOPNOTSUPP;
10109 }
10110
10111 #if TG3_VLAN_TAG_USED
10112 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10113 {
10114         struct tg3 *tp = netdev_priv(dev);
10115
10116         if (!netif_running(dev)) {
10117                 tp->vlgrp = grp;
10118                 return;
10119         }
10120
10121         tg3_netif_stop(tp);
10122
10123         tg3_full_lock(tp, 0);
10124
10125         tp->vlgrp = grp;
10126
10127         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10128         __tg3_set_rx_mode(dev);
10129
10130         tg3_netif_start(tp);
10131
10132         tg3_full_unlock(tp);
10133 }
10134 #endif
10135
10136 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10137 {
10138         struct tg3 *tp = netdev_priv(dev);
10139
10140         memcpy(ec, &tp->coal, sizeof(*ec));
10141         return 0;
10142 }
10143
10144 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10145 {
10146         struct tg3 *tp = netdev_priv(dev);
10147         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10148         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10149
10150         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10151                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10152                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10153                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10154                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10155         }
10156
10157         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10158             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10159             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10160             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10161             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10162             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10163             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10164             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10165             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10166             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10167                 return -EINVAL;
10168
10169         /* No rx interrupts will be generated if both are zero */
10170         if ((ec->rx_coalesce_usecs == 0) &&
10171             (ec->rx_max_coalesced_frames == 0))
10172                 return -EINVAL;
10173
10174         /* No tx interrupts will be generated if both are zero */
10175         if ((ec->tx_coalesce_usecs == 0) &&
10176             (ec->tx_max_coalesced_frames == 0))
10177                 return -EINVAL;
10178
10179         /* Only copy relevant parameters, ignore all others. */
10180         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10181         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10182         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10183         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10184         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10185         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10186         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10187         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10188         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10189
10190         if (netif_running(dev)) {
10191                 tg3_full_lock(tp, 0);
10192                 __tg3_set_coalesce(tp, &tp->coal);
10193                 tg3_full_unlock(tp);
10194         }
10195         return 0;
10196 }
10197
10198 static const struct ethtool_ops tg3_ethtool_ops = {
10199         .get_settings           = tg3_get_settings,
10200         .set_settings           = tg3_set_settings,
10201         .get_drvinfo            = tg3_get_drvinfo,
10202         .get_regs_len           = tg3_get_regs_len,
10203         .get_regs               = tg3_get_regs,
10204         .get_wol                = tg3_get_wol,
10205         .set_wol                = tg3_set_wol,
10206         .get_msglevel           = tg3_get_msglevel,
10207         .set_msglevel           = tg3_set_msglevel,
10208         .nway_reset             = tg3_nway_reset,
10209         .get_link               = ethtool_op_get_link,
10210         .get_eeprom_len         = tg3_get_eeprom_len,
10211         .get_eeprom             = tg3_get_eeprom,
10212         .set_eeprom             = tg3_set_eeprom,
10213         .get_ringparam          = tg3_get_ringparam,
10214         .set_ringparam          = tg3_set_ringparam,
10215         .get_pauseparam         = tg3_get_pauseparam,
10216         .set_pauseparam         = tg3_set_pauseparam,
10217         .get_rx_csum            = tg3_get_rx_csum,
10218         .set_rx_csum            = tg3_set_rx_csum,
10219         .set_tx_csum            = tg3_set_tx_csum,
10220         .set_sg                 = ethtool_op_set_sg,
10221         .set_tso                = tg3_set_tso,
10222         .self_test              = tg3_self_test,
10223         .get_strings            = tg3_get_strings,
10224         .phys_id                = tg3_phys_id,
10225         .get_ethtool_stats      = tg3_get_ethtool_stats,
10226         .get_coalesce           = tg3_get_coalesce,
10227         .set_coalesce           = tg3_set_coalesce,
10228         .get_sset_count         = tg3_get_sset_count,
10229 };
10230
10231 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10232 {
10233         u32 cursize, val, magic;
10234
10235         tp->nvram_size = EEPROM_CHIP_SIZE;
10236
10237         if (tg3_nvram_read(tp, 0, &magic) != 0)
10238                 return;
10239
10240         if ((magic != TG3_EEPROM_MAGIC) &&
10241             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10242             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10243                 return;
10244
10245         /*
10246          * Size the chip by reading offsets at increasing powers of two.
10247          * When we encounter our validation signature, we know the addressing
10248          * has wrapped around, and thus have our chip size.
10249          */
10250         cursize = 0x10;
10251
10252         while (cursize < tp->nvram_size) {
10253                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10254                         return;
10255
10256                 if (val == magic)
10257                         break;
10258
10259                 cursize <<= 1;
10260         }
10261
10262         tp->nvram_size = cursize;
10263 }
10264
10265 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10266 {
10267         u32 val;
10268
10269         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10270             tg3_nvram_read(tp, 0, &val) != 0)
10271                 return;
10272
10273         /* Selfboot format */
10274         if (val != TG3_EEPROM_MAGIC) {
10275                 tg3_get_eeprom_size(tp);
10276                 return;
10277         }
10278
10279         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10280                 if (val != 0) {
10281                         /* This is confusing.  We want to operate on the
10282                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10283                          * call will read from NVRAM and byteswap the data
10284                          * according to the byteswapping settings for all
10285                          * other register accesses.  This ensures the data we
10286                          * want will always reside in the lower 16-bits.
10287                          * However, the data in NVRAM is in LE format, which
10288                          * means the data from the NVRAM read will always be
10289                          * opposite the endianness of the CPU.  The 16-bit
10290                          * byteswap then brings the data to CPU endianness.
10291                          */
10292                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10293                         return;
10294                 }
10295         }
10296         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10297 }
10298
10299 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10300 {
10301         u32 nvcfg1;
10302
10303         nvcfg1 = tr32(NVRAM_CFG1);
10304         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10305                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10306         } else {
10307                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10308                 tw32(NVRAM_CFG1, nvcfg1);
10309         }
10310
10311         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10312             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10313                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10314                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10315                         tp->nvram_jedecnum = JEDEC_ATMEL;
10316                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10317                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10318                         break;
10319                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10320                         tp->nvram_jedecnum = JEDEC_ATMEL;
10321                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10322                         break;
10323                 case FLASH_VENDOR_ATMEL_EEPROM:
10324                         tp->nvram_jedecnum = JEDEC_ATMEL;
10325                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10326                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10327                         break;
10328                 case FLASH_VENDOR_ST:
10329                         tp->nvram_jedecnum = JEDEC_ST;
10330                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10331                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10332                         break;
10333                 case FLASH_VENDOR_SAIFUN:
10334                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10335                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10336                         break;
10337                 case FLASH_VENDOR_SST_SMALL:
10338                 case FLASH_VENDOR_SST_LARGE:
10339                         tp->nvram_jedecnum = JEDEC_SST;
10340                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10341                         break;
10342                 }
10343         } else {
10344                 tp->nvram_jedecnum = JEDEC_ATMEL;
10345                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10346                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10347         }
10348 }
10349
10350 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10351 {
10352         u32 nvcfg1;
10353
10354         nvcfg1 = tr32(NVRAM_CFG1);
10355
10356         /* NVRAM protection for TPM */
10357         if (nvcfg1 & (1 << 27))
10358                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10359
10360         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10361         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10362         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10363                 tp->nvram_jedecnum = JEDEC_ATMEL;
10364                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10365                 break;
10366         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10367                 tp->nvram_jedecnum = JEDEC_ATMEL;
10368                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10369                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10370                 break;
10371         case FLASH_5752VENDOR_ST_M45PE10:
10372         case FLASH_5752VENDOR_ST_M45PE20:
10373         case FLASH_5752VENDOR_ST_M45PE40:
10374                 tp->nvram_jedecnum = JEDEC_ST;
10375                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10377                 break;
10378         }
10379
10380         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10381                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10382                 case FLASH_5752PAGE_SIZE_256:
10383                         tp->nvram_pagesize = 256;
10384                         break;
10385                 case FLASH_5752PAGE_SIZE_512:
10386                         tp->nvram_pagesize = 512;
10387                         break;
10388                 case FLASH_5752PAGE_SIZE_1K:
10389                         tp->nvram_pagesize = 1024;
10390                         break;
10391                 case FLASH_5752PAGE_SIZE_2K:
10392                         tp->nvram_pagesize = 2048;
10393                         break;
10394                 case FLASH_5752PAGE_SIZE_4K:
10395                         tp->nvram_pagesize = 4096;
10396                         break;
10397                 case FLASH_5752PAGE_SIZE_264:
10398                         tp->nvram_pagesize = 264;
10399                         break;
10400                 }
10401         } else {
10402                 /* For eeprom, set pagesize to maximum eeprom size */
10403                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10404
10405                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10406                 tw32(NVRAM_CFG1, nvcfg1);
10407         }
10408 }
10409
10410 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10411 {
10412         u32 nvcfg1, protect = 0;
10413
10414         nvcfg1 = tr32(NVRAM_CFG1);
10415
10416         /* NVRAM protection for TPM */
10417         if (nvcfg1 & (1 << 27)) {
10418                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10419                 protect = 1;
10420         }
10421
10422         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10423         switch (nvcfg1) {
10424         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10425         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10426         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10427         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10428                 tp->nvram_jedecnum = JEDEC_ATMEL;
10429                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10430                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10431                 tp->nvram_pagesize = 264;
10432                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10433                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10434                         tp->nvram_size = (protect ? 0x3e200 :
10435                                           TG3_NVRAM_SIZE_512KB);
10436                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10437                         tp->nvram_size = (protect ? 0x1f200 :
10438                                           TG3_NVRAM_SIZE_256KB);
10439                 else
10440                         tp->nvram_size = (protect ? 0x1f200 :
10441                                           TG3_NVRAM_SIZE_128KB);
10442                 break;
10443         case FLASH_5752VENDOR_ST_M45PE10:
10444         case FLASH_5752VENDOR_ST_M45PE20:
10445         case FLASH_5752VENDOR_ST_M45PE40:
10446                 tp->nvram_jedecnum = JEDEC_ST;
10447                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10448                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10449                 tp->nvram_pagesize = 256;
10450                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10451                         tp->nvram_size = (protect ?
10452                                           TG3_NVRAM_SIZE_64KB :
10453                                           TG3_NVRAM_SIZE_128KB);
10454                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10455                         tp->nvram_size = (protect ?
10456                                           TG3_NVRAM_SIZE_64KB :
10457                                           TG3_NVRAM_SIZE_256KB);
10458                 else
10459                         tp->nvram_size = (protect ?
10460                                           TG3_NVRAM_SIZE_128KB :
10461                                           TG3_NVRAM_SIZE_512KB);
10462                 break;
10463         }
10464 }
10465
10466 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10467 {
10468         u32 nvcfg1;
10469
10470         nvcfg1 = tr32(NVRAM_CFG1);
10471
10472         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10473         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10474         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10475         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10476         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10477                 tp->nvram_jedecnum = JEDEC_ATMEL;
10478                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10479                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10480
10481                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10482                 tw32(NVRAM_CFG1, nvcfg1);
10483                 break;
10484         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10485         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10486         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10487         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10488                 tp->nvram_jedecnum = JEDEC_ATMEL;
10489                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10490                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10491                 tp->nvram_pagesize = 264;
10492                 break;
10493         case FLASH_5752VENDOR_ST_M45PE10:
10494         case FLASH_5752VENDOR_ST_M45PE20:
10495         case FLASH_5752VENDOR_ST_M45PE40:
10496                 tp->nvram_jedecnum = JEDEC_ST;
10497                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10498                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10499                 tp->nvram_pagesize = 256;
10500                 break;
10501         }
10502 }
10503
10504 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10505 {
10506         u32 nvcfg1, protect = 0;
10507
10508         nvcfg1 = tr32(NVRAM_CFG1);
10509
10510         /* NVRAM protection for TPM */
10511         if (nvcfg1 & (1 << 27)) {
10512                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10513                 protect = 1;
10514         }
10515
10516         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10517         switch (nvcfg1) {
10518         case FLASH_5761VENDOR_ATMEL_ADB021D:
10519         case FLASH_5761VENDOR_ATMEL_ADB041D:
10520         case FLASH_5761VENDOR_ATMEL_ADB081D:
10521         case FLASH_5761VENDOR_ATMEL_ADB161D:
10522         case FLASH_5761VENDOR_ATMEL_MDB021D:
10523         case FLASH_5761VENDOR_ATMEL_MDB041D:
10524         case FLASH_5761VENDOR_ATMEL_MDB081D:
10525         case FLASH_5761VENDOR_ATMEL_MDB161D:
10526                 tp->nvram_jedecnum = JEDEC_ATMEL;
10527                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10528                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10529                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10530                 tp->nvram_pagesize = 256;
10531                 break;
10532         case FLASH_5761VENDOR_ST_A_M45PE20:
10533         case FLASH_5761VENDOR_ST_A_M45PE40:
10534         case FLASH_5761VENDOR_ST_A_M45PE80:
10535         case FLASH_5761VENDOR_ST_A_M45PE16:
10536         case FLASH_5761VENDOR_ST_M_M45PE20:
10537         case FLASH_5761VENDOR_ST_M_M45PE40:
10538         case FLASH_5761VENDOR_ST_M_M45PE80:
10539         case FLASH_5761VENDOR_ST_M_M45PE16:
10540                 tp->nvram_jedecnum = JEDEC_ST;
10541                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10542                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10543                 tp->nvram_pagesize = 256;
10544                 break;
10545         }
10546
10547         if (protect) {
10548                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10549         } else {
10550                 switch (nvcfg1) {
10551                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10552                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10553                 case FLASH_5761VENDOR_ST_A_M45PE16:
10554                 case FLASH_5761VENDOR_ST_M_M45PE16:
10555                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10556                         break;
10557                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10558                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10559                 case FLASH_5761VENDOR_ST_A_M45PE80:
10560                 case FLASH_5761VENDOR_ST_M_M45PE80:
10561                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10562                         break;
10563                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10564                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10565                 case FLASH_5761VENDOR_ST_A_M45PE40:
10566                 case FLASH_5761VENDOR_ST_M_M45PE40:
10567                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10568                         break;
10569                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10570                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10571                 case FLASH_5761VENDOR_ST_A_M45PE20:
10572                 case FLASH_5761VENDOR_ST_M_M45PE20:
10573                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10574                         break;
10575                 }
10576         }
10577 }
10578
10579 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10580 {
10581         tp->nvram_jedecnum = JEDEC_ATMEL;
10582         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10583         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10584 }
10585
10586 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10587 {
10588         u32 nvcfg1;
10589
10590         nvcfg1 = tr32(NVRAM_CFG1);
10591
10592         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10593         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10594         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10595                 tp->nvram_jedecnum = JEDEC_ATMEL;
10596                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10597                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10598
10599                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10600                 tw32(NVRAM_CFG1, nvcfg1);
10601                 return;
10602         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10603         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10604         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10605         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10606         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10607         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10608         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10609                 tp->nvram_jedecnum = JEDEC_ATMEL;
10610                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10611                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10612
10613                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10614                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10615                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10616                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10617                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10618                         break;
10619                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10620                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10621                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10622                         break;
10623                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10624                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10625                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10626                         break;
10627                 }
10628                 break;
10629         case FLASH_5752VENDOR_ST_M45PE10:
10630         case FLASH_5752VENDOR_ST_M45PE20:
10631         case FLASH_5752VENDOR_ST_M45PE40:
10632                 tp->nvram_jedecnum = JEDEC_ST;
10633                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10634                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10635
10636                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10637                 case FLASH_5752VENDOR_ST_M45PE10:
10638                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10639                         break;
10640                 case FLASH_5752VENDOR_ST_M45PE20:
10641                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10642                         break;
10643                 case FLASH_5752VENDOR_ST_M45PE40:
10644                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10645                         break;
10646                 }
10647                 break;
10648         default:
10649                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10650                 return;
10651         }
10652
10653         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10654         case FLASH_5752PAGE_SIZE_256:
10655                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10656                 tp->nvram_pagesize = 256;
10657                 break;
10658         case FLASH_5752PAGE_SIZE_512:
10659                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10660                 tp->nvram_pagesize = 512;
10661                 break;
10662         case FLASH_5752PAGE_SIZE_1K:
10663                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10664                 tp->nvram_pagesize = 1024;
10665                 break;
10666         case FLASH_5752PAGE_SIZE_2K:
10667                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10668                 tp->nvram_pagesize = 2048;
10669                 break;
10670         case FLASH_5752PAGE_SIZE_4K:
10671                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10672                 tp->nvram_pagesize = 4096;
10673                 break;
10674         case FLASH_5752PAGE_SIZE_264:
10675                 tp->nvram_pagesize = 264;
10676                 break;
10677         case FLASH_5752PAGE_SIZE_528:
10678                 tp->nvram_pagesize = 528;
10679                 break;
10680         }
10681 }
10682
10683 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10684 static void __devinit tg3_nvram_init(struct tg3 *tp)
10685 {
10686         tw32_f(GRC_EEPROM_ADDR,
10687              (EEPROM_ADDR_FSM_RESET |
10688               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10689                EEPROM_ADDR_CLKPERD_SHIFT)));
10690
10691         msleep(1);
10692
10693         /* Enable seeprom accesses. */
10694         tw32_f(GRC_LOCAL_CTRL,
10695              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10696         udelay(100);
10697
10698         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10699             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10700                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10701
10702                 if (tg3_nvram_lock(tp)) {
10703                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10704                                "tg3_nvram_init failed.\n", tp->dev->name);
10705                         return;
10706                 }
10707                 tg3_enable_nvram_access(tp);
10708
10709                 tp->nvram_size = 0;
10710
10711                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10712                         tg3_get_5752_nvram_info(tp);
10713                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10714                         tg3_get_5755_nvram_info(tp);
10715                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10716                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10717                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10718                         tg3_get_5787_nvram_info(tp);
10719                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10720                         tg3_get_5761_nvram_info(tp);
10721                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10722                         tg3_get_5906_nvram_info(tp);
10723                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10724                         tg3_get_57780_nvram_info(tp);
10725                 else
10726                         tg3_get_nvram_info(tp);
10727
10728                 if (tp->nvram_size == 0)
10729                         tg3_get_nvram_size(tp);
10730
10731                 tg3_disable_nvram_access(tp);
10732                 tg3_nvram_unlock(tp);
10733
10734         } else {
10735                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10736
10737                 tg3_get_eeprom_size(tp);
10738         }
10739 }
10740
10741 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10742                                     u32 offset, u32 len, u8 *buf)
10743 {
10744         int i, j, rc = 0;
10745         u32 val;
10746
10747         for (i = 0; i < len; i += 4) {
10748                 u32 addr;
10749                 __be32 data;
10750
10751                 addr = offset + i;
10752
10753                 memcpy(&data, buf + i, 4);
10754
10755                 /*
10756                  * The SEEPROM interface expects the data to always be opposite
10757                  * the native endian format.  We accomplish this by reversing
10758                  * all the operations that would have been performed on the
10759                  * data from a call to tg3_nvram_read_be32().
10760                  */
10761                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10762
10763                 val = tr32(GRC_EEPROM_ADDR);
10764                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10765
10766                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10767                         EEPROM_ADDR_READ);
10768                 tw32(GRC_EEPROM_ADDR, val |
10769                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10770                         (addr & EEPROM_ADDR_ADDR_MASK) |
10771                         EEPROM_ADDR_START |
10772                         EEPROM_ADDR_WRITE);
10773
10774                 for (j = 0; j < 1000; j++) {
10775                         val = tr32(GRC_EEPROM_ADDR);
10776
10777                         if (val & EEPROM_ADDR_COMPLETE)
10778                                 break;
10779                         msleep(1);
10780                 }
10781                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10782                         rc = -EBUSY;
10783                         break;
10784                 }
10785         }
10786
10787         return rc;
10788 }
10789
10790 /* offset and length are dword aligned */
10791 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10792                 u8 *buf)
10793 {
10794         int ret = 0;
10795         u32 pagesize = tp->nvram_pagesize;
10796         u32 pagemask = pagesize - 1;
10797         u32 nvram_cmd;
10798         u8 *tmp;
10799
10800         tmp = kmalloc(pagesize, GFP_KERNEL);
10801         if (tmp == NULL)
10802                 return -ENOMEM;
10803
10804         while (len) {
10805                 int j;
10806                 u32 phy_addr, page_off, size;
10807
10808                 phy_addr = offset & ~pagemask;
10809
10810                 for (j = 0; j < pagesize; j += 4) {
10811                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10812                                                   (__be32 *) (tmp + j));
10813                         if (ret)
10814                                 break;
10815                 }
10816                 if (ret)
10817                         break;
10818
10819                 page_off = offset & pagemask;
10820                 size = pagesize;
10821                 if (len < size)
10822                         size = len;
10823
10824                 len -= size;
10825
10826                 memcpy(tmp + page_off, buf, size);
10827
10828                 offset = offset + (pagesize - page_off);
10829
10830                 tg3_enable_nvram_access(tp);
10831
10832                 /*
10833                  * Before we can erase the flash page, we need
10834                  * to issue a special "write enable" command.
10835                  */
10836                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10837
10838                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10839                         break;
10840
10841                 /* Erase the target page */
10842                 tw32(NVRAM_ADDR, phy_addr);
10843
10844                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10845                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10846
10847                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10848                         break;
10849
10850                 /* Issue another write enable to start the write. */
10851                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10852
10853                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10854                         break;
10855
10856                 for (j = 0; j < pagesize; j += 4) {
10857                         __be32 data;
10858
10859                         data = *((__be32 *) (tmp + j));
10860
10861                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10862
10863                         tw32(NVRAM_ADDR, phy_addr + j);
10864
10865                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10866                                 NVRAM_CMD_WR;
10867
10868                         if (j == 0)
10869                                 nvram_cmd |= NVRAM_CMD_FIRST;
10870                         else if (j == (pagesize - 4))
10871                                 nvram_cmd |= NVRAM_CMD_LAST;
10872
10873                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10874                                 break;
10875                 }
10876                 if (ret)
10877                         break;
10878         }
10879
10880         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10881         tg3_nvram_exec_cmd(tp, nvram_cmd);
10882
10883         kfree(tmp);
10884
10885         return ret;
10886 }
10887
10888 /* offset and length are dword aligned */
10889 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10890                 u8 *buf)
10891 {
10892         int i, ret = 0;
10893
10894         for (i = 0; i < len; i += 4, offset += 4) {
10895                 u32 page_off, phy_addr, nvram_cmd;
10896                 __be32 data;
10897
10898                 memcpy(&data, buf + i, 4);
10899                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10900
10901                 page_off = offset % tp->nvram_pagesize;
10902
10903                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10904
10905                 tw32(NVRAM_ADDR, phy_addr);
10906
10907                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10908
10909                 if ((page_off == 0) || (i == 0))
10910                         nvram_cmd |= NVRAM_CMD_FIRST;
10911                 if (page_off == (tp->nvram_pagesize - 4))
10912                         nvram_cmd |= NVRAM_CMD_LAST;
10913
10914                 if (i == (len - 4))
10915                         nvram_cmd |= NVRAM_CMD_LAST;
10916
10917                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10918                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10919                     (tp->nvram_jedecnum == JEDEC_ST) &&
10920                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10921
10922                         if ((ret = tg3_nvram_exec_cmd(tp,
10923                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10924                                 NVRAM_CMD_DONE)))
10925
10926                                 break;
10927                 }
10928                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10929                         /* We always do complete word writes to eeprom. */
10930                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10931                 }
10932
10933                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10934                         break;
10935         }
10936         return ret;
10937 }
10938
10939 /* offset and length are dword aligned */
10940 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10941 {
10942         int ret;
10943
10944         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10945                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10946                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10947                 udelay(40);
10948         }
10949
10950         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10951                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10952         }
10953         else {
10954                 u32 grc_mode;
10955
10956                 ret = tg3_nvram_lock(tp);
10957                 if (ret)
10958                         return ret;
10959
10960                 tg3_enable_nvram_access(tp);
10961                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10962                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10963                         tw32(NVRAM_WRITE1, 0x406);
10964
10965                 grc_mode = tr32(GRC_MODE);
10966                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10967
10968                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10969                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10970
10971                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10972                                 buf);
10973                 }
10974                 else {
10975                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10976                                 buf);
10977                 }
10978
10979                 grc_mode = tr32(GRC_MODE);
10980                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10981
10982                 tg3_disable_nvram_access(tp);
10983                 tg3_nvram_unlock(tp);
10984         }
10985
10986         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10987                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10988                 udelay(40);
10989         }
10990
10991         return ret;
10992 }
10993
10994 struct subsys_tbl_ent {
10995         u16 subsys_vendor, subsys_devid;
10996         u32 phy_id;
10997 };
10998
10999 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11000         /* Broadcom boards. */
11001         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11002         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11003         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11004         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11005         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11006         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11007         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11008         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11009         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11010         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11011         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11012
11013         /* 3com boards. */
11014         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11015         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11016         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11017         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11018         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11019
11020         /* DELL boards. */
11021         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11022         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11023         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11024         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11025
11026         /* Compaq boards. */
11027         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11028         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11029         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11030         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11031         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11032
11033         /* IBM boards. */
11034         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11035 };
11036
11037 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11038 {
11039         int i;
11040
11041         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11042                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11043                      tp->pdev->subsystem_vendor) &&
11044                     (subsys_id_to_phy_id[i].subsys_devid ==
11045                      tp->pdev->subsystem_device))
11046                         return &subsys_id_to_phy_id[i];
11047         }
11048         return NULL;
11049 }
11050
11051 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11052 {
11053         u32 val;
11054         u16 pmcsr;
11055
11056         /* On some early chips the SRAM cannot be accessed in D3hot state,
11057          * so need make sure we're in D0.
11058          */
11059         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11060         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11061         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11062         msleep(1);
11063
11064         /* Make sure register accesses (indirect or otherwise)
11065          * will function correctly.
11066          */
11067         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11068                                tp->misc_host_ctrl);
11069
11070         /* The memory arbiter has to be enabled in order for SRAM accesses
11071          * to succeed.  Normally on powerup the tg3 chip firmware will make
11072          * sure it is enabled, but other entities such as system netboot
11073          * code might disable it.
11074          */
11075         val = tr32(MEMARB_MODE);
11076         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11077
11078         tp->phy_id = PHY_ID_INVALID;
11079         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11080
11081         /* Assume an onboard device and WOL capable by default.  */
11082         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11083
11084         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11085                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11086                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11087                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11088                 }
11089                 val = tr32(VCPU_CFGSHDW);
11090                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11091                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11092                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11093                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11094                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11095                 goto done;
11096         }
11097
11098         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11099         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11100                 u32 nic_cfg, led_cfg;
11101                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11102                 int eeprom_phy_serdes = 0;
11103
11104                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11105                 tp->nic_sram_data_cfg = nic_cfg;
11106
11107                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11108                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11109                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11110                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11111                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11112                     (ver > 0) && (ver < 0x100))
11113                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11114
11115                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11116                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11117
11118                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11119                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11120                         eeprom_phy_serdes = 1;
11121
11122                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11123                 if (nic_phy_id != 0) {
11124                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11125                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11126
11127                         eeprom_phy_id  = (id1 >> 16) << 10;
11128                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11129                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11130                 } else
11131                         eeprom_phy_id = 0;
11132
11133                 tp->phy_id = eeprom_phy_id;
11134                 if (eeprom_phy_serdes) {
11135                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11136                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11137                         else
11138                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11139                 }
11140
11141                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11142                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11143                                     SHASTA_EXT_LED_MODE_MASK);
11144                 else
11145                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11146
11147                 switch (led_cfg) {
11148                 default:
11149                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11150                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11151                         break;
11152
11153                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11154                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11155                         break;
11156
11157                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11158                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11159
11160                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11161                          * read on some older 5700/5701 bootcode.
11162                          */
11163                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11164                             ASIC_REV_5700 ||
11165                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11166                             ASIC_REV_5701)
11167                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11168
11169                         break;
11170
11171                 case SHASTA_EXT_LED_SHARED:
11172                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11173                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11174                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11175                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11176                                                  LED_CTRL_MODE_PHY_2);
11177                         break;
11178
11179                 case SHASTA_EXT_LED_MAC:
11180                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11181                         break;
11182
11183                 case SHASTA_EXT_LED_COMBO:
11184                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11185                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11186                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11187                                                  LED_CTRL_MODE_PHY_2);
11188                         break;
11189
11190                 }
11191
11192                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11193                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11194                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11195                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11196
11197                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11198                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11199
11200                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11201                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11202                         if ((tp->pdev->subsystem_vendor ==
11203                              PCI_VENDOR_ID_ARIMA) &&
11204                             (tp->pdev->subsystem_device == 0x205a ||
11205                              tp->pdev->subsystem_device == 0x2063))
11206                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11207                 } else {
11208                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11209                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11210                 }
11211
11212                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11213                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11214                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11215                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11216                 }
11217
11218                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11219                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11220                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11221
11222                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11223                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11224                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11225
11226                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11227                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11228                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11229
11230                 if (cfg2 & (1 << 17))
11231                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11232
11233                 /* serdes signal pre-emphasis in register 0x590 set by */
11234                 /* bootcode if bit 18 is set */
11235                 if (cfg2 & (1 << 18))
11236                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11237
11238                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11239                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11240                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11241                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11242
11243                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11244                         u32 cfg3;
11245
11246                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11247                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11248                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11249                 }
11250
11251                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11252                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11253                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11254                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11255                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11256                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11257         }
11258 done:
11259         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11260         device_set_wakeup_enable(&tp->pdev->dev,
11261                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11262 }
11263
11264 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11265 {
11266         int i;
11267         u32 val;
11268
11269         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11270         tw32(OTP_CTRL, cmd);
11271
11272         /* Wait for up to 1 ms for command to execute. */
11273         for (i = 0; i < 100; i++) {
11274                 val = tr32(OTP_STATUS);
11275                 if (val & OTP_STATUS_CMD_DONE)
11276                         break;
11277                 udelay(10);
11278         }
11279
11280         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11281 }
11282
11283 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11284  * configuration is a 32-bit value that straddles the alignment boundary.
11285  * We do two 32-bit reads and then shift and merge the results.
11286  */
11287 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11288 {
11289         u32 bhalf_otp, thalf_otp;
11290
11291         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11292
11293         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11294                 return 0;
11295
11296         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11297
11298         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11299                 return 0;
11300
11301         thalf_otp = tr32(OTP_READ_DATA);
11302
11303         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11304
11305         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11306                 return 0;
11307
11308         bhalf_otp = tr32(OTP_READ_DATA);
11309
11310         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11311 }
11312
11313 static int __devinit tg3_phy_probe(struct tg3 *tp)
11314 {
11315         u32 hw_phy_id_1, hw_phy_id_2;
11316         u32 hw_phy_id, hw_phy_id_masked;
11317         int err;
11318
11319         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11320                 return tg3_phy_init(tp);
11321
11322         /* Reading the PHY ID register can conflict with ASF
11323          * firmware access to the PHY hardware.
11324          */
11325         err = 0;
11326         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11327             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11328                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11329         } else {
11330                 /* Now read the physical PHY_ID from the chip and verify
11331                  * that it is sane.  If it doesn't look good, we fall back
11332                  * to either the hard-coded table based PHY_ID and failing
11333                  * that the value found in the eeprom area.
11334                  */
11335                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11336                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11337
11338                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11339                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11340                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11341
11342                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11343         }
11344
11345         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11346                 tp->phy_id = hw_phy_id;
11347                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11348                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11349                 else
11350                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11351         } else {
11352                 if (tp->phy_id != PHY_ID_INVALID) {
11353                         /* Do nothing, phy ID already set up in
11354                          * tg3_get_eeprom_hw_cfg().
11355                          */
11356                 } else {
11357                         struct subsys_tbl_ent *p;
11358
11359                         /* No eeprom signature?  Try the hardcoded
11360                          * subsys device table.
11361                          */
11362                         p = lookup_by_subsys(tp);
11363                         if (!p)
11364                                 return -ENODEV;
11365
11366                         tp->phy_id = p->phy_id;
11367                         if (!tp->phy_id ||
11368                             tp->phy_id == PHY_ID_BCM8002)
11369                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11370                 }
11371         }
11372
11373         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11374             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11375             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11376                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11377
11378                 tg3_readphy(tp, MII_BMSR, &bmsr);
11379                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11380                     (bmsr & BMSR_LSTATUS))
11381                         goto skip_phy_reset;
11382
11383                 err = tg3_phy_reset(tp);
11384                 if (err)
11385                         return err;
11386
11387                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11388                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11389                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11390                 tg3_ctrl = 0;
11391                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11392                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11393                                     MII_TG3_CTRL_ADV_1000_FULL);
11394                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11395                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11396                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11397                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11398                 }
11399
11400                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11401                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11402                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11403                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11404                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11405
11406                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11407                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11408
11409                         tg3_writephy(tp, MII_BMCR,
11410                                      BMCR_ANENABLE | BMCR_ANRESTART);
11411                 }
11412                 tg3_phy_set_wirespeed(tp);
11413
11414                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11415                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11416                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11417         }
11418
11419 skip_phy_reset:
11420         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11421                 err = tg3_init_5401phy_dsp(tp);
11422                 if (err)
11423                         return err;
11424         }
11425
11426         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11427                 err = tg3_init_5401phy_dsp(tp);
11428         }
11429
11430         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11431                 tp->link_config.advertising =
11432                         (ADVERTISED_1000baseT_Half |
11433                          ADVERTISED_1000baseT_Full |
11434                          ADVERTISED_Autoneg |
11435                          ADVERTISED_FIBRE);
11436         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11437                 tp->link_config.advertising &=
11438                         ~(ADVERTISED_1000baseT_Half |
11439                           ADVERTISED_1000baseT_Full);
11440
11441         return err;
11442 }
11443
11444 static void __devinit tg3_read_partno(struct tg3 *tp)
11445 {
11446         unsigned char vpd_data[256];   /* in little-endian format */
11447         unsigned int i;
11448         u32 magic;
11449
11450         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11451             tg3_nvram_read(tp, 0x0, &magic))
11452                 goto out_not_found;
11453
11454         if (magic == TG3_EEPROM_MAGIC) {
11455                 for (i = 0; i < 256; i += 4) {
11456                         u32 tmp;
11457
11458                         /* The data is in little-endian format in NVRAM.
11459                          * Use the big-endian read routines to preserve
11460                          * the byte order as it exists in NVRAM.
11461                          */
11462                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11463                                 goto out_not_found;
11464
11465                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11466                 }
11467         } else {
11468                 int vpd_cap;
11469
11470                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11471                 for (i = 0; i < 256; i += 4) {
11472                         u32 tmp, j = 0;
11473                         __le32 v;
11474                         u16 tmp16;
11475
11476                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11477                                               i);
11478                         while (j++ < 100) {
11479                                 pci_read_config_word(tp->pdev, vpd_cap +
11480                                                      PCI_VPD_ADDR, &tmp16);
11481                                 if (tmp16 & 0x8000)
11482                                         break;
11483                                 msleep(1);
11484                         }
11485                         if (!(tmp16 & 0x8000))
11486                                 goto out_not_found;
11487
11488                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11489                                               &tmp);
11490                         v = cpu_to_le32(tmp);
11491                         memcpy(&vpd_data[i], &v, sizeof(v));
11492                 }
11493         }
11494
11495         /* Now parse and find the part number. */
11496         for (i = 0; i < 254; ) {
11497                 unsigned char val = vpd_data[i];
11498                 unsigned int block_end;
11499
11500                 if (val == 0x82 || val == 0x91) {
11501                         i = (i + 3 +
11502                              (vpd_data[i + 1] +
11503                               (vpd_data[i + 2] << 8)));
11504                         continue;
11505                 }
11506
11507                 if (val != 0x90)
11508                         goto out_not_found;
11509
11510                 block_end = (i + 3 +
11511                              (vpd_data[i + 1] +
11512                               (vpd_data[i + 2] << 8)));
11513                 i += 3;
11514
11515                 if (block_end > 256)
11516                         goto out_not_found;
11517
11518                 while (i < (block_end - 2)) {
11519                         if (vpd_data[i + 0] == 'P' &&
11520                             vpd_data[i + 1] == 'N') {
11521                                 int partno_len = vpd_data[i + 2];
11522
11523                                 i += 3;
11524                                 if (partno_len > 24 || (partno_len + i) > 256)
11525                                         goto out_not_found;
11526
11527                                 memcpy(tp->board_part_number,
11528                                        &vpd_data[i], partno_len);
11529
11530                                 /* Success. */
11531                                 return;
11532                         }
11533                         i += 3 + vpd_data[i + 2];
11534                 }
11535
11536                 /* Part number not found. */
11537                 goto out_not_found;
11538         }
11539
11540 out_not_found:
11541         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11542                 strcpy(tp->board_part_number, "BCM95906");
11543         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11544                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11545                 strcpy(tp->board_part_number, "BCM57780");
11546         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11547                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11548                 strcpy(tp->board_part_number, "BCM57760");
11549         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11550                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11551                 strcpy(tp->board_part_number, "BCM57790");
11552         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11553                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11554                 strcpy(tp->board_part_number, "BCM57788");
11555         else
11556                 strcpy(tp->board_part_number, "none");
11557 }
11558
11559 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11560 {
11561         u32 val;
11562
11563         if (tg3_nvram_read(tp, offset, &val) ||
11564             (val & 0xfc000000) != 0x0c000000 ||
11565             tg3_nvram_read(tp, offset + 4, &val) ||
11566             val != 0)
11567                 return 0;
11568
11569         return 1;
11570 }
11571
11572 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11573 {
11574         u32 val, offset, start, ver_offset;
11575         int i;
11576         bool newver = false;
11577
11578         if (tg3_nvram_read(tp, 0xc, &offset) ||
11579             tg3_nvram_read(tp, 0x4, &start))
11580                 return;
11581
11582         offset = tg3_nvram_logical_addr(tp, offset);
11583
11584         if (tg3_nvram_read(tp, offset, &val))
11585                 return;
11586
11587         if ((val & 0xfc000000) == 0x0c000000) {
11588                 if (tg3_nvram_read(tp, offset + 4, &val))
11589                         return;
11590
11591                 if (val == 0)
11592                         newver = true;
11593         }
11594
11595         if (newver) {
11596                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11597                         return;
11598
11599                 offset = offset + ver_offset - start;
11600                 for (i = 0; i < 16; i += 4) {
11601                         __be32 v;
11602                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11603                                 return;
11604
11605                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11606                 }
11607         } else {
11608                 u32 major, minor;
11609
11610                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11611                         return;
11612
11613                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11614                         TG3_NVM_BCVER_MAJSFT;
11615                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11616                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11617         }
11618 }
11619
11620 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11621 {
11622         u32 val, major, minor;
11623
11624         /* Use native endian representation */
11625         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11626                 return;
11627
11628         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11629                 TG3_NVM_HWSB_CFG1_MAJSFT;
11630         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11631                 TG3_NVM_HWSB_CFG1_MINSFT;
11632
11633         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11634 }
11635
11636 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11637 {
11638         u32 offset, major, minor, build;
11639
11640         tp->fw_ver[0] = 's';
11641         tp->fw_ver[1] = 'b';
11642         tp->fw_ver[2] = '\0';
11643
11644         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11645                 return;
11646
11647         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11648         case TG3_EEPROM_SB_REVISION_0:
11649                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11650                 break;
11651         case TG3_EEPROM_SB_REVISION_2:
11652                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11653                 break;
11654         case TG3_EEPROM_SB_REVISION_3:
11655                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11656                 break;
11657         default:
11658                 return;
11659         }
11660
11661         if (tg3_nvram_read(tp, offset, &val))
11662                 return;
11663
11664         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11665                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11666         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11667                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11668         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11669
11670         if (minor > 99 || build > 26)
11671                 return;
11672
11673         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11674
11675         if (build > 0) {
11676                 tp->fw_ver[8] = 'a' + build - 1;
11677                 tp->fw_ver[9] = '\0';
11678         }
11679 }
11680
11681 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11682 {
11683         u32 val, offset, start;
11684         int i, vlen;
11685
11686         for (offset = TG3_NVM_DIR_START;
11687              offset < TG3_NVM_DIR_END;
11688              offset += TG3_NVM_DIRENT_SIZE) {
11689                 if (tg3_nvram_read(tp, offset, &val))
11690                         return;
11691
11692                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11693                         break;
11694         }
11695
11696         if (offset == TG3_NVM_DIR_END)
11697                 return;
11698
11699         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11700                 start = 0x08000000;
11701         else if (tg3_nvram_read(tp, offset - 4, &start))
11702                 return;
11703
11704         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11705             !tg3_fw_img_is_valid(tp, offset) ||
11706             tg3_nvram_read(tp, offset + 8, &val))
11707                 return;
11708
11709         offset += val - start;
11710
11711         vlen = strlen(tp->fw_ver);
11712
11713         tp->fw_ver[vlen++] = ',';
11714         tp->fw_ver[vlen++] = ' ';
11715
11716         for (i = 0; i < 4; i++) {
11717                 __be32 v;
11718                 if (tg3_nvram_read_be32(tp, offset, &v))
11719                         return;
11720
11721                 offset += sizeof(v);
11722
11723                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11724                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11725                         break;
11726                 }
11727
11728                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11729                 vlen += sizeof(v);
11730         }
11731 }
11732
11733 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11734 {
11735         int vlen;
11736         u32 apedata;
11737
11738         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11739             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11740                 return;
11741
11742         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11743         if (apedata != APE_SEG_SIG_MAGIC)
11744                 return;
11745
11746         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11747         if (!(apedata & APE_FW_STATUS_READY))
11748                 return;
11749
11750         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11751
11752         vlen = strlen(tp->fw_ver);
11753
11754         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11755                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11756                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11757                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11758                  (apedata & APE_FW_VERSION_BLDMSK));
11759 }
11760
11761 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11762 {
11763         u32 val;
11764
11765         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11766                 tp->fw_ver[0] = 's';
11767                 tp->fw_ver[1] = 'b';
11768                 tp->fw_ver[2] = '\0';
11769
11770                 return;
11771         }
11772
11773         if (tg3_nvram_read(tp, 0, &val))
11774                 return;
11775
11776         if (val == TG3_EEPROM_MAGIC)
11777                 tg3_read_bc_ver(tp);
11778         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11779                 tg3_read_sb_ver(tp, val);
11780         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11781                 tg3_read_hwsb_ver(tp);
11782         else
11783                 return;
11784
11785         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11786              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11787                 return;
11788
11789         tg3_read_mgmtfw_ver(tp);
11790
11791         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11792 }
11793
11794 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11795
11796 static int __devinit tg3_get_invariants(struct tg3 *tp)
11797 {
11798         static struct pci_device_id write_reorder_chipsets[] = {
11799                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11800                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11801                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11802                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11803                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11804                              PCI_DEVICE_ID_VIA_8385_0) },
11805                 { },
11806         };
11807         u32 misc_ctrl_reg;
11808         u32 pci_state_reg, grc_misc_cfg;
11809         u32 val;
11810         u16 pci_cmd;
11811         int err;
11812
11813         /* Force memory write invalidate off.  If we leave it on,
11814          * then on 5700_BX chips we have to enable a workaround.
11815          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11816          * to match the cacheline size.  The Broadcom driver have this
11817          * workaround but turns MWI off all the times so never uses
11818          * it.  This seems to suggest that the workaround is insufficient.
11819          */
11820         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11821         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11822         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11823
11824         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11825          * has the register indirect write enable bit set before
11826          * we try to access any of the MMIO registers.  It is also
11827          * critical that the PCI-X hw workaround situation is decided
11828          * before that as well.
11829          */
11830         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11831                               &misc_ctrl_reg);
11832
11833         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11834                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11835         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11836                 u32 prod_id_asic_rev;
11837
11838                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11839                                       &prod_id_asic_rev);
11840                 tp->pci_chip_rev_id = prod_id_asic_rev;
11841         }
11842
11843         /* Wrong chip ID in 5752 A0. This code can be removed later
11844          * as A0 is not in production.
11845          */
11846         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11847                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11848
11849         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11850          * we need to disable memory and use config. cycles
11851          * only to access all registers. The 5702/03 chips
11852          * can mistakenly decode the special cycles from the
11853          * ICH chipsets as memory write cycles, causing corruption
11854          * of register and memory space. Only certain ICH bridges
11855          * will drive special cycles with non-zero data during the
11856          * address phase which can fall within the 5703's address
11857          * range. This is not an ICH bug as the PCI spec allows
11858          * non-zero address during special cycles. However, only
11859          * these ICH bridges are known to drive non-zero addresses
11860          * during special cycles.
11861          *
11862          * Since special cycles do not cross PCI bridges, we only
11863          * enable this workaround if the 5703 is on the secondary
11864          * bus of these ICH bridges.
11865          */
11866         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11867             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11868                 static struct tg3_dev_id {
11869                         u32     vendor;
11870                         u32     device;
11871                         u32     rev;
11872                 } ich_chipsets[] = {
11873                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11874                           PCI_ANY_ID },
11875                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11876                           PCI_ANY_ID },
11877                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11878                           0xa },
11879                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11880                           PCI_ANY_ID },
11881                         { },
11882                 };
11883                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11884                 struct pci_dev *bridge = NULL;
11885
11886                 while (pci_id->vendor != 0) {
11887                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11888                                                 bridge);
11889                         if (!bridge) {
11890                                 pci_id++;
11891                                 continue;
11892                         }
11893                         if (pci_id->rev != PCI_ANY_ID) {
11894                                 if (bridge->revision > pci_id->rev)
11895                                         continue;
11896                         }
11897                         if (bridge->subordinate &&
11898                             (bridge->subordinate->number ==
11899                              tp->pdev->bus->number)) {
11900
11901                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11902                                 pci_dev_put(bridge);
11903                                 break;
11904                         }
11905                 }
11906         }
11907
11908         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11909                 static struct tg3_dev_id {
11910                         u32     vendor;
11911                         u32     device;
11912                 } bridge_chipsets[] = {
11913                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11914                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11915                         { },
11916                 };
11917                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11918                 struct pci_dev *bridge = NULL;
11919
11920                 while (pci_id->vendor != 0) {
11921                         bridge = pci_get_device(pci_id->vendor,
11922                                                 pci_id->device,
11923                                                 bridge);
11924                         if (!bridge) {
11925                                 pci_id++;
11926                                 continue;
11927                         }
11928                         if (bridge->subordinate &&
11929                             (bridge->subordinate->number <=
11930                              tp->pdev->bus->number) &&
11931                             (bridge->subordinate->subordinate >=
11932                              tp->pdev->bus->number)) {
11933                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11934                                 pci_dev_put(bridge);
11935                                 break;
11936                         }
11937                 }
11938         }
11939
11940         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11941          * DMA addresses > 40-bit. This bridge may have other additional
11942          * 57xx devices behind it in some 4-port NIC designs for example.
11943          * Any tg3 device found behind the bridge will also need the 40-bit
11944          * DMA workaround.
11945          */
11946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11947             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11948                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11949                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11950                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11951         }
11952         else {
11953                 struct pci_dev *bridge = NULL;
11954
11955                 do {
11956                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11957                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11958                                                 bridge);
11959                         if (bridge && bridge->subordinate &&
11960                             (bridge->subordinate->number <=
11961                              tp->pdev->bus->number) &&
11962                             (bridge->subordinate->subordinate >=
11963                              tp->pdev->bus->number)) {
11964                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11965                                 pci_dev_put(bridge);
11966                                 break;
11967                         }
11968                 } while (bridge);
11969         }
11970
11971         /* Initialize misc host control in PCI block. */
11972         tp->misc_host_ctrl |= (misc_ctrl_reg &
11973                                MISC_HOST_CTRL_CHIPREV);
11974         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11975                                tp->misc_host_ctrl);
11976
11977         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11978             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11979                 tp->pdev_peer = tg3_find_peer(tp);
11980
11981         /* Intentionally exclude ASIC_REV_5906 */
11982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11983             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11987             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11988                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11989
11990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11992             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11993             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11994             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11995                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11996
11997         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11998             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11999                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12000
12001         /* 5700 B0 chips do not support checksumming correctly due
12002          * to hardware bugs.
12003          */
12004         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12005                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12006         else {
12007                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12008                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12009                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12010                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12011         }
12012
12013         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12014                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12015                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12016                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12017                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12018                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12019                      tp->pdev_peer == tp->pdev))
12020                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12021
12022                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12023                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12024                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12025                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12026                 } else {
12027                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12028                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12029                                 ASIC_REV_5750 &&
12030                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12031                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12032                 }
12033         }
12034
12035         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12036              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12037                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12038
12039         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12040                               &pci_state_reg);
12041
12042         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12043         if (tp->pcie_cap != 0) {
12044                 u16 lnkctl;
12045
12046                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12047
12048                 pcie_set_readrq(tp->pdev, 4096);
12049
12050                 pci_read_config_word(tp->pdev,
12051                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12052                                      &lnkctl);
12053                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12054                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12055                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12056                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12057                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12058                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12059                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12060                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12061                 }
12062         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12063                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12064         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12065                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12066                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12067                 if (!tp->pcix_cap) {
12068                         printk(KERN_ERR PFX "Cannot find PCI-X "
12069                                             "capability, aborting.\n");
12070                         return -EIO;
12071                 }
12072
12073                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12074                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12075         }
12076
12077         /* If we have an AMD 762 or VIA K8T800 chipset, write
12078          * reordering to the mailbox registers done by the host
12079          * controller can cause major troubles.  We read back from
12080          * every mailbox register write to force the writes to be
12081          * posted to the chip in order.
12082          */
12083         if (pci_dev_present(write_reorder_chipsets) &&
12084             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12085                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12086
12087         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12088                              &tp->pci_cacheline_sz);
12089         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12090                              &tp->pci_lat_timer);
12091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12092             tp->pci_lat_timer < 64) {
12093                 tp->pci_lat_timer = 64;
12094                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12095                                       tp->pci_lat_timer);
12096         }
12097
12098         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12099                 /* 5700 BX chips need to have their TX producer index
12100                  * mailboxes written twice to workaround a bug.
12101                  */
12102                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12103
12104                 /* If we are in PCI-X mode, enable register write workaround.
12105                  *
12106                  * The workaround is to use indirect register accesses
12107                  * for all chip writes not to mailbox registers.
12108                  */
12109                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12110                         u32 pm_reg;
12111
12112                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12113
12114                         /* The chip can have it's power management PCI config
12115                          * space registers clobbered due to this bug.
12116                          * So explicitly force the chip into D0 here.
12117                          */
12118                         pci_read_config_dword(tp->pdev,
12119                                               tp->pm_cap + PCI_PM_CTRL,
12120                                               &pm_reg);
12121                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12122                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12123                         pci_write_config_dword(tp->pdev,
12124                                                tp->pm_cap + PCI_PM_CTRL,
12125                                                pm_reg);
12126
12127                         /* Also, force SERR#/PERR# in PCI command. */
12128                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12129                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12130                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12131                 }
12132         }
12133
12134         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12135                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12136         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12137                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12138
12139         /* Chip-specific fixup from Broadcom driver */
12140         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12141             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12142                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12143                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12144         }
12145
12146         /* Default fast path register access methods */
12147         tp->read32 = tg3_read32;
12148         tp->write32 = tg3_write32;
12149         tp->read32_mbox = tg3_read32;
12150         tp->write32_mbox = tg3_write32;
12151         tp->write32_tx_mbox = tg3_write32;
12152         tp->write32_rx_mbox = tg3_write32;
12153
12154         /* Various workaround register access methods */
12155         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12156                 tp->write32 = tg3_write_indirect_reg32;
12157         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12158                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12159                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12160                 /*
12161                  * Back to back register writes can cause problems on these
12162                  * chips, the workaround is to read back all reg writes
12163                  * except those to mailbox regs.
12164                  *
12165                  * See tg3_write_indirect_reg32().
12166                  */
12167                 tp->write32 = tg3_write_flush_reg32;
12168         }
12169
12170
12171         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12172             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12173                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12174                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12175                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12176         }
12177
12178         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12179                 tp->read32 = tg3_read_indirect_reg32;
12180                 tp->write32 = tg3_write_indirect_reg32;
12181                 tp->read32_mbox = tg3_read_indirect_mbox;
12182                 tp->write32_mbox = tg3_write_indirect_mbox;
12183                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12184                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12185
12186                 iounmap(tp->regs);
12187                 tp->regs = NULL;
12188
12189                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12190                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12191                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12192         }
12193         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12194                 tp->read32_mbox = tg3_read32_mbox_5906;
12195                 tp->write32_mbox = tg3_write32_mbox_5906;
12196                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12197                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12198         }
12199
12200         if (tp->write32 == tg3_write_indirect_reg32 ||
12201             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12202              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12203               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12204                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12205
12206         /* Get eeprom hw config before calling tg3_set_power_state().
12207          * In particular, the TG3_FLG2_IS_NIC flag must be
12208          * determined before calling tg3_set_power_state() so that
12209          * we know whether or not to switch out of Vaux power.
12210          * When the flag is set, it means that GPIO1 is used for eeprom
12211          * write protect and also implies that it is a LOM where GPIOs
12212          * are not used to switch power.
12213          */
12214         tg3_get_eeprom_hw_cfg(tp);
12215
12216         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12217                 /* Allow reads and writes to the
12218                  * APE register and memory space.
12219                  */
12220                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12221                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12222                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12223                                        pci_state_reg);
12224         }
12225
12226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12227             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12228             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12229             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12230                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12231
12232         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12233          * GPIO1 driven high will bring 5700's external PHY out of reset.
12234          * It is also used as eeprom write protect on LOMs.
12235          */
12236         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12237         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12238             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12239                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12240                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12241         /* Unused GPIO3 must be driven as output on 5752 because there
12242          * are no pull-up resistors on unused GPIO pins.
12243          */
12244         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12245                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12246
12247         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12248             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12249                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12250
12251         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12252             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12253                 /* Turn off the debug UART. */
12254                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12255                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12256                         /* Keep VMain power. */
12257                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12258                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12259         }
12260
12261         /* Force the chip into D0. */
12262         err = tg3_set_power_state(tp, PCI_D0);
12263         if (err) {
12264                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12265                        pci_name(tp->pdev));
12266                 return err;
12267         }
12268
12269         /* Derive initial jumbo mode from MTU assigned in
12270          * ether_setup() via the alloc_etherdev() call
12271          */
12272         if (tp->dev->mtu > ETH_DATA_LEN &&
12273             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12274                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12275
12276         /* Determine WakeOnLan speed to use. */
12277         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12278             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12279             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12280             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12281                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12282         } else {
12283                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12284         }
12285
12286         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12287                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12288
12289         /* A few boards don't want Ethernet@WireSpeed phy feature */
12290         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12291             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12292              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12293              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12294             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12295             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12296                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12297
12298         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12299             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12300                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12301         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12302                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12303
12304         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12305             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12306             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12307             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12308                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12309                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12310                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12311                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12312                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12313                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12314                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12315                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12316                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12317                 } else
12318                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12319         }
12320
12321         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12322             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12323                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12324                 if (tp->phy_otp == 0)
12325                         tp->phy_otp = TG3_OTP_DEFAULT;
12326         }
12327
12328         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12329                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12330         else
12331                 tp->mi_mode = MAC_MI_MODE_BASE;
12332
12333         tp->coalesce_mode = 0;
12334         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12335             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12336                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12337
12338         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12339             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12340                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12341
12342         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12343              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12344             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12345                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12346
12347         err = tg3_mdio_init(tp);
12348         if (err)
12349                 return err;
12350
12351         /* Initialize data/descriptor byte/word swapping. */
12352         val = tr32(GRC_MODE);
12353         val &= GRC_MODE_HOST_STACKUP;
12354         tw32(GRC_MODE, val | tp->grc_mode);
12355
12356         tg3_switch_clocks(tp);
12357
12358         /* Clear this out for sanity. */
12359         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12360
12361         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12362                               &pci_state_reg);
12363         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12364             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12365                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12366
12367                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12368                     chiprevid == CHIPREV_ID_5701_B0 ||
12369                     chiprevid == CHIPREV_ID_5701_B2 ||
12370                     chiprevid == CHIPREV_ID_5701_B5) {
12371                         void __iomem *sram_base;
12372
12373                         /* Write some dummy words into the SRAM status block
12374                          * area, see if it reads back correctly.  If the return
12375                          * value is bad, force enable the PCIX workaround.
12376                          */
12377                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12378
12379                         writel(0x00000000, sram_base);
12380                         writel(0x00000000, sram_base + 4);
12381                         writel(0xffffffff, sram_base + 4);
12382                         if (readl(sram_base) != 0x00000000)
12383                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12384                 }
12385         }
12386
12387         udelay(50);
12388         tg3_nvram_init(tp);
12389
12390         grc_misc_cfg = tr32(GRC_MISC_CFG);
12391         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12392
12393         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12394             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12395              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12396                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12397
12398         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12399             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12400                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12401         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12402                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12403                                       HOSTCC_MODE_CLRTICK_TXBD);
12404
12405                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12406                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12407                                        tp->misc_host_ctrl);
12408         }
12409
12410         /* Preserve the APE MAC_MODE bits */
12411         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12412                 tp->mac_mode = tr32(MAC_MODE) |
12413                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12414         else
12415                 tp->mac_mode = TG3_DEF_MAC_MODE;
12416
12417         /* these are limited to 10/100 only */
12418         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12419              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12420             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12421              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12422              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12423               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12424               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12425             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12426              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12427               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12428               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12429             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12430             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12431                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12432
12433         err = tg3_phy_probe(tp);
12434         if (err) {
12435                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12436                        pci_name(tp->pdev), err);
12437                 /* ... but do not return immediately ... */
12438                 tg3_mdio_fini(tp);
12439         }
12440
12441         tg3_read_partno(tp);
12442         tg3_read_fw_ver(tp);
12443
12444         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12445                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12446         } else {
12447                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12448                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12449                 else
12450                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12451         }
12452
12453         /* 5700 {AX,BX} chips have a broken status block link
12454          * change bit implementation, so we must use the
12455          * status register in those cases.
12456          */
12457         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12458                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12459         else
12460                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12461
12462         /* The led_ctrl is set during tg3_phy_probe, here we might
12463          * have to force the link status polling mechanism based
12464          * upon subsystem IDs.
12465          */
12466         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12467             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12468             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12469                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12470                                   TG3_FLAG_USE_LINKCHG_REG);
12471         }
12472
12473         /* For all SERDES we poll the MAC status register. */
12474         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12475                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12476         else
12477                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12478
12479         tp->rx_offset = NET_IP_ALIGN;
12480         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12481             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12482                 tp->rx_offset = 0;
12483
12484         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12485
12486         /* Increment the rx prod index on the rx std ring by at most
12487          * 8 for these chips to workaround hw errata.
12488          */
12489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12490             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12491             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12492                 tp->rx_std_max_post = 8;
12493
12494         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12495                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12496                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12497
12498         return err;
12499 }
12500
12501 #ifdef CONFIG_SPARC
12502 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12503 {
12504         struct net_device *dev = tp->dev;
12505         struct pci_dev *pdev = tp->pdev;
12506         struct device_node *dp = pci_device_to_OF_node(pdev);
12507         const unsigned char *addr;
12508         int len;
12509
12510         addr = of_get_property(dp, "local-mac-address", &len);
12511         if (addr && len == 6) {
12512                 memcpy(dev->dev_addr, addr, 6);
12513                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12514                 return 0;
12515         }
12516         return -ENODEV;
12517 }
12518
12519 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12520 {
12521         struct net_device *dev = tp->dev;
12522
12523         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12524         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12525         return 0;
12526 }
12527 #endif
12528
12529 static int __devinit tg3_get_device_address(struct tg3 *tp)
12530 {
12531         struct net_device *dev = tp->dev;
12532         u32 hi, lo, mac_offset;
12533         int addr_ok = 0;
12534
12535 #ifdef CONFIG_SPARC
12536         if (!tg3_get_macaddr_sparc(tp))
12537                 return 0;
12538 #endif
12539
12540         mac_offset = 0x7c;
12541         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12542             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12543                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12544                         mac_offset = 0xcc;
12545                 if (tg3_nvram_lock(tp))
12546                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12547                 else
12548                         tg3_nvram_unlock(tp);
12549         }
12550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12551                 mac_offset = 0x10;
12552
12553         /* First try to get it from MAC address mailbox. */
12554         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12555         if ((hi >> 16) == 0x484b) {
12556                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12557                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12558
12559                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12560                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12561                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12562                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12563                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12564
12565                 /* Some old bootcode may report a 0 MAC address in SRAM */
12566                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12567         }
12568         if (!addr_ok) {
12569                 /* Next, try NVRAM. */
12570                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12571                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12572                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12573                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12574                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12575                 }
12576                 /* Finally just fetch it out of the MAC control regs. */
12577                 else {
12578                         hi = tr32(MAC_ADDR_0_HIGH);
12579                         lo = tr32(MAC_ADDR_0_LOW);
12580
12581                         dev->dev_addr[5] = lo & 0xff;
12582                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12583                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12584                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12585                         dev->dev_addr[1] = hi & 0xff;
12586                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12587                 }
12588         }
12589
12590         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12591 #ifdef CONFIG_SPARC
12592                 if (!tg3_get_default_macaddr_sparc(tp))
12593                         return 0;
12594 #endif
12595                 return -EINVAL;
12596         }
12597         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12598         return 0;
12599 }
12600
12601 #define BOUNDARY_SINGLE_CACHELINE       1
12602 #define BOUNDARY_MULTI_CACHELINE        2
12603
12604 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12605 {
12606         int cacheline_size;
12607         u8 byte;
12608         int goal;
12609
12610         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12611         if (byte == 0)
12612                 cacheline_size = 1024;
12613         else
12614                 cacheline_size = (int) byte * 4;
12615
12616         /* On 5703 and later chips, the boundary bits have no
12617          * effect.
12618          */
12619         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12620             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12621             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12622                 goto out;
12623
12624 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12625         goal = BOUNDARY_MULTI_CACHELINE;
12626 #else
12627 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12628         goal = BOUNDARY_SINGLE_CACHELINE;
12629 #else
12630         goal = 0;
12631 #endif
12632 #endif
12633
12634         if (!goal)
12635                 goto out;
12636
12637         /* PCI controllers on most RISC systems tend to disconnect
12638          * when a device tries to burst across a cache-line boundary.
12639          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12640          *
12641          * Unfortunately, for PCI-E there are only limited
12642          * write-side controls for this, and thus for reads
12643          * we will still get the disconnects.  We'll also waste
12644          * these PCI cycles for both read and write for chips
12645          * other than 5700 and 5701 which do not implement the
12646          * boundary bits.
12647          */
12648         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12649             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12650                 switch (cacheline_size) {
12651                 case 16:
12652                 case 32:
12653                 case 64:
12654                 case 128:
12655                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12656                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12657                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12658                         } else {
12659                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12660                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12661                         }
12662                         break;
12663
12664                 case 256:
12665                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12666                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12667                         break;
12668
12669                 default:
12670                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12671                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12672                         break;
12673                 }
12674         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12675                 switch (cacheline_size) {
12676                 case 16:
12677                 case 32:
12678                 case 64:
12679                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12680                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12681                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12682                                 break;
12683                         }
12684                         /* fallthrough */
12685                 case 128:
12686                 default:
12687                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12688                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12689                         break;
12690                 }
12691         } else {
12692                 switch (cacheline_size) {
12693                 case 16:
12694                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12695                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12696                                         DMA_RWCTRL_WRITE_BNDRY_16);
12697                                 break;
12698                         }
12699                         /* fallthrough */
12700                 case 32:
12701                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12702                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12703                                         DMA_RWCTRL_WRITE_BNDRY_32);
12704                                 break;
12705                         }
12706                         /* fallthrough */
12707                 case 64:
12708                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12709                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12710                                         DMA_RWCTRL_WRITE_BNDRY_64);
12711                                 break;
12712                         }
12713                         /* fallthrough */
12714                 case 128:
12715                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12716                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12717                                         DMA_RWCTRL_WRITE_BNDRY_128);
12718                                 break;
12719                         }
12720                         /* fallthrough */
12721                 case 256:
12722                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12723                                 DMA_RWCTRL_WRITE_BNDRY_256);
12724                         break;
12725                 case 512:
12726                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12727                                 DMA_RWCTRL_WRITE_BNDRY_512);
12728                         break;
12729                 case 1024:
12730                 default:
12731                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12732                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12733                         break;
12734                 }
12735         }
12736
12737 out:
12738         return val;
12739 }
12740
12741 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12742 {
12743         struct tg3_internal_buffer_desc test_desc;
12744         u32 sram_dma_descs;
12745         int i, ret;
12746
12747         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12748
12749         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12750         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12751         tw32(RDMAC_STATUS, 0);
12752         tw32(WDMAC_STATUS, 0);
12753
12754         tw32(BUFMGR_MODE, 0);
12755         tw32(FTQ_RESET, 0);
12756
12757         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12758         test_desc.addr_lo = buf_dma & 0xffffffff;
12759         test_desc.nic_mbuf = 0x00002100;
12760         test_desc.len = size;
12761
12762         /*
12763          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12764          * the *second* time the tg3 driver was getting loaded after an
12765          * initial scan.
12766          *
12767          * Broadcom tells me:
12768          *   ...the DMA engine is connected to the GRC block and a DMA
12769          *   reset may affect the GRC block in some unpredictable way...
12770          *   The behavior of resets to individual blocks has not been tested.
12771          *
12772          * Broadcom noted the GRC reset will also reset all sub-components.
12773          */
12774         if (to_device) {
12775                 test_desc.cqid_sqid = (13 << 8) | 2;
12776
12777                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12778                 udelay(40);
12779         } else {
12780                 test_desc.cqid_sqid = (16 << 8) | 7;
12781
12782                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12783                 udelay(40);
12784         }
12785         test_desc.flags = 0x00000005;
12786
12787         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12788                 u32 val;
12789
12790                 val = *(((u32 *)&test_desc) + i);
12791                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12792                                        sram_dma_descs + (i * sizeof(u32)));
12793                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12794         }
12795         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12796
12797         if (to_device) {
12798                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12799         } else {
12800                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12801         }
12802
12803         ret = -ENODEV;
12804         for (i = 0; i < 40; i++) {
12805                 u32 val;
12806
12807                 if (to_device)
12808                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12809                 else
12810                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12811                 if ((val & 0xffff) == sram_dma_descs) {
12812                         ret = 0;
12813                         break;
12814                 }
12815
12816                 udelay(100);
12817         }
12818
12819         return ret;
12820 }
12821
12822 #define TEST_BUFFER_SIZE        0x2000
12823
12824 static int __devinit tg3_test_dma(struct tg3 *tp)
12825 {
12826         dma_addr_t buf_dma;
12827         u32 *buf, saved_dma_rwctrl;
12828         int ret;
12829
12830         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12831         if (!buf) {
12832                 ret = -ENOMEM;
12833                 goto out_nofree;
12834         }
12835
12836         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12837                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12838
12839         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12840
12841         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12842                 /* DMA read watermark not used on PCIE */
12843                 tp->dma_rwctrl |= 0x00180000;
12844         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12845                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12846                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12847                         tp->dma_rwctrl |= 0x003f0000;
12848                 else
12849                         tp->dma_rwctrl |= 0x003f000f;
12850         } else {
12851                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12852                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12853                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12854                         u32 read_water = 0x7;
12855
12856                         /* If the 5704 is behind the EPB bridge, we can
12857                          * do the less restrictive ONE_DMA workaround for
12858                          * better performance.
12859                          */
12860                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12861                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12862                                 tp->dma_rwctrl |= 0x8000;
12863                         else if (ccval == 0x6 || ccval == 0x7)
12864                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12865
12866                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12867                                 read_water = 4;
12868                         /* Set bit 23 to enable PCIX hw bug fix */
12869                         tp->dma_rwctrl |=
12870                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12871                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12872                                 (1 << 23);
12873                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12874                         /* 5780 always in PCIX mode */
12875                         tp->dma_rwctrl |= 0x00144000;
12876                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12877                         /* 5714 always in PCIX mode */
12878                         tp->dma_rwctrl |= 0x00148000;
12879                 } else {
12880                         tp->dma_rwctrl |= 0x001b000f;
12881                 }
12882         }
12883
12884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12886                 tp->dma_rwctrl &= 0xfffffff0;
12887
12888         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12889             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12890                 /* Remove this if it causes problems for some boards. */
12891                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12892
12893                 /* On 5700/5701 chips, we need to set this bit.
12894                  * Otherwise the chip will issue cacheline transactions
12895                  * to streamable DMA memory with not all the byte
12896                  * enables turned on.  This is an error on several
12897                  * RISC PCI controllers, in particular sparc64.
12898                  *
12899                  * On 5703/5704 chips, this bit has been reassigned
12900                  * a different meaning.  In particular, it is used
12901                  * on those chips to enable a PCI-X workaround.
12902                  */
12903                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12904         }
12905
12906         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12907
12908 #if 0
12909         /* Unneeded, already done by tg3_get_invariants.  */
12910         tg3_switch_clocks(tp);
12911 #endif
12912
12913         ret = 0;
12914         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12915             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12916                 goto out;
12917
12918         /* It is best to perform DMA test with maximum write burst size
12919          * to expose the 5700/5701 write DMA bug.
12920          */
12921         saved_dma_rwctrl = tp->dma_rwctrl;
12922         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12923         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12924
12925         while (1) {
12926                 u32 *p = buf, i;
12927
12928                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12929                         p[i] = i;
12930
12931                 /* Send the buffer to the chip. */
12932                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12933                 if (ret) {
12934                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12935                         break;
12936                 }
12937
12938 #if 0
12939                 /* validate data reached card RAM correctly. */
12940                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12941                         u32 val;
12942                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12943                         if (le32_to_cpu(val) != p[i]) {
12944                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12945                                 /* ret = -ENODEV here? */
12946                         }
12947                         p[i] = 0;
12948                 }
12949 #endif
12950                 /* Now read it back. */
12951                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12952                 if (ret) {
12953                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12954
12955                         break;
12956                 }
12957
12958                 /* Verify it. */
12959                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12960                         if (p[i] == i)
12961                                 continue;
12962
12963                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12964                             DMA_RWCTRL_WRITE_BNDRY_16) {
12965                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12966                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12967                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12968                                 break;
12969                         } else {
12970                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12971                                 ret = -ENODEV;
12972                                 goto out;
12973                         }
12974                 }
12975
12976                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12977                         /* Success. */
12978                         ret = 0;
12979                         break;
12980                 }
12981         }
12982         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12983             DMA_RWCTRL_WRITE_BNDRY_16) {
12984                 static struct pci_device_id dma_wait_state_chipsets[] = {
12985                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12986                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12987                         { },
12988                 };
12989
12990                 /* DMA test passed without adjusting DMA boundary,
12991                  * now look for chipsets that are known to expose the
12992                  * DMA bug without failing the test.
12993                  */
12994                 if (pci_dev_present(dma_wait_state_chipsets)) {
12995                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12996                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12997                 }
12998                 else
12999                         /* Safe to use the calculated DMA boundary. */
13000                         tp->dma_rwctrl = saved_dma_rwctrl;
13001
13002                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13003         }
13004
13005 out:
13006         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13007 out_nofree:
13008         return ret;
13009 }
13010
13011 static void __devinit tg3_init_link_config(struct tg3 *tp)
13012 {
13013         tp->link_config.advertising =
13014                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13015                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13016                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13017                  ADVERTISED_Autoneg | ADVERTISED_MII);
13018         tp->link_config.speed = SPEED_INVALID;
13019         tp->link_config.duplex = DUPLEX_INVALID;
13020         tp->link_config.autoneg = AUTONEG_ENABLE;
13021         tp->link_config.active_speed = SPEED_INVALID;
13022         tp->link_config.active_duplex = DUPLEX_INVALID;
13023         tp->link_config.phy_is_low_power = 0;
13024         tp->link_config.orig_speed = SPEED_INVALID;
13025         tp->link_config.orig_duplex = DUPLEX_INVALID;
13026         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13027 }
13028
13029 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13030 {
13031         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13032                 tp->bufmgr_config.mbuf_read_dma_low_water =
13033                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13034                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13035                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13036                 tp->bufmgr_config.mbuf_high_water =
13037                         DEFAULT_MB_HIGH_WATER_5705;
13038                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13039                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13040                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13041                         tp->bufmgr_config.mbuf_high_water =
13042                                 DEFAULT_MB_HIGH_WATER_5906;
13043                 }
13044
13045                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13046                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13047                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13048                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13049                 tp->bufmgr_config.mbuf_high_water_jumbo =
13050                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13051         } else {
13052                 tp->bufmgr_config.mbuf_read_dma_low_water =
13053                         DEFAULT_MB_RDMA_LOW_WATER;
13054                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13055                         DEFAULT_MB_MACRX_LOW_WATER;
13056                 tp->bufmgr_config.mbuf_high_water =
13057                         DEFAULT_MB_HIGH_WATER;
13058
13059                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13060                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13061                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13062                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13063                 tp->bufmgr_config.mbuf_high_water_jumbo =
13064                         DEFAULT_MB_HIGH_WATER_JUMBO;
13065         }
13066
13067         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13068         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13069 }
13070
13071 static char * __devinit tg3_phy_string(struct tg3 *tp)
13072 {
13073         switch (tp->phy_id & PHY_ID_MASK) {
13074         case PHY_ID_BCM5400:    return "5400";
13075         case PHY_ID_BCM5401:    return "5401";
13076         case PHY_ID_BCM5411:    return "5411";
13077         case PHY_ID_BCM5701:    return "5701";
13078         case PHY_ID_BCM5703:    return "5703";
13079         case PHY_ID_BCM5704:    return "5704";
13080         case PHY_ID_BCM5705:    return "5705";
13081         case PHY_ID_BCM5750:    return "5750";
13082         case PHY_ID_BCM5752:    return "5752";
13083         case PHY_ID_BCM5714:    return "5714";
13084         case PHY_ID_BCM5780:    return "5780";
13085         case PHY_ID_BCM5755:    return "5755";
13086         case PHY_ID_BCM5787:    return "5787";
13087         case PHY_ID_BCM5784:    return "5784";
13088         case PHY_ID_BCM5756:    return "5722/5756";
13089         case PHY_ID_BCM5906:    return "5906";
13090         case PHY_ID_BCM5761:    return "5761";
13091         case PHY_ID_BCM8002:    return "8002/serdes";
13092         case 0:                 return "serdes";
13093         default:                return "unknown";
13094         }
13095 }
13096
13097 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13098 {
13099         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13100                 strcpy(str, "PCI Express");
13101                 return str;
13102         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13103                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13104
13105                 strcpy(str, "PCIX:");
13106
13107                 if ((clock_ctrl == 7) ||
13108                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13109                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13110                         strcat(str, "133MHz");
13111                 else if (clock_ctrl == 0)
13112                         strcat(str, "33MHz");
13113                 else if (clock_ctrl == 2)
13114                         strcat(str, "50MHz");
13115                 else if (clock_ctrl == 4)
13116                         strcat(str, "66MHz");
13117                 else if (clock_ctrl == 6)
13118                         strcat(str, "100MHz");
13119         } else {
13120                 strcpy(str, "PCI:");
13121                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13122                         strcat(str, "66MHz");
13123                 else
13124                         strcat(str, "33MHz");
13125         }
13126         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13127                 strcat(str, ":32-bit");
13128         else
13129                 strcat(str, ":64-bit");
13130         return str;
13131 }
13132
13133 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13134 {
13135         struct pci_dev *peer;
13136         unsigned int func, devnr = tp->pdev->devfn & ~7;
13137
13138         for (func = 0; func < 8; func++) {
13139                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13140                 if (peer && peer != tp->pdev)
13141                         break;
13142                 pci_dev_put(peer);
13143         }
13144         /* 5704 can be configured in single-port mode, set peer to
13145          * tp->pdev in that case.
13146          */
13147         if (!peer) {
13148                 peer = tp->pdev;
13149                 return peer;
13150         }
13151
13152         /*
13153          * We don't need to keep the refcount elevated; there's no way
13154          * to remove one half of this device without removing the other
13155          */
13156         pci_dev_put(peer);
13157
13158         return peer;
13159 }
13160
13161 static void __devinit tg3_init_coal(struct tg3 *tp)
13162 {
13163         struct ethtool_coalesce *ec = &tp->coal;
13164
13165         memset(ec, 0, sizeof(*ec));
13166         ec->cmd = ETHTOOL_GCOALESCE;
13167         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13168         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13169         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13170         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13171         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13172         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13173         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13174         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13175         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13176
13177         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13178                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13179                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13180                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13181                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13182                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13183         }
13184
13185         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13186                 ec->rx_coalesce_usecs_irq = 0;
13187                 ec->tx_coalesce_usecs_irq = 0;
13188                 ec->stats_block_coalesce_usecs = 0;
13189         }
13190 }
13191
13192 static const struct net_device_ops tg3_netdev_ops = {
13193         .ndo_open               = tg3_open,
13194         .ndo_stop               = tg3_close,
13195         .ndo_start_xmit         = tg3_start_xmit,
13196         .ndo_get_stats          = tg3_get_stats,
13197         .ndo_validate_addr      = eth_validate_addr,
13198         .ndo_set_multicast_list = tg3_set_rx_mode,
13199         .ndo_set_mac_address    = tg3_set_mac_addr,
13200         .ndo_do_ioctl           = tg3_ioctl,
13201         .ndo_tx_timeout         = tg3_tx_timeout,
13202         .ndo_change_mtu         = tg3_change_mtu,
13203 #if TG3_VLAN_TAG_USED
13204         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13205 #endif
13206 #ifdef CONFIG_NET_POLL_CONTROLLER
13207         .ndo_poll_controller    = tg3_poll_controller,
13208 #endif
13209 };
13210
13211 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13212         .ndo_open               = tg3_open,
13213         .ndo_stop               = tg3_close,
13214         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13215         .ndo_get_stats          = tg3_get_stats,
13216         .ndo_validate_addr      = eth_validate_addr,
13217         .ndo_set_multicast_list = tg3_set_rx_mode,
13218         .ndo_set_mac_address    = tg3_set_mac_addr,
13219         .ndo_do_ioctl           = tg3_ioctl,
13220         .ndo_tx_timeout         = tg3_tx_timeout,
13221         .ndo_change_mtu         = tg3_change_mtu,
13222 #if TG3_VLAN_TAG_USED
13223         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13224 #endif
13225 #ifdef CONFIG_NET_POLL_CONTROLLER
13226         .ndo_poll_controller    = tg3_poll_controller,
13227 #endif
13228 };
13229
13230 static int __devinit tg3_init_one(struct pci_dev *pdev,
13231                                   const struct pci_device_id *ent)
13232 {
13233         static int tg3_version_printed = 0;
13234         struct net_device *dev;
13235         struct tg3 *tp;
13236         int err, pm_cap;
13237         char str[40];
13238         u64 dma_mask, persist_dma_mask;
13239
13240         if (tg3_version_printed++ == 0)
13241                 printk(KERN_INFO "%s", version);
13242
13243         err = pci_enable_device(pdev);
13244         if (err) {
13245                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13246                        "aborting.\n");
13247                 return err;
13248         }
13249
13250         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13251         if (err) {
13252                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13253                        "aborting.\n");
13254                 goto err_out_disable_pdev;
13255         }
13256
13257         pci_set_master(pdev);
13258
13259         /* Find power-management capability. */
13260         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13261         if (pm_cap == 0) {
13262                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13263                        "aborting.\n");
13264                 err = -EIO;
13265                 goto err_out_free_res;
13266         }
13267
13268         dev = alloc_etherdev(sizeof(*tp));
13269         if (!dev) {
13270                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13271                 err = -ENOMEM;
13272                 goto err_out_free_res;
13273         }
13274
13275         SET_NETDEV_DEV(dev, &pdev->dev);
13276
13277 #if TG3_VLAN_TAG_USED
13278         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13279 #endif
13280
13281         tp = netdev_priv(dev);
13282         tp->pdev = pdev;
13283         tp->dev = dev;
13284         tp->pm_cap = pm_cap;
13285         tp->rx_mode = TG3_DEF_RX_MODE;
13286         tp->tx_mode = TG3_DEF_TX_MODE;
13287
13288         if (tg3_debug > 0)
13289                 tp->msg_enable = tg3_debug;
13290         else
13291                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13292
13293         /* The word/byte swap controls here control register access byte
13294          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13295          * setting below.
13296          */
13297         tp->misc_host_ctrl =
13298                 MISC_HOST_CTRL_MASK_PCI_INT |
13299                 MISC_HOST_CTRL_WORD_SWAP |
13300                 MISC_HOST_CTRL_INDIR_ACCESS |
13301                 MISC_HOST_CTRL_PCISTATE_RW;
13302
13303         /* The NONFRM (non-frame) byte/word swap controls take effect
13304          * on descriptor entries, anything which isn't packet data.
13305          *
13306          * The StrongARM chips on the board (one for tx, one for rx)
13307          * are running in big-endian mode.
13308          */
13309         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13310                         GRC_MODE_WSWAP_NONFRM_DATA);
13311 #ifdef __BIG_ENDIAN
13312         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13313 #endif
13314         spin_lock_init(&tp->lock);
13315         spin_lock_init(&tp->indirect_lock);
13316         INIT_WORK(&tp->reset_task, tg3_reset_task);
13317
13318         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13319         if (!tp->regs) {
13320                 printk(KERN_ERR PFX "Cannot map device registers, "
13321                        "aborting.\n");
13322                 err = -ENOMEM;
13323                 goto err_out_free_dev;
13324         }
13325
13326         tg3_init_link_config(tp);
13327
13328         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13329         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13330         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13331
13332         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13333         dev->ethtool_ops = &tg3_ethtool_ops;
13334         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13335         dev->irq = pdev->irq;
13336
13337         err = tg3_get_invariants(tp);
13338         if (err) {
13339                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13340                        "aborting.\n");
13341                 goto err_out_iounmap;
13342         }
13343
13344         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13345             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13346                 dev->netdev_ops = &tg3_netdev_ops;
13347         else
13348                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13349
13350
13351         /* The EPB bridge inside 5714, 5715, and 5780 and any
13352          * device behind the EPB cannot support DMA addresses > 40-bit.
13353          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13354          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13355          * do DMA address check in tg3_start_xmit().
13356          */
13357         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13358                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13359         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13360                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13361 #ifdef CONFIG_HIGHMEM
13362                 dma_mask = DMA_BIT_MASK(64);
13363 #endif
13364         } else
13365                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13366
13367         /* Configure DMA attributes. */
13368         if (dma_mask > DMA_BIT_MASK(32)) {
13369                 err = pci_set_dma_mask(pdev, dma_mask);
13370                 if (!err) {
13371                         dev->features |= NETIF_F_HIGHDMA;
13372                         err = pci_set_consistent_dma_mask(pdev,
13373                                                           persist_dma_mask);
13374                         if (err < 0) {
13375                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13376                                        "DMA for consistent allocations\n");
13377                                 goto err_out_iounmap;
13378                         }
13379                 }
13380         }
13381         if (err || dma_mask == DMA_BIT_MASK(32)) {
13382                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13383                 if (err) {
13384                         printk(KERN_ERR PFX "No usable DMA configuration, "
13385                                "aborting.\n");
13386                         goto err_out_iounmap;
13387                 }
13388         }
13389
13390         tg3_init_bufmgr_config(tp);
13391
13392         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13393                 tp->fw_needed = FIRMWARE_TG3;
13394
13395         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13396                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13397         }
13398         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13399             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13400             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13401             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13402             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13403                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13404         } else {
13405                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13406                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13407                         tp->fw_needed = FIRMWARE_TG3TSO5;
13408                 else
13409                         tp->fw_needed = FIRMWARE_TG3TSO;
13410         }
13411
13412         /* TSO is on by default on chips that support hardware TSO.
13413          * Firmware TSO on older chips gives lower performance, so it
13414          * is off by default, but can be enabled using ethtool.
13415          */
13416         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13417                 if (dev->features & NETIF_F_IP_CSUM)
13418                         dev->features |= NETIF_F_TSO;
13419                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13420                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13421                         dev->features |= NETIF_F_TSO6;
13422                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13423                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13424                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13425                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13426                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13427                         dev->features |= NETIF_F_TSO_ECN;
13428         }
13429
13430
13431         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13432             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13433             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13434                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13435                 tp->rx_pending = 63;
13436         }
13437
13438         err = tg3_get_device_address(tp);
13439         if (err) {
13440                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13441                        "aborting.\n");
13442                 goto err_out_fw;
13443         }
13444
13445         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13446                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13447                 if (!tp->aperegs) {
13448                         printk(KERN_ERR PFX "Cannot map APE registers, "
13449                                "aborting.\n");
13450                         err = -ENOMEM;
13451                         goto err_out_fw;
13452                 }
13453
13454                 tg3_ape_lock_init(tp);
13455
13456                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13457                         tg3_read_dash_ver(tp);
13458         }
13459
13460         /*
13461          * Reset chip in case UNDI or EFI driver did not shutdown
13462          * DMA self test will enable WDMAC and we'll see (spurious)
13463          * pending DMA on the PCI bus at that point.
13464          */
13465         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13466             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13467                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13468                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13469         }
13470
13471         err = tg3_test_dma(tp);
13472         if (err) {
13473                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13474                 goto err_out_apeunmap;
13475         }
13476
13477         /* flow control autonegotiation is default behavior */
13478         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13479         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13480
13481         tg3_init_coal(tp);
13482
13483         pci_set_drvdata(pdev, dev);
13484
13485         err = register_netdev(dev);
13486         if (err) {
13487                 printk(KERN_ERR PFX "Cannot register net device, "
13488                        "aborting.\n");
13489                 goto err_out_apeunmap;
13490         }
13491
13492         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13493                dev->name,
13494                tp->board_part_number,
13495                tp->pci_chip_rev_id,
13496                tg3_bus_string(tp, str),
13497                dev->dev_addr);
13498
13499         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13500                 printk(KERN_INFO
13501                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13502                        tp->dev->name,
13503                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13504                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13505         else
13506                 printk(KERN_INFO
13507                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13508                        tp->dev->name, tg3_phy_string(tp),
13509                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13510                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13511                          "10/100/1000Base-T")),
13512                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13513
13514         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13515                dev->name,
13516                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13517                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13518                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13519                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13520                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13521         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13522                dev->name, tp->dma_rwctrl,
13523                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13524                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13525
13526         return 0;
13527
13528 err_out_apeunmap:
13529         if (tp->aperegs) {
13530                 iounmap(tp->aperegs);
13531                 tp->aperegs = NULL;
13532         }
13533
13534 err_out_fw:
13535         if (tp->fw)
13536                 release_firmware(tp->fw);
13537
13538 err_out_iounmap:
13539         if (tp->regs) {
13540                 iounmap(tp->regs);
13541                 tp->regs = NULL;
13542         }
13543
13544 err_out_free_dev:
13545         free_netdev(dev);
13546
13547 err_out_free_res:
13548         pci_release_regions(pdev);
13549
13550 err_out_disable_pdev:
13551         pci_disable_device(pdev);
13552         pci_set_drvdata(pdev, NULL);
13553         return err;
13554 }
13555
13556 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13557 {
13558         struct net_device *dev = pci_get_drvdata(pdev);
13559
13560         if (dev) {
13561                 struct tg3 *tp = netdev_priv(dev);
13562
13563                 if (tp->fw)
13564                         release_firmware(tp->fw);
13565
13566                 flush_scheduled_work();
13567
13568                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13569                         tg3_phy_fini(tp);
13570                         tg3_mdio_fini(tp);
13571                 }
13572
13573                 unregister_netdev(dev);
13574                 if (tp->aperegs) {
13575                         iounmap(tp->aperegs);
13576                         tp->aperegs = NULL;
13577                 }
13578                 if (tp->regs) {
13579                         iounmap(tp->regs);
13580                         tp->regs = NULL;
13581                 }
13582                 free_netdev(dev);
13583                 pci_release_regions(pdev);
13584                 pci_disable_device(pdev);
13585                 pci_set_drvdata(pdev, NULL);
13586         }
13587 }
13588
13589 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13590 {
13591         struct net_device *dev = pci_get_drvdata(pdev);
13592         struct tg3 *tp = netdev_priv(dev);
13593         pci_power_t target_state;
13594         int err;
13595
13596         /* PCI register 4 needs to be saved whether netif_running() or not.
13597          * MSI address and data need to be saved if using MSI and
13598          * netif_running().
13599          */
13600         pci_save_state(pdev);
13601
13602         if (!netif_running(dev))
13603                 return 0;
13604
13605         flush_scheduled_work();
13606         tg3_phy_stop(tp);
13607         tg3_netif_stop(tp);
13608
13609         del_timer_sync(&tp->timer);
13610
13611         tg3_full_lock(tp, 1);
13612         tg3_disable_ints(tp);
13613         tg3_full_unlock(tp);
13614
13615         netif_device_detach(dev);
13616
13617         tg3_full_lock(tp, 0);
13618         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13619         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13620         tg3_full_unlock(tp);
13621
13622         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13623
13624         err = tg3_set_power_state(tp, target_state);
13625         if (err) {
13626                 int err2;
13627
13628                 tg3_full_lock(tp, 0);
13629
13630                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13631                 err2 = tg3_restart_hw(tp, 1);
13632                 if (err2)
13633                         goto out;
13634
13635                 tp->timer.expires = jiffies + tp->timer_offset;
13636                 add_timer(&tp->timer);
13637
13638                 netif_device_attach(dev);
13639                 tg3_netif_start(tp);
13640
13641 out:
13642                 tg3_full_unlock(tp);
13643
13644                 if (!err2)
13645                         tg3_phy_start(tp);
13646         }
13647
13648         return err;
13649 }
13650
13651 static int tg3_resume(struct pci_dev *pdev)
13652 {
13653         struct net_device *dev = pci_get_drvdata(pdev);
13654         struct tg3 *tp = netdev_priv(dev);
13655         int err;
13656
13657         pci_restore_state(tp->pdev);
13658
13659         if (!netif_running(dev))
13660                 return 0;
13661
13662         err = tg3_set_power_state(tp, PCI_D0);
13663         if (err)
13664                 return err;
13665
13666         netif_device_attach(dev);
13667
13668         tg3_full_lock(tp, 0);
13669
13670         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13671         err = tg3_restart_hw(tp, 1);
13672         if (err)
13673                 goto out;
13674
13675         tp->timer.expires = jiffies + tp->timer_offset;
13676         add_timer(&tp->timer);
13677
13678         tg3_netif_start(tp);
13679
13680 out:
13681         tg3_full_unlock(tp);
13682
13683         if (!err)
13684                 tg3_phy_start(tp);
13685
13686         return err;
13687 }
13688
13689 static struct pci_driver tg3_driver = {
13690         .name           = DRV_MODULE_NAME,
13691         .id_table       = tg3_pci_tbl,
13692         .probe          = tg3_init_one,
13693         .remove         = __devexit_p(tg3_remove_one),
13694         .suspend        = tg3_suspend,
13695         .resume         = tg3_resume
13696 };
13697
13698 static int __init tg3_init(void)
13699 {
13700         return pci_register_driver(&tg3_driver);
13701 }
13702
13703 static void __exit tg3_cleanup(void)
13704 {
13705         pci_unregister_driver(&tg3_driver);
13706 }
13707
13708 module_init(tg3_init);
13709 module_exit(tg3_cleanup);