2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.101"
72 #define DRV_MODULE_RELDATE "August 28, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define TG3_DMA_BYTE_ENAB 64
130 #define TG3_RX_STD_DMA_SZ 1536
131 #define TG3_RX_JMB_DMA_SZ 9046
133 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138 /* minimum number of free TX descriptors required to wake up TX process */
139 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
141 #define TG3_RAW_IP_ALIGN 2
143 /* number of ETHTOOL_GSTATS u64's */
144 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
146 #define TG3_NUM_TEST 6
148 #define FIRMWARE_TG3 "tigon/tg3.bin"
149 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
152 static char version[] __devinitdata =
153 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157 MODULE_LICENSE("GPL");
158 MODULE_VERSION(DRV_MODULE_VERSION);
159 MODULE_FIRMWARE(FIRMWARE_TG3);
160 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165 module_param(tg3_debug, int, 0);
166 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
168 static struct pci_device_id tg3_pci_tbl[] = {
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
247 static const struct {
248 const char string[ETH_GSTRING_LEN];
249 } ethtool_stats_keys[TG3_NUM_STATS] = {
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
282 { "tx_flow_control" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
315 { "rx_threshold_hit" },
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
328 static const struct {
329 const char string[ETH_GSTRING_LEN];
330 } ethtool_test_keys[TG3_NUM_TEST] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
339 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
341 writel(val, tp->regs + off);
344 static u32 tg3_read32(struct tg3 *tp, u32 off)
346 return (readl(tp->regs + off));
349 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
351 writel(val, tp->aperegs + off);
354 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
356 return (readl(tp->aperegs + off));
359 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363 spin_lock_irqsave(&tp->indirect_lock, flags);
364 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
365 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
366 spin_unlock_irqrestore(&tp->indirect_lock, flags);
369 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
371 writel(val, tp->regs + off);
372 readl(tp->regs + off);
375 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
392 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
393 TG3_64BIT_REG_LOW, val);
396 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
397 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
398 TG3_64BIT_REG_LOW, val);
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
410 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
412 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
413 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 /* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
434 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
436 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
437 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
438 /* Non-posted methods */
439 tp->write32(tp, off, val);
442 tg3_write32(tp, off, val);
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
454 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
456 tp->write32_mbox(tp, off, val);
457 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
458 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
459 tp->read32_mbox(tp, off);
462 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
464 void __iomem *mbox = tp->regs + off;
466 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
468 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
474 return (readl(tp->regs + off + GRCMBOX_BASE));
477 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
479 writel(val, tp->regs + off + GRCMBOX_BASE);
482 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
483 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
484 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
486 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
488 #define tw32(reg,val) tp->write32(tp, reg, val)
489 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
491 #define tr32(reg) tp->read32(tp, reg)
493 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
498 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
501 spin_lock_irqsave(&tp->indirect_lock, flags);
502 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
503 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
506 /* Always leave this as zero. */
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
510 tw32_f(TG3PCI_MEM_WIN_DATA, val);
512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
518 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
523 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
528 spin_lock_irqsave(&tp->indirect_lock, flags);
529 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
530 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
531 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
533 /* Always leave this as zero. */
534 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
537 *val = tr32(TG3PCI_MEM_WIN_DATA);
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
542 spin_unlock_irqrestore(&tp->indirect_lock, flags);
545 static void tg3_ape_lock_init(struct tg3 *tp)
549 /* Make sure the driver hasn't any stale locks. */
550 for (i = 0; i < 8; i++)
551 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
552 APE_LOCK_GRANT_DRIVER);
555 static int tg3_ape_lock(struct tg3 *tp, int locknum)
561 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 case TG3_APE_LOCK_GRC:
566 case TG3_APE_LOCK_MEM:
574 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i = 0; i < 100; i++) {
578 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
579 if (status == APE_LOCK_GRANT_DRIVER)
584 if (status != APE_LOCK_GRANT_DRIVER) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
587 APE_LOCK_GRANT_DRIVER);
595 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 case TG3_APE_LOCK_GRC:
604 case TG3_APE_LOCK_MEM:
611 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
614 static void tg3_disable_ints(struct tg3 *tp)
616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
618 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
621 static void tg3_enable_ints(struct tg3 *tp)
624 struct tg3_napi *tnapi = &tp->napi[0];
628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
631 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
632 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
634 coal_now = tnapi->coal_now;
636 /* Force an initial interrupt */
637 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
638 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
639 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
641 tw32(HOSTCC_MODE, tp->coalesce_mode |
642 HOSTCC_MODE_ENABLE | coal_now);
645 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
647 struct tg3 *tp = tnapi->tp;
648 struct tg3_hw_status *sblk = tnapi->hw_status;
649 unsigned int work_exists = 0;
651 /* check for phy events */
652 if (!(tp->tg3_flags &
653 (TG3_FLAG_USE_LINKCHG_REG |
654 TG3_FLAG_POLL_SERDES))) {
655 if (sblk->status & SD_STATUS_LINK_CHG)
658 /* check for RX/TX work to do */
659 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
660 sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
669 * which reenables interrupts
671 static void tg3_int_reenable(struct tg3_napi *tnapi)
673 struct tg3 *tp = tnapi->tp;
675 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
678 /* When doing tagged status, this work check is unnecessary.
679 * The last_tag we write above tells the chip which piece of
680 * work we've completed.
682 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
684 tw32(HOSTCC_MODE, tp->coalesce_mode |
685 HOSTCC_MODE_ENABLE | tnapi->coal_now);
688 static inline void tg3_netif_stop(struct tg3 *tp)
690 tp->dev->trans_start = jiffies; /* prevent tx timeout */
691 napi_disable(&tp->napi[0].napi);
692 netif_tx_disable(tp->dev);
695 static inline void tg3_netif_start(struct tg3 *tp)
697 struct tg3_napi *tnapi = &tp->napi[0];
698 netif_wake_queue(tp->dev);
699 /* NOTE: unconditional netif_wake_queue is only appropriate
700 * so long as all callers are assured to have free tx slots
701 * (such as after tg3_init_hw)
703 napi_enable(&tnapi->napi);
704 tnapi->hw_status->status |= SD_STATUS_UPDATED;
708 static void tg3_switch_clocks(struct tg3 *tp)
710 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
713 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
714 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
717 orig_clock_ctrl = clock_ctrl;
718 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
719 CLOCK_CTRL_CLKRUN_OENABLE |
721 tp->pci_clock_ctrl = clock_ctrl;
723 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
724 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
725 tw32_wait_f(TG3PCI_CLOCK_CTRL,
726 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
728 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
729 tw32_wait_f(TG3PCI_CLOCK_CTRL,
731 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
733 tw32_wait_f(TG3PCI_CLOCK_CTRL,
734 clock_ctrl | (CLOCK_CTRL_ALTCLK),
737 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
740 #define PHY_BUSY_LOOPS 5000
742 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
748 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
750 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
756 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
757 MI_COM_PHY_ADDR_MASK);
758 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
759 MI_COM_REG_ADDR_MASK);
760 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
762 tw32_f(MAC_MI_COM, frame_val);
764 loops = PHY_BUSY_LOOPS;
767 frame_val = tr32(MAC_MI_COM);
769 if ((frame_val & MI_COM_BUSY) == 0) {
771 frame_val = tr32(MAC_MI_COM);
779 *val = frame_val & MI_COM_DATA_MASK;
783 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
784 tw32_f(MAC_MI_MODE, tp->mi_mode);
791 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
797 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
798 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
801 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
803 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
807 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (val & MI_COM_DATA_MASK);
812 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
814 tw32_f(MAC_MI_COM, frame_val);
816 loops = PHY_BUSY_LOOPS;
819 frame_val = tr32(MAC_MI_COM);
820 if ((frame_val & MI_COM_BUSY) == 0) {
822 frame_val = tr32(MAC_MI_COM);
832 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
833 tw32_f(MAC_MI_MODE, tp->mi_mode);
840 static int tg3_bmcr_reset(struct tg3 *tp)
845 /* OK, reset it, and poll the BMCR_RESET bit until it
846 * clears or we time out.
848 phy_control = BMCR_RESET;
849 err = tg3_writephy(tp, MII_BMCR, phy_control);
855 err = tg3_readphy(tp, MII_BMCR, &phy_control);
859 if ((phy_control & BMCR_RESET) == 0) {
871 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
873 struct tg3 *tp = bp->priv;
876 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
879 if (tg3_readphy(tp, reg, &val))
885 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
887 struct tg3 *tp = bp->priv;
889 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
892 if (tg3_writephy(tp, reg, val))
898 static int tg3_mdio_reset(struct mii_bus *bp)
903 static void tg3_mdio_config_5785(struct tg3 *tp)
906 struct phy_device *phydev;
908 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
909 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
910 case TG3_PHY_ID_BCM50610:
911 val = MAC_PHYCFG2_50610_LED_MODES;
913 case TG3_PHY_ID_BCMAC131:
914 val = MAC_PHYCFG2_AC131_LED_MODES;
916 case TG3_PHY_ID_RTL8211C:
917 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
919 case TG3_PHY_ID_RTL8201E:
920 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
926 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
927 tw32(MAC_PHYCFG2, val);
929 val = tr32(MAC_PHYCFG1);
930 val &= ~(MAC_PHYCFG1_RGMII_INT |
931 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
932 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
933 tw32(MAC_PHYCFG1, val);
938 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
939 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
940 MAC_PHYCFG2_FMODE_MASK_MASK |
941 MAC_PHYCFG2_GMODE_MASK_MASK |
942 MAC_PHYCFG2_ACT_MASK_MASK |
943 MAC_PHYCFG2_QUAL_MASK_MASK |
944 MAC_PHYCFG2_INBAND_ENABLE;
946 tw32(MAC_PHYCFG2, val);
948 val = tr32(MAC_PHYCFG1);
949 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
950 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
951 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
952 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
953 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
954 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
955 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
957 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
958 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
959 tw32(MAC_PHYCFG1, val);
961 val = tr32(MAC_EXT_RGMII_MODE);
962 val &= ~(MAC_RGMII_MODE_RX_INT_B |
963 MAC_RGMII_MODE_RX_QUALITY |
964 MAC_RGMII_MODE_RX_ACTIVITY |
965 MAC_RGMII_MODE_RX_ENG_DET |
966 MAC_RGMII_MODE_TX_ENABLE |
967 MAC_RGMII_MODE_TX_LOWPWR |
968 MAC_RGMII_MODE_TX_RESET);
969 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
970 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
971 val |= MAC_RGMII_MODE_RX_INT_B |
972 MAC_RGMII_MODE_RX_QUALITY |
973 MAC_RGMII_MODE_RX_ACTIVITY |
974 MAC_RGMII_MODE_RX_ENG_DET;
975 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
976 val |= MAC_RGMII_MODE_TX_ENABLE |
977 MAC_RGMII_MODE_TX_LOWPWR |
978 MAC_RGMII_MODE_TX_RESET;
980 tw32(MAC_EXT_RGMII_MODE, val);
983 static void tg3_mdio_start(struct tg3 *tp)
985 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
986 mutex_lock(&tp->mdio_bus->mdio_lock);
987 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
988 mutex_unlock(&tp->mdio_bus->mdio_lock);
991 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
992 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
997 tg3_mdio_config_5785(tp);
1000 static void tg3_mdio_stop(struct tg3 *tp)
1002 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1003 mutex_lock(&tp->mdio_bus->mdio_lock);
1004 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1005 mutex_unlock(&tp->mdio_bus->mdio_lock);
1009 static int tg3_mdio_init(struct tg3 *tp)
1013 struct phy_device *phydev;
1017 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1018 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1021 tp->mdio_bus = mdiobus_alloc();
1022 if (tp->mdio_bus == NULL)
1025 tp->mdio_bus->name = "tg3 mdio bus";
1026 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1027 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1028 tp->mdio_bus->priv = tp;
1029 tp->mdio_bus->parent = &tp->pdev->dev;
1030 tp->mdio_bus->read = &tg3_mdio_read;
1031 tp->mdio_bus->write = &tg3_mdio_write;
1032 tp->mdio_bus->reset = &tg3_mdio_reset;
1033 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1034 tp->mdio_bus->irq = &tp->mdio_irq[0];
1036 for (i = 0; i < PHY_MAX_ADDR; i++)
1037 tp->mdio_bus->irq[i] = PHY_POLL;
1039 /* The bus registration will look for all the PHYs on the mdio bus.
1040 * Unfortunately, it does not ensure the PHY is powered up before
1041 * accessing the PHY ID registers. A chip reset is the
1042 * quickest way to bring the device back to an operational state..
1044 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1047 i = mdiobus_register(tp->mdio_bus);
1049 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1051 mdiobus_free(tp->mdio_bus);
1055 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1057 if (!phydev || !phydev->drv) {
1058 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1059 mdiobus_unregister(tp->mdio_bus);
1060 mdiobus_free(tp->mdio_bus);
1064 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1065 case TG3_PHY_ID_BCM57780:
1066 phydev->interface = PHY_INTERFACE_MODE_GMII;
1068 case TG3_PHY_ID_BCM50610:
1069 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1070 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1071 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1072 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1073 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1074 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1076 case TG3_PHY_ID_RTL8211C:
1077 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1079 case TG3_PHY_ID_RTL8201E:
1080 case TG3_PHY_ID_BCMAC131:
1081 phydev->interface = PHY_INTERFACE_MODE_MII;
1082 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1086 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1089 tg3_mdio_config_5785(tp);
1094 static void tg3_mdio_fini(struct tg3 *tp)
1096 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1097 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1098 mdiobus_unregister(tp->mdio_bus);
1099 mdiobus_free(tp->mdio_bus);
1100 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1104 /* tp->lock is held. */
1105 static inline void tg3_generate_fw_event(struct tg3 *tp)
1109 val = tr32(GRC_RX_CPU_EVENT);
1110 val |= GRC_RX_CPU_DRIVER_EVENT;
1111 tw32_f(GRC_RX_CPU_EVENT, val);
1113 tp->last_event_jiffies = jiffies;
1116 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1118 /* tp->lock is held. */
1119 static void tg3_wait_for_event_ack(struct tg3 *tp)
1122 unsigned int delay_cnt;
1125 /* If enough time has passed, no wait is necessary. */
1126 time_remain = (long)(tp->last_event_jiffies + 1 +
1127 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1129 if (time_remain < 0)
1132 /* Check if we can shorten the wait time. */
1133 delay_cnt = jiffies_to_usecs(time_remain);
1134 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1135 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1136 delay_cnt = (delay_cnt >> 3) + 1;
1138 for (i = 0; i < delay_cnt; i++) {
1139 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1145 /* tp->lock is held. */
1146 static void tg3_ump_link_report(struct tg3 *tp)
1151 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1152 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1155 tg3_wait_for_event_ack(tp);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1159 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1162 if (!tg3_readphy(tp, MII_BMCR, ®))
1164 if (!tg3_readphy(tp, MII_BMSR, ®))
1165 val |= (reg & 0xffff);
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1169 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1171 if (!tg3_readphy(tp, MII_LPA, ®))
1172 val |= (reg & 0xffff);
1173 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1176 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1177 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1179 if (!tg3_readphy(tp, MII_STAT1000, ®))
1180 val |= (reg & 0xffff);
1182 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1184 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1190 tg3_generate_fw_event(tp);
1193 static void tg3_link_report(struct tg3 *tp)
1195 if (!netif_carrier_ok(tp->dev)) {
1196 if (netif_msg_link(tp))
1197 printk(KERN_INFO PFX "%s: Link is down.\n",
1199 tg3_ump_link_report(tp);
1200 } else if (netif_msg_link(tp)) {
1201 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1203 (tp->link_config.active_speed == SPEED_1000 ?
1205 (tp->link_config.active_speed == SPEED_100 ?
1207 (tp->link_config.active_duplex == DUPLEX_FULL ?
1210 printk(KERN_INFO PFX
1211 "%s: Flow control is %s for TX and %s for RX.\n",
1213 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1215 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1217 tg3_ump_link_report(tp);
1221 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226 miireg = ADVERTISE_PAUSE_CAP;
1227 else if (flow_ctrl & FLOW_CTRL_TX)
1228 miireg = ADVERTISE_PAUSE_ASYM;
1229 else if (flow_ctrl & FLOW_CTRL_RX)
1230 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1237 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1241 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1242 miireg = ADVERTISE_1000XPAUSE;
1243 else if (flow_ctrl & FLOW_CTRL_TX)
1244 miireg = ADVERTISE_1000XPSE_ASYM;
1245 else if (flow_ctrl & FLOW_CTRL_RX)
1246 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1253 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1257 if (lcladv & ADVERTISE_1000XPAUSE) {
1258 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1259 if (rmtadv & LPA_1000XPAUSE)
1260 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1261 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1264 if (rmtadv & LPA_1000XPAUSE)
1265 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1267 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1268 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1275 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1279 u32 old_rx_mode = tp->rx_mode;
1280 u32 old_tx_mode = tp->tx_mode;
1282 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1283 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1285 autoneg = tp->link_config.autoneg;
1287 if (autoneg == AUTONEG_ENABLE &&
1288 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1289 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1290 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1292 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1294 flowctrl = tp->link_config.flowctrl;
1296 tp->link_config.active_flowctrl = flowctrl;
1298 if (flowctrl & FLOW_CTRL_RX)
1299 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1301 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1303 if (old_rx_mode != tp->rx_mode)
1304 tw32_f(MAC_RX_MODE, tp->rx_mode);
1306 if (flowctrl & FLOW_CTRL_TX)
1307 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1309 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1311 if (old_tx_mode != tp->tx_mode)
1312 tw32_f(MAC_TX_MODE, tp->tx_mode);
1315 static void tg3_adjust_link(struct net_device *dev)
1317 u8 oldflowctrl, linkmesg = 0;
1318 u32 mac_mode, lcl_adv, rmt_adv;
1319 struct tg3 *tp = netdev_priv(dev);
1320 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1322 spin_lock(&tp->lock);
1324 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1325 MAC_MODE_HALF_DUPLEX);
1327 oldflowctrl = tp->link_config.active_flowctrl;
1333 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1334 mac_mode |= MAC_MODE_PORT_MODE_MII;
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1338 if (phydev->duplex == DUPLEX_HALF)
1339 mac_mode |= MAC_MODE_HALF_DUPLEX;
1341 lcl_adv = tg3_advert_flowctrl_1000T(
1342 tp->link_config.flowctrl);
1345 rmt_adv = LPA_PAUSE_CAP;
1346 if (phydev->asym_pause)
1347 rmt_adv |= LPA_PAUSE_ASYM;
1350 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1352 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1354 if (mac_mode != tp->mac_mode) {
1355 tp->mac_mode = mac_mode;
1356 tw32_f(MAC_MODE, tp->mac_mode);
1360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1361 if (phydev->speed == SPEED_10)
1363 MAC_MI_STAT_10MBPS_MODE |
1364 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1366 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1369 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1370 tw32(MAC_TX_LENGTHS,
1371 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1372 (6 << TX_LENGTHS_IPG_SHIFT) |
1373 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1375 tw32(MAC_TX_LENGTHS,
1376 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1377 (6 << TX_LENGTHS_IPG_SHIFT) |
1378 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1380 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1381 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1382 phydev->speed != tp->link_config.active_speed ||
1383 phydev->duplex != tp->link_config.active_duplex ||
1384 oldflowctrl != tp->link_config.active_flowctrl)
1387 tp->link_config.active_speed = phydev->speed;
1388 tp->link_config.active_duplex = phydev->duplex;
1390 spin_unlock(&tp->lock);
1393 tg3_link_report(tp);
1396 static int tg3_phy_init(struct tg3 *tp)
1398 struct phy_device *phydev;
1400 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1403 /* Bring the PHY back to a known state. */
1406 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1408 /* Attach the MAC to the PHY. */
1409 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1410 phydev->dev_flags, phydev->interface);
1411 if (IS_ERR(phydev)) {
1412 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1413 return PTR_ERR(phydev);
1416 /* Mask with MAC supported features. */
1417 switch (phydev->interface) {
1418 case PHY_INTERFACE_MODE_GMII:
1419 case PHY_INTERFACE_MODE_RGMII:
1420 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1421 phydev->supported &= (PHY_GBIT_FEATURES |
1423 SUPPORTED_Asym_Pause);
1427 case PHY_INTERFACE_MODE_MII:
1428 phydev->supported &= (PHY_BASIC_FEATURES |
1430 SUPPORTED_Asym_Pause);
1433 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1437 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1439 phydev->advertising = phydev->supported;
1444 static void tg3_phy_start(struct tg3 *tp)
1446 struct phy_device *phydev;
1448 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1451 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1453 if (tp->link_config.phy_is_low_power) {
1454 tp->link_config.phy_is_low_power = 0;
1455 phydev->speed = tp->link_config.orig_speed;
1456 phydev->duplex = tp->link_config.orig_duplex;
1457 phydev->autoneg = tp->link_config.orig_autoneg;
1458 phydev->advertising = tp->link_config.orig_advertising;
1463 phy_start_aneg(phydev);
1466 static void tg3_phy_stop(struct tg3 *tp)
1468 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1471 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1474 static void tg3_phy_fini(struct tg3 *tp)
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1477 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1478 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1482 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1485 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1488 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1492 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1495 tg3_writephy(tp, MII_TG3_FET_TEST,
1496 phytest | MII_TG3_FET_SHADOW_EN);
1497 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1499 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1501 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1502 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1504 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1508 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1515 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1516 tg3_phy_fet_toggle_apd(tp, enable);
1520 reg = MII_TG3_MISC_SHDW_WREN |
1521 MII_TG3_MISC_SHDW_SCR5_SEL |
1522 MII_TG3_MISC_SHDW_SCR5_LPED |
1523 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1524 MII_TG3_MISC_SHDW_SCR5_SDTL |
1525 MII_TG3_MISC_SHDW_SCR5_C125OE;
1526 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1527 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1529 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1532 reg = MII_TG3_MISC_SHDW_WREN |
1533 MII_TG3_MISC_SHDW_APD_SEL |
1534 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1536 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1538 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1541 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1545 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1546 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1549 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1552 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1553 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1555 tg3_writephy(tp, MII_TG3_FET_TEST,
1556 ephy | MII_TG3_FET_SHADOW_EN);
1557 if (!tg3_readphy(tp, reg, &phy)) {
1559 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1561 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1562 tg3_writephy(tp, reg, phy);
1564 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1567 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1568 MII_TG3_AUXCTL_SHDWSEL_MISC;
1569 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1570 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1572 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1574 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1575 phy |= MII_TG3_AUXCTL_MISC_WREN;
1576 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1581 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1585 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1588 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1589 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1590 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1591 (val | (1 << 15) | (1 << 4)));
1594 static void tg3_phy_apply_otp(struct tg3 *tp)
1603 /* Enable SM_DSP clock and tx 6dB coding. */
1604 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1605 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1606 MII_TG3_AUXCTL_ACTL_TX_6DB;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1609 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1610 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1611 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1613 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1614 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1615 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1617 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1618 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1619 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1621 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1622 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1624 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1625 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1627 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1628 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1629 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1631 /* Turn off SM_DSP clock. */
1632 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1633 MII_TG3_AUXCTL_ACTL_TX_6DB;
1634 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1637 static int tg3_wait_macro_done(struct tg3 *tp)
1644 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1645 if ((tmp32 & 0x1000) == 0)
1655 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1657 static const u32 test_pat[4][6] = {
1658 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1659 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1660 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1661 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1665 for (chan = 0; chan < 4; chan++) {
1668 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1669 (chan * 0x2000) | 0x0200);
1670 tg3_writephy(tp, 0x16, 0x0002);
1672 for (i = 0; i < 6; i++)
1673 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1676 tg3_writephy(tp, 0x16, 0x0202);
1677 if (tg3_wait_macro_done(tp)) {
1682 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1683 (chan * 0x2000) | 0x0200);
1684 tg3_writephy(tp, 0x16, 0x0082);
1685 if (tg3_wait_macro_done(tp)) {
1690 tg3_writephy(tp, 0x16, 0x0802);
1691 if (tg3_wait_macro_done(tp)) {
1696 for (i = 0; i < 6; i += 2) {
1699 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1700 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1701 tg3_wait_macro_done(tp)) {
1707 if (low != test_pat[chan][i] ||
1708 high != test_pat[chan][i+1]) {
1709 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1710 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1711 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1721 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1725 for (chan = 0; chan < 4; chan++) {
1728 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1729 (chan * 0x2000) | 0x0200);
1730 tg3_writephy(tp, 0x16, 0x0002);
1731 for (i = 0; i < 6; i++)
1732 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp))
1741 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1743 u32 reg32, phy9_orig;
1744 int retries, do_phy_reset, err;
1750 err = tg3_bmcr_reset(tp);
1756 /* Disable transmitter and interrupt. */
1757 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1761 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1763 /* Set full-duplex, 1000 mbps. */
1764 tg3_writephy(tp, MII_BMCR,
1765 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1767 /* Set to master mode. */
1768 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1771 tg3_writephy(tp, MII_TG3_CTRL,
1772 (MII_TG3_CTRL_AS_MASTER |
1773 MII_TG3_CTRL_ENABLE_AS_MASTER));
1775 /* Enable SM_DSP_CLOCK and 6dB. */
1776 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1778 /* Block the PHY control access. */
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1782 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1785 } while (--retries);
1787 err = tg3_phy_reset_chanpat(tp);
1791 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1792 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1794 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1795 tg3_writephy(tp, 0x16, 0x0000);
1797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1799 /* Set Extended packet length bit for jumbo frames */
1800 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1803 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1806 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1808 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1810 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1817 /* This will reset the tigon3 PHY if there is no valid
1818 * link unless the FORCE argument is non-zero.
1820 static int tg3_phy_reset(struct tg3 *tp)
1826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1829 val = tr32(GRC_MISC_CFG);
1830 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1833 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1834 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1838 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1839 netif_carrier_off(tp->dev);
1840 tg3_link_report(tp);
1843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1846 err = tg3_phy_reset_5703_4_5(tp);
1853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1854 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1855 cpmuctrl = tr32(TG3_CPMU_CTRL);
1856 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1858 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1861 err = tg3_bmcr_reset(tp);
1865 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1868 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1869 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1871 tw32(TG3_CPMU_CTRL, cpmuctrl);
1874 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1875 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1878 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1879 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1880 CPMU_LSPD_1000MB_MACCLK_12_5) {
1881 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1883 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1887 tg3_phy_apply_otp(tp);
1889 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1890 tg3_phy_toggle_apd(tp, true);
1892 tg3_phy_toggle_apd(tp, false);
1895 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1896 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1898 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1900 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1903 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1904 tg3_writephy(tp, 0x1c, 0x8d68);
1905 tg3_writephy(tp, 0x1c, 0x8d68);
1907 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1910 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1911 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1912 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1915 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1917 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1918 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1919 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1920 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1921 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1922 tg3_writephy(tp, MII_TG3_TEST1,
1923 MII_TG3_TEST1_TRIM_EN | 0x4);
1925 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1926 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1928 /* Set Extended packet length bit (bit 14) on all chips that */
1929 /* support jumbo frames */
1930 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1931 /* Cannot do read-modify-write on 5401 */
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1933 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1936 /* Set bit 14 with read-modify-write to preserve other bits */
1937 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1938 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1942 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1943 * jumbo frames transmission.
1945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1948 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1949 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1950 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1954 /* adjust output voltage */
1955 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1958 tg3_phy_toggle_automdix(tp, 1);
1959 tg3_phy_set_wirespeed(tp);
1963 static void tg3_frob_aux_power(struct tg3 *tp)
1965 struct tg3 *tp_peer = tp;
1967 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1970 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1971 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1972 struct net_device *dev_peer;
1974 dev_peer = pci_get_drvdata(tp->pdev_peer);
1975 /* remove_one() may have been run on the peer. */
1979 tp_peer = netdev_priv(dev_peer);
1982 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1983 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1984 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1985 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1988 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1989 (GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT0 |
1993 GRC_LCLCTRL_GPIO_OUTPUT1),
1995 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1996 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1997 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1998 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1999 GRC_LCLCTRL_GPIO_OE1 |
2000 GRC_LCLCTRL_GPIO_OE2 |
2001 GRC_LCLCTRL_GPIO_OUTPUT0 |
2002 GRC_LCLCTRL_GPIO_OUTPUT1 |
2004 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2007 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2009 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2010 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2013 u32 grc_local_ctrl = 0;
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2019 /* Workaround to prevent overdrawing Amps. */
2020 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2022 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 grc_local_ctrl, 100);
2027 /* On 5753 and variants, GPIO2 cannot be used. */
2028 no_gpio2 = tp->nic_sram_data_cfg &
2029 NIC_SRAM_DATA_CFG_NO_GPIO2;
2031 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2032 GRC_LCLCTRL_GPIO_OE1 |
2033 GRC_LCLCTRL_GPIO_OE2 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 GRC_LCLCTRL_GPIO_OUTPUT2;
2037 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2038 GRC_LCLCTRL_GPIO_OUTPUT2);
2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 grc_local_ctrl, 100);
2043 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2045 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2046 grc_local_ctrl, 100);
2049 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2050 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2051 grc_local_ctrl, 100);
2055 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2056 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2057 if (tp_peer != tp &&
2058 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2061 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2062 (GRC_LCLCTRL_GPIO_OE1 |
2063 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2065 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2066 GRC_LCLCTRL_GPIO_OE1, 100);
2068 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2069 (GRC_LCLCTRL_GPIO_OE1 |
2070 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2075 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2077 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2079 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2080 if (speed != SPEED_10)
2082 } else if (speed == SPEED_10)
2088 static int tg3_setup_phy(struct tg3 *, int);
2090 #define RESET_KIND_SHUTDOWN 0
2091 #define RESET_KIND_INIT 1
2092 #define RESET_KIND_SUSPEND 2
2094 static void tg3_write_sig_post_reset(struct tg3 *, int);
2095 static int tg3_halt_cpu(struct tg3 *, u32);
2097 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2103 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2104 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2107 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2108 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2109 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2114 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2116 val = tr32(GRC_MISC_CFG);
2117 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2120 } else if (do_low_power) {
2121 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2122 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2124 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2126 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2127 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2128 MII_TG3_AUXCTL_PCTL_VREG_11V);
2131 /* The PHY should not be powered down on some chips because
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2137 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2140 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2141 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2142 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2143 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2144 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2145 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2148 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2151 /* tp->lock is held. */
2152 static int tg3_nvram_lock(struct tg3 *tp)
2154 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2157 if (tp->nvram_lock_cnt == 0) {
2158 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2159 for (i = 0; i < 8000; i++) {
2160 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2165 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2169 tp->nvram_lock_cnt++;
2174 /* tp->lock is held. */
2175 static void tg3_nvram_unlock(struct tg3 *tp)
2177 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2178 if (tp->nvram_lock_cnt > 0)
2179 tp->nvram_lock_cnt--;
2180 if (tp->nvram_lock_cnt == 0)
2181 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2185 /* tp->lock is held. */
2186 static void tg3_enable_nvram_access(struct tg3 *tp)
2188 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2189 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2190 u32 nvaccess = tr32(NVRAM_ACCESS);
2192 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2196 /* tp->lock is held. */
2197 static void tg3_disable_nvram_access(struct tg3 *tp)
2199 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2200 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2201 u32 nvaccess = tr32(NVRAM_ACCESS);
2203 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2207 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2208 u32 offset, u32 *val)
2213 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2216 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2217 EEPROM_ADDR_DEVID_MASK |
2219 tw32(GRC_EEPROM_ADDR,
2221 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2222 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2223 EEPROM_ADDR_ADDR_MASK) |
2224 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2226 for (i = 0; i < 1000; i++) {
2227 tmp = tr32(GRC_EEPROM_ADDR);
2229 if (tmp & EEPROM_ADDR_COMPLETE)
2233 if (!(tmp & EEPROM_ADDR_COMPLETE))
2236 tmp = tr32(GRC_EEPROM_DATA);
2239 * The data will always be opposite the native endian
2240 * format. Perform a blind byteswap to compensate.
2247 #define NVRAM_CMD_TIMEOUT 10000
2249 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2253 tw32(NVRAM_CMD, nvram_cmd);
2254 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2256 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2262 if (i == NVRAM_CMD_TIMEOUT)
2268 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2270 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2271 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2272 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2274 (tp->nvram_jedecnum == JEDEC_ATMEL))
2276 addr = ((addr / tp->nvram_pagesize) <<
2277 ATMEL_AT45DB0X1B_PAGE_POS) +
2278 (addr % tp->nvram_pagesize);
2283 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2285 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2286 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2287 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2288 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2289 (tp->nvram_jedecnum == JEDEC_ATMEL))
2291 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2292 tp->nvram_pagesize) +
2293 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2298 /* NOTE: Data read in from NVRAM is byteswapped according to
2299 * the byteswapping settings for all other register accesses.
2300 * tg3 devices are BE devices, so on a BE machine, the data
2301 * returned will be exactly as it is seen in NVRAM. On a LE
2302 * machine, the 32-bit value will be byteswapped.
2304 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2308 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2309 return tg3_nvram_read_using_eeprom(tp, offset, val);
2311 offset = tg3_nvram_phys_addr(tp, offset);
2313 if (offset > NVRAM_ADDR_MSK)
2316 ret = tg3_nvram_lock(tp);
2320 tg3_enable_nvram_access(tp);
2322 tw32(NVRAM_ADDR, offset);
2323 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2324 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2327 *val = tr32(NVRAM_RDDATA);
2329 tg3_disable_nvram_access(tp);
2331 tg3_nvram_unlock(tp);
2336 /* Ensures NVRAM data is in bytestream format. */
2337 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2340 int res = tg3_nvram_read(tp, offset, &v);
2342 *val = cpu_to_be32(v);
2346 /* tp->lock is held. */
2347 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2349 u32 addr_high, addr_low;
2352 addr_high = ((tp->dev->dev_addr[0] << 8) |
2353 tp->dev->dev_addr[1]);
2354 addr_low = ((tp->dev->dev_addr[2] << 24) |
2355 (tp->dev->dev_addr[3] << 16) |
2356 (tp->dev->dev_addr[4] << 8) |
2357 (tp->dev->dev_addr[5] << 0));
2358 for (i = 0; i < 4; i++) {
2359 if (i == 1 && skip_mac_1)
2361 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2362 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2365 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2367 for (i = 0; i < 12; i++) {
2368 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2369 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2373 addr_high = (tp->dev->dev_addr[0] +
2374 tp->dev->dev_addr[1] +
2375 tp->dev->dev_addr[2] +
2376 tp->dev->dev_addr[3] +
2377 tp->dev->dev_addr[4] +
2378 tp->dev->dev_addr[5]) &
2379 TX_BACKOFF_SEED_MASK;
2380 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2383 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2386 bool device_should_wake, do_low_power;
2388 /* Make sure register accesses (indirect or otherwise)
2389 * will function correctly.
2391 pci_write_config_dword(tp->pdev,
2392 TG3PCI_MISC_HOST_CTRL,
2393 tp->misc_host_ctrl);
2397 pci_enable_wake(tp->pdev, state, false);
2398 pci_set_power_state(tp->pdev, PCI_D0);
2400 /* Switch out of Vaux if it is a NIC */
2401 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2402 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2412 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2413 tp->dev->name, state);
2417 /* Restore the CLKREQ setting. */
2418 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2421 pci_read_config_word(tp->pdev,
2422 tp->pcie_cap + PCI_EXP_LNKCTL,
2424 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2425 pci_write_config_word(tp->pdev,
2426 tp->pcie_cap + PCI_EXP_LNKCTL,
2430 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2431 tw32(TG3PCI_MISC_HOST_CTRL,
2432 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2434 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2435 device_may_wakeup(&tp->pdev->dev) &&
2436 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2438 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2439 do_low_power = false;
2440 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2441 !tp->link_config.phy_is_low_power) {
2442 struct phy_device *phydev;
2443 u32 phyid, advertising;
2445 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2447 tp->link_config.phy_is_low_power = 1;
2449 tp->link_config.orig_speed = phydev->speed;
2450 tp->link_config.orig_duplex = phydev->duplex;
2451 tp->link_config.orig_autoneg = phydev->autoneg;
2452 tp->link_config.orig_advertising = phydev->advertising;
2454 advertising = ADVERTISED_TP |
2456 ADVERTISED_Autoneg |
2457 ADVERTISED_10baseT_Half;
2459 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2460 device_should_wake) {
2461 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2463 ADVERTISED_100baseT_Half |
2464 ADVERTISED_100baseT_Full |
2465 ADVERTISED_10baseT_Full;
2467 advertising |= ADVERTISED_10baseT_Full;
2470 phydev->advertising = advertising;
2472 phy_start_aneg(phydev);
2474 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2475 if (phyid != TG3_PHY_ID_BCMAC131) {
2476 phyid &= TG3_PHY_OUI_MASK;
2477 if (phyid == TG3_PHY_OUI_1 ||
2478 phyid == TG3_PHY_OUI_2 ||
2479 phyid == TG3_PHY_OUI_3)
2480 do_low_power = true;
2484 do_low_power = true;
2486 if (tp->link_config.phy_is_low_power == 0) {
2487 tp->link_config.phy_is_low_power = 1;
2488 tp->link_config.orig_speed = tp->link_config.speed;
2489 tp->link_config.orig_duplex = tp->link_config.duplex;
2490 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2493 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2494 tp->link_config.speed = SPEED_10;
2495 tp->link_config.duplex = DUPLEX_HALF;
2496 tp->link_config.autoneg = AUTONEG_ENABLE;
2497 tg3_setup_phy(tp, 0);
2501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2504 val = tr32(GRC_VCPU_EXT_CTRL);
2505 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2506 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2510 for (i = 0; i < 200; i++) {
2511 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2512 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2517 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2518 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2519 WOL_DRV_STATE_SHUTDOWN |
2523 if (device_should_wake) {
2526 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2528 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2532 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2533 mac_mode = MAC_MODE_PORT_MODE_GMII;
2535 mac_mode = MAC_MODE_PORT_MODE_MII;
2537 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2538 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2540 u32 speed = (tp->tg3_flags &
2541 TG3_FLAG_WOL_SPEED_100MB) ?
2542 SPEED_100 : SPEED_10;
2543 if (tg3_5700_link_polarity(tp, speed))
2544 mac_mode |= MAC_MODE_LINK_POLARITY;
2546 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2549 mac_mode = MAC_MODE_PORT_MODE_TBI;
2552 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2553 tw32(MAC_LED_CTRL, tp->led_ctrl);
2555 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2556 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2557 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2558 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2559 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2560 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2562 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2563 mac_mode |= tp->mac_mode &
2564 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2565 if (mac_mode & MAC_MODE_APE_TX_EN)
2566 mac_mode |= MAC_MODE_TDE_ENABLE;
2569 tw32_f(MAC_MODE, mac_mode);
2572 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2576 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2577 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2581 base_val = tp->pci_clock_ctrl;
2582 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2583 CLOCK_CTRL_TXCLK_DISABLE);
2585 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2586 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2587 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2588 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2591 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2592 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2593 u32 newbits1, newbits2;
2595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2597 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2598 CLOCK_CTRL_TXCLK_DISABLE |
2600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2601 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2602 newbits1 = CLOCK_CTRL_625_CORE;
2603 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2605 newbits1 = CLOCK_CTRL_ALTCLK;
2606 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2609 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2612 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2615 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2620 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2621 CLOCK_CTRL_TXCLK_DISABLE |
2622 CLOCK_CTRL_44MHZ_CORE);
2624 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2627 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2628 tp->pci_clock_ctrl | newbits3, 40);
2632 if (!(device_should_wake) &&
2633 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2634 tg3_power_down_phy(tp, do_low_power);
2636 tg3_frob_aux_power(tp);
2638 /* Workaround for unstable PLL clock */
2639 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2640 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2641 u32 val = tr32(0x7d00);
2643 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2645 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2648 err = tg3_nvram_lock(tp);
2649 tg3_halt_cpu(tp, RX_CPU_BASE);
2651 tg3_nvram_unlock(tp);
2655 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2657 if (device_should_wake)
2658 pci_enable_wake(tp->pdev, state, true);
2660 /* Finally, set the new power state. */
2661 pci_set_power_state(tp->pdev, state);
2666 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2668 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2669 case MII_TG3_AUX_STAT_10HALF:
2671 *duplex = DUPLEX_HALF;
2674 case MII_TG3_AUX_STAT_10FULL:
2676 *duplex = DUPLEX_FULL;
2679 case MII_TG3_AUX_STAT_100HALF:
2681 *duplex = DUPLEX_HALF;
2684 case MII_TG3_AUX_STAT_100FULL:
2686 *duplex = DUPLEX_FULL;
2689 case MII_TG3_AUX_STAT_1000HALF:
2690 *speed = SPEED_1000;
2691 *duplex = DUPLEX_HALF;
2694 case MII_TG3_AUX_STAT_1000FULL:
2695 *speed = SPEED_1000;
2696 *duplex = DUPLEX_FULL;
2700 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2701 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2703 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2707 *speed = SPEED_INVALID;
2708 *duplex = DUPLEX_INVALID;
2713 static void tg3_phy_copper_begin(struct tg3 *tp)
2718 if (tp->link_config.phy_is_low_power) {
2719 /* Entering low power mode. Disable gigabit and
2720 * 100baseT advertisements.
2722 tg3_writephy(tp, MII_TG3_CTRL, 0);
2724 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2725 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2726 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2727 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2729 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2730 } else if (tp->link_config.speed == SPEED_INVALID) {
2731 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2732 tp->link_config.advertising &=
2733 ~(ADVERTISED_1000baseT_Half |
2734 ADVERTISED_1000baseT_Full);
2736 new_adv = ADVERTISE_CSMA;
2737 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2738 new_adv |= ADVERTISE_10HALF;
2739 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2740 new_adv |= ADVERTISE_10FULL;
2741 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2742 new_adv |= ADVERTISE_100HALF;
2743 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2744 new_adv |= ADVERTISE_100FULL;
2746 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2748 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2750 if (tp->link_config.advertising &
2751 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2753 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2754 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2755 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2756 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2757 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2758 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2759 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2760 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2761 MII_TG3_CTRL_ENABLE_AS_MASTER);
2762 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2764 tg3_writephy(tp, MII_TG3_CTRL, 0);
2767 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2768 new_adv |= ADVERTISE_CSMA;
2770 /* Asking for a specific link mode. */
2771 if (tp->link_config.speed == SPEED_1000) {
2772 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2774 if (tp->link_config.duplex == DUPLEX_FULL)
2775 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2777 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2778 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2780 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2781 MII_TG3_CTRL_ENABLE_AS_MASTER);
2783 if (tp->link_config.speed == SPEED_100) {
2784 if (tp->link_config.duplex == DUPLEX_FULL)
2785 new_adv |= ADVERTISE_100FULL;
2787 new_adv |= ADVERTISE_100HALF;
2789 if (tp->link_config.duplex == DUPLEX_FULL)
2790 new_adv |= ADVERTISE_10FULL;
2792 new_adv |= ADVERTISE_10HALF;
2794 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2802 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2803 tp->link_config.speed != SPEED_INVALID) {
2804 u32 bmcr, orig_bmcr;
2806 tp->link_config.active_speed = tp->link_config.speed;
2807 tp->link_config.active_duplex = tp->link_config.duplex;
2810 switch (tp->link_config.speed) {
2816 bmcr |= BMCR_SPEED100;
2820 bmcr |= TG3_BMCR_SPEED1000;
2824 if (tp->link_config.duplex == DUPLEX_FULL)
2825 bmcr |= BMCR_FULLDPLX;
2827 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2828 (bmcr != orig_bmcr)) {
2829 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2830 for (i = 0; i < 1500; i++) {
2834 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2835 tg3_readphy(tp, MII_BMSR, &tmp))
2837 if (!(tmp & BMSR_LSTATUS)) {
2842 tg3_writephy(tp, MII_BMCR, bmcr);
2846 tg3_writephy(tp, MII_BMCR,
2847 BMCR_ANENABLE | BMCR_ANRESTART);
2851 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2855 /* Turn off tap power management. */
2856 /* Set Extended packet length bit */
2857 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2859 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2860 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2862 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2863 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2865 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2866 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2868 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2869 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2871 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2872 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2879 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2881 u32 adv_reg, all_mask = 0;
2883 if (mask & ADVERTISED_10baseT_Half)
2884 all_mask |= ADVERTISE_10HALF;
2885 if (mask & ADVERTISED_10baseT_Full)
2886 all_mask |= ADVERTISE_10FULL;
2887 if (mask & ADVERTISED_100baseT_Half)
2888 all_mask |= ADVERTISE_100HALF;
2889 if (mask & ADVERTISED_100baseT_Full)
2890 all_mask |= ADVERTISE_100FULL;
2892 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2895 if ((adv_reg & all_mask) != all_mask)
2897 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2901 if (mask & ADVERTISED_1000baseT_Half)
2902 all_mask |= ADVERTISE_1000HALF;
2903 if (mask & ADVERTISED_1000baseT_Full)
2904 all_mask |= ADVERTISE_1000FULL;
2906 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2909 if ((tg3_ctrl & all_mask) != all_mask)
2915 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2919 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2922 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2923 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2925 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2926 if (curadv != reqadv)
2929 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2930 tg3_readphy(tp, MII_LPA, rmtadv);
2932 /* Reprogram the advertisement register, even if it
2933 * does not affect the current link. If the link
2934 * gets renegotiated in the future, we can save an
2935 * additional renegotiation cycle by advertising
2936 * it correctly in the first place.
2938 if (curadv != reqadv) {
2939 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2940 ADVERTISE_PAUSE_ASYM);
2941 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2948 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2950 int current_link_up;
2952 u32 lcl_adv, rmt_adv;
2960 (MAC_STATUS_SYNC_CHANGED |
2961 MAC_STATUS_CFG_CHANGED |
2962 MAC_STATUS_MI_COMPLETION |
2963 MAC_STATUS_LNKSTATE_CHANGED));
2966 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2968 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2974 /* Some third-party PHYs need to be reset on link going
2977 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2980 netif_carrier_ok(tp->dev)) {
2981 tg3_readphy(tp, MII_BMSR, &bmsr);
2982 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2983 !(bmsr & BMSR_LSTATUS))
2989 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2990 tg3_readphy(tp, MII_BMSR, &bmsr);
2991 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2992 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2995 if (!(bmsr & BMSR_LSTATUS)) {
2996 err = tg3_init_5401phy_dsp(tp);
3000 tg3_readphy(tp, MII_BMSR, &bmsr);
3001 for (i = 0; i < 1000; i++) {
3003 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3004 (bmsr & BMSR_LSTATUS)) {
3010 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3011 !(bmsr & BMSR_LSTATUS) &&
3012 tp->link_config.active_speed == SPEED_1000) {
3013 err = tg3_phy_reset(tp);
3015 err = tg3_init_5401phy_dsp(tp);
3020 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3021 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3022 /* 5701 {A0,B0} CRC bug workaround */
3023 tg3_writephy(tp, 0x15, 0x0a75);
3024 tg3_writephy(tp, 0x1c, 0x8c68);
3025 tg3_writephy(tp, 0x1c, 0x8d68);
3026 tg3_writephy(tp, 0x1c, 0x8c68);
3029 /* Clear pending interrupts... */
3030 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3031 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3033 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3034 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3035 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3036 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3040 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3041 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3042 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3044 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3047 current_link_up = 0;
3048 current_speed = SPEED_INVALID;
3049 current_duplex = DUPLEX_INVALID;
3051 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3055 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3056 if (!(val & (1 << 10))) {
3058 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3064 for (i = 0; i < 100; i++) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 (bmsr & BMSR_LSTATUS))
3072 if (bmsr & BMSR_LSTATUS) {
3075 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3076 for (i = 0; i < 2000; i++) {
3078 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3083 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3088 for (i = 0; i < 200; i++) {
3089 tg3_readphy(tp, MII_BMCR, &bmcr);
3090 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3092 if (bmcr && bmcr != 0x7fff)
3100 tp->link_config.active_speed = current_speed;
3101 tp->link_config.active_duplex = current_duplex;
3103 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3104 if ((bmcr & BMCR_ANENABLE) &&
3105 tg3_copper_is_advertising_all(tp,
3106 tp->link_config.advertising)) {
3107 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3109 current_link_up = 1;
3112 if (!(bmcr & BMCR_ANENABLE) &&
3113 tp->link_config.speed == current_speed &&
3114 tp->link_config.duplex == current_duplex &&
3115 tp->link_config.flowctrl ==
3116 tp->link_config.active_flowctrl) {
3117 current_link_up = 1;
3121 if (current_link_up == 1 &&
3122 tp->link_config.active_duplex == DUPLEX_FULL)
3123 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3127 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3130 tg3_phy_copper_begin(tp);
3132 tg3_readphy(tp, MII_BMSR, &tmp);
3133 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3134 (tmp & BMSR_LSTATUS))
3135 current_link_up = 1;
3138 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3139 if (current_link_up == 1) {
3140 if (tp->link_config.active_speed == SPEED_100 ||
3141 tp->link_config.active_speed == SPEED_10)
3142 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3144 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3145 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3146 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3148 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3150 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3151 if (tp->link_config.active_duplex == DUPLEX_HALF)
3152 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3155 if (current_link_up == 1 &&
3156 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3157 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3159 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3162 /* ??? Without this setting Netgear GA302T PHY does not
3163 * ??? send/receive packets...
3165 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3166 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3167 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3168 tw32_f(MAC_MI_MODE, tp->mi_mode);
3172 tw32_f(MAC_MODE, tp->mac_mode);
3175 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3176 /* Polled via timer. */
3177 tw32_f(MAC_EVENT, 0);
3179 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3183 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3184 current_link_up == 1 &&
3185 tp->link_config.active_speed == SPEED_1000 &&
3186 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3187 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3190 (MAC_STATUS_SYNC_CHANGED |
3191 MAC_STATUS_CFG_CHANGED));
3194 NIC_SRAM_FIRMWARE_MBOX,
3195 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3198 /* Prevent send BD corruption. */
3199 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3200 u16 oldlnkctl, newlnkctl;
3202 pci_read_config_word(tp->pdev,
3203 tp->pcie_cap + PCI_EXP_LNKCTL,
3205 if (tp->link_config.active_speed == SPEED_100 ||
3206 tp->link_config.active_speed == SPEED_10)
3207 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3209 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3210 if (newlnkctl != oldlnkctl)
3211 pci_write_config_word(tp->pdev,
3212 tp->pcie_cap + PCI_EXP_LNKCTL,
3214 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3215 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3216 if (tp->link_config.active_speed == SPEED_100 ||
3217 tp->link_config.active_speed == SPEED_10)
3218 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3220 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3221 if (newreg != oldreg)
3222 tw32(TG3_PCIE_LNKCTL, newreg);
3225 if (current_link_up != netif_carrier_ok(tp->dev)) {
3226 if (current_link_up)
3227 netif_carrier_on(tp->dev);
3229 netif_carrier_off(tp->dev);
3230 tg3_link_report(tp);
3236 struct tg3_fiber_aneginfo {
3238 #define ANEG_STATE_UNKNOWN 0
3239 #define ANEG_STATE_AN_ENABLE 1
3240 #define ANEG_STATE_RESTART_INIT 2
3241 #define ANEG_STATE_RESTART 3
3242 #define ANEG_STATE_DISABLE_LINK_OK 4
3243 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3244 #define ANEG_STATE_ABILITY_DETECT 6
3245 #define ANEG_STATE_ACK_DETECT_INIT 7
3246 #define ANEG_STATE_ACK_DETECT 8
3247 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3248 #define ANEG_STATE_COMPLETE_ACK 10
3249 #define ANEG_STATE_IDLE_DETECT_INIT 11
3250 #define ANEG_STATE_IDLE_DETECT 12
3251 #define ANEG_STATE_LINK_OK 13
3252 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3253 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3256 #define MR_AN_ENABLE 0x00000001
3257 #define MR_RESTART_AN 0x00000002
3258 #define MR_AN_COMPLETE 0x00000004
3259 #define MR_PAGE_RX 0x00000008
3260 #define MR_NP_LOADED 0x00000010
3261 #define MR_TOGGLE_TX 0x00000020
3262 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3263 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3264 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3265 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3266 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3267 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3268 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3269 #define MR_TOGGLE_RX 0x00002000
3270 #define MR_NP_RX 0x00004000
3272 #define MR_LINK_OK 0x80000000
3274 unsigned long link_time, cur_time;
3276 u32 ability_match_cfg;
3277 int ability_match_count;
3279 char ability_match, idle_match, ack_match;
3281 u32 txconfig, rxconfig;
3282 #define ANEG_CFG_NP 0x00000080
3283 #define ANEG_CFG_ACK 0x00000040
3284 #define ANEG_CFG_RF2 0x00000020
3285 #define ANEG_CFG_RF1 0x00000010
3286 #define ANEG_CFG_PS2 0x00000001
3287 #define ANEG_CFG_PS1 0x00008000
3288 #define ANEG_CFG_HD 0x00004000
3289 #define ANEG_CFG_FD 0x00002000
3290 #define ANEG_CFG_INVAL 0x00001f06
3295 #define ANEG_TIMER_ENAB 2
3296 #define ANEG_FAILED -1
3298 #define ANEG_STATE_SETTLE_TIME 10000
3300 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3301 struct tg3_fiber_aneginfo *ap)
3304 unsigned long delta;
3308 if (ap->state == ANEG_STATE_UNKNOWN) {
3312 ap->ability_match_cfg = 0;
3313 ap->ability_match_count = 0;
3314 ap->ability_match = 0;
3320 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3321 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3323 if (rx_cfg_reg != ap->ability_match_cfg) {
3324 ap->ability_match_cfg = rx_cfg_reg;
3325 ap->ability_match = 0;
3326 ap->ability_match_count = 0;
3328 if (++ap->ability_match_count > 1) {
3329 ap->ability_match = 1;
3330 ap->ability_match_cfg = rx_cfg_reg;
3333 if (rx_cfg_reg & ANEG_CFG_ACK)
3341 ap->ability_match_cfg = 0;
3342 ap->ability_match_count = 0;
3343 ap->ability_match = 0;
3349 ap->rxconfig = rx_cfg_reg;
3353 case ANEG_STATE_UNKNOWN:
3354 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3355 ap->state = ANEG_STATE_AN_ENABLE;
3358 case ANEG_STATE_AN_ENABLE:
3359 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3360 if (ap->flags & MR_AN_ENABLE) {
3363 ap->ability_match_cfg = 0;
3364 ap->ability_match_count = 0;
3365 ap->ability_match = 0;
3369 ap->state = ANEG_STATE_RESTART_INIT;
3371 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3375 case ANEG_STATE_RESTART_INIT:
3376 ap->link_time = ap->cur_time;
3377 ap->flags &= ~(MR_NP_LOADED);
3379 tw32(MAC_TX_AUTO_NEG, 0);
3380 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3381 tw32_f(MAC_MODE, tp->mac_mode);
3384 ret = ANEG_TIMER_ENAB;
3385 ap->state = ANEG_STATE_RESTART;
3388 case ANEG_STATE_RESTART:
3389 delta = ap->cur_time - ap->link_time;
3390 if (delta > ANEG_STATE_SETTLE_TIME) {
3391 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3393 ret = ANEG_TIMER_ENAB;
3397 case ANEG_STATE_DISABLE_LINK_OK:
3401 case ANEG_STATE_ABILITY_DETECT_INIT:
3402 ap->flags &= ~(MR_TOGGLE_TX);
3403 ap->txconfig = ANEG_CFG_FD;
3404 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3405 if (flowctrl & ADVERTISE_1000XPAUSE)
3406 ap->txconfig |= ANEG_CFG_PS1;
3407 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3408 ap->txconfig |= ANEG_CFG_PS2;
3409 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3410 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3411 tw32_f(MAC_MODE, tp->mac_mode);
3414 ap->state = ANEG_STATE_ABILITY_DETECT;
3417 case ANEG_STATE_ABILITY_DETECT:
3418 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3419 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3423 case ANEG_STATE_ACK_DETECT_INIT:
3424 ap->txconfig |= ANEG_CFG_ACK;
3425 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3426 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3427 tw32_f(MAC_MODE, tp->mac_mode);
3430 ap->state = ANEG_STATE_ACK_DETECT;
3433 case ANEG_STATE_ACK_DETECT:
3434 if (ap->ack_match != 0) {
3435 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3436 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3437 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3439 ap->state = ANEG_STATE_AN_ENABLE;
3441 } else if (ap->ability_match != 0 &&
3442 ap->rxconfig == 0) {
3443 ap->state = ANEG_STATE_AN_ENABLE;
3447 case ANEG_STATE_COMPLETE_ACK_INIT:
3448 if (ap->rxconfig & ANEG_CFG_INVAL) {
3452 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3453 MR_LP_ADV_HALF_DUPLEX |
3454 MR_LP_ADV_SYM_PAUSE |
3455 MR_LP_ADV_ASYM_PAUSE |
3456 MR_LP_ADV_REMOTE_FAULT1 |
3457 MR_LP_ADV_REMOTE_FAULT2 |
3458 MR_LP_ADV_NEXT_PAGE |
3461 if (ap->rxconfig & ANEG_CFG_FD)
3462 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3463 if (ap->rxconfig & ANEG_CFG_HD)
3464 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3465 if (ap->rxconfig & ANEG_CFG_PS1)
3466 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3467 if (ap->rxconfig & ANEG_CFG_PS2)
3468 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3469 if (ap->rxconfig & ANEG_CFG_RF1)
3470 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3471 if (ap->rxconfig & ANEG_CFG_RF2)
3472 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3473 if (ap->rxconfig & ANEG_CFG_NP)
3474 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3476 ap->link_time = ap->cur_time;
3478 ap->flags ^= (MR_TOGGLE_TX);
3479 if (ap->rxconfig & 0x0008)
3480 ap->flags |= MR_TOGGLE_RX;
3481 if (ap->rxconfig & ANEG_CFG_NP)
3482 ap->flags |= MR_NP_RX;
3483 ap->flags |= MR_PAGE_RX;
3485 ap->state = ANEG_STATE_COMPLETE_ACK;
3486 ret = ANEG_TIMER_ENAB;
3489 case ANEG_STATE_COMPLETE_ACK:
3490 if (ap->ability_match != 0 &&
3491 ap->rxconfig == 0) {
3492 ap->state = ANEG_STATE_AN_ENABLE;
3495 delta = ap->cur_time - ap->link_time;
3496 if (delta > ANEG_STATE_SETTLE_TIME) {
3497 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3498 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3500 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3501 !(ap->flags & MR_NP_RX)) {
3502 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3510 case ANEG_STATE_IDLE_DETECT_INIT:
3511 ap->link_time = ap->cur_time;
3512 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3513 tw32_f(MAC_MODE, tp->mac_mode);
3516 ap->state = ANEG_STATE_IDLE_DETECT;
3517 ret = ANEG_TIMER_ENAB;
3520 case ANEG_STATE_IDLE_DETECT:
3521 if (ap->ability_match != 0 &&
3522 ap->rxconfig == 0) {
3523 ap->state = ANEG_STATE_AN_ENABLE;
3526 delta = ap->cur_time - ap->link_time;
3527 if (delta > ANEG_STATE_SETTLE_TIME) {
3528 /* XXX another gem from the Broadcom driver :( */
3529 ap->state = ANEG_STATE_LINK_OK;
3533 case ANEG_STATE_LINK_OK:
3534 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3538 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3539 /* ??? unimplemented */
3542 case ANEG_STATE_NEXT_PAGE_WAIT:
3543 /* ??? unimplemented */
3554 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3557 struct tg3_fiber_aneginfo aninfo;
3558 int status = ANEG_FAILED;
3562 tw32_f(MAC_TX_AUTO_NEG, 0);
3564 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3565 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3568 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3571 memset(&aninfo, 0, sizeof(aninfo));
3572 aninfo.flags |= MR_AN_ENABLE;
3573 aninfo.state = ANEG_STATE_UNKNOWN;
3574 aninfo.cur_time = 0;
3576 while (++tick < 195000) {
3577 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3578 if (status == ANEG_DONE || status == ANEG_FAILED)
3584 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3585 tw32_f(MAC_MODE, tp->mac_mode);
3588 *txflags = aninfo.txconfig;
3589 *rxflags = aninfo.flags;
3591 if (status == ANEG_DONE &&
3592 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3593 MR_LP_ADV_FULL_DUPLEX)))
3599 static void tg3_init_bcm8002(struct tg3 *tp)
3601 u32 mac_status = tr32(MAC_STATUS);
3604 /* Reset when initting first time or we have a link. */
3605 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3606 !(mac_status & MAC_STATUS_PCS_SYNCED))
3609 /* Set PLL lock range. */
3610 tg3_writephy(tp, 0x16, 0x8007);
3613 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3615 /* Wait for reset to complete. */
3616 /* XXX schedule_timeout() ... */
3617 for (i = 0; i < 500; i++)
3620 /* Config mode; select PMA/Ch 1 regs. */
3621 tg3_writephy(tp, 0x10, 0x8411);
3623 /* Enable auto-lock and comdet, select txclk for tx. */
3624 tg3_writephy(tp, 0x11, 0x0a10);
3626 tg3_writephy(tp, 0x18, 0x00a0);
3627 tg3_writephy(tp, 0x16, 0x41ff);
3629 /* Assert and deassert POR. */
3630 tg3_writephy(tp, 0x13, 0x0400);
3632 tg3_writephy(tp, 0x13, 0x0000);
3634 tg3_writephy(tp, 0x11, 0x0a50);
3636 tg3_writephy(tp, 0x11, 0x0a10);
3638 /* Wait for signal to stabilize */
3639 /* XXX schedule_timeout() ... */
3640 for (i = 0; i < 15000; i++)
3643 /* Deselect the channel register so we can read the PHYID
3646 tg3_writephy(tp, 0x10, 0x8011);
3649 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3652 u32 sg_dig_ctrl, sg_dig_status;
3653 u32 serdes_cfg, expected_sg_dig_ctrl;
3654 int workaround, port_a;
3655 int current_link_up;
3658 expected_sg_dig_ctrl = 0;
3661 current_link_up = 0;
3663 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3664 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3666 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3669 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3670 /* preserve bits 20-23 for voltage regulator */
3671 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3674 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3676 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3677 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3679 u32 val = serdes_cfg;
3685 tw32_f(MAC_SERDES_CFG, val);
3688 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3690 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3691 tg3_setup_flow_control(tp, 0, 0);
3692 current_link_up = 1;
3697 /* Want auto-negotiation. */
3698 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3700 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3701 if (flowctrl & ADVERTISE_1000XPAUSE)
3702 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3703 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3704 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3706 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3707 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3708 tp->serdes_counter &&
3709 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3710 MAC_STATUS_RCVD_CFG)) ==
3711 MAC_STATUS_PCS_SYNCED)) {
3712 tp->serdes_counter--;
3713 current_link_up = 1;
3718 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3719 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3721 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3723 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3724 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3725 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3726 MAC_STATUS_SIGNAL_DET)) {
3727 sg_dig_status = tr32(SG_DIG_STATUS);
3728 mac_status = tr32(MAC_STATUS);
3730 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3731 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3732 u32 local_adv = 0, remote_adv = 0;
3734 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3735 local_adv |= ADVERTISE_1000XPAUSE;
3736 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3737 local_adv |= ADVERTISE_1000XPSE_ASYM;
3739 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3740 remote_adv |= LPA_1000XPAUSE;
3741 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3742 remote_adv |= LPA_1000XPAUSE_ASYM;
3744 tg3_setup_flow_control(tp, local_adv, remote_adv);
3745 current_link_up = 1;
3746 tp->serdes_counter = 0;
3747 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3748 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3749 if (tp->serdes_counter)
3750 tp->serdes_counter--;
3753 u32 val = serdes_cfg;
3760 tw32_f(MAC_SERDES_CFG, val);
3763 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3766 /* Link parallel detection - link is up */
3767 /* only if we have PCS_SYNC and not */
3768 /* receiving config code words */
3769 mac_status = tr32(MAC_STATUS);
3770 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3771 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3772 tg3_setup_flow_control(tp, 0, 0);
3773 current_link_up = 1;
3775 TG3_FLG2_PARALLEL_DETECT;
3776 tp->serdes_counter =
3777 SERDES_PARALLEL_DET_TIMEOUT;
3779 goto restart_autoneg;
3783 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3788 return current_link_up;
3791 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3793 int current_link_up = 0;
3795 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3798 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3799 u32 txflags, rxflags;
3802 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3803 u32 local_adv = 0, remote_adv = 0;
3805 if (txflags & ANEG_CFG_PS1)
3806 local_adv |= ADVERTISE_1000XPAUSE;
3807 if (txflags & ANEG_CFG_PS2)
3808 local_adv |= ADVERTISE_1000XPSE_ASYM;
3810 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE;
3812 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3813 remote_adv |= LPA_1000XPAUSE_ASYM;
3815 tg3_setup_flow_control(tp, local_adv, remote_adv);
3817 current_link_up = 1;
3819 for (i = 0; i < 30; i++) {
3822 (MAC_STATUS_SYNC_CHANGED |
3823 MAC_STATUS_CFG_CHANGED));
3825 if ((tr32(MAC_STATUS) &
3826 (MAC_STATUS_SYNC_CHANGED |
3827 MAC_STATUS_CFG_CHANGED)) == 0)
3831 mac_status = tr32(MAC_STATUS);
3832 if (current_link_up == 0 &&
3833 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG))
3835 current_link_up = 1;
3837 tg3_setup_flow_control(tp, 0, 0);
3839 /* Forcing 1000FD link up. */
3840 current_link_up = 1;
3842 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3845 tw32_f(MAC_MODE, tp->mac_mode);
3850 return current_link_up;
3853 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3856 u16 orig_active_speed;
3857 u8 orig_active_duplex;
3859 int current_link_up;
3862 orig_pause_cfg = tp->link_config.active_flowctrl;
3863 orig_active_speed = tp->link_config.active_speed;
3864 orig_active_duplex = tp->link_config.active_duplex;
3866 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3867 netif_carrier_ok(tp->dev) &&
3868 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3869 mac_status = tr32(MAC_STATUS);
3870 mac_status &= (MAC_STATUS_PCS_SYNCED |
3871 MAC_STATUS_SIGNAL_DET |
3872 MAC_STATUS_CFG_CHANGED |
3873 MAC_STATUS_RCVD_CFG);
3874 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3875 MAC_STATUS_SIGNAL_DET)) {
3876 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED));
3882 tw32_f(MAC_TX_AUTO_NEG, 0);
3884 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3885 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3886 tw32_f(MAC_MODE, tp->mac_mode);
3889 if (tp->phy_id == PHY_ID_BCM8002)
3890 tg3_init_bcm8002(tp);
3892 /* Enable link change event even when serdes polling. */
3893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3896 current_link_up = 0;
3897 mac_status = tr32(MAC_STATUS);
3899 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3900 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3902 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3904 tp->napi[0].hw_status->status =
3905 (SD_STATUS_UPDATED |
3906 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3908 for (i = 0; i < 100; i++) {
3909 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3910 MAC_STATUS_CFG_CHANGED));
3912 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3913 MAC_STATUS_CFG_CHANGED |
3914 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3918 mac_status = tr32(MAC_STATUS);
3919 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3920 current_link_up = 0;
3921 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3922 tp->serdes_counter == 0) {
3923 tw32_f(MAC_MODE, (tp->mac_mode |
3924 MAC_MODE_SEND_CONFIGS));
3926 tw32_f(MAC_MODE, tp->mac_mode);
3930 if (current_link_up == 1) {
3931 tp->link_config.active_speed = SPEED_1000;
3932 tp->link_config.active_duplex = DUPLEX_FULL;
3933 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3934 LED_CTRL_LNKLED_OVERRIDE |
3935 LED_CTRL_1000MBPS_ON));
3937 tp->link_config.active_speed = SPEED_INVALID;
3938 tp->link_config.active_duplex = DUPLEX_INVALID;
3939 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3940 LED_CTRL_LNKLED_OVERRIDE |
3941 LED_CTRL_TRAFFIC_OVERRIDE));
3944 if (current_link_up != netif_carrier_ok(tp->dev)) {
3945 if (current_link_up)
3946 netif_carrier_on(tp->dev);
3948 netif_carrier_off(tp->dev);
3949 tg3_link_report(tp);
3951 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3952 if (orig_pause_cfg != now_pause_cfg ||
3953 orig_active_speed != tp->link_config.active_speed ||
3954 orig_active_duplex != tp->link_config.active_duplex)
3955 tg3_link_report(tp);
3961 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3963 int current_link_up, err = 0;
3967 u32 local_adv, remote_adv;
3969 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3970 tw32_f(MAC_MODE, tp->mac_mode);
3976 (MAC_STATUS_SYNC_CHANGED |
3977 MAC_STATUS_CFG_CHANGED |
3978 MAC_STATUS_MI_COMPLETION |
3979 MAC_STATUS_LNKSTATE_CHANGED));
3985 current_link_up = 0;
3986 current_speed = SPEED_INVALID;
3987 current_duplex = DUPLEX_INVALID;
3989 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3990 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3992 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3993 bmsr |= BMSR_LSTATUS;
3995 bmsr &= ~BMSR_LSTATUS;
3998 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4000 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4001 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4002 /* do nothing, just check for link up at the end */
4003 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4006 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4007 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4008 ADVERTISE_1000XPAUSE |
4009 ADVERTISE_1000XPSE_ASYM |
4012 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4014 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4015 new_adv |= ADVERTISE_1000XHALF;
4016 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4017 new_adv |= ADVERTISE_1000XFULL;
4019 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4020 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4021 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4022 tg3_writephy(tp, MII_BMCR, bmcr);
4024 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4025 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4033 bmcr &= ~BMCR_SPEED1000;
4034 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4036 if (tp->link_config.duplex == DUPLEX_FULL)
4037 new_bmcr |= BMCR_FULLDPLX;
4039 if (new_bmcr != bmcr) {
4040 /* BMCR_SPEED1000 is a reserved bit that needs
4041 * to be set on write.
4043 new_bmcr |= BMCR_SPEED1000;
4045 /* Force a linkdown */
4046 if (netif_carrier_ok(tp->dev)) {
4049 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4050 adv &= ~(ADVERTISE_1000XFULL |
4051 ADVERTISE_1000XHALF |
4053 tg3_writephy(tp, MII_ADVERTISE, adv);
4054 tg3_writephy(tp, MII_BMCR, bmcr |
4058 netif_carrier_off(tp->dev);
4060 tg3_writephy(tp, MII_BMCR, new_bmcr);
4062 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4063 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4064 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4066 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4067 bmsr |= BMSR_LSTATUS;
4069 bmsr &= ~BMSR_LSTATUS;
4071 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4075 if (bmsr & BMSR_LSTATUS) {
4076 current_speed = SPEED_1000;
4077 current_link_up = 1;
4078 if (bmcr & BMCR_FULLDPLX)
4079 current_duplex = DUPLEX_FULL;
4081 current_duplex = DUPLEX_HALF;
4086 if (bmcr & BMCR_ANENABLE) {
4089 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4090 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4091 common = local_adv & remote_adv;
4092 if (common & (ADVERTISE_1000XHALF |
4093 ADVERTISE_1000XFULL)) {
4094 if (common & ADVERTISE_1000XFULL)
4095 current_duplex = DUPLEX_FULL;
4097 current_duplex = DUPLEX_HALF;
4100 current_link_up = 0;
4104 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4105 tg3_setup_flow_control(tp, local_adv, remote_adv);
4107 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4108 if (tp->link_config.active_duplex == DUPLEX_HALF)
4109 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4111 tw32_f(MAC_MODE, tp->mac_mode);
4114 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4116 tp->link_config.active_speed = current_speed;
4117 tp->link_config.active_duplex = current_duplex;
4119 if (current_link_up != netif_carrier_ok(tp->dev)) {
4120 if (current_link_up)
4121 netif_carrier_on(tp->dev);
4123 netif_carrier_off(tp->dev);
4124 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126 tg3_link_report(tp);
4131 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4133 if (tp->serdes_counter) {
4134 /* Give autoneg time to complete. */
4135 tp->serdes_counter--;
4138 if (!netif_carrier_ok(tp->dev) &&
4139 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4142 tg3_readphy(tp, MII_BMCR, &bmcr);
4143 if (bmcr & BMCR_ANENABLE) {
4146 /* Select shadow register 0x1f */
4147 tg3_writephy(tp, 0x1c, 0x7c00);
4148 tg3_readphy(tp, 0x1c, &phy1);
4150 /* Select expansion interrupt status register */
4151 tg3_writephy(tp, 0x17, 0x0f01);
4152 tg3_readphy(tp, 0x15, &phy2);
4153 tg3_readphy(tp, 0x15, &phy2);
4155 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4156 /* We have signal detect and not receiving
4157 * config code words, link is up by parallel
4161 bmcr &= ~BMCR_ANENABLE;
4162 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4163 tg3_writephy(tp, MII_BMCR, bmcr);
4164 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4168 else if (netif_carrier_ok(tp->dev) &&
4169 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4170 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp, 0x17, 0x0f01);
4175 tg3_readphy(tp, 0x15, &phy2);
4179 /* Config code words received, turn on autoneg. */
4180 tg3_readphy(tp, MII_BMCR, &bmcr);
4181 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4183 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4189 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4193 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4194 err = tg3_setup_fiber_phy(tp, force_reset);
4195 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4196 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4198 err = tg3_setup_copper_phy(tp, force_reset);
4201 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4204 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4205 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4207 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4212 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4213 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4214 tw32(GRC_MISC_CFG, val);
4217 if (tp->link_config.active_speed == SPEED_1000 &&
4218 tp->link_config.active_duplex == DUPLEX_HALF)
4219 tw32(MAC_TX_LENGTHS,
4220 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4221 (6 << TX_LENGTHS_IPG_SHIFT) |
4222 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4224 tw32(MAC_TX_LENGTHS,
4225 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4226 (6 << TX_LENGTHS_IPG_SHIFT) |
4227 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4229 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4230 if (netif_carrier_ok(tp->dev)) {
4231 tw32(HOSTCC_STAT_COAL_TICKS,
4232 tp->coal.stats_block_coalesce_usecs);
4234 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4238 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4239 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4240 if (!netif_carrier_ok(tp->dev))
4241 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4244 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4245 tw32(PCIE_PWR_MGMT_THRESH, val);
4251 /* This is called whenever we suspect that the system chipset is re-
4252 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4253 * is bogus tx completions. We try to recover by setting the
4254 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4257 static void tg3_tx_recover(struct tg3 *tp)
4259 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4260 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4262 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4263 "mapped I/O cycles to the network device, attempting to "
4264 "recover. Please report the problem to the driver maintainer "
4265 "and include system chipset information.\n", tp->dev->name);
4267 spin_lock(&tp->lock);
4268 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4269 spin_unlock(&tp->lock);
4272 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4275 return tnapi->tx_pending -
4276 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4279 /* Tigon3 never reports partial packet sends. So we do not
4280 * need special logic to handle SKBs that have not had all
4281 * of their frags sent yet, like SunGEM does.
4283 static void tg3_tx(struct tg3_napi *tnapi)
4285 struct tg3 *tp = tnapi->tp;
4286 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4287 u32 sw_idx = tnapi->tx_cons;
4289 while (sw_idx != hw_idx) {
4290 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4291 struct sk_buff *skb = ri->skb;
4294 if (unlikely(skb == NULL)) {
4299 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4303 sw_idx = NEXT_TX(sw_idx);
4305 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4306 ri = &tnapi->tx_buffers[sw_idx];
4307 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4309 sw_idx = NEXT_TX(sw_idx);
4314 if (unlikely(tx_bug)) {
4320 tnapi->tx_cons = sw_idx;
4322 /* Need to make the tx_cons update visible to tg3_start_xmit()
4323 * before checking for netif_queue_stopped(). Without the
4324 * memory barrier, there is a small possibility that tg3_start_xmit()
4325 * will miss it and cause the queue to be stopped forever.
4329 if (unlikely(netif_queue_stopped(tp->dev) &&
4330 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4331 netif_tx_lock(tp->dev);
4332 if (netif_queue_stopped(tp->dev) &&
4333 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4334 netif_wake_queue(tp->dev);
4335 netif_tx_unlock(tp->dev);
4339 /* Returns size of skb allocated or < 0 on error.
4341 * We only need to fill in the address because the other members
4342 * of the RX descriptor are invariant, see tg3_init_rings.
4344 * Note the purposeful assymetry of cpu vs. chip accesses. For
4345 * posting buffers we only dirty the first cache line of the RX
4346 * descriptor (containing the address). Whereas for the RX status
4347 * buffers the cpu only reads the last cacheline of the RX descriptor
4348 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4350 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4351 int src_idx, u32 dest_idx_unmasked)
4353 struct tg3 *tp = tnapi->tp;
4354 struct tg3_rx_buffer_desc *desc;
4355 struct ring_info *map, *src_map;
4356 struct sk_buff *skb;
4358 int skb_size, dest_idx;
4359 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4362 switch (opaque_key) {
4363 case RXD_OPAQUE_RING_STD:
4364 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4365 desc = &tpr->rx_std[dest_idx];
4366 map = &tpr->rx_std_buffers[dest_idx];
4368 src_map = &tpr->rx_std_buffers[src_idx];
4369 skb_size = tp->rx_pkt_map_sz;
4372 case RXD_OPAQUE_RING_JUMBO:
4373 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4374 desc = &tpr->rx_jmb[dest_idx].std;
4375 map = &tpr->rx_jmb_buffers[dest_idx];
4377 src_map = &tpr->rx_jmb_buffers[src_idx];
4378 skb_size = TG3_RX_JMB_MAP_SZ;
4385 /* Do not overwrite any of the map or rp information
4386 * until we are sure we can commit to a new buffer.
4388 * Callers depend upon this behavior and assume that
4389 * we leave everything unchanged if we fail.
4391 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4395 skb_reserve(skb, tp->rx_offset);
4397 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4398 PCI_DMA_FROMDEVICE);
4401 pci_unmap_addr_set(map, mapping, mapping);
4403 if (src_map != NULL)
4404 src_map->skb = NULL;
4406 desc->addr_hi = ((u64)mapping >> 32);
4407 desc->addr_lo = ((u64)mapping & 0xffffffff);
4412 /* We only need to move over in the address because the other
4413 * members of the RX descriptor are invariant. See notes above
4414 * tg3_alloc_rx_skb for full details.
4416 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4417 int src_idx, u32 dest_idx_unmasked)
4419 struct tg3 *tp = tnapi->tp;
4420 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4421 struct ring_info *src_map, *dest_map;
4423 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4425 switch (opaque_key) {
4426 case RXD_OPAQUE_RING_STD:
4427 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4428 dest_desc = &tpr->rx_std[dest_idx];
4429 dest_map = &tpr->rx_std_buffers[dest_idx];
4430 src_desc = &tpr->rx_std[src_idx];
4431 src_map = &tpr->rx_std_buffers[src_idx];
4434 case RXD_OPAQUE_RING_JUMBO:
4435 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4436 dest_desc = &tpr->rx_jmb[dest_idx].std;
4437 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4438 src_desc = &tpr->rx_jmb[src_idx].std;
4439 src_map = &tpr->rx_jmb_buffers[src_idx];
4446 dest_map->skb = src_map->skb;
4447 pci_unmap_addr_set(dest_map, mapping,
4448 pci_unmap_addr(src_map, mapping));
4449 dest_desc->addr_hi = src_desc->addr_hi;
4450 dest_desc->addr_lo = src_desc->addr_lo;
4452 src_map->skb = NULL;
4455 /* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4479 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4481 struct tg3 *tp = tnapi->tp;
4482 u32 work_mask, rx_std_posted = 0;
4483 u32 sw_idx = tnapi->rx_rcb_ptr;
4486 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4488 hw_idx = tnapi->hw_status->idx[0].rx_producer;
4490 * We need to order the read of hw_idx and the read of
4491 * the opaque cookie.
4496 while (sw_idx != hw_idx && budget > 0) {
4497 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4499 struct sk_buff *skb;
4500 dma_addr_t dma_addr;
4501 u32 opaque_key, desc_idx, *post_ptr;
4503 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4504 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4505 if (opaque_key == RXD_OPAQUE_RING_STD) {
4506 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4507 dma_addr = pci_unmap_addr(ri, mapping);
4509 post_ptr = &tpr->rx_std_ptr;
4511 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4512 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4513 dma_addr = pci_unmap_addr(ri, mapping);
4515 post_ptr = &tpr->rx_jmb_ptr;
4517 goto next_pkt_nopost;
4519 work_mask |= opaque_key;
4521 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4522 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4524 tg3_recycle_rx(tnapi, opaque_key,
4525 desc_idx, *post_ptr);
4527 /* Other statistics kept track of by card. */
4528 tp->net_stats.rx_dropped++;
4532 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4535 if (len > RX_COPY_THRESHOLD
4536 && tp->rx_offset == NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4544 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4545 desc_idx, *post_ptr);
4549 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4550 PCI_DMA_FROMDEVICE);
4554 struct sk_buff *copy_skb;
4556 tg3_recycle_rx(tnapi, opaque_key,
4557 desc_idx, *post_ptr);
4559 copy_skb = netdev_alloc_skb(tp->dev,
4560 len + TG3_RAW_IP_ALIGN);
4561 if (copy_skb == NULL)
4562 goto drop_it_no_recycle;
4564 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4565 skb_put(copy_skb, len);
4566 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4567 skb_copy_from_linear_data(skb, copy_skb->data, len);
4568 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4570 /* We'll reuse the original ring buffer. */
4574 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4575 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4576 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4577 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4578 skb->ip_summed = CHECKSUM_UNNECESSARY;
4580 skb->ip_summed = CHECKSUM_NONE;
4582 skb->protocol = eth_type_trans(skb, tp->dev);
4584 if (len > (tp->dev->mtu + ETH_HLEN) &&
4585 skb->protocol != htons(ETH_P_8021Q)) {
4590 #if TG3_VLAN_TAG_USED
4591 if (tp->vlgrp != NULL &&
4592 desc->type_flags & RXD_FLAG_VLAN) {
4593 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4594 desc->err_vlan & RXD_VLAN_MASK, skb);
4597 napi_gro_receive(&tnapi->napi, skb);
4605 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4606 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4609 TG3_64BIT_REG_LOW, idx);
4610 work_mask &= ~RXD_OPAQUE_RING_STD;
4615 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx == hw_idx) {
4619 hw_idx = tnapi->hw_status->idx[0].rx_producer;
4624 /* ACK the status ring. */
4625 tnapi->rx_rcb_ptr = sw_idx;
4626 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4628 /* Refill RX ring(s). */
4629 if (work_mask & RXD_OPAQUE_RING_STD) {
4630 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4634 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4635 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4644 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4646 struct tg3 *tp = tnapi->tp;
4647 struct tg3_hw_status *sblk = tnapi->hw_status;
4649 /* handle link change and other phy events */
4650 if (!(tp->tg3_flags &
4651 (TG3_FLAG_USE_LINKCHG_REG |
4652 TG3_FLAG_POLL_SERDES))) {
4653 if (sblk->status & SD_STATUS_LINK_CHG) {
4654 sblk->status = SD_STATUS_UPDATED |
4655 (sblk->status & ~SD_STATUS_LINK_CHG);
4656 spin_lock(&tp->lock);
4657 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4659 (MAC_STATUS_SYNC_CHANGED |
4660 MAC_STATUS_CFG_CHANGED |
4661 MAC_STATUS_MI_COMPLETION |
4662 MAC_STATUS_LNKSTATE_CHANGED));
4665 tg3_setup_phy(tp, 0);
4666 spin_unlock(&tp->lock);
4670 /* run TX completion thread */
4671 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4673 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
4679 * code synchronizes with tg3->napi.poll()
4681 if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr)
4682 work_done += tg3_rx(tnapi, budget - work_done);
4687 static int tg3_poll(struct napi_struct *napi, int budget)
4689 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4690 struct tg3 *tp = tnapi->tp;
4692 struct tg3_hw_status *sblk = tnapi->hw_status;
4695 work_done = tg3_poll_work(tnapi, work_done, budget);
4697 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4700 if (unlikely(work_done >= budget))
4703 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4704 /* tp->last_tag is used in tg3_int_reenable() below
4705 * to tell the hw how much work has been processed,
4706 * so we must read it before checking for more work.
4708 tnapi->last_tag = sblk->status_tag;
4709 tnapi->last_irq_tag = tnapi->last_tag;
4712 sblk->status &= ~SD_STATUS_UPDATED;
4714 if (likely(!tg3_has_work(tnapi))) {
4715 napi_complete(napi);
4716 tg3_int_reenable(tnapi);
4724 /* work_done is guaranteed to be less than budget. */
4725 napi_complete(napi);
4726 schedule_work(&tp->reset_task);
4730 static void tg3_irq_quiesce(struct tg3 *tp)
4732 BUG_ON(tp->irq_sync);
4737 synchronize_irq(tp->pdev->irq);
4740 static inline int tg3_irq_sync(struct tg3 *tp)
4742 return tp->irq_sync;
4745 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4746 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4747 * with as well. Most of the time, this is not necessary except when
4748 * shutting down the device.
4750 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4752 spin_lock_bh(&tp->lock);
4754 tg3_irq_quiesce(tp);
4757 static inline void tg3_full_unlock(struct tg3 *tp)
4759 spin_unlock_bh(&tp->lock);
4762 /* One-shot MSI handler - Chip automatically disables interrupt
4763 * after sending MSI so driver doesn't have to do it.
4765 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4767 struct tg3_napi *tnapi = dev_id;
4768 struct tg3 *tp = tnapi->tp;
4770 prefetch(tnapi->hw_status);
4771 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4773 if (likely(!tg3_irq_sync(tp)))
4774 napi_schedule(&tnapi->napi);
4779 /* MSI ISR - No need to check for interrupt sharing and no need to
4780 * flush status block and interrupt mailbox. PCI ordering rules
4781 * guarantee that MSI will arrive after the status block.
4783 static irqreturn_t tg3_msi(int irq, void *dev_id)
4785 struct tg3_napi *tnapi = dev_id;
4786 struct tg3 *tp = tnapi->tp;
4788 prefetch(tnapi->hw_status);
4789 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4791 * Writing any value to intr-mbox-0 clears PCI INTA# and
4792 * chip-internal interrupt pending events.
4793 * Writing non-zero to intr-mbox-0 additional tells the
4794 * NIC to stop sending us irqs, engaging "in-intr-handler"
4797 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4798 if (likely(!tg3_irq_sync(tp)))
4799 napi_schedule(&tnapi->napi);
4801 return IRQ_RETVAL(1);
4804 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4806 struct tg3_napi *tnapi = dev_id;
4807 struct tg3 *tp = tnapi->tp;
4808 struct tg3_hw_status *sblk = tnapi->hw_status;
4809 unsigned int handled = 1;
4811 /* In INTx mode, it is possible for the interrupt to arrive at
4812 * the CPU before the status block posted prior to the interrupt.
4813 * Reading the PCI State register will confirm whether the
4814 * interrupt is ours and will flush the status block.
4816 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4817 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4818 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4825 * Writing any value to intr-mbox-0 clears PCI INTA# and
4826 * chip-internal interrupt pending events.
4827 * Writing non-zero to intr-mbox-0 additional tells the
4828 * NIC to stop sending us irqs, engaging "in-intr-handler"
4831 * Flush the mailbox to de-assert the IRQ immediately to prevent
4832 * spurious interrupts. The flush impacts performance but
4833 * excessive spurious interrupts can be worse in some cases.
4835 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4836 if (tg3_irq_sync(tp))
4838 sblk->status &= ~SD_STATUS_UPDATED;
4839 if (likely(tg3_has_work(tnapi))) {
4840 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4841 napi_schedule(&tnapi->napi);
4843 /* No work, shared interrupt perhaps? re-enable
4844 * interrupts, and flush that PCI write
4846 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4850 return IRQ_RETVAL(handled);
4853 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4855 struct tg3_napi *tnapi = dev_id;
4856 struct tg3 *tp = tnapi->tp;
4857 struct tg3_hw_status *sblk = tnapi->hw_status;
4858 unsigned int handled = 1;
4860 /* In INTx mode, it is possible for the interrupt to arrive at
4861 * the CPU before the status block posted prior to the interrupt.
4862 * Reading the PCI State register will confirm whether the
4863 * interrupt is ours and will flush the status block.
4865 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4866 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4867 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4874 * writing any value to intr-mbox-0 clears PCI INTA# and
4875 * chip-internal interrupt pending events.
4876 * writing non-zero to intr-mbox-0 additional tells the
4877 * NIC to stop sending us irqs, engaging "in-intr-handler"
4880 * Flush the mailbox to de-assert the IRQ immediately to prevent
4881 * spurious interrupts. The flush impacts performance but
4882 * excessive spurious interrupts can be worse in some cases.
4884 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4887 * In a shared interrupt configuration, sometimes other devices'
4888 * interrupts will scream. We record the current status tag here
4889 * so that the above check can report that the screaming interrupts
4890 * are unhandled. Eventually they will be silenced.
4892 tnapi->last_irq_tag = sblk->status_tag;
4894 if (tg3_irq_sync(tp))
4897 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4899 napi_schedule(&tnapi->napi);
4902 return IRQ_RETVAL(handled);
4905 /* ISR for interrupt test */
4906 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4908 struct tg3_napi *tnapi = dev_id;
4909 struct tg3 *tp = tnapi->tp;
4910 struct tg3_hw_status *sblk = tnapi->hw_status;
4912 if ((sblk->status & SD_STATUS_UPDATED) ||
4913 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4914 tg3_disable_ints(tp);
4915 return IRQ_RETVAL(1);
4917 return IRQ_RETVAL(0);
4920 static int tg3_init_hw(struct tg3 *, int);
4921 static int tg3_halt(struct tg3 *, int, int);
4923 /* Restart hardware after configuration changes, self-test, etc.
4924 * Invoked with tp->lock held.
4926 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4927 __releases(tp->lock)
4928 __acquires(tp->lock)
4932 err = tg3_init_hw(tp, reset_phy);
4934 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4935 "aborting.\n", tp->dev->name);
4936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4937 tg3_full_unlock(tp);
4938 del_timer_sync(&tp->timer);
4940 napi_enable(&tp->napi[0].napi);
4942 tg3_full_lock(tp, 0);
4947 #ifdef CONFIG_NET_POLL_CONTROLLER
4948 static void tg3_poll_controller(struct net_device *dev)
4950 struct tg3 *tp = netdev_priv(dev);
4952 tg3_interrupt(tp->pdev->irq, dev);
4956 static void tg3_reset_task(struct work_struct *work)
4958 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4960 unsigned int restart_timer;
4962 tg3_full_lock(tp, 0);
4964 if (!netif_running(tp->dev)) {
4965 tg3_full_unlock(tp);
4969 tg3_full_unlock(tp);
4975 tg3_full_lock(tp, 1);
4977 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4978 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4980 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4981 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4982 tp->write32_rx_mbox = tg3_write_flush_reg32;
4983 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4984 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4987 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4988 err = tg3_init_hw(tp, 1);
4992 tg3_netif_start(tp);
4995 mod_timer(&tp->timer, jiffies + 1);
4998 tg3_full_unlock(tp);
5004 static void tg3_dump_short_state(struct tg3 *tp)
5006 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5007 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5008 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5009 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5012 static void tg3_tx_timeout(struct net_device *dev)
5014 struct tg3 *tp = netdev_priv(dev);
5016 if (netif_msg_tx_err(tp)) {
5017 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5019 tg3_dump_short_state(tp);
5022 schedule_work(&tp->reset_task);
5025 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5026 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5028 u32 base = (u32) mapping & 0xffffffff;
5030 return ((base > 0xffffdcc0) &&
5031 (base + len + 8 < base));
5034 /* Test for DMA addresses > 40-bit */
5035 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5038 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5039 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5040 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5047 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5049 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5050 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5051 u32 last_plus_one, u32 *start,
5052 u32 base_flags, u32 mss)
5054 struct tg3_napi *tnapi = &tp->napi[0];
5055 struct sk_buff *new_skb;
5056 dma_addr_t new_addr = 0;
5060 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5061 new_skb = skb_copy(skb, GFP_ATOMIC);
5063 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5065 new_skb = skb_copy_expand(skb,
5066 skb_headroom(skb) + more_headroom,
5067 skb_tailroom(skb), GFP_ATOMIC);
5073 /* New SKB is guaranteed to be linear. */
5075 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5076 new_addr = skb_shinfo(new_skb)->dma_head;
5078 /* Make sure new skb does not cross any 4G boundaries.
5079 * Drop the packet if it does.
5081 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5083 skb_dma_unmap(&tp->pdev->dev, new_skb,
5086 dev_kfree_skb(new_skb);
5089 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5090 base_flags, 1 | (mss << 1));
5091 *start = NEXT_TX(entry);
5095 /* Now clean up the sw ring entries. */
5097 while (entry != last_plus_one) {
5099 tnapi->tx_buffers[entry].skb = new_skb;
5101 tnapi->tx_buffers[entry].skb = NULL;
5102 entry = NEXT_TX(entry);
5106 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5112 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5113 dma_addr_t mapping, int len, u32 flags,
5116 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5117 int is_end = (mss_and_is_end & 0x1);
5118 u32 mss = (mss_and_is_end >> 1);
5122 flags |= TXD_FLAG_END;
5123 if (flags & TXD_FLAG_VLAN) {
5124 vlan_tag = flags >> 16;
5127 vlan_tag |= (mss << TXD_MSS_SHIFT);
5129 txd->addr_hi = ((u64) mapping >> 32);
5130 txd->addr_lo = ((u64) mapping & 0xffffffff);
5131 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5132 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5135 /* hard_start_xmit for devices that don't have any bugs and
5136 * support TG3_FLG2_HW_TSO_2 only.
5138 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5139 struct net_device *dev)
5141 struct tg3 *tp = netdev_priv(dev);
5142 u32 len, entry, base_flags, mss;
5143 struct skb_shared_info *sp;
5145 struct tg3_napi *tnapi = &tp->napi[0];
5147 len = skb_headlen(skb);
5149 /* We are running in BH disabled context with netif_tx_lock
5150 * and TX reclaim runs via tp->napi.poll inside of a software
5151 * interrupt. Furthermore, IRQ processing runs lockless so we have
5152 * no IRQ context deadlocks to worry about either. Rejoice!
5154 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5155 if (!netif_queue_stopped(dev)) {
5156 netif_stop_queue(dev);
5158 /* This is a hard error, log it. */
5159 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5160 "queue awake!\n", dev->name);
5162 return NETDEV_TX_BUSY;
5165 entry = tnapi->tx_prod;
5168 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5169 int tcp_opt_len, ip_tcp_len;
5171 if (skb_header_cloned(skb) &&
5172 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5177 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5178 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5180 struct iphdr *iph = ip_hdr(skb);
5182 tcp_opt_len = tcp_optlen(skb);
5183 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5186 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5187 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5190 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5191 TXD_FLAG_CPU_POST_DMA);
5193 tcp_hdr(skb)->check = 0;
5196 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5197 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5198 #if TG3_VLAN_TAG_USED
5199 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5200 base_flags |= (TXD_FLAG_VLAN |
5201 (vlan_tx_tag_get(skb) << 16));
5204 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5209 sp = skb_shinfo(skb);
5211 mapping = sp->dma_head;
5213 tnapi->tx_buffers[entry].skb = skb;
5215 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5216 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5218 entry = NEXT_TX(entry);
5220 /* Now loop through additional data fragments, and queue them. */
5221 if (skb_shinfo(skb)->nr_frags > 0) {
5222 unsigned int i, last;
5224 last = skb_shinfo(skb)->nr_frags - 1;
5225 for (i = 0; i <= last; i++) {
5226 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5229 mapping = sp->dma_maps[i];
5230 tnapi->tx_buffers[entry].skb = NULL;
5232 tg3_set_txd(tnapi, entry, mapping, len,
5233 base_flags, (i == last) | (mss << 1));
5235 entry = NEXT_TX(entry);
5239 /* Packets are ready, update Tx producer idx local and on card. */
5240 tw32_tx_mbox(tnapi->prodmbox, entry);
5242 tnapi->tx_prod = entry;
5243 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5244 netif_stop_queue(dev);
5245 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5246 netif_wake_queue(tp->dev);
5252 return NETDEV_TX_OK;
5255 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5256 struct net_device *);
5258 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5259 * TSO header is greater than 80 bytes.
5261 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5263 struct sk_buff *segs, *nskb;
5264 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5266 /* Estimate the number of fragments in the worst case */
5267 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5268 netif_stop_queue(tp->dev);
5269 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5270 return NETDEV_TX_BUSY;
5272 netif_wake_queue(tp->dev);
5275 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5277 goto tg3_tso_bug_end;
5283 tg3_start_xmit_dma_bug(nskb, tp->dev);
5289 return NETDEV_TX_OK;
5292 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5293 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5295 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5296 struct net_device *dev)
5298 struct tg3 *tp = netdev_priv(dev);
5299 u32 len, entry, base_flags, mss;
5300 struct skb_shared_info *sp;
5301 int would_hit_hwbug;
5303 struct tg3_napi *tnapi = &tp->napi[0];
5305 len = skb_headlen(skb);
5307 /* We are running in BH disabled context with netif_tx_lock
5308 * and TX reclaim runs via tp->napi.poll inside of a software
5309 * interrupt. Furthermore, IRQ processing runs lockless so we have
5310 * no IRQ context deadlocks to worry about either. Rejoice!
5312 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5313 if (!netif_queue_stopped(dev)) {
5314 netif_stop_queue(dev);
5316 /* This is a hard error, log it. */
5317 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5318 "queue awake!\n", dev->name);
5320 return NETDEV_TX_BUSY;
5323 entry = tnapi->tx_prod;
5325 if (skb->ip_summed == CHECKSUM_PARTIAL)
5326 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5328 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5330 int tcp_opt_len, ip_tcp_len, hdr_len;
5332 if (skb_header_cloned(skb) &&
5333 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5338 tcp_opt_len = tcp_optlen(skb);
5339 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5341 hdr_len = ip_tcp_len + tcp_opt_len;
5342 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5343 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5344 return (tg3_tso_bug(tp, skb));
5346 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5347 TXD_FLAG_CPU_POST_DMA);
5351 iph->tot_len = htons(mss + hdr_len);
5352 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5353 tcp_hdr(skb)->check = 0;
5354 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5356 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5361 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5362 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5363 if (tcp_opt_len || iph->ihl > 5) {
5366 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5367 mss |= (tsflags << 11);
5370 if (tcp_opt_len || iph->ihl > 5) {
5373 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5374 base_flags |= tsflags << 12;
5378 #if TG3_VLAN_TAG_USED
5379 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5380 base_flags |= (TXD_FLAG_VLAN |
5381 (vlan_tx_tag_get(skb) << 16));
5384 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5389 sp = skb_shinfo(skb);
5391 mapping = sp->dma_head;
5393 tnapi->tx_buffers[entry].skb = skb;
5395 would_hit_hwbug = 0;
5397 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5398 would_hit_hwbug = 1;
5399 else if (tg3_4g_overflow_test(mapping, len))
5400 would_hit_hwbug = 1;
5402 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5403 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5405 entry = NEXT_TX(entry);
5407 /* Now loop through additional data fragments, and queue them. */
5408 if (skb_shinfo(skb)->nr_frags > 0) {
5409 unsigned int i, last;
5411 last = skb_shinfo(skb)->nr_frags - 1;
5412 for (i = 0; i <= last; i++) {
5413 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5416 mapping = sp->dma_maps[i];
5418 tnapi->tx_buffers[entry].skb = NULL;
5420 if (tg3_4g_overflow_test(mapping, len))
5421 would_hit_hwbug = 1;
5423 if (tg3_40bit_overflow_test(tp, mapping, len))
5424 would_hit_hwbug = 1;
5426 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5427 tg3_set_txd(tnapi, entry, mapping, len,
5428 base_flags, (i == last)|(mss << 1));
5430 tg3_set_txd(tnapi, entry, mapping, len,
5431 base_flags, (i == last));
5433 entry = NEXT_TX(entry);
5437 if (would_hit_hwbug) {
5438 u32 last_plus_one = entry;
5441 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5442 start &= (TG3_TX_RING_SIZE - 1);
5444 /* If the workaround fails due to memory/mapping
5445 * failure, silently drop this packet.
5447 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5448 &start, base_flags, mss))
5454 /* Packets are ready, update Tx producer idx local and on card. */
5455 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5457 tnapi->tx_prod = entry;
5458 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5459 netif_stop_queue(dev);
5460 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5461 netif_wake_queue(tp->dev);
5467 return NETDEV_TX_OK;
5470 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5475 if (new_mtu > ETH_DATA_LEN) {
5476 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5477 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5478 ethtool_op_set_tso(dev, 0);
5481 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5483 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5484 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5485 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5489 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5491 struct tg3 *tp = netdev_priv(dev);
5494 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5497 if (!netif_running(dev)) {
5498 /* We'll just catch it later when the
5501 tg3_set_mtu(dev, tp, new_mtu);
5509 tg3_full_lock(tp, 1);
5511 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5513 tg3_set_mtu(dev, tp, new_mtu);
5515 err = tg3_restart_hw(tp, 0);
5518 tg3_netif_start(tp);
5520 tg3_full_unlock(tp);
5528 static void tg3_rx_prodring_free(struct tg3 *tp,
5529 struct tg3_rx_prodring_set *tpr)
5532 struct ring_info *rxp;
5534 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5535 rxp = &tpr->rx_std_buffers[i];
5537 if (rxp->skb == NULL)
5540 pci_unmap_single(tp->pdev,
5541 pci_unmap_addr(rxp, mapping),
5543 PCI_DMA_FROMDEVICE);
5544 dev_kfree_skb_any(rxp->skb);
5548 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5549 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5550 rxp = &tpr->rx_jmb_buffers[i];
5552 if (rxp->skb == NULL)
5555 pci_unmap_single(tp->pdev,
5556 pci_unmap_addr(rxp, mapping),
5558 PCI_DMA_FROMDEVICE);
5559 dev_kfree_skb_any(rxp->skb);
5565 /* Initialize tx/rx rings for packet processing.
5567 * The chip has been shut down and the driver detached from
5568 * the networking, so no interrupts or new tx packets will
5569 * end up in the driver. tp->{tx,}lock are held and thus
5572 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5573 struct tg3_rx_prodring_set *tpr)
5575 u32 i, rx_pkt_dma_sz;
5576 struct tg3_napi *tnapi = &tp->napi[0];
5578 /* Zero out all descriptors. */
5579 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5581 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5582 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5583 tp->dev->mtu > ETH_DATA_LEN)
5584 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5585 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5587 /* Initialize invariants of the rings, we only set this
5588 * stuff once. This works because the card does not
5589 * write into the rx buffer posting rings.
5591 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5592 struct tg3_rx_buffer_desc *rxd;
5594 rxd = &tpr->rx_std[i];
5595 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5596 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5597 rxd->opaque = (RXD_OPAQUE_RING_STD |
5598 (i << RXD_OPAQUE_INDEX_SHIFT));
5601 /* Now allocate fresh SKBs for each rx ring. */
5602 for (i = 0; i < tp->rx_pending; i++) {
5603 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5604 printk(KERN_WARNING PFX
5605 "%s: Using a smaller RX standard ring, "
5606 "only %d out of %d buffers were allocated "
5608 tp->dev->name, i, tp->rx_pending);
5616 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5619 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5621 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5622 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5623 struct tg3_rx_buffer_desc *rxd;
5625 rxd = &tpr->rx_jmb[i].std;
5626 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5627 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5629 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5630 (i << RXD_OPAQUE_INDEX_SHIFT));
5633 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5634 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5636 printk(KERN_WARNING PFX
5637 "%s: Using a smaller RX jumbo ring, "
5638 "only %d out of %d buffers were "
5639 "allocated successfully.\n",
5640 tp->dev->name, i, tp->rx_jumbo_pending);
5643 tp->rx_jumbo_pending = i;
5653 tg3_rx_prodring_free(tp, tpr);
5657 static void tg3_rx_prodring_fini(struct tg3 *tp,
5658 struct tg3_rx_prodring_set *tpr)
5660 kfree(tpr->rx_std_buffers);
5661 tpr->rx_std_buffers = NULL;
5662 kfree(tpr->rx_jmb_buffers);
5663 tpr->rx_jmb_buffers = NULL;
5665 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5666 tpr->rx_std, tpr->rx_std_mapping);
5670 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5671 tpr->rx_jmb, tpr->rx_jmb_mapping);
5676 static int tg3_rx_prodring_init(struct tg3 *tp,
5677 struct tg3_rx_prodring_set *tpr)
5679 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5680 TG3_RX_RING_SIZE, GFP_KERNEL);
5681 if (!tpr->rx_std_buffers)
5684 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5685 &tpr->rx_std_mapping);
5689 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5690 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5691 TG3_RX_JUMBO_RING_SIZE,
5693 if (!tpr->rx_jmb_buffers)
5696 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5697 TG3_RX_JUMBO_RING_BYTES,
5698 &tpr->rx_jmb_mapping);
5706 tg3_rx_prodring_fini(tp, tpr);
5710 /* Free up pending packets in all rx/tx rings.
5712 * The chip has been shut down and the driver detached from
5713 * the networking, so no interrupts or new tx packets will
5714 * end up in the driver. tp->{tx,}lock is not held and we are not
5715 * in an interrupt context and thus may sleep.
5717 static void tg3_free_rings(struct tg3 *tp)
5719 struct tg3_napi *tnapi = &tp->napi[0];
5722 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5723 struct tx_ring_info *txp;
5724 struct sk_buff *skb;
5726 txp = &tnapi->tx_buffers[i];
5734 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5738 i += skb_shinfo(skb)->nr_frags + 1;
5740 dev_kfree_skb_any(skb);
5743 tg3_rx_prodring_free(tp, &tp->prodring[0]);
5746 /* Initialize tx/rx rings for packet processing.
5748 * The chip has been shut down and the driver detached from
5749 * the networking, so no interrupts or new tx packets will
5750 * end up in the driver. tp->{tx,}lock are held and thus
5753 static int tg3_init_rings(struct tg3 *tp)
5755 struct tg3_napi *tnapi = &tp->napi[0];
5757 /* Free up all the SKBs. */
5760 /* Zero out all descriptors. */
5761 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5763 tnapi->rx_rcb_ptr = 0;
5764 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5766 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5770 * Must not be invoked with interrupt sources disabled and
5771 * the hardware shutdown down.
5773 static void tg3_free_consistent(struct tg3 *tp)
5775 struct tg3_napi *tnapi = &tp->napi[0];
5777 kfree(tnapi->tx_buffers);
5778 tnapi->tx_buffers = NULL;
5779 if (tnapi->tx_ring) {
5780 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5781 tnapi->tx_ring, tnapi->tx_desc_mapping);
5782 tnapi->tx_ring = NULL;
5784 if (tnapi->rx_rcb) {
5785 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5786 tnapi->rx_rcb, tnapi->rx_rcb_mapping);
5787 tnapi->rx_rcb = NULL;
5789 if (tnapi->hw_status) {
5790 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5792 tnapi->status_mapping);
5793 tnapi->hw_status = NULL;
5796 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5797 tp->hw_stats, tp->stats_mapping);
5798 tp->hw_stats = NULL;
5800 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5804 * Must not be invoked with interrupt sources disabled and
5805 * the hardware shutdown down. Can sleep.
5807 static int tg3_alloc_consistent(struct tg3 *tp)
5809 struct tg3_napi *tnapi = &tp->napi[0];
5811 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5814 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5815 TG3_TX_RING_SIZE, GFP_KERNEL);
5816 if (!tnapi->tx_buffers)
5819 tnapi->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5820 &tnapi->tx_desc_mapping);
5821 if (!tnapi->tx_ring)
5824 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5826 &tnapi->status_mapping);
5827 if (!tnapi->hw_status)
5830 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5832 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5833 TG3_RX_RCB_RING_BYTES(tp),
5834 &tnapi->rx_rcb_mapping);
5838 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5840 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5841 sizeof(struct tg3_hw_stats),
5842 &tp->stats_mapping);
5846 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5851 tg3_free_consistent(tp);
5855 #define MAX_WAIT_CNT 1000
5857 /* To stop a block, clear the enable bit and poll till it
5858 * clears. tp->lock is held.
5860 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5865 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5872 /* We can't enable/disable these bits of the
5873 * 5705/5750, just say success.
5886 for (i = 0; i < MAX_WAIT_CNT; i++) {
5889 if ((val & enable_bit) == 0)
5893 if (i == MAX_WAIT_CNT && !silent) {
5894 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5895 "ofs=%lx enable_bit=%x\n",
5903 /* tp->lock is held. */
5904 static int tg3_abort_hw(struct tg3 *tp, int silent)
5907 struct tg3_napi *tnapi = &tp->napi[0];
5909 tg3_disable_ints(tp);
5911 tp->rx_mode &= ~RX_MODE_ENABLE;
5912 tw32_f(MAC_RX_MODE, tp->rx_mode);
5915 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5916 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5917 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5918 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5919 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5920 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5922 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5923 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5924 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5925 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5926 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5927 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5928 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5930 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5931 tw32_f(MAC_MODE, tp->mac_mode);
5934 tp->tx_mode &= ~TX_MODE_ENABLE;
5935 tw32_f(MAC_TX_MODE, tp->tx_mode);
5937 for (i = 0; i < MAX_WAIT_CNT; i++) {
5939 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5942 if (i >= MAX_WAIT_CNT) {
5943 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5944 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5945 tp->dev->name, tr32(MAC_TX_MODE));
5949 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5950 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5951 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5953 tw32(FTQ_RESET, 0xffffffff);
5954 tw32(FTQ_RESET, 0x00000000);
5956 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5957 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5959 if (tnapi->hw_status)
5960 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5962 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5967 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5972 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5973 if (apedata != APE_SEG_SIG_MAGIC)
5976 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5977 if (!(apedata & APE_FW_STATUS_READY))
5980 /* Wait for up to 1 millisecond for APE to service previous event. */
5981 for (i = 0; i < 10; i++) {
5982 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5985 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5987 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5988 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5989 event | APE_EVENT_STATUS_EVENT_PENDING);
5991 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5993 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5999 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6000 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6003 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6008 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6012 case RESET_KIND_INIT:
6013 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6014 APE_HOST_SEG_SIG_MAGIC);
6015 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6016 APE_HOST_SEG_LEN_MAGIC);
6017 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6018 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6019 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6020 APE_HOST_DRIVER_ID_MAGIC);
6021 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6022 APE_HOST_BEHAV_NO_PHYLOCK);
6024 event = APE_EVENT_STATUS_STATE_START;
6026 case RESET_KIND_SHUTDOWN:
6027 /* With the interface we are currently using,
6028 * APE does not track driver state. Wiping
6029 * out the HOST SEGMENT SIGNATURE forces
6030 * the APE to assume OS absent status.
6032 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6034 event = APE_EVENT_STATUS_STATE_UNLOAD;
6036 case RESET_KIND_SUSPEND:
6037 event = APE_EVENT_STATUS_STATE_SUSPEND;
6043 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6045 tg3_ape_send_event(tp, event);
6048 /* tp->lock is held. */
6049 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6051 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6052 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6054 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6056 case RESET_KIND_INIT:
6057 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6061 case RESET_KIND_SHUTDOWN:
6062 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6066 case RESET_KIND_SUSPEND:
6067 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6076 if (kind == RESET_KIND_INIT ||
6077 kind == RESET_KIND_SUSPEND)
6078 tg3_ape_driver_state_change(tp, kind);
6081 /* tp->lock is held. */
6082 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6084 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6086 case RESET_KIND_INIT:
6087 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6088 DRV_STATE_START_DONE);
6091 case RESET_KIND_SHUTDOWN:
6092 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6093 DRV_STATE_UNLOAD_DONE);
6101 if (kind == RESET_KIND_SHUTDOWN)
6102 tg3_ape_driver_state_change(tp, kind);
6105 /* tp->lock is held. */
6106 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6108 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6110 case RESET_KIND_INIT:
6111 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6115 case RESET_KIND_SHUTDOWN:
6116 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6120 case RESET_KIND_SUSPEND:
6121 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6131 static int tg3_poll_fw(struct tg3 *tp)
6136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6137 /* Wait up to 20ms for init done. */
6138 for (i = 0; i < 200; i++) {
6139 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6146 /* Wait for firmware initialization to complete. */
6147 for (i = 0; i < 100000; i++) {
6148 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6149 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6154 /* Chip might not be fitted with firmware. Some Sun onboard
6155 * parts are configured like that. So don't signal the timeout
6156 * of the above loop as an error, but do report the lack of
6157 * running firmware once.
6160 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6161 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6163 printk(KERN_INFO PFX "%s: No firmware running.\n",
6170 /* Save PCI command register before chip reset */
6171 static void tg3_save_pci_state(struct tg3 *tp)
6173 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6176 /* Restore PCI state after chip reset */
6177 static void tg3_restore_pci_state(struct tg3 *tp)
6181 /* Re-enable indirect register accesses. */
6182 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6183 tp->misc_host_ctrl);
6185 /* Set MAX PCI retry to zero. */
6186 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6187 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6188 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6189 val |= PCISTATE_RETRY_SAME_DMA;
6190 /* Allow reads and writes to the APE register and memory space. */
6191 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6192 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6193 PCISTATE_ALLOW_APE_SHMEM_WR;
6194 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6196 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6198 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6199 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6200 pcie_set_readrq(tp->pdev, 4096);
6202 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6203 tp->pci_cacheline_sz);
6204 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6209 /* Make sure PCI-X relaxed ordering bit is clear. */
6210 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6213 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6215 pcix_cmd &= ~PCI_X_CMD_ERO;
6216 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6220 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6222 /* Chip reset on 5780 will reset MSI enable bit,
6223 * so need to restore it.
6225 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6228 pci_read_config_word(tp->pdev,
6229 tp->msi_cap + PCI_MSI_FLAGS,
6231 pci_write_config_word(tp->pdev,
6232 tp->msi_cap + PCI_MSI_FLAGS,
6233 ctrl | PCI_MSI_FLAGS_ENABLE);
6234 val = tr32(MSGINT_MODE);
6235 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6240 static void tg3_stop_fw(struct tg3 *);
6242 /* tp->lock is held. */
6243 static int tg3_chip_reset(struct tg3 *tp)
6246 void (*write_op)(struct tg3 *, u32, u32);
6253 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6255 /* No matching tg3_nvram_unlock() after this because
6256 * chip reset below will undo the nvram lock.
6258 tp->nvram_lock_cnt = 0;
6260 /* GRC_MISC_CFG core clock reset will clear the memory
6261 * enable bit in PCI register 4 and the MSI enable bit
6262 * on some chips, so we save relevant registers here.
6264 tg3_save_pci_state(tp);
6266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6267 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6268 tw32(GRC_FASTBOOT_PC, 0);
6271 * We must avoid the readl() that normally takes place.
6272 * It locks machines, causes machine checks, and other
6273 * fun things. So, temporarily disable the 5701
6274 * hardware workaround, while we do the reset.
6276 write_op = tp->write32;
6277 if (write_op == tg3_write_flush_reg32)
6278 tp->write32 = tg3_write32;
6280 /* Prevent the irq handler from reading or writing PCI registers
6281 * during chip reset when the memory enable bit in the PCI command
6282 * register may be cleared. The chip does not generate interrupt
6283 * at this time, but the irq handler may still be called due to irq
6284 * sharing or irqpoll.
6286 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6287 if (tp->napi[0].hw_status) {
6288 tp->napi[0].hw_status->status = 0;
6289 tp->napi[0].hw_status->status_tag = 0;
6291 tp->napi[0].last_tag = 0;
6292 tp->napi[0].last_irq_tag = 0;
6294 synchronize_irq(tp->pdev->irq);
6296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6297 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6298 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6302 val = GRC_MISC_CFG_CORECLK_RESET;
6304 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6305 if (tr32(0x7e2c) == 0x60) {
6308 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6309 tw32(GRC_MISC_CFG, (1 << 29));
6314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6315 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6316 tw32(GRC_VCPU_EXT_CTRL,
6317 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6320 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6321 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6322 tw32(GRC_MISC_CFG, val);
6324 /* restore 5701 hardware bug workaround write method */
6325 tp->write32 = write_op;
6327 /* Unfortunately, we have to delay before the PCI read back.
6328 * Some 575X chips even will not respond to a PCI cfg access
6329 * when the reset command is given to the chip.
6331 * How do these hardware designers expect things to work
6332 * properly if the PCI write is posted for a long period
6333 * of time? It is always necessary to have some method by
6334 * which a register read back can occur to push the write
6335 * out which does the reset.
6337 * For most tg3 variants the trick below was working.
6342 /* Flush PCI posted writes. The normal MMIO registers
6343 * are inaccessible at this time so this is the only
6344 * way to make this reliably (actually, this is no longer
6345 * the case, see above). I tried to use indirect
6346 * register read/write but this upset some 5701 variants.
6348 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6352 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6355 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6359 /* Wait for link training to complete. */
6360 for (i = 0; i < 5000; i++)
6363 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6364 pci_write_config_dword(tp->pdev, 0xc4,
6365 cfg_val | (1 << 15));
6368 /* Clear the "no snoop" and "relaxed ordering" bits. */
6369 pci_read_config_word(tp->pdev,
6370 tp->pcie_cap + PCI_EXP_DEVCTL,
6372 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6373 PCI_EXP_DEVCTL_NOSNOOP_EN);
6375 * Older PCIe devices only support the 128 byte
6376 * MPS setting. Enforce the restriction.
6378 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6379 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6380 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6381 pci_write_config_word(tp->pdev,
6382 tp->pcie_cap + PCI_EXP_DEVCTL,
6385 pcie_set_readrq(tp->pdev, 4096);
6387 /* Clear error status */
6388 pci_write_config_word(tp->pdev,
6389 tp->pcie_cap + PCI_EXP_DEVSTA,
6390 PCI_EXP_DEVSTA_CED |
6391 PCI_EXP_DEVSTA_NFED |
6392 PCI_EXP_DEVSTA_FED |
6393 PCI_EXP_DEVSTA_URD);
6396 tg3_restore_pci_state(tp);
6398 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6401 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6402 val = tr32(MEMARB_MODE);
6403 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6405 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6407 tw32(0x5000, 0x400);
6410 tw32(GRC_MODE, tp->grc_mode);
6412 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6415 tw32(0xc4, val | (1 << 15));
6418 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6420 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6421 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6422 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6423 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6426 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6427 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6428 tw32_f(MAC_MODE, tp->mac_mode);
6429 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6430 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6431 tw32_f(MAC_MODE, tp->mac_mode);
6432 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6433 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6434 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6435 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6436 tw32_f(MAC_MODE, tp->mac_mode);
6438 tw32_f(MAC_MODE, 0);
6441 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6443 err = tg3_poll_fw(tp);
6449 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6450 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6453 tw32(0x7c00, val | (1 << 25));
6456 /* Reprobe ASF enable state. */
6457 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6458 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6459 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6460 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6463 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6464 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6465 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6466 tp->last_event_jiffies = jiffies;
6467 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6468 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6475 /* tp->lock is held. */
6476 static void tg3_stop_fw(struct tg3 *tp)
6478 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6479 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6480 /* Wait for RX cpu to ACK the previous event. */
6481 tg3_wait_for_event_ack(tp);
6483 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6485 tg3_generate_fw_event(tp);
6487 /* Wait for RX cpu to ACK this event. */
6488 tg3_wait_for_event_ack(tp);
6492 /* tp->lock is held. */
6493 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6499 tg3_write_sig_pre_reset(tp, kind);
6501 tg3_abort_hw(tp, silent);
6502 err = tg3_chip_reset(tp);
6504 __tg3_set_mac_addr(tp, 0);
6506 tg3_write_sig_legacy(tp, kind);
6507 tg3_write_sig_post_reset(tp, kind);
6515 #define RX_CPU_SCRATCH_BASE 0x30000
6516 #define RX_CPU_SCRATCH_SIZE 0x04000
6517 #define TX_CPU_SCRATCH_BASE 0x34000
6518 #define TX_CPU_SCRATCH_SIZE 0x04000
6520 /* tp->lock is held. */
6521 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6525 BUG_ON(offset == TX_CPU_BASE &&
6526 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6529 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6531 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6534 if (offset == RX_CPU_BASE) {
6535 for (i = 0; i < 10000; i++) {
6536 tw32(offset + CPU_STATE, 0xffffffff);
6537 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6538 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6542 tw32(offset + CPU_STATE, 0xffffffff);
6543 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6546 for (i = 0; i < 10000; i++) {
6547 tw32(offset + CPU_STATE, 0xffffffff);
6548 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6549 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6555 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6558 (offset == RX_CPU_BASE ? "RX" : "TX"));
6562 /* Clear firmware's nvram arbitration. */
6563 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6564 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6569 unsigned int fw_base;
6570 unsigned int fw_len;
6571 const __be32 *fw_data;
6574 /* tp->lock is held. */
6575 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6576 int cpu_scratch_size, struct fw_info *info)
6578 int err, lock_err, i;
6579 void (*write_op)(struct tg3 *, u32, u32);
6581 if (cpu_base == TX_CPU_BASE &&
6582 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6583 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6584 "TX cpu firmware on %s which is 5705.\n",
6589 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6590 write_op = tg3_write_mem;
6592 write_op = tg3_write_indirect_reg32;
6594 /* It is possible that bootcode is still loading at this point.
6595 * Get the nvram lock first before halting the cpu.
6597 lock_err = tg3_nvram_lock(tp);
6598 err = tg3_halt_cpu(tp, cpu_base);
6600 tg3_nvram_unlock(tp);
6604 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6605 write_op(tp, cpu_scratch_base + i, 0);
6606 tw32(cpu_base + CPU_STATE, 0xffffffff);
6607 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6608 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6609 write_op(tp, (cpu_scratch_base +
6610 (info->fw_base & 0xffff) +
6612 be32_to_cpu(info->fw_data[i]));
6620 /* tp->lock is held. */
6621 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6623 struct fw_info info;
6624 const __be32 *fw_data;
6627 fw_data = (void *)tp->fw->data;
6629 /* Firmware blob starts with version numbers, followed by
6630 start address and length. We are setting complete length.
6631 length = end_address_of_bss - start_address_of_text.
6632 Remainder is the blob to be loaded contiguously
6633 from start address. */
6635 info.fw_base = be32_to_cpu(fw_data[1]);
6636 info.fw_len = tp->fw->size - 12;
6637 info.fw_data = &fw_data[3];
6639 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6640 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6645 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6646 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6651 /* Now startup only the RX cpu. */
6652 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6653 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6655 for (i = 0; i < 5; i++) {
6656 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6658 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6659 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6660 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6664 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6665 "to set RX CPU PC, is %08x should be %08x\n",
6666 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6670 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6671 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6676 /* 5705 needs a special version of the TSO firmware. */
6678 /* tp->lock is held. */
6679 static int tg3_load_tso_firmware(struct tg3 *tp)
6681 struct fw_info info;
6682 const __be32 *fw_data;
6683 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6686 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6689 fw_data = (void *)tp->fw->data;
6691 /* Firmware blob starts with version numbers, followed by
6692 start address and length. We are setting complete length.
6693 length = end_address_of_bss - start_address_of_text.
6694 Remainder is the blob to be loaded contiguously
6695 from start address. */
6697 info.fw_base = be32_to_cpu(fw_data[1]);
6698 cpu_scratch_size = tp->fw_len;
6699 info.fw_len = tp->fw->size - 12;
6700 info.fw_data = &fw_data[3];
6702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6703 cpu_base = RX_CPU_BASE;
6704 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6706 cpu_base = TX_CPU_BASE;
6707 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6708 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6711 err = tg3_load_firmware_cpu(tp, cpu_base,
6712 cpu_scratch_base, cpu_scratch_size,
6717 /* Now startup the cpu. */
6718 tw32(cpu_base + CPU_STATE, 0xffffffff);
6719 tw32_f(cpu_base + CPU_PC, info.fw_base);
6721 for (i = 0; i < 5; i++) {
6722 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6724 tw32(cpu_base + CPU_STATE, 0xffffffff);
6725 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6726 tw32_f(cpu_base + CPU_PC, info.fw_base);
6730 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6731 "to set CPU PC, is %08x should be %08x\n",
6732 tp->dev->name, tr32(cpu_base + CPU_PC),
6736 tw32(cpu_base + CPU_STATE, 0xffffffff);
6737 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6742 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6744 struct tg3 *tp = netdev_priv(dev);
6745 struct sockaddr *addr = p;
6746 int err = 0, skip_mac_1 = 0;
6748 if (!is_valid_ether_addr(addr->sa_data))
6751 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6753 if (!netif_running(dev))
6756 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6757 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6759 addr0_high = tr32(MAC_ADDR_0_HIGH);
6760 addr0_low = tr32(MAC_ADDR_0_LOW);
6761 addr1_high = tr32(MAC_ADDR_1_HIGH);
6762 addr1_low = tr32(MAC_ADDR_1_LOW);
6764 /* Skip MAC addr 1 if ASF is using it. */
6765 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6766 !(addr1_high == 0 && addr1_low == 0))
6769 spin_lock_bh(&tp->lock);
6770 __tg3_set_mac_addr(tp, skip_mac_1);
6771 spin_unlock_bh(&tp->lock);
6776 /* tp->lock is held. */
6777 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6778 dma_addr_t mapping, u32 maxlen_flags,
6782 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6783 ((u64) mapping >> 32));
6785 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6786 ((u64) mapping & 0xffffffff));
6788 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6791 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6793 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6797 static void __tg3_set_rx_mode(struct net_device *);
6798 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6800 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6801 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6802 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6803 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6804 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6805 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6806 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6808 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6809 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6810 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6811 u32 val = ec->stats_block_coalesce_usecs;
6813 if (!netif_carrier_ok(tp->dev))
6816 tw32(HOSTCC_STAT_COAL_TICKS, val);
6820 /* tp->lock is held. */
6821 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6823 u32 val, rdmac_mode;
6825 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
6827 tg3_disable_ints(tp);
6831 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6833 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6834 tg3_abort_hw(tp, 1);
6838 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6841 err = tg3_chip_reset(tp);
6845 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6847 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6848 val = tr32(TG3_CPMU_CTRL);
6849 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6850 tw32(TG3_CPMU_CTRL, val);
6852 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6853 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6854 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6855 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6857 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6858 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6859 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6860 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6862 val = tr32(TG3_CPMU_HST_ACC);
6863 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6864 val |= CPMU_HST_ACC_MACCLK_6_25;
6865 tw32(TG3_CPMU_HST_ACC, val);
6868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6869 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6870 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6871 PCIE_PWR_MGMT_L1_THRESH_4MS;
6872 tw32(PCIE_PWR_MGMT_THRESH, val);
6874 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6875 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6877 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6880 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6881 val = tr32(TG3_PCIE_LNKCTL);
6882 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6883 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6885 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6886 tw32(TG3_PCIE_LNKCTL, val);
6889 /* This works around an issue with Athlon chipsets on
6890 * B3 tigon3 silicon. This bit has no effect on any
6891 * other revision. But do not set this on PCI Express
6892 * chips and don't even touch the clocks if the CPMU is present.
6894 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6895 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6896 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6897 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6900 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6901 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6902 val = tr32(TG3PCI_PCISTATE);
6903 val |= PCISTATE_RETRY_SAME_DMA;
6904 tw32(TG3PCI_PCISTATE, val);
6907 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6908 /* Allow reads and writes to the
6909 * APE register and memory space.
6911 val = tr32(TG3PCI_PCISTATE);
6912 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6913 PCISTATE_ALLOW_APE_SHMEM_WR;
6914 tw32(TG3PCI_PCISTATE, val);
6917 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6918 /* Enable some hw fixes. */
6919 val = tr32(TG3PCI_MSI_DATA);
6920 val |= (1 << 26) | (1 << 28) | (1 << 29);
6921 tw32(TG3PCI_MSI_DATA, val);
6924 /* Descriptor ring init may make accesses to the
6925 * NIC SRAM area to setup the TX descriptors, so we
6926 * can only do this after the hardware has been
6927 * successfully reset.
6929 err = tg3_init_rings(tp);
6933 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6934 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6935 /* This value is determined during the probe time DMA
6936 * engine test, tg3_test_dma.
6938 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6941 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6942 GRC_MODE_4X_NIC_SEND_RINGS |
6943 GRC_MODE_NO_TX_PHDR_CSUM |
6944 GRC_MODE_NO_RX_PHDR_CSUM);
6945 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6947 /* Pseudo-header checksum is done by hardware logic and not
6948 * the offload processers, so make the chip do the pseudo-
6949 * header checksums on receive. For transmit it is more
6950 * convenient to do the pseudo-header checksum in software
6951 * as Linux does that on transmit for us in all cases.
6953 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6957 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6959 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6960 val = tr32(GRC_MISC_CFG);
6962 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6963 tw32(GRC_MISC_CFG, val);
6965 /* Initialize MBUF/DESC pool. */
6966 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6968 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6969 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6971 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6973 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6974 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6975 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6977 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6980 fw_len = tp->fw_len;
6981 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6982 tw32(BUFMGR_MB_POOL_ADDR,
6983 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6984 tw32(BUFMGR_MB_POOL_SIZE,
6985 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6988 if (tp->dev->mtu <= ETH_DATA_LEN) {
6989 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6990 tp->bufmgr_config.mbuf_read_dma_low_water);
6991 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6992 tp->bufmgr_config.mbuf_mac_rx_low_water);
6993 tw32(BUFMGR_MB_HIGH_WATER,
6994 tp->bufmgr_config.mbuf_high_water);
6996 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6997 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6998 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6999 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7000 tw32(BUFMGR_MB_HIGH_WATER,
7001 tp->bufmgr_config.mbuf_high_water_jumbo);
7003 tw32(BUFMGR_DMA_LOW_WATER,
7004 tp->bufmgr_config.dma_low_water);
7005 tw32(BUFMGR_DMA_HIGH_WATER,
7006 tp->bufmgr_config.dma_high_water);
7008 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7009 for (i = 0; i < 2000; i++) {
7010 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7015 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7020 /* Setup replenish threshold. */
7021 val = tp->rx_pending / 8;
7024 else if (val > tp->rx_std_max_post)
7025 val = tp->rx_std_max_post;
7026 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7027 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7028 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7030 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7031 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7034 tw32(RCVBDI_STD_THRESH, val);
7036 /* Initialize TG3_BDINFO's at:
7037 * RCVDBDI_STD_BD: standard eth size rx ring
7038 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7039 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7042 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7043 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7044 * ring attribute flags
7045 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7047 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7048 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7050 * The size of each ring is fixed in the firmware, but the location is
7053 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7054 ((u64) tpr->rx_std_mapping >> 32));
7055 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7056 ((u64) tpr->rx_std_mapping & 0xffffffff));
7057 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7058 NIC_SRAM_RX_BUFFER_DESC);
7060 /* Disable the mini ring */
7061 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7062 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7063 BDINFO_FLAGS_DISABLED);
7065 /* Program the jumbo buffer descriptor ring control
7066 * blocks on those devices that have them.
7068 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7069 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7070 /* Setup replenish threshold. */
7071 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7073 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7074 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7075 ((u64) tpr->rx_jmb_mapping >> 32));
7076 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7077 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7078 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7079 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7080 BDINFO_FLAGS_USE_EXT_RECV);
7081 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7082 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7084 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7085 BDINFO_FLAGS_DISABLED);
7088 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7090 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7092 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7094 /* There is only one send ring on 5705/5750, no need to explicitly
7095 * disable the others.
7097 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7098 /* Clear out send RCB ring in SRAM. */
7099 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7100 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7101 BDINFO_FLAGS_DISABLED);
7104 tp->napi[0].tx_prod = 0;
7105 tp->napi[0].tx_cons = 0;
7106 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7108 val = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7109 tw32_mailbox(val, 0);
7111 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7112 tp->napi[0].tx_desc_mapping,
7113 (TG3_TX_RING_SIZE <<
7114 BDINFO_FLAGS_MAXLEN_SHIFT),
7115 NIC_SRAM_TX_BUFFER_DESC);
7117 /* There is only one receive return ring on 5705/5750, no need
7118 * to explicitly disable the others.
7120 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7121 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7122 i += TG3_BDINFO_SIZE) {
7123 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7124 BDINFO_FLAGS_DISABLED);
7128 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7130 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7131 tp->napi[0].rx_rcb_mapping,
7132 (TG3_RX_RCB_RING_SIZE(tp) <<
7133 BDINFO_FLAGS_MAXLEN_SHIFT),
7136 tpr->rx_std_ptr = tp->rx_pending;
7137 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7140 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7141 tp->rx_jumbo_pending : 0;
7142 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7145 /* Initialize MAC address and backoff seed. */
7146 __tg3_set_mac_addr(tp, 0);
7148 /* MTU + ethernet header + FCS + optional VLAN tag */
7149 tw32(MAC_RX_MTU_SIZE,
7150 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7152 /* The slot time is changed by tg3_setup_phy if we
7153 * run at gigabit with half duplex.
7155 tw32(MAC_TX_LENGTHS,
7156 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7157 (6 << TX_LENGTHS_IPG_SHIFT) |
7158 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7160 /* Receive rules. */
7161 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7162 tw32(RCVLPC_CONFIG, 0x0181);
7164 /* Calculate RDMAC_MODE setting early, we need it to determine
7165 * the RCVLPC_STATE_ENABLE mask.
7167 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7168 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7169 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7170 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7171 RDMAC_MODE_LNGREAD_ENAB);
7173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7174 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7175 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7176 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7177 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7178 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7180 /* If statement applies to 5705 and 5750 PCI devices only */
7181 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7182 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7183 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7184 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7186 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7187 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7188 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7189 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7193 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7194 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7196 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7197 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7199 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7200 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7201 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7203 /* Receive/send statistics. */
7204 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7205 val = tr32(RCVLPC_STATS_ENABLE);
7206 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7207 tw32(RCVLPC_STATS_ENABLE, val);
7208 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7209 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7210 val = tr32(RCVLPC_STATS_ENABLE);
7211 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7212 tw32(RCVLPC_STATS_ENABLE, val);
7214 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7216 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7217 tw32(SNDDATAI_STATSENAB, 0xffffff);
7218 tw32(SNDDATAI_STATSCTRL,
7219 (SNDDATAI_SCTRL_ENABLE |
7220 SNDDATAI_SCTRL_FASTUPD));
7222 /* Setup host coalescing engine. */
7223 tw32(HOSTCC_MODE, 0);
7224 for (i = 0; i < 2000; i++) {
7225 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7230 __tg3_set_coalesce(tp, &tp->coal);
7232 /* set status block DMA address */
7233 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7234 ((u64) tp->napi[0].status_mapping >> 32));
7235 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7236 ((u64) tp->napi[0].status_mapping & 0xffffffff));
7238 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7239 /* Status/statistics block address. See tg3_timer,
7240 * the tg3_periodic_fetch_stats call there, and
7241 * tg3_get_stats to see how this works for 5705/5750 chips.
7243 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7244 ((u64) tp->stats_mapping >> 32));
7245 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7246 ((u64) tp->stats_mapping & 0xffffffff));
7247 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7248 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7251 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7253 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7254 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7255 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7256 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7258 /* Clear statistics/status block in chip, and status block in ram. */
7259 for (i = NIC_SRAM_STATS_BLK;
7260 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7262 tg3_write_mem(tp, i, 0);
7265 memset(tp->napi[0].hw_status, 0, TG3_HW_STATUS_SIZE);
7267 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7268 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7269 /* reset to prevent losing 1st rx packet intermittently */
7270 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7274 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7275 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7278 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7279 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7280 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7281 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7282 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7283 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7284 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7287 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7288 * If TG3_FLG2_IS_NIC is zero, we should read the
7289 * register to preserve the GPIO settings for LOMs. The GPIOs,
7290 * whether used as inputs or outputs, are set by boot code after
7293 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7296 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7297 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7298 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7300 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7301 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7302 GRC_LCLCTRL_GPIO_OUTPUT3;
7304 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7305 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7307 tp->grc_local_ctrl &= ~gpio_mask;
7308 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7310 /* GPIO1 must be driven high for eeprom write protect */
7311 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7312 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7313 GRC_LCLCTRL_GPIO_OUTPUT1);
7315 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7318 tw32_mailbox_f(tp->napi[0].int_mbox, 0);
7320 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7321 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7325 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7326 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7327 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7328 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7329 WDMAC_MODE_LNGREAD_ENAB);
7331 /* If statement applies to 5705 and 5750 PCI devices only */
7332 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7333 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7335 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7336 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7337 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7339 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7340 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7341 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7342 val |= WDMAC_MODE_RX_ACCEL;
7346 /* Enable host coalescing bug fix */
7347 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7348 val |= WDMAC_MODE_STATUS_TAG_FIX;
7350 tw32_f(WDMAC_MODE, val);
7353 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7356 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7359 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7360 pcix_cmd |= PCI_X_CMD_READ_2K;
7361 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7362 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7363 pcix_cmd |= PCI_X_CMD_READ_2K;
7365 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7369 tw32_f(RDMAC_MODE, rdmac_mode);
7372 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7374 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7376 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7378 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7380 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7382 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7383 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7384 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7385 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7386 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7387 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7388 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7389 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7391 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7392 err = tg3_load_5701_a0_firmware_fix(tp);
7397 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7398 err = tg3_load_tso_firmware(tp);
7403 tp->tx_mode = TX_MODE_ENABLE;
7404 tw32_f(MAC_TX_MODE, tp->tx_mode);
7407 tp->rx_mode = RX_MODE_ENABLE;
7408 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7409 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7411 tw32_f(MAC_RX_MODE, tp->rx_mode);
7414 tw32(MAC_LED_CTRL, tp->led_ctrl);
7416 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7417 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7418 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7421 tw32_f(MAC_RX_MODE, tp->rx_mode);
7424 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7425 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7426 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7427 /* Set drive transmission level to 1.2V */
7428 /* only if the signal pre-emphasis bit is not set */
7429 val = tr32(MAC_SERDES_CFG);
7432 tw32(MAC_SERDES_CFG, val);
7434 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7435 tw32(MAC_SERDES_CFG, 0x616000);
7438 /* Prevent chip from dropping frames when flow control
7441 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7444 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7445 /* Use hardware link auto-negotiation */
7446 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7449 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7450 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7453 tmp = tr32(SERDES_RX_CTRL);
7454 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7455 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7456 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7457 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7460 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7461 if (tp->link_config.phy_is_low_power) {
7462 tp->link_config.phy_is_low_power = 0;
7463 tp->link_config.speed = tp->link_config.orig_speed;
7464 tp->link_config.duplex = tp->link_config.orig_duplex;
7465 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7468 err = tg3_setup_phy(tp, 0);
7472 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7473 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7476 /* Clear CRC stats. */
7477 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7478 tg3_writephy(tp, MII_TG3_TEST1,
7479 tmp | MII_TG3_TEST1_CRC_EN);
7480 tg3_readphy(tp, 0x14, &tmp);
7485 __tg3_set_rx_mode(tp->dev);
7487 /* Initialize receive rules. */
7488 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7489 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7490 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7491 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7493 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7494 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7498 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7502 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7504 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7506 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7508 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7510 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7512 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7514 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7516 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7518 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7520 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7522 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7524 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7526 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7528 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7536 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7537 /* Write our heartbeat update interval to APE. */
7538 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7539 APE_HOST_HEARTBEAT_INT_DISABLE);
7541 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7546 /* Called at device open time to get the chip ready for
7547 * packet processing. Invoked with tp->lock held.
7549 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7551 tg3_switch_clocks(tp);
7553 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7555 return tg3_reset_hw(tp, reset_phy);
7558 #define TG3_STAT_ADD32(PSTAT, REG) \
7559 do { u32 __val = tr32(REG); \
7560 (PSTAT)->low += __val; \
7561 if ((PSTAT)->low < __val) \
7562 (PSTAT)->high += 1; \
7565 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7567 struct tg3_hw_stats *sp = tp->hw_stats;
7569 if (!netif_carrier_ok(tp->dev))
7572 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7573 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7574 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7575 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7576 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7577 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7578 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7579 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7580 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7581 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7582 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7583 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7584 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7586 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7587 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7588 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7589 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7590 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7591 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7592 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7593 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7594 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7595 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7596 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7597 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7598 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7599 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7601 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7602 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7603 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7606 static void tg3_timer(unsigned long __opaque)
7608 struct tg3 *tp = (struct tg3 *) __opaque;
7613 spin_lock(&tp->lock);
7615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7616 /* All of this garbage is because when using non-tagged
7617 * IRQ status the mailbox/status_block protocol the chip
7618 * uses with the cpu is race prone.
7620 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7621 tw32(GRC_LOCAL_CTRL,
7622 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7624 tw32(HOSTCC_MODE, tp->coalesce_mode |
7625 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7628 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7629 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7630 spin_unlock(&tp->lock);
7631 schedule_work(&tp->reset_task);
7636 /* This part only runs once per second. */
7637 if (!--tp->timer_counter) {
7638 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7639 tg3_periodic_fetch_stats(tp);
7641 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7645 mac_stat = tr32(MAC_STATUS);
7648 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7649 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7651 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7655 tg3_setup_phy(tp, 0);
7656 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7657 u32 mac_stat = tr32(MAC_STATUS);
7660 if (netif_carrier_ok(tp->dev) &&
7661 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7664 if (! netif_carrier_ok(tp->dev) &&
7665 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7666 MAC_STATUS_SIGNAL_DET))) {
7670 if (!tp->serdes_counter) {
7673 ~MAC_MODE_PORT_MODE_MASK));
7675 tw32_f(MAC_MODE, tp->mac_mode);
7678 tg3_setup_phy(tp, 0);
7680 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7681 tg3_serdes_parallel_detect(tp);
7683 tp->timer_counter = tp->timer_multiplier;
7686 /* Heartbeat is only sent once every 2 seconds.
7688 * The heartbeat is to tell the ASF firmware that the host
7689 * driver is still alive. In the event that the OS crashes,
7690 * ASF needs to reset the hardware to free up the FIFO space
7691 * that may be filled with rx packets destined for the host.
7692 * If the FIFO is full, ASF will no longer function properly.
7694 * Unintended resets have been reported on real time kernels
7695 * where the timer doesn't run on time. Netpoll will also have
7698 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7699 * to check the ring condition when the heartbeat is expiring
7700 * before doing the reset. This will prevent most unintended
7703 if (!--tp->asf_counter) {
7704 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7705 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7706 tg3_wait_for_event_ack(tp);
7708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7709 FWCMD_NICDRV_ALIVE3);
7710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7711 /* 5 seconds timeout */
7712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7714 tg3_generate_fw_event(tp);
7716 tp->asf_counter = tp->asf_multiplier;
7719 spin_unlock(&tp->lock);
7722 tp->timer.expires = jiffies + tp->timer_offset;
7723 add_timer(&tp->timer);
7726 static int tg3_request_irq(struct tg3 *tp)
7729 unsigned long flags;
7730 char *name = tp->dev->name;
7732 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7734 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7736 flags = IRQF_SAMPLE_RANDOM;
7739 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7740 fn = tg3_interrupt_tagged;
7741 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7743 return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]);
7746 static int tg3_test_interrupt(struct tg3 *tp)
7748 struct tg3_napi *tnapi = &tp->napi[0];
7749 struct net_device *dev = tp->dev;
7750 int err, i, intr_ok = 0;
7752 if (!netif_running(dev))
7755 tg3_disable_ints(tp);
7757 free_irq(tp->pdev->irq, tnapi);
7759 err = request_irq(tp->pdev->irq, tg3_test_isr,
7760 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7764 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7765 tg3_enable_ints(tp);
7767 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7770 for (i = 0; i < 5; i++) {
7771 u32 int_mbox, misc_host_ctrl;
7773 int_mbox = tr32_mailbox(tnapi->int_mbox);
7774 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7776 if ((int_mbox != 0) ||
7777 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7785 tg3_disable_ints(tp);
7787 free_irq(tp->pdev->irq, tnapi);
7789 err = tg3_request_irq(tp);
7800 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7801 * successfully restored
7803 static int tg3_test_msi(struct tg3 *tp)
7808 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7811 /* Turn off SERR reporting in case MSI terminates with Master
7814 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7815 pci_write_config_word(tp->pdev, PCI_COMMAND,
7816 pci_cmd & ~PCI_COMMAND_SERR);
7818 err = tg3_test_interrupt(tp);
7820 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7825 /* other failures */
7829 /* MSI test failed, go back to INTx mode */
7830 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7831 "switching to INTx mode. Please report this failure to "
7832 "the PCI maintainer and include system chipset information.\n",
7835 free_irq(tp->pdev->irq, &tp->napi[0]);
7837 pci_disable_msi(tp->pdev);
7839 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7841 err = tg3_request_irq(tp);
7845 /* Need to reset the chip because the MSI cycle may have terminated
7846 * with Master Abort.
7848 tg3_full_lock(tp, 1);
7850 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7851 err = tg3_init_hw(tp, 1);
7853 tg3_full_unlock(tp);
7856 free_irq(tp->pdev->irq, &tp->napi[0]);
7861 static int tg3_request_firmware(struct tg3 *tp)
7863 const __be32 *fw_data;
7865 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7866 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7867 tp->dev->name, tp->fw_needed);
7871 fw_data = (void *)tp->fw->data;
7873 /* Firmware blob starts with version numbers, followed by
7874 * start address and _full_ length including BSS sections
7875 * (which must be longer than the actual data, of course
7878 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7879 if (tp->fw_len < (tp->fw->size - 12)) {
7880 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7881 tp->dev->name, tp->fw_len, tp->fw_needed);
7882 release_firmware(tp->fw);
7887 /* We no longer need firmware; we have it. */
7888 tp->fw_needed = NULL;
7892 static void tg3_ints_init(struct tg3 *tp)
7894 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7895 /* All MSI supporting chips should support tagged
7896 * status. Assert that this is the case.
7898 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7899 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7900 "Not using MSI.\n", tp->dev->name);
7901 } else if (pci_enable_msi(tp->pdev) == 0) {
7904 msi_mode = tr32(MSGINT_MODE);
7905 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7906 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7911 static void tg3_ints_fini(struct tg3 *tp)
7913 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7914 pci_disable_msi(tp->pdev);
7915 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7919 static int tg3_open(struct net_device *dev)
7921 struct tg3 *tp = netdev_priv(dev);
7924 if (tp->fw_needed) {
7925 err = tg3_request_firmware(tp);
7926 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7930 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7932 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7933 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7934 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7936 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7940 netif_carrier_off(tp->dev);
7942 err = tg3_set_power_state(tp, PCI_D0);
7946 tg3_full_lock(tp, 0);
7948 tg3_disable_ints(tp);
7949 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7951 tg3_full_unlock(tp);
7953 /* The placement of this call is tied
7954 * to the setup and use of Host TX descriptors.
7956 err = tg3_alloc_consistent(tp);
7962 napi_enable(&tp->napi[0].napi);
7964 err = tg3_request_irq(tp);
7969 tg3_full_lock(tp, 0);
7971 err = tg3_init_hw(tp, 1);
7973 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7976 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7977 tp->timer_offset = HZ;
7979 tp->timer_offset = HZ / 10;
7981 BUG_ON(tp->timer_offset > HZ);
7982 tp->timer_counter = tp->timer_multiplier =
7983 (HZ / tp->timer_offset);
7984 tp->asf_counter = tp->asf_multiplier =
7985 ((HZ / tp->timer_offset) * 2);
7987 init_timer(&tp->timer);
7988 tp->timer.expires = jiffies + tp->timer_offset;
7989 tp->timer.data = (unsigned long) tp;
7990 tp->timer.function = tg3_timer;
7993 tg3_full_unlock(tp);
7998 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7999 err = tg3_test_msi(tp);
8002 tg3_full_lock(tp, 0);
8003 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8005 tg3_full_unlock(tp);
8010 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8011 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8012 u32 val = tr32(PCIE_TRANSACTION_CFG);
8014 tw32(PCIE_TRANSACTION_CFG,
8015 val | PCIE_TRANS_CFG_1SHOT_MSI);
8022 tg3_full_lock(tp, 0);
8024 add_timer(&tp->timer);
8025 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8026 tg3_enable_ints(tp);
8028 tg3_full_unlock(tp);
8030 netif_start_queue(dev);
8035 free_irq(tp->pdev->irq, &tp->napi[0]);
8038 napi_disable(&tp->napi[0].napi);
8040 tg3_free_consistent(tp);
8045 /*static*/ void tg3_dump_state(struct tg3 *tp)
8047 u32 val32, val32_2, val32_3, val32_4, val32_5;
8050 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8052 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8053 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8054 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8058 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8059 tr32(MAC_MODE), tr32(MAC_STATUS));
8060 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8061 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8062 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8063 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8064 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8065 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8067 /* Send data initiator control block */
8068 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8069 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8070 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8071 tr32(SNDDATAI_STATSCTRL));
8073 /* Send data completion control block */
8074 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8076 /* Send BD ring selector block */
8077 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8078 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8080 /* Send BD initiator control block */
8081 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8082 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8084 /* Send BD completion control block */
8085 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8087 /* Receive list placement control block */
8088 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8089 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8090 printk(" RCVLPC_STATSCTRL[%08x]\n",
8091 tr32(RCVLPC_STATSCTRL));
8093 /* Receive data and receive BD initiator control block */
8094 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8095 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8097 /* Receive data completion control block */
8098 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8101 /* Receive BD initiator control block */
8102 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8103 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8105 /* Receive BD completion control block */
8106 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8107 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8109 /* Receive list selector control block */
8110 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8111 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8113 /* Mbuf cluster free block */
8114 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8115 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8117 /* Host coalescing control block */
8118 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8119 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8120 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8121 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8122 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8123 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8124 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8125 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8126 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8127 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8128 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8129 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8131 /* Memory arbiter control block */
8132 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8133 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8135 /* Buffer manager control block */
8136 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8137 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8138 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8139 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8140 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8141 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8142 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8143 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8145 /* Read DMA control block */
8146 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8147 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8149 /* Write DMA control block */
8150 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8151 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8153 /* DMA completion block */
8154 printk("DEBUG: DMAC_MODE[%08x]\n",
8158 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8159 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8160 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8161 tr32(GRC_LOCAL_CTRL));
8164 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8165 tr32(RCVDBDI_JUMBO_BD + 0x0),
8166 tr32(RCVDBDI_JUMBO_BD + 0x4),
8167 tr32(RCVDBDI_JUMBO_BD + 0x8),
8168 tr32(RCVDBDI_JUMBO_BD + 0xc));
8169 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8170 tr32(RCVDBDI_STD_BD + 0x0),
8171 tr32(RCVDBDI_STD_BD + 0x4),
8172 tr32(RCVDBDI_STD_BD + 0x8),
8173 tr32(RCVDBDI_STD_BD + 0xc));
8174 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8175 tr32(RCVDBDI_MINI_BD + 0x0),
8176 tr32(RCVDBDI_MINI_BD + 0x4),
8177 tr32(RCVDBDI_MINI_BD + 0x8),
8178 tr32(RCVDBDI_MINI_BD + 0xc));
8180 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8181 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8182 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8183 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8184 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8185 val32, val32_2, val32_3, val32_4);
8187 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8188 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8189 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8190 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8191 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8192 val32, val32_2, val32_3, val32_4);
8194 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8195 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8196 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8197 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8198 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8199 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8200 val32, val32_2, val32_3, val32_4, val32_5);
8202 /* SW status block */
8204 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8207 sblk->rx_jumbo_consumer,
8209 sblk->rx_mini_consumer,
8210 sblk->idx[0].rx_producer,
8211 sblk->idx[0].tx_consumer);
8213 /* SW statistics block */
8214 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8215 ((u32 *)tp->hw_stats)[0],
8216 ((u32 *)tp->hw_stats)[1],
8217 ((u32 *)tp->hw_stats)[2],
8218 ((u32 *)tp->hw_stats)[3]);
8221 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8222 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8223 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8224 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8225 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8227 /* NIC side send descriptors. */
8228 for (i = 0; i < 6; i++) {
8231 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8232 + (i * sizeof(struct tg3_tx_buffer_desc));
8233 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8235 readl(txd + 0x0), readl(txd + 0x4),
8236 readl(txd + 0x8), readl(txd + 0xc));
8239 /* NIC side RX descriptors. */
8240 for (i = 0; i < 6; i++) {
8243 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8244 + (i * sizeof(struct tg3_rx_buffer_desc));
8245 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8247 readl(rxd + 0x0), readl(rxd + 0x4),
8248 readl(rxd + 0x8), readl(rxd + 0xc));
8249 rxd += (4 * sizeof(u32));
8250 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8252 readl(rxd + 0x0), readl(rxd + 0x4),
8253 readl(rxd + 0x8), readl(rxd + 0xc));
8256 for (i = 0; i < 6; i++) {
8259 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8260 + (i * sizeof(struct tg3_rx_buffer_desc));
8261 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8263 readl(rxd + 0x0), readl(rxd + 0x4),
8264 readl(rxd + 0x8), readl(rxd + 0xc));
8265 rxd += (4 * sizeof(u32));
8266 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8268 readl(rxd + 0x0), readl(rxd + 0x4),
8269 readl(rxd + 0x8), readl(rxd + 0xc));
8274 static struct net_device_stats *tg3_get_stats(struct net_device *);
8275 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8277 static int tg3_close(struct net_device *dev)
8279 struct tg3 *tp = netdev_priv(dev);
8281 napi_disable(&tp->napi[0].napi);
8282 cancel_work_sync(&tp->reset_task);
8284 netif_stop_queue(dev);
8286 del_timer_sync(&tp->timer);
8288 tg3_full_lock(tp, 1);
8293 tg3_disable_ints(tp);
8295 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8297 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8299 tg3_full_unlock(tp);
8301 free_irq(tp->pdev->irq, &tp->napi[0]);
8305 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8306 sizeof(tp->net_stats_prev));
8307 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8308 sizeof(tp->estats_prev));
8310 tg3_free_consistent(tp);
8312 tg3_set_power_state(tp, PCI_D3hot);
8314 netif_carrier_off(tp->dev);
8319 static inline unsigned long get_stat64(tg3_stat64_t *val)
8323 #if (BITS_PER_LONG == 32)
8326 ret = ((u64)val->high << 32) | ((u64)val->low);
8331 static inline u64 get_estat64(tg3_stat64_t *val)
8333 return ((u64)val->high << 32) | ((u64)val->low);
8336 static unsigned long calc_crc_errors(struct tg3 *tp)
8338 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8340 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8341 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8342 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8345 spin_lock_bh(&tp->lock);
8346 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8347 tg3_writephy(tp, MII_TG3_TEST1,
8348 val | MII_TG3_TEST1_CRC_EN);
8349 tg3_readphy(tp, 0x14, &val);
8352 spin_unlock_bh(&tp->lock);
8354 tp->phy_crc_errors += val;
8356 return tp->phy_crc_errors;
8359 return get_stat64(&hw_stats->rx_fcs_errors);
8362 #define ESTAT_ADD(member) \
8363 estats->member = old_estats->member + \
8364 get_estat64(&hw_stats->member)
8366 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8368 struct tg3_ethtool_stats *estats = &tp->estats;
8369 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8370 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8375 ESTAT_ADD(rx_octets);
8376 ESTAT_ADD(rx_fragments);
8377 ESTAT_ADD(rx_ucast_packets);
8378 ESTAT_ADD(rx_mcast_packets);
8379 ESTAT_ADD(rx_bcast_packets);
8380 ESTAT_ADD(rx_fcs_errors);
8381 ESTAT_ADD(rx_align_errors);
8382 ESTAT_ADD(rx_xon_pause_rcvd);
8383 ESTAT_ADD(rx_xoff_pause_rcvd);
8384 ESTAT_ADD(rx_mac_ctrl_rcvd);
8385 ESTAT_ADD(rx_xoff_entered);
8386 ESTAT_ADD(rx_frame_too_long_errors);
8387 ESTAT_ADD(rx_jabbers);
8388 ESTAT_ADD(rx_undersize_packets);
8389 ESTAT_ADD(rx_in_length_errors);
8390 ESTAT_ADD(rx_out_length_errors);
8391 ESTAT_ADD(rx_64_or_less_octet_packets);
8392 ESTAT_ADD(rx_65_to_127_octet_packets);
8393 ESTAT_ADD(rx_128_to_255_octet_packets);
8394 ESTAT_ADD(rx_256_to_511_octet_packets);
8395 ESTAT_ADD(rx_512_to_1023_octet_packets);
8396 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8397 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8398 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8399 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8400 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8402 ESTAT_ADD(tx_octets);
8403 ESTAT_ADD(tx_collisions);
8404 ESTAT_ADD(tx_xon_sent);
8405 ESTAT_ADD(tx_xoff_sent);
8406 ESTAT_ADD(tx_flow_control);
8407 ESTAT_ADD(tx_mac_errors);
8408 ESTAT_ADD(tx_single_collisions);
8409 ESTAT_ADD(tx_mult_collisions);
8410 ESTAT_ADD(tx_deferred);
8411 ESTAT_ADD(tx_excessive_collisions);
8412 ESTAT_ADD(tx_late_collisions);
8413 ESTAT_ADD(tx_collide_2times);
8414 ESTAT_ADD(tx_collide_3times);
8415 ESTAT_ADD(tx_collide_4times);
8416 ESTAT_ADD(tx_collide_5times);
8417 ESTAT_ADD(tx_collide_6times);
8418 ESTAT_ADD(tx_collide_7times);
8419 ESTAT_ADD(tx_collide_8times);
8420 ESTAT_ADD(tx_collide_9times);
8421 ESTAT_ADD(tx_collide_10times);
8422 ESTAT_ADD(tx_collide_11times);
8423 ESTAT_ADD(tx_collide_12times);
8424 ESTAT_ADD(tx_collide_13times);
8425 ESTAT_ADD(tx_collide_14times);
8426 ESTAT_ADD(tx_collide_15times);
8427 ESTAT_ADD(tx_ucast_packets);
8428 ESTAT_ADD(tx_mcast_packets);
8429 ESTAT_ADD(tx_bcast_packets);
8430 ESTAT_ADD(tx_carrier_sense_errors);
8431 ESTAT_ADD(tx_discards);
8432 ESTAT_ADD(tx_errors);
8434 ESTAT_ADD(dma_writeq_full);
8435 ESTAT_ADD(dma_write_prioq_full);
8436 ESTAT_ADD(rxbds_empty);
8437 ESTAT_ADD(rx_discards);
8438 ESTAT_ADD(rx_errors);
8439 ESTAT_ADD(rx_threshold_hit);
8441 ESTAT_ADD(dma_readq_full);
8442 ESTAT_ADD(dma_read_prioq_full);
8443 ESTAT_ADD(tx_comp_queue_full);
8445 ESTAT_ADD(ring_set_send_prod_index);
8446 ESTAT_ADD(ring_status_update);
8447 ESTAT_ADD(nic_irqs);
8448 ESTAT_ADD(nic_avoided_irqs);
8449 ESTAT_ADD(nic_tx_threshold_hit);
8454 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8456 struct tg3 *tp = netdev_priv(dev);
8457 struct net_device_stats *stats = &tp->net_stats;
8458 struct net_device_stats *old_stats = &tp->net_stats_prev;
8459 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8464 stats->rx_packets = old_stats->rx_packets +
8465 get_stat64(&hw_stats->rx_ucast_packets) +
8466 get_stat64(&hw_stats->rx_mcast_packets) +
8467 get_stat64(&hw_stats->rx_bcast_packets);
8469 stats->tx_packets = old_stats->tx_packets +
8470 get_stat64(&hw_stats->tx_ucast_packets) +
8471 get_stat64(&hw_stats->tx_mcast_packets) +
8472 get_stat64(&hw_stats->tx_bcast_packets);
8474 stats->rx_bytes = old_stats->rx_bytes +
8475 get_stat64(&hw_stats->rx_octets);
8476 stats->tx_bytes = old_stats->tx_bytes +
8477 get_stat64(&hw_stats->tx_octets);
8479 stats->rx_errors = old_stats->rx_errors +
8480 get_stat64(&hw_stats->rx_errors);
8481 stats->tx_errors = old_stats->tx_errors +
8482 get_stat64(&hw_stats->tx_errors) +
8483 get_stat64(&hw_stats->tx_mac_errors) +
8484 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8485 get_stat64(&hw_stats->tx_discards);
8487 stats->multicast = old_stats->multicast +
8488 get_stat64(&hw_stats->rx_mcast_packets);
8489 stats->collisions = old_stats->collisions +
8490 get_stat64(&hw_stats->tx_collisions);
8492 stats->rx_length_errors = old_stats->rx_length_errors +
8493 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8494 get_stat64(&hw_stats->rx_undersize_packets);
8496 stats->rx_over_errors = old_stats->rx_over_errors +
8497 get_stat64(&hw_stats->rxbds_empty);
8498 stats->rx_frame_errors = old_stats->rx_frame_errors +
8499 get_stat64(&hw_stats->rx_align_errors);
8500 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8501 get_stat64(&hw_stats->tx_discards);
8502 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8503 get_stat64(&hw_stats->tx_carrier_sense_errors);
8505 stats->rx_crc_errors = old_stats->rx_crc_errors +
8506 calc_crc_errors(tp);
8508 stats->rx_missed_errors = old_stats->rx_missed_errors +
8509 get_stat64(&hw_stats->rx_discards);
8514 static inline u32 calc_crc(unsigned char *buf, int len)
8522 for (j = 0; j < len; j++) {
8525 for (k = 0; k < 8; k++) {
8539 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8541 /* accept or reject all multicast frames */
8542 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8543 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8544 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8545 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8548 static void __tg3_set_rx_mode(struct net_device *dev)
8550 struct tg3 *tp = netdev_priv(dev);
8553 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8554 RX_MODE_KEEP_VLAN_TAG);
8556 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8559 #if TG3_VLAN_TAG_USED
8561 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8562 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8564 /* By definition, VLAN is disabled always in this
8567 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8568 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8571 if (dev->flags & IFF_PROMISC) {
8572 /* Promiscuous mode. */
8573 rx_mode |= RX_MODE_PROMISC;
8574 } else if (dev->flags & IFF_ALLMULTI) {
8575 /* Accept all multicast. */
8576 tg3_set_multi (tp, 1);
8577 } else if (dev->mc_count < 1) {
8578 /* Reject all multicast. */
8579 tg3_set_multi (tp, 0);
8581 /* Accept one or more multicast(s). */
8582 struct dev_mc_list *mclist;
8584 u32 mc_filter[4] = { 0, };
8589 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8590 i++, mclist = mclist->next) {
8592 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8594 regidx = (bit & 0x60) >> 5;
8596 mc_filter[regidx] |= (1 << bit);
8599 tw32(MAC_HASH_REG_0, mc_filter[0]);
8600 tw32(MAC_HASH_REG_1, mc_filter[1]);
8601 tw32(MAC_HASH_REG_2, mc_filter[2]);
8602 tw32(MAC_HASH_REG_3, mc_filter[3]);
8605 if (rx_mode != tp->rx_mode) {
8606 tp->rx_mode = rx_mode;
8607 tw32_f(MAC_RX_MODE, rx_mode);
8612 static void tg3_set_rx_mode(struct net_device *dev)
8614 struct tg3 *tp = netdev_priv(dev);
8616 if (!netif_running(dev))
8619 tg3_full_lock(tp, 0);
8620 __tg3_set_rx_mode(dev);
8621 tg3_full_unlock(tp);
8624 #define TG3_REGDUMP_LEN (32 * 1024)
8626 static int tg3_get_regs_len(struct net_device *dev)
8628 return TG3_REGDUMP_LEN;
8631 static void tg3_get_regs(struct net_device *dev,
8632 struct ethtool_regs *regs, void *_p)
8635 struct tg3 *tp = netdev_priv(dev);
8641 memset(p, 0, TG3_REGDUMP_LEN);
8643 if (tp->link_config.phy_is_low_power)
8646 tg3_full_lock(tp, 0);
8648 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8649 #define GET_REG32_LOOP(base,len) \
8650 do { p = (u32 *)(orig_p + (base)); \
8651 for (i = 0; i < len; i += 4) \
8652 __GET_REG32((base) + i); \
8654 #define GET_REG32_1(reg) \
8655 do { p = (u32 *)(orig_p + (reg)); \
8656 __GET_REG32((reg)); \
8659 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8660 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8661 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8662 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8663 GET_REG32_1(SNDDATAC_MODE);
8664 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8665 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8666 GET_REG32_1(SNDBDC_MODE);
8667 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8668 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8669 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8670 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8671 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8672 GET_REG32_1(RCVDCC_MODE);
8673 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8674 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8675 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8676 GET_REG32_1(MBFREE_MODE);
8677 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8678 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8679 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8680 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8681 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8682 GET_REG32_1(RX_CPU_MODE);
8683 GET_REG32_1(RX_CPU_STATE);
8684 GET_REG32_1(RX_CPU_PGMCTR);
8685 GET_REG32_1(RX_CPU_HWBKPT);
8686 GET_REG32_1(TX_CPU_MODE);
8687 GET_REG32_1(TX_CPU_STATE);
8688 GET_REG32_1(TX_CPU_PGMCTR);
8689 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8690 GET_REG32_LOOP(FTQ_RESET, 0x120);
8691 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8692 GET_REG32_1(DMAC_MODE);
8693 GET_REG32_LOOP(GRC_MODE, 0x4c);
8694 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8695 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8698 #undef GET_REG32_LOOP
8701 tg3_full_unlock(tp);
8704 static int tg3_get_eeprom_len(struct net_device *dev)
8706 struct tg3 *tp = netdev_priv(dev);
8708 return tp->nvram_size;
8711 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8713 struct tg3 *tp = netdev_priv(dev);
8716 u32 i, offset, len, b_offset, b_count;
8719 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8722 if (tp->link_config.phy_is_low_power)
8725 offset = eeprom->offset;
8729 eeprom->magic = TG3_EEPROM_MAGIC;
8732 /* adjustments to start on required 4 byte boundary */
8733 b_offset = offset & 3;
8734 b_count = 4 - b_offset;
8735 if (b_count > len) {
8736 /* i.e. offset=1 len=2 */
8739 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8742 memcpy(data, ((char*)&val) + b_offset, b_count);
8745 eeprom->len += b_count;
8748 /* read bytes upto the last 4 byte boundary */
8749 pd = &data[eeprom->len];
8750 for (i = 0; i < (len - (len & 3)); i += 4) {
8751 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8756 memcpy(pd + i, &val, 4);
8761 /* read last bytes not ending on 4 byte boundary */
8762 pd = &data[eeprom->len];
8764 b_offset = offset + len - b_count;
8765 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8768 memcpy(pd, &val, b_count);
8769 eeprom->len += b_count;
8774 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8776 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8778 struct tg3 *tp = netdev_priv(dev);
8780 u32 offset, len, b_offset, odd_len;
8784 if (tp->link_config.phy_is_low_power)
8787 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8788 eeprom->magic != TG3_EEPROM_MAGIC)
8791 offset = eeprom->offset;
8794 if ((b_offset = (offset & 3))) {
8795 /* adjustments to start on required 4 byte boundary */
8796 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8807 /* adjustments to end on required 4 byte boundary */
8809 len = (len + 3) & ~3;
8810 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8816 if (b_offset || odd_len) {
8817 buf = kmalloc(len, GFP_KERNEL);
8821 memcpy(buf, &start, 4);
8823 memcpy(buf+len-4, &end, 4);
8824 memcpy(buf + b_offset, data, eeprom->len);
8827 ret = tg3_nvram_write_block(tp, offset, len, buf);
8835 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8837 struct tg3 *tp = netdev_priv(dev);
8839 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8840 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8842 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8845 cmd->supported = (SUPPORTED_Autoneg);
8847 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8848 cmd->supported |= (SUPPORTED_1000baseT_Half |
8849 SUPPORTED_1000baseT_Full);
8851 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8852 cmd->supported |= (SUPPORTED_100baseT_Half |
8853 SUPPORTED_100baseT_Full |
8854 SUPPORTED_10baseT_Half |
8855 SUPPORTED_10baseT_Full |
8857 cmd->port = PORT_TP;
8859 cmd->supported |= SUPPORTED_FIBRE;
8860 cmd->port = PORT_FIBRE;
8863 cmd->advertising = tp->link_config.advertising;
8864 if (netif_running(dev)) {
8865 cmd->speed = tp->link_config.active_speed;
8866 cmd->duplex = tp->link_config.active_duplex;
8868 cmd->phy_address = PHY_ADDR;
8869 cmd->transceiver = XCVR_INTERNAL;
8870 cmd->autoneg = tp->link_config.autoneg;
8876 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8878 struct tg3 *tp = netdev_priv(dev);
8880 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8881 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8883 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8886 if (cmd->autoneg != AUTONEG_ENABLE &&
8887 cmd->autoneg != AUTONEG_DISABLE)
8890 if (cmd->autoneg == AUTONEG_DISABLE &&
8891 cmd->duplex != DUPLEX_FULL &&
8892 cmd->duplex != DUPLEX_HALF)
8895 if (cmd->autoneg == AUTONEG_ENABLE) {
8896 u32 mask = ADVERTISED_Autoneg |
8898 ADVERTISED_Asym_Pause;
8900 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8901 mask |= ADVERTISED_1000baseT_Half |
8902 ADVERTISED_1000baseT_Full;
8904 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8905 mask |= ADVERTISED_100baseT_Half |
8906 ADVERTISED_100baseT_Full |
8907 ADVERTISED_10baseT_Half |
8908 ADVERTISED_10baseT_Full |
8911 mask |= ADVERTISED_FIBRE;
8913 if (cmd->advertising & ~mask)
8916 mask &= (ADVERTISED_1000baseT_Half |
8917 ADVERTISED_1000baseT_Full |
8918 ADVERTISED_100baseT_Half |
8919 ADVERTISED_100baseT_Full |
8920 ADVERTISED_10baseT_Half |
8921 ADVERTISED_10baseT_Full);
8923 cmd->advertising &= mask;
8925 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8926 if (cmd->speed != SPEED_1000)
8929 if (cmd->duplex != DUPLEX_FULL)
8932 if (cmd->speed != SPEED_100 &&
8933 cmd->speed != SPEED_10)
8938 tg3_full_lock(tp, 0);
8940 tp->link_config.autoneg = cmd->autoneg;
8941 if (cmd->autoneg == AUTONEG_ENABLE) {
8942 tp->link_config.advertising = (cmd->advertising |
8943 ADVERTISED_Autoneg);
8944 tp->link_config.speed = SPEED_INVALID;
8945 tp->link_config.duplex = DUPLEX_INVALID;
8947 tp->link_config.advertising = 0;
8948 tp->link_config.speed = cmd->speed;
8949 tp->link_config.duplex = cmd->duplex;
8952 tp->link_config.orig_speed = tp->link_config.speed;
8953 tp->link_config.orig_duplex = tp->link_config.duplex;
8954 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8956 if (netif_running(dev))
8957 tg3_setup_phy(tp, 1);
8959 tg3_full_unlock(tp);
8964 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8966 struct tg3 *tp = netdev_priv(dev);
8968 strcpy(info->driver, DRV_MODULE_NAME);
8969 strcpy(info->version, DRV_MODULE_VERSION);
8970 strcpy(info->fw_version, tp->fw_ver);
8971 strcpy(info->bus_info, pci_name(tp->pdev));
8974 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8976 struct tg3 *tp = netdev_priv(dev);
8978 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8979 device_can_wakeup(&tp->pdev->dev))
8980 wol->supported = WAKE_MAGIC;
8984 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8985 device_can_wakeup(&tp->pdev->dev))
8986 wol->wolopts = WAKE_MAGIC;
8987 memset(&wol->sopass, 0, sizeof(wol->sopass));
8990 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8992 struct tg3 *tp = netdev_priv(dev);
8993 struct device *dp = &tp->pdev->dev;
8995 if (wol->wolopts & ~WAKE_MAGIC)
8997 if ((wol->wolopts & WAKE_MAGIC) &&
8998 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9001 spin_lock_bh(&tp->lock);
9002 if (wol->wolopts & WAKE_MAGIC) {
9003 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9004 device_set_wakeup_enable(dp, true);
9006 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9007 device_set_wakeup_enable(dp, false);
9009 spin_unlock_bh(&tp->lock);
9014 static u32 tg3_get_msglevel(struct net_device *dev)
9016 struct tg3 *tp = netdev_priv(dev);
9017 return tp->msg_enable;
9020 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9022 struct tg3 *tp = netdev_priv(dev);
9023 tp->msg_enable = value;
9026 static int tg3_set_tso(struct net_device *dev, u32 value)
9028 struct tg3 *tp = netdev_priv(dev);
9030 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9035 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9036 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9038 dev->features |= NETIF_F_TSO6;
9039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9040 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9041 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9043 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9044 dev->features |= NETIF_F_TSO_ECN;
9046 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9048 return ethtool_op_set_tso(dev, value);
9051 static int tg3_nway_reset(struct net_device *dev)
9053 struct tg3 *tp = netdev_priv(dev);
9056 if (!netif_running(dev))
9059 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9062 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9063 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9065 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9069 spin_lock_bh(&tp->lock);
9071 tg3_readphy(tp, MII_BMCR, &bmcr);
9072 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9073 ((bmcr & BMCR_ANENABLE) ||
9074 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9075 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9079 spin_unlock_bh(&tp->lock);
9085 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9087 struct tg3 *tp = netdev_priv(dev);
9089 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9090 ering->rx_mini_max_pending = 0;
9091 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9092 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9094 ering->rx_jumbo_max_pending = 0;
9096 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9098 ering->rx_pending = tp->rx_pending;
9099 ering->rx_mini_pending = 0;
9100 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9101 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9103 ering->rx_jumbo_pending = 0;
9105 ering->tx_pending = tp->napi[0].tx_pending;
9108 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9110 struct tg3 *tp = netdev_priv(dev);
9111 int irq_sync = 0, err = 0;
9113 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9114 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9115 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9116 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9117 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9118 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9121 if (netif_running(dev)) {
9127 tg3_full_lock(tp, irq_sync);
9129 tp->rx_pending = ering->rx_pending;
9131 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9132 tp->rx_pending > 63)
9133 tp->rx_pending = 63;
9134 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9135 tp->napi[0].tx_pending = ering->tx_pending;
9137 if (netif_running(dev)) {
9138 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9139 err = tg3_restart_hw(tp, 1);
9141 tg3_netif_start(tp);
9144 tg3_full_unlock(tp);
9146 if (irq_sync && !err)
9152 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9154 struct tg3 *tp = netdev_priv(dev);
9156 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9158 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9159 epause->rx_pause = 1;
9161 epause->rx_pause = 0;
9163 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9164 epause->tx_pause = 1;
9166 epause->tx_pause = 0;
9169 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9171 struct tg3 *tp = netdev_priv(dev);
9174 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9175 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9178 if (epause->autoneg) {
9180 struct phy_device *phydev;
9182 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9184 if (epause->rx_pause) {
9185 if (epause->tx_pause)
9186 newadv = ADVERTISED_Pause;
9188 newadv = ADVERTISED_Pause |
9189 ADVERTISED_Asym_Pause;
9190 } else if (epause->tx_pause) {
9191 newadv = ADVERTISED_Asym_Pause;
9195 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9196 u32 oldadv = phydev->advertising &
9198 ADVERTISED_Asym_Pause);
9199 if (oldadv != newadv) {
9200 phydev->advertising &=
9201 ~(ADVERTISED_Pause |
9202 ADVERTISED_Asym_Pause);
9203 phydev->advertising |= newadv;
9204 err = phy_start_aneg(phydev);
9207 tp->link_config.advertising &=
9208 ~(ADVERTISED_Pause |
9209 ADVERTISED_Asym_Pause);
9210 tp->link_config.advertising |= newadv;
9213 if (epause->rx_pause)
9214 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9216 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9218 if (epause->tx_pause)
9219 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9221 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9223 if (netif_running(dev))
9224 tg3_setup_flow_control(tp, 0, 0);
9229 if (netif_running(dev)) {
9234 tg3_full_lock(tp, irq_sync);
9236 if (epause->autoneg)
9237 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9239 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9240 if (epause->rx_pause)
9241 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9243 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9244 if (epause->tx_pause)
9245 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9247 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9249 if (netif_running(dev)) {
9250 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9251 err = tg3_restart_hw(tp, 1);
9253 tg3_netif_start(tp);
9256 tg3_full_unlock(tp);
9262 static u32 tg3_get_rx_csum(struct net_device *dev)
9264 struct tg3 *tp = netdev_priv(dev);
9265 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9268 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9270 struct tg3 *tp = netdev_priv(dev);
9272 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9278 spin_lock_bh(&tp->lock);
9280 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9282 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9283 spin_unlock_bh(&tp->lock);
9288 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9290 struct tg3 *tp = netdev_priv(dev);
9292 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9298 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9299 ethtool_op_set_tx_ipv6_csum(dev, data);
9301 ethtool_op_set_tx_csum(dev, data);
9306 static int tg3_get_sset_count (struct net_device *dev, int sset)
9310 return TG3_NUM_TEST;
9312 return TG3_NUM_STATS;
9318 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9320 switch (stringset) {
9322 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
9325 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
9328 WARN_ON(1); /* we need a WARN() */
9333 static int tg3_phys_id(struct net_device *dev, u32 data)
9335 struct tg3 *tp = netdev_priv(dev);
9338 if (!netif_running(tp->dev))
9342 data = UINT_MAX / 2;
9344 for (i = 0; i < (data * 2); i++) {
9346 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9347 LED_CTRL_1000MBPS_ON |
9348 LED_CTRL_100MBPS_ON |
9349 LED_CTRL_10MBPS_ON |
9350 LED_CTRL_TRAFFIC_OVERRIDE |
9351 LED_CTRL_TRAFFIC_BLINK |
9352 LED_CTRL_TRAFFIC_LED);
9355 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9356 LED_CTRL_TRAFFIC_OVERRIDE);
9358 if (msleep_interruptible(500))
9361 tw32(MAC_LED_CTRL, tp->led_ctrl);
9365 static void tg3_get_ethtool_stats (struct net_device *dev,
9366 struct ethtool_stats *estats, u64 *tmp_stats)
9368 struct tg3 *tp = netdev_priv(dev);
9369 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9372 #define NVRAM_TEST_SIZE 0x100
9373 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9374 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9375 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9376 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9377 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9379 static int tg3_test_nvram(struct tg3 *tp)
9383 int i, j, k, err = 0, size;
9385 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9388 if (tg3_nvram_read(tp, 0, &magic) != 0)
9391 if (magic == TG3_EEPROM_MAGIC)
9392 size = NVRAM_TEST_SIZE;
9393 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9394 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9395 TG3_EEPROM_SB_FORMAT_1) {
9396 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9397 case TG3_EEPROM_SB_REVISION_0:
9398 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9400 case TG3_EEPROM_SB_REVISION_2:
9401 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9403 case TG3_EEPROM_SB_REVISION_3:
9404 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9411 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9412 size = NVRAM_SELFBOOT_HW_SIZE;
9416 buf = kmalloc(size, GFP_KERNEL);
9421 for (i = 0, j = 0; i < size; i += 4, j++) {
9422 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9429 /* Selfboot format */
9430 magic = be32_to_cpu(buf[0]);
9431 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9432 TG3_EEPROM_MAGIC_FW) {
9433 u8 *buf8 = (u8 *) buf, csum8 = 0;
9435 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9436 TG3_EEPROM_SB_REVISION_2) {
9437 /* For rev 2, the csum doesn't include the MBA. */
9438 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9440 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9443 for (i = 0; i < size; i++)
9456 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9457 TG3_EEPROM_MAGIC_HW) {
9458 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9459 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9460 u8 *buf8 = (u8 *) buf;
9462 /* Separate the parity bits and the data bytes. */
9463 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9464 if ((i == 0) || (i == 8)) {
9468 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9469 parity[k++] = buf8[i] & msk;
9476 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9477 parity[k++] = buf8[i] & msk;
9480 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9481 parity[k++] = buf8[i] & msk;
9484 data[j++] = buf8[i];
9488 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9489 u8 hw8 = hweight8(data[i]);
9491 if ((hw8 & 0x1) && parity[i])
9493 else if (!(hw8 & 0x1) && !parity[i])
9500 /* Bootstrap checksum at offset 0x10 */
9501 csum = calc_crc((unsigned char *) buf, 0x10);
9502 if (csum != be32_to_cpu(buf[0x10/4]))
9505 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9506 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9507 if (csum != be32_to_cpu(buf[0xfc/4]))
9517 #define TG3_SERDES_TIMEOUT_SEC 2
9518 #define TG3_COPPER_TIMEOUT_SEC 6
9520 static int tg3_test_link(struct tg3 *tp)
9524 if (!netif_running(tp->dev))
9527 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9528 max = TG3_SERDES_TIMEOUT_SEC;
9530 max = TG3_COPPER_TIMEOUT_SEC;
9532 for (i = 0; i < max; i++) {
9533 if (netif_carrier_ok(tp->dev))
9536 if (msleep_interruptible(1000))
9543 /* Only test the commonly used registers */
9544 static int tg3_test_registers(struct tg3 *tp)
9546 int i, is_5705, is_5750;
9547 u32 offset, read_mask, write_mask, val, save_val, read_val;
9551 #define TG3_FL_5705 0x1
9552 #define TG3_FL_NOT_5705 0x2
9553 #define TG3_FL_NOT_5788 0x4
9554 #define TG3_FL_NOT_5750 0x8
9558 /* MAC Control Registers */
9559 { MAC_MODE, TG3_FL_NOT_5705,
9560 0x00000000, 0x00ef6f8c },
9561 { MAC_MODE, TG3_FL_5705,
9562 0x00000000, 0x01ef6b8c },
9563 { MAC_STATUS, TG3_FL_NOT_5705,
9564 0x03800107, 0x00000000 },
9565 { MAC_STATUS, TG3_FL_5705,
9566 0x03800100, 0x00000000 },
9567 { MAC_ADDR_0_HIGH, 0x0000,
9568 0x00000000, 0x0000ffff },
9569 { MAC_ADDR_0_LOW, 0x0000,
9570 0x00000000, 0xffffffff },
9571 { MAC_RX_MTU_SIZE, 0x0000,
9572 0x00000000, 0x0000ffff },
9573 { MAC_TX_MODE, 0x0000,
9574 0x00000000, 0x00000070 },
9575 { MAC_TX_LENGTHS, 0x0000,
9576 0x00000000, 0x00003fff },
9577 { MAC_RX_MODE, TG3_FL_NOT_5705,
9578 0x00000000, 0x000007fc },
9579 { MAC_RX_MODE, TG3_FL_5705,
9580 0x00000000, 0x000007dc },
9581 { MAC_HASH_REG_0, 0x0000,
9582 0x00000000, 0xffffffff },
9583 { MAC_HASH_REG_1, 0x0000,
9584 0x00000000, 0xffffffff },
9585 { MAC_HASH_REG_2, 0x0000,
9586 0x00000000, 0xffffffff },
9587 { MAC_HASH_REG_3, 0x0000,
9588 0x00000000, 0xffffffff },
9590 /* Receive Data and Receive BD Initiator Control Registers. */
9591 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9592 0x00000000, 0xffffffff },
9593 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9594 0x00000000, 0xffffffff },
9595 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9596 0x00000000, 0x00000003 },
9597 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9598 0x00000000, 0xffffffff },
9599 { RCVDBDI_STD_BD+0, 0x0000,
9600 0x00000000, 0xffffffff },
9601 { RCVDBDI_STD_BD+4, 0x0000,
9602 0x00000000, 0xffffffff },
9603 { RCVDBDI_STD_BD+8, 0x0000,
9604 0x00000000, 0xffff0002 },
9605 { RCVDBDI_STD_BD+0xc, 0x0000,
9606 0x00000000, 0xffffffff },
9608 /* Receive BD Initiator Control Registers. */
9609 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9610 0x00000000, 0xffffffff },
9611 { RCVBDI_STD_THRESH, TG3_FL_5705,
9612 0x00000000, 0x000003ff },
9613 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9614 0x00000000, 0xffffffff },
9616 /* Host Coalescing Control Registers. */
9617 { HOSTCC_MODE, TG3_FL_NOT_5705,
9618 0x00000000, 0x00000004 },
9619 { HOSTCC_MODE, TG3_FL_5705,
9620 0x00000000, 0x000000f6 },
9621 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9622 0x00000000, 0xffffffff },
9623 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9624 0x00000000, 0x000003ff },
9625 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9626 0x00000000, 0xffffffff },
9627 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9628 0x00000000, 0x000003ff },
9629 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9630 0x00000000, 0xffffffff },
9631 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9632 0x00000000, 0x000000ff },
9633 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9634 0x00000000, 0xffffffff },
9635 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9636 0x00000000, 0x000000ff },
9637 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9638 0x00000000, 0xffffffff },
9639 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9640 0x00000000, 0xffffffff },
9641 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9642 0x00000000, 0xffffffff },
9643 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9644 0x00000000, 0x000000ff },
9645 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9646 0x00000000, 0xffffffff },
9647 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9648 0x00000000, 0x000000ff },
9649 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9650 0x00000000, 0xffffffff },
9651 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9652 0x00000000, 0xffffffff },
9653 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9654 0x00000000, 0xffffffff },
9655 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9656 0x00000000, 0xffffffff },
9657 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9658 0x00000000, 0xffffffff },
9659 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9660 0xffffffff, 0x00000000 },
9661 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9662 0xffffffff, 0x00000000 },
9664 /* Buffer Manager Control Registers. */
9665 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9666 0x00000000, 0x007fff80 },
9667 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9668 0x00000000, 0x007fffff },
9669 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9670 0x00000000, 0x0000003f },
9671 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9672 0x00000000, 0x000001ff },
9673 { BUFMGR_MB_HIGH_WATER, 0x0000,
9674 0x00000000, 0x000001ff },
9675 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9676 0xffffffff, 0x00000000 },
9677 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9678 0xffffffff, 0x00000000 },
9680 /* Mailbox Registers */
9681 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9682 0x00000000, 0x000001ff },
9683 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9684 0x00000000, 0x000001ff },
9685 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9686 0x00000000, 0x000007ff },
9687 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9688 0x00000000, 0x000001ff },
9690 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9693 is_5705 = is_5750 = 0;
9694 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9696 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9700 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9701 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9704 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9707 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9708 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9711 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9714 offset = (u32) reg_tbl[i].offset;
9715 read_mask = reg_tbl[i].read_mask;
9716 write_mask = reg_tbl[i].write_mask;
9718 /* Save the original register content */
9719 save_val = tr32(offset);
9721 /* Determine the read-only value. */
9722 read_val = save_val & read_mask;
9724 /* Write zero to the register, then make sure the read-only bits
9725 * are not changed and the read/write bits are all zeros.
9731 /* Test the read-only and read/write bits. */
9732 if (((val & read_mask) != read_val) || (val & write_mask))
9735 /* Write ones to all the bits defined by RdMask and WrMask, then
9736 * make sure the read-only bits are not changed and the
9737 * read/write bits are all ones.
9739 tw32(offset, read_mask | write_mask);
9743 /* Test the read-only bits. */
9744 if ((val & read_mask) != read_val)
9747 /* Test the read/write bits. */
9748 if ((val & write_mask) != write_mask)
9751 tw32(offset, save_val);
9757 if (netif_msg_hw(tp))
9758 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9760 tw32(offset, save_val);
9764 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9766 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9770 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9771 for (j = 0; j < len; j += 4) {
9774 tg3_write_mem(tp, offset + j, test_pattern[i]);
9775 tg3_read_mem(tp, offset + j, &val);
9776 if (val != test_pattern[i])
9783 static int tg3_test_memory(struct tg3 *tp)
9785 static struct mem_entry {
9788 } mem_tbl_570x[] = {
9789 { 0x00000000, 0x00b50},
9790 { 0x00002000, 0x1c000},
9791 { 0xffffffff, 0x00000}
9792 }, mem_tbl_5705[] = {
9793 { 0x00000100, 0x0000c},
9794 { 0x00000200, 0x00008},
9795 { 0x00004000, 0x00800},
9796 { 0x00006000, 0x01000},
9797 { 0x00008000, 0x02000},
9798 { 0x00010000, 0x0e000},
9799 { 0xffffffff, 0x00000}
9800 }, mem_tbl_5755[] = {
9801 { 0x00000200, 0x00008},
9802 { 0x00004000, 0x00800},
9803 { 0x00006000, 0x00800},
9804 { 0x00008000, 0x02000},
9805 { 0x00010000, 0x0c000},
9806 { 0xffffffff, 0x00000}
9807 }, mem_tbl_5906[] = {
9808 { 0x00000200, 0x00008},
9809 { 0x00004000, 0x00400},
9810 { 0x00006000, 0x00400},
9811 { 0x00008000, 0x01000},
9812 { 0x00010000, 0x01000},
9813 { 0xffffffff, 0x00000}
9815 struct mem_entry *mem_tbl;
9819 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9820 mem_tbl = mem_tbl_5755;
9821 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9822 mem_tbl = mem_tbl_5906;
9823 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9824 mem_tbl = mem_tbl_5705;
9826 mem_tbl = mem_tbl_570x;
9828 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9829 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9830 mem_tbl[i].len)) != 0)
9837 #define TG3_MAC_LOOPBACK 0
9838 #define TG3_PHY_LOOPBACK 1
9840 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9842 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9843 u32 desc_idx, coal_now;
9844 struct sk_buff *skb, *rx_skb;
9847 int num_pkts, tx_len, rx_len, i, err;
9848 struct tg3_rx_buffer_desc *desc;
9849 struct tg3_napi *tnapi, *rnapi;
9850 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
9852 tnapi = &tp->napi[0];
9853 rnapi = &tp->napi[0];
9854 coal_now = tnapi->coal_now | rnapi->coal_now;
9856 if (loopback_mode == TG3_MAC_LOOPBACK) {
9857 /* HW errata - mac loopback fails in some cases on 5780.
9858 * Normal traffic and PHY loopback are not affected by
9861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9864 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9865 MAC_MODE_PORT_INT_LPBACK;
9866 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9867 mac_mode |= MAC_MODE_LINK_POLARITY;
9868 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9869 mac_mode |= MAC_MODE_PORT_MODE_MII;
9871 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9872 tw32(MAC_MODE, mac_mode);
9873 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9876 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9877 tg3_phy_fet_toggle_apd(tp, false);
9878 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9880 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9882 tg3_phy_toggle_automdix(tp, 0);
9884 tg3_writephy(tp, MII_BMCR, val);
9887 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9888 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9890 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9891 mac_mode |= MAC_MODE_PORT_MODE_MII;
9893 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9895 /* reset to prevent losing 1st rx packet intermittently */
9896 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9897 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9899 tw32_f(MAC_RX_MODE, tp->rx_mode);
9901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9902 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9903 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9904 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9905 mac_mode |= MAC_MODE_LINK_POLARITY;
9906 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9907 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9909 tw32(MAC_MODE, mac_mode);
9917 skb = netdev_alloc_skb(tp->dev, tx_len);
9921 tx_data = skb_put(skb, tx_len);
9922 memcpy(tx_data, tp->dev->dev_addr, 6);
9923 memset(tx_data + 6, 0x0, 8);
9925 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9927 for (i = 14; i < tx_len; i++)
9928 tx_data[i] = (u8) (i & 0xff);
9930 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9932 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9937 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
9941 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
9946 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
9947 tr32_mailbox(tnapi->prodmbox);
9951 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9952 for (i = 0; i < 25; i++) {
9953 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9958 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
9959 rx_idx = rnapi->hw_status->idx[0].rx_producer;
9960 if ((tx_idx == tnapi->tx_prod) &&
9961 (rx_idx == (rx_start_idx + num_pkts)))
9965 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9968 if (tx_idx != tnapi->tx_prod)
9971 if (rx_idx != rx_start_idx + num_pkts)
9974 desc = &rnapi->rx_rcb[rx_start_idx];
9975 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9976 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9977 if (opaque_key != RXD_OPAQUE_RING_STD)
9980 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9981 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9984 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9985 if (rx_len != tx_len)
9988 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
9990 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
9991 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9993 for (i = 14; i < tx_len; i++) {
9994 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9999 /* tg3_free_rings will unmap and free the rx_skb */
10004 #define TG3_MAC_LOOPBACK_FAILED 1
10005 #define TG3_PHY_LOOPBACK_FAILED 2
10006 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10007 TG3_PHY_LOOPBACK_FAILED)
10009 static int tg3_test_loopback(struct tg3 *tp)
10014 if (!netif_running(tp->dev))
10015 return TG3_LOOPBACK_FAILED;
10017 err = tg3_reset_hw(tp, 1);
10019 return TG3_LOOPBACK_FAILED;
10021 /* Turn off gphy autopowerdown. */
10022 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10023 tg3_phy_toggle_apd(tp, false);
10025 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10029 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10031 /* Wait for up to 40 microseconds to acquire lock. */
10032 for (i = 0; i < 4; i++) {
10033 status = tr32(TG3_CPMU_MUTEX_GNT);
10034 if (status == CPMU_MUTEX_GNT_DRIVER)
10039 if (status != CPMU_MUTEX_GNT_DRIVER)
10040 return TG3_LOOPBACK_FAILED;
10042 /* Turn off link-based power management. */
10043 cpmuctrl = tr32(TG3_CPMU_CTRL);
10044 tw32(TG3_CPMU_CTRL,
10045 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10046 CPMU_CTRL_LINK_AWARE_MODE));
10049 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10050 err |= TG3_MAC_LOOPBACK_FAILED;
10052 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10053 tw32(TG3_CPMU_CTRL, cpmuctrl);
10055 /* Release the mutex */
10056 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10059 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10060 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10061 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10062 err |= TG3_PHY_LOOPBACK_FAILED;
10065 /* Re-enable gphy autopowerdown. */
10066 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10067 tg3_phy_toggle_apd(tp, true);
10072 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10075 struct tg3 *tp = netdev_priv(dev);
10077 if (tp->link_config.phy_is_low_power)
10078 tg3_set_power_state(tp, PCI_D0);
10080 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10082 if (tg3_test_nvram(tp) != 0) {
10083 etest->flags |= ETH_TEST_FL_FAILED;
10086 if (tg3_test_link(tp) != 0) {
10087 etest->flags |= ETH_TEST_FL_FAILED;
10090 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10091 int err, err2 = 0, irq_sync = 0;
10093 if (netif_running(dev)) {
10095 tg3_netif_stop(tp);
10099 tg3_full_lock(tp, irq_sync);
10101 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10102 err = tg3_nvram_lock(tp);
10103 tg3_halt_cpu(tp, RX_CPU_BASE);
10104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10105 tg3_halt_cpu(tp, TX_CPU_BASE);
10107 tg3_nvram_unlock(tp);
10109 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10112 if (tg3_test_registers(tp) != 0) {
10113 etest->flags |= ETH_TEST_FL_FAILED;
10116 if (tg3_test_memory(tp) != 0) {
10117 etest->flags |= ETH_TEST_FL_FAILED;
10120 if ((data[4] = tg3_test_loopback(tp)) != 0)
10121 etest->flags |= ETH_TEST_FL_FAILED;
10123 tg3_full_unlock(tp);
10125 if (tg3_test_interrupt(tp) != 0) {
10126 etest->flags |= ETH_TEST_FL_FAILED;
10130 tg3_full_lock(tp, 0);
10132 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10133 if (netif_running(dev)) {
10134 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10135 err2 = tg3_restart_hw(tp, 1);
10137 tg3_netif_start(tp);
10140 tg3_full_unlock(tp);
10142 if (irq_sync && !err2)
10145 if (tp->link_config.phy_is_low_power)
10146 tg3_set_power_state(tp, PCI_D3hot);
10150 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10152 struct mii_ioctl_data *data = if_mii(ifr);
10153 struct tg3 *tp = netdev_priv(dev);
10156 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10157 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10159 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10164 data->phy_id = PHY_ADDR;
10167 case SIOCGMIIREG: {
10170 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10171 break; /* We have no PHY */
10173 if (tp->link_config.phy_is_low_power)
10176 spin_lock_bh(&tp->lock);
10177 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10178 spin_unlock_bh(&tp->lock);
10180 data->val_out = mii_regval;
10186 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10187 break; /* We have no PHY */
10189 if (!capable(CAP_NET_ADMIN))
10192 if (tp->link_config.phy_is_low_power)
10195 spin_lock_bh(&tp->lock);
10196 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10197 spin_unlock_bh(&tp->lock);
10205 return -EOPNOTSUPP;
10208 #if TG3_VLAN_TAG_USED
10209 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10211 struct tg3 *tp = netdev_priv(dev);
10213 if (!netif_running(dev)) {
10218 tg3_netif_stop(tp);
10220 tg3_full_lock(tp, 0);
10224 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10225 __tg3_set_rx_mode(dev);
10227 tg3_netif_start(tp);
10229 tg3_full_unlock(tp);
10233 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10235 struct tg3 *tp = netdev_priv(dev);
10237 memcpy(ec, &tp->coal, sizeof(*ec));
10241 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10243 struct tg3 *tp = netdev_priv(dev);
10244 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10245 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10247 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10248 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10249 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10250 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10251 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10254 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10255 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10256 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10257 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10258 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10259 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10260 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10261 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10262 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10263 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10266 /* No rx interrupts will be generated if both are zero */
10267 if ((ec->rx_coalesce_usecs == 0) &&
10268 (ec->rx_max_coalesced_frames == 0))
10271 /* No tx interrupts will be generated if both are zero */
10272 if ((ec->tx_coalesce_usecs == 0) &&
10273 (ec->tx_max_coalesced_frames == 0))
10276 /* Only copy relevant parameters, ignore all others. */
10277 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10278 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10279 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10280 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10281 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10282 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10283 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10284 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10285 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10287 if (netif_running(dev)) {
10288 tg3_full_lock(tp, 0);
10289 __tg3_set_coalesce(tp, &tp->coal);
10290 tg3_full_unlock(tp);
10295 static const struct ethtool_ops tg3_ethtool_ops = {
10296 .get_settings = tg3_get_settings,
10297 .set_settings = tg3_set_settings,
10298 .get_drvinfo = tg3_get_drvinfo,
10299 .get_regs_len = tg3_get_regs_len,
10300 .get_regs = tg3_get_regs,
10301 .get_wol = tg3_get_wol,
10302 .set_wol = tg3_set_wol,
10303 .get_msglevel = tg3_get_msglevel,
10304 .set_msglevel = tg3_set_msglevel,
10305 .nway_reset = tg3_nway_reset,
10306 .get_link = ethtool_op_get_link,
10307 .get_eeprom_len = tg3_get_eeprom_len,
10308 .get_eeprom = tg3_get_eeprom,
10309 .set_eeprom = tg3_set_eeprom,
10310 .get_ringparam = tg3_get_ringparam,
10311 .set_ringparam = tg3_set_ringparam,
10312 .get_pauseparam = tg3_get_pauseparam,
10313 .set_pauseparam = tg3_set_pauseparam,
10314 .get_rx_csum = tg3_get_rx_csum,
10315 .set_rx_csum = tg3_set_rx_csum,
10316 .set_tx_csum = tg3_set_tx_csum,
10317 .set_sg = ethtool_op_set_sg,
10318 .set_tso = tg3_set_tso,
10319 .self_test = tg3_self_test,
10320 .get_strings = tg3_get_strings,
10321 .phys_id = tg3_phys_id,
10322 .get_ethtool_stats = tg3_get_ethtool_stats,
10323 .get_coalesce = tg3_get_coalesce,
10324 .set_coalesce = tg3_set_coalesce,
10325 .get_sset_count = tg3_get_sset_count,
10328 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10330 u32 cursize, val, magic;
10332 tp->nvram_size = EEPROM_CHIP_SIZE;
10334 if (tg3_nvram_read(tp, 0, &magic) != 0)
10337 if ((magic != TG3_EEPROM_MAGIC) &&
10338 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10339 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10343 * Size the chip by reading offsets at increasing powers of two.
10344 * When we encounter our validation signature, we know the addressing
10345 * has wrapped around, and thus have our chip size.
10349 while (cursize < tp->nvram_size) {
10350 if (tg3_nvram_read(tp, cursize, &val) != 0)
10359 tp->nvram_size = cursize;
10362 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10366 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10367 tg3_nvram_read(tp, 0, &val) != 0)
10370 /* Selfboot format */
10371 if (val != TG3_EEPROM_MAGIC) {
10372 tg3_get_eeprom_size(tp);
10376 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10378 /* This is confusing. We want to operate on the
10379 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10380 * call will read from NVRAM and byteswap the data
10381 * according to the byteswapping settings for all
10382 * other register accesses. This ensures the data we
10383 * want will always reside in the lower 16-bits.
10384 * However, the data in NVRAM is in LE format, which
10385 * means the data from the NVRAM read will always be
10386 * opposite the endianness of the CPU. The 16-bit
10387 * byteswap then brings the data to CPU endianness.
10389 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10393 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10396 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10400 nvcfg1 = tr32(NVRAM_CFG1);
10401 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10402 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10404 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10405 tw32(NVRAM_CFG1, nvcfg1);
10408 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10409 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10410 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10411 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10412 tp->nvram_jedecnum = JEDEC_ATMEL;
10413 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10414 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10416 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10417 tp->nvram_jedecnum = JEDEC_ATMEL;
10418 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10420 case FLASH_VENDOR_ATMEL_EEPROM:
10421 tp->nvram_jedecnum = JEDEC_ATMEL;
10422 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10423 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10425 case FLASH_VENDOR_ST:
10426 tp->nvram_jedecnum = JEDEC_ST;
10427 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10430 case FLASH_VENDOR_SAIFUN:
10431 tp->nvram_jedecnum = JEDEC_SAIFUN;
10432 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10434 case FLASH_VENDOR_SST_SMALL:
10435 case FLASH_VENDOR_SST_LARGE:
10436 tp->nvram_jedecnum = JEDEC_SST;
10437 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10441 tp->nvram_jedecnum = JEDEC_ATMEL;
10442 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10443 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10447 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10451 nvcfg1 = tr32(NVRAM_CFG1);
10453 /* NVRAM protection for TPM */
10454 if (nvcfg1 & (1 << 27))
10455 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10457 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10458 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10459 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10460 tp->nvram_jedecnum = JEDEC_ATMEL;
10461 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10463 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10464 tp->nvram_jedecnum = JEDEC_ATMEL;
10465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10466 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10468 case FLASH_5752VENDOR_ST_M45PE10:
10469 case FLASH_5752VENDOR_ST_M45PE20:
10470 case FLASH_5752VENDOR_ST_M45PE40:
10471 tp->nvram_jedecnum = JEDEC_ST;
10472 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10473 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10477 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10478 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10479 case FLASH_5752PAGE_SIZE_256:
10480 tp->nvram_pagesize = 256;
10482 case FLASH_5752PAGE_SIZE_512:
10483 tp->nvram_pagesize = 512;
10485 case FLASH_5752PAGE_SIZE_1K:
10486 tp->nvram_pagesize = 1024;
10488 case FLASH_5752PAGE_SIZE_2K:
10489 tp->nvram_pagesize = 2048;
10491 case FLASH_5752PAGE_SIZE_4K:
10492 tp->nvram_pagesize = 4096;
10494 case FLASH_5752PAGE_SIZE_264:
10495 tp->nvram_pagesize = 264;
10499 /* For eeprom, set pagesize to maximum eeprom size */
10500 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10502 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10503 tw32(NVRAM_CFG1, nvcfg1);
10507 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10509 u32 nvcfg1, protect = 0;
10511 nvcfg1 = tr32(NVRAM_CFG1);
10513 /* NVRAM protection for TPM */
10514 if (nvcfg1 & (1 << 27)) {
10515 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10519 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10521 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10522 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10523 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10524 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10525 tp->nvram_jedecnum = JEDEC_ATMEL;
10526 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10527 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10528 tp->nvram_pagesize = 264;
10529 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10530 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10531 tp->nvram_size = (protect ? 0x3e200 :
10532 TG3_NVRAM_SIZE_512KB);
10533 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10534 tp->nvram_size = (protect ? 0x1f200 :
10535 TG3_NVRAM_SIZE_256KB);
10537 tp->nvram_size = (protect ? 0x1f200 :
10538 TG3_NVRAM_SIZE_128KB);
10540 case FLASH_5752VENDOR_ST_M45PE10:
10541 case FLASH_5752VENDOR_ST_M45PE20:
10542 case FLASH_5752VENDOR_ST_M45PE40:
10543 tp->nvram_jedecnum = JEDEC_ST;
10544 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10545 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10546 tp->nvram_pagesize = 256;
10547 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10548 tp->nvram_size = (protect ?
10549 TG3_NVRAM_SIZE_64KB :
10550 TG3_NVRAM_SIZE_128KB);
10551 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10552 tp->nvram_size = (protect ?
10553 TG3_NVRAM_SIZE_64KB :
10554 TG3_NVRAM_SIZE_256KB);
10556 tp->nvram_size = (protect ?
10557 TG3_NVRAM_SIZE_128KB :
10558 TG3_NVRAM_SIZE_512KB);
10563 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10567 nvcfg1 = tr32(NVRAM_CFG1);
10569 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10570 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10571 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10572 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10573 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10574 tp->nvram_jedecnum = JEDEC_ATMEL;
10575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10576 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10578 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10579 tw32(NVRAM_CFG1, nvcfg1);
10581 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10582 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10583 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10584 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10585 tp->nvram_jedecnum = JEDEC_ATMEL;
10586 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10587 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10588 tp->nvram_pagesize = 264;
10590 case FLASH_5752VENDOR_ST_M45PE10:
10591 case FLASH_5752VENDOR_ST_M45PE20:
10592 case FLASH_5752VENDOR_ST_M45PE40:
10593 tp->nvram_jedecnum = JEDEC_ST;
10594 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10595 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10596 tp->nvram_pagesize = 256;
10601 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10603 u32 nvcfg1, protect = 0;
10605 nvcfg1 = tr32(NVRAM_CFG1);
10607 /* NVRAM protection for TPM */
10608 if (nvcfg1 & (1 << 27)) {
10609 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10613 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10615 case FLASH_5761VENDOR_ATMEL_ADB021D:
10616 case FLASH_5761VENDOR_ATMEL_ADB041D:
10617 case FLASH_5761VENDOR_ATMEL_ADB081D:
10618 case FLASH_5761VENDOR_ATMEL_ADB161D:
10619 case FLASH_5761VENDOR_ATMEL_MDB021D:
10620 case FLASH_5761VENDOR_ATMEL_MDB041D:
10621 case FLASH_5761VENDOR_ATMEL_MDB081D:
10622 case FLASH_5761VENDOR_ATMEL_MDB161D:
10623 tp->nvram_jedecnum = JEDEC_ATMEL;
10624 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10625 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10626 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10627 tp->nvram_pagesize = 256;
10629 case FLASH_5761VENDOR_ST_A_M45PE20:
10630 case FLASH_5761VENDOR_ST_A_M45PE40:
10631 case FLASH_5761VENDOR_ST_A_M45PE80:
10632 case FLASH_5761VENDOR_ST_A_M45PE16:
10633 case FLASH_5761VENDOR_ST_M_M45PE20:
10634 case FLASH_5761VENDOR_ST_M_M45PE40:
10635 case FLASH_5761VENDOR_ST_M_M45PE80:
10636 case FLASH_5761VENDOR_ST_M_M45PE16:
10637 tp->nvram_jedecnum = JEDEC_ST;
10638 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10639 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10640 tp->nvram_pagesize = 256;
10645 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10648 case FLASH_5761VENDOR_ATMEL_ADB161D:
10649 case FLASH_5761VENDOR_ATMEL_MDB161D:
10650 case FLASH_5761VENDOR_ST_A_M45PE16:
10651 case FLASH_5761VENDOR_ST_M_M45PE16:
10652 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10654 case FLASH_5761VENDOR_ATMEL_ADB081D:
10655 case FLASH_5761VENDOR_ATMEL_MDB081D:
10656 case FLASH_5761VENDOR_ST_A_M45PE80:
10657 case FLASH_5761VENDOR_ST_M_M45PE80:
10658 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10660 case FLASH_5761VENDOR_ATMEL_ADB041D:
10661 case FLASH_5761VENDOR_ATMEL_MDB041D:
10662 case FLASH_5761VENDOR_ST_A_M45PE40:
10663 case FLASH_5761VENDOR_ST_M_M45PE40:
10664 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10666 case FLASH_5761VENDOR_ATMEL_ADB021D:
10667 case FLASH_5761VENDOR_ATMEL_MDB021D:
10668 case FLASH_5761VENDOR_ST_A_M45PE20:
10669 case FLASH_5761VENDOR_ST_M_M45PE20:
10670 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10676 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10678 tp->nvram_jedecnum = JEDEC_ATMEL;
10679 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10680 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10683 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10687 nvcfg1 = tr32(NVRAM_CFG1);
10689 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10690 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10691 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10692 tp->nvram_jedecnum = JEDEC_ATMEL;
10693 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10694 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10696 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10697 tw32(NVRAM_CFG1, nvcfg1);
10699 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10700 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10701 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10702 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10703 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10704 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10705 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10706 tp->nvram_jedecnum = JEDEC_ATMEL;
10707 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10708 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10710 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10711 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10712 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10713 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10714 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10716 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10717 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10718 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10720 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10721 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10722 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10726 case FLASH_5752VENDOR_ST_M45PE10:
10727 case FLASH_5752VENDOR_ST_M45PE20:
10728 case FLASH_5752VENDOR_ST_M45PE40:
10729 tp->nvram_jedecnum = JEDEC_ST;
10730 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10731 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10733 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10734 case FLASH_5752VENDOR_ST_M45PE10:
10735 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10737 case FLASH_5752VENDOR_ST_M45PE20:
10738 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10740 case FLASH_5752VENDOR_ST_M45PE40:
10741 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10746 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10750 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10751 case FLASH_5752PAGE_SIZE_256:
10752 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10753 tp->nvram_pagesize = 256;
10755 case FLASH_5752PAGE_SIZE_512:
10756 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10757 tp->nvram_pagesize = 512;
10759 case FLASH_5752PAGE_SIZE_1K:
10760 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10761 tp->nvram_pagesize = 1024;
10763 case FLASH_5752PAGE_SIZE_2K:
10764 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10765 tp->nvram_pagesize = 2048;
10767 case FLASH_5752PAGE_SIZE_4K:
10768 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10769 tp->nvram_pagesize = 4096;
10771 case FLASH_5752PAGE_SIZE_264:
10772 tp->nvram_pagesize = 264;
10774 case FLASH_5752PAGE_SIZE_528:
10775 tp->nvram_pagesize = 528;
10780 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10781 static void __devinit tg3_nvram_init(struct tg3 *tp)
10783 tw32_f(GRC_EEPROM_ADDR,
10784 (EEPROM_ADDR_FSM_RESET |
10785 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10786 EEPROM_ADDR_CLKPERD_SHIFT)));
10790 /* Enable seeprom accesses. */
10791 tw32_f(GRC_LOCAL_CTRL,
10792 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10795 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10796 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10797 tp->tg3_flags |= TG3_FLAG_NVRAM;
10799 if (tg3_nvram_lock(tp)) {
10800 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10801 "tg3_nvram_init failed.\n", tp->dev->name);
10804 tg3_enable_nvram_access(tp);
10806 tp->nvram_size = 0;
10808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10809 tg3_get_5752_nvram_info(tp);
10810 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10811 tg3_get_5755_nvram_info(tp);
10812 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10815 tg3_get_5787_nvram_info(tp);
10816 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10817 tg3_get_5761_nvram_info(tp);
10818 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10819 tg3_get_5906_nvram_info(tp);
10820 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10821 tg3_get_57780_nvram_info(tp);
10823 tg3_get_nvram_info(tp);
10825 if (tp->nvram_size == 0)
10826 tg3_get_nvram_size(tp);
10828 tg3_disable_nvram_access(tp);
10829 tg3_nvram_unlock(tp);
10832 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10834 tg3_get_eeprom_size(tp);
10838 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10839 u32 offset, u32 len, u8 *buf)
10844 for (i = 0; i < len; i += 4) {
10850 memcpy(&data, buf + i, 4);
10853 * The SEEPROM interface expects the data to always be opposite
10854 * the native endian format. We accomplish this by reversing
10855 * all the operations that would have been performed on the
10856 * data from a call to tg3_nvram_read_be32().
10858 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10860 val = tr32(GRC_EEPROM_ADDR);
10861 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10863 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10865 tw32(GRC_EEPROM_ADDR, val |
10866 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10867 (addr & EEPROM_ADDR_ADDR_MASK) |
10868 EEPROM_ADDR_START |
10869 EEPROM_ADDR_WRITE);
10871 for (j = 0; j < 1000; j++) {
10872 val = tr32(GRC_EEPROM_ADDR);
10874 if (val & EEPROM_ADDR_COMPLETE)
10878 if (!(val & EEPROM_ADDR_COMPLETE)) {
10887 /* offset and length are dword aligned */
10888 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10892 u32 pagesize = tp->nvram_pagesize;
10893 u32 pagemask = pagesize - 1;
10897 tmp = kmalloc(pagesize, GFP_KERNEL);
10903 u32 phy_addr, page_off, size;
10905 phy_addr = offset & ~pagemask;
10907 for (j = 0; j < pagesize; j += 4) {
10908 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10909 (__be32 *) (tmp + j));
10916 page_off = offset & pagemask;
10923 memcpy(tmp + page_off, buf, size);
10925 offset = offset + (pagesize - page_off);
10927 tg3_enable_nvram_access(tp);
10930 * Before we can erase the flash page, we need
10931 * to issue a special "write enable" command.
10933 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10935 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10938 /* Erase the target page */
10939 tw32(NVRAM_ADDR, phy_addr);
10941 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10942 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10944 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10947 /* Issue another write enable to start the write. */
10948 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10950 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10953 for (j = 0; j < pagesize; j += 4) {
10956 data = *((__be32 *) (tmp + j));
10958 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10960 tw32(NVRAM_ADDR, phy_addr + j);
10962 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10966 nvram_cmd |= NVRAM_CMD_FIRST;
10967 else if (j == (pagesize - 4))
10968 nvram_cmd |= NVRAM_CMD_LAST;
10970 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10977 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10978 tg3_nvram_exec_cmd(tp, nvram_cmd);
10985 /* offset and length are dword aligned */
10986 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10991 for (i = 0; i < len; i += 4, offset += 4) {
10992 u32 page_off, phy_addr, nvram_cmd;
10995 memcpy(&data, buf + i, 4);
10996 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10998 page_off = offset % tp->nvram_pagesize;
11000 phy_addr = tg3_nvram_phys_addr(tp, offset);
11002 tw32(NVRAM_ADDR, phy_addr);
11004 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11006 if ((page_off == 0) || (i == 0))
11007 nvram_cmd |= NVRAM_CMD_FIRST;
11008 if (page_off == (tp->nvram_pagesize - 4))
11009 nvram_cmd |= NVRAM_CMD_LAST;
11011 if (i == (len - 4))
11012 nvram_cmd |= NVRAM_CMD_LAST;
11014 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11015 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11016 (tp->nvram_jedecnum == JEDEC_ST) &&
11017 (nvram_cmd & NVRAM_CMD_FIRST)) {
11019 if ((ret = tg3_nvram_exec_cmd(tp,
11020 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11025 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11026 /* We always do complete word writes to eeprom. */
11027 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11030 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11036 /* offset and length are dword aligned */
11037 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11041 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11042 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11043 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11047 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11048 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11053 ret = tg3_nvram_lock(tp);
11057 tg3_enable_nvram_access(tp);
11058 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11059 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11060 tw32(NVRAM_WRITE1, 0x406);
11062 grc_mode = tr32(GRC_MODE);
11063 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11065 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11066 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11068 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11072 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11076 grc_mode = tr32(GRC_MODE);
11077 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11079 tg3_disable_nvram_access(tp);
11080 tg3_nvram_unlock(tp);
11083 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11084 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11091 struct subsys_tbl_ent {
11092 u16 subsys_vendor, subsys_devid;
11096 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11097 /* Broadcom boards. */
11098 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11099 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11100 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11101 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11102 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11103 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11104 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11105 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11106 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11107 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11108 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11111 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11112 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11113 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11114 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11115 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11118 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11119 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11120 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11121 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11123 /* Compaq boards. */
11124 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11125 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11126 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11127 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11128 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11131 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11134 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11138 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11139 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11140 tp->pdev->subsystem_vendor) &&
11141 (subsys_id_to_phy_id[i].subsys_devid ==
11142 tp->pdev->subsystem_device))
11143 return &subsys_id_to_phy_id[i];
11148 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11153 /* On some early chips the SRAM cannot be accessed in D3hot state,
11154 * so need make sure we're in D0.
11156 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11157 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11158 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11161 /* Make sure register accesses (indirect or otherwise)
11162 * will function correctly.
11164 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11165 tp->misc_host_ctrl);
11167 /* The memory arbiter has to be enabled in order for SRAM accesses
11168 * to succeed. Normally on powerup the tg3 chip firmware will make
11169 * sure it is enabled, but other entities such as system netboot
11170 * code might disable it.
11172 val = tr32(MEMARB_MODE);
11173 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11175 tp->phy_id = PHY_ID_INVALID;
11176 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11178 /* Assume an onboard device and WOL capable by default. */
11179 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11182 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11183 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11184 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11186 val = tr32(VCPU_CFGSHDW);
11187 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11188 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11189 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11190 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11191 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11195 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11196 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11197 u32 nic_cfg, led_cfg;
11198 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11199 int eeprom_phy_serdes = 0;
11201 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11202 tp->nic_sram_data_cfg = nic_cfg;
11204 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11205 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11206 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11207 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11208 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11209 (ver > 0) && (ver < 0x100))
11210 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11213 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11215 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11216 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11217 eeprom_phy_serdes = 1;
11219 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11220 if (nic_phy_id != 0) {
11221 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11222 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11224 eeprom_phy_id = (id1 >> 16) << 10;
11225 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11226 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11230 tp->phy_id = eeprom_phy_id;
11231 if (eeprom_phy_serdes) {
11232 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11233 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11235 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11238 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11239 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11240 SHASTA_EXT_LED_MODE_MASK);
11242 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11246 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11247 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11250 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11251 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11254 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11255 tp->led_ctrl = LED_CTRL_MODE_MAC;
11257 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11258 * read on some older 5700/5701 bootcode.
11260 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11262 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11264 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11268 case SHASTA_EXT_LED_SHARED:
11269 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11270 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11271 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11272 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11273 LED_CTRL_MODE_PHY_2);
11276 case SHASTA_EXT_LED_MAC:
11277 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11280 case SHASTA_EXT_LED_COMBO:
11281 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11282 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11283 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11284 LED_CTRL_MODE_PHY_2);
11289 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11291 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11292 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11294 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11295 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11297 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11298 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11299 if ((tp->pdev->subsystem_vendor ==
11300 PCI_VENDOR_ID_ARIMA) &&
11301 (tp->pdev->subsystem_device == 0x205a ||
11302 tp->pdev->subsystem_device == 0x2063))
11303 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11305 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11306 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11309 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11310 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11311 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11312 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11315 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11316 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11317 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11319 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11320 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11321 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11323 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11324 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11325 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11327 if (cfg2 & (1 << 17))
11328 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11330 /* serdes signal pre-emphasis in register 0x590 set by */
11331 /* bootcode if bit 18 is set */
11332 if (cfg2 & (1 << 18))
11333 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11335 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11336 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11337 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11338 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11340 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11343 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11344 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11345 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11348 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11349 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11350 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11351 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11352 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11353 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11356 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11357 device_set_wakeup_enable(&tp->pdev->dev,
11358 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11361 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11366 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11367 tw32(OTP_CTRL, cmd);
11369 /* Wait for up to 1 ms for command to execute. */
11370 for (i = 0; i < 100; i++) {
11371 val = tr32(OTP_STATUS);
11372 if (val & OTP_STATUS_CMD_DONE)
11377 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11380 /* Read the gphy configuration from the OTP region of the chip. The gphy
11381 * configuration is a 32-bit value that straddles the alignment boundary.
11382 * We do two 32-bit reads and then shift and merge the results.
11384 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11386 u32 bhalf_otp, thalf_otp;
11388 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11390 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11393 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11395 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11398 thalf_otp = tr32(OTP_READ_DATA);
11400 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11402 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11405 bhalf_otp = tr32(OTP_READ_DATA);
11407 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11410 static int __devinit tg3_phy_probe(struct tg3 *tp)
11412 u32 hw_phy_id_1, hw_phy_id_2;
11413 u32 hw_phy_id, hw_phy_id_masked;
11416 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11417 return tg3_phy_init(tp);
11419 /* Reading the PHY ID register can conflict with ASF
11420 * firmware access to the PHY hardware.
11423 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11424 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11425 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11427 /* Now read the physical PHY_ID from the chip and verify
11428 * that it is sane. If it doesn't look good, we fall back
11429 * to either the hard-coded table based PHY_ID and failing
11430 * that the value found in the eeprom area.
11432 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11433 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11435 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11436 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11437 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11439 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11442 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11443 tp->phy_id = hw_phy_id;
11444 if (hw_phy_id_masked == PHY_ID_BCM8002)
11445 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11447 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11449 if (tp->phy_id != PHY_ID_INVALID) {
11450 /* Do nothing, phy ID already set up in
11451 * tg3_get_eeprom_hw_cfg().
11454 struct subsys_tbl_ent *p;
11456 /* No eeprom signature? Try the hardcoded
11457 * subsys device table.
11459 p = lookup_by_subsys(tp);
11463 tp->phy_id = p->phy_id;
11465 tp->phy_id == PHY_ID_BCM8002)
11466 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11470 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11471 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11472 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11473 u32 bmsr, adv_reg, tg3_ctrl, mask;
11475 tg3_readphy(tp, MII_BMSR, &bmsr);
11476 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11477 (bmsr & BMSR_LSTATUS))
11478 goto skip_phy_reset;
11480 err = tg3_phy_reset(tp);
11484 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11485 ADVERTISE_100HALF | ADVERTISE_100FULL |
11486 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11488 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11489 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11490 MII_TG3_CTRL_ADV_1000_FULL);
11491 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11492 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11493 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11494 MII_TG3_CTRL_ENABLE_AS_MASTER);
11497 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11498 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11499 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11500 if (!tg3_copper_is_advertising_all(tp, mask)) {
11501 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11503 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11504 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11506 tg3_writephy(tp, MII_BMCR,
11507 BMCR_ANENABLE | BMCR_ANRESTART);
11509 tg3_phy_set_wirespeed(tp);
11511 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11512 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11513 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11517 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11518 err = tg3_init_5401phy_dsp(tp);
11523 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11524 err = tg3_init_5401phy_dsp(tp);
11527 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11528 tp->link_config.advertising =
11529 (ADVERTISED_1000baseT_Half |
11530 ADVERTISED_1000baseT_Full |
11531 ADVERTISED_Autoneg |
11533 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11534 tp->link_config.advertising &=
11535 ~(ADVERTISED_1000baseT_Half |
11536 ADVERTISED_1000baseT_Full);
11541 static void __devinit tg3_read_partno(struct tg3 *tp)
11543 unsigned char vpd_data[256]; /* in little-endian format */
11547 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11548 tg3_nvram_read(tp, 0x0, &magic))
11549 goto out_not_found;
11551 if (magic == TG3_EEPROM_MAGIC) {
11552 for (i = 0; i < 256; i += 4) {
11555 /* The data is in little-endian format in NVRAM.
11556 * Use the big-endian read routines to preserve
11557 * the byte order as it exists in NVRAM.
11559 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11560 goto out_not_found;
11562 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11567 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11568 for (i = 0; i < 256; i += 4) {
11573 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11575 while (j++ < 100) {
11576 pci_read_config_word(tp->pdev, vpd_cap +
11577 PCI_VPD_ADDR, &tmp16);
11578 if (tmp16 & 0x8000)
11582 if (!(tmp16 & 0x8000))
11583 goto out_not_found;
11585 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11587 v = cpu_to_le32(tmp);
11588 memcpy(&vpd_data[i], &v, sizeof(v));
11592 /* Now parse and find the part number. */
11593 for (i = 0; i < 254; ) {
11594 unsigned char val = vpd_data[i];
11595 unsigned int block_end;
11597 if (val == 0x82 || val == 0x91) {
11600 (vpd_data[i + 2] << 8)));
11605 goto out_not_found;
11607 block_end = (i + 3 +
11609 (vpd_data[i + 2] << 8)));
11612 if (block_end > 256)
11613 goto out_not_found;
11615 while (i < (block_end - 2)) {
11616 if (vpd_data[i + 0] == 'P' &&
11617 vpd_data[i + 1] == 'N') {
11618 int partno_len = vpd_data[i + 2];
11621 if (partno_len > 24 || (partno_len + i) > 256)
11622 goto out_not_found;
11624 memcpy(tp->board_part_number,
11625 &vpd_data[i], partno_len);
11630 i += 3 + vpd_data[i + 2];
11633 /* Part number not found. */
11634 goto out_not_found;
11638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11639 strcpy(tp->board_part_number, "BCM95906");
11640 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11641 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11642 strcpy(tp->board_part_number, "BCM57780");
11643 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11644 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11645 strcpy(tp->board_part_number, "BCM57760");
11646 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11648 strcpy(tp->board_part_number, "BCM57790");
11649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11651 strcpy(tp->board_part_number, "BCM57788");
11653 strcpy(tp->board_part_number, "none");
11656 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11660 if (tg3_nvram_read(tp, offset, &val) ||
11661 (val & 0xfc000000) != 0x0c000000 ||
11662 tg3_nvram_read(tp, offset + 4, &val) ||
11669 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11671 u32 val, offset, start, ver_offset;
11673 bool newver = false;
11675 if (tg3_nvram_read(tp, 0xc, &offset) ||
11676 tg3_nvram_read(tp, 0x4, &start))
11679 offset = tg3_nvram_logical_addr(tp, offset);
11681 if (tg3_nvram_read(tp, offset, &val))
11684 if ((val & 0xfc000000) == 0x0c000000) {
11685 if (tg3_nvram_read(tp, offset + 4, &val))
11693 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11696 offset = offset + ver_offset - start;
11697 for (i = 0; i < 16; i += 4) {
11699 if (tg3_nvram_read_be32(tp, offset + i, &v))
11702 memcpy(tp->fw_ver + i, &v, sizeof(v));
11707 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11710 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11711 TG3_NVM_BCVER_MAJSFT;
11712 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11713 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11717 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11719 u32 val, major, minor;
11721 /* Use native endian representation */
11722 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11725 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11726 TG3_NVM_HWSB_CFG1_MAJSFT;
11727 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11728 TG3_NVM_HWSB_CFG1_MINSFT;
11730 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11733 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11735 u32 offset, major, minor, build;
11737 tp->fw_ver[0] = 's';
11738 tp->fw_ver[1] = 'b';
11739 tp->fw_ver[2] = '\0';
11741 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11744 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11745 case TG3_EEPROM_SB_REVISION_0:
11746 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11748 case TG3_EEPROM_SB_REVISION_2:
11749 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11751 case TG3_EEPROM_SB_REVISION_3:
11752 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11758 if (tg3_nvram_read(tp, offset, &val))
11761 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11762 TG3_EEPROM_SB_EDH_BLD_SHFT;
11763 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11764 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11765 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11767 if (minor > 99 || build > 26)
11770 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11773 tp->fw_ver[8] = 'a' + build - 1;
11774 tp->fw_ver[9] = '\0';
11778 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11780 u32 val, offset, start;
11783 for (offset = TG3_NVM_DIR_START;
11784 offset < TG3_NVM_DIR_END;
11785 offset += TG3_NVM_DIRENT_SIZE) {
11786 if (tg3_nvram_read(tp, offset, &val))
11789 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11793 if (offset == TG3_NVM_DIR_END)
11796 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11797 start = 0x08000000;
11798 else if (tg3_nvram_read(tp, offset - 4, &start))
11801 if (tg3_nvram_read(tp, offset + 4, &offset) ||
11802 !tg3_fw_img_is_valid(tp, offset) ||
11803 tg3_nvram_read(tp, offset + 8, &val))
11806 offset += val - start;
11808 vlen = strlen(tp->fw_ver);
11810 tp->fw_ver[vlen++] = ',';
11811 tp->fw_ver[vlen++] = ' ';
11813 for (i = 0; i < 4; i++) {
11815 if (tg3_nvram_read_be32(tp, offset, &v))
11818 offset += sizeof(v);
11820 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11821 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11825 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11830 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11835 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11836 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11839 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11840 if (apedata != APE_SEG_SIG_MAGIC)
11843 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11844 if (!(apedata & APE_FW_STATUS_READY))
11847 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11849 vlen = strlen(tp->fw_ver);
11851 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11852 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11853 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11854 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11855 (apedata & APE_FW_VERSION_BLDMSK));
11858 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11862 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11863 tp->fw_ver[0] = 's';
11864 tp->fw_ver[1] = 'b';
11865 tp->fw_ver[2] = '\0';
11870 if (tg3_nvram_read(tp, 0, &val))
11873 if (val == TG3_EEPROM_MAGIC)
11874 tg3_read_bc_ver(tp);
11875 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11876 tg3_read_sb_ver(tp, val);
11877 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11878 tg3_read_hwsb_ver(tp);
11882 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11883 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11886 tg3_read_mgmtfw_ver(tp);
11888 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11891 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11893 static int __devinit tg3_get_invariants(struct tg3 *tp)
11895 static struct pci_device_id write_reorder_chipsets[] = {
11896 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11897 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11898 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11899 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11900 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11901 PCI_DEVICE_ID_VIA_8385_0) },
11905 u32 pci_state_reg, grc_misc_cfg;
11910 /* Force memory write invalidate off. If we leave it on,
11911 * then on 5700_BX chips we have to enable a workaround.
11912 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11913 * to match the cacheline size. The Broadcom driver have this
11914 * workaround but turns MWI off all the times so never uses
11915 * it. This seems to suggest that the workaround is insufficient.
11917 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11918 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11919 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11921 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11922 * has the register indirect write enable bit set before
11923 * we try to access any of the MMIO registers. It is also
11924 * critical that the PCI-X hw workaround situation is decided
11925 * before that as well.
11927 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11930 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11931 MISC_HOST_CTRL_CHIPREV_SHIFT);
11932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11933 u32 prod_id_asic_rev;
11935 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11936 &prod_id_asic_rev);
11937 tp->pci_chip_rev_id = prod_id_asic_rev;
11940 /* Wrong chip ID in 5752 A0. This code can be removed later
11941 * as A0 is not in production.
11943 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11944 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11946 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11947 * we need to disable memory and use config. cycles
11948 * only to access all registers. The 5702/03 chips
11949 * can mistakenly decode the special cycles from the
11950 * ICH chipsets as memory write cycles, causing corruption
11951 * of register and memory space. Only certain ICH bridges
11952 * will drive special cycles with non-zero data during the
11953 * address phase which can fall within the 5703's address
11954 * range. This is not an ICH bug as the PCI spec allows
11955 * non-zero address during special cycles. However, only
11956 * these ICH bridges are known to drive non-zero addresses
11957 * during special cycles.
11959 * Since special cycles do not cross PCI bridges, we only
11960 * enable this workaround if the 5703 is on the secondary
11961 * bus of these ICH bridges.
11963 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11964 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11965 static struct tg3_dev_id {
11969 } ich_chipsets[] = {
11970 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11972 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11974 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11976 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11980 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11981 struct pci_dev *bridge = NULL;
11983 while (pci_id->vendor != 0) {
11984 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11990 if (pci_id->rev != PCI_ANY_ID) {
11991 if (bridge->revision > pci_id->rev)
11994 if (bridge->subordinate &&
11995 (bridge->subordinate->number ==
11996 tp->pdev->bus->number)) {
11998 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11999 pci_dev_put(bridge);
12005 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12006 static struct tg3_dev_id {
12009 } bridge_chipsets[] = {
12010 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12011 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12014 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12015 struct pci_dev *bridge = NULL;
12017 while (pci_id->vendor != 0) {
12018 bridge = pci_get_device(pci_id->vendor,
12025 if (bridge->subordinate &&
12026 (bridge->subordinate->number <=
12027 tp->pdev->bus->number) &&
12028 (bridge->subordinate->subordinate >=
12029 tp->pdev->bus->number)) {
12030 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12031 pci_dev_put(bridge);
12037 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12038 * DMA addresses > 40-bit. This bridge may have other additional
12039 * 57xx devices behind it in some 4-port NIC designs for example.
12040 * Any tg3 device found behind the bridge will also need the 40-bit
12043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12045 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12046 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12047 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12050 struct pci_dev *bridge = NULL;
12053 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12054 PCI_DEVICE_ID_SERVERWORKS_EPB,
12056 if (bridge && bridge->subordinate &&
12057 (bridge->subordinate->number <=
12058 tp->pdev->bus->number) &&
12059 (bridge->subordinate->subordinate >=
12060 tp->pdev->bus->number)) {
12061 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12062 pci_dev_put(bridge);
12068 /* Initialize misc host control in PCI block. */
12069 tp->misc_host_ctrl |= (misc_ctrl_reg &
12070 MISC_HOST_CTRL_CHIPREV);
12071 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12072 tp->misc_host_ctrl);
12074 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12075 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12076 tp->pdev_peer = tg3_find_peer(tp);
12078 /* Intentionally exclude ASIC_REV_5906 */
12079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12082 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12083 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12085 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12090 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12091 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12092 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12094 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12095 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12096 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12098 /* 5700 B0 chips do not support checksumming correctly due
12099 * to hardware bugs.
12101 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12102 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12104 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12105 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12106 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12107 tp->dev->features |= NETIF_F_IPV6_CSUM;
12110 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12111 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12112 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12113 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12114 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12115 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12116 tp->pdev_peer == tp->pdev))
12117 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12119 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12121 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12122 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12124 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12125 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12127 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12128 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12132 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12133 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12134 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12136 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12139 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12140 if (tp->pcie_cap != 0) {
12143 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12145 pcie_set_readrq(tp->pdev, 4096);
12147 pci_read_config_word(tp->pdev,
12148 tp->pcie_cap + PCI_EXP_LNKCTL,
12150 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12152 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12153 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12155 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12156 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12157 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12159 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12160 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12161 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12162 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12163 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12164 if (!tp->pcix_cap) {
12165 printk(KERN_ERR PFX "Cannot find PCI-X "
12166 "capability, aborting.\n");
12170 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12171 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12174 /* If we have an AMD 762 or VIA K8T800 chipset, write
12175 * reordering to the mailbox registers done by the host
12176 * controller can cause major troubles. We read back from
12177 * every mailbox register write to force the writes to be
12178 * posted to the chip in order.
12180 if (pci_dev_present(write_reorder_chipsets) &&
12181 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12182 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12184 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12185 &tp->pci_cacheline_sz);
12186 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12187 &tp->pci_lat_timer);
12188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12189 tp->pci_lat_timer < 64) {
12190 tp->pci_lat_timer = 64;
12191 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12192 tp->pci_lat_timer);
12195 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12196 /* 5700 BX chips need to have their TX producer index
12197 * mailboxes written twice to workaround a bug.
12199 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12201 /* If we are in PCI-X mode, enable register write workaround.
12203 * The workaround is to use indirect register accesses
12204 * for all chip writes not to mailbox registers.
12206 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12209 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12211 /* The chip can have it's power management PCI config
12212 * space registers clobbered due to this bug.
12213 * So explicitly force the chip into D0 here.
12215 pci_read_config_dword(tp->pdev,
12216 tp->pm_cap + PCI_PM_CTRL,
12218 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12219 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12220 pci_write_config_dword(tp->pdev,
12221 tp->pm_cap + PCI_PM_CTRL,
12224 /* Also, force SERR#/PERR# in PCI command. */
12225 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12226 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12227 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12231 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12232 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12233 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12234 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12236 /* Chip-specific fixup from Broadcom driver */
12237 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12238 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12239 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12240 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12243 /* Default fast path register access methods */
12244 tp->read32 = tg3_read32;
12245 tp->write32 = tg3_write32;
12246 tp->read32_mbox = tg3_read32;
12247 tp->write32_mbox = tg3_write32;
12248 tp->write32_tx_mbox = tg3_write32;
12249 tp->write32_rx_mbox = tg3_write32;
12251 /* Various workaround register access methods */
12252 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12253 tp->write32 = tg3_write_indirect_reg32;
12254 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12255 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12256 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12258 * Back to back register writes can cause problems on these
12259 * chips, the workaround is to read back all reg writes
12260 * except those to mailbox regs.
12262 * See tg3_write_indirect_reg32().
12264 tp->write32 = tg3_write_flush_reg32;
12268 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12269 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12270 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12271 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12272 tp->write32_rx_mbox = tg3_write_flush_reg32;
12275 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12276 tp->read32 = tg3_read_indirect_reg32;
12277 tp->write32 = tg3_write_indirect_reg32;
12278 tp->read32_mbox = tg3_read_indirect_mbox;
12279 tp->write32_mbox = tg3_write_indirect_mbox;
12280 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12281 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12286 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12287 pci_cmd &= ~PCI_COMMAND_MEMORY;
12288 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12290 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12291 tp->read32_mbox = tg3_read32_mbox_5906;
12292 tp->write32_mbox = tg3_write32_mbox_5906;
12293 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12294 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12297 if (tp->write32 == tg3_write_indirect_reg32 ||
12298 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12299 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12301 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12303 /* Get eeprom hw config before calling tg3_set_power_state().
12304 * In particular, the TG3_FLG2_IS_NIC flag must be
12305 * determined before calling tg3_set_power_state() so that
12306 * we know whether or not to switch out of Vaux power.
12307 * When the flag is set, it means that GPIO1 is used for eeprom
12308 * write protect and also implies that it is a LOM where GPIOs
12309 * are not used to switch power.
12311 tg3_get_eeprom_hw_cfg(tp);
12313 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12314 /* Allow reads and writes to the
12315 * APE register and memory space.
12317 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12318 PCISTATE_ALLOW_APE_SHMEM_WR;
12319 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12325 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12326 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12327 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12329 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12330 * GPIO1 driven high will bring 5700's external PHY out of reset.
12331 * It is also used as eeprom write protect on LOMs.
12333 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12334 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12335 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12336 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12337 GRC_LCLCTRL_GPIO_OUTPUT1);
12338 /* Unused GPIO3 must be driven as output on 5752 because there
12339 * are no pull-up resistors on unused GPIO pins.
12341 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12342 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12345 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12346 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12348 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12349 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12350 /* Turn off the debug UART. */
12351 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12352 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12353 /* Keep VMain power. */
12354 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12355 GRC_LCLCTRL_GPIO_OUTPUT0;
12358 /* Force the chip into D0. */
12359 err = tg3_set_power_state(tp, PCI_D0);
12361 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12362 pci_name(tp->pdev));
12366 /* Derive initial jumbo mode from MTU assigned in
12367 * ether_setup() via the alloc_etherdev() call
12369 if (tp->dev->mtu > ETH_DATA_LEN &&
12370 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12371 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12373 /* Determine WakeOnLan speed to use. */
12374 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12375 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12376 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12377 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12378 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12380 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12383 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12384 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12386 /* A few boards don't want Ethernet@WireSpeed phy feature */
12387 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12388 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12389 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12390 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12391 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12392 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12393 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12395 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12396 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12397 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12398 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12399 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12401 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12402 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12403 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12404 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12406 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12409 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12410 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12411 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12412 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12413 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12415 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12419 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12420 tp->phy_otp = tg3_read_otp_phycfg(tp);
12421 if (tp->phy_otp == 0)
12422 tp->phy_otp = TG3_OTP_DEFAULT;
12425 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12426 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12428 tp->mi_mode = MAC_MI_MODE_BASE;
12430 tp->coalesce_mode = 0;
12431 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12432 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12433 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12436 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12437 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12439 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12440 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12441 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12442 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12444 err = tg3_mdio_init(tp);
12448 /* Initialize data/descriptor byte/word swapping. */
12449 val = tr32(GRC_MODE);
12450 val &= GRC_MODE_HOST_STACKUP;
12451 tw32(GRC_MODE, val | tp->grc_mode);
12453 tg3_switch_clocks(tp);
12455 /* Clear this out for sanity. */
12456 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12458 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12460 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12461 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12462 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12464 if (chiprevid == CHIPREV_ID_5701_A0 ||
12465 chiprevid == CHIPREV_ID_5701_B0 ||
12466 chiprevid == CHIPREV_ID_5701_B2 ||
12467 chiprevid == CHIPREV_ID_5701_B5) {
12468 void __iomem *sram_base;
12470 /* Write some dummy words into the SRAM status block
12471 * area, see if it reads back correctly. If the return
12472 * value is bad, force enable the PCIX workaround.
12474 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12476 writel(0x00000000, sram_base);
12477 writel(0x00000000, sram_base + 4);
12478 writel(0xffffffff, sram_base + 4);
12479 if (readl(sram_base) != 0x00000000)
12480 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12485 tg3_nvram_init(tp);
12487 grc_misc_cfg = tr32(GRC_MISC_CFG);
12488 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12491 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12492 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12493 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12495 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12496 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12497 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12498 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12499 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12500 HOSTCC_MODE_CLRTICK_TXBD);
12502 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12503 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12504 tp->misc_host_ctrl);
12507 /* Preserve the APE MAC_MODE bits */
12508 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12509 tp->mac_mode = tr32(MAC_MODE) |
12510 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12512 tp->mac_mode = TG3_DEF_MAC_MODE;
12514 /* these are limited to 10/100 only */
12515 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12516 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12517 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12518 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12519 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12520 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12521 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12522 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12523 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12524 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12525 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12526 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12527 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12528 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12530 err = tg3_phy_probe(tp);
12532 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12533 pci_name(tp->pdev), err);
12534 /* ... but do not return immediately ... */
12538 tg3_read_partno(tp);
12539 tg3_read_fw_ver(tp);
12541 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12542 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12545 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12547 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12550 /* 5700 {AX,BX} chips have a broken status block link
12551 * change bit implementation, so we must use the
12552 * status register in those cases.
12554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12555 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12557 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12559 /* The led_ctrl is set during tg3_phy_probe, here we might
12560 * have to force the link status polling mechanism based
12561 * upon subsystem IDs.
12563 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12564 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12565 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12566 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12567 TG3_FLAG_USE_LINKCHG_REG);
12570 /* For all SERDES we poll the MAC status register. */
12571 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12572 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12574 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12576 tp->rx_offset = NET_IP_ALIGN;
12577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12578 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12581 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12583 /* Increment the rx prod index on the rx std ring by at most
12584 * 8 for these chips to workaround hw errata.
12586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12588 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12589 tp->rx_std_max_post = 8;
12591 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12592 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12593 PCIE_PWR_MGMT_L1_THRESH_MSK;
12598 #ifdef CONFIG_SPARC
12599 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12601 struct net_device *dev = tp->dev;
12602 struct pci_dev *pdev = tp->pdev;
12603 struct device_node *dp = pci_device_to_OF_node(pdev);
12604 const unsigned char *addr;
12607 addr = of_get_property(dp, "local-mac-address", &len);
12608 if (addr && len == 6) {
12609 memcpy(dev->dev_addr, addr, 6);
12610 memcpy(dev->perm_addr, dev->dev_addr, 6);
12616 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12618 struct net_device *dev = tp->dev;
12620 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12621 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12626 static int __devinit tg3_get_device_address(struct tg3 *tp)
12628 struct net_device *dev = tp->dev;
12629 u32 hi, lo, mac_offset;
12632 #ifdef CONFIG_SPARC
12633 if (!tg3_get_macaddr_sparc(tp))
12638 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12639 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12640 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12642 if (tg3_nvram_lock(tp))
12643 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12645 tg3_nvram_unlock(tp);
12647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12650 /* First try to get it from MAC address mailbox. */
12651 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12652 if ((hi >> 16) == 0x484b) {
12653 dev->dev_addr[0] = (hi >> 8) & 0xff;
12654 dev->dev_addr[1] = (hi >> 0) & 0xff;
12656 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12657 dev->dev_addr[2] = (lo >> 24) & 0xff;
12658 dev->dev_addr[3] = (lo >> 16) & 0xff;
12659 dev->dev_addr[4] = (lo >> 8) & 0xff;
12660 dev->dev_addr[5] = (lo >> 0) & 0xff;
12662 /* Some old bootcode may report a 0 MAC address in SRAM */
12663 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12666 /* Next, try NVRAM. */
12667 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12668 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12669 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12670 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12671 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12673 /* Finally just fetch it out of the MAC control regs. */
12675 hi = tr32(MAC_ADDR_0_HIGH);
12676 lo = tr32(MAC_ADDR_0_LOW);
12678 dev->dev_addr[5] = lo & 0xff;
12679 dev->dev_addr[4] = (lo >> 8) & 0xff;
12680 dev->dev_addr[3] = (lo >> 16) & 0xff;
12681 dev->dev_addr[2] = (lo >> 24) & 0xff;
12682 dev->dev_addr[1] = hi & 0xff;
12683 dev->dev_addr[0] = (hi >> 8) & 0xff;
12687 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12688 #ifdef CONFIG_SPARC
12689 if (!tg3_get_default_macaddr_sparc(tp))
12694 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12698 #define BOUNDARY_SINGLE_CACHELINE 1
12699 #define BOUNDARY_MULTI_CACHELINE 2
12701 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12703 int cacheline_size;
12707 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12709 cacheline_size = 1024;
12711 cacheline_size = (int) byte * 4;
12713 /* On 5703 and later chips, the boundary bits have no
12716 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12717 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12718 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12721 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12722 goal = BOUNDARY_MULTI_CACHELINE;
12724 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12725 goal = BOUNDARY_SINGLE_CACHELINE;
12734 /* PCI controllers on most RISC systems tend to disconnect
12735 * when a device tries to burst across a cache-line boundary.
12736 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12738 * Unfortunately, for PCI-E there are only limited
12739 * write-side controls for this, and thus for reads
12740 * we will still get the disconnects. We'll also waste
12741 * these PCI cycles for both read and write for chips
12742 * other than 5700 and 5701 which do not implement the
12745 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12746 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12747 switch (cacheline_size) {
12752 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12753 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12754 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12756 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12757 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12762 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12763 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12767 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12768 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12771 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12772 switch (cacheline_size) {
12776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12777 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12778 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12784 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12785 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12789 switch (cacheline_size) {
12791 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12792 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12793 DMA_RWCTRL_WRITE_BNDRY_16);
12798 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12799 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12800 DMA_RWCTRL_WRITE_BNDRY_32);
12805 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12806 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12807 DMA_RWCTRL_WRITE_BNDRY_64);
12812 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12813 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12814 DMA_RWCTRL_WRITE_BNDRY_128);
12819 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12820 DMA_RWCTRL_WRITE_BNDRY_256);
12823 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12824 DMA_RWCTRL_WRITE_BNDRY_512);
12828 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12829 DMA_RWCTRL_WRITE_BNDRY_1024);
12838 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12840 struct tg3_internal_buffer_desc test_desc;
12841 u32 sram_dma_descs;
12844 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12846 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12847 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12848 tw32(RDMAC_STATUS, 0);
12849 tw32(WDMAC_STATUS, 0);
12851 tw32(BUFMGR_MODE, 0);
12852 tw32(FTQ_RESET, 0);
12854 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12855 test_desc.addr_lo = buf_dma & 0xffffffff;
12856 test_desc.nic_mbuf = 0x00002100;
12857 test_desc.len = size;
12860 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12861 * the *second* time the tg3 driver was getting loaded after an
12864 * Broadcom tells me:
12865 * ...the DMA engine is connected to the GRC block and a DMA
12866 * reset may affect the GRC block in some unpredictable way...
12867 * The behavior of resets to individual blocks has not been tested.
12869 * Broadcom noted the GRC reset will also reset all sub-components.
12872 test_desc.cqid_sqid = (13 << 8) | 2;
12874 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12877 test_desc.cqid_sqid = (16 << 8) | 7;
12879 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12882 test_desc.flags = 0x00000005;
12884 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12887 val = *(((u32 *)&test_desc) + i);
12888 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12889 sram_dma_descs + (i * sizeof(u32)));
12890 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12892 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12895 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12897 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12901 for (i = 0; i < 40; i++) {
12905 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12907 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12908 if ((val & 0xffff) == sram_dma_descs) {
12919 #define TEST_BUFFER_SIZE 0x2000
12921 static int __devinit tg3_test_dma(struct tg3 *tp)
12923 dma_addr_t buf_dma;
12924 u32 *buf, saved_dma_rwctrl;
12927 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12933 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12934 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12936 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12938 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12939 /* DMA read watermark not used on PCIE */
12940 tp->dma_rwctrl |= 0x00180000;
12941 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12942 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12944 tp->dma_rwctrl |= 0x003f0000;
12946 tp->dma_rwctrl |= 0x003f000f;
12948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12950 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12951 u32 read_water = 0x7;
12953 /* If the 5704 is behind the EPB bridge, we can
12954 * do the less restrictive ONE_DMA workaround for
12955 * better performance.
12957 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12959 tp->dma_rwctrl |= 0x8000;
12960 else if (ccval == 0x6 || ccval == 0x7)
12961 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12965 /* Set bit 23 to enable PCIX hw bug fix */
12967 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12968 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12970 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12971 /* 5780 always in PCIX mode */
12972 tp->dma_rwctrl |= 0x00144000;
12973 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12974 /* 5714 always in PCIX mode */
12975 tp->dma_rwctrl |= 0x00148000;
12977 tp->dma_rwctrl |= 0x001b000f;
12981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12982 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12983 tp->dma_rwctrl &= 0xfffffff0;
12985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12987 /* Remove this if it causes problems for some boards. */
12988 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12990 /* On 5700/5701 chips, we need to set this bit.
12991 * Otherwise the chip will issue cacheline transactions
12992 * to streamable DMA memory with not all the byte
12993 * enables turned on. This is an error on several
12994 * RISC PCI controllers, in particular sparc64.
12996 * On 5703/5704 chips, this bit has been reassigned
12997 * a different meaning. In particular, it is used
12998 * on those chips to enable a PCI-X workaround.
13000 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13003 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13006 /* Unneeded, already done by tg3_get_invariants. */
13007 tg3_switch_clocks(tp);
13011 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13012 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13015 /* It is best to perform DMA test with maximum write burst size
13016 * to expose the 5700/5701 write DMA bug.
13018 saved_dma_rwctrl = tp->dma_rwctrl;
13019 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13020 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13025 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13028 /* Send the buffer to the chip. */
13029 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13031 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13036 /* validate data reached card RAM correctly. */
13037 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13039 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13040 if (le32_to_cpu(val) != p[i]) {
13041 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13042 /* ret = -ENODEV here? */
13047 /* Now read it back. */
13048 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13050 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13056 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13060 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13061 DMA_RWCTRL_WRITE_BNDRY_16) {
13062 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13063 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13064 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13067 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13073 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13079 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13080 DMA_RWCTRL_WRITE_BNDRY_16) {
13081 static struct pci_device_id dma_wait_state_chipsets[] = {
13082 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13083 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13087 /* DMA test passed without adjusting DMA boundary,
13088 * now look for chipsets that are known to expose the
13089 * DMA bug without failing the test.
13091 if (pci_dev_present(dma_wait_state_chipsets)) {
13092 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13093 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13096 /* Safe to use the calculated DMA boundary. */
13097 tp->dma_rwctrl = saved_dma_rwctrl;
13099 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13103 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13108 static void __devinit tg3_init_link_config(struct tg3 *tp)
13110 tp->link_config.advertising =
13111 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13112 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13113 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13114 ADVERTISED_Autoneg | ADVERTISED_MII);
13115 tp->link_config.speed = SPEED_INVALID;
13116 tp->link_config.duplex = DUPLEX_INVALID;
13117 tp->link_config.autoneg = AUTONEG_ENABLE;
13118 tp->link_config.active_speed = SPEED_INVALID;
13119 tp->link_config.active_duplex = DUPLEX_INVALID;
13120 tp->link_config.phy_is_low_power = 0;
13121 tp->link_config.orig_speed = SPEED_INVALID;
13122 tp->link_config.orig_duplex = DUPLEX_INVALID;
13123 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13126 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13128 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13129 tp->bufmgr_config.mbuf_read_dma_low_water =
13130 DEFAULT_MB_RDMA_LOW_WATER_5705;
13131 tp->bufmgr_config.mbuf_mac_rx_low_water =
13132 DEFAULT_MB_MACRX_LOW_WATER_5705;
13133 tp->bufmgr_config.mbuf_high_water =
13134 DEFAULT_MB_HIGH_WATER_5705;
13135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13136 tp->bufmgr_config.mbuf_mac_rx_low_water =
13137 DEFAULT_MB_MACRX_LOW_WATER_5906;
13138 tp->bufmgr_config.mbuf_high_water =
13139 DEFAULT_MB_HIGH_WATER_5906;
13142 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13143 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13144 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13145 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13146 tp->bufmgr_config.mbuf_high_water_jumbo =
13147 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13149 tp->bufmgr_config.mbuf_read_dma_low_water =
13150 DEFAULT_MB_RDMA_LOW_WATER;
13151 tp->bufmgr_config.mbuf_mac_rx_low_water =
13152 DEFAULT_MB_MACRX_LOW_WATER;
13153 tp->bufmgr_config.mbuf_high_water =
13154 DEFAULT_MB_HIGH_WATER;
13156 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13157 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13158 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13159 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13160 tp->bufmgr_config.mbuf_high_water_jumbo =
13161 DEFAULT_MB_HIGH_WATER_JUMBO;
13164 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13165 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13168 static char * __devinit tg3_phy_string(struct tg3 *tp)
13170 switch (tp->phy_id & PHY_ID_MASK) {
13171 case PHY_ID_BCM5400: return "5400";
13172 case PHY_ID_BCM5401: return "5401";
13173 case PHY_ID_BCM5411: return "5411";
13174 case PHY_ID_BCM5701: return "5701";
13175 case PHY_ID_BCM5703: return "5703";
13176 case PHY_ID_BCM5704: return "5704";
13177 case PHY_ID_BCM5705: return "5705";
13178 case PHY_ID_BCM5750: return "5750";
13179 case PHY_ID_BCM5752: return "5752";
13180 case PHY_ID_BCM5714: return "5714";
13181 case PHY_ID_BCM5780: return "5780";
13182 case PHY_ID_BCM5755: return "5755";
13183 case PHY_ID_BCM5787: return "5787";
13184 case PHY_ID_BCM5784: return "5784";
13185 case PHY_ID_BCM5756: return "5722/5756";
13186 case PHY_ID_BCM5906: return "5906";
13187 case PHY_ID_BCM5761: return "5761";
13188 case PHY_ID_BCM8002: return "8002/serdes";
13189 case 0: return "serdes";
13190 default: return "unknown";
13194 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13196 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13197 strcpy(str, "PCI Express");
13199 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13200 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13202 strcpy(str, "PCIX:");
13204 if ((clock_ctrl == 7) ||
13205 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13206 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13207 strcat(str, "133MHz");
13208 else if (clock_ctrl == 0)
13209 strcat(str, "33MHz");
13210 else if (clock_ctrl == 2)
13211 strcat(str, "50MHz");
13212 else if (clock_ctrl == 4)
13213 strcat(str, "66MHz");
13214 else if (clock_ctrl == 6)
13215 strcat(str, "100MHz");
13217 strcpy(str, "PCI:");
13218 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13219 strcat(str, "66MHz");
13221 strcat(str, "33MHz");
13223 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13224 strcat(str, ":32-bit");
13226 strcat(str, ":64-bit");
13230 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13232 struct pci_dev *peer;
13233 unsigned int func, devnr = tp->pdev->devfn & ~7;
13235 for (func = 0; func < 8; func++) {
13236 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13237 if (peer && peer != tp->pdev)
13241 /* 5704 can be configured in single-port mode, set peer to
13242 * tp->pdev in that case.
13250 * We don't need to keep the refcount elevated; there's no way
13251 * to remove one half of this device without removing the other
13258 static void __devinit tg3_init_coal(struct tg3 *tp)
13260 struct ethtool_coalesce *ec = &tp->coal;
13262 memset(ec, 0, sizeof(*ec));
13263 ec->cmd = ETHTOOL_GCOALESCE;
13264 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13265 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13266 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13267 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13268 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13269 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13270 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13271 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13272 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13274 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13275 HOSTCC_MODE_CLRTICK_TXBD)) {
13276 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13277 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13278 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13279 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13282 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13283 ec->rx_coalesce_usecs_irq = 0;
13284 ec->tx_coalesce_usecs_irq = 0;
13285 ec->stats_block_coalesce_usecs = 0;
13289 static const struct net_device_ops tg3_netdev_ops = {
13290 .ndo_open = tg3_open,
13291 .ndo_stop = tg3_close,
13292 .ndo_start_xmit = tg3_start_xmit,
13293 .ndo_get_stats = tg3_get_stats,
13294 .ndo_validate_addr = eth_validate_addr,
13295 .ndo_set_multicast_list = tg3_set_rx_mode,
13296 .ndo_set_mac_address = tg3_set_mac_addr,
13297 .ndo_do_ioctl = tg3_ioctl,
13298 .ndo_tx_timeout = tg3_tx_timeout,
13299 .ndo_change_mtu = tg3_change_mtu,
13300 #if TG3_VLAN_TAG_USED
13301 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13303 #ifdef CONFIG_NET_POLL_CONTROLLER
13304 .ndo_poll_controller = tg3_poll_controller,
13308 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13309 .ndo_open = tg3_open,
13310 .ndo_stop = tg3_close,
13311 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13312 .ndo_get_stats = tg3_get_stats,
13313 .ndo_validate_addr = eth_validate_addr,
13314 .ndo_set_multicast_list = tg3_set_rx_mode,
13315 .ndo_set_mac_address = tg3_set_mac_addr,
13316 .ndo_do_ioctl = tg3_ioctl,
13317 .ndo_tx_timeout = tg3_tx_timeout,
13318 .ndo_change_mtu = tg3_change_mtu,
13319 #if TG3_VLAN_TAG_USED
13320 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13322 #ifdef CONFIG_NET_POLL_CONTROLLER
13323 .ndo_poll_controller = tg3_poll_controller,
13327 static int __devinit tg3_init_one(struct pci_dev *pdev,
13328 const struct pci_device_id *ent)
13330 static int tg3_version_printed = 0;
13331 struct net_device *dev;
13335 u64 dma_mask, persist_dma_mask;
13337 if (tg3_version_printed++ == 0)
13338 printk(KERN_INFO "%s", version);
13340 err = pci_enable_device(pdev);
13342 printk(KERN_ERR PFX "Cannot enable PCI device, "
13347 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13349 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13351 goto err_out_disable_pdev;
13354 pci_set_master(pdev);
13356 /* Find power-management capability. */
13357 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13359 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13362 goto err_out_free_res;
13365 dev = alloc_etherdev(sizeof(*tp));
13367 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13369 goto err_out_free_res;
13372 SET_NETDEV_DEV(dev, &pdev->dev);
13374 #if TG3_VLAN_TAG_USED
13375 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13378 tp = netdev_priv(dev);
13381 tp->pm_cap = pm_cap;
13382 tp->rx_mode = TG3_DEF_RX_MODE;
13383 tp->tx_mode = TG3_DEF_TX_MODE;
13386 tp->msg_enable = tg3_debug;
13388 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13390 /* The word/byte swap controls here control register access byte
13391 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13394 tp->misc_host_ctrl =
13395 MISC_HOST_CTRL_MASK_PCI_INT |
13396 MISC_HOST_CTRL_WORD_SWAP |
13397 MISC_HOST_CTRL_INDIR_ACCESS |
13398 MISC_HOST_CTRL_PCISTATE_RW;
13400 /* The NONFRM (non-frame) byte/word swap controls take effect
13401 * on descriptor entries, anything which isn't packet data.
13403 * The StrongARM chips on the board (one for tx, one for rx)
13404 * are running in big-endian mode.
13406 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13407 GRC_MODE_WSWAP_NONFRM_DATA);
13408 #ifdef __BIG_ENDIAN
13409 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13411 spin_lock_init(&tp->lock);
13412 spin_lock_init(&tp->indirect_lock);
13413 INIT_WORK(&tp->reset_task, tg3_reset_task);
13415 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13417 printk(KERN_ERR PFX "Cannot map device registers, "
13420 goto err_out_free_dev;
13423 tg3_init_link_config(tp);
13425 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13426 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13428 tp->napi[0].tp = tp;
13429 tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13430 tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13431 tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13432 tp->napi[0].coal_now = HOSTCC_MODE_NOW;
13433 tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING;
13434 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13435 dev->ethtool_ops = &tg3_ethtool_ops;
13436 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13437 dev->irq = pdev->irq;
13439 err = tg3_get_invariants(tp);
13441 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13443 goto err_out_iounmap;
13446 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13448 dev->netdev_ops = &tg3_netdev_ops;
13450 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13453 /* The EPB bridge inside 5714, 5715, and 5780 and any
13454 * device behind the EPB cannot support DMA addresses > 40-bit.
13455 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13456 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13457 * do DMA address check in tg3_start_xmit().
13459 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13460 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13461 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13462 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13463 #ifdef CONFIG_HIGHMEM
13464 dma_mask = DMA_BIT_MASK(64);
13467 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13469 /* Configure DMA attributes. */
13470 if (dma_mask > DMA_BIT_MASK(32)) {
13471 err = pci_set_dma_mask(pdev, dma_mask);
13473 dev->features |= NETIF_F_HIGHDMA;
13474 err = pci_set_consistent_dma_mask(pdev,
13477 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13478 "DMA for consistent allocations\n");
13479 goto err_out_iounmap;
13483 if (err || dma_mask == DMA_BIT_MASK(32)) {
13484 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13486 printk(KERN_ERR PFX "No usable DMA configuration, "
13488 goto err_out_iounmap;
13492 tg3_init_bufmgr_config(tp);
13494 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13495 tp->fw_needed = FIRMWARE_TG3;
13497 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13498 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13500 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13502 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13504 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13505 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13507 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13509 tp->fw_needed = FIRMWARE_TG3TSO5;
13511 tp->fw_needed = FIRMWARE_TG3TSO;
13514 /* TSO is on by default on chips that support hardware TSO.
13515 * Firmware TSO on older chips gives lower performance, so it
13516 * is off by default, but can be enabled using ethtool.
13518 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13519 if (dev->features & NETIF_F_IP_CSUM)
13520 dev->features |= NETIF_F_TSO;
13521 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13522 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13523 dev->features |= NETIF_F_TSO6;
13524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13525 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13526 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13529 dev->features |= NETIF_F_TSO_ECN;
13533 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13534 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13535 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13536 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13537 tp->rx_pending = 63;
13540 err = tg3_get_device_address(tp);
13542 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13547 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13548 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13549 if (!tp->aperegs) {
13550 printk(KERN_ERR PFX "Cannot map APE registers, "
13556 tg3_ape_lock_init(tp);
13558 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13559 tg3_read_dash_ver(tp);
13563 * Reset chip in case UNDI or EFI driver did not shutdown
13564 * DMA self test will enable WDMAC and we'll see (spurious)
13565 * pending DMA on the PCI bus at that point.
13567 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13568 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13569 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13570 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13573 err = tg3_test_dma(tp);
13575 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13576 goto err_out_apeunmap;
13579 /* flow control autonegotiation is default behavior */
13580 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13581 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13585 pci_set_drvdata(pdev, dev);
13587 err = register_netdev(dev);
13589 printk(KERN_ERR PFX "Cannot register net device, "
13591 goto err_out_apeunmap;
13594 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13596 tp->board_part_number,
13597 tp->pci_chip_rev_id,
13598 tg3_bus_string(tp, str),
13601 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13603 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13605 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13606 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13609 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13610 tp->dev->name, tg3_phy_string(tp),
13611 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13612 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13613 "10/100/1000Base-T")),
13614 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13616 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13618 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13619 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13620 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13621 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13622 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13623 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13624 dev->name, tp->dma_rwctrl,
13625 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13626 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13632 iounmap(tp->aperegs);
13633 tp->aperegs = NULL;
13638 release_firmware(tp->fw);
13650 pci_release_regions(pdev);
13652 err_out_disable_pdev:
13653 pci_disable_device(pdev);
13654 pci_set_drvdata(pdev, NULL);
13658 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13660 struct net_device *dev = pci_get_drvdata(pdev);
13663 struct tg3 *tp = netdev_priv(dev);
13666 release_firmware(tp->fw);
13668 flush_scheduled_work();
13670 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13675 unregister_netdev(dev);
13677 iounmap(tp->aperegs);
13678 tp->aperegs = NULL;
13685 pci_release_regions(pdev);
13686 pci_disable_device(pdev);
13687 pci_set_drvdata(pdev, NULL);
13691 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13693 struct net_device *dev = pci_get_drvdata(pdev);
13694 struct tg3 *tp = netdev_priv(dev);
13695 pci_power_t target_state;
13698 /* PCI register 4 needs to be saved whether netif_running() or not.
13699 * MSI address and data need to be saved if using MSI and
13702 pci_save_state(pdev);
13704 if (!netif_running(dev))
13707 flush_scheduled_work();
13709 tg3_netif_stop(tp);
13711 del_timer_sync(&tp->timer);
13713 tg3_full_lock(tp, 1);
13714 tg3_disable_ints(tp);
13715 tg3_full_unlock(tp);
13717 netif_device_detach(dev);
13719 tg3_full_lock(tp, 0);
13720 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13721 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13722 tg3_full_unlock(tp);
13724 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13726 err = tg3_set_power_state(tp, target_state);
13730 tg3_full_lock(tp, 0);
13732 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13733 err2 = tg3_restart_hw(tp, 1);
13737 tp->timer.expires = jiffies + tp->timer_offset;
13738 add_timer(&tp->timer);
13740 netif_device_attach(dev);
13741 tg3_netif_start(tp);
13744 tg3_full_unlock(tp);
13753 static int tg3_resume(struct pci_dev *pdev)
13755 struct net_device *dev = pci_get_drvdata(pdev);
13756 struct tg3 *tp = netdev_priv(dev);
13759 pci_restore_state(tp->pdev);
13761 if (!netif_running(dev))
13764 err = tg3_set_power_state(tp, PCI_D0);
13768 netif_device_attach(dev);
13770 tg3_full_lock(tp, 0);
13772 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13773 err = tg3_restart_hw(tp, 1);
13777 tp->timer.expires = jiffies + tp->timer_offset;
13778 add_timer(&tp->timer);
13780 tg3_netif_start(tp);
13783 tg3_full_unlock(tp);
13791 static struct pci_driver tg3_driver = {
13792 .name = DRV_MODULE_NAME,
13793 .id_table = tg3_pci_tbl,
13794 .probe = tg3_init_one,
13795 .remove = __devexit_p(tg3_remove_one),
13796 .suspend = tg3_suspend,
13797 .resume = tg3_resume
13800 static int __init tg3_init(void)
13802 return pci_register_driver(&tg3_driver);
13805 static void __exit tg3_cleanup(void)
13807 pci_unregister_driver(&tg3_driver);
13810 module_init(tg3_init);
13811 module_exit(tg3_cleanup);