2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.100"
72 #define DRV_MODULE_RELDATE "August 25, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
134 #define TG3_RAW_IP_ALIGN 2
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139 #define TG3_NUM_TEST 6
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
145 static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION);
152 MODULE_FIRMWARE(FIRMWARE_TG3);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
157 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug, int, 0);
159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
161 static struct pci_device_id tg3_pci_tbl[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
239 static const struct {
240 const char string[ETH_GSTRING_LEN];
241 } ethtool_stats_keys[TG3_NUM_STATS] = {
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
274 { "tx_flow_control" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
307 { "rx_threshold_hit" },
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
320 static const struct {
321 const char string[ETH_GSTRING_LEN];
322 } ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
333 writel(val, tp->regs + off);
336 static u32 tg3_read32(struct tg3 *tp, u32 off)
338 return (readl(tp->regs + off));
341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
343 writel(val, tp->aperegs + off);
346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
348 return (readl(tp->aperegs + off));
351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
355 spin_lock_irqsave(&tp->indirect_lock, flags);
356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
434 tg3_write32(tp, off, val);
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
448 tp->write32_mbox(tp, off, val);
449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
456 void __iomem *mbox = tp->regs + off;
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
466 return (readl(tp->regs + off + GRCMBOX_BASE));
469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
471 writel(val, tp->regs + off + GRCMBOX_BASE);
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
493 spin_lock_irqsave(&tp->indirect_lock, flags);
494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
537 static void tg3_ape_lock_init(struct tg3 *tp)
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
557 case TG3_APE_LOCK_GRC:
558 case TG3_APE_LOCK_MEM:
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
595 case TG3_APE_LOCK_GRC:
596 case TG3_APE_LOCK_MEM:
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
606 static void tg3_disable_ints(struct tg3 *tp)
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
613 static inline void tg3_cond_int(struct tg3 *tp)
615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
623 static void tg3_enable_ints(struct tg3 *tp)
628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
638 static inline unsigned int tg3_has_work(struct tg3 *tp)
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
663 static void tg3_restart_ints(struct tg3 *tp)
665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
679 static inline void tg3_netif_stop(struct tg3 *tp)
681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
682 napi_disable(&tp->napi);
683 netif_tx_disable(tp->dev);
686 static inline void tg3_netif_start(struct tg3 *tp)
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
693 napi_enable(&tp->napi);
694 tp->hw_status->status |= SD_STATUS_UPDATED;
698 static void tg3_switch_clocks(struct tg3 *tp)
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
711 tp->pci_clock_ctrl = clock_ctrl;
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
730 #define PHY_BUSY_LOOPS 5000
732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
752 tw32_f(MAC_MI_COM, frame_val);
754 loops = PHY_BUSY_LOOPS;
757 frame_val = tr32(MAC_MI_COM);
759 if ((frame_val & MI_COM_BUSY) == 0) {
761 frame_val = tr32(MAC_MI_COM);
769 *val = frame_val & MI_COM_DATA_MASK;
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
787 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
804 tw32_f(MAC_MI_COM, frame_val);
806 loops = PHY_BUSY_LOOPS;
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
812 frame_val = tr32(MAC_MI_COM);
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
830 static int tg3_bmcr_reset(struct tg3 *tp)
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
849 if ((phy_control & BMCR_RESET) == 0) {
861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
863 struct tg3 *tp = bp->priv;
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
869 if (tg3_readphy(tp, reg, &val))
875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
877 struct tg3 *tp = bp->priv;
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
882 if (tg3_writephy(tp, reg, val))
888 static int tg3_mdio_reset(struct mii_bus *bp)
893 static void tg3_mdio_config_5785(struct tg3 *tp)
896 struct phy_device *phydev;
898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
919 val = tr32(MAC_PHYCFG1);
920 val &= ~(MAC_PHYCFG1_RGMII_INT |
921 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
922 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
923 tw32(MAC_PHYCFG1, val);
928 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
929 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
930 MAC_PHYCFG2_FMODE_MASK_MASK |
931 MAC_PHYCFG2_GMODE_MASK_MASK |
932 MAC_PHYCFG2_ACT_MASK_MASK |
933 MAC_PHYCFG2_QUAL_MASK_MASK |
934 MAC_PHYCFG2_INBAND_ENABLE;
936 tw32(MAC_PHYCFG2, val);
938 val = tr32(MAC_PHYCFG1);
939 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
940 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
941 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
942 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
943 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
944 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
945 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
947 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
948 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
949 tw32(MAC_PHYCFG1, val);
951 val = tr32(MAC_EXT_RGMII_MODE);
952 val &= ~(MAC_RGMII_MODE_RX_INT_B |
953 MAC_RGMII_MODE_RX_QUALITY |
954 MAC_RGMII_MODE_RX_ACTIVITY |
955 MAC_RGMII_MODE_RX_ENG_DET |
956 MAC_RGMII_MODE_TX_ENABLE |
957 MAC_RGMII_MODE_TX_LOWPWR |
958 MAC_RGMII_MODE_TX_RESET);
959 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
961 val |= MAC_RGMII_MODE_RX_INT_B |
962 MAC_RGMII_MODE_RX_QUALITY |
963 MAC_RGMII_MODE_RX_ACTIVITY |
964 MAC_RGMII_MODE_RX_ENG_DET;
965 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
966 val |= MAC_RGMII_MODE_TX_ENABLE |
967 MAC_RGMII_MODE_TX_LOWPWR |
968 MAC_RGMII_MODE_TX_RESET;
970 tw32(MAC_EXT_RGMII_MODE, val);
973 static void tg3_mdio_start(struct tg3 *tp)
975 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
976 mutex_lock(&tp->mdio_bus->mdio_lock);
977 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
978 mutex_unlock(&tp->mdio_bus->mdio_lock);
981 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
982 tw32_f(MAC_MI_MODE, tp->mi_mode);
985 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
987 tg3_mdio_config_5785(tp);
990 static void tg3_mdio_stop(struct tg3 *tp)
992 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
993 mutex_lock(&tp->mdio_bus->mdio_lock);
994 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
995 mutex_unlock(&tp->mdio_bus->mdio_lock);
999 static int tg3_mdio_init(struct tg3 *tp)
1003 struct phy_device *phydev;
1007 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1008 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1011 tp->mdio_bus = mdiobus_alloc();
1012 if (tp->mdio_bus == NULL)
1015 tp->mdio_bus->name = "tg3 mdio bus";
1016 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1017 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1018 tp->mdio_bus->priv = tp;
1019 tp->mdio_bus->parent = &tp->pdev->dev;
1020 tp->mdio_bus->read = &tg3_mdio_read;
1021 tp->mdio_bus->write = &tg3_mdio_write;
1022 tp->mdio_bus->reset = &tg3_mdio_reset;
1023 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1024 tp->mdio_bus->irq = &tp->mdio_irq[0];
1026 for (i = 0; i < PHY_MAX_ADDR; i++)
1027 tp->mdio_bus->irq[i] = PHY_POLL;
1029 /* The bus registration will look for all the PHYs on the mdio bus.
1030 * Unfortunately, it does not ensure the PHY is powered up before
1031 * accessing the PHY ID registers. A chip reset is the
1032 * quickest way to bring the device back to an operational state..
1034 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1037 i = mdiobus_register(tp->mdio_bus);
1039 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1041 mdiobus_free(tp->mdio_bus);
1045 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1047 if (!phydev || !phydev->drv) {
1048 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1049 mdiobus_unregister(tp->mdio_bus);
1050 mdiobus_free(tp->mdio_bus);
1054 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1055 case TG3_PHY_ID_BCM57780:
1056 phydev->interface = PHY_INTERFACE_MODE_GMII;
1058 case TG3_PHY_ID_BCM50610:
1059 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1060 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1061 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1062 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1063 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1064 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1066 case TG3_PHY_ID_RTL8211C:
1067 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1069 case TG3_PHY_ID_RTL8201E:
1070 case TG3_PHY_ID_BCMAC131:
1071 phydev->interface = PHY_INTERFACE_MODE_MII;
1072 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1076 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1078 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1079 tg3_mdio_config_5785(tp);
1084 static void tg3_mdio_fini(struct tg3 *tp)
1086 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1087 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1088 mdiobus_unregister(tp->mdio_bus);
1089 mdiobus_free(tp->mdio_bus);
1090 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1094 /* tp->lock is held. */
1095 static inline void tg3_generate_fw_event(struct tg3 *tp)
1099 val = tr32(GRC_RX_CPU_EVENT);
1100 val |= GRC_RX_CPU_DRIVER_EVENT;
1101 tw32_f(GRC_RX_CPU_EVENT, val);
1103 tp->last_event_jiffies = jiffies;
1106 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1108 /* tp->lock is held. */
1109 static void tg3_wait_for_event_ack(struct tg3 *tp)
1112 unsigned int delay_cnt;
1115 /* If enough time has passed, no wait is necessary. */
1116 time_remain = (long)(tp->last_event_jiffies + 1 +
1117 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1119 if (time_remain < 0)
1122 /* Check if we can shorten the wait time. */
1123 delay_cnt = jiffies_to_usecs(time_remain);
1124 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1125 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1126 delay_cnt = (delay_cnt >> 3) + 1;
1128 for (i = 0; i < delay_cnt; i++) {
1129 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1135 /* tp->lock is held. */
1136 static void tg3_ump_link_report(struct tg3 *tp)
1141 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1142 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1145 tg3_wait_for_event_ack(tp);
1147 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1149 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1152 if (!tg3_readphy(tp, MII_BMCR, ®))
1154 if (!tg3_readphy(tp, MII_BMSR, ®))
1155 val |= (reg & 0xffff);
1156 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1159 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1161 if (!tg3_readphy(tp, MII_LPA, ®))
1162 val |= (reg & 0xffff);
1163 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1166 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1167 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1169 if (!tg3_readphy(tp, MII_STAT1000, ®))
1170 val |= (reg & 0xffff);
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1174 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1178 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1180 tg3_generate_fw_event(tp);
1183 static void tg3_link_report(struct tg3 *tp)
1185 if (!netif_carrier_ok(tp->dev)) {
1186 if (netif_msg_link(tp))
1187 printk(KERN_INFO PFX "%s: Link is down.\n",
1189 tg3_ump_link_report(tp);
1190 } else if (netif_msg_link(tp)) {
1191 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1193 (tp->link_config.active_speed == SPEED_1000 ?
1195 (tp->link_config.active_speed == SPEED_100 ?
1197 (tp->link_config.active_duplex == DUPLEX_FULL ?
1200 printk(KERN_INFO PFX
1201 "%s: Flow control is %s for TX and %s for RX.\n",
1203 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1205 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1207 tg3_ump_link_report(tp);
1211 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1215 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1216 miireg = ADVERTISE_PAUSE_CAP;
1217 else if (flow_ctrl & FLOW_CTRL_TX)
1218 miireg = ADVERTISE_PAUSE_ASYM;
1219 else if (flow_ctrl & FLOW_CTRL_RX)
1220 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1227 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1231 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1232 miireg = ADVERTISE_1000XPAUSE;
1233 else if (flow_ctrl & FLOW_CTRL_TX)
1234 miireg = ADVERTISE_1000XPSE_ASYM;
1235 else if (flow_ctrl & FLOW_CTRL_RX)
1236 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1243 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1247 if (lcladv & ADVERTISE_1000XPAUSE) {
1248 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1249 if (rmtadv & LPA_1000XPAUSE)
1250 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1251 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1254 if (rmtadv & LPA_1000XPAUSE)
1255 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1257 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1258 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1265 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1269 u32 old_rx_mode = tp->rx_mode;
1270 u32 old_tx_mode = tp->tx_mode;
1272 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1273 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1275 autoneg = tp->link_config.autoneg;
1277 if (autoneg == AUTONEG_ENABLE &&
1278 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1279 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1280 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1282 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1284 flowctrl = tp->link_config.flowctrl;
1286 tp->link_config.active_flowctrl = flowctrl;
1288 if (flowctrl & FLOW_CTRL_RX)
1289 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1291 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1293 if (old_rx_mode != tp->rx_mode)
1294 tw32_f(MAC_RX_MODE, tp->rx_mode);
1296 if (flowctrl & FLOW_CTRL_TX)
1297 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1299 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1301 if (old_tx_mode != tp->tx_mode)
1302 tw32_f(MAC_TX_MODE, tp->tx_mode);
1305 static void tg3_adjust_link(struct net_device *dev)
1307 u8 oldflowctrl, linkmesg = 0;
1308 u32 mac_mode, lcl_adv, rmt_adv;
1309 struct tg3 *tp = netdev_priv(dev);
1310 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1312 spin_lock(&tp->lock);
1314 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1315 MAC_MODE_HALF_DUPLEX);
1317 oldflowctrl = tp->link_config.active_flowctrl;
1323 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1324 mac_mode |= MAC_MODE_PORT_MODE_MII;
1326 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1328 if (phydev->duplex == DUPLEX_HALF)
1329 mac_mode |= MAC_MODE_HALF_DUPLEX;
1331 lcl_adv = tg3_advert_flowctrl_1000T(
1332 tp->link_config.flowctrl);
1335 rmt_adv = LPA_PAUSE_CAP;
1336 if (phydev->asym_pause)
1337 rmt_adv |= LPA_PAUSE_ASYM;
1340 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1342 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1344 if (mac_mode != tp->mac_mode) {
1345 tp->mac_mode = mac_mode;
1346 tw32_f(MAC_MODE, tp->mac_mode);
1350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1351 if (phydev->speed == SPEED_10)
1353 MAC_MI_STAT_10MBPS_MODE |
1354 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1356 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1359 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1360 tw32(MAC_TX_LENGTHS,
1361 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1362 (6 << TX_LENGTHS_IPG_SHIFT) |
1363 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1365 tw32(MAC_TX_LENGTHS,
1366 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1367 (6 << TX_LENGTHS_IPG_SHIFT) |
1368 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1370 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1371 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1372 phydev->speed != tp->link_config.active_speed ||
1373 phydev->duplex != tp->link_config.active_duplex ||
1374 oldflowctrl != tp->link_config.active_flowctrl)
1377 tp->link_config.active_speed = phydev->speed;
1378 tp->link_config.active_duplex = phydev->duplex;
1380 spin_unlock(&tp->lock);
1383 tg3_link_report(tp);
1386 static int tg3_phy_init(struct tg3 *tp)
1388 struct phy_device *phydev;
1390 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1393 /* Bring the PHY back to a known state. */
1396 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1398 /* Attach the MAC to the PHY. */
1399 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1400 phydev->dev_flags, phydev->interface);
1401 if (IS_ERR(phydev)) {
1402 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1403 return PTR_ERR(phydev);
1406 /* Mask with MAC supported features. */
1407 switch (phydev->interface) {
1408 case PHY_INTERFACE_MODE_GMII:
1409 case PHY_INTERFACE_MODE_RGMII:
1410 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1411 phydev->supported &= (PHY_GBIT_FEATURES |
1413 SUPPORTED_Asym_Pause);
1417 case PHY_INTERFACE_MODE_MII:
1418 phydev->supported &= (PHY_BASIC_FEATURES |
1420 SUPPORTED_Asym_Pause);
1423 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1427 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1429 phydev->advertising = phydev->supported;
1434 static void tg3_phy_start(struct tg3 *tp)
1436 struct phy_device *phydev;
1438 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1441 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1443 if (tp->link_config.phy_is_low_power) {
1444 tp->link_config.phy_is_low_power = 0;
1445 phydev->speed = tp->link_config.orig_speed;
1446 phydev->duplex = tp->link_config.orig_duplex;
1447 phydev->autoneg = tp->link_config.orig_autoneg;
1448 phydev->advertising = tp->link_config.orig_advertising;
1453 phy_start_aneg(phydev);
1456 static void tg3_phy_stop(struct tg3 *tp)
1458 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1461 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1464 static void tg3_phy_fini(struct tg3 *tp)
1466 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1467 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1468 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1472 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1474 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1475 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1478 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1482 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1485 tg3_writephy(tp, MII_TG3_FET_TEST,
1486 phytest | MII_TG3_FET_SHADOW_EN);
1487 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1489 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1491 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1492 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1494 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1498 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1502 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1505 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1506 tg3_phy_fet_toggle_apd(tp, enable);
1510 reg = MII_TG3_MISC_SHDW_WREN |
1511 MII_TG3_MISC_SHDW_SCR5_SEL |
1512 MII_TG3_MISC_SHDW_SCR5_LPED |
1513 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1514 MII_TG3_MISC_SHDW_SCR5_SDTL |
1515 MII_TG3_MISC_SHDW_SCR5_C125OE;
1516 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1517 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1519 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1522 reg = MII_TG3_MISC_SHDW_WREN |
1523 MII_TG3_MISC_SHDW_APD_SEL |
1524 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1526 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1528 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1531 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1535 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1536 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1539 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1542 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1543 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1545 tg3_writephy(tp, MII_TG3_FET_TEST,
1546 ephy | MII_TG3_FET_SHADOW_EN);
1547 if (!tg3_readphy(tp, reg, &phy)) {
1549 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1551 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1552 tg3_writephy(tp, reg, phy);
1554 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1557 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1558 MII_TG3_AUXCTL_SHDWSEL_MISC;
1559 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1560 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1562 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1564 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1565 phy |= MII_TG3_AUXCTL_MISC_WREN;
1566 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1571 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1575 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1578 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1579 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1580 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1581 (val | (1 << 15) | (1 << 4)));
1584 static void tg3_phy_apply_otp(struct tg3 *tp)
1593 /* Enable SM_DSP clock and tx 6dB coding. */
1594 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1595 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1596 MII_TG3_AUXCTL_ACTL_TX_6DB;
1597 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1599 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1600 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1601 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1603 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1604 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1605 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1607 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1608 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1609 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1611 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1612 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1614 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1615 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1617 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1618 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1619 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1621 /* Turn off SM_DSP clock. */
1622 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1623 MII_TG3_AUXCTL_ACTL_TX_6DB;
1624 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1627 static int tg3_wait_macro_done(struct tg3 *tp)
1634 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1635 if ((tmp32 & 0x1000) == 0)
1645 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1647 static const u32 test_pat[4][6] = {
1648 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1649 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1650 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1651 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1655 for (chan = 0; chan < 4; chan++) {
1658 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1659 (chan * 0x2000) | 0x0200);
1660 tg3_writephy(tp, 0x16, 0x0002);
1662 for (i = 0; i < 6; i++)
1663 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1666 tg3_writephy(tp, 0x16, 0x0202);
1667 if (tg3_wait_macro_done(tp)) {
1672 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1673 (chan * 0x2000) | 0x0200);
1674 tg3_writephy(tp, 0x16, 0x0082);
1675 if (tg3_wait_macro_done(tp)) {
1680 tg3_writephy(tp, 0x16, 0x0802);
1681 if (tg3_wait_macro_done(tp)) {
1686 for (i = 0; i < 6; i += 2) {
1689 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1690 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1691 tg3_wait_macro_done(tp)) {
1697 if (low != test_pat[chan][i] ||
1698 high != test_pat[chan][i+1]) {
1699 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1700 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1701 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1711 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1715 for (chan = 0; chan < 4; chan++) {
1718 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1719 (chan * 0x2000) | 0x0200);
1720 tg3_writephy(tp, 0x16, 0x0002);
1721 for (i = 0; i < 6; i++)
1722 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1723 tg3_writephy(tp, 0x16, 0x0202);
1724 if (tg3_wait_macro_done(tp))
1731 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1733 u32 reg32, phy9_orig;
1734 int retries, do_phy_reset, err;
1740 err = tg3_bmcr_reset(tp);
1746 /* Disable transmitter and interrupt. */
1747 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1751 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1753 /* Set full-duplex, 1000 mbps. */
1754 tg3_writephy(tp, MII_BMCR,
1755 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1757 /* Set to master mode. */
1758 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1761 tg3_writephy(tp, MII_TG3_CTRL,
1762 (MII_TG3_CTRL_AS_MASTER |
1763 MII_TG3_CTRL_ENABLE_AS_MASTER));
1765 /* Enable SM_DSP_CLOCK and 6dB. */
1766 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1768 /* Block the PHY control access. */
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1770 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1772 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1775 } while (--retries);
1777 err = tg3_phy_reset_chanpat(tp);
1781 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1782 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1784 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1785 tg3_writephy(tp, 0x16, 0x0000);
1787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1788 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1789 /* Set Extended packet length bit for jumbo frames */
1790 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1793 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1796 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1798 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1800 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1807 /* This will reset the tigon3 PHY if there is no valid
1808 * link unless the FORCE argument is non-zero.
1810 static int tg3_phy_reset(struct tg3 *tp)
1816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1819 val = tr32(GRC_MISC_CFG);
1820 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1823 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1824 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1828 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1829 netif_carrier_off(tp->dev);
1830 tg3_link_report(tp);
1833 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1836 err = tg3_phy_reset_5703_4_5(tp);
1843 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1844 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1845 cpmuctrl = tr32(TG3_CPMU_CTRL);
1846 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1848 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1851 err = tg3_bmcr_reset(tp);
1855 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1858 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1859 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1861 tw32(TG3_CPMU_CTRL, cpmuctrl);
1864 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1865 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1868 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1869 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1870 CPMU_LSPD_1000MB_MACCLK_12_5) {
1871 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1873 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1877 tg3_phy_apply_otp(tp);
1879 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1880 tg3_phy_toggle_apd(tp, true);
1882 tg3_phy_toggle_apd(tp, false);
1885 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1886 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1887 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1888 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1889 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1890 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1891 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1893 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1894 tg3_writephy(tp, 0x1c, 0x8d68);
1895 tg3_writephy(tp, 0x1c, 0x8d68);
1897 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1898 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1899 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1900 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1901 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1902 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1903 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1904 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1905 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1907 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1908 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1909 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1910 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1912 tg3_writephy(tp, MII_TG3_TEST1,
1913 MII_TG3_TEST1_TRIM_EN | 0x4);
1915 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1916 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1918 /* Set Extended packet length bit (bit 14) on all chips that */
1919 /* support jumbo frames */
1920 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1921 /* Cannot do read-modify-write on 5401 */
1922 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1923 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1926 /* Set bit 14 with read-modify-write to preserve other bits */
1927 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1928 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1929 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1932 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1933 * jumbo frames transmission.
1935 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1938 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1939 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1940 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1944 /* adjust output voltage */
1945 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1948 tg3_phy_toggle_automdix(tp, 1);
1949 tg3_phy_set_wirespeed(tp);
1953 static void tg3_frob_aux_power(struct tg3 *tp)
1955 struct tg3 *tp_peer = tp;
1957 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1960 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1961 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1962 struct net_device *dev_peer;
1964 dev_peer = pci_get_drvdata(tp->pdev_peer);
1965 /* remove_one() may have been run on the peer. */
1969 tp_peer = netdev_priv(dev_peer);
1972 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1973 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1974 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1975 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1978 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1979 (GRC_LCLCTRL_GPIO_OE0 |
1980 GRC_LCLCTRL_GPIO_OE1 |
1981 GRC_LCLCTRL_GPIO_OE2 |
1982 GRC_LCLCTRL_GPIO_OUTPUT0 |
1983 GRC_LCLCTRL_GPIO_OUTPUT1),
1985 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1986 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1987 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1988 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1989 GRC_LCLCTRL_GPIO_OE1 |
1990 GRC_LCLCTRL_GPIO_OE2 |
1991 GRC_LCLCTRL_GPIO_OUTPUT0 |
1992 GRC_LCLCTRL_GPIO_OUTPUT1 |
1994 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1996 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1997 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1999 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2000 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2003 u32 grc_local_ctrl = 0;
2005 if (tp_peer != tp &&
2006 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2009 /* Workaround to prevent overdrawing Amps. */
2010 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2012 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2013 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2014 grc_local_ctrl, 100);
2017 /* On 5753 and variants, GPIO2 cannot be used. */
2018 no_gpio2 = tp->nic_sram_data_cfg &
2019 NIC_SRAM_DATA_CFG_NO_GPIO2;
2021 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2022 GRC_LCLCTRL_GPIO_OE1 |
2023 GRC_LCLCTRL_GPIO_OE2 |
2024 GRC_LCLCTRL_GPIO_OUTPUT1 |
2025 GRC_LCLCTRL_GPIO_OUTPUT2;
2027 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2028 GRC_LCLCTRL_GPIO_OUTPUT2);
2030 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2031 grc_local_ctrl, 100);
2033 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2035 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2036 grc_local_ctrl, 100);
2039 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 grc_local_ctrl, 100);
2045 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2046 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2047 if (tp_peer != tp &&
2048 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2051 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2052 (GRC_LCLCTRL_GPIO_OE1 |
2053 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056 GRC_LCLCTRL_GPIO_OE1, 100);
2058 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2059 (GRC_LCLCTRL_GPIO_OE1 |
2060 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2065 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2067 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2069 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2070 if (speed != SPEED_10)
2072 } else if (speed == SPEED_10)
2078 static int tg3_setup_phy(struct tg3 *, int);
2080 #define RESET_KIND_SHUTDOWN 0
2081 #define RESET_KIND_INIT 1
2082 #define RESET_KIND_SUSPEND 2
2084 static void tg3_write_sig_post_reset(struct tg3 *, int);
2085 static int tg3_halt_cpu(struct tg3 *, u32);
2087 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2091 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2093 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2094 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2097 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2098 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2099 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2104 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2106 val = tr32(GRC_MISC_CFG);
2107 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2110 } else if (do_low_power) {
2111 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2112 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2114 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2115 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2116 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2117 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2118 MII_TG3_AUXCTL_PCTL_VREG_11V);
2121 /* The PHY should not be powered down on some chips because
2124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2126 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2127 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2130 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2131 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2132 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2133 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2134 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2135 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2138 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2141 /* tp->lock is held. */
2142 static int tg3_nvram_lock(struct tg3 *tp)
2144 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2147 if (tp->nvram_lock_cnt == 0) {
2148 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2149 for (i = 0; i < 8000; i++) {
2150 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2155 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2159 tp->nvram_lock_cnt++;
2164 /* tp->lock is held. */
2165 static void tg3_nvram_unlock(struct tg3 *tp)
2167 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2168 if (tp->nvram_lock_cnt > 0)
2169 tp->nvram_lock_cnt--;
2170 if (tp->nvram_lock_cnt == 0)
2171 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2175 /* tp->lock is held. */
2176 static void tg3_enable_nvram_access(struct tg3 *tp)
2178 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2179 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2180 u32 nvaccess = tr32(NVRAM_ACCESS);
2182 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2186 /* tp->lock is held. */
2187 static void tg3_disable_nvram_access(struct tg3 *tp)
2189 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2190 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2191 u32 nvaccess = tr32(NVRAM_ACCESS);
2193 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2197 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2198 u32 offset, u32 *val)
2203 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2206 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2207 EEPROM_ADDR_DEVID_MASK |
2209 tw32(GRC_EEPROM_ADDR,
2211 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2212 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2213 EEPROM_ADDR_ADDR_MASK) |
2214 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2216 for (i = 0; i < 1000; i++) {
2217 tmp = tr32(GRC_EEPROM_ADDR);
2219 if (tmp & EEPROM_ADDR_COMPLETE)
2223 if (!(tmp & EEPROM_ADDR_COMPLETE))
2226 tmp = tr32(GRC_EEPROM_DATA);
2229 * The data will always be opposite the native endian
2230 * format. Perform a blind byteswap to compensate.
2237 #define NVRAM_CMD_TIMEOUT 10000
2239 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2243 tw32(NVRAM_CMD, nvram_cmd);
2244 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2246 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2252 if (i == NVRAM_CMD_TIMEOUT)
2258 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2260 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2261 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2262 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2263 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2264 (tp->nvram_jedecnum == JEDEC_ATMEL))
2266 addr = ((addr / tp->nvram_pagesize) <<
2267 ATMEL_AT45DB0X1B_PAGE_POS) +
2268 (addr % tp->nvram_pagesize);
2273 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2275 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2276 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2277 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2278 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2279 (tp->nvram_jedecnum == JEDEC_ATMEL))
2281 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2282 tp->nvram_pagesize) +
2283 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2288 /* NOTE: Data read in from NVRAM is byteswapped according to
2289 * the byteswapping settings for all other register accesses.
2290 * tg3 devices are BE devices, so on a BE machine, the data
2291 * returned will be exactly as it is seen in NVRAM. On a LE
2292 * machine, the 32-bit value will be byteswapped.
2294 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2298 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2299 return tg3_nvram_read_using_eeprom(tp, offset, val);
2301 offset = tg3_nvram_phys_addr(tp, offset);
2303 if (offset > NVRAM_ADDR_MSK)
2306 ret = tg3_nvram_lock(tp);
2310 tg3_enable_nvram_access(tp);
2312 tw32(NVRAM_ADDR, offset);
2313 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2314 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2317 *val = tr32(NVRAM_RDDATA);
2319 tg3_disable_nvram_access(tp);
2321 tg3_nvram_unlock(tp);
2326 /* Ensures NVRAM data is in bytestream format. */
2327 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2330 int res = tg3_nvram_read(tp, offset, &v);
2332 *val = cpu_to_be32(v);
2336 /* tp->lock is held. */
2337 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2339 u32 addr_high, addr_low;
2342 addr_high = ((tp->dev->dev_addr[0] << 8) |
2343 tp->dev->dev_addr[1]);
2344 addr_low = ((tp->dev->dev_addr[2] << 24) |
2345 (tp->dev->dev_addr[3] << 16) |
2346 (tp->dev->dev_addr[4] << 8) |
2347 (tp->dev->dev_addr[5] << 0));
2348 for (i = 0; i < 4; i++) {
2349 if (i == 1 && skip_mac_1)
2351 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2352 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2357 for (i = 0; i < 12; i++) {
2358 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2359 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2363 addr_high = (tp->dev->dev_addr[0] +
2364 tp->dev->dev_addr[1] +
2365 tp->dev->dev_addr[2] +
2366 tp->dev->dev_addr[3] +
2367 tp->dev->dev_addr[4] +
2368 tp->dev->dev_addr[5]) &
2369 TX_BACKOFF_SEED_MASK;
2370 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2373 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2376 bool device_should_wake, do_low_power;
2378 /* Make sure register accesses (indirect or otherwise)
2379 * will function correctly.
2381 pci_write_config_dword(tp->pdev,
2382 TG3PCI_MISC_HOST_CTRL,
2383 tp->misc_host_ctrl);
2387 pci_enable_wake(tp->pdev, state, false);
2388 pci_set_power_state(tp->pdev, PCI_D0);
2390 /* Switch out of Vaux if it is a NIC */
2391 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2392 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2402 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2403 tp->dev->name, state);
2407 /* Restore the CLKREQ setting. */
2408 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2411 pci_read_config_word(tp->pdev,
2412 tp->pcie_cap + PCI_EXP_LNKCTL,
2414 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2415 pci_write_config_word(tp->pdev,
2416 tp->pcie_cap + PCI_EXP_LNKCTL,
2420 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2421 tw32(TG3PCI_MISC_HOST_CTRL,
2422 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2424 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2425 device_may_wakeup(&tp->pdev->dev) &&
2426 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2428 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2429 do_low_power = false;
2430 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2431 !tp->link_config.phy_is_low_power) {
2432 struct phy_device *phydev;
2433 u32 phyid, advertising;
2435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2437 tp->link_config.phy_is_low_power = 1;
2439 tp->link_config.orig_speed = phydev->speed;
2440 tp->link_config.orig_duplex = phydev->duplex;
2441 tp->link_config.orig_autoneg = phydev->autoneg;
2442 tp->link_config.orig_advertising = phydev->advertising;
2444 advertising = ADVERTISED_TP |
2446 ADVERTISED_Autoneg |
2447 ADVERTISED_10baseT_Half;
2449 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2450 device_should_wake) {
2451 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2453 ADVERTISED_100baseT_Half |
2454 ADVERTISED_100baseT_Full |
2455 ADVERTISED_10baseT_Full;
2457 advertising |= ADVERTISED_10baseT_Full;
2460 phydev->advertising = advertising;
2462 phy_start_aneg(phydev);
2464 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2465 if (phyid != TG3_PHY_ID_BCMAC131) {
2466 phyid &= TG3_PHY_OUI_MASK;
2467 if (phyid == TG3_PHY_OUI_1 ||
2468 phyid == TG3_PHY_OUI_2 ||
2469 phyid == TG3_PHY_OUI_3)
2470 do_low_power = true;
2474 do_low_power = true;
2476 if (tp->link_config.phy_is_low_power == 0) {
2477 tp->link_config.phy_is_low_power = 1;
2478 tp->link_config.orig_speed = tp->link_config.speed;
2479 tp->link_config.orig_duplex = tp->link_config.duplex;
2480 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2483 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2484 tp->link_config.speed = SPEED_10;
2485 tp->link_config.duplex = DUPLEX_HALF;
2486 tp->link_config.autoneg = AUTONEG_ENABLE;
2487 tg3_setup_phy(tp, 0);
2491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2494 val = tr32(GRC_VCPU_EXT_CTRL);
2495 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2496 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2500 for (i = 0; i < 200; i++) {
2501 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2502 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2507 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2508 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2509 WOL_DRV_STATE_SHUTDOWN |
2513 if (device_should_wake) {
2516 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2518 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2522 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2523 mac_mode = MAC_MODE_PORT_MODE_GMII;
2525 mac_mode = MAC_MODE_PORT_MODE_MII;
2527 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2528 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2530 u32 speed = (tp->tg3_flags &
2531 TG3_FLAG_WOL_SPEED_100MB) ?
2532 SPEED_100 : SPEED_10;
2533 if (tg3_5700_link_polarity(tp, speed))
2534 mac_mode |= MAC_MODE_LINK_POLARITY;
2536 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2539 mac_mode = MAC_MODE_PORT_MODE_TBI;
2542 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2543 tw32(MAC_LED_CTRL, tp->led_ctrl);
2545 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2546 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2547 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2548 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2549 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2550 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2552 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2553 mac_mode |= tp->mac_mode &
2554 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2555 if (mac_mode & MAC_MODE_APE_TX_EN)
2556 mac_mode |= MAC_MODE_TDE_ENABLE;
2559 tw32_f(MAC_MODE, mac_mode);
2562 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2566 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2567 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2571 base_val = tp->pci_clock_ctrl;
2572 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2573 CLOCK_CTRL_TXCLK_DISABLE);
2575 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2576 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2577 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2578 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2579 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2581 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2582 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2583 u32 newbits1, newbits2;
2585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2586 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2587 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2588 CLOCK_CTRL_TXCLK_DISABLE |
2590 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2591 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2592 newbits1 = CLOCK_CTRL_625_CORE;
2593 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2595 newbits1 = CLOCK_CTRL_ALTCLK;
2596 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2599 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2602 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2605 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2609 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2610 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2611 CLOCK_CTRL_TXCLK_DISABLE |
2612 CLOCK_CTRL_44MHZ_CORE);
2614 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2618 tp->pci_clock_ctrl | newbits3, 40);
2622 if (!(device_should_wake) &&
2623 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2624 tg3_power_down_phy(tp, do_low_power);
2626 tg3_frob_aux_power(tp);
2628 /* Workaround for unstable PLL clock */
2629 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2630 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2631 u32 val = tr32(0x7d00);
2633 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2635 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2638 err = tg3_nvram_lock(tp);
2639 tg3_halt_cpu(tp, RX_CPU_BASE);
2641 tg3_nvram_unlock(tp);
2645 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2647 if (device_should_wake)
2648 pci_enable_wake(tp->pdev, state, true);
2650 /* Finally, set the new power state. */
2651 pci_set_power_state(tp->pdev, state);
2656 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2658 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2659 case MII_TG3_AUX_STAT_10HALF:
2661 *duplex = DUPLEX_HALF;
2664 case MII_TG3_AUX_STAT_10FULL:
2666 *duplex = DUPLEX_FULL;
2669 case MII_TG3_AUX_STAT_100HALF:
2671 *duplex = DUPLEX_HALF;
2674 case MII_TG3_AUX_STAT_100FULL:
2676 *duplex = DUPLEX_FULL;
2679 case MII_TG3_AUX_STAT_1000HALF:
2680 *speed = SPEED_1000;
2681 *duplex = DUPLEX_HALF;
2684 case MII_TG3_AUX_STAT_1000FULL:
2685 *speed = SPEED_1000;
2686 *duplex = DUPLEX_FULL;
2690 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2691 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2693 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2697 *speed = SPEED_INVALID;
2698 *duplex = DUPLEX_INVALID;
2703 static void tg3_phy_copper_begin(struct tg3 *tp)
2708 if (tp->link_config.phy_is_low_power) {
2709 /* Entering low power mode. Disable gigabit and
2710 * 100baseT advertisements.
2712 tg3_writephy(tp, MII_TG3_CTRL, 0);
2714 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2715 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2716 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2717 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2719 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2720 } else if (tp->link_config.speed == SPEED_INVALID) {
2721 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2722 tp->link_config.advertising &=
2723 ~(ADVERTISED_1000baseT_Half |
2724 ADVERTISED_1000baseT_Full);
2726 new_adv = ADVERTISE_CSMA;
2727 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2728 new_adv |= ADVERTISE_10HALF;
2729 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2730 new_adv |= ADVERTISE_10FULL;
2731 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2732 new_adv |= ADVERTISE_100HALF;
2733 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2734 new_adv |= ADVERTISE_100FULL;
2736 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2738 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2740 if (tp->link_config.advertising &
2741 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2743 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2744 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2745 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2746 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2747 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2748 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2749 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2750 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2751 MII_TG3_CTRL_ENABLE_AS_MASTER);
2752 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2754 tg3_writephy(tp, MII_TG3_CTRL, 0);
2757 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2758 new_adv |= ADVERTISE_CSMA;
2760 /* Asking for a specific link mode. */
2761 if (tp->link_config.speed == SPEED_1000) {
2762 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2764 if (tp->link_config.duplex == DUPLEX_FULL)
2765 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2767 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2768 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2769 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2770 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2771 MII_TG3_CTRL_ENABLE_AS_MASTER);
2773 if (tp->link_config.speed == SPEED_100) {
2774 if (tp->link_config.duplex == DUPLEX_FULL)
2775 new_adv |= ADVERTISE_100FULL;
2777 new_adv |= ADVERTISE_100HALF;
2779 if (tp->link_config.duplex == DUPLEX_FULL)
2780 new_adv |= ADVERTISE_10FULL;
2782 new_adv |= ADVERTISE_10HALF;
2784 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2789 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2792 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2793 tp->link_config.speed != SPEED_INVALID) {
2794 u32 bmcr, orig_bmcr;
2796 tp->link_config.active_speed = tp->link_config.speed;
2797 tp->link_config.active_duplex = tp->link_config.duplex;
2800 switch (tp->link_config.speed) {
2806 bmcr |= BMCR_SPEED100;
2810 bmcr |= TG3_BMCR_SPEED1000;
2814 if (tp->link_config.duplex == DUPLEX_FULL)
2815 bmcr |= BMCR_FULLDPLX;
2817 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2818 (bmcr != orig_bmcr)) {
2819 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2820 for (i = 0; i < 1500; i++) {
2824 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2825 tg3_readphy(tp, MII_BMSR, &tmp))
2827 if (!(tmp & BMSR_LSTATUS)) {
2832 tg3_writephy(tp, MII_BMCR, bmcr);
2836 tg3_writephy(tp, MII_BMCR,
2837 BMCR_ANENABLE | BMCR_ANRESTART);
2841 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2845 /* Turn off tap power management. */
2846 /* Set Extended packet length bit */
2847 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2849 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2850 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2852 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2853 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2855 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2856 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2858 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2859 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2861 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2862 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2869 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2871 u32 adv_reg, all_mask = 0;
2873 if (mask & ADVERTISED_10baseT_Half)
2874 all_mask |= ADVERTISE_10HALF;
2875 if (mask & ADVERTISED_10baseT_Full)
2876 all_mask |= ADVERTISE_10FULL;
2877 if (mask & ADVERTISED_100baseT_Half)
2878 all_mask |= ADVERTISE_100HALF;
2879 if (mask & ADVERTISED_100baseT_Full)
2880 all_mask |= ADVERTISE_100FULL;
2882 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2885 if ((adv_reg & all_mask) != all_mask)
2887 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2891 if (mask & ADVERTISED_1000baseT_Half)
2892 all_mask |= ADVERTISE_1000HALF;
2893 if (mask & ADVERTISED_1000baseT_Full)
2894 all_mask |= ADVERTISE_1000FULL;
2896 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2899 if ((tg3_ctrl & all_mask) != all_mask)
2905 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2909 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2912 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2913 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2915 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2916 if (curadv != reqadv)
2919 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2920 tg3_readphy(tp, MII_LPA, rmtadv);
2922 /* Reprogram the advertisement register, even if it
2923 * does not affect the current link. If the link
2924 * gets renegotiated in the future, we can save an
2925 * additional renegotiation cycle by advertising
2926 * it correctly in the first place.
2928 if (curadv != reqadv) {
2929 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2930 ADVERTISE_PAUSE_ASYM);
2931 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2938 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2940 int current_link_up;
2942 u32 lcl_adv, rmt_adv;
2950 (MAC_STATUS_SYNC_CHANGED |
2951 MAC_STATUS_CFG_CHANGED |
2952 MAC_STATUS_MI_COMPLETION |
2953 MAC_STATUS_LNKSTATE_CHANGED));
2956 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2958 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2962 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2964 /* Some third-party PHYs need to be reset on link going
2967 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2970 netif_carrier_ok(tp->dev)) {
2971 tg3_readphy(tp, MII_BMSR, &bmsr);
2972 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2973 !(bmsr & BMSR_LSTATUS))
2979 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2980 tg3_readphy(tp, MII_BMSR, &bmsr);
2981 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2982 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2985 if (!(bmsr & BMSR_LSTATUS)) {
2986 err = tg3_init_5401phy_dsp(tp);
2990 tg3_readphy(tp, MII_BMSR, &bmsr);
2991 for (i = 0; i < 1000; i++) {
2993 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2994 (bmsr & BMSR_LSTATUS)) {
3000 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3001 !(bmsr & BMSR_LSTATUS) &&
3002 tp->link_config.active_speed == SPEED_1000) {
3003 err = tg3_phy_reset(tp);
3005 err = tg3_init_5401phy_dsp(tp);
3010 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3011 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3012 /* 5701 {A0,B0} CRC bug workaround */
3013 tg3_writephy(tp, 0x15, 0x0a75);
3014 tg3_writephy(tp, 0x1c, 0x8c68);
3015 tg3_writephy(tp, 0x1c, 0x8d68);
3016 tg3_writephy(tp, 0x1c, 0x8c68);
3019 /* Clear pending interrupts... */
3020 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3021 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3023 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3024 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3025 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3026 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3028 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3030 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3031 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3032 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3034 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3037 current_link_up = 0;
3038 current_speed = SPEED_INVALID;
3039 current_duplex = DUPLEX_INVALID;
3041 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3044 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3045 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3046 if (!(val & (1 << 10))) {
3048 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3054 for (i = 0; i < 100; i++) {
3055 tg3_readphy(tp, MII_BMSR, &bmsr);
3056 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3057 (bmsr & BMSR_LSTATUS))
3062 if (bmsr & BMSR_LSTATUS) {
3065 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3066 for (i = 0; i < 2000; i++) {
3068 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3073 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3078 for (i = 0; i < 200; i++) {
3079 tg3_readphy(tp, MII_BMCR, &bmcr);
3080 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3082 if (bmcr && bmcr != 0x7fff)
3090 tp->link_config.active_speed = current_speed;
3091 tp->link_config.active_duplex = current_duplex;
3093 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3094 if ((bmcr & BMCR_ANENABLE) &&
3095 tg3_copper_is_advertising_all(tp,
3096 tp->link_config.advertising)) {
3097 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3099 current_link_up = 1;
3102 if (!(bmcr & BMCR_ANENABLE) &&
3103 tp->link_config.speed == current_speed &&
3104 tp->link_config.duplex == current_duplex &&
3105 tp->link_config.flowctrl ==
3106 tp->link_config.active_flowctrl) {
3107 current_link_up = 1;
3111 if (current_link_up == 1 &&
3112 tp->link_config.active_duplex == DUPLEX_FULL)
3113 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3117 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3120 tg3_phy_copper_begin(tp);
3122 tg3_readphy(tp, MII_BMSR, &tmp);
3123 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3124 (tmp & BMSR_LSTATUS))
3125 current_link_up = 1;
3128 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3129 if (current_link_up == 1) {
3130 if (tp->link_config.active_speed == SPEED_100 ||
3131 tp->link_config.active_speed == SPEED_10)
3132 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3134 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3135 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3136 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3138 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3140 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3141 if (tp->link_config.active_duplex == DUPLEX_HALF)
3142 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3145 if (current_link_up == 1 &&
3146 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3147 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3149 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3152 /* ??? Without this setting Netgear GA302T PHY does not
3153 * ??? send/receive packets...
3155 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3156 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3157 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3158 tw32_f(MAC_MI_MODE, tp->mi_mode);
3162 tw32_f(MAC_MODE, tp->mac_mode);
3165 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3166 /* Polled via timer. */
3167 tw32_f(MAC_EVENT, 0);
3169 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3174 current_link_up == 1 &&
3175 tp->link_config.active_speed == SPEED_1000 &&
3176 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3177 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3180 (MAC_STATUS_SYNC_CHANGED |
3181 MAC_STATUS_CFG_CHANGED));
3184 NIC_SRAM_FIRMWARE_MBOX,
3185 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3188 /* Prevent send BD corruption. */
3189 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3190 u16 oldlnkctl, newlnkctl;
3192 pci_read_config_word(tp->pdev,
3193 tp->pcie_cap + PCI_EXP_LNKCTL,
3195 if (tp->link_config.active_speed == SPEED_100 ||
3196 tp->link_config.active_speed == SPEED_10)
3197 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3199 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3200 if (newlnkctl != oldlnkctl)
3201 pci_write_config_word(tp->pdev,
3202 tp->pcie_cap + PCI_EXP_LNKCTL,
3204 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3205 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3206 if (tp->link_config.active_speed == SPEED_100 ||
3207 tp->link_config.active_speed == SPEED_10)
3208 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3210 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3211 if (newreg != oldreg)
3212 tw32(TG3_PCIE_LNKCTL, newreg);
3215 if (current_link_up != netif_carrier_ok(tp->dev)) {
3216 if (current_link_up)
3217 netif_carrier_on(tp->dev);
3219 netif_carrier_off(tp->dev);
3220 tg3_link_report(tp);
3226 struct tg3_fiber_aneginfo {
3228 #define ANEG_STATE_UNKNOWN 0
3229 #define ANEG_STATE_AN_ENABLE 1
3230 #define ANEG_STATE_RESTART_INIT 2
3231 #define ANEG_STATE_RESTART 3
3232 #define ANEG_STATE_DISABLE_LINK_OK 4
3233 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3234 #define ANEG_STATE_ABILITY_DETECT 6
3235 #define ANEG_STATE_ACK_DETECT_INIT 7
3236 #define ANEG_STATE_ACK_DETECT 8
3237 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3238 #define ANEG_STATE_COMPLETE_ACK 10
3239 #define ANEG_STATE_IDLE_DETECT_INIT 11
3240 #define ANEG_STATE_IDLE_DETECT 12
3241 #define ANEG_STATE_LINK_OK 13
3242 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3243 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3246 #define MR_AN_ENABLE 0x00000001
3247 #define MR_RESTART_AN 0x00000002
3248 #define MR_AN_COMPLETE 0x00000004
3249 #define MR_PAGE_RX 0x00000008
3250 #define MR_NP_LOADED 0x00000010
3251 #define MR_TOGGLE_TX 0x00000020
3252 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3253 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3254 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3255 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3256 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3257 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3258 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3259 #define MR_TOGGLE_RX 0x00002000
3260 #define MR_NP_RX 0x00004000
3262 #define MR_LINK_OK 0x80000000
3264 unsigned long link_time, cur_time;
3266 u32 ability_match_cfg;
3267 int ability_match_count;
3269 char ability_match, idle_match, ack_match;
3271 u32 txconfig, rxconfig;
3272 #define ANEG_CFG_NP 0x00000080
3273 #define ANEG_CFG_ACK 0x00000040
3274 #define ANEG_CFG_RF2 0x00000020
3275 #define ANEG_CFG_RF1 0x00000010
3276 #define ANEG_CFG_PS2 0x00000001
3277 #define ANEG_CFG_PS1 0x00008000
3278 #define ANEG_CFG_HD 0x00004000
3279 #define ANEG_CFG_FD 0x00002000
3280 #define ANEG_CFG_INVAL 0x00001f06
3285 #define ANEG_TIMER_ENAB 2
3286 #define ANEG_FAILED -1
3288 #define ANEG_STATE_SETTLE_TIME 10000
3290 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3291 struct tg3_fiber_aneginfo *ap)
3294 unsigned long delta;
3298 if (ap->state == ANEG_STATE_UNKNOWN) {
3302 ap->ability_match_cfg = 0;
3303 ap->ability_match_count = 0;
3304 ap->ability_match = 0;
3310 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3311 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3313 if (rx_cfg_reg != ap->ability_match_cfg) {
3314 ap->ability_match_cfg = rx_cfg_reg;
3315 ap->ability_match = 0;
3316 ap->ability_match_count = 0;
3318 if (++ap->ability_match_count > 1) {
3319 ap->ability_match = 1;
3320 ap->ability_match_cfg = rx_cfg_reg;
3323 if (rx_cfg_reg & ANEG_CFG_ACK)
3331 ap->ability_match_cfg = 0;
3332 ap->ability_match_count = 0;
3333 ap->ability_match = 0;
3339 ap->rxconfig = rx_cfg_reg;
3343 case ANEG_STATE_UNKNOWN:
3344 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3345 ap->state = ANEG_STATE_AN_ENABLE;
3348 case ANEG_STATE_AN_ENABLE:
3349 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3350 if (ap->flags & MR_AN_ENABLE) {
3353 ap->ability_match_cfg = 0;
3354 ap->ability_match_count = 0;
3355 ap->ability_match = 0;
3359 ap->state = ANEG_STATE_RESTART_INIT;
3361 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3365 case ANEG_STATE_RESTART_INIT:
3366 ap->link_time = ap->cur_time;
3367 ap->flags &= ~(MR_NP_LOADED);
3369 tw32(MAC_TX_AUTO_NEG, 0);
3370 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3371 tw32_f(MAC_MODE, tp->mac_mode);
3374 ret = ANEG_TIMER_ENAB;
3375 ap->state = ANEG_STATE_RESTART;
3378 case ANEG_STATE_RESTART:
3379 delta = ap->cur_time - ap->link_time;
3380 if (delta > ANEG_STATE_SETTLE_TIME) {
3381 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3383 ret = ANEG_TIMER_ENAB;
3387 case ANEG_STATE_DISABLE_LINK_OK:
3391 case ANEG_STATE_ABILITY_DETECT_INIT:
3392 ap->flags &= ~(MR_TOGGLE_TX);
3393 ap->txconfig = ANEG_CFG_FD;
3394 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3395 if (flowctrl & ADVERTISE_1000XPAUSE)
3396 ap->txconfig |= ANEG_CFG_PS1;
3397 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3398 ap->txconfig |= ANEG_CFG_PS2;
3399 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3400 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3401 tw32_f(MAC_MODE, tp->mac_mode);
3404 ap->state = ANEG_STATE_ABILITY_DETECT;
3407 case ANEG_STATE_ABILITY_DETECT:
3408 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3409 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3413 case ANEG_STATE_ACK_DETECT_INIT:
3414 ap->txconfig |= ANEG_CFG_ACK;
3415 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3416 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3417 tw32_f(MAC_MODE, tp->mac_mode);
3420 ap->state = ANEG_STATE_ACK_DETECT;
3423 case ANEG_STATE_ACK_DETECT:
3424 if (ap->ack_match != 0) {
3425 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3426 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3427 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3429 ap->state = ANEG_STATE_AN_ENABLE;
3431 } else if (ap->ability_match != 0 &&
3432 ap->rxconfig == 0) {
3433 ap->state = ANEG_STATE_AN_ENABLE;
3437 case ANEG_STATE_COMPLETE_ACK_INIT:
3438 if (ap->rxconfig & ANEG_CFG_INVAL) {
3442 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3443 MR_LP_ADV_HALF_DUPLEX |
3444 MR_LP_ADV_SYM_PAUSE |
3445 MR_LP_ADV_ASYM_PAUSE |
3446 MR_LP_ADV_REMOTE_FAULT1 |
3447 MR_LP_ADV_REMOTE_FAULT2 |
3448 MR_LP_ADV_NEXT_PAGE |
3451 if (ap->rxconfig & ANEG_CFG_FD)
3452 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3453 if (ap->rxconfig & ANEG_CFG_HD)
3454 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3455 if (ap->rxconfig & ANEG_CFG_PS1)
3456 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3457 if (ap->rxconfig & ANEG_CFG_PS2)
3458 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3459 if (ap->rxconfig & ANEG_CFG_RF1)
3460 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3461 if (ap->rxconfig & ANEG_CFG_RF2)
3462 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3463 if (ap->rxconfig & ANEG_CFG_NP)
3464 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3466 ap->link_time = ap->cur_time;
3468 ap->flags ^= (MR_TOGGLE_TX);
3469 if (ap->rxconfig & 0x0008)
3470 ap->flags |= MR_TOGGLE_RX;
3471 if (ap->rxconfig & ANEG_CFG_NP)
3472 ap->flags |= MR_NP_RX;
3473 ap->flags |= MR_PAGE_RX;
3475 ap->state = ANEG_STATE_COMPLETE_ACK;
3476 ret = ANEG_TIMER_ENAB;
3479 case ANEG_STATE_COMPLETE_ACK:
3480 if (ap->ability_match != 0 &&
3481 ap->rxconfig == 0) {
3482 ap->state = ANEG_STATE_AN_ENABLE;
3485 delta = ap->cur_time - ap->link_time;
3486 if (delta > ANEG_STATE_SETTLE_TIME) {
3487 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3488 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3490 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3491 !(ap->flags & MR_NP_RX)) {
3492 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3500 case ANEG_STATE_IDLE_DETECT_INIT:
3501 ap->link_time = ap->cur_time;
3502 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3503 tw32_f(MAC_MODE, tp->mac_mode);
3506 ap->state = ANEG_STATE_IDLE_DETECT;
3507 ret = ANEG_TIMER_ENAB;
3510 case ANEG_STATE_IDLE_DETECT:
3511 if (ap->ability_match != 0 &&
3512 ap->rxconfig == 0) {
3513 ap->state = ANEG_STATE_AN_ENABLE;
3516 delta = ap->cur_time - ap->link_time;
3517 if (delta > ANEG_STATE_SETTLE_TIME) {
3518 /* XXX another gem from the Broadcom driver :( */
3519 ap->state = ANEG_STATE_LINK_OK;
3523 case ANEG_STATE_LINK_OK:
3524 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3528 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3529 /* ??? unimplemented */
3532 case ANEG_STATE_NEXT_PAGE_WAIT:
3533 /* ??? unimplemented */
3544 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3547 struct tg3_fiber_aneginfo aninfo;
3548 int status = ANEG_FAILED;
3552 tw32_f(MAC_TX_AUTO_NEG, 0);
3554 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3555 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3558 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3561 memset(&aninfo, 0, sizeof(aninfo));
3562 aninfo.flags |= MR_AN_ENABLE;
3563 aninfo.state = ANEG_STATE_UNKNOWN;
3564 aninfo.cur_time = 0;
3566 while (++tick < 195000) {
3567 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3568 if (status == ANEG_DONE || status == ANEG_FAILED)
3574 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3575 tw32_f(MAC_MODE, tp->mac_mode);
3578 *txflags = aninfo.txconfig;
3579 *rxflags = aninfo.flags;
3581 if (status == ANEG_DONE &&
3582 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3583 MR_LP_ADV_FULL_DUPLEX)))
3589 static void tg3_init_bcm8002(struct tg3 *tp)
3591 u32 mac_status = tr32(MAC_STATUS);
3594 /* Reset when initting first time or we have a link. */
3595 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3596 !(mac_status & MAC_STATUS_PCS_SYNCED))
3599 /* Set PLL lock range. */
3600 tg3_writephy(tp, 0x16, 0x8007);
3603 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3605 /* Wait for reset to complete. */
3606 /* XXX schedule_timeout() ... */
3607 for (i = 0; i < 500; i++)
3610 /* Config mode; select PMA/Ch 1 regs. */
3611 tg3_writephy(tp, 0x10, 0x8411);
3613 /* Enable auto-lock and comdet, select txclk for tx. */
3614 tg3_writephy(tp, 0x11, 0x0a10);
3616 tg3_writephy(tp, 0x18, 0x00a0);
3617 tg3_writephy(tp, 0x16, 0x41ff);
3619 /* Assert and deassert POR. */
3620 tg3_writephy(tp, 0x13, 0x0400);
3622 tg3_writephy(tp, 0x13, 0x0000);
3624 tg3_writephy(tp, 0x11, 0x0a50);
3626 tg3_writephy(tp, 0x11, 0x0a10);
3628 /* Wait for signal to stabilize */
3629 /* XXX schedule_timeout() ... */
3630 for (i = 0; i < 15000; i++)
3633 /* Deselect the channel register so we can read the PHYID
3636 tg3_writephy(tp, 0x10, 0x8011);
3639 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3642 u32 sg_dig_ctrl, sg_dig_status;
3643 u32 serdes_cfg, expected_sg_dig_ctrl;
3644 int workaround, port_a;
3645 int current_link_up;
3648 expected_sg_dig_ctrl = 0;
3651 current_link_up = 0;
3653 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3654 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3656 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3659 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3660 /* preserve bits 20-23 for voltage regulator */
3661 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3664 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3666 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3667 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3669 u32 val = serdes_cfg;
3675 tw32_f(MAC_SERDES_CFG, val);
3678 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3680 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3681 tg3_setup_flow_control(tp, 0, 0);
3682 current_link_up = 1;
3687 /* Want auto-negotiation. */
3688 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3690 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3691 if (flowctrl & ADVERTISE_1000XPAUSE)
3692 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3693 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3694 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3696 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3697 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3698 tp->serdes_counter &&
3699 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3700 MAC_STATUS_RCVD_CFG)) ==
3701 MAC_STATUS_PCS_SYNCED)) {
3702 tp->serdes_counter--;
3703 current_link_up = 1;
3708 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3709 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3711 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3713 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3714 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3715 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3716 MAC_STATUS_SIGNAL_DET)) {
3717 sg_dig_status = tr32(SG_DIG_STATUS);
3718 mac_status = tr32(MAC_STATUS);
3720 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3721 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3722 u32 local_adv = 0, remote_adv = 0;
3724 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3725 local_adv |= ADVERTISE_1000XPAUSE;
3726 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3727 local_adv |= ADVERTISE_1000XPSE_ASYM;
3729 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3730 remote_adv |= LPA_1000XPAUSE;
3731 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3732 remote_adv |= LPA_1000XPAUSE_ASYM;
3734 tg3_setup_flow_control(tp, local_adv, remote_adv);
3735 current_link_up = 1;
3736 tp->serdes_counter = 0;
3737 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3738 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3739 if (tp->serdes_counter)
3740 tp->serdes_counter--;
3743 u32 val = serdes_cfg;
3750 tw32_f(MAC_SERDES_CFG, val);
3753 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3756 /* Link parallel detection - link is up */
3757 /* only if we have PCS_SYNC and not */
3758 /* receiving config code words */
3759 mac_status = tr32(MAC_STATUS);
3760 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3761 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3762 tg3_setup_flow_control(tp, 0, 0);
3763 current_link_up = 1;
3765 TG3_FLG2_PARALLEL_DETECT;
3766 tp->serdes_counter =
3767 SERDES_PARALLEL_DET_TIMEOUT;
3769 goto restart_autoneg;
3773 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3774 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3778 return current_link_up;
3781 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3783 int current_link_up = 0;
3785 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3788 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3789 u32 txflags, rxflags;
3792 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3793 u32 local_adv = 0, remote_adv = 0;
3795 if (txflags & ANEG_CFG_PS1)
3796 local_adv |= ADVERTISE_1000XPAUSE;
3797 if (txflags & ANEG_CFG_PS2)
3798 local_adv |= ADVERTISE_1000XPSE_ASYM;
3800 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3801 remote_adv |= LPA_1000XPAUSE;
3802 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3803 remote_adv |= LPA_1000XPAUSE_ASYM;
3805 tg3_setup_flow_control(tp, local_adv, remote_adv);
3807 current_link_up = 1;
3809 for (i = 0; i < 30; i++) {
3812 (MAC_STATUS_SYNC_CHANGED |
3813 MAC_STATUS_CFG_CHANGED));
3815 if ((tr32(MAC_STATUS) &
3816 (MAC_STATUS_SYNC_CHANGED |
3817 MAC_STATUS_CFG_CHANGED)) == 0)
3821 mac_status = tr32(MAC_STATUS);
3822 if (current_link_up == 0 &&
3823 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3824 !(mac_status & MAC_STATUS_RCVD_CFG))
3825 current_link_up = 1;
3827 tg3_setup_flow_control(tp, 0, 0);
3829 /* Forcing 1000FD link up. */
3830 current_link_up = 1;
3832 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3835 tw32_f(MAC_MODE, tp->mac_mode);
3840 return current_link_up;
3843 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3846 u16 orig_active_speed;
3847 u8 orig_active_duplex;
3849 int current_link_up;
3852 orig_pause_cfg = tp->link_config.active_flowctrl;
3853 orig_active_speed = tp->link_config.active_speed;
3854 orig_active_duplex = tp->link_config.active_duplex;
3856 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3857 netif_carrier_ok(tp->dev) &&
3858 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3859 mac_status = tr32(MAC_STATUS);
3860 mac_status &= (MAC_STATUS_PCS_SYNCED |
3861 MAC_STATUS_SIGNAL_DET |
3862 MAC_STATUS_CFG_CHANGED |
3863 MAC_STATUS_RCVD_CFG);
3864 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3865 MAC_STATUS_SIGNAL_DET)) {
3866 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3867 MAC_STATUS_CFG_CHANGED));
3872 tw32_f(MAC_TX_AUTO_NEG, 0);
3874 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3875 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3876 tw32_f(MAC_MODE, tp->mac_mode);
3879 if (tp->phy_id == PHY_ID_BCM8002)
3880 tg3_init_bcm8002(tp);
3882 /* Enable link change event even when serdes polling. */
3883 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3886 current_link_up = 0;
3887 mac_status = tr32(MAC_STATUS);
3889 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3890 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3892 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3894 tp->hw_status->status =
3895 (SD_STATUS_UPDATED |
3896 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3898 for (i = 0; i < 100; i++) {
3899 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3900 MAC_STATUS_CFG_CHANGED));
3902 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3903 MAC_STATUS_CFG_CHANGED |
3904 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3908 mac_status = tr32(MAC_STATUS);
3909 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3910 current_link_up = 0;
3911 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3912 tp->serdes_counter == 0) {
3913 tw32_f(MAC_MODE, (tp->mac_mode |
3914 MAC_MODE_SEND_CONFIGS));
3916 tw32_f(MAC_MODE, tp->mac_mode);
3920 if (current_link_up == 1) {
3921 tp->link_config.active_speed = SPEED_1000;
3922 tp->link_config.active_duplex = DUPLEX_FULL;
3923 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3924 LED_CTRL_LNKLED_OVERRIDE |
3925 LED_CTRL_1000MBPS_ON));
3927 tp->link_config.active_speed = SPEED_INVALID;
3928 tp->link_config.active_duplex = DUPLEX_INVALID;
3929 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3930 LED_CTRL_LNKLED_OVERRIDE |
3931 LED_CTRL_TRAFFIC_OVERRIDE));
3934 if (current_link_up != netif_carrier_ok(tp->dev)) {
3935 if (current_link_up)
3936 netif_carrier_on(tp->dev);
3938 netif_carrier_off(tp->dev);
3939 tg3_link_report(tp);
3941 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3942 if (orig_pause_cfg != now_pause_cfg ||
3943 orig_active_speed != tp->link_config.active_speed ||
3944 orig_active_duplex != tp->link_config.active_duplex)
3945 tg3_link_report(tp);
3951 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3953 int current_link_up, err = 0;
3957 u32 local_adv, remote_adv;
3959 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3960 tw32_f(MAC_MODE, tp->mac_mode);
3966 (MAC_STATUS_SYNC_CHANGED |
3967 MAC_STATUS_CFG_CHANGED |
3968 MAC_STATUS_MI_COMPLETION |
3969 MAC_STATUS_LNKSTATE_CHANGED));
3975 current_link_up = 0;
3976 current_speed = SPEED_INVALID;
3977 current_duplex = DUPLEX_INVALID;
3979 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3980 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3982 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3983 bmsr |= BMSR_LSTATUS;
3985 bmsr &= ~BMSR_LSTATUS;
3988 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3990 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3991 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3992 /* do nothing, just check for link up at the end */
3993 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3996 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3997 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3998 ADVERTISE_1000XPAUSE |
3999 ADVERTISE_1000XPSE_ASYM |
4002 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4004 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4005 new_adv |= ADVERTISE_1000XHALF;
4006 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4007 new_adv |= ADVERTISE_1000XFULL;
4009 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4010 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4011 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4012 tg3_writephy(tp, MII_BMCR, bmcr);
4014 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4015 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4016 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4023 bmcr &= ~BMCR_SPEED1000;
4024 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4026 if (tp->link_config.duplex == DUPLEX_FULL)
4027 new_bmcr |= BMCR_FULLDPLX;
4029 if (new_bmcr != bmcr) {
4030 /* BMCR_SPEED1000 is a reserved bit that needs
4031 * to be set on write.
4033 new_bmcr |= BMCR_SPEED1000;
4035 /* Force a linkdown */
4036 if (netif_carrier_ok(tp->dev)) {
4039 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4040 adv &= ~(ADVERTISE_1000XFULL |
4041 ADVERTISE_1000XHALF |
4043 tg3_writephy(tp, MII_ADVERTISE, adv);
4044 tg3_writephy(tp, MII_BMCR, bmcr |
4048 netif_carrier_off(tp->dev);
4050 tg3_writephy(tp, MII_BMCR, new_bmcr);
4052 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4056 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4057 bmsr |= BMSR_LSTATUS;
4059 bmsr &= ~BMSR_LSTATUS;
4061 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4065 if (bmsr & BMSR_LSTATUS) {
4066 current_speed = SPEED_1000;
4067 current_link_up = 1;
4068 if (bmcr & BMCR_FULLDPLX)
4069 current_duplex = DUPLEX_FULL;
4071 current_duplex = DUPLEX_HALF;
4076 if (bmcr & BMCR_ANENABLE) {
4079 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4080 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4081 common = local_adv & remote_adv;
4082 if (common & (ADVERTISE_1000XHALF |
4083 ADVERTISE_1000XFULL)) {
4084 if (common & ADVERTISE_1000XFULL)
4085 current_duplex = DUPLEX_FULL;
4087 current_duplex = DUPLEX_HALF;
4090 current_link_up = 0;
4094 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4095 tg3_setup_flow_control(tp, local_adv, remote_adv);
4097 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4098 if (tp->link_config.active_duplex == DUPLEX_HALF)
4099 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4101 tw32_f(MAC_MODE, tp->mac_mode);
4104 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4106 tp->link_config.active_speed = current_speed;
4107 tp->link_config.active_duplex = current_duplex;
4109 if (current_link_up != netif_carrier_ok(tp->dev)) {
4110 if (current_link_up)
4111 netif_carrier_on(tp->dev);
4113 netif_carrier_off(tp->dev);
4114 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4116 tg3_link_report(tp);
4121 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4123 if (tp->serdes_counter) {
4124 /* Give autoneg time to complete. */
4125 tp->serdes_counter--;
4128 if (!netif_carrier_ok(tp->dev) &&
4129 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4132 tg3_readphy(tp, MII_BMCR, &bmcr);
4133 if (bmcr & BMCR_ANENABLE) {
4136 /* Select shadow register 0x1f */
4137 tg3_writephy(tp, 0x1c, 0x7c00);
4138 tg3_readphy(tp, 0x1c, &phy1);
4140 /* Select expansion interrupt status register */
4141 tg3_writephy(tp, 0x17, 0x0f01);
4142 tg3_readphy(tp, 0x15, &phy2);
4143 tg3_readphy(tp, 0x15, &phy2);
4145 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4146 /* We have signal detect and not receiving
4147 * config code words, link is up by parallel
4151 bmcr &= ~BMCR_ANENABLE;
4152 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4153 tg3_writephy(tp, MII_BMCR, bmcr);
4154 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4158 else if (netif_carrier_ok(tp->dev) &&
4159 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4160 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4163 /* Select expansion interrupt status register */
4164 tg3_writephy(tp, 0x17, 0x0f01);
4165 tg3_readphy(tp, 0x15, &phy2);
4169 /* Config code words received, turn on autoneg. */
4170 tg3_readphy(tp, MII_BMCR, &bmcr);
4171 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4173 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4183 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4184 err = tg3_setup_fiber_phy(tp, force_reset);
4185 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4186 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4188 err = tg3_setup_copper_phy(tp, force_reset);
4191 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4194 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4195 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4197 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4202 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4203 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4204 tw32(GRC_MISC_CFG, val);
4207 if (tp->link_config.active_speed == SPEED_1000 &&
4208 tp->link_config.active_duplex == DUPLEX_HALF)
4209 tw32(MAC_TX_LENGTHS,
4210 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4211 (6 << TX_LENGTHS_IPG_SHIFT) |
4212 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4214 tw32(MAC_TX_LENGTHS,
4215 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4216 (6 << TX_LENGTHS_IPG_SHIFT) |
4217 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4219 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4220 if (netif_carrier_ok(tp->dev)) {
4221 tw32(HOSTCC_STAT_COAL_TICKS,
4222 tp->coal.stats_block_coalesce_usecs);
4224 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4228 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4229 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4230 if (!netif_carrier_ok(tp->dev))
4231 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4234 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4235 tw32(PCIE_PWR_MGMT_THRESH, val);
4241 /* This is called whenever we suspect that the system chipset is re-
4242 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4243 * is bogus tx completions. We try to recover by setting the
4244 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4247 static void tg3_tx_recover(struct tg3 *tp)
4249 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4250 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4252 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4253 "mapped I/O cycles to the network device, attempting to "
4254 "recover. Please report the problem to the driver maintainer "
4255 "and include system chipset information.\n", tp->dev->name);
4257 spin_lock(&tp->lock);
4258 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4259 spin_unlock(&tp->lock);
4262 static inline u32 tg3_tx_avail(struct tg3 *tp)
4265 return (tp->tx_pending -
4266 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4269 /* Tigon3 never reports partial packet sends. So we do not
4270 * need special logic to handle SKBs that have not had all
4271 * of their frags sent yet, like SunGEM does.
4273 static void tg3_tx(struct tg3 *tp)
4275 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4276 u32 sw_idx = tp->tx_cons;
4278 while (sw_idx != hw_idx) {
4279 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4280 struct sk_buff *skb = ri->skb;
4283 if (unlikely(skb == NULL)) {
4288 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4292 sw_idx = NEXT_TX(sw_idx);
4294 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4295 ri = &tp->tx_buffers[sw_idx];
4296 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4298 sw_idx = NEXT_TX(sw_idx);
4303 if (unlikely(tx_bug)) {
4309 tp->tx_cons = sw_idx;
4311 /* Need to make the tx_cons update visible to tg3_start_xmit()
4312 * before checking for netif_queue_stopped(). Without the
4313 * memory barrier, there is a small possibility that tg3_start_xmit()
4314 * will miss it and cause the queue to be stopped forever.
4318 if (unlikely(netif_queue_stopped(tp->dev) &&
4319 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4320 netif_tx_lock(tp->dev);
4321 if (netif_queue_stopped(tp->dev) &&
4322 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4323 netif_wake_queue(tp->dev);
4324 netif_tx_unlock(tp->dev);
4328 /* Returns size of skb allocated or < 0 on error.
4330 * We only need to fill in the address because the other members
4331 * of the RX descriptor are invariant, see tg3_init_rings.
4333 * Note the purposeful assymetry of cpu vs. chip accesses. For
4334 * posting buffers we only dirty the first cache line of the RX
4335 * descriptor (containing the address). Whereas for the RX status
4336 * buffers the cpu only reads the last cacheline of the RX descriptor
4337 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4339 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4340 int src_idx, u32 dest_idx_unmasked)
4342 struct tg3_rx_buffer_desc *desc;
4343 struct ring_info *map, *src_map;
4344 struct sk_buff *skb;
4346 int skb_size, dest_idx;
4349 switch (opaque_key) {
4350 case RXD_OPAQUE_RING_STD:
4351 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4352 desc = &tp->rx_std[dest_idx];
4353 map = &tp->rx_std_buffers[dest_idx];
4355 src_map = &tp->rx_std_buffers[src_idx];
4356 skb_size = tp->rx_pkt_buf_sz;
4359 case RXD_OPAQUE_RING_JUMBO:
4360 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4361 desc = &tp->rx_jumbo[dest_idx];
4362 map = &tp->rx_jumbo_buffers[dest_idx];
4364 src_map = &tp->rx_jumbo_buffers[src_idx];
4365 skb_size = RX_JUMBO_PKT_BUF_SZ;
4372 /* Do not overwrite any of the map or rp information
4373 * until we are sure we can commit to a new buffer.
4375 * Callers depend upon this behavior and assume that
4376 * we leave everything unchanged if we fail.
4378 skb = netdev_alloc_skb(tp->dev, skb_size);
4382 skb_reserve(skb, tp->rx_offset);
4384 mapping = pci_map_single(tp->pdev, skb->data,
4385 skb_size - tp->rx_offset,
4386 PCI_DMA_FROMDEVICE);
4389 pci_unmap_addr_set(map, mapping, mapping);
4391 if (src_map != NULL)
4392 src_map->skb = NULL;
4394 desc->addr_hi = ((u64)mapping >> 32);
4395 desc->addr_lo = ((u64)mapping & 0xffffffff);
4400 /* We only need to move over in the address because the other
4401 * members of the RX descriptor are invariant. See notes above
4402 * tg3_alloc_rx_skb for full details.
4404 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4405 int src_idx, u32 dest_idx_unmasked)
4407 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4408 struct ring_info *src_map, *dest_map;
4411 switch (opaque_key) {
4412 case RXD_OPAQUE_RING_STD:
4413 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4414 dest_desc = &tp->rx_std[dest_idx];
4415 dest_map = &tp->rx_std_buffers[dest_idx];
4416 src_desc = &tp->rx_std[src_idx];
4417 src_map = &tp->rx_std_buffers[src_idx];
4420 case RXD_OPAQUE_RING_JUMBO:
4421 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4422 dest_desc = &tp->rx_jumbo[dest_idx];
4423 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4424 src_desc = &tp->rx_jumbo[src_idx];
4425 src_map = &tp->rx_jumbo_buffers[src_idx];
4432 dest_map->skb = src_map->skb;
4433 pci_unmap_addr_set(dest_map, mapping,
4434 pci_unmap_addr(src_map, mapping));
4435 dest_desc->addr_hi = src_desc->addr_hi;
4436 dest_desc->addr_lo = src_desc->addr_lo;
4438 src_map->skb = NULL;
4441 #if TG3_VLAN_TAG_USED
4442 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4444 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4448 /* The RX ring scheme is composed of multiple rings which post fresh
4449 * buffers to the chip, and one special ring the chip uses to report
4450 * status back to the host.
4452 * The special ring reports the status of received packets to the
4453 * host. The chip does not write into the original descriptor the
4454 * RX buffer was obtained from. The chip simply takes the original
4455 * descriptor as provided by the host, updates the status and length
4456 * field, then writes this into the next status ring entry.
4458 * Each ring the host uses to post buffers to the chip is described
4459 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4460 * it is first placed into the on-chip ram. When the packet's length
4461 * is known, it walks down the TG3_BDINFO entries to select the ring.
4462 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4463 * which is within the range of the new packet's length is chosen.
4465 * The "separate ring for rx status" scheme may sound queer, but it makes
4466 * sense from a cache coherency perspective. If only the host writes
4467 * to the buffer post rings, and only the chip writes to the rx status
4468 * rings, then cache lines never move beyond shared-modified state.
4469 * If both the host and chip were to write into the same ring, cache line
4470 * eviction could occur since both entities want it in an exclusive state.
4472 static int tg3_rx(struct tg3 *tp, int budget)
4474 u32 work_mask, rx_std_posted = 0;
4475 u32 sw_idx = tp->rx_rcb_ptr;
4479 hw_idx = tp->hw_status->idx[0].rx_producer;
4481 * We need to order the read of hw_idx and the read of
4482 * the opaque cookie.
4487 while (sw_idx != hw_idx && budget > 0) {
4488 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4490 struct sk_buff *skb;
4491 dma_addr_t dma_addr;
4492 u32 opaque_key, desc_idx, *post_ptr;
4494 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4495 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4496 if (opaque_key == RXD_OPAQUE_RING_STD) {
4497 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4499 skb = tp->rx_std_buffers[desc_idx].skb;
4500 post_ptr = &tp->rx_std_ptr;
4502 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4503 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4505 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4506 post_ptr = &tp->rx_jumbo_ptr;
4509 goto next_pkt_nopost;
4512 work_mask |= opaque_key;
4514 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4515 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4517 tg3_recycle_rx(tp, opaque_key,
4518 desc_idx, *post_ptr);
4520 /* Other statistics kept track of by card. */
4521 tp->net_stats.rx_dropped++;
4525 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4528 if (len > RX_COPY_THRESHOLD
4529 && tp->rx_offset == NET_IP_ALIGN
4530 /* rx_offset will likely not equal NET_IP_ALIGN
4531 * if this is a 5701 card running in PCI-X mode
4532 * [see tg3_get_invariants()]
4537 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4538 desc_idx, *post_ptr);
4542 pci_unmap_single(tp->pdev, dma_addr,
4543 skb_size - tp->rx_offset,
4544 PCI_DMA_FROMDEVICE);
4548 struct sk_buff *copy_skb;
4550 tg3_recycle_rx(tp, opaque_key,
4551 desc_idx, *post_ptr);
4553 copy_skb = netdev_alloc_skb(tp->dev,
4554 len + TG3_RAW_IP_ALIGN);
4555 if (copy_skb == NULL)
4556 goto drop_it_no_recycle;
4558 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4559 skb_put(copy_skb, len);
4560 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4561 skb_copy_from_linear_data(skb, copy_skb->data, len);
4562 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4564 /* We'll reuse the original ring buffer. */
4568 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4569 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4570 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4571 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4572 skb->ip_summed = CHECKSUM_UNNECESSARY;
4574 skb->ip_summed = CHECKSUM_NONE;
4576 skb->protocol = eth_type_trans(skb, tp->dev);
4578 if (len > (tp->dev->mtu + ETH_HLEN) &&
4579 skb->protocol != htons(ETH_P_8021Q)) {
4584 #if TG3_VLAN_TAG_USED
4585 if (tp->vlgrp != NULL &&
4586 desc->type_flags & RXD_FLAG_VLAN) {
4587 tg3_vlan_rx(tp, skb,
4588 desc->err_vlan & RXD_VLAN_MASK);
4591 napi_gro_receive(&tp->napi, skb);
4599 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4600 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4602 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4603 TG3_64BIT_REG_LOW, idx);
4604 work_mask &= ~RXD_OPAQUE_RING_STD;
4609 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4611 /* Refresh hw_idx to see if there is new work */
4612 if (sw_idx == hw_idx) {
4613 hw_idx = tp->hw_status->idx[0].rx_producer;
4618 /* ACK the status ring. */
4619 tp->rx_rcb_ptr = sw_idx;
4620 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4622 /* Refill RX ring(s). */
4623 if (work_mask & RXD_OPAQUE_RING_STD) {
4624 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4625 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4628 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4629 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4630 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4638 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4640 struct tg3_hw_status *sblk = tp->hw_status;
4642 /* handle link change and other phy events */
4643 if (!(tp->tg3_flags &
4644 (TG3_FLAG_USE_LINKCHG_REG |
4645 TG3_FLAG_POLL_SERDES))) {
4646 if (sblk->status & SD_STATUS_LINK_CHG) {
4647 sblk->status = SD_STATUS_UPDATED |
4648 (sblk->status & ~SD_STATUS_LINK_CHG);
4649 spin_lock(&tp->lock);
4650 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4652 (MAC_STATUS_SYNC_CHANGED |
4653 MAC_STATUS_CFG_CHANGED |
4654 MAC_STATUS_MI_COMPLETION |
4655 MAC_STATUS_LNKSTATE_CHANGED));
4658 tg3_setup_phy(tp, 0);
4659 spin_unlock(&tp->lock);
4663 /* run TX completion thread */
4664 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4666 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4670 /* run RX thread, within the bounds set by NAPI.
4671 * All RX "locking" is done by ensuring outside
4672 * code synchronizes with tg3->napi.poll()
4674 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4675 work_done += tg3_rx(tp, budget - work_done);
4680 static int tg3_poll(struct napi_struct *napi, int budget)
4682 struct tg3 *tp = container_of(napi, struct tg3, napi);
4684 struct tg3_hw_status *sblk = tp->hw_status;
4687 work_done = tg3_poll_work(tp, work_done, budget);
4689 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4692 if (unlikely(work_done >= budget))
4695 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4696 /* tp->last_tag is used in tg3_restart_ints() below
4697 * to tell the hw how much work has been processed,
4698 * so we must read it before checking for more work.
4700 tp->last_tag = sblk->status_tag;
4701 tp->last_irq_tag = tp->last_tag;
4704 sblk->status &= ~SD_STATUS_UPDATED;
4706 if (likely(!tg3_has_work(tp))) {
4707 napi_complete(napi);
4708 tg3_restart_ints(tp);
4716 /* work_done is guaranteed to be less than budget. */
4717 napi_complete(napi);
4718 schedule_work(&tp->reset_task);
4722 static void tg3_irq_quiesce(struct tg3 *tp)
4724 BUG_ON(tp->irq_sync);
4729 synchronize_irq(tp->pdev->irq);
4732 static inline int tg3_irq_sync(struct tg3 *tp)
4734 return tp->irq_sync;
4737 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4738 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4739 * with as well. Most of the time, this is not necessary except when
4740 * shutting down the device.
4742 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4744 spin_lock_bh(&tp->lock);
4746 tg3_irq_quiesce(tp);
4749 static inline void tg3_full_unlock(struct tg3 *tp)
4751 spin_unlock_bh(&tp->lock);
4754 /* One-shot MSI handler - Chip automatically disables interrupt
4755 * after sending MSI so driver doesn't have to do it.
4757 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4759 struct net_device *dev = dev_id;
4760 struct tg3 *tp = netdev_priv(dev);
4762 prefetch(tp->hw_status);
4763 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4765 if (likely(!tg3_irq_sync(tp)))
4766 napi_schedule(&tp->napi);
4771 /* MSI ISR - No need to check for interrupt sharing and no need to
4772 * flush status block and interrupt mailbox. PCI ordering rules
4773 * guarantee that MSI will arrive after the status block.
4775 static irqreturn_t tg3_msi(int irq, void *dev_id)
4777 struct net_device *dev = dev_id;
4778 struct tg3 *tp = netdev_priv(dev);
4780 prefetch(tp->hw_status);
4781 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4783 * Writing any value to intr-mbox-0 clears PCI INTA# and
4784 * chip-internal interrupt pending events.
4785 * Writing non-zero to intr-mbox-0 additional tells the
4786 * NIC to stop sending us irqs, engaging "in-intr-handler"
4789 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4790 if (likely(!tg3_irq_sync(tp)))
4791 napi_schedule(&tp->napi);
4793 return IRQ_RETVAL(1);
4796 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4798 struct net_device *dev = dev_id;
4799 struct tg3 *tp = netdev_priv(dev);
4800 struct tg3_hw_status *sblk = tp->hw_status;
4801 unsigned int handled = 1;
4803 /* In INTx mode, it is possible for the interrupt to arrive at
4804 * the CPU before the status block posted prior to the interrupt.
4805 * Reading the PCI State register will confirm whether the
4806 * interrupt is ours and will flush the status block.
4808 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4809 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4810 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4817 * Writing any value to intr-mbox-0 clears PCI INTA# and
4818 * chip-internal interrupt pending events.
4819 * Writing non-zero to intr-mbox-0 additional tells the
4820 * NIC to stop sending us irqs, engaging "in-intr-handler"
4823 * Flush the mailbox to de-assert the IRQ immediately to prevent
4824 * spurious interrupts. The flush impacts performance but
4825 * excessive spurious interrupts can be worse in some cases.
4827 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4828 if (tg3_irq_sync(tp))
4830 sblk->status &= ~SD_STATUS_UPDATED;
4831 if (likely(tg3_has_work(tp))) {
4832 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4833 napi_schedule(&tp->napi);
4835 /* No work, shared interrupt perhaps? re-enable
4836 * interrupts, and flush that PCI write
4838 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4842 return IRQ_RETVAL(handled);
4845 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4847 struct net_device *dev = dev_id;
4848 struct tg3 *tp = netdev_priv(dev);
4849 struct tg3_hw_status *sblk = tp->hw_status;
4850 unsigned int handled = 1;
4852 /* In INTx mode, it is possible for the interrupt to arrive at
4853 * the CPU before the status block posted prior to the interrupt.
4854 * Reading the PCI State register will confirm whether the
4855 * interrupt is ours and will flush the status block.
4857 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4858 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4859 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4866 * writing any value to intr-mbox-0 clears PCI INTA# and
4867 * chip-internal interrupt pending events.
4868 * writing non-zero to intr-mbox-0 additional tells the
4869 * NIC to stop sending us irqs, engaging "in-intr-handler"
4872 * Flush the mailbox to de-assert the IRQ immediately to prevent
4873 * spurious interrupts. The flush impacts performance but
4874 * excessive spurious interrupts can be worse in some cases.
4876 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4879 * In a shared interrupt configuration, sometimes other devices'
4880 * interrupts will scream. We record the current status tag here
4881 * so that the above check can report that the screaming interrupts
4882 * are unhandled. Eventually they will be silenced.
4884 tp->last_irq_tag = sblk->status_tag;
4886 if (tg3_irq_sync(tp))
4889 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4891 napi_schedule(&tp->napi);
4894 return IRQ_RETVAL(handled);
4897 /* ISR for interrupt test */
4898 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4900 struct net_device *dev = dev_id;
4901 struct tg3 *tp = netdev_priv(dev);
4902 struct tg3_hw_status *sblk = tp->hw_status;
4904 if ((sblk->status & SD_STATUS_UPDATED) ||
4905 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4906 tg3_disable_ints(tp);
4907 return IRQ_RETVAL(1);
4909 return IRQ_RETVAL(0);
4912 static int tg3_init_hw(struct tg3 *, int);
4913 static int tg3_halt(struct tg3 *, int, int);
4915 /* Restart hardware after configuration changes, self-test, etc.
4916 * Invoked with tp->lock held.
4918 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4919 __releases(tp->lock)
4920 __acquires(tp->lock)
4924 err = tg3_init_hw(tp, reset_phy);
4926 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4927 "aborting.\n", tp->dev->name);
4928 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4929 tg3_full_unlock(tp);
4930 del_timer_sync(&tp->timer);
4932 napi_enable(&tp->napi);
4934 tg3_full_lock(tp, 0);
4939 #ifdef CONFIG_NET_POLL_CONTROLLER
4940 static void tg3_poll_controller(struct net_device *dev)
4942 struct tg3 *tp = netdev_priv(dev);
4944 tg3_interrupt(tp->pdev->irq, dev);
4948 static void tg3_reset_task(struct work_struct *work)
4950 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4952 unsigned int restart_timer;
4954 tg3_full_lock(tp, 0);
4956 if (!netif_running(tp->dev)) {
4957 tg3_full_unlock(tp);
4961 tg3_full_unlock(tp);
4967 tg3_full_lock(tp, 1);
4969 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4970 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4972 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4973 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4974 tp->write32_rx_mbox = tg3_write_flush_reg32;
4975 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4976 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4979 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4980 err = tg3_init_hw(tp, 1);
4984 tg3_netif_start(tp);
4987 mod_timer(&tp->timer, jiffies + 1);
4990 tg3_full_unlock(tp);
4996 static void tg3_dump_short_state(struct tg3 *tp)
4998 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4999 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5000 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5001 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5004 static void tg3_tx_timeout(struct net_device *dev)
5006 struct tg3 *tp = netdev_priv(dev);
5008 if (netif_msg_tx_err(tp)) {
5009 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5011 tg3_dump_short_state(tp);
5014 schedule_work(&tp->reset_task);
5017 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5018 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5020 u32 base = (u32) mapping & 0xffffffff;
5022 return ((base > 0xffffdcc0) &&
5023 (base + len + 8 < base));
5026 /* Test for DMA addresses > 40-bit */
5027 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5030 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5031 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5032 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5039 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5041 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5042 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5043 u32 last_plus_one, u32 *start,
5044 u32 base_flags, u32 mss)
5046 struct sk_buff *new_skb;
5047 dma_addr_t new_addr = 0;
5051 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5052 new_skb = skb_copy(skb, GFP_ATOMIC);
5054 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5056 new_skb = skb_copy_expand(skb,
5057 skb_headroom(skb) + more_headroom,
5058 skb_tailroom(skb), GFP_ATOMIC);
5064 /* New SKB is guaranteed to be linear. */
5066 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5067 new_addr = skb_shinfo(new_skb)->dma_head;
5069 /* Make sure new skb does not cross any 4G boundaries.
5070 * Drop the packet if it does.
5072 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5074 skb_dma_unmap(&tp->pdev->dev, new_skb,
5077 dev_kfree_skb(new_skb);
5080 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5081 base_flags, 1 | (mss << 1));
5082 *start = NEXT_TX(entry);
5086 /* Now clean up the sw ring entries. */
5088 while (entry != last_plus_one) {
5090 tp->tx_buffers[entry].skb = new_skb;
5092 tp->tx_buffers[entry].skb = NULL;
5094 entry = NEXT_TX(entry);
5098 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5104 static void tg3_set_txd(struct tg3 *tp, int entry,
5105 dma_addr_t mapping, int len, u32 flags,
5108 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5109 int is_end = (mss_and_is_end & 0x1);
5110 u32 mss = (mss_and_is_end >> 1);
5114 flags |= TXD_FLAG_END;
5115 if (flags & TXD_FLAG_VLAN) {
5116 vlan_tag = flags >> 16;
5119 vlan_tag |= (mss << TXD_MSS_SHIFT);
5121 txd->addr_hi = ((u64) mapping >> 32);
5122 txd->addr_lo = ((u64) mapping & 0xffffffff);
5123 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5124 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5127 /* hard_start_xmit for devices that don't have any bugs and
5128 * support TG3_FLG2_HW_TSO_2 only.
5130 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5132 struct tg3 *tp = netdev_priv(dev);
5133 u32 len, entry, base_flags, mss;
5134 struct skb_shared_info *sp;
5137 len = skb_headlen(skb);
5139 /* We are running in BH disabled context with netif_tx_lock
5140 * and TX reclaim runs via tp->napi.poll inside of a software
5141 * interrupt. Furthermore, IRQ processing runs lockless so we have
5142 * no IRQ context deadlocks to worry about either. Rejoice!
5144 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5145 if (!netif_queue_stopped(dev)) {
5146 netif_stop_queue(dev);
5148 /* This is a hard error, log it. */
5149 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5150 "queue awake!\n", dev->name);
5152 return NETDEV_TX_BUSY;
5155 entry = tp->tx_prod;
5158 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5159 int tcp_opt_len, ip_tcp_len;
5161 if (skb_header_cloned(skb) &&
5162 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5167 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5168 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5170 struct iphdr *iph = ip_hdr(skb);
5172 tcp_opt_len = tcp_optlen(skb);
5173 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5176 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5177 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5180 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5181 TXD_FLAG_CPU_POST_DMA);
5183 tcp_hdr(skb)->check = 0;
5186 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5187 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5188 #if TG3_VLAN_TAG_USED
5189 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5190 base_flags |= (TXD_FLAG_VLAN |
5191 (vlan_tx_tag_get(skb) << 16));
5194 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5199 sp = skb_shinfo(skb);
5201 mapping = sp->dma_head;
5203 tp->tx_buffers[entry].skb = skb;
5205 tg3_set_txd(tp, entry, mapping, len, base_flags,
5206 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5208 entry = NEXT_TX(entry);
5210 /* Now loop through additional data fragments, and queue them. */
5211 if (skb_shinfo(skb)->nr_frags > 0) {
5212 unsigned int i, last;
5214 last = skb_shinfo(skb)->nr_frags - 1;
5215 for (i = 0; i <= last; i++) {
5216 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5219 mapping = sp->dma_maps[i];
5220 tp->tx_buffers[entry].skb = NULL;
5222 tg3_set_txd(tp, entry, mapping, len,
5223 base_flags, (i == last) | (mss << 1));
5225 entry = NEXT_TX(entry);
5229 /* Packets are ready, update Tx producer idx local and on card. */
5230 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5232 tp->tx_prod = entry;
5233 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5234 netif_stop_queue(dev);
5235 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5236 netif_wake_queue(tp->dev);
5242 return NETDEV_TX_OK;
5245 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5247 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5248 * TSO header is greater than 80 bytes.
5250 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5252 struct sk_buff *segs, *nskb;
5254 /* Estimate the number of fragments in the worst case */
5255 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5256 netif_stop_queue(tp->dev);
5257 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5258 return NETDEV_TX_BUSY;
5260 netif_wake_queue(tp->dev);
5263 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5265 goto tg3_tso_bug_end;
5271 tg3_start_xmit_dma_bug(nskb, tp->dev);
5277 return NETDEV_TX_OK;
5280 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5281 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5283 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5285 struct tg3 *tp = netdev_priv(dev);
5286 u32 len, entry, base_flags, mss;
5287 struct skb_shared_info *sp;
5288 int would_hit_hwbug;
5291 len = skb_headlen(skb);
5293 /* We are running in BH disabled context with netif_tx_lock
5294 * and TX reclaim runs via tp->napi.poll inside of a software
5295 * interrupt. Furthermore, IRQ processing runs lockless so we have
5296 * no IRQ context deadlocks to worry about either. Rejoice!
5298 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5299 if (!netif_queue_stopped(dev)) {
5300 netif_stop_queue(dev);
5302 /* This is a hard error, log it. */
5303 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5304 "queue awake!\n", dev->name);
5306 return NETDEV_TX_BUSY;
5309 entry = tp->tx_prod;
5311 if (skb->ip_summed == CHECKSUM_PARTIAL)
5312 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5314 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5316 int tcp_opt_len, ip_tcp_len, hdr_len;
5318 if (skb_header_cloned(skb) &&
5319 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5324 tcp_opt_len = tcp_optlen(skb);
5325 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5327 hdr_len = ip_tcp_len + tcp_opt_len;
5328 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5329 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5330 return (tg3_tso_bug(tp, skb));
5332 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5333 TXD_FLAG_CPU_POST_DMA);
5337 iph->tot_len = htons(mss + hdr_len);
5338 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5339 tcp_hdr(skb)->check = 0;
5340 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5342 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5347 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5348 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5349 if (tcp_opt_len || iph->ihl > 5) {
5352 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5353 mss |= (tsflags << 11);
5356 if (tcp_opt_len || iph->ihl > 5) {
5359 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5360 base_flags |= tsflags << 12;
5364 #if TG3_VLAN_TAG_USED
5365 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5366 base_flags |= (TXD_FLAG_VLAN |
5367 (vlan_tx_tag_get(skb) << 16));
5370 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5375 sp = skb_shinfo(skb);
5377 mapping = sp->dma_head;
5379 tp->tx_buffers[entry].skb = skb;
5381 would_hit_hwbug = 0;
5383 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5384 would_hit_hwbug = 1;
5385 else if (tg3_4g_overflow_test(mapping, len))
5386 would_hit_hwbug = 1;
5388 tg3_set_txd(tp, entry, mapping, len, base_flags,
5389 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5391 entry = NEXT_TX(entry);
5393 /* Now loop through additional data fragments, and queue them. */
5394 if (skb_shinfo(skb)->nr_frags > 0) {
5395 unsigned int i, last;
5397 last = skb_shinfo(skb)->nr_frags - 1;
5398 for (i = 0; i <= last; i++) {
5399 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5402 mapping = sp->dma_maps[i];
5404 tp->tx_buffers[entry].skb = NULL;
5406 if (tg3_4g_overflow_test(mapping, len))
5407 would_hit_hwbug = 1;
5409 if (tg3_40bit_overflow_test(tp, mapping, len))
5410 would_hit_hwbug = 1;
5412 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5413 tg3_set_txd(tp, entry, mapping, len,
5414 base_flags, (i == last)|(mss << 1));
5416 tg3_set_txd(tp, entry, mapping, len,
5417 base_flags, (i == last));
5419 entry = NEXT_TX(entry);
5423 if (would_hit_hwbug) {
5424 u32 last_plus_one = entry;
5427 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5428 start &= (TG3_TX_RING_SIZE - 1);
5430 /* If the workaround fails due to memory/mapping
5431 * failure, silently drop this packet.
5433 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5434 &start, base_flags, mss))
5440 /* Packets are ready, update Tx producer idx local and on card. */
5441 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5443 tp->tx_prod = entry;
5444 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5445 netif_stop_queue(dev);
5446 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5447 netif_wake_queue(tp->dev);
5453 return NETDEV_TX_OK;
5456 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5461 if (new_mtu > ETH_DATA_LEN) {
5462 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5463 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5464 ethtool_op_set_tso(dev, 0);
5467 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5469 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5470 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5471 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5475 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5477 struct tg3 *tp = netdev_priv(dev);
5480 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5483 if (!netif_running(dev)) {
5484 /* We'll just catch it later when the
5487 tg3_set_mtu(dev, tp, new_mtu);
5495 tg3_full_lock(tp, 1);
5497 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5499 tg3_set_mtu(dev, tp, new_mtu);
5501 err = tg3_restart_hw(tp, 0);
5504 tg3_netif_start(tp);
5506 tg3_full_unlock(tp);
5514 /* Free up pending packets in all rx/tx rings.
5516 * The chip has been shut down and the driver detached from
5517 * the networking, so no interrupts or new tx packets will
5518 * end up in the driver. tp->{tx,}lock is not held and we are not
5519 * in an interrupt context and thus may sleep.
5521 static void tg3_free_rings(struct tg3 *tp)
5523 struct ring_info *rxp;
5526 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5527 rxp = &tp->rx_std_buffers[i];
5529 if (rxp->skb == NULL)
5531 pci_unmap_single(tp->pdev,
5532 pci_unmap_addr(rxp, mapping),
5533 tp->rx_pkt_buf_sz - tp->rx_offset,
5534 PCI_DMA_FROMDEVICE);
5535 dev_kfree_skb_any(rxp->skb);
5539 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5540 rxp = &tp->rx_jumbo_buffers[i];
5542 if (rxp->skb == NULL)
5544 pci_unmap_single(tp->pdev,
5545 pci_unmap_addr(rxp, mapping),
5546 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5547 PCI_DMA_FROMDEVICE);
5548 dev_kfree_skb_any(rxp->skb);
5552 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5553 struct tx_ring_info *txp;
5554 struct sk_buff *skb;
5556 txp = &tp->tx_buffers[i];
5564 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5568 i += skb_shinfo(skb)->nr_frags + 1;
5570 dev_kfree_skb_any(skb);
5574 /* Initialize tx/rx rings for packet processing.
5576 * The chip has been shut down and the driver detached from
5577 * the networking, so no interrupts or new tx packets will
5578 * end up in the driver. tp->{tx,}lock are held and thus
5581 static int tg3_init_rings(struct tg3 *tp)
5585 /* Free up all the SKBs. */
5588 /* Zero out all descriptors. */
5589 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5590 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5591 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5592 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5594 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5595 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5596 (tp->dev->mtu > ETH_DATA_LEN))
5597 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5599 /* Initialize invariants of the rings, we only set this
5600 * stuff once. This works because the card does not
5601 * write into the rx buffer posting rings.
5603 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5604 struct tg3_rx_buffer_desc *rxd;
5606 rxd = &tp->rx_std[i];
5607 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5609 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5610 rxd->opaque = (RXD_OPAQUE_RING_STD |
5611 (i << RXD_OPAQUE_INDEX_SHIFT));
5614 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5615 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5616 struct tg3_rx_buffer_desc *rxd;
5618 rxd = &tp->rx_jumbo[i];
5619 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5621 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5623 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5624 (i << RXD_OPAQUE_INDEX_SHIFT));
5628 /* Now allocate fresh SKBs for each rx ring. */
5629 for (i = 0; i < tp->rx_pending; i++) {
5630 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5631 printk(KERN_WARNING PFX
5632 "%s: Using a smaller RX standard ring, "
5633 "only %d out of %d buffers were allocated "
5635 tp->dev->name, i, tp->rx_pending);
5643 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5644 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5645 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5647 printk(KERN_WARNING PFX
5648 "%s: Using a smaller RX jumbo ring, "
5649 "only %d out of %d buffers were "
5650 "allocated successfully.\n",
5651 tp->dev->name, i, tp->rx_jumbo_pending);
5656 tp->rx_jumbo_pending = i;
5665 * Must not be invoked with interrupt sources disabled and
5666 * the hardware shutdown down.
5668 static void tg3_free_consistent(struct tg3 *tp)
5670 kfree(tp->rx_std_buffers);
5671 tp->rx_std_buffers = NULL;
5673 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5674 tp->rx_std, tp->rx_std_mapping);
5678 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5679 tp->rx_jumbo, tp->rx_jumbo_mapping);
5680 tp->rx_jumbo = NULL;
5683 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5684 tp->rx_rcb, tp->rx_rcb_mapping);
5688 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5689 tp->tx_ring, tp->tx_desc_mapping);
5692 if (tp->hw_status) {
5693 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5694 tp->hw_status, tp->status_mapping);
5695 tp->hw_status = NULL;
5698 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5699 tp->hw_stats, tp->stats_mapping);
5700 tp->hw_stats = NULL;
5705 * Must not be invoked with interrupt sources disabled and
5706 * the hardware shutdown down. Can sleep.
5708 static int tg3_alloc_consistent(struct tg3 *tp)
5710 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5712 TG3_RX_JUMBO_RING_SIZE)) +
5713 (sizeof(struct tx_ring_info) *
5716 if (!tp->rx_std_buffers)
5719 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5720 tp->tx_buffers = (struct tx_ring_info *)
5721 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5723 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5724 &tp->rx_std_mapping);
5728 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5729 &tp->rx_jumbo_mapping);
5734 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5735 &tp->rx_rcb_mapping);
5739 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5740 &tp->tx_desc_mapping);
5744 tp->hw_status = pci_alloc_consistent(tp->pdev,
5746 &tp->status_mapping);
5750 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5751 sizeof(struct tg3_hw_stats),
5752 &tp->stats_mapping);
5756 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5757 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5762 tg3_free_consistent(tp);
5766 #define MAX_WAIT_CNT 1000
5768 /* To stop a block, clear the enable bit and poll till it
5769 * clears. tp->lock is held.
5771 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5776 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5783 /* We can't enable/disable these bits of the
5784 * 5705/5750, just say success.
5797 for (i = 0; i < MAX_WAIT_CNT; i++) {
5800 if ((val & enable_bit) == 0)
5804 if (i == MAX_WAIT_CNT && !silent) {
5805 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5806 "ofs=%lx enable_bit=%x\n",
5814 /* tp->lock is held. */
5815 static int tg3_abort_hw(struct tg3 *tp, int silent)
5819 tg3_disable_ints(tp);
5821 tp->rx_mode &= ~RX_MODE_ENABLE;
5822 tw32_f(MAC_RX_MODE, tp->rx_mode);
5825 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5826 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5827 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5828 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5829 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5830 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5832 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5833 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5834 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5835 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5836 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5837 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5838 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5840 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5841 tw32_f(MAC_MODE, tp->mac_mode);
5844 tp->tx_mode &= ~TX_MODE_ENABLE;
5845 tw32_f(MAC_TX_MODE, tp->tx_mode);
5847 for (i = 0; i < MAX_WAIT_CNT; i++) {
5849 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5852 if (i >= MAX_WAIT_CNT) {
5853 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5854 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5855 tp->dev->name, tr32(MAC_TX_MODE));
5859 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5860 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5861 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5863 tw32(FTQ_RESET, 0xffffffff);
5864 tw32(FTQ_RESET, 0x00000000);
5866 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5867 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5870 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5872 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5877 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5882 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5883 if (apedata != APE_SEG_SIG_MAGIC)
5886 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5887 if (!(apedata & APE_FW_STATUS_READY))
5890 /* Wait for up to 1 millisecond for APE to service previous event. */
5891 for (i = 0; i < 10; i++) {
5892 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5895 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5897 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5898 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5899 event | APE_EVENT_STATUS_EVENT_PENDING);
5901 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5903 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5909 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5910 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5913 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5918 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5922 case RESET_KIND_INIT:
5923 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5924 APE_HOST_SEG_SIG_MAGIC);
5925 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5926 APE_HOST_SEG_LEN_MAGIC);
5927 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5928 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5929 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5930 APE_HOST_DRIVER_ID_MAGIC);
5931 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5932 APE_HOST_BEHAV_NO_PHYLOCK);
5934 event = APE_EVENT_STATUS_STATE_START;
5936 case RESET_KIND_SHUTDOWN:
5937 /* With the interface we are currently using,
5938 * APE does not track driver state. Wiping
5939 * out the HOST SEGMENT SIGNATURE forces
5940 * the APE to assume OS absent status.
5942 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5944 event = APE_EVENT_STATUS_STATE_UNLOAD;
5946 case RESET_KIND_SUSPEND:
5947 event = APE_EVENT_STATUS_STATE_SUSPEND;
5953 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5955 tg3_ape_send_event(tp, event);
5958 /* tp->lock is held. */
5959 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5961 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5962 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5964 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5966 case RESET_KIND_INIT:
5967 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5971 case RESET_KIND_SHUTDOWN:
5972 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5976 case RESET_KIND_SUSPEND:
5977 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5986 if (kind == RESET_KIND_INIT ||
5987 kind == RESET_KIND_SUSPEND)
5988 tg3_ape_driver_state_change(tp, kind);
5991 /* tp->lock is held. */
5992 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5994 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5996 case RESET_KIND_INIT:
5997 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5998 DRV_STATE_START_DONE);
6001 case RESET_KIND_SHUTDOWN:
6002 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6003 DRV_STATE_UNLOAD_DONE);
6011 if (kind == RESET_KIND_SHUTDOWN)
6012 tg3_ape_driver_state_change(tp, kind);
6015 /* tp->lock is held. */
6016 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6018 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6020 case RESET_KIND_INIT:
6021 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6025 case RESET_KIND_SHUTDOWN:
6026 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6030 case RESET_KIND_SUSPEND:
6031 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6041 static int tg3_poll_fw(struct tg3 *tp)
6046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6047 /* Wait up to 20ms for init done. */
6048 for (i = 0; i < 200; i++) {
6049 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6056 /* Wait for firmware initialization to complete. */
6057 for (i = 0; i < 100000; i++) {
6058 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6059 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6064 /* Chip might not be fitted with firmware. Some Sun onboard
6065 * parts are configured like that. So don't signal the timeout
6066 * of the above loop as an error, but do report the lack of
6067 * running firmware once.
6070 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6071 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6073 printk(KERN_INFO PFX "%s: No firmware running.\n",
6080 /* Save PCI command register before chip reset */
6081 static void tg3_save_pci_state(struct tg3 *tp)
6083 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6086 /* Restore PCI state after chip reset */
6087 static void tg3_restore_pci_state(struct tg3 *tp)
6091 /* Re-enable indirect register accesses. */
6092 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6093 tp->misc_host_ctrl);
6095 /* Set MAX PCI retry to zero. */
6096 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6097 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6098 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6099 val |= PCISTATE_RETRY_SAME_DMA;
6100 /* Allow reads and writes to the APE register and memory space. */
6101 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6102 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6103 PCISTATE_ALLOW_APE_SHMEM_WR;
6104 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6106 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6108 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6109 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6110 pcie_set_readrq(tp->pdev, 4096);
6112 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6113 tp->pci_cacheline_sz);
6114 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6119 /* Make sure PCI-X relaxed ordering bit is clear. */
6120 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6123 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6125 pcix_cmd &= ~PCI_X_CMD_ERO;
6126 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6130 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6132 /* Chip reset on 5780 will reset MSI enable bit,
6133 * so need to restore it.
6135 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6138 pci_read_config_word(tp->pdev,
6139 tp->msi_cap + PCI_MSI_FLAGS,
6141 pci_write_config_word(tp->pdev,
6142 tp->msi_cap + PCI_MSI_FLAGS,
6143 ctrl | PCI_MSI_FLAGS_ENABLE);
6144 val = tr32(MSGINT_MODE);
6145 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6150 static void tg3_stop_fw(struct tg3 *);
6152 /* tp->lock is held. */
6153 static int tg3_chip_reset(struct tg3 *tp)
6156 void (*write_op)(struct tg3 *, u32, u32);
6163 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6165 /* No matching tg3_nvram_unlock() after this because
6166 * chip reset below will undo the nvram lock.
6168 tp->nvram_lock_cnt = 0;
6170 /* GRC_MISC_CFG core clock reset will clear the memory
6171 * enable bit in PCI register 4 and the MSI enable bit
6172 * on some chips, so we save relevant registers here.
6174 tg3_save_pci_state(tp);
6176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6177 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6178 tw32(GRC_FASTBOOT_PC, 0);
6181 * We must avoid the readl() that normally takes place.
6182 * It locks machines, causes machine checks, and other
6183 * fun things. So, temporarily disable the 5701
6184 * hardware workaround, while we do the reset.
6186 write_op = tp->write32;
6187 if (write_op == tg3_write_flush_reg32)
6188 tp->write32 = tg3_write32;
6190 /* Prevent the irq handler from reading or writing PCI registers
6191 * during chip reset when the memory enable bit in the PCI command
6192 * register may be cleared. The chip does not generate interrupt
6193 * at this time, but the irq handler may still be called due to irq
6194 * sharing or irqpoll.
6196 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6197 if (tp->hw_status) {
6198 tp->hw_status->status = 0;
6199 tp->hw_status->status_tag = 0;
6202 tp->last_irq_tag = 0;
6204 synchronize_irq(tp->pdev->irq);
6206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6207 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6208 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6212 val = GRC_MISC_CFG_CORECLK_RESET;
6214 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6215 if (tr32(0x7e2c) == 0x60) {
6218 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6219 tw32(GRC_MISC_CFG, (1 << 29));
6224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6225 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6226 tw32(GRC_VCPU_EXT_CTRL,
6227 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6230 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6231 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6232 tw32(GRC_MISC_CFG, val);
6234 /* restore 5701 hardware bug workaround write method */
6235 tp->write32 = write_op;
6237 /* Unfortunately, we have to delay before the PCI read back.
6238 * Some 575X chips even will not respond to a PCI cfg access
6239 * when the reset command is given to the chip.
6241 * How do these hardware designers expect things to work
6242 * properly if the PCI write is posted for a long period
6243 * of time? It is always necessary to have some method by
6244 * which a register read back can occur to push the write
6245 * out which does the reset.
6247 * For most tg3 variants the trick below was working.
6252 /* Flush PCI posted writes. The normal MMIO registers
6253 * are inaccessible at this time so this is the only
6254 * way to make this reliably (actually, this is no longer
6255 * the case, see above). I tried to use indirect
6256 * register read/write but this upset some 5701 variants.
6258 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6262 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6265 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6269 /* Wait for link training to complete. */
6270 for (i = 0; i < 5000; i++)
6273 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6274 pci_write_config_dword(tp->pdev, 0xc4,
6275 cfg_val | (1 << 15));
6278 /* Clear the "no snoop" and "relaxed ordering" bits. */
6279 pci_read_config_word(tp->pdev,
6280 tp->pcie_cap + PCI_EXP_DEVCTL,
6282 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6283 PCI_EXP_DEVCTL_NOSNOOP_EN);
6285 * Older PCIe devices only support the 128 byte
6286 * MPS setting. Enforce the restriction.
6288 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6289 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6290 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6291 pci_write_config_word(tp->pdev,
6292 tp->pcie_cap + PCI_EXP_DEVCTL,
6295 pcie_set_readrq(tp->pdev, 4096);
6297 /* Clear error status */
6298 pci_write_config_word(tp->pdev,
6299 tp->pcie_cap + PCI_EXP_DEVSTA,
6300 PCI_EXP_DEVSTA_CED |
6301 PCI_EXP_DEVSTA_NFED |
6302 PCI_EXP_DEVSTA_FED |
6303 PCI_EXP_DEVSTA_URD);
6306 tg3_restore_pci_state(tp);
6308 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6311 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6312 val = tr32(MEMARB_MODE);
6313 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6315 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6317 tw32(0x5000, 0x400);
6320 tw32(GRC_MODE, tp->grc_mode);
6322 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6325 tw32(0xc4, val | (1 << 15));
6328 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6329 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6330 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6331 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6332 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6333 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6336 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6337 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6338 tw32_f(MAC_MODE, tp->mac_mode);
6339 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6340 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6341 tw32_f(MAC_MODE, tp->mac_mode);
6342 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6343 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6344 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6345 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6346 tw32_f(MAC_MODE, tp->mac_mode);
6348 tw32_f(MAC_MODE, 0);
6353 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6355 err = tg3_poll_fw(tp);
6359 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6360 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6363 tw32(0x7c00, val | (1 << 25));
6366 /* Reprobe ASF enable state. */
6367 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6368 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6369 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6370 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6373 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6374 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6375 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6376 tp->last_event_jiffies = jiffies;
6377 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6378 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6385 /* tp->lock is held. */
6386 static void tg3_stop_fw(struct tg3 *tp)
6388 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6389 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6390 /* Wait for RX cpu to ACK the previous event. */
6391 tg3_wait_for_event_ack(tp);
6393 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6395 tg3_generate_fw_event(tp);
6397 /* Wait for RX cpu to ACK this event. */
6398 tg3_wait_for_event_ack(tp);
6402 /* tp->lock is held. */
6403 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6409 tg3_write_sig_pre_reset(tp, kind);
6411 tg3_abort_hw(tp, silent);
6412 err = tg3_chip_reset(tp);
6414 __tg3_set_mac_addr(tp, 0);
6416 tg3_write_sig_legacy(tp, kind);
6417 tg3_write_sig_post_reset(tp, kind);
6425 #define RX_CPU_SCRATCH_BASE 0x30000
6426 #define RX_CPU_SCRATCH_SIZE 0x04000
6427 #define TX_CPU_SCRATCH_BASE 0x34000
6428 #define TX_CPU_SCRATCH_SIZE 0x04000
6430 /* tp->lock is held. */
6431 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6435 BUG_ON(offset == TX_CPU_BASE &&
6436 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6439 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6441 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6444 if (offset == RX_CPU_BASE) {
6445 for (i = 0; i < 10000; i++) {
6446 tw32(offset + CPU_STATE, 0xffffffff);
6447 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6448 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6452 tw32(offset + CPU_STATE, 0xffffffff);
6453 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6456 for (i = 0; i < 10000; i++) {
6457 tw32(offset + CPU_STATE, 0xffffffff);
6458 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6459 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6465 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6468 (offset == RX_CPU_BASE ? "RX" : "TX"));
6472 /* Clear firmware's nvram arbitration. */
6473 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6474 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6479 unsigned int fw_base;
6480 unsigned int fw_len;
6481 const __be32 *fw_data;
6484 /* tp->lock is held. */
6485 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6486 int cpu_scratch_size, struct fw_info *info)
6488 int err, lock_err, i;
6489 void (*write_op)(struct tg3 *, u32, u32);
6491 if (cpu_base == TX_CPU_BASE &&
6492 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6493 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6494 "TX cpu firmware on %s which is 5705.\n",
6499 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6500 write_op = tg3_write_mem;
6502 write_op = tg3_write_indirect_reg32;
6504 /* It is possible that bootcode is still loading at this point.
6505 * Get the nvram lock first before halting the cpu.
6507 lock_err = tg3_nvram_lock(tp);
6508 err = tg3_halt_cpu(tp, cpu_base);
6510 tg3_nvram_unlock(tp);
6514 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6515 write_op(tp, cpu_scratch_base + i, 0);
6516 tw32(cpu_base + CPU_STATE, 0xffffffff);
6517 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6518 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6519 write_op(tp, (cpu_scratch_base +
6520 (info->fw_base & 0xffff) +
6522 be32_to_cpu(info->fw_data[i]));
6530 /* tp->lock is held. */
6531 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6533 struct fw_info info;
6534 const __be32 *fw_data;
6537 fw_data = (void *)tp->fw->data;
6539 /* Firmware blob starts with version numbers, followed by
6540 start address and length. We are setting complete length.
6541 length = end_address_of_bss - start_address_of_text.
6542 Remainder is the blob to be loaded contiguously
6543 from start address. */
6545 info.fw_base = be32_to_cpu(fw_data[1]);
6546 info.fw_len = tp->fw->size - 12;
6547 info.fw_data = &fw_data[3];
6549 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6550 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6555 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6556 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6561 /* Now startup only the RX cpu. */
6562 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6563 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6565 for (i = 0; i < 5; i++) {
6566 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6568 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6569 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6570 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6574 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6575 "to set RX CPU PC, is %08x should be %08x\n",
6576 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6580 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6581 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6586 /* 5705 needs a special version of the TSO firmware. */
6588 /* tp->lock is held. */
6589 static int tg3_load_tso_firmware(struct tg3 *tp)
6591 struct fw_info info;
6592 const __be32 *fw_data;
6593 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6596 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6599 fw_data = (void *)tp->fw->data;
6601 /* Firmware blob starts with version numbers, followed by
6602 start address and length. We are setting complete length.
6603 length = end_address_of_bss - start_address_of_text.
6604 Remainder is the blob to be loaded contiguously
6605 from start address. */
6607 info.fw_base = be32_to_cpu(fw_data[1]);
6608 cpu_scratch_size = tp->fw_len;
6609 info.fw_len = tp->fw->size - 12;
6610 info.fw_data = &fw_data[3];
6612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6613 cpu_base = RX_CPU_BASE;
6614 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6616 cpu_base = TX_CPU_BASE;
6617 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6618 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6621 err = tg3_load_firmware_cpu(tp, cpu_base,
6622 cpu_scratch_base, cpu_scratch_size,
6627 /* Now startup the cpu. */
6628 tw32(cpu_base + CPU_STATE, 0xffffffff);
6629 tw32_f(cpu_base + CPU_PC, info.fw_base);
6631 for (i = 0; i < 5; i++) {
6632 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6634 tw32(cpu_base + CPU_STATE, 0xffffffff);
6635 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6636 tw32_f(cpu_base + CPU_PC, info.fw_base);
6640 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6641 "to set CPU PC, is %08x should be %08x\n",
6642 tp->dev->name, tr32(cpu_base + CPU_PC),
6646 tw32(cpu_base + CPU_STATE, 0xffffffff);
6647 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6652 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6654 struct tg3 *tp = netdev_priv(dev);
6655 struct sockaddr *addr = p;
6656 int err = 0, skip_mac_1 = 0;
6658 if (!is_valid_ether_addr(addr->sa_data))
6661 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6663 if (!netif_running(dev))
6666 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6667 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6669 addr0_high = tr32(MAC_ADDR_0_HIGH);
6670 addr0_low = tr32(MAC_ADDR_0_LOW);
6671 addr1_high = tr32(MAC_ADDR_1_HIGH);
6672 addr1_low = tr32(MAC_ADDR_1_LOW);
6674 /* Skip MAC addr 1 if ASF is using it. */
6675 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6676 !(addr1_high == 0 && addr1_low == 0))
6679 spin_lock_bh(&tp->lock);
6680 __tg3_set_mac_addr(tp, skip_mac_1);
6681 spin_unlock_bh(&tp->lock);
6686 /* tp->lock is held. */
6687 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6688 dma_addr_t mapping, u32 maxlen_flags,
6692 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6693 ((u64) mapping >> 32));
6695 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6696 ((u64) mapping & 0xffffffff));
6698 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6701 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6703 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6707 static void __tg3_set_rx_mode(struct net_device *);
6708 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6710 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6711 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6712 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6713 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6714 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6715 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6716 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6718 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6719 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6720 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6721 u32 val = ec->stats_block_coalesce_usecs;
6723 if (!netif_carrier_ok(tp->dev))
6726 tw32(HOSTCC_STAT_COAL_TICKS, val);
6730 /* tp->lock is held. */
6731 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6733 u32 val, rdmac_mode;
6736 tg3_disable_ints(tp);
6740 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6742 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6743 tg3_abort_hw(tp, 1);
6747 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6750 err = tg3_chip_reset(tp);
6754 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6756 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6757 val = tr32(TG3_CPMU_CTRL);
6758 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6759 tw32(TG3_CPMU_CTRL, val);
6761 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6762 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6763 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6764 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6766 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6767 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6768 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6769 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6771 val = tr32(TG3_CPMU_HST_ACC);
6772 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6773 val |= CPMU_HST_ACC_MACCLK_6_25;
6774 tw32(TG3_CPMU_HST_ACC, val);
6777 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6778 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6779 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6780 PCIE_PWR_MGMT_L1_THRESH_4MS;
6781 tw32(PCIE_PWR_MGMT_THRESH, val);
6783 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6784 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6786 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6789 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6790 val = tr32(TG3_PCIE_LNKCTL);
6791 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6792 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6794 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6795 tw32(TG3_PCIE_LNKCTL, val);
6798 /* This works around an issue with Athlon chipsets on
6799 * B3 tigon3 silicon. This bit has no effect on any
6800 * other revision. But do not set this on PCI Express
6801 * chips and don't even touch the clocks if the CPMU is present.
6803 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6804 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6805 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6806 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6809 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6810 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6811 val = tr32(TG3PCI_PCISTATE);
6812 val |= PCISTATE_RETRY_SAME_DMA;
6813 tw32(TG3PCI_PCISTATE, val);
6816 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6817 /* Allow reads and writes to the
6818 * APE register and memory space.
6820 val = tr32(TG3PCI_PCISTATE);
6821 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6822 PCISTATE_ALLOW_APE_SHMEM_WR;
6823 tw32(TG3PCI_PCISTATE, val);
6826 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6827 /* Enable some hw fixes. */
6828 val = tr32(TG3PCI_MSI_DATA);
6829 val |= (1 << 26) | (1 << 28) | (1 << 29);
6830 tw32(TG3PCI_MSI_DATA, val);
6833 /* Descriptor ring init may make accesses to the
6834 * NIC SRAM area to setup the TX descriptors, so we
6835 * can only do this after the hardware has been
6836 * successfully reset.
6838 err = tg3_init_rings(tp);
6842 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6843 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6844 /* This value is determined during the probe time DMA
6845 * engine test, tg3_test_dma.
6847 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6850 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6851 GRC_MODE_4X_NIC_SEND_RINGS |
6852 GRC_MODE_NO_TX_PHDR_CSUM |
6853 GRC_MODE_NO_RX_PHDR_CSUM);
6854 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6856 /* Pseudo-header checksum is done by hardware logic and not
6857 * the offload processers, so make the chip do the pseudo-
6858 * header checksums on receive. For transmit it is more
6859 * convenient to do the pseudo-header checksum in software
6860 * as Linux does that on transmit for us in all cases.
6862 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6866 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6868 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6869 val = tr32(GRC_MISC_CFG);
6871 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6872 tw32(GRC_MISC_CFG, val);
6874 /* Initialize MBUF/DESC pool. */
6875 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6877 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6878 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6880 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6882 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6883 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6884 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6886 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6889 fw_len = tp->fw_len;
6890 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6891 tw32(BUFMGR_MB_POOL_ADDR,
6892 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6893 tw32(BUFMGR_MB_POOL_SIZE,
6894 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6897 if (tp->dev->mtu <= ETH_DATA_LEN) {
6898 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6899 tp->bufmgr_config.mbuf_read_dma_low_water);
6900 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6901 tp->bufmgr_config.mbuf_mac_rx_low_water);
6902 tw32(BUFMGR_MB_HIGH_WATER,
6903 tp->bufmgr_config.mbuf_high_water);
6905 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6906 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6907 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6908 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6909 tw32(BUFMGR_MB_HIGH_WATER,
6910 tp->bufmgr_config.mbuf_high_water_jumbo);
6912 tw32(BUFMGR_DMA_LOW_WATER,
6913 tp->bufmgr_config.dma_low_water);
6914 tw32(BUFMGR_DMA_HIGH_WATER,
6915 tp->bufmgr_config.dma_high_water);
6917 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6918 for (i = 0; i < 2000; i++) {
6919 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6924 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6929 /* Setup replenish threshold. */
6930 val = tp->rx_pending / 8;
6933 else if (val > tp->rx_std_max_post)
6934 val = tp->rx_std_max_post;
6935 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6936 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6937 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6939 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6940 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6943 tw32(RCVBDI_STD_THRESH, val);
6945 /* Initialize TG3_BDINFO's at:
6946 * RCVDBDI_STD_BD: standard eth size rx ring
6947 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6948 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6951 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6952 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6953 * ring attribute flags
6954 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6956 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6957 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6959 * The size of each ring is fixed in the firmware, but the location is
6962 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6963 ((u64) tp->rx_std_mapping >> 32));
6964 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6965 ((u64) tp->rx_std_mapping & 0xffffffff));
6966 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6967 NIC_SRAM_RX_BUFFER_DESC);
6969 /* Don't even try to program the JUMBO/MINI buffer descriptor
6972 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6973 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6974 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6976 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6977 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6979 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6980 BDINFO_FLAGS_DISABLED);
6982 /* Setup replenish threshold. */
6983 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6985 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6986 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6987 ((u64) tp->rx_jumbo_mapping >> 32));
6988 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6989 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6990 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6991 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6992 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6993 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6995 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6996 BDINFO_FLAGS_DISABLED);
7001 /* There is only one send ring on 5705/5750, no need to explicitly
7002 * disable the others.
7004 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7005 /* Clear out send RCB ring in SRAM. */
7006 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7007 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7008 BDINFO_FLAGS_DISABLED);
7013 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7014 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7016 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7017 tp->tx_desc_mapping,
7018 (TG3_TX_RING_SIZE <<
7019 BDINFO_FLAGS_MAXLEN_SHIFT),
7020 NIC_SRAM_TX_BUFFER_DESC);
7022 /* There is only one receive return ring on 5705/5750, no need
7023 * to explicitly disable the others.
7025 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7026 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7027 i += TG3_BDINFO_SIZE) {
7028 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7029 BDINFO_FLAGS_DISABLED);
7034 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7036 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7038 (TG3_RX_RCB_RING_SIZE(tp) <<
7039 BDINFO_FLAGS_MAXLEN_SHIFT),
7042 tp->rx_std_ptr = tp->rx_pending;
7043 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7046 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7047 tp->rx_jumbo_pending : 0;
7048 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7051 /* Initialize MAC address and backoff seed. */
7052 __tg3_set_mac_addr(tp, 0);
7054 /* MTU + ethernet header + FCS + optional VLAN tag */
7055 tw32(MAC_RX_MTU_SIZE,
7056 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7058 /* The slot time is changed by tg3_setup_phy if we
7059 * run at gigabit with half duplex.
7061 tw32(MAC_TX_LENGTHS,
7062 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7063 (6 << TX_LENGTHS_IPG_SHIFT) |
7064 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7066 /* Receive rules. */
7067 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7068 tw32(RCVLPC_CONFIG, 0x0181);
7070 /* Calculate RDMAC_MODE setting early, we need it to determine
7071 * the RCVLPC_STATE_ENABLE mask.
7073 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7074 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7075 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7076 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7077 RDMAC_MODE_LNGREAD_ENAB);
7079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7082 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7083 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7084 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7086 /* If statement applies to 5705 and 5750 PCI devices only */
7087 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7088 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7089 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7090 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7092 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7093 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7094 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7095 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7099 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7100 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7102 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7103 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7107 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7109 /* Receive/send statistics. */
7110 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7111 val = tr32(RCVLPC_STATS_ENABLE);
7112 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7113 tw32(RCVLPC_STATS_ENABLE, val);
7114 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7115 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7116 val = tr32(RCVLPC_STATS_ENABLE);
7117 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7118 tw32(RCVLPC_STATS_ENABLE, val);
7120 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7122 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7123 tw32(SNDDATAI_STATSENAB, 0xffffff);
7124 tw32(SNDDATAI_STATSCTRL,
7125 (SNDDATAI_SCTRL_ENABLE |
7126 SNDDATAI_SCTRL_FASTUPD));
7128 /* Setup host coalescing engine. */
7129 tw32(HOSTCC_MODE, 0);
7130 for (i = 0; i < 2000; i++) {
7131 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7136 __tg3_set_coalesce(tp, &tp->coal);
7138 /* set status block DMA address */
7139 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7140 ((u64) tp->status_mapping >> 32));
7141 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7142 ((u64) tp->status_mapping & 0xffffffff));
7144 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7145 /* Status/statistics block address. See tg3_timer,
7146 * the tg3_periodic_fetch_stats call there, and
7147 * tg3_get_stats to see how this works for 5705/5750 chips.
7149 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7150 ((u64) tp->stats_mapping >> 32));
7151 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7152 ((u64) tp->stats_mapping & 0xffffffff));
7153 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7154 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7157 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7159 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7160 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7161 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7162 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7164 /* Clear statistics/status block in chip, and status block in ram. */
7165 for (i = NIC_SRAM_STATS_BLK;
7166 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7168 tg3_write_mem(tp, i, 0);
7171 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7173 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7174 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7175 /* reset to prevent losing 1st rx packet intermittently */
7176 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7180 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7181 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7184 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7185 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7186 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7187 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7188 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7189 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7190 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7193 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7194 * If TG3_FLG2_IS_NIC is zero, we should read the
7195 * register to preserve the GPIO settings for LOMs. The GPIOs,
7196 * whether used as inputs or outputs, are set by boot code after
7199 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7202 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7203 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7204 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7207 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7208 GRC_LCLCTRL_GPIO_OUTPUT3;
7210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7211 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7213 tp->grc_local_ctrl &= ~gpio_mask;
7214 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7216 /* GPIO1 must be driven high for eeprom write protect */
7217 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7218 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7219 GRC_LCLCTRL_GPIO_OUTPUT1);
7221 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7224 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7226 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7227 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7231 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7232 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7233 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7234 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7235 WDMAC_MODE_LNGREAD_ENAB);
7237 /* If statement applies to 5705 and 5750 PCI devices only */
7238 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7239 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7240 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7241 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7242 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7243 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7245 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7246 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7247 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7248 val |= WDMAC_MODE_RX_ACCEL;
7252 /* Enable host coalescing bug fix */
7253 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7254 val |= WDMAC_MODE_STATUS_TAG_FIX;
7256 tw32_f(WDMAC_MODE, val);
7259 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7262 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7265 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7266 pcix_cmd |= PCI_X_CMD_READ_2K;
7267 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7268 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7269 pcix_cmd |= PCI_X_CMD_READ_2K;
7271 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7275 tw32_f(RDMAC_MODE, rdmac_mode);
7278 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7279 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7280 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7284 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7286 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7288 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7289 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7290 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7291 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7292 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7293 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7294 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7295 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7297 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7298 err = tg3_load_5701_a0_firmware_fix(tp);
7303 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7304 err = tg3_load_tso_firmware(tp);
7309 tp->tx_mode = TX_MODE_ENABLE;
7310 tw32_f(MAC_TX_MODE, tp->tx_mode);
7313 tp->rx_mode = RX_MODE_ENABLE;
7314 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7315 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7317 tw32_f(MAC_RX_MODE, tp->rx_mode);
7320 tw32(MAC_LED_CTRL, tp->led_ctrl);
7322 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7323 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7324 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7327 tw32_f(MAC_RX_MODE, tp->rx_mode);
7330 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7331 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7332 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7333 /* Set drive transmission level to 1.2V */
7334 /* only if the signal pre-emphasis bit is not set */
7335 val = tr32(MAC_SERDES_CFG);
7338 tw32(MAC_SERDES_CFG, val);
7340 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7341 tw32(MAC_SERDES_CFG, 0x616000);
7344 /* Prevent chip from dropping frames when flow control
7347 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7350 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7351 /* Use hardware link auto-negotiation */
7352 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7355 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7359 tmp = tr32(SERDES_RX_CTRL);
7360 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7361 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7362 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7363 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7366 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7367 if (tp->link_config.phy_is_low_power) {
7368 tp->link_config.phy_is_low_power = 0;
7369 tp->link_config.speed = tp->link_config.orig_speed;
7370 tp->link_config.duplex = tp->link_config.orig_duplex;
7371 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7374 err = tg3_setup_phy(tp, 0);
7378 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7379 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7382 /* Clear CRC stats. */
7383 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7384 tg3_writephy(tp, MII_TG3_TEST1,
7385 tmp | MII_TG3_TEST1_CRC_EN);
7386 tg3_readphy(tp, 0x14, &tmp);
7391 __tg3_set_rx_mode(tp->dev);
7393 /* Initialize receive rules. */
7394 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7395 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7396 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7397 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7399 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7400 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7404 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7408 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7410 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7412 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7414 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7416 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7418 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7420 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7422 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7424 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7426 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7428 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7430 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7432 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7434 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7442 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7443 /* Write our heartbeat update interval to APE. */
7444 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7445 APE_HOST_HEARTBEAT_INT_DISABLE);
7447 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7452 /* Called at device open time to get the chip ready for
7453 * packet processing. Invoked with tp->lock held.
7455 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7457 tg3_switch_clocks(tp);
7459 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7461 return tg3_reset_hw(tp, reset_phy);
7464 #define TG3_STAT_ADD32(PSTAT, REG) \
7465 do { u32 __val = tr32(REG); \
7466 (PSTAT)->low += __val; \
7467 if ((PSTAT)->low < __val) \
7468 (PSTAT)->high += 1; \
7471 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7473 struct tg3_hw_stats *sp = tp->hw_stats;
7475 if (!netif_carrier_ok(tp->dev))
7478 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7479 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7480 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7481 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7482 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7483 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7484 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7485 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7486 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7487 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7488 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7489 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7490 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7492 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7493 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7494 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7495 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7496 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7497 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7498 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7499 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7500 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7501 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7502 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7503 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7504 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7505 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7507 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7508 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7509 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7512 static void tg3_timer(unsigned long __opaque)
7514 struct tg3 *tp = (struct tg3 *) __opaque;
7519 spin_lock(&tp->lock);
7521 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7522 /* All of this garbage is because when using non-tagged
7523 * IRQ status the mailbox/status_block protocol the chip
7524 * uses with the cpu is race prone.
7526 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7527 tw32(GRC_LOCAL_CTRL,
7528 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7530 tw32(HOSTCC_MODE, tp->coalesce_mode |
7531 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7534 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7535 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7536 spin_unlock(&tp->lock);
7537 schedule_work(&tp->reset_task);
7542 /* This part only runs once per second. */
7543 if (!--tp->timer_counter) {
7544 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7545 tg3_periodic_fetch_stats(tp);
7547 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7551 mac_stat = tr32(MAC_STATUS);
7554 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7555 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7557 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7561 tg3_setup_phy(tp, 0);
7562 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7563 u32 mac_stat = tr32(MAC_STATUS);
7566 if (netif_carrier_ok(tp->dev) &&
7567 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7570 if (! netif_carrier_ok(tp->dev) &&
7571 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7572 MAC_STATUS_SIGNAL_DET))) {
7576 if (!tp->serdes_counter) {
7579 ~MAC_MODE_PORT_MODE_MASK));
7581 tw32_f(MAC_MODE, tp->mac_mode);
7584 tg3_setup_phy(tp, 0);
7586 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7587 tg3_serdes_parallel_detect(tp);
7589 tp->timer_counter = tp->timer_multiplier;
7592 /* Heartbeat is only sent once every 2 seconds.
7594 * The heartbeat is to tell the ASF firmware that the host
7595 * driver is still alive. In the event that the OS crashes,
7596 * ASF needs to reset the hardware to free up the FIFO space
7597 * that may be filled with rx packets destined for the host.
7598 * If the FIFO is full, ASF will no longer function properly.
7600 * Unintended resets have been reported on real time kernels
7601 * where the timer doesn't run on time. Netpoll will also have
7604 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7605 * to check the ring condition when the heartbeat is expiring
7606 * before doing the reset. This will prevent most unintended
7609 if (!--tp->asf_counter) {
7610 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7611 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7612 tg3_wait_for_event_ack(tp);
7614 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7615 FWCMD_NICDRV_ALIVE3);
7616 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7617 /* 5 seconds timeout */
7618 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7620 tg3_generate_fw_event(tp);
7622 tp->asf_counter = tp->asf_multiplier;
7625 spin_unlock(&tp->lock);
7628 tp->timer.expires = jiffies + tp->timer_offset;
7629 add_timer(&tp->timer);
7632 static int tg3_request_irq(struct tg3 *tp)
7635 unsigned long flags;
7636 struct net_device *dev = tp->dev;
7638 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7642 flags = IRQF_SAMPLE_RANDOM;
7645 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7646 fn = tg3_interrupt_tagged;
7647 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7649 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7652 static int tg3_test_interrupt(struct tg3 *tp)
7654 struct net_device *dev = tp->dev;
7655 int err, i, intr_ok = 0;
7657 if (!netif_running(dev))
7660 tg3_disable_ints(tp);
7662 free_irq(tp->pdev->irq, dev);
7664 err = request_irq(tp->pdev->irq, tg3_test_isr,
7665 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7669 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7670 tg3_enable_ints(tp);
7672 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7675 for (i = 0; i < 5; i++) {
7676 u32 int_mbox, misc_host_ctrl;
7678 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7680 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7682 if ((int_mbox != 0) ||
7683 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7691 tg3_disable_ints(tp);
7693 free_irq(tp->pdev->irq, dev);
7695 err = tg3_request_irq(tp);
7706 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7707 * successfully restored
7709 static int tg3_test_msi(struct tg3 *tp)
7711 struct net_device *dev = tp->dev;
7715 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7718 /* Turn off SERR reporting in case MSI terminates with Master
7721 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7722 pci_write_config_word(tp->pdev, PCI_COMMAND,
7723 pci_cmd & ~PCI_COMMAND_SERR);
7725 err = tg3_test_interrupt(tp);
7727 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7732 /* other failures */
7736 /* MSI test failed, go back to INTx mode */
7737 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7738 "switching to INTx mode. Please report this failure to "
7739 "the PCI maintainer and include system chipset information.\n",
7742 free_irq(tp->pdev->irq, dev);
7743 pci_disable_msi(tp->pdev);
7745 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7747 err = tg3_request_irq(tp);
7751 /* Need to reset the chip because the MSI cycle may have terminated
7752 * with Master Abort.
7754 tg3_full_lock(tp, 1);
7756 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7757 err = tg3_init_hw(tp, 1);
7759 tg3_full_unlock(tp);
7762 free_irq(tp->pdev->irq, dev);
7767 static int tg3_request_firmware(struct tg3 *tp)
7769 const __be32 *fw_data;
7771 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7772 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7773 tp->dev->name, tp->fw_needed);
7777 fw_data = (void *)tp->fw->data;
7779 /* Firmware blob starts with version numbers, followed by
7780 * start address and _full_ length including BSS sections
7781 * (which must be longer than the actual data, of course
7784 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7785 if (tp->fw_len < (tp->fw->size - 12)) {
7786 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7787 tp->dev->name, tp->fw_len, tp->fw_needed);
7788 release_firmware(tp->fw);
7793 /* We no longer need firmware; we have it. */
7794 tp->fw_needed = NULL;
7798 static int tg3_open(struct net_device *dev)
7800 struct tg3 *tp = netdev_priv(dev);
7803 if (tp->fw_needed) {
7804 err = tg3_request_firmware(tp);
7805 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7809 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7811 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7812 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7813 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7815 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7819 netif_carrier_off(tp->dev);
7821 err = tg3_set_power_state(tp, PCI_D0);
7825 tg3_full_lock(tp, 0);
7827 tg3_disable_ints(tp);
7828 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7830 tg3_full_unlock(tp);
7832 /* The placement of this call is tied
7833 * to the setup and use of Host TX descriptors.
7835 err = tg3_alloc_consistent(tp);
7839 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7840 /* All MSI supporting chips should support tagged
7841 * status. Assert that this is the case.
7843 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7844 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7845 "Not using MSI.\n", tp->dev->name);
7846 } else if (pci_enable_msi(tp->pdev) == 0) {
7849 msi_mode = tr32(MSGINT_MODE);
7850 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7851 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7854 err = tg3_request_irq(tp);
7857 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7858 pci_disable_msi(tp->pdev);
7859 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7861 tg3_free_consistent(tp);
7865 napi_enable(&tp->napi);
7867 tg3_full_lock(tp, 0);
7869 err = tg3_init_hw(tp, 1);
7871 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7874 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7875 tp->timer_offset = HZ;
7877 tp->timer_offset = HZ / 10;
7879 BUG_ON(tp->timer_offset > HZ);
7880 tp->timer_counter = tp->timer_multiplier =
7881 (HZ / tp->timer_offset);
7882 tp->asf_counter = tp->asf_multiplier =
7883 ((HZ / tp->timer_offset) * 2);
7885 init_timer(&tp->timer);
7886 tp->timer.expires = jiffies + tp->timer_offset;
7887 tp->timer.data = (unsigned long) tp;
7888 tp->timer.function = tg3_timer;
7891 tg3_full_unlock(tp);
7894 napi_disable(&tp->napi);
7895 free_irq(tp->pdev->irq, dev);
7896 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7897 pci_disable_msi(tp->pdev);
7898 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7900 tg3_free_consistent(tp);
7904 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7905 err = tg3_test_msi(tp);
7908 tg3_full_lock(tp, 0);
7910 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7911 pci_disable_msi(tp->pdev);
7912 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7914 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7916 tg3_free_consistent(tp);
7918 tg3_full_unlock(tp);
7920 napi_disable(&tp->napi);
7925 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7926 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7927 u32 val = tr32(PCIE_TRANSACTION_CFG);
7929 tw32(PCIE_TRANSACTION_CFG,
7930 val | PCIE_TRANS_CFG_1SHOT_MSI);
7937 tg3_full_lock(tp, 0);
7939 add_timer(&tp->timer);
7940 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7941 tg3_enable_ints(tp);
7943 tg3_full_unlock(tp);
7945 netif_start_queue(dev);
7951 /*static*/ void tg3_dump_state(struct tg3 *tp)
7953 u32 val32, val32_2, val32_3, val32_4, val32_5;
7957 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7958 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7959 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7963 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7964 tr32(MAC_MODE), tr32(MAC_STATUS));
7965 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7966 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7967 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7968 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7969 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7970 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7972 /* Send data initiator control block */
7973 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7974 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7975 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7976 tr32(SNDDATAI_STATSCTRL));
7978 /* Send data completion control block */
7979 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7981 /* Send BD ring selector block */
7982 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7983 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7985 /* Send BD initiator control block */
7986 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7987 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7989 /* Send BD completion control block */
7990 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7992 /* Receive list placement control block */
7993 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7994 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7995 printk(" RCVLPC_STATSCTRL[%08x]\n",
7996 tr32(RCVLPC_STATSCTRL));
7998 /* Receive data and receive BD initiator control block */
7999 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8000 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8002 /* Receive data completion control block */
8003 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8006 /* Receive BD initiator control block */
8007 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8008 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8010 /* Receive BD completion control block */
8011 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8012 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8014 /* Receive list selector control block */
8015 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8016 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8018 /* Mbuf cluster free block */
8019 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8020 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8022 /* Host coalescing control block */
8023 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8024 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8025 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8026 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8027 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8028 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8029 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8030 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8031 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8032 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8033 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8034 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8036 /* Memory arbiter control block */
8037 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8038 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8040 /* Buffer manager control block */
8041 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8042 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8043 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8044 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8045 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8046 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8047 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8048 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8050 /* Read DMA control block */
8051 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8052 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8054 /* Write DMA control block */
8055 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8056 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8058 /* DMA completion block */
8059 printk("DEBUG: DMAC_MODE[%08x]\n",
8063 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8064 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8065 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8066 tr32(GRC_LOCAL_CTRL));
8069 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8070 tr32(RCVDBDI_JUMBO_BD + 0x0),
8071 tr32(RCVDBDI_JUMBO_BD + 0x4),
8072 tr32(RCVDBDI_JUMBO_BD + 0x8),
8073 tr32(RCVDBDI_JUMBO_BD + 0xc));
8074 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8075 tr32(RCVDBDI_STD_BD + 0x0),
8076 tr32(RCVDBDI_STD_BD + 0x4),
8077 tr32(RCVDBDI_STD_BD + 0x8),
8078 tr32(RCVDBDI_STD_BD + 0xc));
8079 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8080 tr32(RCVDBDI_MINI_BD + 0x0),
8081 tr32(RCVDBDI_MINI_BD + 0x4),
8082 tr32(RCVDBDI_MINI_BD + 0x8),
8083 tr32(RCVDBDI_MINI_BD + 0xc));
8085 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8086 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8087 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8088 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8089 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8090 val32, val32_2, val32_3, val32_4);
8092 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8093 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8094 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8095 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8096 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8097 val32, val32_2, val32_3, val32_4);
8099 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8100 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8101 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8102 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8103 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8104 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8105 val32, val32_2, val32_3, val32_4, val32_5);
8107 /* SW status block */
8108 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8109 tp->hw_status->status,
8110 tp->hw_status->status_tag,
8111 tp->hw_status->rx_jumbo_consumer,
8112 tp->hw_status->rx_consumer,
8113 tp->hw_status->rx_mini_consumer,
8114 tp->hw_status->idx[0].rx_producer,
8115 tp->hw_status->idx[0].tx_consumer);
8117 /* SW statistics block */
8118 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8119 ((u32 *)tp->hw_stats)[0],
8120 ((u32 *)tp->hw_stats)[1],
8121 ((u32 *)tp->hw_stats)[2],
8122 ((u32 *)tp->hw_stats)[3]);
8125 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8126 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8127 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8128 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8129 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8131 /* NIC side send descriptors. */
8132 for (i = 0; i < 6; i++) {
8135 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8136 + (i * sizeof(struct tg3_tx_buffer_desc));
8137 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8139 readl(txd + 0x0), readl(txd + 0x4),
8140 readl(txd + 0x8), readl(txd + 0xc));
8143 /* NIC side RX descriptors. */
8144 for (i = 0; i < 6; i++) {
8147 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8148 + (i * sizeof(struct tg3_rx_buffer_desc));
8149 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8151 readl(rxd + 0x0), readl(rxd + 0x4),
8152 readl(rxd + 0x8), readl(rxd + 0xc));
8153 rxd += (4 * sizeof(u32));
8154 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8156 readl(rxd + 0x0), readl(rxd + 0x4),
8157 readl(rxd + 0x8), readl(rxd + 0xc));
8160 for (i = 0; i < 6; i++) {
8163 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8164 + (i * sizeof(struct tg3_rx_buffer_desc));
8165 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8167 readl(rxd + 0x0), readl(rxd + 0x4),
8168 readl(rxd + 0x8), readl(rxd + 0xc));
8169 rxd += (4 * sizeof(u32));
8170 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8172 readl(rxd + 0x0), readl(rxd + 0x4),
8173 readl(rxd + 0x8), readl(rxd + 0xc));
8178 static struct net_device_stats *tg3_get_stats(struct net_device *);
8179 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8181 static int tg3_close(struct net_device *dev)
8183 struct tg3 *tp = netdev_priv(dev);
8185 napi_disable(&tp->napi);
8186 cancel_work_sync(&tp->reset_task);
8188 netif_stop_queue(dev);
8190 del_timer_sync(&tp->timer);
8192 tg3_full_lock(tp, 1);
8197 tg3_disable_ints(tp);
8199 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8201 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8203 tg3_full_unlock(tp);
8205 free_irq(tp->pdev->irq, dev);
8206 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8207 pci_disable_msi(tp->pdev);
8208 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8211 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8212 sizeof(tp->net_stats_prev));
8213 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8214 sizeof(tp->estats_prev));
8216 tg3_free_consistent(tp);
8218 tg3_set_power_state(tp, PCI_D3hot);
8220 netif_carrier_off(tp->dev);
8225 static inline unsigned long get_stat64(tg3_stat64_t *val)
8229 #if (BITS_PER_LONG == 32)
8232 ret = ((u64)val->high << 32) | ((u64)val->low);
8237 static inline u64 get_estat64(tg3_stat64_t *val)
8239 return ((u64)val->high << 32) | ((u64)val->low);
8242 static unsigned long calc_crc_errors(struct tg3 *tp)
8244 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8246 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8247 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8251 spin_lock_bh(&tp->lock);
8252 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8253 tg3_writephy(tp, MII_TG3_TEST1,
8254 val | MII_TG3_TEST1_CRC_EN);
8255 tg3_readphy(tp, 0x14, &val);
8258 spin_unlock_bh(&tp->lock);
8260 tp->phy_crc_errors += val;
8262 return tp->phy_crc_errors;
8265 return get_stat64(&hw_stats->rx_fcs_errors);
8268 #define ESTAT_ADD(member) \
8269 estats->member = old_estats->member + \
8270 get_estat64(&hw_stats->member)
8272 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8274 struct tg3_ethtool_stats *estats = &tp->estats;
8275 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8276 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8281 ESTAT_ADD(rx_octets);
8282 ESTAT_ADD(rx_fragments);
8283 ESTAT_ADD(rx_ucast_packets);
8284 ESTAT_ADD(rx_mcast_packets);
8285 ESTAT_ADD(rx_bcast_packets);
8286 ESTAT_ADD(rx_fcs_errors);
8287 ESTAT_ADD(rx_align_errors);
8288 ESTAT_ADD(rx_xon_pause_rcvd);
8289 ESTAT_ADD(rx_xoff_pause_rcvd);
8290 ESTAT_ADD(rx_mac_ctrl_rcvd);
8291 ESTAT_ADD(rx_xoff_entered);
8292 ESTAT_ADD(rx_frame_too_long_errors);
8293 ESTAT_ADD(rx_jabbers);
8294 ESTAT_ADD(rx_undersize_packets);
8295 ESTAT_ADD(rx_in_length_errors);
8296 ESTAT_ADD(rx_out_length_errors);
8297 ESTAT_ADD(rx_64_or_less_octet_packets);
8298 ESTAT_ADD(rx_65_to_127_octet_packets);
8299 ESTAT_ADD(rx_128_to_255_octet_packets);
8300 ESTAT_ADD(rx_256_to_511_octet_packets);
8301 ESTAT_ADD(rx_512_to_1023_octet_packets);
8302 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8303 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8304 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8305 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8306 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8308 ESTAT_ADD(tx_octets);
8309 ESTAT_ADD(tx_collisions);
8310 ESTAT_ADD(tx_xon_sent);
8311 ESTAT_ADD(tx_xoff_sent);
8312 ESTAT_ADD(tx_flow_control);
8313 ESTAT_ADD(tx_mac_errors);
8314 ESTAT_ADD(tx_single_collisions);
8315 ESTAT_ADD(tx_mult_collisions);
8316 ESTAT_ADD(tx_deferred);
8317 ESTAT_ADD(tx_excessive_collisions);
8318 ESTAT_ADD(tx_late_collisions);
8319 ESTAT_ADD(tx_collide_2times);
8320 ESTAT_ADD(tx_collide_3times);
8321 ESTAT_ADD(tx_collide_4times);
8322 ESTAT_ADD(tx_collide_5times);
8323 ESTAT_ADD(tx_collide_6times);
8324 ESTAT_ADD(tx_collide_7times);
8325 ESTAT_ADD(tx_collide_8times);
8326 ESTAT_ADD(tx_collide_9times);
8327 ESTAT_ADD(tx_collide_10times);
8328 ESTAT_ADD(tx_collide_11times);
8329 ESTAT_ADD(tx_collide_12times);
8330 ESTAT_ADD(tx_collide_13times);
8331 ESTAT_ADD(tx_collide_14times);
8332 ESTAT_ADD(tx_collide_15times);
8333 ESTAT_ADD(tx_ucast_packets);
8334 ESTAT_ADD(tx_mcast_packets);
8335 ESTAT_ADD(tx_bcast_packets);
8336 ESTAT_ADD(tx_carrier_sense_errors);
8337 ESTAT_ADD(tx_discards);
8338 ESTAT_ADD(tx_errors);
8340 ESTAT_ADD(dma_writeq_full);
8341 ESTAT_ADD(dma_write_prioq_full);
8342 ESTAT_ADD(rxbds_empty);
8343 ESTAT_ADD(rx_discards);
8344 ESTAT_ADD(rx_errors);
8345 ESTAT_ADD(rx_threshold_hit);
8347 ESTAT_ADD(dma_readq_full);
8348 ESTAT_ADD(dma_read_prioq_full);
8349 ESTAT_ADD(tx_comp_queue_full);
8351 ESTAT_ADD(ring_set_send_prod_index);
8352 ESTAT_ADD(ring_status_update);
8353 ESTAT_ADD(nic_irqs);
8354 ESTAT_ADD(nic_avoided_irqs);
8355 ESTAT_ADD(nic_tx_threshold_hit);
8360 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8362 struct tg3 *tp = netdev_priv(dev);
8363 struct net_device_stats *stats = &tp->net_stats;
8364 struct net_device_stats *old_stats = &tp->net_stats_prev;
8365 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8370 stats->rx_packets = old_stats->rx_packets +
8371 get_stat64(&hw_stats->rx_ucast_packets) +
8372 get_stat64(&hw_stats->rx_mcast_packets) +
8373 get_stat64(&hw_stats->rx_bcast_packets);
8375 stats->tx_packets = old_stats->tx_packets +
8376 get_stat64(&hw_stats->tx_ucast_packets) +
8377 get_stat64(&hw_stats->tx_mcast_packets) +
8378 get_stat64(&hw_stats->tx_bcast_packets);
8380 stats->rx_bytes = old_stats->rx_bytes +
8381 get_stat64(&hw_stats->rx_octets);
8382 stats->tx_bytes = old_stats->tx_bytes +
8383 get_stat64(&hw_stats->tx_octets);
8385 stats->rx_errors = old_stats->rx_errors +
8386 get_stat64(&hw_stats->rx_errors);
8387 stats->tx_errors = old_stats->tx_errors +
8388 get_stat64(&hw_stats->tx_errors) +
8389 get_stat64(&hw_stats->tx_mac_errors) +
8390 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8391 get_stat64(&hw_stats->tx_discards);
8393 stats->multicast = old_stats->multicast +
8394 get_stat64(&hw_stats->rx_mcast_packets);
8395 stats->collisions = old_stats->collisions +
8396 get_stat64(&hw_stats->tx_collisions);
8398 stats->rx_length_errors = old_stats->rx_length_errors +
8399 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8400 get_stat64(&hw_stats->rx_undersize_packets);
8402 stats->rx_over_errors = old_stats->rx_over_errors +
8403 get_stat64(&hw_stats->rxbds_empty);
8404 stats->rx_frame_errors = old_stats->rx_frame_errors +
8405 get_stat64(&hw_stats->rx_align_errors);
8406 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8407 get_stat64(&hw_stats->tx_discards);
8408 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8409 get_stat64(&hw_stats->tx_carrier_sense_errors);
8411 stats->rx_crc_errors = old_stats->rx_crc_errors +
8412 calc_crc_errors(tp);
8414 stats->rx_missed_errors = old_stats->rx_missed_errors +
8415 get_stat64(&hw_stats->rx_discards);
8420 static inline u32 calc_crc(unsigned char *buf, int len)
8428 for (j = 0; j < len; j++) {
8431 for (k = 0; k < 8; k++) {
8445 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8447 /* accept or reject all multicast frames */
8448 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8449 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8450 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8451 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8454 static void __tg3_set_rx_mode(struct net_device *dev)
8456 struct tg3 *tp = netdev_priv(dev);
8459 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8460 RX_MODE_KEEP_VLAN_TAG);
8462 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8465 #if TG3_VLAN_TAG_USED
8467 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8468 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8470 /* By definition, VLAN is disabled always in this
8473 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8474 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8477 if (dev->flags & IFF_PROMISC) {
8478 /* Promiscuous mode. */
8479 rx_mode |= RX_MODE_PROMISC;
8480 } else if (dev->flags & IFF_ALLMULTI) {
8481 /* Accept all multicast. */
8482 tg3_set_multi (tp, 1);
8483 } else if (dev->mc_count < 1) {
8484 /* Reject all multicast. */
8485 tg3_set_multi (tp, 0);
8487 /* Accept one or more multicast(s). */
8488 struct dev_mc_list *mclist;
8490 u32 mc_filter[4] = { 0, };
8495 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8496 i++, mclist = mclist->next) {
8498 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8500 regidx = (bit & 0x60) >> 5;
8502 mc_filter[regidx] |= (1 << bit);
8505 tw32(MAC_HASH_REG_0, mc_filter[0]);
8506 tw32(MAC_HASH_REG_1, mc_filter[1]);
8507 tw32(MAC_HASH_REG_2, mc_filter[2]);
8508 tw32(MAC_HASH_REG_3, mc_filter[3]);
8511 if (rx_mode != tp->rx_mode) {
8512 tp->rx_mode = rx_mode;
8513 tw32_f(MAC_RX_MODE, rx_mode);
8518 static void tg3_set_rx_mode(struct net_device *dev)
8520 struct tg3 *tp = netdev_priv(dev);
8522 if (!netif_running(dev))
8525 tg3_full_lock(tp, 0);
8526 __tg3_set_rx_mode(dev);
8527 tg3_full_unlock(tp);
8530 #define TG3_REGDUMP_LEN (32 * 1024)
8532 static int tg3_get_regs_len(struct net_device *dev)
8534 return TG3_REGDUMP_LEN;
8537 static void tg3_get_regs(struct net_device *dev,
8538 struct ethtool_regs *regs, void *_p)
8541 struct tg3 *tp = netdev_priv(dev);
8547 memset(p, 0, TG3_REGDUMP_LEN);
8549 if (tp->link_config.phy_is_low_power)
8552 tg3_full_lock(tp, 0);
8554 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8555 #define GET_REG32_LOOP(base,len) \
8556 do { p = (u32 *)(orig_p + (base)); \
8557 for (i = 0; i < len; i += 4) \
8558 __GET_REG32((base) + i); \
8560 #define GET_REG32_1(reg) \
8561 do { p = (u32 *)(orig_p + (reg)); \
8562 __GET_REG32((reg)); \
8565 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8566 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8567 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8568 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8569 GET_REG32_1(SNDDATAC_MODE);
8570 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8571 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8572 GET_REG32_1(SNDBDC_MODE);
8573 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8574 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8575 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8576 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8577 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8578 GET_REG32_1(RCVDCC_MODE);
8579 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8580 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8581 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8582 GET_REG32_1(MBFREE_MODE);
8583 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8584 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8585 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8586 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8587 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8588 GET_REG32_1(RX_CPU_MODE);
8589 GET_REG32_1(RX_CPU_STATE);
8590 GET_REG32_1(RX_CPU_PGMCTR);
8591 GET_REG32_1(RX_CPU_HWBKPT);
8592 GET_REG32_1(TX_CPU_MODE);
8593 GET_REG32_1(TX_CPU_STATE);
8594 GET_REG32_1(TX_CPU_PGMCTR);
8595 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8596 GET_REG32_LOOP(FTQ_RESET, 0x120);
8597 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8598 GET_REG32_1(DMAC_MODE);
8599 GET_REG32_LOOP(GRC_MODE, 0x4c);
8600 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8601 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8604 #undef GET_REG32_LOOP
8607 tg3_full_unlock(tp);
8610 static int tg3_get_eeprom_len(struct net_device *dev)
8612 struct tg3 *tp = netdev_priv(dev);
8614 return tp->nvram_size;
8617 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8619 struct tg3 *tp = netdev_priv(dev);
8622 u32 i, offset, len, b_offset, b_count;
8625 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8628 if (tp->link_config.phy_is_low_power)
8631 offset = eeprom->offset;
8635 eeprom->magic = TG3_EEPROM_MAGIC;
8638 /* adjustments to start on required 4 byte boundary */
8639 b_offset = offset & 3;
8640 b_count = 4 - b_offset;
8641 if (b_count > len) {
8642 /* i.e. offset=1 len=2 */
8645 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8648 memcpy(data, ((char*)&val) + b_offset, b_count);
8651 eeprom->len += b_count;
8654 /* read bytes upto the last 4 byte boundary */
8655 pd = &data[eeprom->len];
8656 for (i = 0; i < (len - (len & 3)); i += 4) {
8657 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8662 memcpy(pd + i, &val, 4);
8667 /* read last bytes not ending on 4 byte boundary */
8668 pd = &data[eeprom->len];
8670 b_offset = offset + len - b_count;
8671 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8674 memcpy(pd, &val, b_count);
8675 eeprom->len += b_count;
8680 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8682 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8684 struct tg3 *tp = netdev_priv(dev);
8686 u32 offset, len, b_offset, odd_len;
8690 if (tp->link_config.phy_is_low_power)
8693 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8694 eeprom->magic != TG3_EEPROM_MAGIC)
8697 offset = eeprom->offset;
8700 if ((b_offset = (offset & 3))) {
8701 /* adjustments to start on required 4 byte boundary */
8702 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8713 /* adjustments to end on required 4 byte boundary */
8715 len = (len + 3) & ~3;
8716 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8722 if (b_offset || odd_len) {
8723 buf = kmalloc(len, GFP_KERNEL);
8727 memcpy(buf, &start, 4);
8729 memcpy(buf+len-4, &end, 4);
8730 memcpy(buf + b_offset, data, eeprom->len);
8733 ret = tg3_nvram_write_block(tp, offset, len, buf);
8741 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8743 struct tg3 *tp = netdev_priv(dev);
8745 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8746 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8748 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8751 cmd->supported = (SUPPORTED_Autoneg);
8753 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8754 cmd->supported |= (SUPPORTED_1000baseT_Half |
8755 SUPPORTED_1000baseT_Full);
8757 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8758 cmd->supported |= (SUPPORTED_100baseT_Half |
8759 SUPPORTED_100baseT_Full |
8760 SUPPORTED_10baseT_Half |
8761 SUPPORTED_10baseT_Full |
8763 cmd->port = PORT_TP;
8765 cmd->supported |= SUPPORTED_FIBRE;
8766 cmd->port = PORT_FIBRE;
8769 cmd->advertising = tp->link_config.advertising;
8770 if (netif_running(dev)) {
8771 cmd->speed = tp->link_config.active_speed;
8772 cmd->duplex = tp->link_config.active_duplex;
8774 cmd->phy_address = PHY_ADDR;
8775 cmd->transceiver = XCVR_INTERNAL;
8776 cmd->autoneg = tp->link_config.autoneg;
8782 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8784 struct tg3 *tp = netdev_priv(dev);
8786 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8787 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8789 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8792 if (cmd->autoneg != AUTONEG_ENABLE &&
8793 cmd->autoneg != AUTONEG_DISABLE)
8796 if (cmd->autoneg == AUTONEG_DISABLE &&
8797 cmd->duplex != DUPLEX_FULL &&
8798 cmd->duplex != DUPLEX_HALF)
8801 if (cmd->autoneg == AUTONEG_ENABLE) {
8802 u32 mask = ADVERTISED_Autoneg |
8804 ADVERTISED_Asym_Pause;
8806 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8807 mask |= ADVERTISED_1000baseT_Half |
8808 ADVERTISED_1000baseT_Full;
8810 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8811 mask |= ADVERTISED_100baseT_Half |
8812 ADVERTISED_100baseT_Full |
8813 ADVERTISED_10baseT_Half |
8814 ADVERTISED_10baseT_Full |
8817 mask |= ADVERTISED_FIBRE;
8819 if (cmd->advertising & ~mask)
8822 mask &= (ADVERTISED_1000baseT_Half |
8823 ADVERTISED_1000baseT_Full |
8824 ADVERTISED_100baseT_Half |
8825 ADVERTISED_100baseT_Full |
8826 ADVERTISED_10baseT_Half |
8827 ADVERTISED_10baseT_Full);
8829 cmd->advertising &= mask;
8831 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8832 if (cmd->speed != SPEED_1000)
8835 if (cmd->duplex != DUPLEX_FULL)
8838 if (cmd->speed != SPEED_100 &&
8839 cmd->speed != SPEED_10)
8844 tg3_full_lock(tp, 0);
8846 tp->link_config.autoneg = cmd->autoneg;
8847 if (cmd->autoneg == AUTONEG_ENABLE) {
8848 tp->link_config.advertising = (cmd->advertising |
8849 ADVERTISED_Autoneg);
8850 tp->link_config.speed = SPEED_INVALID;
8851 tp->link_config.duplex = DUPLEX_INVALID;
8853 tp->link_config.advertising = 0;
8854 tp->link_config.speed = cmd->speed;
8855 tp->link_config.duplex = cmd->duplex;
8858 tp->link_config.orig_speed = tp->link_config.speed;
8859 tp->link_config.orig_duplex = tp->link_config.duplex;
8860 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8862 if (netif_running(dev))
8863 tg3_setup_phy(tp, 1);
8865 tg3_full_unlock(tp);
8870 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8872 struct tg3 *tp = netdev_priv(dev);
8874 strcpy(info->driver, DRV_MODULE_NAME);
8875 strcpy(info->version, DRV_MODULE_VERSION);
8876 strcpy(info->fw_version, tp->fw_ver);
8877 strcpy(info->bus_info, pci_name(tp->pdev));
8880 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8882 struct tg3 *tp = netdev_priv(dev);
8884 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8885 device_can_wakeup(&tp->pdev->dev))
8886 wol->supported = WAKE_MAGIC;
8890 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8891 device_can_wakeup(&tp->pdev->dev))
8892 wol->wolopts = WAKE_MAGIC;
8893 memset(&wol->sopass, 0, sizeof(wol->sopass));
8896 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8898 struct tg3 *tp = netdev_priv(dev);
8899 struct device *dp = &tp->pdev->dev;
8901 if (wol->wolopts & ~WAKE_MAGIC)
8903 if ((wol->wolopts & WAKE_MAGIC) &&
8904 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8907 spin_lock_bh(&tp->lock);
8908 if (wol->wolopts & WAKE_MAGIC) {
8909 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8910 device_set_wakeup_enable(dp, true);
8912 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8913 device_set_wakeup_enable(dp, false);
8915 spin_unlock_bh(&tp->lock);
8920 static u32 tg3_get_msglevel(struct net_device *dev)
8922 struct tg3 *tp = netdev_priv(dev);
8923 return tp->msg_enable;
8926 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8928 struct tg3 *tp = netdev_priv(dev);
8929 tp->msg_enable = value;
8932 static int tg3_set_tso(struct net_device *dev, u32 value)
8934 struct tg3 *tp = netdev_priv(dev);
8936 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8941 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8942 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8944 dev->features |= NETIF_F_TSO6;
8945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8946 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8947 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8950 dev->features |= NETIF_F_TSO_ECN;
8952 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8954 return ethtool_op_set_tso(dev, value);
8957 static int tg3_nway_reset(struct net_device *dev)
8959 struct tg3 *tp = netdev_priv(dev);
8962 if (!netif_running(dev))
8965 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8968 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8969 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8971 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8975 spin_lock_bh(&tp->lock);
8977 tg3_readphy(tp, MII_BMCR, &bmcr);
8978 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8979 ((bmcr & BMCR_ANENABLE) ||
8980 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8981 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8985 spin_unlock_bh(&tp->lock);
8991 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8993 struct tg3 *tp = netdev_priv(dev);
8995 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8996 ering->rx_mini_max_pending = 0;
8997 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8998 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9000 ering->rx_jumbo_max_pending = 0;
9002 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9004 ering->rx_pending = tp->rx_pending;
9005 ering->rx_mini_pending = 0;
9006 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9007 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9009 ering->rx_jumbo_pending = 0;
9011 ering->tx_pending = tp->tx_pending;
9014 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9016 struct tg3 *tp = netdev_priv(dev);
9017 int irq_sync = 0, err = 0;
9019 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9020 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9021 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9022 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9023 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9024 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9027 if (netif_running(dev)) {
9033 tg3_full_lock(tp, irq_sync);
9035 tp->rx_pending = ering->rx_pending;
9037 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9038 tp->rx_pending > 63)
9039 tp->rx_pending = 63;
9040 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9041 tp->tx_pending = ering->tx_pending;
9043 if (netif_running(dev)) {
9044 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9045 err = tg3_restart_hw(tp, 1);
9047 tg3_netif_start(tp);
9050 tg3_full_unlock(tp);
9052 if (irq_sync && !err)
9058 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9060 struct tg3 *tp = netdev_priv(dev);
9062 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9064 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9065 epause->rx_pause = 1;
9067 epause->rx_pause = 0;
9069 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9070 epause->tx_pause = 1;
9072 epause->tx_pause = 0;
9075 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9077 struct tg3 *tp = netdev_priv(dev);
9080 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9081 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9084 if (epause->autoneg) {
9086 struct phy_device *phydev;
9088 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9090 if (epause->rx_pause) {
9091 if (epause->tx_pause)
9092 newadv = ADVERTISED_Pause;
9094 newadv = ADVERTISED_Pause |
9095 ADVERTISED_Asym_Pause;
9096 } else if (epause->tx_pause) {
9097 newadv = ADVERTISED_Asym_Pause;
9101 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9102 u32 oldadv = phydev->advertising &
9104 ADVERTISED_Asym_Pause);
9105 if (oldadv != newadv) {
9106 phydev->advertising &=
9107 ~(ADVERTISED_Pause |
9108 ADVERTISED_Asym_Pause);
9109 phydev->advertising |= newadv;
9110 err = phy_start_aneg(phydev);
9113 tp->link_config.advertising &=
9114 ~(ADVERTISED_Pause |
9115 ADVERTISED_Asym_Pause);
9116 tp->link_config.advertising |= newadv;
9119 if (epause->rx_pause)
9120 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9122 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9124 if (epause->tx_pause)
9125 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9127 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9129 if (netif_running(dev))
9130 tg3_setup_flow_control(tp, 0, 0);
9135 if (netif_running(dev)) {
9140 tg3_full_lock(tp, irq_sync);
9142 if (epause->autoneg)
9143 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9145 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9146 if (epause->rx_pause)
9147 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9149 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9150 if (epause->tx_pause)
9151 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9153 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9155 if (netif_running(dev)) {
9156 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9157 err = tg3_restart_hw(tp, 1);
9159 tg3_netif_start(tp);
9162 tg3_full_unlock(tp);
9168 static u32 tg3_get_rx_csum(struct net_device *dev)
9170 struct tg3 *tp = netdev_priv(dev);
9171 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9174 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9176 struct tg3 *tp = netdev_priv(dev);
9178 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9184 spin_lock_bh(&tp->lock);
9186 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9188 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9189 spin_unlock_bh(&tp->lock);
9194 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9196 struct tg3 *tp = netdev_priv(dev);
9198 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9204 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9205 ethtool_op_set_tx_ipv6_csum(dev, data);
9207 ethtool_op_set_tx_csum(dev, data);
9212 static int tg3_get_sset_count (struct net_device *dev, int sset)
9216 return TG3_NUM_TEST;
9218 return TG3_NUM_STATS;
9224 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9226 switch (stringset) {
9228 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
9231 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
9234 WARN_ON(1); /* we need a WARN() */
9239 static int tg3_phys_id(struct net_device *dev, u32 data)
9241 struct tg3 *tp = netdev_priv(dev);
9244 if (!netif_running(tp->dev))
9248 data = UINT_MAX / 2;
9250 for (i = 0; i < (data * 2); i++) {
9252 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9253 LED_CTRL_1000MBPS_ON |
9254 LED_CTRL_100MBPS_ON |
9255 LED_CTRL_10MBPS_ON |
9256 LED_CTRL_TRAFFIC_OVERRIDE |
9257 LED_CTRL_TRAFFIC_BLINK |
9258 LED_CTRL_TRAFFIC_LED);
9261 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9262 LED_CTRL_TRAFFIC_OVERRIDE);
9264 if (msleep_interruptible(500))
9267 tw32(MAC_LED_CTRL, tp->led_ctrl);
9271 static void tg3_get_ethtool_stats (struct net_device *dev,
9272 struct ethtool_stats *estats, u64 *tmp_stats)
9274 struct tg3 *tp = netdev_priv(dev);
9275 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9278 #define NVRAM_TEST_SIZE 0x100
9279 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9280 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9281 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9282 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9283 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9285 static int tg3_test_nvram(struct tg3 *tp)
9289 int i, j, k, err = 0, size;
9291 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9294 if (tg3_nvram_read(tp, 0, &magic) != 0)
9297 if (magic == TG3_EEPROM_MAGIC)
9298 size = NVRAM_TEST_SIZE;
9299 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9300 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9301 TG3_EEPROM_SB_FORMAT_1) {
9302 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9303 case TG3_EEPROM_SB_REVISION_0:
9304 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9306 case TG3_EEPROM_SB_REVISION_2:
9307 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9309 case TG3_EEPROM_SB_REVISION_3:
9310 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9317 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9318 size = NVRAM_SELFBOOT_HW_SIZE;
9322 buf = kmalloc(size, GFP_KERNEL);
9327 for (i = 0, j = 0; i < size; i += 4, j++) {
9328 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9335 /* Selfboot format */
9336 magic = be32_to_cpu(buf[0]);
9337 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9338 TG3_EEPROM_MAGIC_FW) {
9339 u8 *buf8 = (u8 *) buf, csum8 = 0;
9341 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9342 TG3_EEPROM_SB_REVISION_2) {
9343 /* For rev 2, the csum doesn't include the MBA. */
9344 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9346 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9349 for (i = 0; i < size; i++)
9362 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9363 TG3_EEPROM_MAGIC_HW) {
9364 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9365 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9366 u8 *buf8 = (u8 *) buf;
9368 /* Separate the parity bits and the data bytes. */
9369 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9370 if ((i == 0) || (i == 8)) {
9374 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9375 parity[k++] = buf8[i] & msk;
9382 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9383 parity[k++] = buf8[i] & msk;
9386 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9387 parity[k++] = buf8[i] & msk;
9390 data[j++] = buf8[i];
9394 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9395 u8 hw8 = hweight8(data[i]);
9397 if ((hw8 & 0x1) && parity[i])
9399 else if (!(hw8 & 0x1) && !parity[i])
9406 /* Bootstrap checksum at offset 0x10 */
9407 csum = calc_crc((unsigned char *) buf, 0x10);
9408 if (csum != be32_to_cpu(buf[0x10/4]))
9411 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9412 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9413 if (csum != be32_to_cpu(buf[0xfc/4]))
9423 #define TG3_SERDES_TIMEOUT_SEC 2
9424 #define TG3_COPPER_TIMEOUT_SEC 6
9426 static int tg3_test_link(struct tg3 *tp)
9430 if (!netif_running(tp->dev))
9433 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9434 max = TG3_SERDES_TIMEOUT_SEC;
9436 max = TG3_COPPER_TIMEOUT_SEC;
9438 for (i = 0; i < max; i++) {
9439 if (netif_carrier_ok(tp->dev))
9442 if (msleep_interruptible(1000))
9449 /* Only test the commonly used registers */
9450 static int tg3_test_registers(struct tg3 *tp)
9452 int i, is_5705, is_5750;
9453 u32 offset, read_mask, write_mask, val, save_val, read_val;
9457 #define TG3_FL_5705 0x1
9458 #define TG3_FL_NOT_5705 0x2
9459 #define TG3_FL_NOT_5788 0x4
9460 #define TG3_FL_NOT_5750 0x8
9464 /* MAC Control Registers */
9465 { MAC_MODE, TG3_FL_NOT_5705,
9466 0x00000000, 0x00ef6f8c },
9467 { MAC_MODE, TG3_FL_5705,
9468 0x00000000, 0x01ef6b8c },
9469 { MAC_STATUS, TG3_FL_NOT_5705,
9470 0x03800107, 0x00000000 },
9471 { MAC_STATUS, TG3_FL_5705,
9472 0x03800100, 0x00000000 },
9473 { MAC_ADDR_0_HIGH, 0x0000,
9474 0x00000000, 0x0000ffff },
9475 { MAC_ADDR_0_LOW, 0x0000,
9476 0x00000000, 0xffffffff },
9477 { MAC_RX_MTU_SIZE, 0x0000,
9478 0x00000000, 0x0000ffff },
9479 { MAC_TX_MODE, 0x0000,
9480 0x00000000, 0x00000070 },
9481 { MAC_TX_LENGTHS, 0x0000,
9482 0x00000000, 0x00003fff },
9483 { MAC_RX_MODE, TG3_FL_NOT_5705,
9484 0x00000000, 0x000007fc },
9485 { MAC_RX_MODE, TG3_FL_5705,
9486 0x00000000, 0x000007dc },
9487 { MAC_HASH_REG_0, 0x0000,
9488 0x00000000, 0xffffffff },
9489 { MAC_HASH_REG_1, 0x0000,
9490 0x00000000, 0xffffffff },
9491 { MAC_HASH_REG_2, 0x0000,
9492 0x00000000, 0xffffffff },
9493 { MAC_HASH_REG_3, 0x0000,
9494 0x00000000, 0xffffffff },
9496 /* Receive Data and Receive BD Initiator Control Registers. */
9497 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9498 0x00000000, 0xffffffff },
9499 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9500 0x00000000, 0xffffffff },
9501 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9502 0x00000000, 0x00000003 },
9503 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9504 0x00000000, 0xffffffff },
9505 { RCVDBDI_STD_BD+0, 0x0000,
9506 0x00000000, 0xffffffff },
9507 { RCVDBDI_STD_BD+4, 0x0000,
9508 0x00000000, 0xffffffff },
9509 { RCVDBDI_STD_BD+8, 0x0000,
9510 0x00000000, 0xffff0002 },
9511 { RCVDBDI_STD_BD+0xc, 0x0000,
9512 0x00000000, 0xffffffff },
9514 /* Receive BD Initiator Control Registers. */
9515 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9516 0x00000000, 0xffffffff },
9517 { RCVBDI_STD_THRESH, TG3_FL_5705,
9518 0x00000000, 0x000003ff },
9519 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9520 0x00000000, 0xffffffff },
9522 /* Host Coalescing Control Registers. */
9523 { HOSTCC_MODE, TG3_FL_NOT_5705,
9524 0x00000000, 0x00000004 },
9525 { HOSTCC_MODE, TG3_FL_5705,
9526 0x00000000, 0x000000f6 },
9527 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9528 0x00000000, 0xffffffff },
9529 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9530 0x00000000, 0x000003ff },
9531 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9532 0x00000000, 0xffffffff },
9533 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9534 0x00000000, 0x000003ff },
9535 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9536 0x00000000, 0xffffffff },
9537 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9538 0x00000000, 0x000000ff },
9539 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9540 0x00000000, 0xffffffff },
9541 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9542 0x00000000, 0x000000ff },
9543 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9544 0x00000000, 0xffffffff },
9545 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9546 0x00000000, 0xffffffff },
9547 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9548 0x00000000, 0xffffffff },
9549 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9550 0x00000000, 0x000000ff },
9551 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9552 0x00000000, 0xffffffff },
9553 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9554 0x00000000, 0x000000ff },
9555 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9556 0x00000000, 0xffffffff },
9557 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9558 0x00000000, 0xffffffff },
9559 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9560 0x00000000, 0xffffffff },
9561 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9562 0x00000000, 0xffffffff },
9563 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9564 0x00000000, 0xffffffff },
9565 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9566 0xffffffff, 0x00000000 },
9567 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9568 0xffffffff, 0x00000000 },
9570 /* Buffer Manager Control Registers. */
9571 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9572 0x00000000, 0x007fff80 },
9573 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9574 0x00000000, 0x007fffff },
9575 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9576 0x00000000, 0x0000003f },
9577 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9578 0x00000000, 0x000001ff },
9579 { BUFMGR_MB_HIGH_WATER, 0x0000,
9580 0x00000000, 0x000001ff },
9581 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9582 0xffffffff, 0x00000000 },
9583 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9584 0xffffffff, 0x00000000 },
9586 /* Mailbox Registers */
9587 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9588 0x00000000, 0x000001ff },
9589 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9590 0x00000000, 0x000001ff },
9591 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9592 0x00000000, 0x000007ff },
9593 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9594 0x00000000, 0x000001ff },
9596 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9599 is_5705 = is_5750 = 0;
9600 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9602 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9606 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9607 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9610 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9613 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9614 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9617 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9620 offset = (u32) reg_tbl[i].offset;
9621 read_mask = reg_tbl[i].read_mask;
9622 write_mask = reg_tbl[i].write_mask;
9624 /* Save the original register content */
9625 save_val = tr32(offset);
9627 /* Determine the read-only value. */
9628 read_val = save_val & read_mask;
9630 /* Write zero to the register, then make sure the read-only bits
9631 * are not changed and the read/write bits are all zeros.
9637 /* Test the read-only and read/write bits. */
9638 if (((val & read_mask) != read_val) || (val & write_mask))
9641 /* Write ones to all the bits defined by RdMask and WrMask, then
9642 * make sure the read-only bits are not changed and the
9643 * read/write bits are all ones.
9645 tw32(offset, read_mask | write_mask);
9649 /* Test the read-only bits. */
9650 if ((val & read_mask) != read_val)
9653 /* Test the read/write bits. */
9654 if ((val & write_mask) != write_mask)
9657 tw32(offset, save_val);
9663 if (netif_msg_hw(tp))
9664 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9666 tw32(offset, save_val);
9670 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9672 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9676 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9677 for (j = 0; j < len; j += 4) {
9680 tg3_write_mem(tp, offset + j, test_pattern[i]);
9681 tg3_read_mem(tp, offset + j, &val);
9682 if (val != test_pattern[i])
9689 static int tg3_test_memory(struct tg3 *tp)
9691 static struct mem_entry {
9694 } mem_tbl_570x[] = {
9695 { 0x00000000, 0x00b50},
9696 { 0x00002000, 0x1c000},
9697 { 0xffffffff, 0x00000}
9698 }, mem_tbl_5705[] = {
9699 { 0x00000100, 0x0000c},
9700 { 0x00000200, 0x00008},
9701 { 0x00004000, 0x00800},
9702 { 0x00006000, 0x01000},
9703 { 0x00008000, 0x02000},
9704 { 0x00010000, 0x0e000},
9705 { 0xffffffff, 0x00000}
9706 }, mem_tbl_5755[] = {
9707 { 0x00000200, 0x00008},
9708 { 0x00004000, 0x00800},
9709 { 0x00006000, 0x00800},
9710 { 0x00008000, 0x02000},
9711 { 0x00010000, 0x0c000},
9712 { 0xffffffff, 0x00000}
9713 }, mem_tbl_5906[] = {
9714 { 0x00000200, 0x00008},
9715 { 0x00004000, 0x00400},
9716 { 0x00006000, 0x00400},
9717 { 0x00008000, 0x01000},
9718 { 0x00010000, 0x01000},
9719 { 0xffffffff, 0x00000}
9721 struct mem_entry *mem_tbl;
9725 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9726 mem_tbl = mem_tbl_5755;
9727 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9728 mem_tbl = mem_tbl_5906;
9729 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9730 mem_tbl = mem_tbl_5705;
9732 mem_tbl = mem_tbl_570x;
9734 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9735 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9736 mem_tbl[i].len)) != 0)
9743 #define TG3_MAC_LOOPBACK 0
9744 #define TG3_PHY_LOOPBACK 1
9746 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9748 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9750 struct sk_buff *skb, *rx_skb;
9753 int num_pkts, tx_len, rx_len, i, err;
9754 struct tg3_rx_buffer_desc *desc;
9756 if (loopback_mode == TG3_MAC_LOOPBACK) {
9757 /* HW errata - mac loopback fails in some cases on 5780.
9758 * Normal traffic and PHY loopback are not affected by
9761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9764 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9765 MAC_MODE_PORT_INT_LPBACK;
9766 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9767 mac_mode |= MAC_MODE_LINK_POLARITY;
9768 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9769 mac_mode |= MAC_MODE_PORT_MODE_MII;
9771 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9772 tw32(MAC_MODE, mac_mode);
9773 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9776 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9777 tg3_phy_fet_toggle_apd(tp, false);
9778 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9780 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9782 tg3_phy_toggle_automdix(tp, 0);
9784 tg3_writephy(tp, MII_BMCR, val);
9787 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9788 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9789 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9790 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9791 mac_mode |= MAC_MODE_PORT_MODE_MII;
9793 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9795 /* reset to prevent losing 1st rx packet intermittently */
9796 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9797 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9799 tw32_f(MAC_RX_MODE, tp->rx_mode);
9801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9802 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9803 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9804 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9805 mac_mode |= MAC_MODE_LINK_POLARITY;
9806 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9807 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9809 tw32(MAC_MODE, mac_mode);
9817 skb = netdev_alloc_skb(tp->dev, tx_len);
9821 tx_data = skb_put(skb, tx_len);
9822 memcpy(tx_data, tp->dev->dev_addr, 6);
9823 memset(tx_data + 6, 0x0, 8);
9825 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9827 for (i = 14; i < tx_len; i++)
9828 tx_data[i] = (u8) (i & 0xff);
9830 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9832 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9837 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9841 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9846 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9848 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9852 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9853 for (i = 0; i < 25; i++) {
9854 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9859 tx_idx = tp->hw_status->idx[0].tx_consumer;
9860 rx_idx = tp->hw_status->idx[0].rx_producer;
9861 if ((tx_idx == tp->tx_prod) &&
9862 (rx_idx == (rx_start_idx + num_pkts)))
9866 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9869 if (tx_idx != tp->tx_prod)
9872 if (rx_idx != rx_start_idx + num_pkts)
9875 desc = &tp->rx_rcb[rx_start_idx];
9876 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9877 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9878 if (opaque_key != RXD_OPAQUE_RING_STD)
9881 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9882 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9885 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9886 if (rx_len != tx_len)
9889 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9891 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9892 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9894 for (i = 14; i < tx_len; i++) {
9895 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9900 /* tg3_free_rings will unmap and free the rx_skb */
9905 #define TG3_MAC_LOOPBACK_FAILED 1
9906 #define TG3_PHY_LOOPBACK_FAILED 2
9907 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9908 TG3_PHY_LOOPBACK_FAILED)
9910 static int tg3_test_loopback(struct tg3 *tp)
9915 if (!netif_running(tp->dev))
9916 return TG3_LOOPBACK_FAILED;
9918 err = tg3_reset_hw(tp, 1);
9920 return TG3_LOOPBACK_FAILED;
9922 /* Turn off gphy autopowerdown. */
9923 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9924 tg3_phy_toggle_apd(tp, false);
9926 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9930 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9932 /* Wait for up to 40 microseconds to acquire lock. */
9933 for (i = 0; i < 4; i++) {
9934 status = tr32(TG3_CPMU_MUTEX_GNT);
9935 if (status == CPMU_MUTEX_GNT_DRIVER)
9940 if (status != CPMU_MUTEX_GNT_DRIVER)
9941 return TG3_LOOPBACK_FAILED;
9943 /* Turn off link-based power management. */
9944 cpmuctrl = tr32(TG3_CPMU_CTRL);
9946 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9947 CPMU_CTRL_LINK_AWARE_MODE));
9950 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9951 err |= TG3_MAC_LOOPBACK_FAILED;
9953 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9954 tw32(TG3_CPMU_CTRL, cpmuctrl);
9956 /* Release the mutex */
9957 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9960 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9961 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9962 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9963 err |= TG3_PHY_LOOPBACK_FAILED;
9966 /* Re-enable gphy autopowerdown. */
9967 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9968 tg3_phy_toggle_apd(tp, true);
9973 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9976 struct tg3 *tp = netdev_priv(dev);
9978 if (tp->link_config.phy_is_low_power)
9979 tg3_set_power_state(tp, PCI_D0);
9981 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9983 if (tg3_test_nvram(tp) != 0) {
9984 etest->flags |= ETH_TEST_FL_FAILED;
9987 if (tg3_test_link(tp) != 0) {
9988 etest->flags |= ETH_TEST_FL_FAILED;
9991 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9992 int err, err2 = 0, irq_sync = 0;
9994 if (netif_running(dev)) {
10000 tg3_full_lock(tp, irq_sync);
10002 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10003 err = tg3_nvram_lock(tp);
10004 tg3_halt_cpu(tp, RX_CPU_BASE);
10005 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10006 tg3_halt_cpu(tp, TX_CPU_BASE);
10008 tg3_nvram_unlock(tp);
10010 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10013 if (tg3_test_registers(tp) != 0) {
10014 etest->flags |= ETH_TEST_FL_FAILED;
10017 if (tg3_test_memory(tp) != 0) {
10018 etest->flags |= ETH_TEST_FL_FAILED;
10021 if ((data[4] = tg3_test_loopback(tp)) != 0)
10022 etest->flags |= ETH_TEST_FL_FAILED;
10024 tg3_full_unlock(tp);
10026 if (tg3_test_interrupt(tp) != 0) {
10027 etest->flags |= ETH_TEST_FL_FAILED;
10031 tg3_full_lock(tp, 0);
10033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10034 if (netif_running(dev)) {
10035 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10036 err2 = tg3_restart_hw(tp, 1);
10038 tg3_netif_start(tp);
10041 tg3_full_unlock(tp);
10043 if (irq_sync && !err2)
10046 if (tp->link_config.phy_is_low_power)
10047 tg3_set_power_state(tp, PCI_D3hot);
10051 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10053 struct mii_ioctl_data *data = if_mii(ifr);
10054 struct tg3 *tp = netdev_priv(dev);
10057 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10058 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10060 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10065 data->phy_id = PHY_ADDR;
10068 case SIOCGMIIREG: {
10071 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10072 break; /* We have no PHY */
10074 if (tp->link_config.phy_is_low_power)
10077 spin_lock_bh(&tp->lock);
10078 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10079 spin_unlock_bh(&tp->lock);
10081 data->val_out = mii_regval;
10087 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10088 break; /* We have no PHY */
10090 if (!capable(CAP_NET_ADMIN))
10093 if (tp->link_config.phy_is_low_power)
10096 spin_lock_bh(&tp->lock);
10097 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10098 spin_unlock_bh(&tp->lock);
10106 return -EOPNOTSUPP;
10109 #if TG3_VLAN_TAG_USED
10110 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10112 struct tg3 *tp = netdev_priv(dev);
10114 if (!netif_running(dev)) {
10119 tg3_netif_stop(tp);
10121 tg3_full_lock(tp, 0);
10125 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10126 __tg3_set_rx_mode(dev);
10128 tg3_netif_start(tp);
10130 tg3_full_unlock(tp);
10134 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10136 struct tg3 *tp = netdev_priv(dev);
10138 memcpy(ec, &tp->coal, sizeof(*ec));
10142 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10144 struct tg3 *tp = netdev_priv(dev);
10145 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10146 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10148 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10149 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10150 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10151 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10152 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10155 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10156 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10157 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10158 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10159 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10160 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10161 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10162 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10163 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10164 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10167 /* No rx interrupts will be generated if both are zero */
10168 if ((ec->rx_coalesce_usecs == 0) &&
10169 (ec->rx_max_coalesced_frames == 0))
10172 /* No tx interrupts will be generated if both are zero */
10173 if ((ec->tx_coalesce_usecs == 0) &&
10174 (ec->tx_max_coalesced_frames == 0))
10177 /* Only copy relevant parameters, ignore all others. */
10178 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10179 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10180 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10181 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10182 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10183 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10184 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10185 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10186 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10188 if (netif_running(dev)) {
10189 tg3_full_lock(tp, 0);
10190 __tg3_set_coalesce(tp, &tp->coal);
10191 tg3_full_unlock(tp);
10196 static const struct ethtool_ops tg3_ethtool_ops = {
10197 .get_settings = tg3_get_settings,
10198 .set_settings = tg3_set_settings,
10199 .get_drvinfo = tg3_get_drvinfo,
10200 .get_regs_len = tg3_get_regs_len,
10201 .get_regs = tg3_get_regs,
10202 .get_wol = tg3_get_wol,
10203 .set_wol = tg3_set_wol,
10204 .get_msglevel = tg3_get_msglevel,
10205 .set_msglevel = tg3_set_msglevel,
10206 .nway_reset = tg3_nway_reset,
10207 .get_link = ethtool_op_get_link,
10208 .get_eeprom_len = tg3_get_eeprom_len,
10209 .get_eeprom = tg3_get_eeprom,
10210 .set_eeprom = tg3_set_eeprom,
10211 .get_ringparam = tg3_get_ringparam,
10212 .set_ringparam = tg3_set_ringparam,
10213 .get_pauseparam = tg3_get_pauseparam,
10214 .set_pauseparam = tg3_set_pauseparam,
10215 .get_rx_csum = tg3_get_rx_csum,
10216 .set_rx_csum = tg3_set_rx_csum,
10217 .set_tx_csum = tg3_set_tx_csum,
10218 .set_sg = ethtool_op_set_sg,
10219 .set_tso = tg3_set_tso,
10220 .self_test = tg3_self_test,
10221 .get_strings = tg3_get_strings,
10222 .phys_id = tg3_phys_id,
10223 .get_ethtool_stats = tg3_get_ethtool_stats,
10224 .get_coalesce = tg3_get_coalesce,
10225 .set_coalesce = tg3_set_coalesce,
10226 .get_sset_count = tg3_get_sset_count,
10229 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10231 u32 cursize, val, magic;
10233 tp->nvram_size = EEPROM_CHIP_SIZE;
10235 if (tg3_nvram_read(tp, 0, &magic) != 0)
10238 if ((magic != TG3_EEPROM_MAGIC) &&
10239 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10240 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10244 * Size the chip by reading offsets at increasing powers of two.
10245 * When we encounter our validation signature, we know the addressing
10246 * has wrapped around, and thus have our chip size.
10250 while (cursize < tp->nvram_size) {
10251 if (tg3_nvram_read(tp, cursize, &val) != 0)
10260 tp->nvram_size = cursize;
10263 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10267 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10268 tg3_nvram_read(tp, 0, &val) != 0)
10271 /* Selfboot format */
10272 if (val != TG3_EEPROM_MAGIC) {
10273 tg3_get_eeprom_size(tp);
10277 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10279 /* This is confusing. We want to operate on the
10280 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10281 * call will read from NVRAM and byteswap the data
10282 * according to the byteswapping settings for all
10283 * other register accesses. This ensures the data we
10284 * want will always reside in the lower 16-bits.
10285 * However, the data in NVRAM is in LE format, which
10286 * means the data from the NVRAM read will always be
10287 * opposite the endianness of the CPU. The 16-bit
10288 * byteswap then brings the data to CPU endianness.
10290 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10294 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10297 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10301 nvcfg1 = tr32(NVRAM_CFG1);
10302 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10303 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10306 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10307 tw32(NVRAM_CFG1, nvcfg1);
10310 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10311 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10312 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10313 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10314 tp->nvram_jedecnum = JEDEC_ATMEL;
10315 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10316 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10318 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10319 tp->nvram_jedecnum = JEDEC_ATMEL;
10320 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10322 case FLASH_VENDOR_ATMEL_EEPROM:
10323 tp->nvram_jedecnum = JEDEC_ATMEL;
10324 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10325 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10327 case FLASH_VENDOR_ST:
10328 tp->nvram_jedecnum = JEDEC_ST;
10329 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10330 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10332 case FLASH_VENDOR_SAIFUN:
10333 tp->nvram_jedecnum = JEDEC_SAIFUN;
10334 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10336 case FLASH_VENDOR_SST_SMALL:
10337 case FLASH_VENDOR_SST_LARGE:
10338 tp->nvram_jedecnum = JEDEC_SST;
10339 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10344 tp->nvram_jedecnum = JEDEC_ATMEL;
10345 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10346 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10350 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10354 nvcfg1 = tr32(NVRAM_CFG1);
10356 /* NVRAM protection for TPM */
10357 if (nvcfg1 & (1 << 27))
10358 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10360 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10361 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10362 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10363 tp->nvram_jedecnum = JEDEC_ATMEL;
10364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10366 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10367 tp->nvram_jedecnum = JEDEC_ATMEL;
10368 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10369 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10371 case FLASH_5752VENDOR_ST_M45PE10:
10372 case FLASH_5752VENDOR_ST_M45PE20:
10373 case FLASH_5752VENDOR_ST_M45PE40:
10374 tp->nvram_jedecnum = JEDEC_ST;
10375 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10376 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10380 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10381 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10382 case FLASH_5752PAGE_SIZE_256:
10383 tp->nvram_pagesize = 256;
10385 case FLASH_5752PAGE_SIZE_512:
10386 tp->nvram_pagesize = 512;
10388 case FLASH_5752PAGE_SIZE_1K:
10389 tp->nvram_pagesize = 1024;
10391 case FLASH_5752PAGE_SIZE_2K:
10392 tp->nvram_pagesize = 2048;
10394 case FLASH_5752PAGE_SIZE_4K:
10395 tp->nvram_pagesize = 4096;
10397 case FLASH_5752PAGE_SIZE_264:
10398 tp->nvram_pagesize = 264;
10403 /* For eeprom, set pagesize to maximum eeprom size */
10404 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10406 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10407 tw32(NVRAM_CFG1, nvcfg1);
10411 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10413 u32 nvcfg1, protect = 0;
10415 nvcfg1 = tr32(NVRAM_CFG1);
10417 /* NVRAM protection for TPM */
10418 if (nvcfg1 & (1 << 27)) {
10419 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10423 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10425 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10426 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10427 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10428 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10429 tp->nvram_jedecnum = JEDEC_ATMEL;
10430 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10431 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10432 tp->nvram_pagesize = 264;
10433 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10434 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10435 tp->nvram_size = (protect ? 0x3e200 :
10436 TG3_NVRAM_SIZE_512KB);
10437 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10438 tp->nvram_size = (protect ? 0x1f200 :
10439 TG3_NVRAM_SIZE_256KB);
10441 tp->nvram_size = (protect ? 0x1f200 :
10442 TG3_NVRAM_SIZE_128KB);
10444 case FLASH_5752VENDOR_ST_M45PE10:
10445 case FLASH_5752VENDOR_ST_M45PE20:
10446 case FLASH_5752VENDOR_ST_M45PE40:
10447 tp->nvram_jedecnum = JEDEC_ST;
10448 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10449 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10450 tp->nvram_pagesize = 256;
10451 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10452 tp->nvram_size = (protect ?
10453 TG3_NVRAM_SIZE_64KB :
10454 TG3_NVRAM_SIZE_128KB);
10455 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10456 tp->nvram_size = (protect ?
10457 TG3_NVRAM_SIZE_64KB :
10458 TG3_NVRAM_SIZE_256KB);
10460 tp->nvram_size = (protect ?
10461 TG3_NVRAM_SIZE_128KB :
10462 TG3_NVRAM_SIZE_512KB);
10467 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10471 nvcfg1 = tr32(NVRAM_CFG1);
10473 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10474 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10475 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10476 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10477 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10478 tp->nvram_jedecnum = JEDEC_ATMEL;
10479 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10480 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10482 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10483 tw32(NVRAM_CFG1, nvcfg1);
10485 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10486 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10487 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10488 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10489 tp->nvram_jedecnum = JEDEC_ATMEL;
10490 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10491 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10492 tp->nvram_pagesize = 264;
10494 case FLASH_5752VENDOR_ST_M45PE10:
10495 case FLASH_5752VENDOR_ST_M45PE20:
10496 case FLASH_5752VENDOR_ST_M45PE40:
10497 tp->nvram_jedecnum = JEDEC_ST;
10498 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10499 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10500 tp->nvram_pagesize = 256;
10505 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10507 u32 nvcfg1, protect = 0;
10509 nvcfg1 = tr32(NVRAM_CFG1);
10511 /* NVRAM protection for TPM */
10512 if (nvcfg1 & (1 << 27)) {
10513 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10517 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10519 case FLASH_5761VENDOR_ATMEL_ADB021D:
10520 case FLASH_5761VENDOR_ATMEL_ADB041D:
10521 case FLASH_5761VENDOR_ATMEL_ADB081D:
10522 case FLASH_5761VENDOR_ATMEL_ADB161D:
10523 case FLASH_5761VENDOR_ATMEL_MDB021D:
10524 case FLASH_5761VENDOR_ATMEL_MDB041D:
10525 case FLASH_5761VENDOR_ATMEL_MDB081D:
10526 case FLASH_5761VENDOR_ATMEL_MDB161D:
10527 tp->nvram_jedecnum = JEDEC_ATMEL;
10528 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10529 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10530 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10531 tp->nvram_pagesize = 256;
10533 case FLASH_5761VENDOR_ST_A_M45PE20:
10534 case FLASH_5761VENDOR_ST_A_M45PE40:
10535 case FLASH_5761VENDOR_ST_A_M45PE80:
10536 case FLASH_5761VENDOR_ST_A_M45PE16:
10537 case FLASH_5761VENDOR_ST_M_M45PE20:
10538 case FLASH_5761VENDOR_ST_M_M45PE40:
10539 case FLASH_5761VENDOR_ST_M_M45PE80:
10540 case FLASH_5761VENDOR_ST_M_M45PE16:
10541 tp->nvram_jedecnum = JEDEC_ST;
10542 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10543 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10544 tp->nvram_pagesize = 256;
10549 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10552 case FLASH_5761VENDOR_ATMEL_ADB161D:
10553 case FLASH_5761VENDOR_ATMEL_MDB161D:
10554 case FLASH_5761VENDOR_ST_A_M45PE16:
10555 case FLASH_5761VENDOR_ST_M_M45PE16:
10556 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10558 case FLASH_5761VENDOR_ATMEL_ADB081D:
10559 case FLASH_5761VENDOR_ATMEL_MDB081D:
10560 case FLASH_5761VENDOR_ST_A_M45PE80:
10561 case FLASH_5761VENDOR_ST_M_M45PE80:
10562 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10564 case FLASH_5761VENDOR_ATMEL_ADB041D:
10565 case FLASH_5761VENDOR_ATMEL_MDB041D:
10566 case FLASH_5761VENDOR_ST_A_M45PE40:
10567 case FLASH_5761VENDOR_ST_M_M45PE40:
10568 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10570 case FLASH_5761VENDOR_ATMEL_ADB021D:
10571 case FLASH_5761VENDOR_ATMEL_MDB021D:
10572 case FLASH_5761VENDOR_ST_A_M45PE20:
10573 case FLASH_5761VENDOR_ST_M_M45PE20:
10574 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10580 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10582 tp->nvram_jedecnum = JEDEC_ATMEL;
10583 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10584 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10587 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10591 nvcfg1 = tr32(NVRAM_CFG1);
10593 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10594 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10595 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10596 tp->nvram_jedecnum = JEDEC_ATMEL;
10597 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10598 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10600 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10601 tw32(NVRAM_CFG1, nvcfg1);
10603 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10604 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10605 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10606 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10607 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10608 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10609 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10610 tp->nvram_jedecnum = JEDEC_ATMEL;
10611 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10612 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10614 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10615 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10616 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10617 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10618 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10620 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10621 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10622 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10624 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10625 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10626 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10630 case FLASH_5752VENDOR_ST_M45PE10:
10631 case FLASH_5752VENDOR_ST_M45PE20:
10632 case FLASH_5752VENDOR_ST_M45PE40:
10633 tp->nvram_jedecnum = JEDEC_ST;
10634 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10635 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10637 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10638 case FLASH_5752VENDOR_ST_M45PE10:
10639 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10641 case FLASH_5752VENDOR_ST_M45PE20:
10642 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10644 case FLASH_5752VENDOR_ST_M45PE40:
10645 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10650 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10654 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10655 case FLASH_5752PAGE_SIZE_256:
10656 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10657 tp->nvram_pagesize = 256;
10659 case FLASH_5752PAGE_SIZE_512:
10660 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10661 tp->nvram_pagesize = 512;
10663 case FLASH_5752PAGE_SIZE_1K:
10664 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10665 tp->nvram_pagesize = 1024;
10667 case FLASH_5752PAGE_SIZE_2K:
10668 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10669 tp->nvram_pagesize = 2048;
10671 case FLASH_5752PAGE_SIZE_4K:
10672 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10673 tp->nvram_pagesize = 4096;
10675 case FLASH_5752PAGE_SIZE_264:
10676 tp->nvram_pagesize = 264;
10678 case FLASH_5752PAGE_SIZE_528:
10679 tp->nvram_pagesize = 528;
10684 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10685 static void __devinit tg3_nvram_init(struct tg3 *tp)
10687 tw32_f(GRC_EEPROM_ADDR,
10688 (EEPROM_ADDR_FSM_RESET |
10689 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10690 EEPROM_ADDR_CLKPERD_SHIFT)));
10694 /* Enable seeprom accesses. */
10695 tw32_f(GRC_LOCAL_CTRL,
10696 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10699 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10700 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10701 tp->tg3_flags |= TG3_FLAG_NVRAM;
10703 if (tg3_nvram_lock(tp)) {
10704 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10705 "tg3_nvram_init failed.\n", tp->dev->name);
10708 tg3_enable_nvram_access(tp);
10710 tp->nvram_size = 0;
10712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10713 tg3_get_5752_nvram_info(tp);
10714 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10715 tg3_get_5755_nvram_info(tp);
10716 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10719 tg3_get_5787_nvram_info(tp);
10720 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10721 tg3_get_5761_nvram_info(tp);
10722 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10723 tg3_get_5906_nvram_info(tp);
10724 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10725 tg3_get_57780_nvram_info(tp);
10727 tg3_get_nvram_info(tp);
10729 if (tp->nvram_size == 0)
10730 tg3_get_nvram_size(tp);
10732 tg3_disable_nvram_access(tp);
10733 tg3_nvram_unlock(tp);
10736 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10738 tg3_get_eeprom_size(tp);
10742 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10743 u32 offset, u32 len, u8 *buf)
10748 for (i = 0; i < len; i += 4) {
10754 memcpy(&data, buf + i, 4);
10757 * The SEEPROM interface expects the data to always be opposite
10758 * the native endian format. We accomplish this by reversing
10759 * all the operations that would have been performed on the
10760 * data from a call to tg3_nvram_read_be32().
10762 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10764 val = tr32(GRC_EEPROM_ADDR);
10765 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10767 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10769 tw32(GRC_EEPROM_ADDR, val |
10770 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10771 (addr & EEPROM_ADDR_ADDR_MASK) |
10772 EEPROM_ADDR_START |
10773 EEPROM_ADDR_WRITE);
10775 for (j = 0; j < 1000; j++) {
10776 val = tr32(GRC_EEPROM_ADDR);
10778 if (val & EEPROM_ADDR_COMPLETE)
10782 if (!(val & EEPROM_ADDR_COMPLETE)) {
10791 /* offset and length are dword aligned */
10792 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10796 u32 pagesize = tp->nvram_pagesize;
10797 u32 pagemask = pagesize - 1;
10801 tmp = kmalloc(pagesize, GFP_KERNEL);
10807 u32 phy_addr, page_off, size;
10809 phy_addr = offset & ~pagemask;
10811 for (j = 0; j < pagesize; j += 4) {
10812 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10813 (__be32 *) (tmp + j));
10820 page_off = offset & pagemask;
10827 memcpy(tmp + page_off, buf, size);
10829 offset = offset + (pagesize - page_off);
10831 tg3_enable_nvram_access(tp);
10834 * Before we can erase the flash page, we need
10835 * to issue a special "write enable" command.
10837 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10839 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10842 /* Erase the target page */
10843 tw32(NVRAM_ADDR, phy_addr);
10845 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10846 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10848 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10851 /* Issue another write enable to start the write. */
10852 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10854 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10857 for (j = 0; j < pagesize; j += 4) {
10860 data = *((__be32 *) (tmp + j));
10862 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10864 tw32(NVRAM_ADDR, phy_addr + j);
10866 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10870 nvram_cmd |= NVRAM_CMD_FIRST;
10871 else if (j == (pagesize - 4))
10872 nvram_cmd |= NVRAM_CMD_LAST;
10874 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10881 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10882 tg3_nvram_exec_cmd(tp, nvram_cmd);
10889 /* offset and length are dword aligned */
10890 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10895 for (i = 0; i < len; i += 4, offset += 4) {
10896 u32 page_off, phy_addr, nvram_cmd;
10899 memcpy(&data, buf + i, 4);
10900 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10902 page_off = offset % tp->nvram_pagesize;
10904 phy_addr = tg3_nvram_phys_addr(tp, offset);
10906 tw32(NVRAM_ADDR, phy_addr);
10908 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10910 if ((page_off == 0) || (i == 0))
10911 nvram_cmd |= NVRAM_CMD_FIRST;
10912 if (page_off == (tp->nvram_pagesize - 4))
10913 nvram_cmd |= NVRAM_CMD_LAST;
10915 if (i == (len - 4))
10916 nvram_cmd |= NVRAM_CMD_LAST;
10918 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10919 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10920 (tp->nvram_jedecnum == JEDEC_ST) &&
10921 (nvram_cmd & NVRAM_CMD_FIRST)) {
10923 if ((ret = tg3_nvram_exec_cmd(tp,
10924 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10929 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10930 /* We always do complete word writes to eeprom. */
10931 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10934 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10940 /* offset and length are dword aligned */
10941 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10945 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10946 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10947 ~GRC_LCLCTRL_GPIO_OUTPUT1);
10951 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10952 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10957 ret = tg3_nvram_lock(tp);
10961 tg3_enable_nvram_access(tp);
10962 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10963 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10964 tw32(NVRAM_WRITE1, 0x406);
10966 grc_mode = tr32(GRC_MODE);
10967 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10969 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10970 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10972 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10976 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10980 grc_mode = tr32(GRC_MODE);
10981 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10983 tg3_disable_nvram_access(tp);
10984 tg3_nvram_unlock(tp);
10987 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10988 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10995 struct subsys_tbl_ent {
10996 u16 subsys_vendor, subsys_devid;
11000 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11001 /* Broadcom boards. */
11002 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11003 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11004 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11005 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11006 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11007 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11008 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11009 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11010 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11011 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11012 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11015 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11016 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11017 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11018 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11019 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11022 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11023 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11024 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11025 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11027 /* Compaq boards. */
11028 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11029 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11030 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11031 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11032 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11035 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11038 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11042 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11043 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11044 tp->pdev->subsystem_vendor) &&
11045 (subsys_id_to_phy_id[i].subsys_devid ==
11046 tp->pdev->subsystem_device))
11047 return &subsys_id_to_phy_id[i];
11052 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11057 /* On some early chips the SRAM cannot be accessed in D3hot state,
11058 * so need make sure we're in D0.
11060 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11061 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11062 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11065 /* Make sure register accesses (indirect or otherwise)
11066 * will function correctly.
11068 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11069 tp->misc_host_ctrl);
11071 /* The memory arbiter has to be enabled in order for SRAM accesses
11072 * to succeed. Normally on powerup the tg3 chip firmware will make
11073 * sure it is enabled, but other entities such as system netboot
11074 * code might disable it.
11076 val = tr32(MEMARB_MODE);
11077 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11079 tp->phy_id = PHY_ID_INVALID;
11080 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11082 /* Assume an onboard device and WOL capable by default. */
11083 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11086 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11087 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11088 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11090 val = tr32(VCPU_CFGSHDW);
11091 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11092 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11093 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11094 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11095 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11099 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11100 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11101 u32 nic_cfg, led_cfg;
11102 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11103 int eeprom_phy_serdes = 0;
11105 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11106 tp->nic_sram_data_cfg = nic_cfg;
11108 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11109 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11110 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11111 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11112 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11113 (ver > 0) && (ver < 0x100))
11114 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11117 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11119 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11120 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11121 eeprom_phy_serdes = 1;
11123 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11124 if (nic_phy_id != 0) {
11125 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11126 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11128 eeprom_phy_id = (id1 >> 16) << 10;
11129 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11130 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11134 tp->phy_id = eeprom_phy_id;
11135 if (eeprom_phy_serdes) {
11136 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11137 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11139 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11142 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11143 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11144 SHASTA_EXT_LED_MODE_MASK);
11146 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11150 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11151 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11154 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11155 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11158 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11159 tp->led_ctrl = LED_CTRL_MODE_MAC;
11161 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11162 * read on some older 5700/5701 bootcode.
11164 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11166 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11168 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11172 case SHASTA_EXT_LED_SHARED:
11173 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11174 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11175 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11176 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11177 LED_CTRL_MODE_PHY_2);
11180 case SHASTA_EXT_LED_MAC:
11181 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11184 case SHASTA_EXT_LED_COMBO:
11185 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11186 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11187 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11188 LED_CTRL_MODE_PHY_2);
11193 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11195 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11196 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11198 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11199 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11201 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11202 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11203 if ((tp->pdev->subsystem_vendor ==
11204 PCI_VENDOR_ID_ARIMA) &&
11205 (tp->pdev->subsystem_device == 0x205a ||
11206 tp->pdev->subsystem_device == 0x2063))
11207 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11209 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11210 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11213 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11214 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11215 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11216 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11219 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11220 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11221 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11223 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11224 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11225 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11227 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11228 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11229 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11231 if (cfg2 & (1 << 17))
11232 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11234 /* serdes signal pre-emphasis in register 0x590 set by */
11235 /* bootcode if bit 18 is set */
11236 if (cfg2 & (1 << 18))
11237 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11239 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11240 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11241 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11242 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11244 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11247 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11248 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11249 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11252 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11253 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11254 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11255 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11256 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11257 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11260 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11261 device_set_wakeup_enable(&tp->pdev->dev,
11262 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11265 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11270 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11271 tw32(OTP_CTRL, cmd);
11273 /* Wait for up to 1 ms for command to execute. */
11274 for (i = 0; i < 100; i++) {
11275 val = tr32(OTP_STATUS);
11276 if (val & OTP_STATUS_CMD_DONE)
11281 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11284 /* Read the gphy configuration from the OTP region of the chip. The gphy
11285 * configuration is a 32-bit value that straddles the alignment boundary.
11286 * We do two 32-bit reads and then shift and merge the results.
11288 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11290 u32 bhalf_otp, thalf_otp;
11292 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11294 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11297 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11299 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11302 thalf_otp = tr32(OTP_READ_DATA);
11304 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11306 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11309 bhalf_otp = tr32(OTP_READ_DATA);
11311 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11314 static int __devinit tg3_phy_probe(struct tg3 *tp)
11316 u32 hw_phy_id_1, hw_phy_id_2;
11317 u32 hw_phy_id, hw_phy_id_masked;
11320 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11321 return tg3_phy_init(tp);
11323 /* Reading the PHY ID register can conflict with ASF
11324 * firmware access to the PHY hardware.
11327 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11328 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11329 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11331 /* Now read the physical PHY_ID from the chip and verify
11332 * that it is sane. If it doesn't look good, we fall back
11333 * to either the hard-coded table based PHY_ID and failing
11334 * that the value found in the eeprom area.
11336 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11337 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11339 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11340 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11341 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11343 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11346 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11347 tp->phy_id = hw_phy_id;
11348 if (hw_phy_id_masked == PHY_ID_BCM8002)
11349 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11351 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11353 if (tp->phy_id != PHY_ID_INVALID) {
11354 /* Do nothing, phy ID already set up in
11355 * tg3_get_eeprom_hw_cfg().
11358 struct subsys_tbl_ent *p;
11360 /* No eeprom signature? Try the hardcoded
11361 * subsys device table.
11363 p = lookup_by_subsys(tp);
11367 tp->phy_id = p->phy_id;
11369 tp->phy_id == PHY_ID_BCM8002)
11370 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11374 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11375 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11376 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11377 u32 bmsr, adv_reg, tg3_ctrl, mask;
11379 tg3_readphy(tp, MII_BMSR, &bmsr);
11380 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11381 (bmsr & BMSR_LSTATUS))
11382 goto skip_phy_reset;
11384 err = tg3_phy_reset(tp);
11388 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11389 ADVERTISE_100HALF | ADVERTISE_100FULL |
11390 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11392 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11393 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11394 MII_TG3_CTRL_ADV_1000_FULL);
11395 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11396 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11397 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11398 MII_TG3_CTRL_ENABLE_AS_MASTER);
11401 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11402 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11403 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11404 if (!tg3_copper_is_advertising_all(tp, mask)) {
11405 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11407 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11408 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11410 tg3_writephy(tp, MII_BMCR,
11411 BMCR_ANENABLE | BMCR_ANRESTART);
11413 tg3_phy_set_wirespeed(tp);
11415 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11416 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11417 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11421 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11422 err = tg3_init_5401phy_dsp(tp);
11427 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11428 err = tg3_init_5401phy_dsp(tp);
11431 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11432 tp->link_config.advertising =
11433 (ADVERTISED_1000baseT_Half |
11434 ADVERTISED_1000baseT_Full |
11435 ADVERTISED_Autoneg |
11437 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11438 tp->link_config.advertising &=
11439 ~(ADVERTISED_1000baseT_Half |
11440 ADVERTISED_1000baseT_Full);
11445 static void __devinit tg3_read_partno(struct tg3 *tp)
11447 unsigned char vpd_data[256]; /* in little-endian format */
11451 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11452 tg3_nvram_read(tp, 0x0, &magic))
11453 goto out_not_found;
11455 if (magic == TG3_EEPROM_MAGIC) {
11456 for (i = 0; i < 256; i += 4) {
11459 /* The data is in little-endian format in NVRAM.
11460 * Use the big-endian read routines to preserve
11461 * the byte order as it exists in NVRAM.
11463 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11464 goto out_not_found;
11466 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11471 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11472 for (i = 0; i < 256; i += 4) {
11477 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11479 while (j++ < 100) {
11480 pci_read_config_word(tp->pdev, vpd_cap +
11481 PCI_VPD_ADDR, &tmp16);
11482 if (tmp16 & 0x8000)
11486 if (!(tmp16 & 0x8000))
11487 goto out_not_found;
11489 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11491 v = cpu_to_le32(tmp);
11492 memcpy(&vpd_data[i], &v, sizeof(v));
11496 /* Now parse and find the part number. */
11497 for (i = 0; i < 254; ) {
11498 unsigned char val = vpd_data[i];
11499 unsigned int block_end;
11501 if (val == 0x82 || val == 0x91) {
11504 (vpd_data[i + 2] << 8)));
11509 goto out_not_found;
11511 block_end = (i + 3 +
11513 (vpd_data[i + 2] << 8)));
11516 if (block_end > 256)
11517 goto out_not_found;
11519 while (i < (block_end - 2)) {
11520 if (vpd_data[i + 0] == 'P' &&
11521 vpd_data[i + 1] == 'N') {
11522 int partno_len = vpd_data[i + 2];
11525 if (partno_len > 24 || (partno_len + i) > 256)
11526 goto out_not_found;
11528 memcpy(tp->board_part_number,
11529 &vpd_data[i], partno_len);
11534 i += 3 + vpd_data[i + 2];
11537 /* Part number not found. */
11538 goto out_not_found;
11542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11543 strcpy(tp->board_part_number, "BCM95906");
11544 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11545 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11546 strcpy(tp->board_part_number, "BCM57780");
11547 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11548 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11549 strcpy(tp->board_part_number, "BCM57760");
11550 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11551 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11552 strcpy(tp->board_part_number, "BCM57790");
11553 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11554 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11555 strcpy(tp->board_part_number, "BCM57788");
11557 strcpy(tp->board_part_number, "none");
11560 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11564 if (tg3_nvram_read(tp, offset, &val) ||
11565 (val & 0xfc000000) != 0x0c000000 ||
11566 tg3_nvram_read(tp, offset + 4, &val) ||
11573 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11575 u32 val, offset, start, ver_offset;
11577 bool newver = false;
11579 if (tg3_nvram_read(tp, 0xc, &offset) ||
11580 tg3_nvram_read(tp, 0x4, &start))
11583 offset = tg3_nvram_logical_addr(tp, offset);
11585 if (tg3_nvram_read(tp, offset, &val))
11588 if ((val & 0xfc000000) == 0x0c000000) {
11589 if (tg3_nvram_read(tp, offset + 4, &val))
11597 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11600 offset = offset + ver_offset - start;
11601 for (i = 0; i < 16; i += 4) {
11603 if (tg3_nvram_read_be32(tp, offset + i, &v))
11606 memcpy(tp->fw_ver + i, &v, sizeof(v));
11611 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11614 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11615 TG3_NVM_BCVER_MAJSFT;
11616 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11617 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11621 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11623 u32 val, major, minor;
11625 /* Use native endian representation */
11626 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11629 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11630 TG3_NVM_HWSB_CFG1_MAJSFT;
11631 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11632 TG3_NVM_HWSB_CFG1_MINSFT;
11634 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11637 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11639 u32 offset, major, minor, build;
11641 tp->fw_ver[0] = 's';
11642 tp->fw_ver[1] = 'b';
11643 tp->fw_ver[2] = '\0';
11645 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11648 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11649 case TG3_EEPROM_SB_REVISION_0:
11650 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11652 case TG3_EEPROM_SB_REVISION_2:
11653 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11655 case TG3_EEPROM_SB_REVISION_3:
11656 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11662 if (tg3_nvram_read(tp, offset, &val))
11665 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11666 TG3_EEPROM_SB_EDH_BLD_SHFT;
11667 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11668 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11669 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11671 if (minor > 99 || build > 26)
11674 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11677 tp->fw_ver[8] = 'a' + build - 1;
11678 tp->fw_ver[9] = '\0';
11682 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11684 u32 val, offset, start;
11687 for (offset = TG3_NVM_DIR_START;
11688 offset < TG3_NVM_DIR_END;
11689 offset += TG3_NVM_DIRENT_SIZE) {
11690 if (tg3_nvram_read(tp, offset, &val))
11693 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11697 if (offset == TG3_NVM_DIR_END)
11700 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11701 start = 0x08000000;
11702 else if (tg3_nvram_read(tp, offset - 4, &start))
11705 if (tg3_nvram_read(tp, offset + 4, &offset) ||
11706 !tg3_fw_img_is_valid(tp, offset) ||
11707 tg3_nvram_read(tp, offset + 8, &val))
11710 offset += val - start;
11712 vlen = strlen(tp->fw_ver);
11714 tp->fw_ver[vlen++] = ',';
11715 tp->fw_ver[vlen++] = ' ';
11717 for (i = 0; i < 4; i++) {
11719 if (tg3_nvram_read_be32(tp, offset, &v))
11722 offset += sizeof(v);
11724 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11725 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11729 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11734 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11739 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11740 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11743 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11744 if (apedata != APE_SEG_SIG_MAGIC)
11747 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11748 if (!(apedata & APE_FW_STATUS_READY))
11751 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11753 vlen = strlen(tp->fw_ver);
11755 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11756 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11757 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11758 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11759 (apedata & APE_FW_VERSION_BLDMSK));
11762 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11766 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11767 tp->fw_ver[0] = 's';
11768 tp->fw_ver[1] = 'b';
11769 tp->fw_ver[2] = '\0';
11774 if (tg3_nvram_read(tp, 0, &val))
11777 if (val == TG3_EEPROM_MAGIC)
11778 tg3_read_bc_ver(tp);
11779 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11780 tg3_read_sb_ver(tp, val);
11781 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11782 tg3_read_hwsb_ver(tp);
11786 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11787 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11790 tg3_read_mgmtfw_ver(tp);
11792 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11795 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11797 static int __devinit tg3_get_invariants(struct tg3 *tp)
11799 static struct pci_device_id write_reorder_chipsets[] = {
11800 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11801 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11802 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11803 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11804 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11805 PCI_DEVICE_ID_VIA_8385_0) },
11809 u32 pci_state_reg, grc_misc_cfg;
11814 /* Force memory write invalidate off. If we leave it on,
11815 * then on 5700_BX chips we have to enable a workaround.
11816 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11817 * to match the cacheline size. The Broadcom driver have this
11818 * workaround but turns MWI off all the times so never uses
11819 * it. This seems to suggest that the workaround is insufficient.
11821 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11822 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11823 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11825 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11826 * has the register indirect write enable bit set before
11827 * we try to access any of the MMIO registers. It is also
11828 * critical that the PCI-X hw workaround situation is decided
11829 * before that as well.
11831 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11834 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11835 MISC_HOST_CTRL_CHIPREV_SHIFT);
11836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11837 u32 prod_id_asic_rev;
11839 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11840 &prod_id_asic_rev);
11841 tp->pci_chip_rev_id = prod_id_asic_rev;
11844 /* Wrong chip ID in 5752 A0. This code can be removed later
11845 * as A0 is not in production.
11847 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11848 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11850 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11851 * we need to disable memory and use config. cycles
11852 * only to access all registers. The 5702/03 chips
11853 * can mistakenly decode the special cycles from the
11854 * ICH chipsets as memory write cycles, causing corruption
11855 * of register and memory space. Only certain ICH bridges
11856 * will drive special cycles with non-zero data during the
11857 * address phase which can fall within the 5703's address
11858 * range. This is not an ICH bug as the PCI spec allows
11859 * non-zero address during special cycles. However, only
11860 * these ICH bridges are known to drive non-zero addresses
11861 * during special cycles.
11863 * Since special cycles do not cross PCI bridges, we only
11864 * enable this workaround if the 5703 is on the secondary
11865 * bus of these ICH bridges.
11867 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11868 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11869 static struct tg3_dev_id {
11873 } ich_chipsets[] = {
11874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11876 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11884 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11885 struct pci_dev *bridge = NULL;
11887 while (pci_id->vendor != 0) {
11888 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11894 if (pci_id->rev != PCI_ANY_ID) {
11895 if (bridge->revision > pci_id->rev)
11898 if (bridge->subordinate &&
11899 (bridge->subordinate->number ==
11900 tp->pdev->bus->number)) {
11902 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11903 pci_dev_put(bridge);
11909 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11910 static struct tg3_dev_id {
11913 } bridge_chipsets[] = {
11914 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11915 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11918 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11919 struct pci_dev *bridge = NULL;
11921 while (pci_id->vendor != 0) {
11922 bridge = pci_get_device(pci_id->vendor,
11929 if (bridge->subordinate &&
11930 (bridge->subordinate->number <=
11931 tp->pdev->bus->number) &&
11932 (bridge->subordinate->subordinate >=
11933 tp->pdev->bus->number)) {
11934 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11935 pci_dev_put(bridge);
11941 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11942 * DMA addresses > 40-bit. This bridge may have other additional
11943 * 57xx devices behind it in some 4-port NIC designs for example.
11944 * Any tg3 device found behind the bridge will also need the 40-bit
11947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11949 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11950 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11951 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11954 struct pci_dev *bridge = NULL;
11957 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11958 PCI_DEVICE_ID_SERVERWORKS_EPB,
11960 if (bridge && bridge->subordinate &&
11961 (bridge->subordinate->number <=
11962 tp->pdev->bus->number) &&
11963 (bridge->subordinate->subordinate >=
11964 tp->pdev->bus->number)) {
11965 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11966 pci_dev_put(bridge);
11972 /* Initialize misc host control in PCI block. */
11973 tp->misc_host_ctrl |= (misc_ctrl_reg &
11974 MISC_HOST_CTRL_CHIPREV);
11975 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11976 tp->misc_host_ctrl);
11978 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11979 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11980 tp->pdev_peer = tg3_find_peer(tp);
11982 /* Intentionally exclude ASIC_REV_5906 */
11983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11989 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11993 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11994 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11995 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11996 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11998 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11999 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12000 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12002 /* 5700 B0 chips do not support checksumming correctly due
12003 * to hardware bugs.
12005 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12006 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12008 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12009 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12010 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12011 tp->dev->features |= NETIF_F_IPV6_CSUM;
12014 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12015 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12016 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12017 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12018 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12019 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12020 tp->pdev_peer == tp->pdev))
12021 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12023 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12025 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12026 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12028 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12029 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12031 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12032 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12036 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12037 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12038 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12040 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12043 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12044 if (tp->pcie_cap != 0) {
12047 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12049 pcie_set_readrq(tp->pdev, 4096);
12051 pci_read_config_word(tp->pdev,
12052 tp->pcie_cap + PCI_EXP_LNKCTL,
12054 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12056 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12059 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12060 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12061 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12063 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12064 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12065 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12066 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12067 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12068 if (!tp->pcix_cap) {
12069 printk(KERN_ERR PFX "Cannot find PCI-X "
12070 "capability, aborting.\n");
12074 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12075 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12078 /* If we have an AMD 762 or VIA K8T800 chipset, write
12079 * reordering to the mailbox registers done by the host
12080 * controller can cause major troubles. We read back from
12081 * every mailbox register write to force the writes to be
12082 * posted to the chip in order.
12084 if (pci_dev_present(write_reorder_chipsets) &&
12085 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12086 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12088 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12089 &tp->pci_cacheline_sz);
12090 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12091 &tp->pci_lat_timer);
12092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12093 tp->pci_lat_timer < 64) {
12094 tp->pci_lat_timer = 64;
12095 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12096 tp->pci_lat_timer);
12099 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12100 /* 5700 BX chips need to have their TX producer index
12101 * mailboxes written twice to workaround a bug.
12103 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12105 /* If we are in PCI-X mode, enable register write workaround.
12107 * The workaround is to use indirect register accesses
12108 * for all chip writes not to mailbox registers.
12110 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12113 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12115 /* The chip can have it's power management PCI config
12116 * space registers clobbered due to this bug.
12117 * So explicitly force the chip into D0 here.
12119 pci_read_config_dword(tp->pdev,
12120 tp->pm_cap + PCI_PM_CTRL,
12122 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12123 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12124 pci_write_config_dword(tp->pdev,
12125 tp->pm_cap + PCI_PM_CTRL,
12128 /* Also, force SERR#/PERR# in PCI command. */
12129 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12130 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12131 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12135 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12136 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12137 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12138 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12140 /* Chip-specific fixup from Broadcom driver */
12141 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12142 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12143 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12144 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12147 /* Default fast path register access methods */
12148 tp->read32 = tg3_read32;
12149 tp->write32 = tg3_write32;
12150 tp->read32_mbox = tg3_read32;
12151 tp->write32_mbox = tg3_write32;
12152 tp->write32_tx_mbox = tg3_write32;
12153 tp->write32_rx_mbox = tg3_write32;
12155 /* Various workaround register access methods */
12156 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12157 tp->write32 = tg3_write_indirect_reg32;
12158 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12159 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12160 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12162 * Back to back register writes can cause problems on these
12163 * chips, the workaround is to read back all reg writes
12164 * except those to mailbox regs.
12166 * See tg3_write_indirect_reg32().
12168 tp->write32 = tg3_write_flush_reg32;
12172 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12173 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12174 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12175 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12176 tp->write32_rx_mbox = tg3_write_flush_reg32;
12179 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12180 tp->read32 = tg3_read_indirect_reg32;
12181 tp->write32 = tg3_write_indirect_reg32;
12182 tp->read32_mbox = tg3_read_indirect_mbox;
12183 tp->write32_mbox = tg3_write_indirect_mbox;
12184 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12185 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12190 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12191 pci_cmd &= ~PCI_COMMAND_MEMORY;
12192 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12195 tp->read32_mbox = tg3_read32_mbox_5906;
12196 tp->write32_mbox = tg3_write32_mbox_5906;
12197 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12198 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12201 if (tp->write32 == tg3_write_indirect_reg32 ||
12202 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12203 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12204 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12205 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12207 /* Get eeprom hw config before calling tg3_set_power_state().
12208 * In particular, the TG3_FLG2_IS_NIC flag must be
12209 * determined before calling tg3_set_power_state() so that
12210 * we know whether or not to switch out of Vaux power.
12211 * When the flag is set, it means that GPIO1 is used for eeprom
12212 * write protect and also implies that it is a LOM where GPIOs
12213 * are not used to switch power.
12215 tg3_get_eeprom_hw_cfg(tp);
12217 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12218 /* Allow reads and writes to the
12219 * APE register and memory space.
12221 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12222 PCISTATE_ALLOW_APE_SHMEM_WR;
12223 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12227 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12231 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12233 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12234 * GPIO1 driven high will bring 5700's external PHY out of reset.
12235 * It is also used as eeprom write protect on LOMs.
12237 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12238 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12239 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12240 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12241 GRC_LCLCTRL_GPIO_OUTPUT1);
12242 /* Unused GPIO3 must be driven as output on 5752 because there
12243 * are no pull-up resistors on unused GPIO pins.
12245 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12246 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12250 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12252 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12253 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12254 /* Turn off the debug UART. */
12255 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12256 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12257 /* Keep VMain power. */
12258 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12259 GRC_LCLCTRL_GPIO_OUTPUT0;
12262 /* Force the chip into D0. */
12263 err = tg3_set_power_state(tp, PCI_D0);
12265 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12266 pci_name(tp->pdev));
12270 /* Derive initial jumbo mode from MTU assigned in
12271 * ether_setup() via the alloc_etherdev() call
12273 if (tp->dev->mtu > ETH_DATA_LEN &&
12274 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12275 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12277 /* Determine WakeOnLan speed to use. */
12278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12279 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12280 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12281 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12282 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12284 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12288 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12290 /* A few boards don't want Ethernet@WireSpeed phy feature */
12291 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12292 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12293 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12294 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12295 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12296 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12297 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12299 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12300 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12301 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12302 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12303 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12305 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12306 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12307 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12308 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12309 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12313 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12314 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12315 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12316 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12317 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12319 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12322 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12323 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12324 tp->phy_otp = tg3_read_otp_phycfg(tp);
12325 if (tp->phy_otp == 0)
12326 tp->phy_otp = TG3_OTP_DEFAULT;
12329 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12330 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12332 tp->mi_mode = MAC_MI_MODE_BASE;
12334 tp->coalesce_mode = 0;
12335 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12336 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12337 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12340 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12341 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12343 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12344 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12345 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12346 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12348 err = tg3_mdio_init(tp);
12352 /* Initialize data/descriptor byte/word swapping. */
12353 val = tr32(GRC_MODE);
12354 val &= GRC_MODE_HOST_STACKUP;
12355 tw32(GRC_MODE, val | tp->grc_mode);
12357 tg3_switch_clocks(tp);
12359 /* Clear this out for sanity. */
12360 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12362 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12364 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12365 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12366 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12368 if (chiprevid == CHIPREV_ID_5701_A0 ||
12369 chiprevid == CHIPREV_ID_5701_B0 ||
12370 chiprevid == CHIPREV_ID_5701_B2 ||
12371 chiprevid == CHIPREV_ID_5701_B5) {
12372 void __iomem *sram_base;
12374 /* Write some dummy words into the SRAM status block
12375 * area, see if it reads back correctly. If the return
12376 * value is bad, force enable the PCIX workaround.
12378 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12380 writel(0x00000000, sram_base);
12381 writel(0x00000000, sram_base + 4);
12382 writel(0xffffffff, sram_base + 4);
12383 if (readl(sram_base) != 0x00000000)
12384 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12389 tg3_nvram_init(tp);
12391 grc_misc_cfg = tr32(GRC_MISC_CFG);
12392 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12395 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12396 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12397 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12399 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12400 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12401 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12402 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12403 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12404 HOSTCC_MODE_CLRTICK_TXBD);
12406 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12407 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12408 tp->misc_host_ctrl);
12411 /* Preserve the APE MAC_MODE bits */
12412 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12413 tp->mac_mode = tr32(MAC_MODE) |
12414 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12416 tp->mac_mode = TG3_DEF_MAC_MODE;
12418 /* these are limited to 10/100 only */
12419 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12420 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12421 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12422 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12423 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12424 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12425 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12426 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12427 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12428 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12429 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12430 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12431 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12432 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12434 err = tg3_phy_probe(tp);
12436 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12437 pci_name(tp->pdev), err);
12438 /* ... but do not return immediately ... */
12442 tg3_read_partno(tp);
12443 tg3_read_fw_ver(tp);
12445 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12446 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12449 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12451 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12454 /* 5700 {AX,BX} chips have a broken status block link
12455 * change bit implementation, so we must use the
12456 * status register in those cases.
12458 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12459 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12461 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12463 /* The led_ctrl is set during tg3_phy_probe, here we might
12464 * have to force the link status polling mechanism based
12465 * upon subsystem IDs.
12467 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12468 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12469 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12470 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12471 TG3_FLAG_USE_LINKCHG_REG);
12474 /* For all SERDES we poll the MAC status register. */
12475 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12476 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12478 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12480 tp->rx_offset = NET_IP_ALIGN;
12481 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12482 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12485 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12487 /* Increment the rx prod index on the rx std ring by at most
12488 * 8 for these chips to workaround hw errata.
12490 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12491 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12492 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12493 tp->rx_std_max_post = 8;
12495 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12496 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12497 PCIE_PWR_MGMT_L1_THRESH_MSK;
12502 #ifdef CONFIG_SPARC
12503 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12505 struct net_device *dev = tp->dev;
12506 struct pci_dev *pdev = tp->pdev;
12507 struct device_node *dp = pci_device_to_OF_node(pdev);
12508 const unsigned char *addr;
12511 addr = of_get_property(dp, "local-mac-address", &len);
12512 if (addr && len == 6) {
12513 memcpy(dev->dev_addr, addr, 6);
12514 memcpy(dev->perm_addr, dev->dev_addr, 6);
12520 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12522 struct net_device *dev = tp->dev;
12524 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12525 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12530 static int __devinit tg3_get_device_address(struct tg3 *tp)
12532 struct net_device *dev = tp->dev;
12533 u32 hi, lo, mac_offset;
12536 #ifdef CONFIG_SPARC
12537 if (!tg3_get_macaddr_sparc(tp))
12542 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12543 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12544 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12546 if (tg3_nvram_lock(tp))
12547 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12549 tg3_nvram_unlock(tp);
12551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12554 /* First try to get it from MAC address mailbox. */
12555 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12556 if ((hi >> 16) == 0x484b) {
12557 dev->dev_addr[0] = (hi >> 8) & 0xff;
12558 dev->dev_addr[1] = (hi >> 0) & 0xff;
12560 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12561 dev->dev_addr[2] = (lo >> 24) & 0xff;
12562 dev->dev_addr[3] = (lo >> 16) & 0xff;
12563 dev->dev_addr[4] = (lo >> 8) & 0xff;
12564 dev->dev_addr[5] = (lo >> 0) & 0xff;
12566 /* Some old bootcode may report a 0 MAC address in SRAM */
12567 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12570 /* Next, try NVRAM. */
12571 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12572 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12573 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12574 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12575 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12577 /* Finally just fetch it out of the MAC control regs. */
12579 hi = tr32(MAC_ADDR_0_HIGH);
12580 lo = tr32(MAC_ADDR_0_LOW);
12582 dev->dev_addr[5] = lo & 0xff;
12583 dev->dev_addr[4] = (lo >> 8) & 0xff;
12584 dev->dev_addr[3] = (lo >> 16) & 0xff;
12585 dev->dev_addr[2] = (lo >> 24) & 0xff;
12586 dev->dev_addr[1] = hi & 0xff;
12587 dev->dev_addr[0] = (hi >> 8) & 0xff;
12591 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12592 #ifdef CONFIG_SPARC
12593 if (!tg3_get_default_macaddr_sparc(tp))
12598 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12602 #define BOUNDARY_SINGLE_CACHELINE 1
12603 #define BOUNDARY_MULTI_CACHELINE 2
12605 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12607 int cacheline_size;
12611 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12613 cacheline_size = 1024;
12615 cacheline_size = (int) byte * 4;
12617 /* On 5703 and later chips, the boundary bits have no
12620 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12621 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12622 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12625 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12626 goal = BOUNDARY_MULTI_CACHELINE;
12628 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12629 goal = BOUNDARY_SINGLE_CACHELINE;
12638 /* PCI controllers on most RISC systems tend to disconnect
12639 * when a device tries to burst across a cache-line boundary.
12640 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12642 * Unfortunately, for PCI-E there are only limited
12643 * write-side controls for this, and thus for reads
12644 * we will still get the disconnects. We'll also waste
12645 * these PCI cycles for both read and write for chips
12646 * other than 5700 and 5701 which do not implement the
12649 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12650 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12651 switch (cacheline_size) {
12656 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12657 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12658 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12660 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12661 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12666 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12667 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12671 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12672 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12675 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12676 switch (cacheline_size) {
12680 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12681 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12682 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12688 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12689 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12693 switch (cacheline_size) {
12695 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12696 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12697 DMA_RWCTRL_WRITE_BNDRY_16);
12702 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12703 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12704 DMA_RWCTRL_WRITE_BNDRY_32);
12709 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12710 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12711 DMA_RWCTRL_WRITE_BNDRY_64);
12716 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12717 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12718 DMA_RWCTRL_WRITE_BNDRY_128);
12723 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12724 DMA_RWCTRL_WRITE_BNDRY_256);
12727 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12728 DMA_RWCTRL_WRITE_BNDRY_512);
12732 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12733 DMA_RWCTRL_WRITE_BNDRY_1024);
12742 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12744 struct tg3_internal_buffer_desc test_desc;
12745 u32 sram_dma_descs;
12748 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12750 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12751 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12752 tw32(RDMAC_STATUS, 0);
12753 tw32(WDMAC_STATUS, 0);
12755 tw32(BUFMGR_MODE, 0);
12756 tw32(FTQ_RESET, 0);
12758 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12759 test_desc.addr_lo = buf_dma & 0xffffffff;
12760 test_desc.nic_mbuf = 0x00002100;
12761 test_desc.len = size;
12764 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12765 * the *second* time the tg3 driver was getting loaded after an
12768 * Broadcom tells me:
12769 * ...the DMA engine is connected to the GRC block and a DMA
12770 * reset may affect the GRC block in some unpredictable way...
12771 * The behavior of resets to individual blocks has not been tested.
12773 * Broadcom noted the GRC reset will also reset all sub-components.
12776 test_desc.cqid_sqid = (13 << 8) | 2;
12778 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12781 test_desc.cqid_sqid = (16 << 8) | 7;
12783 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12786 test_desc.flags = 0x00000005;
12788 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12791 val = *(((u32 *)&test_desc) + i);
12792 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12793 sram_dma_descs + (i * sizeof(u32)));
12794 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12796 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12799 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12801 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12805 for (i = 0; i < 40; i++) {
12809 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12811 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12812 if ((val & 0xffff) == sram_dma_descs) {
12823 #define TEST_BUFFER_SIZE 0x2000
12825 static int __devinit tg3_test_dma(struct tg3 *tp)
12827 dma_addr_t buf_dma;
12828 u32 *buf, saved_dma_rwctrl;
12831 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12837 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12838 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12840 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12842 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12843 /* DMA read watermark not used on PCIE */
12844 tp->dma_rwctrl |= 0x00180000;
12845 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12846 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12848 tp->dma_rwctrl |= 0x003f0000;
12850 tp->dma_rwctrl |= 0x003f000f;
12852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12853 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12854 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12855 u32 read_water = 0x7;
12857 /* If the 5704 is behind the EPB bridge, we can
12858 * do the less restrictive ONE_DMA workaround for
12859 * better performance.
12861 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12863 tp->dma_rwctrl |= 0x8000;
12864 else if (ccval == 0x6 || ccval == 0x7)
12865 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12867 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12869 /* Set bit 23 to enable PCIX hw bug fix */
12871 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12872 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12874 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12875 /* 5780 always in PCIX mode */
12876 tp->dma_rwctrl |= 0x00144000;
12877 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12878 /* 5714 always in PCIX mode */
12879 tp->dma_rwctrl |= 0x00148000;
12881 tp->dma_rwctrl |= 0x001b000f;
12885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12886 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12887 tp->dma_rwctrl &= 0xfffffff0;
12889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12891 /* Remove this if it causes problems for some boards. */
12892 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12894 /* On 5700/5701 chips, we need to set this bit.
12895 * Otherwise the chip will issue cacheline transactions
12896 * to streamable DMA memory with not all the byte
12897 * enables turned on. This is an error on several
12898 * RISC PCI controllers, in particular sparc64.
12900 * On 5703/5704 chips, this bit has been reassigned
12901 * a different meaning. In particular, it is used
12902 * on those chips to enable a PCI-X workaround.
12904 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12907 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12910 /* Unneeded, already done by tg3_get_invariants. */
12911 tg3_switch_clocks(tp);
12915 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12916 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12919 /* It is best to perform DMA test with maximum write burst size
12920 * to expose the 5700/5701 write DMA bug.
12922 saved_dma_rwctrl = tp->dma_rwctrl;
12923 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12924 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12929 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12932 /* Send the buffer to the chip. */
12933 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12935 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12940 /* validate data reached card RAM correctly. */
12941 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12943 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12944 if (le32_to_cpu(val) != p[i]) {
12945 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12946 /* ret = -ENODEV here? */
12951 /* Now read it back. */
12952 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12954 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12960 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12964 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12965 DMA_RWCTRL_WRITE_BNDRY_16) {
12966 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12967 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12968 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12971 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12977 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12983 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12984 DMA_RWCTRL_WRITE_BNDRY_16) {
12985 static struct pci_device_id dma_wait_state_chipsets[] = {
12986 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12987 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12991 /* DMA test passed without adjusting DMA boundary,
12992 * now look for chipsets that are known to expose the
12993 * DMA bug without failing the test.
12995 if (pci_dev_present(dma_wait_state_chipsets)) {
12996 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12997 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13000 /* Safe to use the calculated DMA boundary. */
13001 tp->dma_rwctrl = saved_dma_rwctrl;
13003 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13007 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13012 static void __devinit tg3_init_link_config(struct tg3 *tp)
13014 tp->link_config.advertising =
13015 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13016 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13017 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13018 ADVERTISED_Autoneg | ADVERTISED_MII);
13019 tp->link_config.speed = SPEED_INVALID;
13020 tp->link_config.duplex = DUPLEX_INVALID;
13021 tp->link_config.autoneg = AUTONEG_ENABLE;
13022 tp->link_config.active_speed = SPEED_INVALID;
13023 tp->link_config.active_duplex = DUPLEX_INVALID;
13024 tp->link_config.phy_is_low_power = 0;
13025 tp->link_config.orig_speed = SPEED_INVALID;
13026 tp->link_config.orig_duplex = DUPLEX_INVALID;
13027 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13030 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13032 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13033 tp->bufmgr_config.mbuf_read_dma_low_water =
13034 DEFAULT_MB_RDMA_LOW_WATER_5705;
13035 tp->bufmgr_config.mbuf_mac_rx_low_water =
13036 DEFAULT_MB_MACRX_LOW_WATER_5705;
13037 tp->bufmgr_config.mbuf_high_water =
13038 DEFAULT_MB_HIGH_WATER_5705;
13039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13040 tp->bufmgr_config.mbuf_mac_rx_low_water =
13041 DEFAULT_MB_MACRX_LOW_WATER_5906;
13042 tp->bufmgr_config.mbuf_high_water =
13043 DEFAULT_MB_HIGH_WATER_5906;
13046 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13047 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13048 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13049 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13050 tp->bufmgr_config.mbuf_high_water_jumbo =
13051 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13053 tp->bufmgr_config.mbuf_read_dma_low_water =
13054 DEFAULT_MB_RDMA_LOW_WATER;
13055 tp->bufmgr_config.mbuf_mac_rx_low_water =
13056 DEFAULT_MB_MACRX_LOW_WATER;
13057 tp->bufmgr_config.mbuf_high_water =
13058 DEFAULT_MB_HIGH_WATER;
13060 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13061 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13062 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13063 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13064 tp->bufmgr_config.mbuf_high_water_jumbo =
13065 DEFAULT_MB_HIGH_WATER_JUMBO;
13068 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13069 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13072 static char * __devinit tg3_phy_string(struct tg3 *tp)
13074 switch (tp->phy_id & PHY_ID_MASK) {
13075 case PHY_ID_BCM5400: return "5400";
13076 case PHY_ID_BCM5401: return "5401";
13077 case PHY_ID_BCM5411: return "5411";
13078 case PHY_ID_BCM5701: return "5701";
13079 case PHY_ID_BCM5703: return "5703";
13080 case PHY_ID_BCM5704: return "5704";
13081 case PHY_ID_BCM5705: return "5705";
13082 case PHY_ID_BCM5750: return "5750";
13083 case PHY_ID_BCM5752: return "5752";
13084 case PHY_ID_BCM5714: return "5714";
13085 case PHY_ID_BCM5780: return "5780";
13086 case PHY_ID_BCM5755: return "5755";
13087 case PHY_ID_BCM5787: return "5787";
13088 case PHY_ID_BCM5784: return "5784";
13089 case PHY_ID_BCM5756: return "5722/5756";
13090 case PHY_ID_BCM5906: return "5906";
13091 case PHY_ID_BCM5761: return "5761";
13092 case PHY_ID_BCM8002: return "8002/serdes";
13093 case 0: return "serdes";
13094 default: return "unknown";
13098 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13100 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13101 strcpy(str, "PCI Express");
13103 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13104 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13106 strcpy(str, "PCIX:");
13108 if ((clock_ctrl == 7) ||
13109 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13110 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13111 strcat(str, "133MHz");
13112 else if (clock_ctrl == 0)
13113 strcat(str, "33MHz");
13114 else if (clock_ctrl == 2)
13115 strcat(str, "50MHz");
13116 else if (clock_ctrl == 4)
13117 strcat(str, "66MHz");
13118 else if (clock_ctrl == 6)
13119 strcat(str, "100MHz");
13121 strcpy(str, "PCI:");
13122 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13123 strcat(str, "66MHz");
13125 strcat(str, "33MHz");
13127 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13128 strcat(str, ":32-bit");
13130 strcat(str, ":64-bit");
13134 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13136 struct pci_dev *peer;
13137 unsigned int func, devnr = tp->pdev->devfn & ~7;
13139 for (func = 0; func < 8; func++) {
13140 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13141 if (peer && peer != tp->pdev)
13145 /* 5704 can be configured in single-port mode, set peer to
13146 * tp->pdev in that case.
13154 * We don't need to keep the refcount elevated; there's no way
13155 * to remove one half of this device without removing the other
13162 static void __devinit tg3_init_coal(struct tg3 *tp)
13164 struct ethtool_coalesce *ec = &tp->coal;
13166 memset(ec, 0, sizeof(*ec));
13167 ec->cmd = ETHTOOL_GCOALESCE;
13168 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13169 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13170 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13171 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13172 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13173 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13174 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13175 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13176 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13178 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13179 HOSTCC_MODE_CLRTICK_TXBD)) {
13180 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13181 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13182 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13183 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13186 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13187 ec->rx_coalesce_usecs_irq = 0;
13188 ec->tx_coalesce_usecs_irq = 0;
13189 ec->stats_block_coalesce_usecs = 0;
13193 static const struct net_device_ops tg3_netdev_ops = {
13194 .ndo_open = tg3_open,
13195 .ndo_stop = tg3_close,
13196 .ndo_start_xmit = tg3_start_xmit,
13197 .ndo_get_stats = tg3_get_stats,
13198 .ndo_validate_addr = eth_validate_addr,
13199 .ndo_set_multicast_list = tg3_set_rx_mode,
13200 .ndo_set_mac_address = tg3_set_mac_addr,
13201 .ndo_do_ioctl = tg3_ioctl,
13202 .ndo_tx_timeout = tg3_tx_timeout,
13203 .ndo_change_mtu = tg3_change_mtu,
13204 #if TG3_VLAN_TAG_USED
13205 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13207 #ifdef CONFIG_NET_POLL_CONTROLLER
13208 .ndo_poll_controller = tg3_poll_controller,
13212 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13213 .ndo_open = tg3_open,
13214 .ndo_stop = tg3_close,
13215 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13216 .ndo_get_stats = tg3_get_stats,
13217 .ndo_validate_addr = eth_validate_addr,
13218 .ndo_set_multicast_list = tg3_set_rx_mode,
13219 .ndo_set_mac_address = tg3_set_mac_addr,
13220 .ndo_do_ioctl = tg3_ioctl,
13221 .ndo_tx_timeout = tg3_tx_timeout,
13222 .ndo_change_mtu = tg3_change_mtu,
13223 #if TG3_VLAN_TAG_USED
13224 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13226 #ifdef CONFIG_NET_POLL_CONTROLLER
13227 .ndo_poll_controller = tg3_poll_controller,
13231 static int __devinit tg3_init_one(struct pci_dev *pdev,
13232 const struct pci_device_id *ent)
13234 static int tg3_version_printed = 0;
13235 struct net_device *dev;
13239 u64 dma_mask, persist_dma_mask;
13241 if (tg3_version_printed++ == 0)
13242 printk(KERN_INFO "%s", version);
13244 err = pci_enable_device(pdev);
13246 printk(KERN_ERR PFX "Cannot enable PCI device, "
13251 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13253 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13255 goto err_out_disable_pdev;
13258 pci_set_master(pdev);
13260 /* Find power-management capability. */
13261 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13263 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13266 goto err_out_free_res;
13269 dev = alloc_etherdev(sizeof(*tp));
13271 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13273 goto err_out_free_res;
13276 SET_NETDEV_DEV(dev, &pdev->dev);
13278 #if TG3_VLAN_TAG_USED
13279 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13282 tp = netdev_priv(dev);
13285 tp->pm_cap = pm_cap;
13286 tp->rx_mode = TG3_DEF_RX_MODE;
13287 tp->tx_mode = TG3_DEF_TX_MODE;
13290 tp->msg_enable = tg3_debug;
13292 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13294 /* The word/byte swap controls here control register access byte
13295 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13298 tp->misc_host_ctrl =
13299 MISC_HOST_CTRL_MASK_PCI_INT |
13300 MISC_HOST_CTRL_WORD_SWAP |
13301 MISC_HOST_CTRL_INDIR_ACCESS |
13302 MISC_HOST_CTRL_PCISTATE_RW;
13304 /* The NONFRM (non-frame) byte/word swap controls take effect
13305 * on descriptor entries, anything which isn't packet data.
13307 * The StrongARM chips on the board (one for tx, one for rx)
13308 * are running in big-endian mode.
13310 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13311 GRC_MODE_WSWAP_NONFRM_DATA);
13312 #ifdef __BIG_ENDIAN
13313 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13315 spin_lock_init(&tp->lock);
13316 spin_lock_init(&tp->indirect_lock);
13317 INIT_WORK(&tp->reset_task, tg3_reset_task);
13319 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13321 printk(KERN_ERR PFX "Cannot map device registers, "
13324 goto err_out_free_dev;
13327 tg3_init_link_config(tp);
13329 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13330 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13331 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13333 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13334 dev->ethtool_ops = &tg3_ethtool_ops;
13335 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13336 dev->irq = pdev->irq;
13338 err = tg3_get_invariants(tp);
13340 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13342 goto err_out_iounmap;
13345 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13347 dev->netdev_ops = &tg3_netdev_ops;
13349 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13352 /* The EPB bridge inside 5714, 5715, and 5780 and any
13353 * device behind the EPB cannot support DMA addresses > 40-bit.
13354 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13355 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13356 * do DMA address check in tg3_start_xmit().
13358 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13359 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13360 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13361 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13362 #ifdef CONFIG_HIGHMEM
13363 dma_mask = DMA_BIT_MASK(64);
13366 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13368 /* Configure DMA attributes. */
13369 if (dma_mask > DMA_BIT_MASK(32)) {
13370 err = pci_set_dma_mask(pdev, dma_mask);
13372 dev->features |= NETIF_F_HIGHDMA;
13373 err = pci_set_consistent_dma_mask(pdev,
13376 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13377 "DMA for consistent allocations\n");
13378 goto err_out_iounmap;
13382 if (err || dma_mask == DMA_BIT_MASK(32)) {
13383 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13385 printk(KERN_ERR PFX "No usable DMA configuration, "
13387 goto err_out_iounmap;
13391 tg3_init_bufmgr_config(tp);
13393 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13394 tp->fw_needed = FIRMWARE_TG3;
13396 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13397 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13399 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13400 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13401 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13402 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13403 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13404 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13406 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13408 tp->fw_needed = FIRMWARE_TG3TSO5;
13410 tp->fw_needed = FIRMWARE_TG3TSO;
13413 /* TSO is on by default on chips that support hardware TSO.
13414 * Firmware TSO on older chips gives lower performance, so it
13415 * is off by default, but can be enabled using ethtool.
13417 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13418 if (dev->features & NETIF_F_IP_CSUM)
13419 dev->features |= NETIF_F_TSO;
13420 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13421 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13422 dev->features |= NETIF_F_TSO6;
13423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13424 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13425 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13428 dev->features |= NETIF_F_TSO_ECN;
13432 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13433 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13434 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13435 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13436 tp->rx_pending = 63;
13439 err = tg3_get_device_address(tp);
13441 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13446 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13447 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13448 if (!tp->aperegs) {
13449 printk(KERN_ERR PFX "Cannot map APE registers, "
13455 tg3_ape_lock_init(tp);
13457 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13458 tg3_read_dash_ver(tp);
13462 * Reset chip in case UNDI or EFI driver did not shutdown
13463 * DMA self test will enable WDMAC and we'll see (spurious)
13464 * pending DMA on the PCI bus at that point.
13466 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13467 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13468 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13469 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13472 err = tg3_test_dma(tp);
13474 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13475 goto err_out_apeunmap;
13478 /* flow control autonegotiation is default behavior */
13479 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13480 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13484 pci_set_drvdata(pdev, dev);
13486 err = register_netdev(dev);
13488 printk(KERN_ERR PFX "Cannot register net device, "
13490 goto err_out_apeunmap;
13493 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13495 tp->board_part_number,
13496 tp->pci_chip_rev_id,
13497 tg3_bus_string(tp, str),
13500 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13502 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13504 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13505 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13508 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13509 tp->dev->name, tg3_phy_string(tp),
13510 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13511 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13512 "10/100/1000Base-T")),
13513 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13515 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13517 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13518 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13519 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13520 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13521 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13522 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13523 dev->name, tp->dma_rwctrl,
13524 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13525 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13531 iounmap(tp->aperegs);
13532 tp->aperegs = NULL;
13537 release_firmware(tp->fw);
13549 pci_release_regions(pdev);
13551 err_out_disable_pdev:
13552 pci_disable_device(pdev);
13553 pci_set_drvdata(pdev, NULL);
13557 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13559 struct net_device *dev = pci_get_drvdata(pdev);
13562 struct tg3 *tp = netdev_priv(dev);
13565 release_firmware(tp->fw);
13567 flush_scheduled_work();
13569 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13574 unregister_netdev(dev);
13576 iounmap(tp->aperegs);
13577 tp->aperegs = NULL;
13584 pci_release_regions(pdev);
13585 pci_disable_device(pdev);
13586 pci_set_drvdata(pdev, NULL);
13590 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13592 struct net_device *dev = pci_get_drvdata(pdev);
13593 struct tg3 *tp = netdev_priv(dev);
13594 pci_power_t target_state;
13597 /* PCI register 4 needs to be saved whether netif_running() or not.
13598 * MSI address and data need to be saved if using MSI and
13601 pci_save_state(pdev);
13603 if (!netif_running(dev))
13606 flush_scheduled_work();
13608 tg3_netif_stop(tp);
13610 del_timer_sync(&tp->timer);
13612 tg3_full_lock(tp, 1);
13613 tg3_disable_ints(tp);
13614 tg3_full_unlock(tp);
13616 netif_device_detach(dev);
13618 tg3_full_lock(tp, 0);
13619 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13620 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13621 tg3_full_unlock(tp);
13623 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13625 err = tg3_set_power_state(tp, target_state);
13629 tg3_full_lock(tp, 0);
13631 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13632 err2 = tg3_restart_hw(tp, 1);
13636 tp->timer.expires = jiffies + tp->timer_offset;
13637 add_timer(&tp->timer);
13639 netif_device_attach(dev);
13640 tg3_netif_start(tp);
13643 tg3_full_unlock(tp);
13652 static int tg3_resume(struct pci_dev *pdev)
13654 struct net_device *dev = pci_get_drvdata(pdev);
13655 struct tg3 *tp = netdev_priv(dev);
13658 pci_restore_state(tp->pdev);
13660 if (!netif_running(dev))
13663 err = tg3_set_power_state(tp, PCI_D0);
13667 netif_device_attach(dev);
13669 tg3_full_lock(tp, 0);
13671 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13672 err = tg3_restart_hw(tp, 1);
13676 tp->timer.expires = jiffies + tp->timer_offset;
13677 add_timer(&tp->timer);
13679 tg3_netif_start(tp);
13682 tg3_full_unlock(tp);
13690 static struct pci_driver tg3_driver = {
13691 .name = DRV_MODULE_NAME,
13692 .id_table = tg3_pci_tbl,
13693 .probe = tg3_init_one,
13694 .remove = __devexit_p(tg3_remove_one),
13695 .suspend = tg3_suspend,
13696 .resume = tg3_resume
13699 static int __init tg3_init(void)
13701 return pci_register_driver(&tg3_driver);
13704 static void __exit tg3_cleanup(void)
13706 pci_unregister_driver(&tg3_driver);
13709 module_init(tg3_init);
13710 module_exit(tg3_cleanup);