2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.104"
72 #define DRV_MODULE_RELDATE "November 13, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130 #define TG3_DMA_BYTE_ENAB 64
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140 #define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
143 #define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
146 /* minimum number of free TX descriptors required to wake up TX process */
147 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
149 #define TG3_RAW_IP_ALIGN 2
151 /* number of ETHTOOL_GSTATS u64's */
152 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
154 #define TG3_NUM_TEST 6
156 #define FIRMWARE_TG3 "tigon/tg3.bin"
157 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
160 static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_MODULE_VERSION);
167 MODULE_FIRMWARE(FIRMWARE_TG3);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
171 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
173 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174 module_param(tg3_debug, int, 0);
175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
177 static struct pci_device_id tg3_pci_tbl[] = {
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
259 static const struct {
260 const char string[ETH_GSTRING_LEN];
261 } ethtool_stats_keys[TG3_NUM_STATS] = {
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
294 { "tx_flow_control" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
327 { "rx_threshold_hit" },
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
340 static const struct {
341 const char string[ETH_GSTRING_LEN];
342 } ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
353 writel(val, tp->regs + off);
356 static u32 tg3_read32(struct tg3 *tp, u32 off)
358 return (readl(tp->regs + off));
361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
363 writel(val, tp->aperegs + off);
366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
368 return (readl(tp->aperegs + off));
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
408 if (off == TG3_RX_STD_PROD_IDX_REG) {
409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
454 tg3_write32(tp, off, val);
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
468 tp->write32_mbox(tp, off, val);
469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
476 void __iomem *mbox = tp->regs + off;
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
486 return (readl(tp->regs + off + GRCMBOX_BASE));
489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
491 writel(val, tp->regs + off + GRCMBOX_BASE);
494 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
495 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
496 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
498 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
500 #define tw32(reg,val) tp->write32(tp, reg, val)
501 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
503 #define tr32(reg) tp->read32(tp, reg)
505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
513 spin_lock_irqsave(&tp->indirect_lock, flags);
514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
540 spin_lock_irqsave(&tp->indirect_lock, flags);
541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
557 static void tg3_ape_lock_init(struct tg3 *tp)
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
577 case TG3_APE_LOCK_GRC:
578 case TG3_APE_LOCK_MEM:
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
615 case TG3_APE_LOCK_GRC:
616 case TG3_APE_LOCK_MEM:
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
626 static void tg3_disable_ints(struct tg3 *tp)
630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
636 static void tg3_enable_ints(struct tg3 *tp)
644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
653 coal_now |= tnapi->coal_now;
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
667 struct tg3 *tp = tnapi->tp;
668 struct tg3_hw_status *sblk = tnapi->hw_status;
669 unsigned int work_exists = 0;
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
678 /* check for RX/TX work to do */
679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
689 * which reenables interrupts
691 static void tg3_int_reenable(struct tg3_napi *tnapi)
693 struct tg3 *tp = tnapi->tp;
695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704 tw32(HOSTCC_MODE, tp->coalesce_mode |
705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
708 static void tg3_napi_disable(struct tg3 *tp)
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
716 static void tg3_napi_enable(struct tg3 *tp)
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
724 static inline void tg3_netif_stop(struct tg3 *tp)
726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
727 tg3_napi_disable(tp);
728 netif_tx_disable(tp->dev);
731 static inline void tg3_netif_start(struct tg3 *tp)
733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
737 netif_tx_wake_all_queues(tp->dev);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
744 static void tg3_switch_clocks(struct tg3 *tp)
749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
759 tp->pci_clock_ctrl = clock_ctrl;
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
778 #define PHY_BUSY_LOOPS 5000
780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
800 tw32_f(MAC_MI_COM, frame_val);
802 loops = PHY_BUSY_LOOPS;
805 frame_val = tr32(MAC_MI_COM);
807 if ((frame_val & MI_COM_BUSY) == 0) {
809 frame_val = tr32(MAC_MI_COM);
817 *val = frame_val & MI_COM_DATA_MASK;
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
852 tw32_f(MAC_MI_COM, frame_val);
854 loops = PHY_BUSY_LOOPS;
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
860 frame_val = tr32(MAC_MI_COM);
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 static int tg3_bmcr_reset(struct tg3 *tp)
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
897 if ((phy_control & BMCR_RESET) == 0) {
909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
911 struct tg3 *tp = bp->priv;
914 spin_lock_bh(&tp->lock);
916 if (tg3_readphy(tp, reg, &val))
919 spin_unlock_bh(&tp->lock);
924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
926 struct tg3 *tp = bp->priv;
929 spin_lock_bh(&tp->lock);
931 if (tg3_writephy(tp, reg, val))
934 spin_unlock_bh(&tp->lock);
939 static int tg3_mdio_reset(struct mii_bus *bp)
944 static void tg3_mdio_config_5785(struct tg3 *tp)
947 struct phy_device *phydev;
949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
952 case TG3_PHY_ID_BCM50610M:
953 val = MAC_PHYCFG2_50610_LED_MODES;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
971 val = tr32(MAC_PHYCFG1);
972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
975 tw32(MAC_PHYCFG1, val);
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
988 tw32(MAC_PHYCFG2, val);
990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1022 tw32(MAC_EXT_RGMII_MODE, val);
1025 static void tg3_mdio_start(struct tg3 *tp)
1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1044 tp->phy_addr = TG3_PHY_MII_ADDR;
1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
1051 static int tg3_mdio_init(struct tg3 *tp)
1055 struct phy_device *phydev;
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
1079 tp->mdio_bus->irq[i] = PHY_POLL;
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1086 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1089 i = mdiobus_register(tp->mdio_bus);
1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1093 mdiobus_free(tp->mdio_bus);
1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1111 case TG3_PHY_ID_BCM50610:
1112 case TG3_PHY_ID_BCM50610M:
1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114 PHY_BRCM_RX_REFCLK_UNUSED |
1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1127 case TG3_PHY_ID_RTL8201E:
1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
1143 static void tg3_mdio_fini(struct tg3 *tp)
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1161 tp->last_event_jiffies = jiffies;
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1170 unsigned int delay_cnt;
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1177 if (time_remain < 0)
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
1186 for (i = 0; i < delay_cnt; i++) {
1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1203 tg3_wait_for_event_ack(tp);
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1210 if (!tg3_readphy(tp, MII_BMCR, ®))
1212 if (!tg3_readphy(tp, MII_BMSR, ®))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1217 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1219 if (!tg3_readphy(tp, MII_LPA, ®))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1227 if (!tg3_readphy(tp, MII_STAT1000, ®))
1228 val |= (reg & 0xffff);
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1232 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1238 tg3_generate_fw_event(tp);
1241 static void tg3_link_report(struct tg3 *tp)
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1251 (tp->link_config.active_speed == SPEED_1000 ?
1253 (tp->link_config.active_speed == SPEED_100 ?
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1265 tg3_ump_link_report(tp);
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274 miireg = ADVERTISE_PAUSE_CAP;
1275 else if (flow_ctrl & FLOW_CTRL_TX)
1276 miireg = ADVERTISE_PAUSE_ASYM;
1277 else if (flow_ctrl & FLOW_CTRL_RX)
1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290 miireg = ADVERTISE_1000XPAUSE;
1291 else if (flow_ctrl & FLOW_CTRL_TX)
1292 miireg = ADVERTISE_1000XPSE_ASYM;
1293 else if (flow_ctrl & FLOW_CTRL_RX)
1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1312 if (rmtadv & LPA_1000XPAUSE)
1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1333 autoneg = tp->link_config.autoneg;
1335 if (autoneg == AUTONEG_ENABLE &&
1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1342 flowctrl = tp->link_config.flowctrl;
1344 tp->link_config.active_flowctrl = flowctrl;
1346 if (flowctrl & FLOW_CTRL_RX)
1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1351 if (old_rx_mode != tp->rx_mode)
1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
1354 if (flowctrl & FLOW_CTRL_TX)
1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1359 if (old_tx_mode != tp->tx_mode)
1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
1363 static void tg3_adjust_link(struct net_device *dev)
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1370 spin_lock_bh(&tp->lock);
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1375 oldflowctrl = tp->link_config.active_flowctrl;
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1441 spin_unlock_bh(&tp->lock);
1444 tg3_link_report(tp);
1447 static int tg3_phy_init(struct tg3 *tp)
1449 struct phy_device *phydev;
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1454 /* Bring the PHY back to a known state. */
1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1459 /* Attach the MAC to the PHY. */
1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461 phydev->dev_flags, phydev->interface);
1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1467 /* Mask with MAC supported features. */
1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1474 SUPPORTED_Asym_Pause);
1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1481 SUPPORTED_Asym_Pause);
1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1490 phydev->advertising = phydev->supported;
1495 static void tg3_phy_start(struct tg3 *tp)
1497 struct phy_device *phydev;
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1514 phy_start_aneg(phydev);
1517 static void tg3_phy_stop(struct tg3 *tp)
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1525 static void tg3_phy_fini(struct tg3 *tp)
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1566 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1567 tg3_phy_fet_toggle_apd(tp, enable);
1571 reg = MII_TG3_MISC_SHDW_WREN |
1572 MII_TG3_MISC_SHDW_SCR5_SEL |
1573 MII_TG3_MISC_SHDW_SCR5_LPED |
1574 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1575 MII_TG3_MISC_SHDW_SCR5_SDTL |
1576 MII_TG3_MISC_SHDW_SCR5_C125OE;
1577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1578 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1580 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1583 reg = MII_TG3_MISC_SHDW_WREN |
1584 MII_TG3_MISC_SHDW_APD_SEL |
1585 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1587 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1589 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1592 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1596 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1597 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1603 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1604 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1606 tg3_writephy(tp, MII_TG3_FET_TEST,
1607 ephy | MII_TG3_FET_SHADOW_EN);
1608 if (!tg3_readphy(tp, reg, &phy)) {
1610 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1612 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1613 tg3_writephy(tp, reg, phy);
1615 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1618 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1619 MII_TG3_AUXCTL_SHDWSEL_MISC;
1620 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1621 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1623 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1625 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1626 phy |= MII_TG3_AUXCTL_MISC_WREN;
1627 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1632 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1636 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1639 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1640 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1641 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1642 (val | (1 << 15) | (1 << 4)));
1645 static void tg3_phy_apply_otp(struct tg3 *tp)
1654 /* Enable SM_DSP clock and tx 6dB coding. */
1655 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1656 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1657 MII_TG3_AUXCTL_ACTL_TX_6DB;
1658 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1660 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1661 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1662 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1664 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1665 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1666 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1668 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1669 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1670 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1672 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1675 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1678 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1679 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1680 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1682 /* Turn off SM_DSP clock. */
1683 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1688 static int tg3_wait_macro_done(struct tg3 *tp)
1695 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1696 if ((tmp32 & 0x1000) == 0)
1706 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1708 static const u32 test_pat[4][6] = {
1709 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1710 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1711 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1712 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1716 for (chan = 0; chan < 4; chan++) {
1719 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1720 (chan * 0x2000) | 0x0200);
1721 tg3_writephy(tp, 0x16, 0x0002);
1723 for (i = 0; i < 6; i++)
1724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1727 tg3_writephy(tp, 0x16, 0x0202);
1728 if (tg3_wait_macro_done(tp)) {
1733 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734 (chan * 0x2000) | 0x0200);
1735 tg3_writephy(tp, 0x16, 0x0082);
1736 if (tg3_wait_macro_done(tp)) {
1741 tg3_writephy(tp, 0x16, 0x0802);
1742 if (tg3_wait_macro_done(tp)) {
1747 for (i = 0; i < 6; i += 2) {
1750 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1751 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1752 tg3_wait_macro_done(tp)) {
1758 if (low != test_pat[chan][i] ||
1759 high != test_pat[chan][i+1]) {
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1761 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1762 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1772 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1776 for (chan = 0; chan < 4; chan++) {
1779 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1780 (chan * 0x2000) | 0x0200);
1781 tg3_writephy(tp, 0x16, 0x0002);
1782 for (i = 0; i < 6; i++)
1783 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1784 tg3_writephy(tp, 0x16, 0x0202);
1785 if (tg3_wait_macro_done(tp))
1792 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1794 u32 reg32, phy9_orig;
1795 int retries, do_phy_reset, err;
1801 err = tg3_bmcr_reset(tp);
1807 /* Disable transmitter and interrupt. */
1808 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1812 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1814 /* Set full-duplex, 1000 mbps. */
1815 tg3_writephy(tp, MII_BMCR,
1816 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1818 /* Set to master mode. */
1819 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1822 tg3_writephy(tp, MII_TG3_CTRL,
1823 (MII_TG3_CTRL_AS_MASTER |
1824 MII_TG3_CTRL_ENABLE_AS_MASTER));
1826 /* Enable SM_DSP_CLOCK and 6dB. */
1827 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1829 /* Block the PHY control access. */
1830 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1831 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1833 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1836 } while (--retries);
1838 err = tg3_phy_reset_chanpat(tp);
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1843 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1845 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1846 tg3_writephy(tp, 0x16, 0x0000);
1848 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1850 /* Set Extended packet length bit for jumbo frames */
1851 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1857 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1859 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1868 /* This will reset the tigon3 PHY if there is no valid
1869 * link unless the FORCE argument is non-zero.
1871 static int tg3_phy_reset(struct tg3 *tp)
1877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1880 val = tr32(GRC_MISC_CFG);
1881 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1884 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1885 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1889 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1890 netif_carrier_off(tp->dev);
1891 tg3_link_report(tp);
1894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1897 err = tg3_phy_reset_5703_4_5(tp);
1904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1905 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1906 cpmuctrl = tr32(TG3_CPMU_CTRL);
1907 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1909 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1912 err = tg3_bmcr_reset(tp);
1916 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1919 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1920 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1922 tw32(TG3_CPMU_CTRL, cpmuctrl);
1925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1926 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1929 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1930 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1931 CPMU_LSPD_1000MB_MACCLK_12_5) {
1932 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1934 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1938 tg3_phy_apply_otp(tp);
1940 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1941 tg3_phy_toggle_apd(tp, true);
1943 tg3_phy_toggle_apd(tp, false);
1946 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1947 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1954 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1955 tg3_writephy(tp, 0x1c, 0x8d68);
1956 tg3_writephy(tp, 0x1c, 0x8d68);
1958 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1959 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1962 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1963 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1964 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1965 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1966 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1968 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1972 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1973 tg3_writephy(tp, MII_TG3_TEST1,
1974 MII_TG3_TEST1_TRIM_EN | 0x4);
1976 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1979 /* Set Extended packet length bit (bit 14) on all chips that */
1980 /* support jumbo frames */
1981 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1982 /* Cannot do read-modify-write on 5401 */
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1984 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1996 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1999 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2001 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2005 /* adjust output voltage */
2006 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2009 tg3_phy_toggle_automdix(tp, 1);
2010 tg3_phy_set_wirespeed(tp);
2014 static void tg3_frob_aux_power(struct tg3 *tp)
2016 struct tg3 *tp_peer = tp;
2018 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2024 struct net_device *dev_peer;
2026 dev_peer = pci_get_drvdata(tp->pdev_peer);
2027 /* remove_one() may have been run on the peer. */
2031 tp_peer = netdev_priv(dev_peer);
2034 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2035 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2036 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2040 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2041 (GRC_LCLCTRL_GPIO_OE0 |
2042 GRC_LCLCTRL_GPIO_OE1 |
2043 GRC_LCLCTRL_GPIO_OE2 |
2044 GRC_LCLCTRL_GPIO_OUTPUT0 |
2045 GRC_LCLCTRL_GPIO_OUTPUT1),
2047 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2049 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2050 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2051 GRC_LCLCTRL_GPIO_OE1 |
2052 GRC_LCLCTRL_GPIO_OE2 |
2053 GRC_LCLCTRL_GPIO_OUTPUT0 |
2054 GRC_LCLCTRL_GPIO_OUTPUT1 |
2056 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2058 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2059 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2065 u32 grc_local_ctrl = 0;
2067 if (tp_peer != tp &&
2068 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2071 /* Workaround to prevent overdrawing Amps. */
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2074 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2075 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2076 grc_local_ctrl, 100);
2079 /* On 5753 and variants, GPIO2 cannot be used. */
2080 no_gpio2 = tp->nic_sram_data_cfg &
2081 NIC_SRAM_DATA_CFG_NO_GPIO2;
2083 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2084 GRC_LCLCTRL_GPIO_OE1 |
2085 GRC_LCLCTRL_GPIO_OE2 |
2086 GRC_LCLCTRL_GPIO_OUTPUT1 |
2087 GRC_LCLCTRL_GPIO_OUTPUT2;
2089 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2090 GRC_LCLCTRL_GPIO_OUTPUT2);
2092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2093 grc_local_ctrl, 100);
2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 grc_local_ctrl, 100);
2101 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2102 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2103 grc_local_ctrl, 100);
2107 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2109 if (tp_peer != tp &&
2110 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114 (GRC_LCLCTRL_GPIO_OE1 |
2115 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2117 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118 GRC_LCLCTRL_GPIO_OE1, 100);
2120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121 (GRC_LCLCTRL_GPIO_OE1 |
2122 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2127 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2129 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2131 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2132 if (speed != SPEED_10)
2134 } else if (speed == SPEED_10)
2140 static int tg3_setup_phy(struct tg3 *, int);
2142 #define RESET_KIND_SHUTDOWN 0
2143 #define RESET_KIND_INIT 1
2144 #define RESET_KIND_SUSPEND 2
2146 static void tg3_write_sig_post_reset(struct tg3 *, int);
2147 static int tg3_halt_cpu(struct tg3 *, u32);
2149 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2153 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2155 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2156 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2159 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2160 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2161 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2168 val = tr32(GRC_MISC_CFG);
2169 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2172 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2174 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2177 tg3_writephy(tp, MII_ADVERTISE, 0);
2178 tg3_writephy(tp, MII_BMCR,
2179 BMCR_ANENABLE | BMCR_ANRESTART);
2181 tg3_writephy(tp, MII_TG3_FET_TEST,
2182 phytest | MII_TG3_FET_SHADOW_EN);
2183 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2184 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2186 MII_TG3_FET_SHDW_AUXMODE4,
2189 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2192 } else if (do_low_power) {
2193 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2194 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2196 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2197 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2198 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2199 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2200 MII_TG3_AUXCTL_PCTL_VREG_11V);
2203 /* The PHY should not be powered down on some chips because
2206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2208 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2209 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2212 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2213 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2214 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2215 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2216 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2217 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2220 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2223 /* tp->lock is held. */
2224 static int tg3_nvram_lock(struct tg3 *tp)
2226 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2229 if (tp->nvram_lock_cnt == 0) {
2230 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2231 for (i = 0; i < 8000; i++) {
2232 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2237 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2241 tp->nvram_lock_cnt++;
2246 /* tp->lock is held. */
2247 static void tg3_nvram_unlock(struct tg3 *tp)
2249 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2250 if (tp->nvram_lock_cnt > 0)
2251 tp->nvram_lock_cnt--;
2252 if (tp->nvram_lock_cnt == 0)
2253 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2257 /* tp->lock is held. */
2258 static void tg3_enable_nvram_access(struct tg3 *tp)
2260 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2261 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2262 u32 nvaccess = tr32(NVRAM_ACCESS);
2264 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2268 /* tp->lock is held. */
2269 static void tg3_disable_nvram_access(struct tg3 *tp)
2271 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2272 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2273 u32 nvaccess = tr32(NVRAM_ACCESS);
2275 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2279 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2280 u32 offset, u32 *val)
2285 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2288 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2289 EEPROM_ADDR_DEVID_MASK |
2291 tw32(GRC_EEPROM_ADDR,
2293 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2294 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2295 EEPROM_ADDR_ADDR_MASK) |
2296 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2298 for (i = 0; i < 1000; i++) {
2299 tmp = tr32(GRC_EEPROM_ADDR);
2301 if (tmp & EEPROM_ADDR_COMPLETE)
2305 if (!(tmp & EEPROM_ADDR_COMPLETE))
2308 tmp = tr32(GRC_EEPROM_DATA);
2311 * The data will always be opposite the native endian
2312 * format. Perform a blind byteswap to compensate.
2319 #define NVRAM_CMD_TIMEOUT 10000
2321 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2325 tw32(NVRAM_CMD, nvram_cmd);
2326 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2328 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2334 if (i == NVRAM_CMD_TIMEOUT)
2340 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2342 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2343 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2344 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2345 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2346 (tp->nvram_jedecnum == JEDEC_ATMEL))
2348 addr = ((addr / tp->nvram_pagesize) <<
2349 ATMEL_AT45DB0X1B_PAGE_POS) +
2350 (addr % tp->nvram_pagesize);
2355 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2357 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2358 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2359 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2360 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2361 (tp->nvram_jedecnum == JEDEC_ATMEL))
2363 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2364 tp->nvram_pagesize) +
2365 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2370 /* NOTE: Data read in from NVRAM is byteswapped according to
2371 * the byteswapping settings for all other register accesses.
2372 * tg3 devices are BE devices, so on a BE machine, the data
2373 * returned will be exactly as it is seen in NVRAM. On a LE
2374 * machine, the 32-bit value will be byteswapped.
2376 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2380 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2381 return tg3_nvram_read_using_eeprom(tp, offset, val);
2383 offset = tg3_nvram_phys_addr(tp, offset);
2385 if (offset > NVRAM_ADDR_MSK)
2388 ret = tg3_nvram_lock(tp);
2392 tg3_enable_nvram_access(tp);
2394 tw32(NVRAM_ADDR, offset);
2395 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2396 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2399 *val = tr32(NVRAM_RDDATA);
2401 tg3_disable_nvram_access(tp);
2403 tg3_nvram_unlock(tp);
2408 /* Ensures NVRAM data is in bytestream format. */
2409 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2412 int res = tg3_nvram_read(tp, offset, &v);
2414 *val = cpu_to_be32(v);
2418 /* tp->lock is held. */
2419 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2421 u32 addr_high, addr_low;
2424 addr_high = ((tp->dev->dev_addr[0] << 8) |
2425 tp->dev->dev_addr[1]);
2426 addr_low = ((tp->dev->dev_addr[2] << 24) |
2427 (tp->dev->dev_addr[3] << 16) |
2428 (tp->dev->dev_addr[4] << 8) |
2429 (tp->dev->dev_addr[5] << 0));
2430 for (i = 0; i < 4; i++) {
2431 if (i == 1 && skip_mac_1)
2433 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2434 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2439 for (i = 0; i < 12; i++) {
2440 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2441 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2445 addr_high = (tp->dev->dev_addr[0] +
2446 tp->dev->dev_addr[1] +
2447 tp->dev->dev_addr[2] +
2448 tp->dev->dev_addr[3] +
2449 tp->dev->dev_addr[4] +
2450 tp->dev->dev_addr[5]) &
2451 TX_BACKOFF_SEED_MASK;
2452 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2455 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2458 bool device_should_wake, do_low_power;
2460 /* Make sure register accesses (indirect or otherwise)
2461 * will function correctly.
2463 pci_write_config_dword(tp->pdev,
2464 TG3PCI_MISC_HOST_CTRL,
2465 tp->misc_host_ctrl);
2469 pci_enable_wake(tp->pdev, state, false);
2470 pci_set_power_state(tp->pdev, PCI_D0);
2472 /* Switch out of Vaux if it is a NIC */
2473 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2474 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2484 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2485 tp->dev->name, state);
2489 /* Restore the CLKREQ setting. */
2490 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2493 pci_read_config_word(tp->pdev,
2494 tp->pcie_cap + PCI_EXP_LNKCTL,
2496 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2497 pci_write_config_word(tp->pdev,
2498 tp->pcie_cap + PCI_EXP_LNKCTL,
2502 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2503 tw32(TG3PCI_MISC_HOST_CTRL,
2504 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2506 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2507 device_may_wakeup(&tp->pdev->dev) &&
2508 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2510 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2511 do_low_power = false;
2512 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2513 !tp->link_config.phy_is_low_power) {
2514 struct phy_device *phydev;
2515 u32 phyid, advertising;
2517 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2519 tp->link_config.phy_is_low_power = 1;
2521 tp->link_config.orig_speed = phydev->speed;
2522 tp->link_config.orig_duplex = phydev->duplex;
2523 tp->link_config.orig_autoneg = phydev->autoneg;
2524 tp->link_config.orig_advertising = phydev->advertising;
2526 advertising = ADVERTISED_TP |
2528 ADVERTISED_Autoneg |
2529 ADVERTISED_10baseT_Half;
2531 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2532 device_should_wake) {
2533 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full |
2537 ADVERTISED_10baseT_Full;
2539 advertising |= ADVERTISED_10baseT_Full;
2542 phydev->advertising = advertising;
2544 phy_start_aneg(phydev);
2546 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2547 if (phyid != TG3_PHY_ID_BCMAC131) {
2548 phyid &= TG3_PHY_OUI_MASK;
2549 if (phyid == TG3_PHY_OUI_1 ||
2550 phyid == TG3_PHY_OUI_2 ||
2551 phyid == TG3_PHY_OUI_3)
2552 do_low_power = true;
2556 do_low_power = true;
2558 if (tp->link_config.phy_is_low_power == 0) {
2559 tp->link_config.phy_is_low_power = 1;
2560 tp->link_config.orig_speed = tp->link_config.speed;
2561 tp->link_config.orig_duplex = tp->link_config.duplex;
2562 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2565 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2566 tp->link_config.speed = SPEED_10;
2567 tp->link_config.duplex = DUPLEX_HALF;
2568 tp->link_config.autoneg = AUTONEG_ENABLE;
2569 tg3_setup_phy(tp, 0);
2573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2576 val = tr32(GRC_VCPU_EXT_CTRL);
2577 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2578 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2582 for (i = 0; i < 200; i++) {
2583 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2584 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2589 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2590 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2591 WOL_DRV_STATE_SHUTDOWN |
2595 if (device_should_wake) {
2598 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2600 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2604 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2605 mac_mode = MAC_MODE_PORT_MODE_GMII;
2607 mac_mode = MAC_MODE_PORT_MODE_MII;
2609 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2610 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2612 u32 speed = (tp->tg3_flags &
2613 TG3_FLAG_WOL_SPEED_100MB) ?
2614 SPEED_100 : SPEED_10;
2615 if (tg3_5700_link_polarity(tp, speed))
2616 mac_mode |= MAC_MODE_LINK_POLARITY;
2618 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2621 mac_mode = MAC_MODE_PORT_MODE_TBI;
2624 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2625 tw32(MAC_LED_CTRL, tp->led_ctrl);
2627 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2628 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2629 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2630 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2631 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2632 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2634 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2635 mac_mode |= tp->mac_mode &
2636 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2637 if (mac_mode & MAC_MODE_APE_TX_EN)
2638 mac_mode |= MAC_MODE_TDE_ENABLE;
2641 tw32_f(MAC_MODE, mac_mode);
2644 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2648 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2649 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2653 base_val = tp->pci_clock_ctrl;
2654 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2655 CLOCK_CTRL_TXCLK_DISABLE);
2657 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2658 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2659 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2660 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2663 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2664 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2665 u32 newbits1, newbits2;
2667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2668 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2669 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2670 CLOCK_CTRL_TXCLK_DISABLE |
2672 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2673 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2674 newbits1 = CLOCK_CTRL_625_CORE;
2675 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2677 newbits1 = CLOCK_CTRL_ALTCLK;
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2681 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2684 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2687 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2692 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2693 CLOCK_CTRL_TXCLK_DISABLE |
2694 CLOCK_CTRL_44MHZ_CORE);
2696 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2699 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2700 tp->pci_clock_ctrl | newbits3, 40);
2704 if (!(device_should_wake) &&
2705 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2706 tg3_power_down_phy(tp, do_low_power);
2708 tg3_frob_aux_power(tp);
2710 /* Workaround for unstable PLL clock */
2711 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2712 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2713 u32 val = tr32(0x7d00);
2715 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2717 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2720 err = tg3_nvram_lock(tp);
2721 tg3_halt_cpu(tp, RX_CPU_BASE);
2723 tg3_nvram_unlock(tp);
2727 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2729 if (device_should_wake)
2730 pci_enable_wake(tp->pdev, state, true);
2732 /* Finally, set the new power state. */
2733 pci_set_power_state(tp->pdev, state);
2738 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2740 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2741 case MII_TG3_AUX_STAT_10HALF:
2743 *duplex = DUPLEX_HALF;
2746 case MII_TG3_AUX_STAT_10FULL:
2748 *duplex = DUPLEX_FULL;
2751 case MII_TG3_AUX_STAT_100HALF:
2753 *duplex = DUPLEX_HALF;
2756 case MII_TG3_AUX_STAT_100FULL:
2758 *duplex = DUPLEX_FULL;
2761 case MII_TG3_AUX_STAT_1000HALF:
2762 *speed = SPEED_1000;
2763 *duplex = DUPLEX_HALF;
2766 case MII_TG3_AUX_STAT_1000FULL:
2767 *speed = SPEED_1000;
2768 *duplex = DUPLEX_FULL;
2772 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2773 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2775 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2779 *speed = SPEED_INVALID;
2780 *duplex = DUPLEX_INVALID;
2785 static void tg3_phy_copper_begin(struct tg3 *tp)
2790 if (tp->link_config.phy_is_low_power) {
2791 /* Entering low power mode. Disable gigabit and
2792 * 100baseT advertisements.
2794 tg3_writephy(tp, MII_TG3_CTRL, 0);
2796 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2797 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2798 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2799 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2801 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2802 } else if (tp->link_config.speed == SPEED_INVALID) {
2803 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2804 tp->link_config.advertising &=
2805 ~(ADVERTISED_1000baseT_Half |
2806 ADVERTISED_1000baseT_Full);
2808 new_adv = ADVERTISE_CSMA;
2809 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2810 new_adv |= ADVERTISE_10HALF;
2811 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2812 new_adv |= ADVERTISE_10FULL;
2813 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2814 new_adv |= ADVERTISE_100HALF;
2815 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2816 new_adv |= ADVERTISE_100FULL;
2818 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2820 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2822 if (tp->link_config.advertising &
2823 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2825 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2826 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2827 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2828 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2829 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2830 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2831 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2832 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2833 MII_TG3_CTRL_ENABLE_AS_MASTER);
2834 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2836 tg3_writephy(tp, MII_TG3_CTRL, 0);
2839 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2840 new_adv |= ADVERTISE_CSMA;
2842 /* Asking for a specific link mode. */
2843 if (tp->link_config.speed == SPEED_1000) {
2844 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2846 if (tp->link_config.duplex == DUPLEX_FULL)
2847 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2849 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2850 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2851 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2852 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2853 MII_TG3_CTRL_ENABLE_AS_MASTER);
2855 if (tp->link_config.speed == SPEED_100) {
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 new_adv |= ADVERTISE_100FULL;
2859 new_adv |= ADVERTISE_100HALF;
2861 if (tp->link_config.duplex == DUPLEX_FULL)
2862 new_adv |= ADVERTISE_10FULL;
2864 new_adv |= ADVERTISE_10HALF;
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2874 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2875 tp->link_config.speed != SPEED_INVALID) {
2876 u32 bmcr, orig_bmcr;
2878 tp->link_config.active_speed = tp->link_config.speed;
2879 tp->link_config.active_duplex = tp->link_config.duplex;
2882 switch (tp->link_config.speed) {
2888 bmcr |= BMCR_SPEED100;
2892 bmcr |= TG3_BMCR_SPEED1000;
2896 if (tp->link_config.duplex == DUPLEX_FULL)
2897 bmcr |= BMCR_FULLDPLX;
2899 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2900 (bmcr != orig_bmcr)) {
2901 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2902 for (i = 0; i < 1500; i++) {
2906 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2907 tg3_readphy(tp, MII_BMSR, &tmp))
2909 if (!(tmp & BMSR_LSTATUS)) {
2914 tg3_writephy(tp, MII_BMCR, bmcr);
2918 tg3_writephy(tp, MII_BMCR,
2919 BMCR_ANENABLE | BMCR_ANRESTART);
2923 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2927 /* Turn off tap power management. */
2928 /* Set Extended packet length bit */
2929 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2931 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2932 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2934 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2935 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2951 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2953 u32 adv_reg, all_mask = 0;
2955 if (mask & ADVERTISED_10baseT_Half)
2956 all_mask |= ADVERTISE_10HALF;
2957 if (mask & ADVERTISED_10baseT_Full)
2958 all_mask |= ADVERTISE_10FULL;
2959 if (mask & ADVERTISED_100baseT_Half)
2960 all_mask |= ADVERTISE_100HALF;
2961 if (mask & ADVERTISED_100baseT_Full)
2962 all_mask |= ADVERTISE_100FULL;
2964 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2967 if ((adv_reg & all_mask) != all_mask)
2969 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2973 if (mask & ADVERTISED_1000baseT_Half)
2974 all_mask |= ADVERTISE_1000HALF;
2975 if (mask & ADVERTISED_1000baseT_Full)
2976 all_mask |= ADVERTISE_1000FULL;
2978 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2981 if ((tg3_ctrl & all_mask) != all_mask)
2987 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2991 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2994 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2995 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2997 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2998 if (curadv != reqadv)
3001 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3002 tg3_readphy(tp, MII_LPA, rmtadv);
3004 /* Reprogram the advertisement register, even if it
3005 * does not affect the current link. If the link
3006 * gets renegotiated in the future, we can save an
3007 * additional renegotiation cycle by advertising
3008 * it correctly in the first place.
3010 if (curadv != reqadv) {
3011 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3012 ADVERTISE_PAUSE_ASYM);
3013 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3020 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3022 int current_link_up;
3024 u32 lcl_adv, rmt_adv;
3032 (MAC_STATUS_SYNC_CHANGED |
3033 MAC_STATUS_CFG_CHANGED |
3034 MAC_STATUS_MI_COMPLETION |
3035 MAC_STATUS_LNKSTATE_CHANGED));
3038 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3040 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3044 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3046 /* Some third-party PHYs need to be reset on link going
3049 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3052 netif_carrier_ok(tp->dev)) {
3053 tg3_readphy(tp, MII_BMSR, &bmsr);
3054 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3055 !(bmsr & BMSR_LSTATUS))
3061 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3062 tg3_readphy(tp, MII_BMSR, &bmsr);
3063 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3064 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3067 if (!(bmsr & BMSR_LSTATUS)) {
3068 err = tg3_init_5401phy_dsp(tp);
3072 tg3_readphy(tp, MII_BMSR, &bmsr);
3073 for (i = 0; i < 1000; i++) {
3075 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3076 (bmsr & BMSR_LSTATUS)) {
3082 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3083 !(bmsr & BMSR_LSTATUS) &&
3084 tp->link_config.active_speed == SPEED_1000) {
3085 err = tg3_phy_reset(tp);
3087 err = tg3_init_5401phy_dsp(tp);
3092 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3093 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3094 /* 5701 {A0,B0} CRC bug workaround */
3095 tg3_writephy(tp, 0x15, 0x0a75);
3096 tg3_writephy(tp, 0x1c, 0x8c68);
3097 tg3_writephy(tp, 0x1c, 0x8d68);
3098 tg3_writephy(tp, 0x1c, 0x8c68);
3101 /* Clear pending interrupts... */
3102 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3103 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3105 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3106 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3107 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3108 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3112 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3113 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3114 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3116 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3119 current_link_up = 0;
3120 current_speed = SPEED_INVALID;
3121 current_duplex = DUPLEX_INVALID;
3123 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3126 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3127 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3128 if (!(val & (1 << 10))) {
3130 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3136 for (i = 0; i < 100; i++) {
3137 tg3_readphy(tp, MII_BMSR, &bmsr);
3138 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3139 (bmsr & BMSR_LSTATUS))
3144 if (bmsr & BMSR_LSTATUS) {
3147 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3148 for (i = 0; i < 2000; i++) {
3150 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3155 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3160 for (i = 0; i < 200; i++) {
3161 tg3_readphy(tp, MII_BMCR, &bmcr);
3162 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3164 if (bmcr && bmcr != 0x7fff)
3172 tp->link_config.active_speed = current_speed;
3173 tp->link_config.active_duplex = current_duplex;
3175 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3176 if ((bmcr & BMCR_ANENABLE) &&
3177 tg3_copper_is_advertising_all(tp,
3178 tp->link_config.advertising)) {
3179 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3181 current_link_up = 1;
3184 if (!(bmcr & BMCR_ANENABLE) &&
3185 tp->link_config.speed == current_speed &&
3186 tp->link_config.duplex == current_duplex &&
3187 tp->link_config.flowctrl ==
3188 tp->link_config.active_flowctrl) {
3189 current_link_up = 1;
3193 if (current_link_up == 1 &&
3194 tp->link_config.active_duplex == DUPLEX_FULL)
3195 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3199 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3202 tg3_phy_copper_begin(tp);
3204 tg3_readphy(tp, MII_BMSR, &tmp);
3205 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3206 (tmp & BMSR_LSTATUS))
3207 current_link_up = 1;
3210 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3211 if (current_link_up == 1) {
3212 if (tp->link_config.active_speed == SPEED_100 ||
3213 tp->link_config.active_speed == SPEED_10)
3214 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3216 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3217 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3218 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3220 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3222 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3223 if (tp->link_config.active_duplex == DUPLEX_HALF)
3224 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3227 if (current_link_up == 1 &&
3228 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3229 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3231 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3234 /* ??? Without this setting Netgear GA302T PHY does not
3235 * ??? send/receive packets...
3237 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3238 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3239 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3240 tw32_f(MAC_MI_MODE, tp->mi_mode);
3244 tw32_f(MAC_MODE, tp->mac_mode);
3247 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3248 /* Polled via timer. */
3249 tw32_f(MAC_EVENT, 0);
3251 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3256 current_link_up == 1 &&
3257 tp->link_config.active_speed == SPEED_1000 &&
3258 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3259 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3262 (MAC_STATUS_SYNC_CHANGED |
3263 MAC_STATUS_CFG_CHANGED));
3266 NIC_SRAM_FIRMWARE_MBOX,
3267 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3270 /* Prevent send BD corruption. */
3271 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3272 u16 oldlnkctl, newlnkctl;
3274 pci_read_config_word(tp->pdev,
3275 tp->pcie_cap + PCI_EXP_LNKCTL,
3277 if (tp->link_config.active_speed == SPEED_100 ||
3278 tp->link_config.active_speed == SPEED_10)
3279 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3281 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3282 if (newlnkctl != oldlnkctl)
3283 pci_write_config_word(tp->pdev,
3284 tp->pcie_cap + PCI_EXP_LNKCTL,
3288 if (current_link_up != netif_carrier_ok(tp->dev)) {
3289 if (current_link_up)
3290 netif_carrier_on(tp->dev);
3292 netif_carrier_off(tp->dev);
3293 tg3_link_report(tp);
3299 struct tg3_fiber_aneginfo {
3301 #define ANEG_STATE_UNKNOWN 0
3302 #define ANEG_STATE_AN_ENABLE 1
3303 #define ANEG_STATE_RESTART_INIT 2
3304 #define ANEG_STATE_RESTART 3
3305 #define ANEG_STATE_DISABLE_LINK_OK 4
3306 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3307 #define ANEG_STATE_ABILITY_DETECT 6
3308 #define ANEG_STATE_ACK_DETECT_INIT 7
3309 #define ANEG_STATE_ACK_DETECT 8
3310 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3311 #define ANEG_STATE_COMPLETE_ACK 10
3312 #define ANEG_STATE_IDLE_DETECT_INIT 11
3313 #define ANEG_STATE_IDLE_DETECT 12
3314 #define ANEG_STATE_LINK_OK 13
3315 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3316 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3319 #define MR_AN_ENABLE 0x00000001
3320 #define MR_RESTART_AN 0x00000002
3321 #define MR_AN_COMPLETE 0x00000004
3322 #define MR_PAGE_RX 0x00000008
3323 #define MR_NP_LOADED 0x00000010
3324 #define MR_TOGGLE_TX 0x00000020
3325 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3326 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3327 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3328 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3329 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3330 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3331 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3332 #define MR_TOGGLE_RX 0x00002000
3333 #define MR_NP_RX 0x00004000
3335 #define MR_LINK_OK 0x80000000
3337 unsigned long link_time, cur_time;
3339 u32 ability_match_cfg;
3340 int ability_match_count;
3342 char ability_match, idle_match, ack_match;
3344 u32 txconfig, rxconfig;
3345 #define ANEG_CFG_NP 0x00000080
3346 #define ANEG_CFG_ACK 0x00000040
3347 #define ANEG_CFG_RF2 0x00000020
3348 #define ANEG_CFG_RF1 0x00000010
3349 #define ANEG_CFG_PS2 0x00000001
3350 #define ANEG_CFG_PS1 0x00008000
3351 #define ANEG_CFG_HD 0x00004000
3352 #define ANEG_CFG_FD 0x00002000
3353 #define ANEG_CFG_INVAL 0x00001f06
3358 #define ANEG_TIMER_ENAB 2
3359 #define ANEG_FAILED -1
3361 #define ANEG_STATE_SETTLE_TIME 10000
3363 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3364 struct tg3_fiber_aneginfo *ap)
3367 unsigned long delta;
3371 if (ap->state == ANEG_STATE_UNKNOWN) {
3375 ap->ability_match_cfg = 0;
3376 ap->ability_match_count = 0;
3377 ap->ability_match = 0;
3383 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3384 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3386 if (rx_cfg_reg != ap->ability_match_cfg) {
3387 ap->ability_match_cfg = rx_cfg_reg;
3388 ap->ability_match = 0;
3389 ap->ability_match_count = 0;
3391 if (++ap->ability_match_count > 1) {
3392 ap->ability_match = 1;
3393 ap->ability_match_cfg = rx_cfg_reg;
3396 if (rx_cfg_reg & ANEG_CFG_ACK)
3404 ap->ability_match_cfg = 0;
3405 ap->ability_match_count = 0;
3406 ap->ability_match = 0;
3412 ap->rxconfig = rx_cfg_reg;
3416 case ANEG_STATE_UNKNOWN:
3417 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3418 ap->state = ANEG_STATE_AN_ENABLE;
3421 case ANEG_STATE_AN_ENABLE:
3422 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3423 if (ap->flags & MR_AN_ENABLE) {
3426 ap->ability_match_cfg = 0;
3427 ap->ability_match_count = 0;
3428 ap->ability_match = 0;
3432 ap->state = ANEG_STATE_RESTART_INIT;
3434 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3438 case ANEG_STATE_RESTART_INIT:
3439 ap->link_time = ap->cur_time;
3440 ap->flags &= ~(MR_NP_LOADED);
3442 tw32(MAC_TX_AUTO_NEG, 0);
3443 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3444 tw32_f(MAC_MODE, tp->mac_mode);
3447 ret = ANEG_TIMER_ENAB;
3448 ap->state = ANEG_STATE_RESTART;
3451 case ANEG_STATE_RESTART:
3452 delta = ap->cur_time - ap->link_time;
3453 if (delta > ANEG_STATE_SETTLE_TIME) {
3454 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3456 ret = ANEG_TIMER_ENAB;
3460 case ANEG_STATE_DISABLE_LINK_OK:
3464 case ANEG_STATE_ABILITY_DETECT_INIT:
3465 ap->flags &= ~(MR_TOGGLE_TX);
3466 ap->txconfig = ANEG_CFG_FD;
3467 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3468 if (flowctrl & ADVERTISE_1000XPAUSE)
3469 ap->txconfig |= ANEG_CFG_PS1;
3470 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3471 ap->txconfig |= ANEG_CFG_PS2;
3472 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3473 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3474 tw32_f(MAC_MODE, tp->mac_mode);
3477 ap->state = ANEG_STATE_ABILITY_DETECT;
3480 case ANEG_STATE_ABILITY_DETECT:
3481 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3482 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3486 case ANEG_STATE_ACK_DETECT_INIT:
3487 ap->txconfig |= ANEG_CFG_ACK;
3488 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3489 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490 tw32_f(MAC_MODE, tp->mac_mode);
3493 ap->state = ANEG_STATE_ACK_DETECT;
3496 case ANEG_STATE_ACK_DETECT:
3497 if (ap->ack_match != 0) {
3498 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3499 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3500 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3502 ap->state = ANEG_STATE_AN_ENABLE;
3504 } else if (ap->ability_match != 0 &&
3505 ap->rxconfig == 0) {
3506 ap->state = ANEG_STATE_AN_ENABLE;
3510 case ANEG_STATE_COMPLETE_ACK_INIT:
3511 if (ap->rxconfig & ANEG_CFG_INVAL) {
3515 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3516 MR_LP_ADV_HALF_DUPLEX |
3517 MR_LP_ADV_SYM_PAUSE |
3518 MR_LP_ADV_ASYM_PAUSE |
3519 MR_LP_ADV_REMOTE_FAULT1 |
3520 MR_LP_ADV_REMOTE_FAULT2 |
3521 MR_LP_ADV_NEXT_PAGE |
3524 if (ap->rxconfig & ANEG_CFG_FD)
3525 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3526 if (ap->rxconfig & ANEG_CFG_HD)
3527 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3528 if (ap->rxconfig & ANEG_CFG_PS1)
3529 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3530 if (ap->rxconfig & ANEG_CFG_PS2)
3531 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3532 if (ap->rxconfig & ANEG_CFG_RF1)
3533 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3534 if (ap->rxconfig & ANEG_CFG_RF2)
3535 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3536 if (ap->rxconfig & ANEG_CFG_NP)
3537 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3539 ap->link_time = ap->cur_time;
3541 ap->flags ^= (MR_TOGGLE_TX);
3542 if (ap->rxconfig & 0x0008)
3543 ap->flags |= MR_TOGGLE_RX;
3544 if (ap->rxconfig & ANEG_CFG_NP)
3545 ap->flags |= MR_NP_RX;
3546 ap->flags |= MR_PAGE_RX;
3548 ap->state = ANEG_STATE_COMPLETE_ACK;
3549 ret = ANEG_TIMER_ENAB;
3552 case ANEG_STATE_COMPLETE_ACK:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3561 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3563 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3564 !(ap->flags & MR_NP_RX)) {
3565 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3573 case ANEG_STATE_IDLE_DETECT_INIT:
3574 ap->link_time = ap->cur_time;
3575 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3576 tw32_f(MAC_MODE, tp->mac_mode);
3579 ap->state = ANEG_STATE_IDLE_DETECT;
3580 ret = ANEG_TIMER_ENAB;
3583 case ANEG_STATE_IDLE_DETECT:
3584 if (ap->ability_match != 0 &&
3585 ap->rxconfig == 0) {
3586 ap->state = ANEG_STATE_AN_ENABLE;
3589 delta = ap->cur_time - ap->link_time;
3590 if (delta > ANEG_STATE_SETTLE_TIME) {
3591 /* XXX another gem from the Broadcom driver :( */
3592 ap->state = ANEG_STATE_LINK_OK;
3596 case ANEG_STATE_LINK_OK:
3597 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3601 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3602 /* ??? unimplemented */
3605 case ANEG_STATE_NEXT_PAGE_WAIT:
3606 /* ??? unimplemented */
3617 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3620 struct tg3_fiber_aneginfo aninfo;
3621 int status = ANEG_FAILED;
3625 tw32_f(MAC_TX_AUTO_NEG, 0);
3627 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3628 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3631 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3634 memset(&aninfo, 0, sizeof(aninfo));
3635 aninfo.flags |= MR_AN_ENABLE;
3636 aninfo.state = ANEG_STATE_UNKNOWN;
3637 aninfo.cur_time = 0;
3639 while (++tick < 195000) {
3640 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3641 if (status == ANEG_DONE || status == ANEG_FAILED)
3647 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3648 tw32_f(MAC_MODE, tp->mac_mode);
3651 *txflags = aninfo.txconfig;
3652 *rxflags = aninfo.flags;
3654 if (status == ANEG_DONE &&
3655 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3656 MR_LP_ADV_FULL_DUPLEX)))
3662 static void tg3_init_bcm8002(struct tg3 *tp)
3664 u32 mac_status = tr32(MAC_STATUS);
3667 /* Reset when initting first time or we have a link. */
3668 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3669 !(mac_status & MAC_STATUS_PCS_SYNCED))
3672 /* Set PLL lock range. */
3673 tg3_writephy(tp, 0x16, 0x8007);
3676 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3678 /* Wait for reset to complete. */
3679 /* XXX schedule_timeout() ... */
3680 for (i = 0; i < 500; i++)
3683 /* Config mode; select PMA/Ch 1 regs. */
3684 tg3_writephy(tp, 0x10, 0x8411);
3686 /* Enable auto-lock and comdet, select txclk for tx. */
3687 tg3_writephy(tp, 0x11, 0x0a10);
3689 tg3_writephy(tp, 0x18, 0x00a0);
3690 tg3_writephy(tp, 0x16, 0x41ff);
3692 /* Assert and deassert POR. */
3693 tg3_writephy(tp, 0x13, 0x0400);
3695 tg3_writephy(tp, 0x13, 0x0000);
3697 tg3_writephy(tp, 0x11, 0x0a50);
3699 tg3_writephy(tp, 0x11, 0x0a10);
3701 /* Wait for signal to stabilize */
3702 /* XXX schedule_timeout() ... */
3703 for (i = 0; i < 15000; i++)
3706 /* Deselect the channel register so we can read the PHYID
3709 tg3_writephy(tp, 0x10, 0x8011);
3712 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3715 u32 sg_dig_ctrl, sg_dig_status;
3716 u32 serdes_cfg, expected_sg_dig_ctrl;
3717 int workaround, port_a;
3718 int current_link_up;
3721 expected_sg_dig_ctrl = 0;
3724 current_link_up = 0;
3726 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3727 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3729 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3732 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3733 /* preserve bits 20-23 for voltage regulator */
3734 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3737 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3739 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3740 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3742 u32 val = serdes_cfg;
3748 tw32_f(MAC_SERDES_CFG, val);
3751 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3753 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3754 tg3_setup_flow_control(tp, 0, 0);
3755 current_link_up = 1;
3760 /* Want auto-negotiation. */
3761 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3763 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3764 if (flowctrl & ADVERTISE_1000XPAUSE)
3765 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3766 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3767 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3769 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3770 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3771 tp->serdes_counter &&
3772 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3773 MAC_STATUS_RCVD_CFG)) ==
3774 MAC_STATUS_PCS_SYNCED)) {
3775 tp->serdes_counter--;
3776 current_link_up = 1;
3781 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3782 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3784 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3786 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3787 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3788 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3789 MAC_STATUS_SIGNAL_DET)) {
3790 sg_dig_status = tr32(SG_DIG_STATUS);
3791 mac_status = tr32(MAC_STATUS);
3793 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3794 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3795 u32 local_adv = 0, remote_adv = 0;
3797 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3798 local_adv |= ADVERTISE_1000XPAUSE;
3799 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3800 local_adv |= ADVERTISE_1000XPSE_ASYM;
3802 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3803 remote_adv |= LPA_1000XPAUSE;
3804 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3805 remote_adv |= LPA_1000XPAUSE_ASYM;
3807 tg3_setup_flow_control(tp, local_adv, remote_adv);
3808 current_link_up = 1;
3809 tp->serdes_counter = 0;
3810 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3811 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3812 if (tp->serdes_counter)
3813 tp->serdes_counter--;
3816 u32 val = serdes_cfg;
3823 tw32_f(MAC_SERDES_CFG, val);
3826 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3829 /* Link parallel detection - link is up */
3830 /* only if we have PCS_SYNC and not */
3831 /* receiving config code words */
3832 mac_status = tr32(MAC_STATUS);
3833 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3834 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3835 tg3_setup_flow_control(tp, 0, 0);
3836 current_link_up = 1;
3838 TG3_FLG2_PARALLEL_DETECT;
3839 tp->serdes_counter =
3840 SERDES_PARALLEL_DET_TIMEOUT;
3842 goto restart_autoneg;
3846 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3847 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3851 return current_link_up;
3854 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3856 int current_link_up = 0;
3858 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3861 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3862 u32 txflags, rxflags;
3865 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3866 u32 local_adv = 0, remote_adv = 0;
3868 if (txflags & ANEG_CFG_PS1)
3869 local_adv |= ADVERTISE_1000XPAUSE;
3870 if (txflags & ANEG_CFG_PS2)
3871 local_adv |= ADVERTISE_1000XPSE_ASYM;
3873 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3874 remote_adv |= LPA_1000XPAUSE;
3875 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3876 remote_adv |= LPA_1000XPAUSE_ASYM;
3878 tg3_setup_flow_control(tp, local_adv, remote_adv);
3880 current_link_up = 1;
3882 for (i = 0; i < 30; i++) {
3885 (MAC_STATUS_SYNC_CHANGED |
3886 MAC_STATUS_CFG_CHANGED));
3888 if ((tr32(MAC_STATUS) &
3889 (MAC_STATUS_SYNC_CHANGED |
3890 MAC_STATUS_CFG_CHANGED)) == 0)
3894 mac_status = tr32(MAC_STATUS);
3895 if (current_link_up == 0 &&
3896 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3897 !(mac_status & MAC_STATUS_RCVD_CFG))
3898 current_link_up = 1;
3900 tg3_setup_flow_control(tp, 0, 0);
3902 /* Forcing 1000FD link up. */
3903 current_link_up = 1;
3905 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3908 tw32_f(MAC_MODE, tp->mac_mode);
3913 return current_link_up;
3916 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3919 u16 orig_active_speed;
3920 u8 orig_active_duplex;
3922 int current_link_up;
3925 orig_pause_cfg = tp->link_config.active_flowctrl;
3926 orig_active_speed = tp->link_config.active_speed;
3927 orig_active_duplex = tp->link_config.active_duplex;
3929 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3930 netif_carrier_ok(tp->dev) &&
3931 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3932 mac_status = tr32(MAC_STATUS);
3933 mac_status &= (MAC_STATUS_PCS_SYNCED |
3934 MAC_STATUS_SIGNAL_DET |
3935 MAC_STATUS_CFG_CHANGED |
3936 MAC_STATUS_RCVD_CFG);
3937 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3938 MAC_STATUS_SIGNAL_DET)) {
3939 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3940 MAC_STATUS_CFG_CHANGED));
3945 tw32_f(MAC_TX_AUTO_NEG, 0);
3947 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3948 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3949 tw32_f(MAC_MODE, tp->mac_mode);
3952 if (tp->phy_id == PHY_ID_BCM8002)
3953 tg3_init_bcm8002(tp);
3955 /* Enable link change event even when serdes polling. */
3956 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3959 current_link_up = 0;
3960 mac_status = tr32(MAC_STATUS);
3962 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3963 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3965 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3967 tp->napi[0].hw_status->status =
3968 (SD_STATUS_UPDATED |
3969 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3971 for (i = 0; i < 100; i++) {
3972 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3973 MAC_STATUS_CFG_CHANGED));
3975 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3976 MAC_STATUS_CFG_CHANGED |
3977 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3981 mac_status = tr32(MAC_STATUS);
3982 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3983 current_link_up = 0;
3984 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3985 tp->serdes_counter == 0) {
3986 tw32_f(MAC_MODE, (tp->mac_mode |
3987 MAC_MODE_SEND_CONFIGS));
3989 tw32_f(MAC_MODE, tp->mac_mode);
3993 if (current_link_up == 1) {
3994 tp->link_config.active_speed = SPEED_1000;
3995 tp->link_config.active_duplex = DUPLEX_FULL;
3996 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3997 LED_CTRL_LNKLED_OVERRIDE |
3998 LED_CTRL_1000MBPS_ON));
4000 tp->link_config.active_speed = SPEED_INVALID;
4001 tp->link_config.active_duplex = DUPLEX_INVALID;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_TRAFFIC_OVERRIDE));
4007 if (current_link_up != netif_carrier_ok(tp->dev)) {
4008 if (current_link_up)
4009 netif_carrier_on(tp->dev);
4011 netif_carrier_off(tp->dev);
4012 tg3_link_report(tp);
4014 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4015 if (orig_pause_cfg != now_pause_cfg ||
4016 orig_active_speed != tp->link_config.active_speed ||
4017 orig_active_duplex != tp->link_config.active_duplex)
4018 tg3_link_report(tp);
4024 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4026 int current_link_up, err = 0;
4030 u32 local_adv, remote_adv;
4032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4033 tw32_f(MAC_MODE, tp->mac_mode);
4039 (MAC_STATUS_SYNC_CHANGED |
4040 MAC_STATUS_CFG_CHANGED |
4041 MAC_STATUS_MI_COMPLETION |
4042 MAC_STATUS_LNKSTATE_CHANGED));
4048 current_link_up = 0;
4049 current_speed = SPEED_INVALID;
4050 current_duplex = DUPLEX_INVALID;
4052 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4053 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4055 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4056 bmsr |= BMSR_LSTATUS;
4058 bmsr &= ~BMSR_LSTATUS;
4061 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4063 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4064 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4065 /* do nothing, just check for link up at the end */
4066 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4069 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4070 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4071 ADVERTISE_1000XPAUSE |
4072 ADVERTISE_1000XPSE_ASYM |
4075 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4077 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4078 new_adv |= ADVERTISE_1000XHALF;
4079 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4080 new_adv |= ADVERTISE_1000XFULL;
4082 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4083 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4084 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4085 tg3_writephy(tp, MII_BMCR, bmcr);
4087 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4088 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4089 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4096 bmcr &= ~BMCR_SPEED1000;
4097 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4099 if (tp->link_config.duplex == DUPLEX_FULL)
4100 new_bmcr |= BMCR_FULLDPLX;
4102 if (new_bmcr != bmcr) {
4103 /* BMCR_SPEED1000 is a reserved bit that needs
4104 * to be set on write.
4106 new_bmcr |= BMCR_SPEED1000;
4108 /* Force a linkdown */
4109 if (netif_carrier_ok(tp->dev)) {
4112 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4113 adv &= ~(ADVERTISE_1000XFULL |
4114 ADVERTISE_1000XHALF |
4116 tg3_writephy(tp, MII_ADVERTISE, adv);
4117 tg3_writephy(tp, MII_BMCR, bmcr |
4121 netif_carrier_off(tp->dev);
4123 tg3_writephy(tp, MII_BMCR, new_bmcr);
4125 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4126 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4127 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4129 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4130 bmsr |= BMSR_LSTATUS;
4132 bmsr &= ~BMSR_LSTATUS;
4134 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4138 if (bmsr & BMSR_LSTATUS) {
4139 current_speed = SPEED_1000;
4140 current_link_up = 1;
4141 if (bmcr & BMCR_FULLDPLX)
4142 current_duplex = DUPLEX_FULL;
4144 current_duplex = DUPLEX_HALF;
4149 if (bmcr & BMCR_ANENABLE) {
4152 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4153 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4154 common = local_adv & remote_adv;
4155 if (common & (ADVERTISE_1000XHALF |
4156 ADVERTISE_1000XFULL)) {
4157 if (common & ADVERTISE_1000XFULL)
4158 current_duplex = DUPLEX_FULL;
4160 current_duplex = DUPLEX_HALF;
4163 current_link_up = 0;
4167 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4168 tg3_setup_flow_control(tp, local_adv, remote_adv);
4170 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4171 if (tp->link_config.active_duplex == DUPLEX_HALF)
4172 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4174 tw32_f(MAC_MODE, tp->mac_mode);
4177 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4179 tp->link_config.active_speed = current_speed;
4180 tp->link_config.active_duplex = current_duplex;
4182 if (current_link_up != netif_carrier_ok(tp->dev)) {
4183 if (current_link_up)
4184 netif_carrier_on(tp->dev);
4186 netif_carrier_off(tp->dev);
4187 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4189 tg3_link_report(tp);
4194 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4196 if (tp->serdes_counter) {
4197 /* Give autoneg time to complete. */
4198 tp->serdes_counter--;
4201 if (!netif_carrier_ok(tp->dev) &&
4202 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4205 tg3_readphy(tp, MII_BMCR, &bmcr);
4206 if (bmcr & BMCR_ANENABLE) {
4209 /* Select shadow register 0x1f */
4210 tg3_writephy(tp, 0x1c, 0x7c00);
4211 tg3_readphy(tp, 0x1c, &phy1);
4213 /* Select expansion interrupt status register */
4214 tg3_writephy(tp, 0x17, 0x0f01);
4215 tg3_readphy(tp, 0x15, &phy2);
4216 tg3_readphy(tp, 0x15, &phy2);
4218 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4219 /* We have signal detect and not receiving
4220 * config code words, link is up by parallel
4224 bmcr &= ~BMCR_ANENABLE;
4225 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4226 tg3_writephy(tp, MII_BMCR, bmcr);
4227 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4231 else if (netif_carrier_ok(tp->dev) &&
4232 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4233 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4236 /* Select expansion interrupt status register */
4237 tg3_writephy(tp, 0x17, 0x0f01);
4238 tg3_readphy(tp, 0x15, &phy2);
4242 /* Config code words received, turn on autoneg. */
4243 tg3_readphy(tp, MII_BMCR, &bmcr);
4244 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4246 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4252 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4257 err = tg3_setup_fiber_phy(tp, force_reset);
4258 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4259 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4261 err = tg3_setup_copper_phy(tp, force_reset);
4264 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4267 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4268 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4270 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4275 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4276 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4277 tw32(GRC_MISC_CFG, val);
4280 if (tp->link_config.active_speed == SPEED_1000 &&
4281 tp->link_config.active_duplex == DUPLEX_HALF)
4282 tw32(MAC_TX_LENGTHS,
4283 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4284 (6 << TX_LENGTHS_IPG_SHIFT) |
4285 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4287 tw32(MAC_TX_LENGTHS,
4288 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4289 (6 << TX_LENGTHS_IPG_SHIFT) |
4290 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4292 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4293 if (netif_carrier_ok(tp->dev)) {
4294 tw32(HOSTCC_STAT_COAL_TICKS,
4295 tp->coal.stats_block_coalesce_usecs);
4297 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4301 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4302 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4303 if (!netif_carrier_ok(tp->dev))
4304 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4307 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4308 tw32(PCIE_PWR_MGMT_THRESH, val);
4314 /* This is called whenever we suspect that the system chipset is re-
4315 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4316 * is bogus tx completions. We try to recover by setting the
4317 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4320 static void tg3_tx_recover(struct tg3 *tp)
4322 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4323 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4325 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4326 "mapped I/O cycles to the network device, attempting to "
4327 "recover. Please report the problem to the driver maintainer "
4328 "and include system chipset information.\n", tp->dev->name);
4330 spin_lock(&tp->lock);
4331 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4332 spin_unlock(&tp->lock);
4335 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4338 return tnapi->tx_pending -
4339 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4342 /* Tigon3 never reports partial packet sends. So we do not
4343 * need special logic to handle SKBs that have not had all
4344 * of their frags sent yet, like SunGEM does.
4346 static void tg3_tx(struct tg3_napi *tnapi)
4348 struct tg3 *tp = tnapi->tp;
4349 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4350 u32 sw_idx = tnapi->tx_cons;
4351 struct netdev_queue *txq;
4352 int index = tnapi - tp->napi;
4354 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4357 txq = netdev_get_tx_queue(tp->dev, index);
4359 while (sw_idx != hw_idx) {
4360 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4361 struct sk_buff *skb = ri->skb;
4364 if (unlikely(skb == NULL)) {
4369 pci_unmap_single(tp->pdev,
4370 pci_unmap_addr(ri, mapping),
4376 sw_idx = NEXT_TX(sw_idx);
4378 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4379 ri = &tnapi->tx_buffers[sw_idx];
4380 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4383 pci_unmap_page(tp->pdev,
4384 pci_unmap_addr(ri, mapping),
4385 skb_shinfo(skb)->frags[i].size,
4387 sw_idx = NEXT_TX(sw_idx);
4392 if (unlikely(tx_bug)) {
4398 tnapi->tx_cons = sw_idx;
4400 /* Need to make the tx_cons update visible to tg3_start_xmit()
4401 * before checking for netif_queue_stopped(). Without the
4402 * memory barrier, there is a small possibility that tg3_start_xmit()
4403 * will miss it and cause the queue to be stopped forever.
4407 if (unlikely(netif_tx_queue_stopped(txq) &&
4408 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4409 __netif_tx_lock(txq, smp_processor_id());
4410 if (netif_tx_queue_stopped(txq) &&
4411 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4412 netif_tx_wake_queue(txq);
4413 __netif_tx_unlock(txq);
4417 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4422 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4423 map_sz, PCI_DMA_FROMDEVICE);
4424 dev_kfree_skb_any(ri->skb);
4428 /* Returns size of skb allocated or < 0 on error.
4430 * We only need to fill in the address because the other members
4431 * of the RX descriptor are invariant, see tg3_init_rings.
4433 * Note the purposeful assymetry of cpu vs. chip accesses. For
4434 * posting buffers we only dirty the first cache line of the RX
4435 * descriptor (containing the address). Whereas for the RX status
4436 * buffers the cpu only reads the last cacheline of the RX descriptor
4437 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4439 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4440 u32 opaque_key, u32 dest_idx_unmasked)
4442 struct tg3_rx_buffer_desc *desc;
4443 struct ring_info *map, *src_map;
4444 struct sk_buff *skb;
4446 int skb_size, dest_idx;
4449 switch (opaque_key) {
4450 case RXD_OPAQUE_RING_STD:
4451 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4452 desc = &tpr->rx_std[dest_idx];
4453 map = &tpr->rx_std_buffers[dest_idx];
4454 skb_size = tp->rx_pkt_map_sz;
4457 case RXD_OPAQUE_RING_JUMBO:
4458 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4459 desc = &tpr->rx_jmb[dest_idx].std;
4460 map = &tpr->rx_jmb_buffers[dest_idx];
4461 skb_size = TG3_RX_JMB_MAP_SZ;
4468 /* Do not overwrite any of the map or rp information
4469 * until we are sure we can commit to a new buffer.
4471 * Callers depend upon this behavior and assume that
4472 * we leave everything unchanged if we fail.
4474 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4478 skb_reserve(skb, tp->rx_offset);
4480 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4481 PCI_DMA_FROMDEVICE);
4482 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4488 pci_unmap_addr_set(map, mapping, mapping);
4490 desc->addr_hi = ((u64)mapping >> 32);
4491 desc->addr_lo = ((u64)mapping & 0xffffffff);
4496 /* We only need to move over in the address because the other
4497 * members of the RX descriptor are invariant. See notes above
4498 * tg3_alloc_rx_skb for full details.
4500 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4501 struct tg3_rx_prodring_set *dpr,
4502 u32 opaque_key, int src_idx,
4503 u32 dest_idx_unmasked)
4505 struct tg3 *tp = tnapi->tp;
4506 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4507 struct ring_info *src_map, *dest_map;
4509 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4511 switch (opaque_key) {
4512 case RXD_OPAQUE_RING_STD:
4513 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4514 dest_desc = &dpr->rx_std[dest_idx];
4515 dest_map = &dpr->rx_std_buffers[dest_idx];
4516 src_desc = &spr->rx_std[src_idx];
4517 src_map = &spr->rx_std_buffers[src_idx];
4520 case RXD_OPAQUE_RING_JUMBO:
4521 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4522 dest_desc = &dpr->rx_jmb[dest_idx].std;
4523 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4524 src_desc = &spr->rx_jmb[src_idx].std;
4525 src_map = &spr->rx_jmb_buffers[src_idx];
4532 dest_map->skb = src_map->skb;
4533 pci_unmap_addr_set(dest_map, mapping,
4534 pci_unmap_addr(src_map, mapping));
4535 dest_desc->addr_hi = src_desc->addr_hi;
4536 dest_desc->addr_lo = src_desc->addr_lo;
4537 src_map->skb = NULL;
4540 /* The RX ring scheme is composed of multiple rings which post fresh
4541 * buffers to the chip, and one special ring the chip uses to report
4542 * status back to the host.
4544 * The special ring reports the status of received packets to the
4545 * host. The chip does not write into the original descriptor the
4546 * RX buffer was obtained from. The chip simply takes the original
4547 * descriptor as provided by the host, updates the status and length
4548 * field, then writes this into the next status ring entry.
4550 * Each ring the host uses to post buffers to the chip is described
4551 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4552 * it is first placed into the on-chip ram. When the packet's length
4553 * is known, it walks down the TG3_BDINFO entries to select the ring.
4554 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4555 * which is within the range of the new packet's length is chosen.
4557 * The "separate ring for rx status" scheme may sound queer, but it makes
4558 * sense from a cache coherency perspective. If only the host writes
4559 * to the buffer post rings, and only the chip writes to the rx status
4560 * rings, then cache lines never move beyond shared-modified state.
4561 * If both the host and chip were to write into the same ring, cache line
4562 * eviction could occur since both entities want it in an exclusive state.
4564 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4566 struct tg3 *tp = tnapi->tp;
4567 u32 work_mask, rx_std_posted = 0;
4568 u32 std_prod_idx, jmb_prod_idx;
4569 u32 sw_idx = tnapi->rx_rcb_ptr;
4572 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4574 hw_idx = *(tnapi->rx_rcb_prod_idx);
4576 * We need to order the read of hw_idx and the read of
4577 * the opaque cookie.
4582 std_prod_idx = tpr->rx_std_prod_idx;
4583 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4584 while (sw_idx != hw_idx && budget > 0) {
4585 struct ring_info *ri;
4586 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4588 struct sk_buff *skb;
4589 dma_addr_t dma_addr;
4590 u32 opaque_key, desc_idx, *post_ptr;
4592 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4593 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4594 if (opaque_key == RXD_OPAQUE_RING_STD) {
4595 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4596 dma_addr = pci_unmap_addr(ri, mapping);
4598 post_ptr = &std_prod_idx;
4600 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4601 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4602 dma_addr = pci_unmap_addr(ri, mapping);
4604 post_ptr = &jmb_prod_idx;
4606 goto next_pkt_nopost;
4608 work_mask |= opaque_key;
4610 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4611 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4613 tg3_recycle_rx(tnapi, tpr, opaque_key,
4614 desc_idx, *post_ptr);
4616 /* Other statistics kept track of by card. */
4617 tp->net_stats.rx_dropped++;
4621 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4624 if (len > RX_COPY_THRESHOLD &&
4625 tp->rx_offset == NET_IP_ALIGN) {
4626 /* rx_offset will likely not equal NET_IP_ALIGN
4627 * if this is a 5701 card running in PCI-X mode
4628 * [see tg3_get_invariants()]
4632 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4639 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4640 PCI_DMA_FROMDEVICE);
4644 struct sk_buff *copy_skb;
4646 tg3_recycle_rx(tnapi, tpr, opaque_key,
4647 desc_idx, *post_ptr);
4649 copy_skb = netdev_alloc_skb(tp->dev,
4650 len + TG3_RAW_IP_ALIGN);
4651 if (copy_skb == NULL)
4652 goto drop_it_no_recycle;
4654 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4655 skb_put(copy_skb, len);
4656 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4657 skb_copy_from_linear_data(skb, copy_skb->data, len);
4658 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4660 /* We'll reuse the original ring buffer. */
4664 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4665 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4666 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4667 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4668 skb->ip_summed = CHECKSUM_UNNECESSARY;
4670 skb->ip_summed = CHECKSUM_NONE;
4672 skb->protocol = eth_type_trans(skb, tp->dev);
4674 if (len > (tp->dev->mtu + ETH_HLEN) &&
4675 skb->protocol != htons(ETH_P_8021Q)) {
4680 #if TG3_VLAN_TAG_USED
4681 if (tp->vlgrp != NULL &&
4682 desc->type_flags & RXD_FLAG_VLAN) {
4683 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4684 desc->err_vlan & RXD_VLAN_MASK, skb);
4687 napi_gro_receive(&tnapi->napi, skb);
4695 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4696 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4697 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4698 work_mask &= ~RXD_OPAQUE_RING_STD;
4703 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4705 /* Refresh hw_idx to see if there is new work */
4706 if (sw_idx == hw_idx) {
4707 hw_idx = *(tnapi->rx_rcb_prod_idx);
4712 /* ACK the status ring. */
4713 tnapi->rx_rcb_ptr = sw_idx;
4714 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4716 /* Refill RX ring(s). */
4717 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4718 if (work_mask & RXD_OPAQUE_RING_STD) {
4719 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721 tpr->rx_std_prod_idx);
4723 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4724 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4725 TG3_RX_JUMBO_RING_SIZE;
4726 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4727 tpr->rx_jmb_prod_idx);
4730 } else if (work_mask) {
4731 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4732 * updated before the producer indices can be updated.
4736 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4737 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4739 napi_schedule(&tp->napi[1].napi);
4745 static void tg3_poll_link(struct tg3 *tp)
4747 /* handle link change and other phy events */
4748 if (!(tp->tg3_flags &
4749 (TG3_FLAG_USE_LINKCHG_REG |
4750 TG3_FLAG_POLL_SERDES))) {
4751 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4753 if (sblk->status & SD_STATUS_LINK_CHG) {
4754 sblk->status = SD_STATUS_UPDATED |
4755 (sblk->status & ~SD_STATUS_LINK_CHG);
4756 spin_lock(&tp->lock);
4757 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4759 (MAC_STATUS_SYNC_CHANGED |
4760 MAC_STATUS_CFG_CHANGED |
4761 MAC_STATUS_MI_COMPLETION |
4762 MAC_STATUS_LNKSTATE_CHANGED));
4765 tg3_setup_phy(tp, 0);
4766 spin_unlock(&tp->lock);
4771 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4772 struct tg3_rx_prodring_set *dpr,
4773 struct tg3_rx_prodring_set *spr)
4775 u32 si, di, cpycnt, src_prod_idx;
4779 src_prod_idx = spr->rx_std_prod_idx;
4781 /* Make sure updates to the rx_std_buffers[] entries and the
4782 * standard producer index are seen in the correct order.
4786 if (spr->rx_std_cons_idx == src_prod_idx)
4789 if (spr->rx_std_cons_idx < src_prod_idx)
4790 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4792 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4794 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4796 si = spr->rx_std_cons_idx;
4797 di = dpr->rx_std_prod_idx;
4799 memcpy(&dpr->rx_std_buffers[di],
4800 &spr->rx_std_buffers[si],
4801 cpycnt * sizeof(struct ring_info));
4803 for (i = 0; i < cpycnt; i++, di++, si++) {
4804 struct tg3_rx_buffer_desc *sbd, *dbd;
4805 sbd = &spr->rx_std[si];
4806 dbd = &dpr->rx_std[di];
4807 dbd->addr_hi = sbd->addr_hi;
4808 dbd->addr_lo = sbd->addr_lo;
4811 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4813 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4818 src_prod_idx = spr->rx_jmb_prod_idx;
4820 /* Make sure updates to the rx_jmb_buffers[] entries and
4821 * the jumbo producer index are seen in the correct order.
4825 if (spr->rx_jmb_cons_idx == src_prod_idx)
4828 if (spr->rx_jmb_cons_idx < src_prod_idx)
4829 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4831 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4833 cpycnt = min(cpycnt,
4834 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4836 si = spr->rx_jmb_cons_idx;
4837 di = dpr->rx_jmb_prod_idx;
4839 memcpy(&dpr->rx_jmb_buffers[di],
4840 &spr->rx_jmb_buffers[si],
4841 cpycnt * sizeof(struct ring_info));
4843 for (i = 0; i < cpycnt; i++, di++, si++) {
4844 struct tg3_rx_buffer_desc *sbd, *dbd;
4845 sbd = &spr->rx_jmb[si].std;
4846 dbd = &dpr->rx_jmb[di].std;
4847 dbd->addr_hi = sbd->addr_hi;
4848 dbd->addr_lo = sbd->addr_lo;
4851 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4852 TG3_RX_JUMBO_RING_SIZE;
4853 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4854 TG3_RX_JUMBO_RING_SIZE;
4858 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4860 struct tg3 *tp = tnapi->tp;
4862 /* run TX completion thread */
4863 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4865 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4869 /* run RX thread, within the bounds set by NAPI.
4870 * All RX "locking" is done by ensuring outside
4871 * code synchronizes with tg3->napi.poll()
4873 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4874 work_done += tg3_rx(tnapi, budget - work_done);
4876 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4878 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4879 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4881 for (i = 2; i < tp->irq_cnt; i++)
4882 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4883 tp->napi[i].prodring);
4887 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4888 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4889 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4892 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4893 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4894 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4903 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4905 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4906 struct tg3 *tp = tnapi->tp;
4908 struct tg3_hw_status *sblk = tnapi->hw_status;
4911 work_done = tg3_poll_work(tnapi, work_done, budget);
4913 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4916 if (unlikely(work_done >= budget))
4919 /* tp->last_tag is used in tg3_restart_ints() below
4920 * to tell the hw how much work has been processed,
4921 * so we must read it before checking for more work.
4923 tnapi->last_tag = sblk->status_tag;
4924 tnapi->last_irq_tag = tnapi->last_tag;
4927 /* check for RX/TX work to do */
4928 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4929 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4930 napi_complete(napi);
4931 /* Reenable interrupts. */
4932 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4941 /* work_done is guaranteed to be less than budget. */
4942 napi_complete(napi);
4943 schedule_work(&tp->reset_task);
4947 static int tg3_poll(struct napi_struct *napi, int budget)
4949 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4950 struct tg3 *tp = tnapi->tp;
4952 struct tg3_hw_status *sblk = tnapi->hw_status;
4957 work_done = tg3_poll_work(tnapi, work_done, budget);
4959 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4962 if (unlikely(work_done >= budget))
4965 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4966 /* tp->last_tag is used in tg3_int_reenable() below
4967 * to tell the hw how much work has been processed,
4968 * so we must read it before checking for more work.
4970 tnapi->last_tag = sblk->status_tag;
4971 tnapi->last_irq_tag = tnapi->last_tag;
4974 sblk->status &= ~SD_STATUS_UPDATED;
4976 if (likely(!tg3_has_work(tnapi))) {
4977 napi_complete(napi);
4978 tg3_int_reenable(tnapi);
4986 /* work_done is guaranteed to be less than budget. */
4987 napi_complete(napi);
4988 schedule_work(&tp->reset_task);
4992 static void tg3_irq_quiesce(struct tg3 *tp)
4996 BUG_ON(tp->irq_sync);
5001 for (i = 0; i < tp->irq_cnt; i++)
5002 synchronize_irq(tp->napi[i].irq_vec);
5005 static inline int tg3_irq_sync(struct tg3 *tp)
5007 return tp->irq_sync;
5010 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5011 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5012 * with as well. Most of the time, this is not necessary except when
5013 * shutting down the device.
5015 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5017 spin_lock_bh(&tp->lock);
5019 tg3_irq_quiesce(tp);
5022 static inline void tg3_full_unlock(struct tg3 *tp)
5024 spin_unlock_bh(&tp->lock);
5027 /* One-shot MSI handler - Chip automatically disables interrupt
5028 * after sending MSI so driver doesn't have to do it.
5030 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5032 struct tg3_napi *tnapi = dev_id;
5033 struct tg3 *tp = tnapi->tp;
5035 prefetch(tnapi->hw_status);
5037 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5039 if (likely(!tg3_irq_sync(tp)))
5040 napi_schedule(&tnapi->napi);
5045 /* MSI ISR - No need to check for interrupt sharing and no need to
5046 * flush status block and interrupt mailbox. PCI ordering rules
5047 * guarantee that MSI will arrive after the status block.
5049 static irqreturn_t tg3_msi(int irq, void *dev_id)
5051 struct tg3_napi *tnapi = dev_id;
5052 struct tg3 *tp = tnapi->tp;
5054 prefetch(tnapi->hw_status);
5056 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5058 * Writing any value to intr-mbox-0 clears PCI INTA# and
5059 * chip-internal interrupt pending events.
5060 * Writing non-zero to intr-mbox-0 additional tells the
5061 * NIC to stop sending us irqs, engaging "in-intr-handler"
5064 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5065 if (likely(!tg3_irq_sync(tp)))
5066 napi_schedule(&tnapi->napi);
5068 return IRQ_RETVAL(1);
5071 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5073 struct tg3_napi *tnapi = dev_id;
5074 struct tg3 *tp = tnapi->tp;
5075 struct tg3_hw_status *sblk = tnapi->hw_status;
5076 unsigned int handled = 1;
5078 /* In INTx mode, it is possible for the interrupt to arrive at
5079 * the CPU before the status block posted prior to the interrupt.
5080 * Reading the PCI State register will confirm whether the
5081 * interrupt is ours and will flush the status block.
5083 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5084 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5085 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5092 * Writing any value to intr-mbox-0 clears PCI INTA# and
5093 * chip-internal interrupt pending events.
5094 * Writing non-zero to intr-mbox-0 additional tells the
5095 * NIC to stop sending us irqs, engaging "in-intr-handler"
5098 * Flush the mailbox to de-assert the IRQ immediately to prevent
5099 * spurious interrupts. The flush impacts performance but
5100 * excessive spurious interrupts can be worse in some cases.
5102 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5103 if (tg3_irq_sync(tp))
5105 sblk->status &= ~SD_STATUS_UPDATED;
5106 if (likely(tg3_has_work(tnapi))) {
5107 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5108 napi_schedule(&tnapi->napi);
5110 /* No work, shared interrupt perhaps? re-enable
5111 * interrupts, and flush that PCI write
5113 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5117 return IRQ_RETVAL(handled);
5120 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5122 struct tg3_napi *tnapi = dev_id;
5123 struct tg3 *tp = tnapi->tp;
5124 struct tg3_hw_status *sblk = tnapi->hw_status;
5125 unsigned int handled = 1;
5127 /* In INTx mode, it is possible for the interrupt to arrive at
5128 * the CPU before the status block posted prior to the interrupt.
5129 * Reading the PCI State register will confirm whether the
5130 * interrupt is ours and will flush the status block.
5132 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5133 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5134 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5141 * writing any value to intr-mbox-0 clears PCI INTA# and
5142 * chip-internal interrupt pending events.
5143 * writing non-zero to intr-mbox-0 additional tells the
5144 * NIC to stop sending us irqs, engaging "in-intr-handler"
5147 * Flush the mailbox to de-assert the IRQ immediately to prevent
5148 * spurious interrupts. The flush impacts performance but
5149 * excessive spurious interrupts can be worse in some cases.
5151 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5154 * In a shared interrupt configuration, sometimes other devices'
5155 * interrupts will scream. We record the current status tag here
5156 * so that the above check can report that the screaming interrupts
5157 * are unhandled. Eventually they will be silenced.
5159 tnapi->last_irq_tag = sblk->status_tag;
5161 if (tg3_irq_sync(tp))
5164 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5166 napi_schedule(&tnapi->napi);
5169 return IRQ_RETVAL(handled);
5172 /* ISR for interrupt test */
5173 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5175 struct tg3_napi *tnapi = dev_id;
5176 struct tg3 *tp = tnapi->tp;
5177 struct tg3_hw_status *sblk = tnapi->hw_status;
5179 if ((sblk->status & SD_STATUS_UPDATED) ||
5180 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5181 tg3_disable_ints(tp);
5182 return IRQ_RETVAL(1);
5184 return IRQ_RETVAL(0);
5187 static int tg3_init_hw(struct tg3 *, int);
5188 static int tg3_halt(struct tg3 *, int, int);
5190 /* Restart hardware after configuration changes, self-test, etc.
5191 * Invoked with tp->lock held.
5193 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5194 __releases(tp->lock)
5195 __acquires(tp->lock)
5199 err = tg3_init_hw(tp, reset_phy);
5201 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5202 "aborting.\n", tp->dev->name);
5203 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5204 tg3_full_unlock(tp);
5205 del_timer_sync(&tp->timer);
5207 tg3_napi_enable(tp);
5209 tg3_full_lock(tp, 0);
5214 #ifdef CONFIG_NET_POLL_CONTROLLER
5215 static void tg3_poll_controller(struct net_device *dev)
5218 struct tg3 *tp = netdev_priv(dev);
5220 for (i = 0; i < tp->irq_cnt; i++)
5221 tg3_interrupt(tp->napi[i].irq_vec, dev);
5225 static void tg3_reset_task(struct work_struct *work)
5227 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5229 unsigned int restart_timer;
5231 tg3_full_lock(tp, 0);
5233 if (!netif_running(tp->dev)) {
5234 tg3_full_unlock(tp);
5238 tg3_full_unlock(tp);
5244 tg3_full_lock(tp, 1);
5246 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5247 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5249 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5250 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5251 tp->write32_rx_mbox = tg3_write_flush_reg32;
5252 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5253 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5256 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5257 err = tg3_init_hw(tp, 1);
5261 tg3_netif_start(tp);
5264 mod_timer(&tp->timer, jiffies + 1);
5267 tg3_full_unlock(tp);
5273 static void tg3_dump_short_state(struct tg3 *tp)
5275 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5276 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5277 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5278 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5281 static void tg3_tx_timeout(struct net_device *dev)
5283 struct tg3 *tp = netdev_priv(dev);
5285 if (netif_msg_tx_err(tp)) {
5286 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5288 tg3_dump_short_state(tp);
5291 schedule_work(&tp->reset_task);
5294 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5295 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5297 u32 base = (u32) mapping & 0xffffffff;
5299 return ((base > 0xffffdcc0) &&
5300 (base + len + 8 < base));
5303 /* Test for DMA addresses > 40-bit */
5304 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5307 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5308 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5309 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5316 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5318 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5319 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5320 struct sk_buff *skb, u32 last_plus_one,
5321 u32 *start, u32 base_flags, u32 mss)
5323 struct tg3 *tp = tnapi->tp;
5324 struct sk_buff *new_skb;
5325 dma_addr_t new_addr = 0;
5329 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5330 new_skb = skb_copy(skb, GFP_ATOMIC);
5332 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5334 new_skb = skb_copy_expand(skb,
5335 skb_headroom(skb) + more_headroom,
5336 skb_tailroom(skb), GFP_ATOMIC);
5342 /* New SKB is guaranteed to be linear. */
5344 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5346 /* Make sure the mapping succeeded */
5347 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5349 dev_kfree_skb(new_skb);
5352 /* Make sure new skb does not cross any 4G boundaries.
5353 * Drop the packet if it does.
5355 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5356 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5357 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5360 dev_kfree_skb(new_skb);
5363 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5364 base_flags, 1 | (mss << 1));
5365 *start = NEXT_TX(entry);
5369 /* Now clean up the sw ring entries. */
5371 while (entry != last_plus_one) {
5375 len = skb_headlen(skb);
5377 len = skb_shinfo(skb)->frags[i-1].size;
5379 pci_unmap_single(tp->pdev,
5380 pci_unmap_addr(&tnapi->tx_buffers[entry],
5382 len, PCI_DMA_TODEVICE);
5384 tnapi->tx_buffers[entry].skb = new_skb;
5385 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5388 tnapi->tx_buffers[entry].skb = NULL;
5390 entry = NEXT_TX(entry);
5399 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5400 dma_addr_t mapping, int len, u32 flags,
5403 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5404 int is_end = (mss_and_is_end & 0x1);
5405 u32 mss = (mss_and_is_end >> 1);
5409 flags |= TXD_FLAG_END;
5410 if (flags & TXD_FLAG_VLAN) {
5411 vlan_tag = flags >> 16;
5414 vlan_tag |= (mss << TXD_MSS_SHIFT);
5416 txd->addr_hi = ((u64) mapping >> 32);
5417 txd->addr_lo = ((u64) mapping & 0xffffffff);
5418 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5419 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5422 /* hard_start_xmit for devices that don't have any bugs and
5423 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5425 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5426 struct net_device *dev)
5428 struct tg3 *tp = netdev_priv(dev);
5429 u32 len, entry, base_flags, mss;
5431 struct tg3_napi *tnapi;
5432 struct netdev_queue *txq;
5433 unsigned int i, last;
5436 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5437 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5438 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5441 /* We are running in BH disabled context with netif_tx_lock
5442 * and TX reclaim runs via tp->napi.poll inside of a software
5443 * interrupt. Furthermore, IRQ processing runs lockless so we have
5444 * no IRQ context deadlocks to worry about either. Rejoice!
5446 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5447 if (!netif_tx_queue_stopped(txq)) {
5448 netif_tx_stop_queue(txq);
5450 /* This is a hard error, log it. */
5451 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5452 "queue awake!\n", dev->name);
5454 return NETDEV_TX_BUSY;
5457 entry = tnapi->tx_prod;
5460 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5461 int tcp_opt_len, ip_tcp_len;
5464 if (skb_header_cloned(skb) &&
5465 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5470 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5471 hdrlen = skb_headlen(skb) - ETH_HLEN;
5473 struct iphdr *iph = ip_hdr(skb);
5475 tcp_opt_len = tcp_optlen(skb);
5476 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5479 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5480 hdrlen = ip_tcp_len + tcp_opt_len;
5483 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5484 mss |= (hdrlen & 0xc) << 12;
5486 base_flags |= 0x00000010;
5487 base_flags |= (hdrlen & 0x3e0) << 5;
5491 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5492 TXD_FLAG_CPU_POST_DMA);
5494 tcp_hdr(skb)->check = 0;
5497 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5498 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5499 #if TG3_VLAN_TAG_USED
5500 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5501 base_flags |= (TXD_FLAG_VLAN |
5502 (vlan_tx_tag_get(skb) << 16));
5505 len = skb_headlen(skb);
5507 /* Queue skb data, a.k.a. the main skb fragment. */
5508 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5509 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5514 tnapi->tx_buffers[entry].skb = skb;
5515 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5518 !mss && skb->len > ETH_DATA_LEN)
5519 base_flags |= TXD_FLAG_JMB_PKT;
5521 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5522 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5524 entry = NEXT_TX(entry);
5526 /* Now loop through additional data fragments, and queue them. */
5527 if (skb_shinfo(skb)->nr_frags > 0) {
5528 last = skb_shinfo(skb)->nr_frags - 1;
5529 for (i = 0; i <= last; i++) {
5530 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5533 mapping = pci_map_page(tp->pdev,
5536 len, PCI_DMA_TODEVICE);
5537 if (pci_dma_mapping_error(tp->pdev, mapping))
5540 tnapi->tx_buffers[entry].skb = NULL;
5541 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5544 tg3_set_txd(tnapi, entry, mapping, len,
5545 base_flags, (i == last) | (mss << 1));
5547 entry = NEXT_TX(entry);
5551 /* Packets are ready, update Tx producer idx local and on card. */
5552 tw32_tx_mbox(tnapi->prodmbox, entry);
5554 tnapi->tx_prod = entry;
5555 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5556 netif_tx_stop_queue(txq);
5557 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5558 netif_tx_wake_queue(txq);
5564 return NETDEV_TX_OK;
5568 entry = tnapi->tx_prod;
5569 tnapi->tx_buffers[entry].skb = NULL;
5570 pci_unmap_single(tp->pdev,
5571 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5574 for (i = 0; i <= last; i++) {
5575 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5576 entry = NEXT_TX(entry);
5578 pci_unmap_page(tp->pdev,
5579 pci_unmap_addr(&tnapi->tx_buffers[entry],
5581 frag->size, PCI_DMA_TODEVICE);
5585 return NETDEV_TX_OK;
5588 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5589 struct net_device *);
5591 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5592 * TSO header is greater than 80 bytes.
5594 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5596 struct sk_buff *segs, *nskb;
5597 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5599 /* Estimate the number of fragments in the worst case */
5600 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5601 netif_stop_queue(tp->dev);
5602 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5603 return NETDEV_TX_BUSY;
5605 netif_wake_queue(tp->dev);
5608 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5610 goto tg3_tso_bug_end;
5616 tg3_start_xmit_dma_bug(nskb, tp->dev);
5622 return NETDEV_TX_OK;
5625 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5626 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5628 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5629 struct net_device *dev)
5631 struct tg3 *tp = netdev_priv(dev);
5632 u32 len, entry, base_flags, mss;
5633 int would_hit_hwbug;
5635 struct tg3_napi *tnapi;
5636 struct netdev_queue *txq;
5637 unsigned int i, last;
5640 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5641 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5642 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5645 /* We are running in BH disabled context with netif_tx_lock
5646 * and TX reclaim runs via tp->napi.poll inside of a software
5647 * interrupt. Furthermore, IRQ processing runs lockless so we have
5648 * no IRQ context deadlocks to worry about either. Rejoice!
5650 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5651 if (!netif_tx_queue_stopped(txq)) {
5652 netif_tx_stop_queue(txq);
5654 /* This is a hard error, log it. */
5655 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5656 "queue awake!\n", dev->name);
5658 return NETDEV_TX_BUSY;
5661 entry = tnapi->tx_prod;
5663 if (skb->ip_summed == CHECKSUM_PARTIAL)
5664 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5666 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5668 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5670 if (skb_header_cloned(skb) &&
5671 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5676 tcp_opt_len = tcp_optlen(skb);
5677 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5679 hdr_len = ip_tcp_len + tcp_opt_len;
5680 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5681 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5682 return (tg3_tso_bug(tp, skb));
5684 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5685 TXD_FLAG_CPU_POST_DMA);
5689 iph->tot_len = htons(mss + hdr_len);
5690 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5691 tcp_hdr(skb)->check = 0;
5692 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5694 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5699 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5700 mss |= (hdr_len & 0xc) << 12;
5702 base_flags |= 0x00000010;
5703 base_flags |= (hdr_len & 0x3e0) << 5;
5704 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5705 mss |= hdr_len << 9;
5706 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5708 if (tcp_opt_len || iph->ihl > 5) {
5711 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5712 mss |= (tsflags << 11);
5715 if (tcp_opt_len || iph->ihl > 5) {
5718 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5719 base_flags |= tsflags << 12;
5723 #if TG3_VLAN_TAG_USED
5724 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5725 base_flags |= (TXD_FLAG_VLAN |
5726 (vlan_tx_tag_get(skb) << 16));
5729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5730 !mss && skb->len > ETH_DATA_LEN)
5731 base_flags |= TXD_FLAG_JMB_PKT;
5733 len = skb_headlen(skb);
5735 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5736 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5741 tnapi->tx_buffers[entry].skb = skb;
5742 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5744 would_hit_hwbug = 0;
5746 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5747 would_hit_hwbug = 1;
5749 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5750 tg3_4g_overflow_test(mapping, len))
5751 would_hit_hwbug = 1;
5753 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5754 tg3_40bit_overflow_test(tp, mapping, len))
5755 would_hit_hwbug = 1;
5757 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5758 would_hit_hwbug = 1;
5760 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5761 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5763 entry = NEXT_TX(entry);
5765 /* Now loop through additional data fragments, and queue them. */
5766 if (skb_shinfo(skb)->nr_frags > 0) {
5767 last = skb_shinfo(skb)->nr_frags - 1;
5768 for (i = 0; i <= last; i++) {
5769 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5772 mapping = pci_map_page(tp->pdev,
5775 len, PCI_DMA_TODEVICE);
5777 tnapi->tx_buffers[entry].skb = NULL;
5778 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5780 if (pci_dma_mapping_error(tp->pdev, mapping))
5783 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5785 would_hit_hwbug = 1;
5787 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5788 tg3_4g_overflow_test(mapping, len))
5789 would_hit_hwbug = 1;
5791 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5792 tg3_40bit_overflow_test(tp, mapping, len))
5793 would_hit_hwbug = 1;
5795 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5796 tg3_set_txd(tnapi, entry, mapping, len,
5797 base_flags, (i == last)|(mss << 1));
5799 tg3_set_txd(tnapi, entry, mapping, len,
5800 base_flags, (i == last));
5802 entry = NEXT_TX(entry);
5806 if (would_hit_hwbug) {
5807 u32 last_plus_one = entry;
5810 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5811 start &= (TG3_TX_RING_SIZE - 1);
5813 /* If the workaround fails due to memory/mapping
5814 * failure, silently drop this packet.
5816 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5817 &start, base_flags, mss))
5823 /* Packets are ready, update Tx producer idx local and on card. */
5824 tw32_tx_mbox(tnapi->prodmbox, entry);
5826 tnapi->tx_prod = entry;
5827 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5828 netif_tx_stop_queue(txq);
5829 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5830 netif_tx_wake_queue(txq);
5836 return NETDEV_TX_OK;
5840 entry = tnapi->tx_prod;
5841 tnapi->tx_buffers[entry].skb = NULL;
5842 pci_unmap_single(tp->pdev,
5843 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5846 for (i = 0; i <= last; i++) {
5847 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5848 entry = NEXT_TX(entry);
5850 pci_unmap_page(tp->pdev,
5851 pci_unmap_addr(&tnapi->tx_buffers[entry],
5853 frag->size, PCI_DMA_TODEVICE);
5857 return NETDEV_TX_OK;
5860 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5865 if (new_mtu > ETH_DATA_LEN) {
5866 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5867 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5868 ethtool_op_set_tso(dev, 0);
5871 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5873 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5874 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5875 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5879 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5881 struct tg3 *tp = netdev_priv(dev);
5884 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5887 if (!netif_running(dev)) {
5888 /* We'll just catch it later when the
5891 tg3_set_mtu(dev, tp, new_mtu);
5899 tg3_full_lock(tp, 1);
5901 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5903 tg3_set_mtu(dev, tp, new_mtu);
5905 err = tg3_restart_hw(tp, 0);
5908 tg3_netif_start(tp);
5910 tg3_full_unlock(tp);
5918 static void tg3_rx_prodring_free(struct tg3 *tp,
5919 struct tg3_rx_prodring_set *tpr)
5923 if (tpr != &tp->prodring[0]) {
5924 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5925 i = (i + 1) % TG3_RX_RING_SIZE)
5926 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5929 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5930 for (i = tpr->rx_jmb_cons_idx;
5931 i != tpr->rx_jmb_prod_idx;
5932 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5933 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5941 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5942 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5945 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5946 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5947 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5952 /* Initialize tx/rx rings for packet processing.
5954 * The chip has been shut down and the driver detached from
5955 * the networking, so no interrupts or new tx packets will
5956 * end up in the driver. tp->{tx,}lock are held and thus
5959 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5960 struct tg3_rx_prodring_set *tpr)
5962 u32 i, rx_pkt_dma_sz;
5964 tpr->rx_std_cons_idx = 0;
5965 tpr->rx_std_prod_idx = 0;
5966 tpr->rx_jmb_cons_idx = 0;
5967 tpr->rx_jmb_prod_idx = 0;
5969 if (tpr != &tp->prodring[0]) {
5970 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5971 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5972 memset(&tpr->rx_jmb_buffers[0], 0,
5973 TG3_RX_JMB_BUFF_RING_SIZE);
5977 /* Zero out all descriptors. */
5978 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5980 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5981 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5982 tp->dev->mtu > ETH_DATA_LEN)
5983 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5984 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5986 /* Initialize invariants of the rings, we only set this
5987 * stuff once. This works because the card does not
5988 * write into the rx buffer posting rings.
5990 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5991 struct tg3_rx_buffer_desc *rxd;
5993 rxd = &tpr->rx_std[i];
5994 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5995 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5996 rxd->opaque = (RXD_OPAQUE_RING_STD |
5997 (i << RXD_OPAQUE_INDEX_SHIFT));
6000 /* Now allocate fresh SKBs for each rx ring. */
6001 for (i = 0; i < tp->rx_pending; i++) {
6002 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6003 printk(KERN_WARNING PFX
6004 "%s: Using a smaller RX standard ring, "
6005 "only %d out of %d buffers were allocated "
6007 tp->dev->name, i, tp->rx_pending);
6015 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6018 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6020 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6021 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6022 struct tg3_rx_buffer_desc *rxd;
6024 rxd = &tpr->rx_jmb[i].std;
6025 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6026 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6028 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6029 (i << RXD_OPAQUE_INDEX_SHIFT));
6032 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6033 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6035 printk(KERN_WARNING PFX
6036 "%s: Using a smaller RX jumbo ring, "
6037 "only %d out of %d buffers were "
6038 "allocated successfully.\n",
6039 tp->dev->name, i, tp->rx_jumbo_pending);
6042 tp->rx_jumbo_pending = i;
6052 tg3_rx_prodring_free(tp, tpr);
6056 static void tg3_rx_prodring_fini(struct tg3 *tp,
6057 struct tg3_rx_prodring_set *tpr)
6059 kfree(tpr->rx_std_buffers);
6060 tpr->rx_std_buffers = NULL;
6061 kfree(tpr->rx_jmb_buffers);
6062 tpr->rx_jmb_buffers = NULL;
6064 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6065 tpr->rx_std, tpr->rx_std_mapping);
6069 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6070 tpr->rx_jmb, tpr->rx_jmb_mapping);
6075 static int tg3_rx_prodring_init(struct tg3 *tp,
6076 struct tg3_rx_prodring_set *tpr)
6078 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6079 if (!tpr->rx_std_buffers)
6082 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6083 &tpr->rx_std_mapping);
6087 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6088 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6090 if (!tpr->rx_jmb_buffers)
6093 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6094 TG3_RX_JUMBO_RING_BYTES,
6095 &tpr->rx_jmb_mapping);
6103 tg3_rx_prodring_fini(tp, tpr);
6107 /* Free up pending packets in all rx/tx rings.
6109 * The chip has been shut down and the driver detached from
6110 * the networking, so no interrupts or new tx packets will
6111 * end up in the driver. tp->{tx,}lock is not held and we are not
6112 * in an interrupt context and thus may sleep.
6114 static void tg3_free_rings(struct tg3 *tp)
6118 for (j = 0; j < tp->irq_cnt; j++) {
6119 struct tg3_napi *tnapi = &tp->napi[j];
6121 if (!tnapi->tx_buffers)
6124 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6125 struct ring_info *txp;
6126 struct sk_buff *skb;
6129 txp = &tnapi->tx_buffers[i];
6137 pci_unmap_single(tp->pdev,
6138 pci_unmap_addr(txp, mapping),
6145 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6146 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6147 pci_unmap_page(tp->pdev,
6148 pci_unmap_addr(txp, mapping),
6149 skb_shinfo(skb)->frags[k].size,
6154 dev_kfree_skb_any(skb);
6157 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6158 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6162 /* Initialize tx/rx rings for packet processing.
6164 * The chip has been shut down and the driver detached from
6165 * the networking, so no interrupts or new tx packets will
6166 * end up in the driver. tp->{tx,}lock are held and thus
6169 static int tg3_init_rings(struct tg3 *tp)
6173 /* Free up all the SKBs. */
6176 for (i = 0; i < tp->irq_cnt; i++) {
6177 struct tg3_napi *tnapi = &tp->napi[i];
6179 tnapi->last_tag = 0;
6180 tnapi->last_irq_tag = 0;
6181 tnapi->hw_status->status = 0;
6182 tnapi->hw_status->status_tag = 0;
6183 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6188 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6190 tnapi->rx_rcb_ptr = 0;
6192 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6194 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6195 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6203 * Must not be invoked with interrupt sources disabled and
6204 * the hardware shutdown down.
6206 static void tg3_free_consistent(struct tg3 *tp)
6210 for (i = 0; i < tp->irq_cnt; i++) {
6211 struct tg3_napi *tnapi = &tp->napi[i];
6213 if (tnapi->tx_ring) {
6214 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6215 tnapi->tx_ring, tnapi->tx_desc_mapping);
6216 tnapi->tx_ring = NULL;
6219 kfree(tnapi->tx_buffers);
6220 tnapi->tx_buffers = NULL;
6222 if (tnapi->rx_rcb) {
6223 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6225 tnapi->rx_rcb_mapping);
6226 tnapi->rx_rcb = NULL;
6229 if (tnapi->hw_status) {
6230 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6232 tnapi->status_mapping);
6233 tnapi->hw_status = NULL;
6238 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6239 tp->hw_stats, tp->stats_mapping);
6240 tp->hw_stats = NULL;
6243 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6244 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6248 * Must not be invoked with interrupt sources disabled and
6249 * the hardware shutdown down. Can sleep.
6251 static int tg3_alloc_consistent(struct tg3 *tp)
6255 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6256 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6260 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6261 sizeof(struct tg3_hw_stats),
6262 &tp->stats_mapping);
6266 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6268 for (i = 0; i < tp->irq_cnt; i++) {
6269 struct tg3_napi *tnapi = &tp->napi[i];
6270 struct tg3_hw_status *sblk;
6272 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6274 &tnapi->status_mapping);
6275 if (!tnapi->hw_status)
6278 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6279 sblk = tnapi->hw_status;
6282 * When RSS is enabled, the status block format changes
6283 * slightly. The "rx_jumbo_consumer", "reserved",
6284 * and "rx_mini_consumer" members get mapped to the
6285 * other three rx return ring producer indexes.
6289 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6292 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6295 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6298 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6302 if (tp->irq_cnt == 1)
6303 tnapi->prodring = &tp->prodring[0];
6305 tnapi->prodring = &tp->prodring[i - 1];
6308 * If multivector RSS is enabled, vector 0 does not handle
6309 * rx or tx interrupts. Don't allocate any resources for it.
6311 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6314 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6315 TG3_RX_RCB_RING_BYTES(tp),
6316 &tnapi->rx_rcb_mapping);
6320 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6322 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6323 TG3_TX_RING_SIZE, GFP_KERNEL);
6324 if (!tnapi->tx_buffers)
6327 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6329 &tnapi->tx_desc_mapping);
6330 if (!tnapi->tx_ring)
6337 tg3_free_consistent(tp);
6341 #define MAX_WAIT_CNT 1000
6343 /* To stop a block, clear the enable bit and poll till it
6344 * clears. tp->lock is held.
6346 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6351 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6358 /* We can't enable/disable these bits of the
6359 * 5705/5750, just say success.
6372 for (i = 0; i < MAX_WAIT_CNT; i++) {
6375 if ((val & enable_bit) == 0)
6379 if (i == MAX_WAIT_CNT && !silent) {
6380 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6381 "ofs=%lx enable_bit=%x\n",
6389 /* tp->lock is held. */
6390 static int tg3_abort_hw(struct tg3 *tp, int silent)
6394 tg3_disable_ints(tp);
6396 tp->rx_mode &= ~RX_MODE_ENABLE;
6397 tw32_f(MAC_RX_MODE, tp->rx_mode);
6400 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6401 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6402 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6403 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6404 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6405 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6407 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6408 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6409 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6410 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6411 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6412 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6413 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6415 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6416 tw32_f(MAC_MODE, tp->mac_mode);
6419 tp->tx_mode &= ~TX_MODE_ENABLE;
6420 tw32_f(MAC_TX_MODE, tp->tx_mode);
6422 for (i = 0; i < MAX_WAIT_CNT; i++) {
6424 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6427 if (i >= MAX_WAIT_CNT) {
6428 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6429 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6430 tp->dev->name, tr32(MAC_TX_MODE));
6434 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6435 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6436 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6438 tw32(FTQ_RESET, 0xffffffff);
6439 tw32(FTQ_RESET, 0x00000000);
6441 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6442 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6444 for (i = 0; i < tp->irq_cnt; i++) {
6445 struct tg3_napi *tnapi = &tp->napi[i];
6446 if (tnapi->hw_status)
6447 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6450 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6455 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6460 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6461 if (apedata != APE_SEG_SIG_MAGIC)
6464 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6465 if (!(apedata & APE_FW_STATUS_READY))
6468 /* Wait for up to 1 millisecond for APE to service previous event. */
6469 for (i = 0; i < 10; i++) {
6470 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6473 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6475 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6476 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6477 event | APE_EVENT_STATUS_EVENT_PENDING);
6479 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6481 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6487 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6488 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6491 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6496 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6500 case RESET_KIND_INIT:
6501 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6502 APE_HOST_SEG_SIG_MAGIC);
6503 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6504 APE_HOST_SEG_LEN_MAGIC);
6505 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6506 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6507 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6508 APE_HOST_DRIVER_ID_MAGIC);
6509 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6510 APE_HOST_BEHAV_NO_PHYLOCK);
6512 event = APE_EVENT_STATUS_STATE_START;
6514 case RESET_KIND_SHUTDOWN:
6515 /* With the interface we are currently using,
6516 * APE does not track driver state. Wiping
6517 * out the HOST SEGMENT SIGNATURE forces
6518 * the APE to assume OS absent status.
6520 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6522 event = APE_EVENT_STATUS_STATE_UNLOAD;
6524 case RESET_KIND_SUSPEND:
6525 event = APE_EVENT_STATUS_STATE_SUSPEND;
6531 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6533 tg3_ape_send_event(tp, event);
6536 /* tp->lock is held. */
6537 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6539 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6540 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6542 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6544 case RESET_KIND_INIT:
6545 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6549 case RESET_KIND_SHUTDOWN:
6550 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6554 case RESET_KIND_SUSPEND:
6555 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6564 if (kind == RESET_KIND_INIT ||
6565 kind == RESET_KIND_SUSPEND)
6566 tg3_ape_driver_state_change(tp, kind);
6569 /* tp->lock is held. */
6570 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6572 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6574 case RESET_KIND_INIT:
6575 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6576 DRV_STATE_START_DONE);
6579 case RESET_KIND_SHUTDOWN:
6580 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6581 DRV_STATE_UNLOAD_DONE);
6589 if (kind == RESET_KIND_SHUTDOWN)
6590 tg3_ape_driver_state_change(tp, kind);
6593 /* tp->lock is held. */
6594 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6596 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6598 case RESET_KIND_INIT:
6599 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6603 case RESET_KIND_SHUTDOWN:
6604 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6608 case RESET_KIND_SUSPEND:
6609 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6619 static int tg3_poll_fw(struct tg3 *tp)
6624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6625 /* Wait up to 20ms for init done. */
6626 for (i = 0; i < 200; i++) {
6627 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6634 /* Wait for firmware initialization to complete. */
6635 for (i = 0; i < 100000; i++) {
6636 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6637 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6642 /* Chip might not be fitted with firmware. Some Sun onboard
6643 * parts are configured like that. So don't signal the timeout
6644 * of the above loop as an error, but do report the lack of
6645 * running firmware once.
6648 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6649 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6651 printk(KERN_INFO PFX "%s: No firmware running.\n",
6658 /* Save PCI command register before chip reset */
6659 static void tg3_save_pci_state(struct tg3 *tp)
6661 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6664 /* Restore PCI state after chip reset */
6665 static void tg3_restore_pci_state(struct tg3 *tp)
6669 /* Re-enable indirect register accesses. */
6670 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6671 tp->misc_host_ctrl);
6673 /* Set MAX PCI retry to zero. */
6674 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6675 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6676 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6677 val |= PCISTATE_RETRY_SAME_DMA;
6678 /* Allow reads and writes to the APE register and memory space. */
6679 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6680 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6681 PCISTATE_ALLOW_APE_SHMEM_WR;
6682 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6684 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6686 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6687 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6688 pcie_set_readrq(tp->pdev, 4096);
6690 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6691 tp->pci_cacheline_sz);
6692 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6697 /* Make sure PCI-X relaxed ordering bit is clear. */
6698 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6701 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6703 pcix_cmd &= ~PCI_X_CMD_ERO;
6704 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6708 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6710 /* Chip reset on 5780 will reset MSI enable bit,
6711 * so need to restore it.
6713 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6716 pci_read_config_word(tp->pdev,
6717 tp->msi_cap + PCI_MSI_FLAGS,
6719 pci_write_config_word(tp->pdev,
6720 tp->msi_cap + PCI_MSI_FLAGS,
6721 ctrl | PCI_MSI_FLAGS_ENABLE);
6722 val = tr32(MSGINT_MODE);
6723 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6728 static void tg3_stop_fw(struct tg3 *);
6730 /* tp->lock is held. */
6731 static int tg3_chip_reset(struct tg3 *tp)
6734 void (*write_op)(struct tg3 *, u32, u32);
6739 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6741 /* No matching tg3_nvram_unlock() after this because
6742 * chip reset below will undo the nvram lock.
6744 tp->nvram_lock_cnt = 0;
6746 /* GRC_MISC_CFG core clock reset will clear the memory
6747 * enable bit in PCI register 4 and the MSI enable bit
6748 * on some chips, so we save relevant registers here.
6750 tg3_save_pci_state(tp);
6752 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6753 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6754 tw32(GRC_FASTBOOT_PC, 0);
6757 * We must avoid the readl() that normally takes place.
6758 * It locks machines, causes machine checks, and other
6759 * fun things. So, temporarily disable the 5701
6760 * hardware workaround, while we do the reset.
6762 write_op = tp->write32;
6763 if (write_op == tg3_write_flush_reg32)
6764 tp->write32 = tg3_write32;
6766 /* Prevent the irq handler from reading or writing PCI registers
6767 * during chip reset when the memory enable bit in the PCI command
6768 * register may be cleared. The chip does not generate interrupt
6769 * at this time, but the irq handler may still be called due to irq
6770 * sharing or irqpoll.
6772 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6773 for (i = 0; i < tp->irq_cnt; i++) {
6774 struct tg3_napi *tnapi = &tp->napi[i];
6775 if (tnapi->hw_status) {
6776 tnapi->hw_status->status = 0;
6777 tnapi->hw_status->status_tag = 0;
6779 tnapi->last_tag = 0;
6780 tnapi->last_irq_tag = 0;
6784 for (i = 0; i < tp->irq_cnt; i++)
6785 synchronize_irq(tp->napi[i].irq_vec);
6787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6788 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6789 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6793 val = GRC_MISC_CFG_CORECLK_RESET;
6795 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6796 if (tr32(0x7e2c) == 0x60) {
6799 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6800 tw32(GRC_MISC_CFG, (1 << 29));
6805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6806 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6807 tw32(GRC_VCPU_EXT_CTRL,
6808 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6811 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6812 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6813 tw32(GRC_MISC_CFG, val);
6815 /* restore 5701 hardware bug workaround write method */
6816 tp->write32 = write_op;
6818 /* Unfortunately, we have to delay before the PCI read back.
6819 * Some 575X chips even will not respond to a PCI cfg access
6820 * when the reset command is given to the chip.
6822 * How do these hardware designers expect things to work
6823 * properly if the PCI write is posted for a long period
6824 * of time? It is always necessary to have some method by
6825 * which a register read back can occur to push the write
6826 * out which does the reset.
6828 * For most tg3 variants the trick below was working.
6833 /* Flush PCI posted writes. The normal MMIO registers
6834 * are inaccessible at this time so this is the only
6835 * way to make this reliably (actually, this is no longer
6836 * the case, see above). I tried to use indirect
6837 * register read/write but this upset some 5701 variants.
6839 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6843 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6846 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6850 /* Wait for link training to complete. */
6851 for (i = 0; i < 5000; i++)
6854 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6855 pci_write_config_dword(tp->pdev, 0xc4,
6856 cfg_val | (1 << 15));
6859 /* Clear the "no snoop" and "relaxed ordering" bits. */
6860 pci_read_config_word(tp->pdev,
6861 tp->pcie_cap + PCI_EXP_DEVCTL,
6863 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6864 PCI_EXP_DEVCTL_NOSNOOP_EN);
6866 * Older PCIe devices only support the 128 byte
6867 * MPS setting. Enforce the restriction.
6869 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6870 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6871 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6872 pci_write_config_word(tp->pdev,
6873 tp->pcie_cap + PCI_EXP_DEVCTL,
6876 pcie_set_readrq(tp->pdev, 4096);
6878 /* Clear error status */
6879 pci_write_config_word(tp->pdev,
6880 tp->pcie_cap + PCI_EXP_DEVSTA,
6881 PCI_EXP_DEVSTA_CED |
6882 PCI_EXP_DEVSTA_NFED |
6883 PCI_EXP_DEVSTA_FED |
6884 PCI_EXP_DEVSTA_URD);
6887 tg3_restore_pci_state(tp);
6889 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6892 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6893 val = tr32(MEMARB_MODE);
6894 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6896 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6898 tw32(0x5000, 0x400);
6901 tw32(GRC_MODE, tp->grc_mode);
6903 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6906 tw32(0xc4, val | (1 << 15));
6909 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6911 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6912 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6913 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6914 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6917 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6918 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6919 tw32_f(MAC_MODE, tp->mac_mode);
6920 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6921 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6922 tw32_f(MAC_MODE, tp->mac_mode);
6923 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6924 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6925 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6926 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6927 tw32_f(MAC_MODE, tp->mac_mode);
6929 tw32_f(MAC_MODE, 0);
6932 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6934 err = tg3_poll_fw(tp);
6940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6943 phy_addr = tp->phy_addr;
6944 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6946 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6947 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6948 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6949 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6950 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6951 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6954 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6955 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6956 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6957 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6958 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6961 tp->phy_addr = phy_addr;
6964 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6965 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6966 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6967 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6970 tw32(0x7c00, val | (1 << 25));
6973 /* Reprobe ASF enable state. */
6974 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6975 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6976 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6977 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6980 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6981 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6982 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6983 tp->last_event_jiffies = jiffies;
6984 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6985 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6992 /* tp->lock is held. */
6993 static void tg3_stop_fw(struct tg3 *tp)
6995 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6996 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6997 /* Wait for RX cpu to ACK the previous event. */
6998 tg3_wait_for_event_ack(tp);
7000 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7002 tg3_generate_fw_event(tp);
7004 /* Wait for RX cpu to ACK this event. */
7005 tg3_wait_for_event_ack(tp);
7009 /* tp->lock is held. */
7010 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7016 tg3_write_sig_pre_reset(tp, kind);
7018 tg3_abort_hw(tp, silent);
7019 err = tg3_chip_reset(tp);
7021 __tg3_set_mac_addr(tp, 0);
7023 tg3_write_sig_legacy(tp, kind);
7024 tg3_write_sig_post_reset(tp, kind);
7032 #define RX_CPU_SCRATCH_BASE 0x30000
7033 #define RX_CPU_SCRATCH_SIZE 0x04000
7034 #define TX_CPU_SCRATCH_BASE 0x34000
7035 #define TX_CPU_SCRATCH_SIZE 0x04000
7037 /* tp->lock is held. */
7038 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7042 BUG_ON(offset == TX_CPU_BASE &&
7043 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7046 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7048 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7051 if (offset == RX_CPU_BASE) {
7052 for (i = 0; i < 10000; i++) {
7053 tw32(offset + CPU_STATE, 0xffffffff);
7054 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7055 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7059 tw32(offset + CPU_STATE, 0xffffffff);
7060 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7063 for (i = 0; i < 10000; i++) {
7064 tw32(offset + CPU_STATE, 0xffffffff);
7065 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7066 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7072 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7075 (offset == RX_CPU_BASE ? "RX" : "TX"));
7079 /* Clear firmware's nvram arbitration. */
7080 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7081 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7086 unsigned int fw_base;
7087 unsigned int fw_len;
7088 const __be32 *fw_data;
7091 /* tp->lock is held. */
7092 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7093 int cpu_scratch_size, struct fw_info *info)
7095 int err, lock_err, i;
7096 void (*write_op)(struct tg3 *, u32, u32);
7098 if (cpu_base == TX_CPU_BASE &&
7099 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7100 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7101 "TX cpu firmware on %s which is 5705.\n",
7106 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7107 write_op = tg3_write_mem;
7109 write_op = tg3_write_indirect_reg32;
7111 /* It is possible that bootcode is still loading at this point.
7112 * Get the nvram lock first before halting the cpu.
7114 lock_err = tg3_nvram_lock(tp);
7115 err = tg3_halt_cpu(tp, cpu_base);
7117 tg3_nvram_unlock(tp);
7121 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7122 write_op(tp, cpu_scratch_base + i, 0);
7123 tw32(cpu_base + CPU_STATE, 0xffffffff);
7124 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7125 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7126 write_op(tp, (cpu_scratch_base +
7127 (info->fw_base & 0xffff) +
7129 be32_to_cpu(info->fw_data[i]));
7137 /* tp->lock is held. */
7138 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7140 struct fw_info info;
7141 const __be32 *fw_data;
7144 fw_data = (void *)tp->fw->data;
7146 /* Firmware blob starts with version numbers, followed by
7147 start address and length. We are setting complete length.
7148 length = end_address_of_bss - start_address_of_text.
7149 Remainder is the blob to be loaded contiguously
7150 from start address. */
7152 info.fw_base = be32_to_cpu(fw_data[1]);
7153 info.fw_len = tp->fw->size - 12;
7154 info.fw_data = &fw_data[3];
7156 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7157 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7162 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7163 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7168 /* Now startup only the RX cpu. */
7169 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7170 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7172 for (i = 0; i < 5; i++) {
7173 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7175 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7176 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7177 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7181 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7182 "to set RX CPU PC, is %08x should be %08x\n",
7183 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7187 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7188 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7193 /* 5705 needs a special version of the TSO firmware. */
7195 /* tp->lock is held. */
7196 static int tg3_load_tso_firmware(struct tg3 *tp)
7198 struct fw_info info;
7199 const __be32 *fw_data;
7200 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7203 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7206 fw_data = (void *)tp->fw->data;
7208 /* Firmware blob starts with version numbers, followed by
7209 start address and length. We are setting complete length.
7210 length = end_address_of_bss - start_address_of_text.
7211 Remainder is the blob to be loaded contiguously
7212 from start address. */
7214 info.fw_base = be32_to_cpu(fw_data[1]);
7215 cpu_scratch_size = tp->fw_len;
7216 info.fw_len = tp->fw->size - 12;
7217 info.fw_data = &fw_data[3];
7219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7220 cpu_base = RX_CPU_BASE;
7221 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7223 cpu_base = TX_CPU_BASE;
7224 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7225 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7228 err = tg3_load_firmware_cpu(tp, cpu_base,
7229 cpu_scratch_base, cpu_scratch_size,
7234 /* Now startup the cpu. */
7235 tw32(cpu_base + CPU_STATE, 0xffffffff);
7236 tw32_f(cpu_base + CPU_PC, info.fw_base);
7238 for (i = 0; i < 5; i++) {
7239 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7241 tw32(cpu_base + CPU_STATE, 0xffffffff);
7242 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7243 tw32_f(cpu_base + CPU_PC, info.fw_base);
7247 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7248 "to set CPU PC, is %08x should be %08x\n",
7249 tp->dev->name, tr32(cpu_base + CPU_PC),
7253 tw32(cpu_base + CPU_STATE, 0xffffffff);
7254 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7259 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7261 struct tg3 *tp = netdev_priv(dev);
7262 struct sockaddr *addr = p;
7263 int err = 0, skip_mac_1 = 0;
7265 if (!is_valid_ether_addr(addr->sa_data))
7268 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7270 if (!netif_running(dev))
7273 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7274 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7276 addr0_high = tr32(MAC_ADDR_0_HIGH);
7277 addr0_low = tr32(MAC_ADDR_0_LOW);
7278 addr1_high = tr32(MAC_ADDR_1_HIGH);
7279 addr1_low = tr32(MAC_ADDR_1_LOW);
7281 /* Skip MAC addr 1 if ASF is using it. */
7282 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7283 !(addr1_high == 0 && addr1_low == 0))
7286 spin_lock_bh(&tp->lock);
7287 __tg3_set_mac_addr(tp, skip_mac_1);
7288 spin_unlock_bh(&tp->lock);
7293 /* tp->lock is held. */
7294 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7295 dma_addr_t mapping, u32 maxlen_flags,
7299 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7300 ((u64) mapping >> 32));
7302 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7303 ((u64) mapping & 0xffffffff));
7305 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7308 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7310 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7314 static void __tg3_set_rx_mode(struct net_device *);
7315 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7319 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7320 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7321 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7322 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7324 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7325 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7326 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7328 tw32(HOSTCC_TXCOL_TICKS, 0);
7329 tw32(HOSTCC_TXMAX_FRAMES, 0);
7330 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7332 tw32(HOSTCC_RXCOL_TICKS, 0);
7333 tw32(HOSTCC_RXMAX_FRAMES, 0);
7334 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7337 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7338 u32 val = ec->stats_block_coalesce_usecs;
7340 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7341 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7343 if (!netif_carrier_ok(tp->dev))
7346 tw32(HOSTCC_STAT_COAL_TICKS, val);
7349 for (i = 0; i < tp->irq_cnt - 1; i++) {
7352 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7353 tw32(reg, ec->rx_coalesce_usecs);
7354 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7355 tw32(reg, ec->tx_coalesce_usecs);
7356 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7357 tw32(reg, ec->rx_max_coalesced_frames);
7358 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7359 tw32(reg, ec->tx_max_coalesced_frames);
7360 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7361 tw32(reg, ec->rx_max_coalesced_frames_irq);
7362 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7363 tw32(reg, ec->tx_max_coalesced_frames_irq);
7366 for (; i < tp->irq_max - 1; i++) {
7367 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7368 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7369 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7370 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7371 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7372 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7376 /* tp->lock is held. */
7377 static void tg3_rings_reset(struct tg3 *tp)
7380 u32 stblk, txrcb, rxrcb, limit;
7381 struct tg3_napi *tnapi = &tp->napi[0];
7383 /* Disable all transmit rings but the first. */
7384 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7385 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7387 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7389 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7390 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7391 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7392 BDINFO_FLAGS_DISABLED);
7395 /* Disable all receive return rings but the first. */
7396 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7397 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7398 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7399 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7400 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7401 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7403 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7405 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7406 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7407 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7408 BDINFO_FLAGS_DISABLED);
7410 /* Disable interrupts */
7411 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7413 /* Zero mailbox registers. */
7414 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7415 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7416 tp->napi[i].tx_prod = 0;
7417 tp->napi[i].tx_cons = 0;
7418 tw32_mailbox(tp->napi[i].prodmbox, 0);
7419 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7420 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7423 tp->napi[0].tx_prod = 0;
7424 tp->napi[0].tx_cons = 0;
7425 tw32_mailbox(tp->napi[0].prodmbox, 0);
7426 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7429 /* Make sure the NIC-based send BD rings are disabled. */
7430 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7431 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7432 for (i = 0; i < 16; i++)
7433 tw32_tx_mbox(mbox + i * 8, 0);
7436 txrcb = NIC_SRAM_SEND_RCB;
7437 rxrcb = NIC_SRAM_RCV_RET_RCB;
7439 /* Clear status block in ram. */
7440 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7442 /* Set status block DMA address */
7443 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7444 ((u64) tnapi->status_mapping >> 32));
7445 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7446 ((u64) tnapi->status_mapping & 0xffffffff));
7448 if (tnapi->tx_ring) {
7449 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7450 (TG3_TX_RING_SIZE <<
7451 BDINFO_FLAGS_MAXLEN_SHIFT),
7452 NIC_SRAM_TX_BUFFER_DESC);
7453 txrcb += TG3_BDINFO_SIZE;
7456 if (tnapi->rx_rcb) {
7457 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7458 (TG3_RX_RCB_RING_SIZE(tp) <<
7459 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7460 rxrcb += TG3_BDINFO_SIZE;
7463 stblk = HOSTCC_STATBLCK_RING1;
7465 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7466 u64 mapping = (u64)tnapi->status_mapping;
7467 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7468 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7470 /* Clear status block in ram. */
7471 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7473 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7474 (TG3_TX_RING_SIZE <<
7475 BDINFO_FLAGS_MAXLEN_SHIFT),
7476 NIC_SRAM_TX_BUFFER_DESC);
7478 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7479 (TG3_RX_RCB_RING_SIZE(tp) <<
7480 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7483 txrcb += TG3_BDINFO_SIZE;
7484 rxrcb += TG3_BDINFO_SIZE;
7488 /* tp->lock is held. */
7489 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7491 u32 val, rdmac_mode;
7493 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7495 tg3_disable_ints(tp);
7499 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7501 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7502 tg3_abort_hw(tp, 1);
7506 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7509 err = tg3_chip_reset(tp);
7513 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7515 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7516 val = tr32(TG3_CPMU_CTRL);
7517 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7518 tw32(TG3_CPMU_CTRL, val);
7520 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7521 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7522 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7523 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7525 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7526 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7527 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7528 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7530 val = tr32(TG3_CPMU_HST_ACC);
7531 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7532 val |= CPMU_HST_ACC_MACCLK_6_25;
7533 tw32(TG3_CPMU_HST_ACC, val);
7536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7537 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7538 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7539 PCIE_PWR_MGMT_L1_THRESH_4MS;
7540 tw32(PCIE_PWR_MGMT_THRESH, val);
7542 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7543 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7545 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7547 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7548 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7551 /* This works around an issue with Athlon chipsets on
7552 * B3 tigon3 silicon. This bit has no effect on any
7553 * other revision. But do not set this on PCI Express
7554 * chips and don't even touch the clocks if the CPMU is present.
7556 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7557 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7558 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7559 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7562 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7563 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7564 val = tr32(TG3PCI_PCISTATE);
7565 val |= PCISTATE_RETRY_SAME_DMA;
7566 tw32(TG3PCI_PCISTATE, val);
7569 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7570 /* Allow reads and writes to the
7571 * APE register and memory space.
7573 val = tr32(TG3PCI_PCISTATE);
7574 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7575 PCISTATE_ALLOW_APE_SHMEM_WR;
7576 tw32(TG3PCI_PCISTATE, val);
7579 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7580 /* Enable some hw fixes. */
7581 val = tr32(TG3PCI_MSI_DATA);
7582 val |= (1 << 26) | (1 << 28) | (1 << 29);
7583 tw32(TG3PCI_MSI_DATA, val);
7586 /* Descriptor ring init may make accesses to the
7587 * NIC SRAM area to setup the TX descriptors, so we
7588 * can only do this after the hardware has been
7589 * successfully reset.
7591 err = tg3_init_rings(tp);
7595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7596 val = tr32(TG3PCI_DMA_RW_CTRL) &
7597 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7598 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7599 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7600 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7601 /* This value is determined during the probe time DMA
7602 * engine test, tg3_test_dma.
7604 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7607 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7608 GRC_MODE_4X_NIC_SEND_RINGS |
7609 GRC_MODE_NO_TX_PHDR_CSUM |
7610 GRC_MODE_NO_RX_PHDR_CSUM);
7611 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7613 /* Pseudo-header checksum is done by hardware logic and not
7614 * the offload processers, so make the chip do the pseudo-
7615 * header checksums on receive. For transmit it is more
7616 * convenient to do the pseudo-header checksum in software
7617 * as Linux does that on transmit for us in all cases.
7619 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7623 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7625 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7626 val = tr32(GRC_MISC_CFG);
7628 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7629 tw32(GRC_MISC_CFG, val);
7631 /* Initialize MBUF/DESC pool. */
7632 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7634 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7635 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7637 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7639 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7640 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7641 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7643 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7646 fw_len = tp->fw_len;
7647 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7648 tw32(BUFMGR_MB_POOL_ADDR,
7649 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7650 tw32(BUFMGR_MB_POOL_SIZE,
7651 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7654 if (tp->dev->mtu <= ETH_DATA_LEN) {
7655 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7656 tp->bufmgr_config.mbuf_read_dma_low_water);
7657 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7658 tp->bufmgr_config.mbuf_mac_rx_low_water);
7659 tw32(BUFMGR_MB_HIGH_WATER,
7660 tp->bufmgr_config.mbuf_high_water);
7662 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7663 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7664 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7665 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7666 tw32(BUFMGR_MB_HIGH_WATER,
7667 tp->bufmgr_config.mbuf_high_water_jumbo);
7669 tw32(BUFMGR_DMA_LOW_WATER,
7670 tp->bufmgr_config.dma_low_water);
7671 tw32(BUFMGR_DMA_HIGH_WATER,
7672 tp->bufmgr_config.dma_high_water);
7674 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7675 for (i = 0; i < 2000; i++) {
7676 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7681 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7686 /* Setup replenish threshold. */
7687 val = tp->rx_pending / 8;
7690 else if (val > tp->rx_std_max_post)
7691 val = tp->rx_std_max_post;
7692 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7693 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7694 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7696 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7697 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7700 tw32(RCVBDI_STD_THRESH, val);
7702 /* Initialize TG3_BDINFO's at:
7703 * RCVDBDI_STD_BD: standard eth size rx ring
7704 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7705 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7708 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7709 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7710 * ring attribute flags
7711 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7713 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7714 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7716 * The size of each ring is fixed in the firmware, but the location is
7719 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7720 ((u64) tpr->rx_std_mapping >> 32));
7721 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7722 ((u64) tpr->rx_std_mapping & 0xffffffff));
7723 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7724 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7725 NIC_SRAM_RX_BUFFER_DESC);
7727 /* Disable the mini ring */
7728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7729 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7730 BDINFO_FLAGS_DISABLED);
7732 /* Program the jumbo buffer descriptor ring control
7733 * blocks on those devices that have them.
7735 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7736 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7737 /* Setup replenish threshold. */
7738 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7740 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7741 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7742 ((u64) tpr->rx_jmb_mapping >> 32));
7743 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7744 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7745 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7746 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7747 BDINFO_FLAGS_USE_EXT_RECV);
7748 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7749 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7750 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7752 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7753 BDINFO_FLAGS_DISABLED);
7756 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7757 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7758 (RX_STD_MAX_SIZE << 2);
7760 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7762 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7764 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7766 tpr->rx_std_prod_idx = tp->rx_pending;
7767 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7769 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7770 tp->rx_jumbo_pending : 0;
7771 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7773 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7774 tw32(STD_REPLENISH_LWM, 32);
7775 tw32(JMB_REPLENISH_LWM, 16);
7778 tg3_rings_reset(tp);
7780 /* Initialize MAC address and backoff seed. */
7781 __tg3_set_mac_addr(tp, 0);
7783 /* MTU + ethernet header + FCS + optional VLAN tag */
7784 tw32(MAC_RX_MTU_SIZE,
7785 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7787 /* The slot time is changed by tg3_setup_phy if we
7788 * run at gigabit with half duplex.
7790 tw32(MAC_TX_LENGTHS,
7791 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7792 (6 << TX_LENGTHS_IPG_SHIFT) |
7793 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7795 /* Receive rules. */
7796 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7797 tw32(RCVLPC_CONFIG, 0x0181);
7799 /* Calculate RDMAC_MODE setting early, we need it to determine
7800 * the RCVLPC_STATE_ENABLE mask.
7802 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7803 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7804 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7805 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7806 RDMAC_MODE_LNGREAD_ENAB);
7808 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7809 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7811 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7812 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7813 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7815 /* If statement applies to 5705 and 5750 PCI devices only */
7816 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7817 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7818 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7819 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7821 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7822 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7823 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7824 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7828 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7829 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7831 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7832 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7834 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7837 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7839 /* Receive/send statistics. */
7840 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7841 val = tr32(RCVLPC_STATS_ENABLE);
7842 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7843 tw32(RCVLPC_STATS_ENABLE, val);
7844 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7845 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7846 val = tr32(RCVLPC_STATS_ENABLE);
7847 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7848 tw32(RCVLPC_STATS_ENABLE, val);
7850 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7852 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7853 tw32(SNDDATAI_STATSENAB, 0xffffff);
7854 tw32(SNDDATAI_STATSCTRL,
7855 (SNDDATAI_SCTRL_ENABLE |
7856 SNDDATAI_SCTRL_FASTUPD));
7858 /* Setup host coalescing engine. */
7859 tw32(HOSTCC_MODE, 0);
7860 for (i = 0; i < 2000; i++) {
7861 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7866 __tg3_set_coalesce(tp, &tp->coal);
7868 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7869 /* Status/statistics block address. See tg3_timer,
7870 * the tg3_periodic_fetch_stats call there, and
7871 * tg3_get_stats to see how this works for 5705/5750 chips.
7873 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7874 ((u64) tp->stats_mapping >> 32));
7875 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7876 ((u64) tp->stats_mapping & 0xffffffff));
7877 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7879 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7881 /* Clear statistics and status block memory areas */
7882 for (i = NIC_SRAM_STATS_BLK;
7883 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7885 tg3_write_mem(tp, i, 0);
7890 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7892 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7893 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7894 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7895 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7897 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7898 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7899 /* reset to prevent losing 1st rx packet intermittently */
7900 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7904 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7905 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7908 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7909 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7910 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7911 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7912 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7913 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7914 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7917 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7918 * If TG3_FLG2_IS_NIC is zero, we should read the
7919 * register to preserve the GPIO settings for LOMs. The GPIOs,
7920 * whether used as inputs or outputs, are set by boot code after
7923 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7926 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7927 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7928 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7931 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7932 GRC_LCLCTRL_GPIO_OUTPUT3;
7934 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7935 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7937 tp->grc_local_ctrl &= ~gpio_mask;
7938 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7940 /* GPIO1 must be driven high for eeprom write protect */
7941 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7942 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7943 GRC_LCLCTRL_GPIO_OUTPUT1);
7945 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7948 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7949 val = tr32(MSGINT_MODE);
7950 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7951 tw32(MSGINT_MODE, val);
7954 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7955 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7959 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7960 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7961 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7962 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7963 WDMAC_MODE_LNGREAD_ENAB);
7965 /* If statement applies to 5705 and 5750 PCI devices only */
7966 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7967 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7969 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7970 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7971 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7973 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7974 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7975 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7976 val |= WDMAC_MODE_RX_ACCEL;
7980 /* Enable host coalescing bug fix */
7981 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7982 val |= WDMAC_MODE_STATUS_TAG_FIX;
7984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7985 val |= WDMAC_MODE_BURST_ALL_DATA;
7987 tw32_f(WDMAC_MODE, val);
7990 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7993 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7996 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7997 pcix_cmd |= PCI_X_CMD_READ_2K;
7998 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7999 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8000 pcix_cmd |= PCI_X_CMD_READ_2K;
8002 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8006 tw32_f(RDMAC_MODE, rdmac_mode);
8009 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8010 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8011 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8015 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8017 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8019 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8020 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8021 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8022 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8023 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8024 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8025 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8026 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8027 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8028 tw32(SNDBDI_MODE, val);
8029 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8031 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8032 err = tg3_load_5701_a0_firmware_fix(tp);
8037 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8038 err = tg3_load_tso_firmware(tp);
8043 tp->tx_mode = TX_MODE_ENABLE;
8044 tw32_f(MAC_TX_MODE, tp->tx_mode);
8047 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8048 u32 reg = MAC_RSS_INDIR_TBL_0;
8049 u8 *ent = (u8 *)&val;
8051 /* Setup the indirection table */
8052 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8053 int idx = i % sizeof(val);
8055 ent[idx] = i % (tp->irq_cnt - 1);
8056 if (idx == sizeof(val) - 1) {
8062 /* Setup the "secret" hash key. */
8063 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8064 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8065 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8066 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8067 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8068 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8069 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8070 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8071 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8072 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8075 tp->rx_mode = RX_MODE_ENABLE;
8076 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8077 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8079 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8080 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8081 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8082 RX_MODE_RSS_IPV6_HASH_EN |
8083 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8084 RX_MODE_RSS_IPV4_HASH_EN |
8085 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8087 tw32_f(MAC_RX_MODE, tp->rx_mode);
8090 tw32(MAC_LED_CTRL, tp->led_ctrl);
8092 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8093 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8094 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8097 tw32_f(MAC_RX_MODE, tp->rx_mode);
8100 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8101 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8102 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8103 /* Set drive transmission level to 1.2V */
8104 /* only if the signal pre-emphasis bit is not set */
8105 val = tr32(MAC_SERDES_CFG);
8108 tw32(MAC_SERDES_CFG, val);
8110 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8111 tw32(MAC_SERDES_CFG, 0x616000);
8114 /* Prevent chip from dropping frames when flow control
8117 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
8119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8120 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8121 /* Use hardware link auto-negotiation */
8122 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8125 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8126 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8129 tmp = tr32(SERDES_RX_CTRL);
8130 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8131 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8132 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8133 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8136 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8137 if (tp->link_config.phy_is_low_power) {
8138 tp->link_config.phy_is_low_power = 0;
8139 tp->link_config.speed = tp->link_config.orig_speed;
8140 tp->link_config.duplex = tp->link_config.orig_duplex;
8141 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8144 err = tg3_setup_phy(tp, 0);
8148 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8149 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8152 /* Clear CRC stats. */
8153 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8154 tg3_writephy(tp, MII_TG3_TEST1,
8155 tmp | MII_TG3_TEST1_CRC_EN);
8156 tg3_readphy(tp, 0x14, &tmp);
8161 __tg3_set_rx_mode(tp->dev);
8163 /* Initialize receive rules. */
8164 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8165 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8166 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8167 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8169 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8170 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8174 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8178 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8180 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8182 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8184 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8186 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8188 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8190 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8192 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8194 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8196 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8198 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8200 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8202 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8204 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8212 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8213 /* Write our heartbeat update interval to APE. */
8214 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8215 APE_HOST_HEARTBEAT_INT_DISABLE);
8217 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8222 /* Called at device open time to get the chip ready for
8223 * packet processing. Invoked with tp->lock held.
8225 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8227 tg3_switch_clocks(tp);
8229 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8231 return tg3_reset_hw(tp, reset_phy);
8234 #define TG3_STAT_ADD32(PSTAT, REG) \
8235 do { u32 __val = tr32(REG); \
8236 (PSTAT)->low += __val; \
8237 if ((PSTAT)->low < __val) \
8238 (PSTAT)->high += 1; \
8241 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8243 struct tg3_hw_stats *sp = tp->hw_stats;
8245 if (!netif_carrier_ok(tp->dev))
8248 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8249 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8250 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8251 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8252 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8253 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8254 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8255 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8256 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8257 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8258 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8259 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8260 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8262 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8263 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8264 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8265 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8266 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8267 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8268 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8269 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8270 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8271 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8272 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8273 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8274 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8275 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8277 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8278 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8279 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8282 static void tg3_timer(unsigned long __opaque)
8284 struct tg3 *tp = (struct tg3 *) __opaque;
8289 spin_lock(&tp->lock);
8291 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8292 /* All of this garbage is because when using non-tagged
8293 * IRQ status the mailbox/status_block protocol the chip
8294 * uses with the cpu is race prone.
8296 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8297 tw32(GRC_LOCAL_CTRL,
8298 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8300 tw32(HOSTCC_MODE, tp->coalesce_mode |
8301 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8304 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8305 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8306 spin_unlock(&tp->lock);
8307 schedule_work(&tp->reset_task);
8312 /* This part only runs once per second. */
8313 if (!--tp->timer_counter) {
8314 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8315 tg3_periodic_fetch_stats(tp);
8317 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8321 mac_stat = tr32(MAC_STATUS);
8324 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8325 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8327 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8331 tg3_setup_phy(tp, 0);
8332 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8333 u32 mac_stat = tr32(MAC_STATUS);
8336 if (netif_carrier_ok(tp->dev) &&
8337 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8340 if (! netif_carrier_ok(tp->dev) &&
8341 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8342 MAC_STATUS_SIGNAL_DET))) {
8346 if (!tp->serdes_counter) {
8349 ~MAC_MODE_PORT_MODE_MASK));
8351 tw32_f(MAC_MODE, tp->mac_mode);
8354 tg3_setup_phy(tp, 0);
8356 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8357 tg3_serdes_parallel_detect(tp);
8359 tp->timer_counter = tp->timer_multiplier;
8362 /* Heartbeat is only sent once every 2 seconds.
8364 * The heartbeat is to tell the ASF firmware that the host
8365 * driver is still alive. In the event that the OS crashes,
8366 * ASF needs to reset the hardware to free up the FIFO space
8367 * that may be filled with rx packets destined for the host.
8368 * If the FIFO is full, ASF will no longer function properly.
8370 * Unintended resets have been reported on real time kernels
8371 * where the timer doesn't run on time. Netpoll will also have
8374 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8375 * to check the ring condition when the heartbeat is expiring
8376 * before doing the reset. This will prevent most unintended
8379 if (!--tp->asf_counter) {
8380 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8381 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8382 tg3_wait_for_event_ack(tp);
8384 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8385 FWCMD_NICDRV_ALIVE3);
8386 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8387 /* 5 seconds timeout */
8388 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8390 tg3_generate_fw_event(tp);
8392 tp->asf_counter = tp->asf_multiplier;
8395 spin_unlock(&tp->lock);
8398 tp->timer.expires = jiffies + tp->timer_offset;
8399 add_timer(&tp->timer);
8402 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8405 unsigned long flags;
8407 struct tg3_napi *tnapi = &tp->napi[irq_num];
8409 if (tp->irq_cnt == 1)
8410 name = tp->dev->name;
8412 name = &tnapi->irq_lbl[0];
8413 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8414 name[IFNAMSIZ-1] = 0;
8417 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8419 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8421 flags = IRQF_SAMPLE_RANDOM;
8424 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8425 fn = tg3_interrupt_tagged;
8426 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8429 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8432 static int tg3_test_interrupt(struct tg3 *tp)
8434 struct tg3_napi *tnapi = &tp->napi[0];
8435 struct net_device *dev = tp->dev;
8436 int err, i, intr_ok = 0;
8439 if (!netif_running(dev))
8442 tg3_disable_ints(tp);
8444 free_irq(tnapi->irq_vec, tnapi);
8447 * Turn off MSI one shot mode. Otherwise this test has no
8448 * observable way to know whether the interrupt was delivered.
8450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8451 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8452 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8453 tw32(MSGINT_MODE, val);
8456 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8457 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8461 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8462 tg3_enable_ints(tp);
8464 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8467 for (i = 0; i < 5; i++) {
8468 u32 int_mbox, misc_host_ctrl;
8470 int_mbox = tr32_mailbox(tnapi->int_mbox);
8471 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8473 if ((int_mbox != 0) ||
8474 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8482 tg3_disable_ints(tp);
8484 free_irq(tnapi->irq_vec, tnapi);
8486 err = tg3_request_irq(tp, 0);
8492 /* Reenable MSI one shot mode. */
8493 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8494 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8495 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8496 tw32(MSGINT_MODE, val);
8504 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8505 * successfully restored
8507 static int tg3_test_msi(struct tg3 *tp)
8512 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8515 /* Turn off SERR reporting in case MSI terminates with Master
8518 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8519 pci_write_config_word(tp->pdev, PCI_COMMAND,
8520 pci_cmd & ~PCI_COMMAND_SERR);
8522 err = tg3_test_interrupt(tp);
8524 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8529 /* other failures */
8533 /* MSI test failed, go back to INTx mode */
8534 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8535 "switching to INTx mode. Please report this failure to "
8536 "the PCI maintainer and include system chipset information.\n",
8539 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8541 pci_disable_msi(tp->pdev);
8543 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8545 err = tg3_request_irq(tp, 0);
8549 /* Need to reset the chip because the MSI cycle may have terminated
8550 * with Master Abort.
8552 tg3_full_lock(tp, 1);
8554 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8555 err = tg3_init_hw(tp, 1);
8557 tg3_full_unlock(tp);
8560 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8565 static int tg3_request_firmware(struct tg3 *tp)
8567 const __be32 *fw_data;
8569 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8570 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8571 tp->dev->name, tp->fw_needed);
8575 fw_data = (void *)tp->fw->data;
8577 /* Firmware blob starts with version numbers, followed by
8578 * start address and _full_ length including BSS sections
8579 * (which must be longer than the actual data, of course
8582 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8583 if (tp->fw_len < (tp->fw->size - 12)) {
8584 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8585 tp->dev->name, tp->fw_len, tp->fw_needed);
8586 release_firmware(tp->fw);
8591 /* We no longer need firmware; we have it. */
8592 tp->fw_needed = NULL;
8596 static bool tg3_enable_msix(struct tg3 *tp)
8598 int i, rc, cpus = num_online_cpus();
8599 struct msix_entry msix_ent[tp->irq_max];
8602 /* Just fallback to the simpler MSI mode. */
8606 * We want as many rx rings enabled as there are cpus.
8607 * The first MSIX vector only deals with link interrupts, etc,
8608 * so we add one to the number of vectors we are requesting.
8610 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8612 for (i = 0; i < tp->irq_max; i++) {
8613 msix_ent[i].entry = i;
8614 msix_ent[i].vector = 0;
8617 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8619 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8621 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8624 "%s: Requested %d MSI-X vectors, received %d\n",
8625 tp->dev->name, tp->irq_cnt, rc);
8629 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8631 for (i = 0; i < tp->irq_max; i++)
8632 tp->napi[i].irq_vec = msix_ent[i].vector;
8634 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8639 static void tg3_ints_init(struct tg3 *tp)
8641 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8642 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8643 /* All MSI supporting chips should support tagged
8644 * status. Assert that this is the case.
8646 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8647 "Not using MSI.\n", tp->dev->name);
8651 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8652 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8653 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8654 pci_enable_msi(tp->pdev) == 0)
8655 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8657 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8658 u32 msi_mode = tr32(MSGINT_MODE);
8659 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8660 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8661 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8664 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8666 tp->napi[0].irq_vec = tp->pdev->irq;
8667 tp->dev->real_num_tx_queues = 1;
8671 static void tg3_ints_fini(struct tg3 *tp)
8673 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8674 pci_disable_msix(tp->pdev);
8675 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8676 pci_disable_msi(tp->pdev);
8677 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8678 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8681 static int tg3_open(struct net_device *dev)
8683 struct tg3 *tp = netdev_priv(dev);
8686 if (tp->fw_needed) {
8687 err = tg3_request_firmware(tp);
8688 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8692 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8694 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8695 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8696 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8698 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8702 netif_carrier_off(tp->dev);
8704 err = tg3_set_power_state(tp, PCI_D0);
8708 tg3_full_lock(tp, 0);
8710 tg3_disable_ints(tp);
8711 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8713 tg3_full_unlock(tp);
8716 * Setup interrupts first so we know how
8717 * many NAPI resources to allocate
8721 /* The placement of this call is tied
8722 * to the setup and use of Host TX descriptors.
8724 err = tg3_alloc_consistent(tp);
8728 tg3_napi_enable(tp);
8730 for (i = 0; i < tp->irq_cnt; i++) {
8731 struct tg3_napi *tnapi = &tp->napi[i];
8732 err = tg3_request_irq(tp, i);
8734 for (i--; i >= 0; i--)
8735 free_irq(tnapi->irq_vec, tnapi);
8743 tg3_full_lock(tp, 0);
8745 err = tg3_init_hw(tp, 1);
8747 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8750 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8751 tp->timer_offset = HZ;
8753 tp->timer_offset = HZ / 10;
8755 BUG_ON(tp->timer_offset > HZ);
8756 tp->timer_counter = tp->timer_multiplier =
8757 (HZ / tp->timer_offset);
8758 tp->asf_counter = tp->asf_multiplier =
8759 ((HZ / tp->timer_offset) * 2);
8761 init_timer(&tp->timer);
8762 tp->timer.expires = jiffies + tp->timer_offset;
8763 tp->timer.data = (unsigned long) tp;
8764 tp->timer.function = tg3_timer;
8767 tg3_full_unlock(tp);
8772 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8773 err = tg3_test_msi(tp);
8776 tg3_full_lock(tp, 0);
8777 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8779 tg3_full_unlock(tp);
8784 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8785 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8786 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8787 u32 val = tr32(PCIE_TRANSACTION_CFG);
8789 tw32(PCIE_TRANSACTION_CFG,
8790 val | PCIE_TRANS_CFG_1SHOT_MSI);
8796 tg3_full_lock(tp, 0);
8798 add_timer(&tp->timer);
8799 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8800 tg3_enable_ints(tp);
8802 tg3_full_unlock(tp);
8804 netif_tx_start_all_queues(dev);
8809 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8810 struct tg3_napi *tnapi = &tp->napi[i];
8811 free_irq(tnapi->irq_vec, tnapi);
8815 tg3_napi_disable(tp);
8816 tg3_free_consistent(tp);
8824 /*static*/ void tg3_dump_state(struct tg3 *tp)
8826 u32 val32, val32_2, val32_3, val32_4, val32_5;
8829 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8831 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8832 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8833 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8837 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8838 tr32(MAC_MODE), tr32(MAC_STATUS));
8839 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8840 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8841 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8842 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8843 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8844 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8846 /* Send data initiator control block */
8847 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8848 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8849 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8850 tr32(SNDDATAI_STATSCTRL));
8852 /* Send data completion control block */
8853 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8855 /* Send BD ring selector block */
8856 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8857 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8859 /* Send BD initiator control block */
8860 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8861 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8863 /* Send BD completion control block */
8864 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8866 /* Receive list placement control block */
8867 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8868 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8869 printk(" RCVLPC_STATSCTRL[%08x]\n",
8870 tr32(RCVLPC_STATSCTRL));
8872 /* Receive data and receive BD initiator control block */
8873 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8874 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8876 /* Receive data completion control block */
8877 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8880 /* Receive BD initiator control block */
8881 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8882 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8884 /* Receive BD completion control block */
8885 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8886 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8888 /* Receive list selector control block */
8889 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8890 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8892 /* Mbuf cluster free block */
8893 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8894 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8896 /* Host coalescing control block */
8897 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8898 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8899 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8900 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8901 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8902 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8903 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8904 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8905 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8906 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8907 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8908 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8910 /* Memory arbiter control block */
8911 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8912 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8914 /* Buffer manager control block */
8915 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8916 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8917 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8918 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8919 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8920 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8921 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8922 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8924 /* Read DMA control block */
8925 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8926 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8928 /* Write DMA control block */
8929 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8930 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8932 /* DMA completion block */
8933 printk("DEBUG: DMAC_MODE[%08x]\n",
8937 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8938 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8939 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8940 tr32(GRC_LOCAL_CTRL));
8943 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8944 tr32(RCVDBDI_JUMBO_BD + 0x0),
8945 tr32(RCVDBDI_JUMBO_BD + 0x4),
8946 tr32(RCVDBDI_JUMBO_BD + 0x8),
8947 tr32(RCVDBDI_JUMBO_BD + 0xc));
8948 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8949 tr32(RCVDBDI_STD_BD + 0x0),
8950 tr32(RCVDBDI_STD_BD + 0x4),
8951 tr32(RCVDBDI_STD_BD + 0x8),
8952 tr32(RCVDBDI_STD_BD + 0xc));
8953 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8954 tr32(RCVDBDI_MINI_BD + 0x0),
8955 tr32(RCVDBDI_MINI_BD + 0x4),
8956 tr32(RCVDBDI_MINI_BD + 0x8),
8957 tr32(RCVDBDI_MINI_BD + 0xc));
8959 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8960 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8961 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8962 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8963 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8964 val32, val32_2, val32_3, val32_4);
8966 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8967 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8968 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8969 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8970 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8971 val32, val32_2, val32_3, val32_4);
8973 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8974 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8975 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8976 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8977 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8978 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8979 val32, val32_2, val32_3, val32_4, val32_5);
8981 /* SW status block */
8983 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8986 sblk->rx_jumbo_consumer,
8988 sblk->rx_mini_consumer,
8989 sblk->idx[0].rx_producer,
8990 sblk->idx[0].tx_consumer);
8992 /* SW statistics block */
8993 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8994 ((u32 *)tp->hw_stats)[0],
8995 ((u32 *)tp->hw_stats)[1],
8996 ((u32 *)tp->hw_stats)[2],
8997 ((u32 *)tp->hw_stats)[3]);
9000 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9001 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9002 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9003 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9004 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9006 /* NIC side send descriptors. */
9007 for (i = 0; i < 6; i++) {
9010 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9011 + (i * sizeof(struct tg3_tx_buffer_desc));
9012 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9014 readl(txd + 0x0), readl(txd + 0x4),
9015 readl(txd + 0x8), readl(txd + 0xc));
9018 /* NIC side RX descriptors. */
9019 for (i = 0; i < 6; i++) {
9022 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9023 + (i * sizeof(struct tg3_rx_buffer_desc));
9024 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9026 readl(rxd + 0x0), readl(rxd + 0x4),
9027 readl(rxd + 0x8), readl(rxd + 0xc));
9028 rxd += (4 * sizeof(u32));
9029 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9031 readl(rxd + 0x0), readl(rxd + 0x4),
9032 readl(rxd + 0x8), readl(rxd + 0xc));
9035 for (i = 0; i < 6; i++) {
9038 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9039 + (i * sizeof(struct tg3_rx_buffer_desc));
9040 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9042 readl(rxd + 0x0), readl(rxd + 0x4),
9043 readl(rxd + 0x8), readl(rxd + 0xc));
9044 rxd += (4 * sizeof(u32));
9045 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9047 readl(rxd + 0x0), readl(rxd + 0x4),
9048 readl(rxd + 0x8), readl(rxd + 0xc));
9053 static struct net_device_stats *tg3_get_stats(struct net_device *);
9054 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9056 static int tg3_close(struct net_device *dev)
9059 struct tg3 *tp = netdev_priv(dev);
9061 tg3_napi_disable(tp);
9062 cancel_work_sync(&tp->reset_task);
9064 netif_tx_stop_all_queues(dev);
9066 del_timer_sync(&tp->timer);
9070 tg3_full_lock(tp, 1);
9075 tg3_disable_ints(tp);
9077 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9079 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9081 tg3_full_unlock(tp);
9083 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9084 struct tg3_napi *tnapi = &tp->napi[i];
9085 free_irq(tnapi->irq_vec, tnapi);
9090 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9091 sizeof(tp->net_stats_prev));
9092 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9093 sizeof(tp->estats_prev));
9095 tg3_free_consistent(tp);
9097 tg3_set_power_state(tp, PCI_D3hot);
9099 netif_carrier_off(tp->dev);
9104 static inline unsigned long get_stat64(tg3_stat64_t *val)
9108 #if (BITS_PER_LONG == 32)
9111 ret = ((u64)val->high << 32) | ((u64)val->low);
9116 static inline u64 get_estat64(tg3_stat64_t *val)
9118 return ((u64)val->high << 32) | ((u64)val->low);
9121 static unsigned long calc_crc_errors(struct tg3 *tp)
9123 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9125 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9126 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9130 spin_lock_bh(&tp->lock);
9131 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9132 tg3_writephy(tp, MII_TG3_TEST1,
9133 val | MII_TG3_TEST1_CRC_EN);
9134 tg3_readphy(tp, 0x14, &val);
9137 spin_unlock_bh(&tp->lock);
9139 tp->phy_crc_errors += val;
9141 return tp->phy_crc_errors;
9144 return get_stat64(&hw_stats->rx_fcs_errors);
9147 #define ESTAT_ADD(member) \
9148 estats->member = old_estats->member + \
9149 get_estat64(&hw_stats->member)
9151 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9153 struct tg3_ethtool_stats *estats = &tp->estats;
9154 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9155 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9160 ESTAT_ADD(rx_octets);
9161 ESTAT_ADD(rx_fragments);
9162 ESTAT_ADD(rx_ucast_packets);
9163 ESTAT_ADD(rx_mcast_packets);
9164 ESTAT_ADD(rx_bcast_packets);
9165 ESTAT_ADD(rx_fcs_errors);
9166 ESTAT_ADD(rx_align_errors);
9167 ESTAT_ADD(rx_xon_pause_rcvd);
9168 ESTAT_ADD(rx_xoff_pause_rcvd);
9169 ESTAT_ADD(rx_mac_ctrl_rcvd);
9170 ESTAT_ADD(rx_xoff_entered);
9171 ESTAT_ADD(rx_frame_too_long_errors);
9172 ESTAT_ADD(rx_jabbers);
9173 ESTAT_ADD(rx_undersize_packets);
9174 ESTAT_ADD(rx_in_length_errors);
9175 ESTAT_ADD(rx_out_length_errors);
9176 ESTAT_ADD(rx_64_or_less_octet_packets);
9177 ESTAT_ADD(rx_65_to_127_octet_packets);
9178 ESTAT_ADD(rx_128_to_255_octet_packets);
9179 ESTAT_ADD(rx_256_to_511_octet_packets);
9180 ESTAT_ADD(rx_512_to_1023_octet_packets);
9181 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9182 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9183 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9184 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9185 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9187 ESTAT_ADD(tx_octets);
9188 ESTAT_ADD(tx_collisions);
9189 ESTAT_ADD(tx_xon_sent);
9190 ESTAT_ADD(tx_xoff_sent);
9191 ESTAT_ADD(tx_flow_control);
9192 ESTAT_ADD(tx_mac_errors);
9193 ESTAT_ADD(tx_single_collisions);
9194 ESTAT_ADD(tx_mult_collisions);
9195 ESTAT_ADD(tx_deferred);
9196 ESTAT_ADD(tx_excessive_collisions);
9197 ESTAT_ADD(tx_late_collisions);
9198 ESTAT_ADD(tx_collide_2times);
9199 ESTAT_ADD(tx_collide_3times);
9200 ESTAT_ADD(tx_collide_4times);
9201 ESTAT_ADD(tx_collide_5times);
9202 ESTAT_ADD(tx_collide_6times);
9203 ESTAT_ADD(tx_collide_7times);
9204 ESTAT_ADD(tx_collide_8times);
9205 ESTAT_ADD(tx_collide_9times);
9206 ESTAT_ADD(tx_collide_10times);
9207 ESTAT_ADD(tx_collide_11times);
9208 ESTAT_ADD(tx_collide_12times);
9209 ESTAT_ADD(tx_collide_13times);
9210 ESTAT_ADD(tx_collide_14times);
9211 ESTAT_ADD(tx_collide_15times);
9212 ESTAT_ADD(tx_ucast_packets);
9213 ESTAT_ADD(tx_mcast_packets);
9214 ESTAT_ADD(tx_bcast_packets);
9215 ESTAT_ADD(tx_carrier_sense_errors);
9216 ESTAT_ADD(tx_discards);
9217 ESTAT_ADD(tx_errors);
9219 ESTAT_ADD(dma_writeq_full);
9220 ESTAT_ADD(dma_write_prioq_full);
9221 ESTAT_ADD(rxbds_empty);
9222 ESTAT_ADD(rx_discards);
9223 ESTAT_ADD(rx_errors);
9224 ESTAT_ADD(rx_threshold_hit);
9226 ESTAT_ADD(dma_readq_full);
9227 ESTAT_ADD(dma_read_prioq_full);
9228 ESTAT_ADD(tx_comp_queue_full);
9230 ESTAT_ADD(ring_set_send_prod_index);
9231 ESTAT_ADD(ring_status_update);
9232 ESTAT_ADD(nic_irqs);
9233 ESTAT_ADD(nic_avoided_irqs);
9234 ESTAT_ADD(nic_tx_threshold_hit);
9239 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9241 struct tg3 *tp = netdev_priv(dev);
9242 struct net_device_stats *stats = &tp->net_stats;
9243 struct net_device_stats *old_stats = &tp->net_stats_prev;
9244 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9249 stats->rx_packets = old_stats->rx_packets +
9250 get_stat64(&hw_stats->rx_ucast_packets) +
9251 get_stat64(&hw_stats->rx_mcast_packets) +
9252 get_stat64(&hw_stats->rx_bcast_packets);
9254 stats->tx_packets = old_stats->tx_packets +
9255 get_stat64(&hw_stats->tx_ucast_packets) +
9256 get_stat64(&hw_stats->tx_mcast_packets) +
9257 get_stat64(&hw_stats->tx_bcast_packets);
9259 stats->rx_bytes = old_stats->rx_bytes +
9260 get_stat64(&hw_stats->rx_octets);
9261 stats->tx_bytes = old_stats->tx_bytes +
9262 get_stat64(&hw_stats->tx_octets);
9264 stats->rx_errors = old_stats->rx_errors +
9265 get_stat64(&hw_stats->rx_errors);
9266 stats->tx_errors = old_stats->tx_errors +
9267 get_stat64(&hw_stats->tx_errors) +
9268 get_stat64(&hw_stats->tx_mac_errors) +
9269 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9270 get_stat64(&hw_stats->tx_discards);
9272 stats->multicast = old_stats->multicast +
9273 get_stat64(&hw_stats->rx_mcast_packets);
9274 stats->collisions = old_stats->collisions +
9275 get_stat64(&hw_stats->tx_collisions);
9277 stats->rx_length_errors = old_stats->rx_length_errors +
9278 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9279 get_stat64(&hw_stats->rx_undersize_packets);
9281 stats->rx_over_errors = old_stats->rx_over_errors +
9282 get_stat64(&hw_stats->rxbds_empty);
9283 stats->rx_frame_errors = old_stats->rx_frame_errors +
9284 get_stat64(&hw_stats->rx_align_errors);
9285 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9286 get_stat64(&hw_stats->tx_discards);
9287 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9288 get_stat64(&hw_stats->tx_carrier_sense_errors);
9290 stats->rx_crc_errors = old_stats->rx_crc_errors +
9291 calc_crc_errors(tp);
9293 stats->rx_missed_errors = old_stats->rx_missed_errors +
9294 get_stat64(&hw_stats->rx_discards);
9299 static inline u32 calc_crc(unsigned char *buf, int len)
9307 for (j = 0; j < len; j++) {
9310 for (k = 0; k < 8; k++) {
9324 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9326 /* accept or reject all multicast frames */
9327 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9328 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9329 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9330 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9333 static void __tg3_set_rx_mode(struct net_device *dev)
9335 struct tg3 *tp = netdev_priv(dev);
9338 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9339 RX_MODE_KEEP_VLAN_TAG);
9341 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9344 #if TG3_VLAN_TAG_USED
9346 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9347 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9349 /* By definition, VLAN is disabled always in this
9352 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9353 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9356 if (dev->flags & IFF_PROMISC) {
9357 /* Promiscuous mode. */
9358 rx_mode |= RX_MODE_PROMISC;
9359 } else if (dev->flags & IFF_ALLMULTI) {
9360 /* Accept all multicast. */
9361 tg3_set_multi (tp, 1);
9362 } else if (dev->mc_count < 1) {
9363 /* Reject all multicast. */
9364 tg3_set_multi (tp, 0);
9366 /* Accept one or more multicast(s). */
9367 struct dev_mc_list *mclist;
9369 u32 mc_filter[4] = { 0, };
9374 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9375 i++, mclist = mclist->next) {
9377 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9379 regidx = (bit & 0x60) >> 5;
9381 mc_filter[regidx] |= (1 << bit);
9384 tw32(MAC_HASH_REG_0, mc_filter[0]);
9385 tw32(MAC_HASH_REG_1, mc_filter[1]);
9386 tw32(MAC_HASH_REG_2, mc_filter[2]);
9387 tw32(MAC_HASH_REG_3, mc_filter[3]);
9390 if (rx_mode != tp->rx_mode) {
9391 tp->rx_mode = rx_mode;
9392 tw32_f(MAC_RX_MODE, rx_mode);
9397 static void tg3_set_rx_mode(struct net_device *dev)
9399 struct tg3 *tp = netdev_priv(dev);
9401 if (!netif_running(dev))
9404 tg3_full_lock(tp, 0);
9405 __tg3_set_rx_mode(dev);
9406 tg3_full_unlock(tp);
9409 #define TG3_REGDUMP_LEN (32 * 1024)
9411 static int tg3_get_regs_len(struct net_device *dev)
9413 return TG3_REGDUMP_LEN;
9416 static void tg3_get_regs(struct net_device *dev,
9417 struct ethtool_regs *regs, void *_p)
9420 struct tg3 *tp = netdev_priv(dev);
9426 memset(p, 0, TG3_REGDUMP_LEN);
9428 if (tp->link_config.phy_is_low_power)
9431 tg3_full_lock(tp, 0);
9433 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9434 #define GET_REG32_LOOP(base,len) \
9435 do { p = (u32 *)(orig_p + (base)); \
9436 for (i = 0; i < len; i += 4) \
9437 __GET_REG32((base) + i); \
9439 #define GET_REG32_1(reg) \
9440 do { p = (u32 *)(orig_p + (reg)); \
9441 __GET_REG32((reg)); \
9444 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9445 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9446 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9447 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9448 GET_REG32_1(SNDDATAC_MODE);
9449 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9450 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9451 GET_REG32_1(SNDBDC_MODE);
9452 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9453 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9454 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9455 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9456 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9457 GET_REG32_1(RCVDCC_MODE);
9458 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9459 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9460 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9461 GET_REG32_1(MBFREE_MODE);
9462 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9463 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9464 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9465 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9466 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9467 GET_REG32_1(RX_CPU_MODE);
9468 GET_REG32_1(RX_CPU_STATE);
9469 GET_REG32_1(RX_CPU_PGMCTR);
9470 GET_REG32_1(RX_CPU_HWBKPT);
9471 GET_REG32_1(TX_CPU_MODE);
9472 GET_REG32_1(TX_CPU_STATE);
9473 GET_REG32_1(TX_CPU_PGMCTR);
9474 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9475 GET_REG32_LOOP(FTQ_RESET, 0x120);
9476 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9477 GET_REG32_1(DMAC_MODE);
9478 GET_REG32_LOOP(GRC_MODE, 0x4c);
9479 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9480 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9483 #undef GET_REG32_LOOP
9486 tg3_full_unlock(tp);
9489 static int tg3_get_eeprom_len(struct net_device *dev)
9491 struct tg3 *tp = netdev_priv(dev);
9493 return tp->nvram_size;
9496 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9498 struct tg3 *tp = netdev_priv(dev);
9501 u32 i, offset, len, b_offset, b_count;
9504 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9507 if (tp->link_config.phy_is_low_power)
9510 offset = eeprom->offset;
9514 eeprom->magic = TG3_EEPROM_MAGIC;
9517 /* adjustments to start on required 4 byte boundary */
9518 b_offset = offset & 3;
9519 b_count = 4 - b_offset;
9520 if (b_count > len) {
9521 /* i.e. offset=1 len=2 */
9524 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9527 memcpy(data, ((char*)&val) + b_offset, b_count);
9530 eeprom->len += b_count;
9533 /* read bytes upto the last 4 byte boundary */
9534 pd = &data[eeprom->len];
9535 for (i = 0; i < (len - (len & 3)); i += 4) {
9536 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9541 memcpy(pd + i, &val, 4);
9546 /* read last bytes not ending on 4 byte boundary */
9547 pd = &data[eeprom->len];
9549 b_offset = offset + len - b_count;
9550 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9553 memcpy(pd, &val, b_count);
9554 eeprom->len += b_count;
9559 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9561 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9563 struct tg3 *tp = netdev_priv(dev);
9565 u32 offset, len, b_offset, odd_len;
9569 if (tp->link_config.phy_is_low_power)
9572 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9573 eeprom->magic != TG3_EEPROM_MAGIC)
9576 offset = eeprom->offset;
9579 if ((b_offset = (offset & 3))) {
9580 /* adjustments to start on required 4 byte boundary */
9581 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9592 /* adjustments to end on required 4 byte boundary */
9594 len = (len + 3) & ~3;
9595 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9601 if (b_offset || odd_len) {
9602 buf = kmalloc(len, GFP_KERNEL);
9606 memcpy(buf, &start, 4);
9608 memcpy(buf+len-4, &end, 4);
9609 memcpy(buf + b_offset, data, eeprom->len);
9612 ret = tg3_nvram_write_block(tp, offset, len, buf);
9620 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9622 struct tg3 *tp = netdev_priv(dev);
9624 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9625 struct phy_device *phydev;
9626 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9628 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9629 return phy_ethtool_gset(phydev, cmd);
9632 cmd->supported = (SUPPORTED_Autoneg);
9634 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9635 cmd->supported |= (SUPPORTED_1000baseT_Half |
9636 SUPPORTED_1000baseT_Full);
9638 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9639 cmd->supported |= (SUPPORTED_100baseT_Half |
9640 SUPPORTED_100baseT_Full |
9641 SUPPORTED_10baseT_Half |
9642 SUPPORTED_10baseT_Full |
9644 cmd->port = PORT_TP;
9646 cmd->supported |= SUPPORTED_FIBRE;
9647 cmd->port = PORT_FIBRE;
9650 cmd->advertising = tp->link_config.advertising;
9651 if (netif_running(dev)) {
9652 cmd->speed = tp->link_config.active_speed;
9653 cmd->duplex = tp->link_config.active_duplex;
9655 cmd->phy_address = tp->phy_addr;
9656 cmd->transceiver = XCVR_INTERNAL;
9657 cmd->autoneg = tp->link_config.autoneg;
9663 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9665 struct tg3 *tp = netdev_priv(dev);
9667 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9668 struct phy_device *phydev;
9669 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9671 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9672 return phy_ethtool_sset(phydev, cmd);
9675 if (cmd->autoneg != AUTONEG_ENABLE &&
9676 cmd->autoneg != AUTONEG_DISABLE)
9679 if (cmd->autoneg == AUTONEG_DISABLE &&
9680 cmd->duplex != DUPLEX_FULL &&
9681 cmd->duplex != DUPLEX_HALF)
9684 if (cmd->autoneg == AUTONEG_ENABLE) {
9685 u32 mask = ADVERTISED_Autoneg |
9687 ADVERTISED_Asym_Pause;
9689 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9690 mask |= ADVERTISED_1000baseT_Half |
9691 ADVERTISED_1000baseT_Full;
9693 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9694 mask |= ADVERTISED_100baseT_Half |
9695 ADVERTISED_100baseT_Full |
9696 ADVERTISED_10baseT_Half |
9697 ADVERTISED_10baseT_Full |
9700 mask |= ADVERTISED_FIBRE;
9702 if (cmd->advertising & ~mask)
9705 mask &= (ADVERTISED_1000baseT_Half |
9706 ADVERTISED_1000baseT_Full |
9707 ADVERTISED_100baseT_Half |
9708 ADVERTISED_100baseT_Full |
9709 ADVERTISED_10baseT_Half |
9710 ADVERTISED_10baseT_Full);
9712 cmd->advertising &= mask;
9714 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9715 if (cmd->speed != SPEED_1000)
9718 if (cmd->duplex != DUPLEX_FULL)
9721 if (cmd->speed != SPEED_100 &&
9722 cmd->speed != SPEED_10)
9727 tg3_full_lock(tp, 0);
9729 tp->link_config.autoneg = cmd->autoneg;
9730 if (cmd->autoneg == AUTONEG_ENABLE) {
9731 tp->link_config.advertising = (cmd->advertising |
9732 ADVERTISED_Autoneg);
9733 tp->link_config.speed = SPEED_INVALID;
9734 tp->link_config.duplex = DUPLEX_INVALID;
9736 tp->link_config.advertising = 0;
9737 tp->link_config.speed = cmd->speed;
9738 tp->link_config.duplex = cmd->duplex;
9741 tp->link_config.orig_speed = tp->link_config.speed;
9742 tp->link_config.orig_duplex = tp->link_config.duplex;
9743 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9745 if (netif_running(dev))
9746 tg3_setup_phy(tp, 1);
9748 tg3_full_unlock(tp);
9753 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9755 struct tg3 *tp = netdev_priv(dev);
9757 strcpy(info->driver, DRV_MODULE_NAME);
9758 strcpy(info->version, DRV_MODULE_VERSION);
9759 strcpy(info->fw_version, tp->fw_ver);
9760 strcpy(info->bus_info, pci_name(tp->pdev));
9763 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9765 struct tg3 *tp = netdev_priv(dev);
9767 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9768 device_can_wakeup(&tp->pdev->dev))
9769 wol->supported = WAKE_MAGIC;
9773 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9774 device_can_wakeup(&tp->pdev->dev))
9775 wol->wolopts = WAKE_MAGIC;
9776 memset(&wol->sopass, 0, sizeof(wol->sopass));
9779 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9781 struct tg3 *tp = netdev_priv(dev);
9782 struct device *dp = &tp->pdev->dev;
9784 if (wol->wolopts & ~WAKE_MAGIC)
9786 if ((wol->wolopts & WAKE_MAGIC) &&
9787 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9790 spin_lock_bh(&tp->lock);
9791 if (wol->wolopts & WAKE_MAGIC) {
9792 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9793 device_set_wakeup_enable(dp, true);
9795 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9796 device_set_wakeup_enable(dp, false);
9798 spin_unlock_bh(&tp->lock);
9803 static u32 tg3_get_msglevel(struct net_device *dev)
9805 struct tg3 *tp = netdev_priv(dev);
9806 return tp->msg_enable;
9809 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9811 struct tg3 *tp = netdev_priv(dev);
9812 tp->msg_enable = value;
9815 static int tg3_set_tso(struct net_device *dev, u32 value)
9817 struct tg3 *tp = netdev_priv(dev);
9819 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9824 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9825 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9826 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9828 dev->features |= NETIF_F_TSO6;
9829 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9830 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9831 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9832 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9833 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9835 dev->features |= NETIF_F_TSO_ECN;
9837 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9839 return ethtool_op_set_tso(dev, value);
9842 static int tg3_nway_reset(struct net_device *dev)
9844 struct tg3 *tp = netdev_priv(dev);
9847 if (!netif_running(dev))
9850 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9853 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9854 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9856 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9860 spin_lock_bh(&tp->lock);
9862 tg3_readphy(tp, MII_BMCR, &bmcr);
9863 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9864 ((bmcr & BMCR_ANENABLE) ||
9865 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9866 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9870 spin_unlock_bh(&tp->lock);
9876 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9878 struct tg3 *tp = netdev_priv(dev);
9880 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9881 ering->rx_mini_max_pending = 0;
9882 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9883 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9885 ering->rx_jumbo_max_pending = 0;
9887 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9889 ering->rx_pending = tp->rx_pending;
9890 ering->rx_mini_pending = 0;
9891 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9892 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9894 ering->rx_jumbo_pending = 0;
9896 ering->tx_pending = tp->napi[0].tx_pending;
9899 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9901 struct tg3 *tp = netdev_priv(dev);
9902 int i, irq_sync = 0, err = 0;
9904 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9905 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9906 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9907 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9908 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9909 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9912 if (netif_running(dev)) {
9918 tg3_full_lock(tp, irq_sync);
9920 tp->rx_pending = ering->rx_pending;
9922 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9923 tp->rx_pending > 63)
9924 tp->rx_pending = 63;
9925 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9927 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9928 tp->napi[i].tx_pending = ering->tx_pending;
9930 if (netif_running(dev)) {
9931 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9932 err = tg3_restart_hw(tp, 1);
9934 tg3_netif_start(tp);
9937 tg3_full_unlock(tp);
9939 if (irq_sync && !err)
9945 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9947 struct tg3 *tp = netdev_priv(dev);
9949 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9951 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9952 epause->rx_pause = 1;
9954 epause->rx_pause = 0;
9956 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9957 epause->tx_pause = 1;
9959 epause->tx_pause = 0;
9962 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9964 struct tg3 *tp = netdev_priv(dev);
9967 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9968 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9971 if (epause->autoneg) {
9973 struct phy_device *phydev;
9975 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9977 if (epause->rx_pause) {
9978 if (epause->tx_pause)
9979 newadv = ADVERTISED_Pause;
9981 newadv = ADVERTISED_Pause |
9982 ADVERTISED_Asym_Pause;
9983 } else if (epause->tx_pause) {
9984 newadv = ADVERTISED_Asym_Pause;
9988 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9989 u32 oldadv = phydev->advertising &
9991 ADVERTISED_Asym_Pause);
9992 if (oldadv != newadv) {
9993 phydev->advertising &=
9994 ~(ADVERTISED_Pause |
9995 ADVERTISED_Asym_Pause);
9996 phydev->advertising |= newadv;
9997 err = phy_start_aneg(phydev);
10000 tp->link_config.advertising &=
10001 ~(ADVERTISED_Pause |
10002 ADVERTISED_Asym_Pause);
10003 tp->link_config.advertising |= newadv;
10006 if (epause->rx_pause)
10007 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10009 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10011 if (epause->tx_pause)
10012 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10014 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10016 if (netif_running(dev))
10017 tg3_setup_flow_control(tp, 0, 0);
10022 if (netif_running(dev)) {
10023 tg3_netif_stop(tp);
10027 tg3_full_lock(tp, irq_sync);
10029 if (epause->autoneg)
10030 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10032 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10033 if (epause->rx_pause)
10034 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10036 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10037 if (epause->tx_pause)
10038 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10040 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10042 if (netif_running(dev)) {
10043 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10044 err = tg3_restart_hw(tp, 1);
10046 tg3_netif_start(tp);
10049 tg3_full_unlock(tp);
10055 static u32 tg3_get_rx_csum(struct net_device *dev)
10057 struct tg3 *tp = netdev_priv(dev);
10058 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10061 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10063 struct tg3 *tp = netdev_priv(dev);
10065 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10071 spin_lock_bh(&tp->lock);
10073 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10075 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10076 spin_unlock_bh(&tp->lock);
10081 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10083 struct tg3 *tp = netdev_priv(dev);
10085 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10091 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10092 ethtool_op_set_tx_ipv6_csum(dev, data);
10094 ethtool_op_set_tx_csum(dev, data);
10099 static int tg3_get_sset_count (struct net_device *dev, int sset)
10103 return TG3_NUM_TEST;
10105 return TG3_NUM_STATS;
10107 return -EOPNOTSUPP;
10111 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10113 switch (stringset) {
10115 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10118 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10121 WARN_ON(1); /* we need a WARN() */
10126 static int tg3_phys_id(struct net_device *dev, u32 data)
10128 struct tg3 *tp = netdev_priv(dev);
10131 if (!netif_running(tp->dev))
10135 data = UINT_MAX / 2;
10137 for (i = 0; i < (data * 2); i++) {
10139 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10140 LED_CTRL_1000MBPS_ON |
10141 LED_CTRL_100MBPS_ON |
10142 LED_CTRL_10MBPS_ON |
10143 LED_CTRL_TRAFFIC_OVERRIDE |
10144 LED_CTRL_TRAFFIC_BLINK |
10145 LED_CTRL_TRAFFIC_LED);
10148 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10149 LED_CTRL_TRAFFIC_OVERRIDE);
10151 if (msleep_interruptible(500))
10154 tw32(MAC_LED_CTRL, tp->led_ctrl);
10158 static void tg3_get_ethtool_stats (struct net_device *dev,
10159 struct ethtool_stats *estats, u64 *tmp_stats)
10161 struct tg3 *tp = netdev_priv(dev);
10162 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10165 #define NVRAM_TEST_SIZE 0x100
10166 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10167 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10168 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10169 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10170 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10172 static int tg3_test_nvram(struct tg3 *tp)
10176 int i, j, k, err = 0, size;
10178 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10181 if (tg3_nvram_read(tp, 0, &magic) != 0)
10184 if (magic == TG3_EEPROM_MAGIC)
10185 size = NVRAM_TEST_SIZE;
10186 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10187 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10188 TG3_EEPROM_SB_FORMAT_1) {
10189 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10190 case TG3_EEPROM_SB_REVISION_0:
10191 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10193 case TG3_EEPROM_SB_REVISION_2:
10194 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10196 case TG3_EEPROM_SB_REVISION_3:
10197 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10204 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10205 size = NVRAM_SELFBOOT_HW_SIZE;
10209 buf = kmalloc(size, GFP_KERNEL);
10214 for (i = 0, j = 0; i < size; i += 4, j++) {
10215 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10222 /* Selfboot format */
10223 magic = be32_to_cpu(buf[0]);
10224 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10225 TG3_EEPROM_MAGIC_FW) {
10226 u8 *buf8 = (u8 *) buf, csum8 = 0;
10228 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10229 TG3_EEPROM_SB_REVISION_2) {
10230 /* For rev 2, the csum doesn't include the MBA. */
10231 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10233 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10236 for (i = 0; i < size; i++)
10249 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10250 TG3_EEPROM_MAGIC_HW) {
10251 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10252 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10253 u8 *buf8 = (u8 *) buf;
10255 /* Separate the parity bits and the data bytes. */
10256 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10257 if ((i == 0) || (i == 8)) {
10261 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10262 parity[k++] = buf8[i] & msk;
10265 else if (i == 16) {
10269 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10270 parity[k++] = buf8[i] & msk;
10273 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10274 parity[k++] = buf8[i] & msk;
10277 data[j++] = buf8[i];
10281 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10282 u8 hw8 = hweight8(data[i]);
10284 if ((hw8 & 0x1) && parity[i])
10286 else if (!(hw8 & 0x1) && !parity[i])
10293 /* Bootstrap checksum at offset 0x10 */
10294 csum = calc_crc((unsigned char *) buf, 0x10);
10295 if (csum != be32_to_cpu(buf[0x10/4]))
10298 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10299 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10300 if (csum != be32_to_cpu(buf[0xfc/4]))
10310 #define TG3_SERDES_TIMEOUT_SEC 2
10311 #define TG3_COPPER_TIMEOUT_SEC 6
10313 static int tg3_test_link(struct tg3 *tp)
10317 if (!netif_running(tp->dev))
10320 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10321 max = TG3_SERDES_TIMEOUT_SEC;
10323 max = TG3_COPPER_TIMEOUT_SEC;
10325 for (i = 0; i < max; i++) {
10326 if (netif_carrier_ok(tp->dev))
10329 if (msleep_interruptible(1000))
10336 /* Only test the commonly used registers */
10337 static int tg3_test_registers(struct tg3 *tp)
10339 int i, is_5705, is_5750;
10340 u32 offset, read_mask, write_mask, val, save_val, read_val;
10344 #define TG3_FL_5705 0x1
10345 #define TG3_FL_NOT_5705 0x2
10346 #define TG3_FL_NOT_5788 0x4
10347 #define TG3_FL_NOT_5750 0x8
10351 /* MAC Control Registers */
10352 { MAC_MODE, TG3_FL_NOT_5705,
10353 0x00000000, 0x00ef6f8c },
10354 { MAC_MODE, TG3_FL_5705,
10355 0x00000000, 0x01ef6b8c },
10356 { MAC_STATUS, TG3_FL_NOT_5705,
10357 0x03800107, 0x00000000 },
10358 { MAC_STATUS, TG3_FL_5705,
10359 0x03800100, 0x00000000 },
10360 { MAC_ADDR_0_HIGH, 0x0000,
10361 0x00000000, 0x0000ffff },
10362 { MAC_ADDR_0_LOW, 0x0000,
10363 0x00000000, 0xffffffff },
10364 { MAC_RX_MTU_SIZE, 0x0000,
10365 0x00000000, 0x0000ffff },
10366 { MAC_TX_MODE, 0x0000,
10367 0x00000000, 0x00000070 },
10368 { MAC_TX_LENGTHS, 0x0000,
10369 0x00000000, 0x00003fff },
10370 { MAC_RX_MODE, TG3_FL_NOT_5705,
10371 0x00000000, 0x000007fc },
10372 { MAC_RX_MODE, TG3_FL_5705,
10373 0x00000000, 0x000007dc },
10374 { MAC_HASH_REG_0, 0x0000,
10375 0x00000000, 0xffffffff },
10376 { MAC_HASH_REG_1, 0x0000,
10377 0x00000000, 0xffffffff },
10378 { MAC_HASH_REG_2, 0x0000,
10379 0x00000000, 0xffffffff },
10380 { MAC_HASH_REG_3, 0x0000,
10381 0x00000000, 0xffffffff },
10383 /* Receive Data and Receive BD Initiator Control Registers. */
10384 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10385 0x00000000, 0xffffffff },
10386 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10387 0x00000000, 0xffffffff },
10388 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10389 0x00000000, 0x00000003 },
10390 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10391 0x00000000, 0xffffffff },
10392 { RCVDBDI_STD_BD+0, 0x0000,
10393 0x00000000, 0xffffffff },
10394 { RCVDBDI_STD_BD+4, 0x0000,
10395 0x00000000, 0xffffffff },
10396 { RCVDBDI_STD_BD+8, 0x0000,
10397 0x00000000, 0xffff0002 },
10398 { RCVDBDI_STD_BD+0xc, 0x0000,
10399 0x00000000, 0xffffffff },
10401 /* Receive BD Initiator Control Registers. */
10402 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10403 0x00000000, 0xffffffff },
10404 { RCVBDI_STD_THRESH, TG3_FL_5705,
10405 0x00000000, 0x000003ff },
10406 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10407 0x00000000, 0xffffffff },
10409 /* Host Coalescing Control Registers. */
10410 { HOSTCC_MODE, TG3_FL_NOT_5705,
10411 0x00000000, 0x00000004 },
10412 { HOSTCC_MODE, TG3_FL_5705,
10413 0x00000000, 0x000000f6 },
10414 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10415 0x00000000, 0xffffffff },
10416 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10417 0x00000000, 0x000003ff },
10418 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10419 0x00000000, 0xffffffff },
10420 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10421 0x00000000, 0x000003ff },
10422 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10423 0x00000000, 0xffffffff },
10424 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10425 0x00000000, 0x000000ff },
10426 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10427 0x00000000, 0xffffffff },
10428 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10429 0x00000000, 0x000000ff },
10430 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10431 0x00000000, 0xffffffff },
10432 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10433 0x00000000, 0xffffffff },
10434 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10435 0x00000000, 0xffffffff },
10436 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10437 0x00000000, 0x000000ff },
10438 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10439 0x00000000, 0xffffffff },
10440 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10441 0x00000000, 0x000000ff },
10442 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10443 0x00000000, 0xffffffff },
10444 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10445 0x00000000, 0xffffffff },
10446 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10447 0x00000000, 0xffffffff },
10448 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10449 0x00000000, 0xffffffff },
10450 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10451 0x00000000, 0xffffffff },
10452 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10453 0xffffffff, 0x00000000 },
10454 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10455 0xffffffff, 0x00000000 },
10457 /* Buffer Manager Control Registers. */
10458 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10459 0x00000000, 0x007fff80 },
10460 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10461 0x00000000, 0x007fffff },
10462 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10463 0x00000000, 0x0000003f },
10464 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10465 0x00000000, 0x000001ff },
10466 { BUFMGR_MB_HIGH_WATER, 0x0000,
10467 0x00000000, 0x000001ff },
10468 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10469 0xffffffff, 0x00000000 },
10470 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10471 0xffffffff, 0x00000000 },
10473 /* Mailbox Registers */
10474 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10475 0x00000000, 0x000001ff },
10476 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10477 0x00000000, 0x000001ff },
10478 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10479 0x00000000, 0x000007ff },
10480 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10481 0x00000000, 0x000001ff },
10483 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10486 is_5705 = is_5750 = 0;
10487 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10489 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10493 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10494 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10497 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10500 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10501 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10504 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10507 offset = (u32) reg_tbl[i].offset;
10508 read_mask = reg_tbl[i].read_mask;
10509 write_mask = reg_tbl[i].write_mask;
10511 /* Save the original register content */
10512 save_val = tr32(offset);
10514 /* Determine the read-only value. */
10515 read_val = save_val & read_mask;
10517 /* Write zero to the register, then make sure the read-only bits
10518 * are not changed and the read/write bits are all zeros.
10522 val = tr32(offset);
10524 /* Test the read-only and read/write bits. */
10525 if (((val & read_mask) != read_val) || (val & write_mask))
10528 /* Write ones to all the bits defined by RdMask and WrMask, then
10529 * make sure the read-only bits are not changed and the
10530 * read/write bits are all ones.
10532 tw32(offset, read_mask | write_mask);
10534 val = tr32(offset);
10536 /* Test the read-only bits. */
10537 if ((val & read_mask) != read_val)
10540 /* Test the read/write bits. */
10541 if ((val & write_mask) != write_mask)
10544 tw32(offset, save_val);
10550 if (netif_msg_hw(tp))
10551 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10553 tw32(offset, save_val);
10557 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10559 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10563 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10564 for (j = 0; j < len; j += 4) {
10567 tg3_write_mem(tp, offset + j, test_pattern[i]);
10568 tg3_read_mem(tp, offset + j, &val);
10569 if (val != test_pattern[i])
10576 static int tg3_test_memory(struct tg3 *tp)
10578 static struct mem_entry {
10581 } mem_tbl_570x[] = {
10582 { 0x00000000, 0x00b50},
10583 { 0x00002000, 0x1c000},
10584 { 0xffffffff, 0x00000}
10585 }, mem_tbl_5705[] = {
10586 { 0x00000100, 0x0000c},
10587 { 0x00000200, 0x00008},
10588 { 0x00004000, 0x00800},
10589 { 0x00006000, 0x01000},
10590 { 0x00008000, 0x02000},
10591 { 0x00010000, 0x0e000},
10592 { 0xffffffff, 0x00000}
10593 }, mem_tbl_5755[] = {
10594 { 0x00000200, 0x00008},
10595 { 0x00004000, 0x00800},
10596 { 0x00006000, 0x00800},
10597 { 0x00008000, 0x02000},
10598 { 0x00010000, 0x0c000},
10599 { 0xffffffff, 0x00000}
10600 }, mem_tbl_5906[] = {
10601 { 0x00000200, 0x00008},
10602 { 0x00004000, 0x00400},
10603 { 0x00006000, 0x00400},
10604 { 0x00008000, 0x01000},
10605 { 0x00010000, 0x01000},
10606 { 0xffffffff, 0x00000}
10608 struct mem_entry *mem_tbl;
10612 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10613 mem_tbl = mem_tbl_5755;
10614 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10615 mem_tbl = mem_tbl_5906;
10616 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10617 mem_tbl = mem_tbl_5705;
10619 mem_tbl = mem_tbl_570x;
10621 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10622 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10623 mem_tbl[i].len)) != 0)
10630 #define TG3_MAC_LOOPBACK 0
10631 #define TG3_PHY_LOOPBACK 1
10633 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10635 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10636 u32 desc_idx, coal_now;
10637 struct sk_buff *skb, *rx_skb;
10640 int num_pkts, tx_len, rx_len, i, err;
10641 struct tg3_rx_buffer_desc *desc;
10642 struct tg3_napi *tnapi, *rnapi;
10643 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10645 if (tp->irq_cnt > 1) {
10646 tnapi = &tp->napi[1];
10647 rnapi = &tp->napi[1];
10649 tnapi = &tp->napi[0];
10650 rnapi = &tp->napi[0];
10652 coal_now = tnapi->coal_now | rnapi->coal_now;
10654 if (loopback_mode == TG3_MAC_LOOPBACK) {
10655 /* HW errata - mac loopback fails in some cases on 5780.
10656 * Normal traffic and PHY loopback are not affected by
10659 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10662 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10663 MAC_MODE_PORT_INT_LPBACK;
10664 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10665 mac_mode |= MAC_MODE_LINK_POLARITY;
10666 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10667 mac_mode |= MAC_MODE_PORT_MODE_MII;
10669 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10670 tw32(MAC_MODE, mac_mode);
10671 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10674 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10675 tg3_phy_fet_toggle_apd(tp, false);
10676 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10678 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10680 tg3_phy_toggle_automdix(tp, 0);
10682 tg3_writephy(tp, MII_BMCR, val);
10685 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10686 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10688 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10689 mac_mode |= MAC_MODE_PORT_MODE_MII;
10691 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10693 /* reset to prevent losing 1st rx packet intermittently */
10694 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10695 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10697 tw32_f(MAC_RX_MODE, tp->rx_mode);
10699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10700 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10701 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10702 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10703 mac_mode |= MAC_MODE_LINK_POLARITY;
10704 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10705 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10707 tw32(MAC_MODE, mac_mode);
10715 skb = netdev_alloc_skb(tp->dev, tx_len);
10719 tx_data = skb_put(skb, tx_len);
10720 memcpy(tx_data, tp->dev->dev_addr, 6);
10721 memset(tx_data + 6, 0x0, 8);
10723 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10725 for (i = 14; i < tx_len; i++)
10726 tx_data[i] = (u8) (i & 0xff);
10728 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10729 if (pci_dma_mapping_error(tp->pdev, map)) {
10730 dev_kfree_skb(skb);
10734 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10739 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10743 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10748 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10749 tr32_mailbox(tnapi->prodmbox);
10753 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10754 for (i = 0; i < 35; i++) {
10755 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10760 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10761 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10762 if ((tx_idx == tnapi->tx_prod) &&
10763 (rx_idx == (rx_start_idx + num_pkts)))
10767 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10768 dev_kfree_skb(skb);
10770 if (tx_idx != tnapi->tx_prod)
10773 if (rx_idx != rx_start_idx + num_pkts)
10776 desc = &rnapi->rx_rcb[rx_start_idx];
10777 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10778 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10779 if (opaque_key != RXD_OPAQUE_RING_STD)
10782 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10783 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10786 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10787 if (rx_len != tx_len)
10790 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10792 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10793 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10795 for (i = 14; i < tx_len; i++) {
10796 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10801 /* tg3_free_rings will unmap and free the rx_skb */
10806 #define TG3_MAC_LOOPBACK_FAILED 1
10807 #define TG3_PHY_LOOPBACK_FAILED 2
10808 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10809 TG3_PHY_LOOPBACK_FAILED)
10811 static int tg3_test_loopback(struct tg3 *tp)
10816 if (!netif_running(tp->dev))
10817 return TG3_LOOPBACK_FAILED;
10819 err = tg3_reset_hw(tp, 1);
10821 return TG3_LOOPBACK_FAILED;
10823 /* Turn off gphy autopowerdown. */
10824 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10825 tg3_phy_toggle_apd(tp, false);
10827 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10831 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10833 /* Wait for up to 40 microseconds to acquire lock. */
10834 for (i = 0; i < 4; i++) {
10835 status = tr32(TG3_CPMU_MUTEX_GNT);
10836 if (status == CPMU_MUTEX_GNT_DRIVER)
10841 if (status != CPMU_MUTEX_GNT_DRIVER)
10842 return TG3_LOOPBACK_FAILED;
10844 /* Turn off link-based power management. */
10845 cpmuctrl = tr32(TG3_CPMU_CTRL);
10846 tw32(TG3_CPMU_CTRL,
10847 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10848 CPMU_CTRL_LINK_AWARE_MODE));
10851 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10852 err |= TG3_MAC_LOOPBACK_FAILED;
10854 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10855 tw32(TG3_CPMU_CTRL, cpmuctrl);
10857 /* Release the mutex */
10858 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10861 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10862 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10863 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10864 err |= TG3_PHY_LOOPBACK_FAILED;
10867 /* Re-enable gphy autopowerdown. */
10868 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10869 tg3_phy_toggle_apd(tp, true);
10874 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10877 struct tg3 *tp = netdev_priv(dev);
10879 if (tp->link_config.phy_is_low_power)
10880 tg3_set_power_state(tp, PCI_D0);
10882 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10884 if (tg3_test_nvram(tp) != 0) {
10885 etest->flags |= ETH_TEST_FL_FAILED;
10888 if (tg3_test_link(tp) != 0) {
10889 etest->flags |= ETH_TEST_FL_FAILED;
10892 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10893 int err, err2 = 0, irq_sync = 0;
10895 if (netif_running(dev)) {
10897 tg3_netif_stop(tp);
10901 tg3_full_lock(tp, irq_sync);
10903 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10904 err = tg3_nvram_lock(tp);
10905 tg3_halt_cpu(tp, RX_CPU_BASE);
10906 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10907 tg3_halt_cpu(tp, TX_CPU_BASE);
10909 tg3_nvram_unlock(tp);
10911 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10914 if (tg3_test_registers(tp) != 0) {
10915 etest->flags |= ETH_TEST_FL_FAILED;
10918 if (tg3_test_memory(tp) != 0) {
10919 etest->flags |= ETH_TEST_FL_FAILED;
10922 if ((data[4] = tg3_test_loopback(tp)) != 0)
10923 etest->flags |= ETH_TEST_FL_FAILED;
10925 tg3_full_unlock(tp);
10927 if (tg3_test_interrupt(tp) != 0) {
10928 etest->flags |= ETH_TEST_FL_FAILED;
10932 tg3_full_lock(tp, 0);
10934 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10935 if (netif_running(dev)) {
10936 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10937 err2 = tg3_restart_hw(tp, 1);
10939 tg3_netif_start(tp);
10942 tg3_full_unlock(tp);
10944 if (irq_sync && !err2)
10947 if (tp->link_config.phy_is_low_power)
10948 tg3_set_power_state(tp, PCI_D3hot);
10952 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10954 struct mii_ioctl_data *data = if_mii(ifr);
10955 struct tg3 *tp = netdev_priv(dev);
10958 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10959 struct phy_device *phydev;
10960 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10962 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10963 return phy_mii_ioctl(phydev, data, cmd);
10968 data->phy_id = tp->phy_addr;
10971 case SIOCGMIIREG: {
10974 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10975 break; /* We have no PHY */
10977 if (tp->link_config.phy_is_low_power)
10980 spin_lock_bh(&tp->lock);
10981 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10982 spin_unlock_bh(&tp->lock);
10984 data->val_out = mii_regval;
10990 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10991 break; /* We have no PHY */
10993 if (tp->link_config.phy_is_low_power)
10996 spin_lock_bh(&tp->lock);
10997 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10998 spin_unlock_bh(&tp->lock);
11006 return -EOPNOTSUPP;
11009 #if TG3_VLAN_TAG_USED
11010 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11012 struct tg3 *tp = netdev_priv(dev);
11014 if (!netif_running(dev)) {
11019 tg3_netif_stop(tp);
11021 tg3_full_lock(tp, 0);
11025 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11026 __tg3_set_rx_mode(dev);
11028 tg3_netif_start(tp);
11030 tg3_full_unlock(tp);
11034 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11036 struct tg3 *tp = netdev_priv(dev);
11038 memcpy(ec, &tp->coal, sizeof(*ec));
11042 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11044 struct tg3 *tp = netdev_priv(dev);
11045 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11046 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11048 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11049 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11050 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11051 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11052 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11055 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11056 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11057 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11058 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11059 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11060 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11061 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11062 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11063 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11064 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11067 /* No rx interrupts will be generated if both are zero */
11068 if ((ec->rx_coalesce_usecs == 0) &&
11069 (ec->rx_max_coalesced_frames == 0))
11072 /* No tx interrupts will be generated if both are zero */
11073 if ((ec->tx_coalesce_usecs == 0) &&
11074 (ec->tx_max_coalesced_frames == 0))
11077 /* Only copy relevant parameters, ignore all others. */
11078 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11079 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11080 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11081 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11082 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11083 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11084 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11085 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11086 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11088 if (netif_running(dev)) {
11089 tg3_full_lock(tp, 0);
11090 __tg3_set_coalesce(tp, &tp->coal);
11091 tg3_full_unlock(tp);
11096 static const struct ethtool_ops tg3_ethtool_ops = {
11097 .get_settings = tg3_get_settings,
11098 .set_settings = tg3_set_settings,
11099 .get_drvinfo = tg3_get_drvinfo,
11100 .get_regs_len = tg3_get_regs_len,
11101 .get_regs = tg3_get_regs,
11102 .get_wol = tg3_get_wol,
11103 .set_wol = tg3_set_wol,
11104 .get_msglevel = tg3_get_msglevel,
11105 .set_msglevel = tg3_set_msglevel,
11106 .nway_reset = tg3_nway_reset,
11107 .get_link = ethtool_op_get_link,
11108 .get_eeprom_len = tg3_get_eeprom_len,
11109 .get_eeprom = tg3_get_eeprom,
11110 .set_eeprom = tg3_set_eeprom,
11111 .get_ringparam = tg3_get_ringparam,
11112 .set_ringparam = tg3_set_ringparam,
11113 .get_pauseparam = tg3_get_pauseparam,
11114 .set_pauseparam = tg3_set_pauseparam,
11115 .get_rx_csum = tg3_get_rx_csum,
11116 .set_rx_csum = tg3_set_rx_csum,
11117 .set_tx_csum = tg3_set_tx_csum,
11118 .set_sg = ethtool_op_set_sg,
11119 .set_tso = tg3_set_tso,
11120 .self_test = tg3_self_test,
11121 .get_strings = tg3_get_strings,
11122 .phys_id = tg3_phys_id,
11123 .get_ethtool_stats = tg3_get_ethtool_stats,
11124 .get_coalesce = tg3_get_coalesce,
11125 .set_coalesce = tg3_set_coalesce,
11126 .get_sset_count = tg3_get_sset_count,
11129 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11131 u32 cursize, val, magic;
11133 tp->nvram_size = EEPROM_CHIP_SIZE;
11135 if (tg3_nvram_read(tp, 0, &magic) != 0)
11138 if ((magic != TG3_EEPROM_MAGIC) &&
11139 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11140 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11144 * Size the chip by reading offsets at increasing powers of two.
11145 * When we encounter our validation signature, we know the addressing
11146 * has wrapped around, and thus have our chip size.
11150 while (cursize < tp->nvram_size) {
11151 if (tg3_nvram_read(tp, cursize, &val) != 0)
11160 tp->nvram_size = cursize;
11163 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11167 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11168 tg3_nvram_read(tp, 0, &val) != 0)
11171 /* Selfboot format */
11172 if (val != TG3_EEPROM_MAGIC) {
11173 tg3_get_eeprom_size(tp);
11177 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11179 /* This is confusing. We want to operate on the
11180 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11181 * call will read from NVRAM and byteswap the data
11182 * according to the byteswapping settings for all
11183 * other register accesses. This ensures the data we
11184 * want will always reside in the lower 16-bits.
11185 * However, the data in NVRAM is in LE format, which
11186 * means the data from the NVRAM read will always be
11187 * opposite the endianness of the CPU. The 16-bit
11188 * byteswap then brings the data to CPU endianness.
11190 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11194 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11197 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11201 nvcfg1 = tr32(NVRAM_CFG1);
11202 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11203 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11205 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11206 tw32(NVRAM_CFG1, nvcfg1);
11209 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11210 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11211 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11212 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11213 tp->nvram_jedecnum = JEDEC_ATMEL;
11214 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11215 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11217 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11218 tp->nvram_jedecnum = JEDEC_ATMEL;
11219 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11221 case FLASH_VENDOR_ATMEL_EEPROM:
11222 tp->nvram_jedecnum = JEDEC_ATMEL;
11223 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11224 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11226 case FLASH_VENDOR_ST:
11227 tp->nvram_jedecnum = JEDEC_ST;
11228 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11229 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11231 case FLASH_VENDOR_SAIFUN:
11232 tp->nvram_jedecnum = JEDEC_SAIFUN;
11233 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11235 case FLASH_VENDOR_SST_SMALL:
11236 case FLASH_VENDOR_SST_LARGE:
11237 tp->nvram_jedecnum = JEDEC_SST;
11238 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11242 tp->nvram_jedecnum = JEDEC_ATMEL;
11243 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11244 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11248 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11250 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11251 case FLASH_5752PAGE_SIZE_256:
11252 tp->nvram_pagesize = 256;
11254 case FLASH_5752PAGE_SIZE_512:
11255 tp->nvram_pagesize = 512;
11257 case FLASH_5752PAGE_SIZE_1K:
11258 tp->nvram_pagesize = 1024;
11260 case FLASH_5752PAGE_SIZE_2K:
11261 tp->nvram_pagesize = 2048;
11263 case FLASH_5752PAGE_SIZE_4K:
11264 tp->nvram_pagesize = 4096;
11266 case FLASH_5752PAGE_SIZE_264:
11267 tp->nvram_pagesize = 264;
11269 case FLASH_5752PAGE_SIZE_528:
11270 tp->nvram_pagesize = 528;
11275 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11279 nvcfg1 = tr32(NVRAM_CFG1);
11281 /* NVRAM protection for TPM */
11282 if (nvcfg1 & (1 << 27))
11283 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11285 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11286 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11287 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11288 tp->nvram_jedecnum = JEDEC_ATMEL;
11289 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11291 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11292 tp->nvram_jedecnum = JEDEC_ATMEL;
11293 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11294 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11296 case FLASH_5752VENDOR_ST_M45PE10:
11297 case FLASH_5752VENDOR_ST_M45PE20:
11298 case FLASH_5752VENDOR_ST_M45PE40:
11299 tp->nvram_jedecnum = JEDEC_ST;
11300 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11301 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11305 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11306 tg3_nvram_get_pagesize(tp, nvcfg1);
11308 /* For eeprom, set pagesize to maximum eeprom size */
11309 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11311 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11312 tw32(NVRAM_CFG1, nvcfg1);
11316 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11318 u32 nvcfg1, protect = 0;
11320 nvcfg1 = tr32(NVRAM_CFG1);
11322 /* NVRAM protection for TPM */
11323 if (nvcfg1 & (1 << 27)) {
11324 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11328 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11330 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11331 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11332 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11333 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11334 tp->nvram_jedecnum = JEDEC_ATMEL;
11335 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11336 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11337 tp->nvram_pagesize = 264;
11338 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11339 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11340 tp->nvram_size = (protect ? 0x3e200 :
11341 TG3_NVRAM_SIZE_512KB);
11342 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11343 tp->nvram_size = (protect ? 0x1f200 :
11344 TG3_NVRAM_SIZE_256KB);
11346 tp->nvram_size = (protect ? 0x1f200 :
11347 TG3_NVRAM_SIZE_128KB);
11349 case FLASH_5752VENDOR_ST_M45PE10:
11350 case FLASH_5752VENDOR_ST_M45PE20:
11351 case FLASH_5752VENDOR_ST_M45PE40:
11352 tp->nvram_jedecnum = JEDEC_ST;
11353 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11354 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11355 tp->nvram_pagesize = 256;
11356 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11357 tp->nvram_size = (protect ?
11358 TG3_NVRAM_SIZE_64KB :
11359 TG3_NVRAM_SIZE_128KB);
11360 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11361 tp->nvram_size = (protect ?
11362 TG3_NVRAM_SIZE_64KB :
11363 TG3_NVRAM_SIZE_256KB);
11365 tp->nvram_size = (protect ?
11366 TG3_NVRAM_SIZE_128KB :
11367 TG3_NVRAM_SIZE_512KB);
11372 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11376 nvcfg1 = tr32(NVRAM_CFG1);
11378 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11379 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11380 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11381 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11382 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11383 tp->nvram_jedecnum = JEDEC_ATMEL;
11384 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11385 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11387 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11388 tw32(NVRAM_CFG1, nvcfg1);
11390 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11391 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11392 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11393 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11394 tp->nvram_jedecnum = JEDEC_ATMEL;
11395 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11396 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11397 tp->nvram_pagesize = 264;
11399 case FLASH_5752VENDOR_ST_M45PE10:
11400 case FLASH_5752VENDOR_ST_M45PE20:
11401 case FLASH_5752VENDOR_ST_M45PE40:
11402 tp->nvram_jedecnum = JEDEC_ST;
11403 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11404 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11405 tp->nvram_pagesize = 256;
11410 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11412 u32 nvcfg1, protect = 0;
11414 nvcfg1 = tr32(NVRAM_CFG1);
11416 /* NVRAM protection for TPM */
11417 if (nvcfg1 & (1 << 27)) {
11418 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11422 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11424 case FLASH_5761VENDOR_ATMEL_ADB021D:
11425 case FLASH_5761VENDOR_ATMEL_ADB041D:
11426 case FLASH_5761VENDOR_ATMEL_ADB081D:
11427 case FLASH_5761VENDOR_ATMEL_ADB161D:
11428 case FLASH_5761VENDOR_ATMEL_MDB021D:
11429 case FLASH_5761VENDOR_ATMEL_MDB041D:
11430 case FLASH_5761VENDOR_ATMEL_MDB081D:
11431 case FLASH_5761VENDOR_ATMEL_MDB161D:
11432 tp->nvram_jedecnum = JEDEC_ATMEL;
11433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11434 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11435 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11436 tp->nvram_pagesize = 256;
11438 case FLASH_5761VENDOR_ST_A_M45PE20:
11439 case FLASH_5761VENDOR_ST_A_M45PE40:
11440 case FLASH_5761VENDOR_ST_A_M45PE80:
11441 case FLASH_5761VENDOR_ST_A_M45PE16:
11442 case FLASH_5761VENDOR_ST_M_M45PE20:
11443 case FLASH_5761VENDOR_ST_M_M45PE40:
11444 case FLASH_5761VENDOR_ST_M_M45PE80:
11445 case FLASH_5761VENDOR_ST_M_M45PE16:
11446 tp->nvram_jedecnum = JEDEC_ST;
11447 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11448 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11449 tp->nvram_pagesize = 256;
11454 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11457 case FLASH_5761VENDOR_ATMEL_ADB161D:
11458 case FLASH_5761VENDOR_ATMEL_MDB161D:
11459 case FLASH_5761VENDOR_ST_A_M45PE16:
11460 case FLASH_5761VENDOR_ST_M_M45PE16:
11461 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11463 case FLASH_5761VENDOR_ATMEL_ADB081D:
11464 case FLASH_5761VENDOR_ATMEL_MDB081D:
11465 case FLASH_5761VENDOR_ST_A_M45PE80:
11466 case FLASH_5761VENDOR_ST_M_M45PE80:
11467 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11469 case FLASH_5761VENDOR_ATMEL_ADB041D:
11470 case FLASH_5761VENDOR_ATMEL_MDB041D:
11471 case FLASH_5761VENDOR_ST_A_M45PE40:
11472 case FLASH_5761VENDOR_ST_M_M45PE40:
11473 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11475 case FLASH_5761VENDOR_ATMEL_ADB021D:
11476 case FLASH_5761VENDOR_ATMEL_MDB021D:
11477 case FLASH_5761VENDOR_ST_A_M45PE20:
11478 case FLASH_5761VENDOR_ST_M_M45PE20:
11479 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11485 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11487 tp->nvram_jedecnum = JEDEC_ATMEL;
11488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11489 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11492 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11496 nvcfg1 = tr32(NVRAM_CFG1);
11498 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11499 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11500 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11501 tp->nvram_jedecnum = JEDEC_ATMEL;
11502 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11503 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11505 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11506 tw32(NVRAM_CFG1, nvcfg1);
11508 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11509 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11510 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11511 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11512 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11513 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11514 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11515 tp->nvram_jedecnum = JEDEC_ATMEL;
11516 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11517 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11519 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11520 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11521 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11522 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11523 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11525 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11526 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11527 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11529 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11530 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11531 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11535 case FLASH_5752VENDOR_ST_M45PE10:
11536 case FLASH_5752VENDOR_ST_M45PE20:
11537 case FLASH_5752VENDOR_ST_M45PE40:
11538 tp->nvram_jedecnum = JEDEC_ST;
11539 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11540 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11542 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11543 case FLASH_5752VENDOR_ST_M45PE10:
11544 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11546 case FLASH_5752VENDOR_ST_M45PE20:
11547 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11549 case FLASH_5752VENDOR_ST_M45PE40:
11550 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11555 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11559 tg3_nvram_get_pagesize(tp, nvcfg1);
11560 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11561 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11565 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11569 nvcfg1 = tr32(NVRAM_CFG1);
11571 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11572 case FLASH_5717VENDOR_ATMEL_EEPROM:
11573 case FLASH_5717VENDOR_MICRO_EEPROM:
11574 tp->nvram_jedecnum = JEDEC_ATMEL;
11575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11576 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11578 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11579 tw32(NVRAM_CFG1, nvcfg1);
11581 case FLASH_5717VENDOR_ATMEL_MDB011D:
11582 case FLASH_5717VENDOR_ATMEL_ADB011B:
11583 case FLASH_5717VENDOR_ATMEL_ADB011D:
11584 case FLASH_5717VENDOR_ATMEL_MDB021D:
11585 case FLASH_5717VENDOR_ATMEL_ADB021B:
11586 case FLASH_5717VENDOR_ATMEL_ADB021D:
11587 case FLASH_5717VENDOR_ATMEL_45USPT:
11588 tp->nvram_jedecnum = JEDEC_ATMEL;
11589 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11590 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11592 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11593 case FLASH_5717VENDOR_ATMEL_MDB021D:
11594 case FLASH_5717VENDOR_ATMEL_ADB021B:
11595 case FLASH_5717VENDOR_ATMEL_ADB021D:
11596 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11599 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11603 case FLASH_5717VENDOR_ST_M_M25PE10:
11604 case FLASH_5717VENDOR_ST_A_M25PE10:
11605 case FLASH_5717VENDOR_ST_M_M45PE10:
11606 case FLASH_5717VENDOR_ST_A_M45PE10:
11607 case FLASH_5717VENDOR_ST_M_M25PE20:
11608 case FLASH_5717VENDOR_ST_A_M25PE20:
11609 case FLASH_5717VENDOR_ST_M_M45PE20:
11610 case FLASH_5717VENDOR_ST_A_M45PE20:
11611 case FLASH_5717VENDOR_ST_25USPT:
11612 case FLASH_5717VENDOR_ST_45USPT:
11613 tp->nvram_jedecnum = JEDEC_ST;
11614 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11615 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11617 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11618 case FLASH_5717VENDOR_ST_M_M25PE20:
11619 case FLASH_5717VENDOR_ST_A_M25PE20:
11620 case FLASH_5717VENDOR_ST_M_M45PE20:
11621 case FLASH_5717VENDOR_ST_A_M45PE20:
11622 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11625 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11630 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11634 tg3_nvram_get_pagesize(tp, nvcfg1);
11635 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11636 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11639 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11640 static void __devinit tg3_nvram_init(struct tg3 *tp)
11642 tw32_f(GRC_EEPROM_ADDR,
11643 (EEPROM_ADDR_FSM_RESET |
11644 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11645 EEPROM_ADDR_CLKPERD_SHIFT)));
11649 /* Enable seeprom accesses. */
11650 tw32_f(GRC_LOCAL_CTRL,
11651 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11654 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11655 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11656 tp->tg3_flags |= TG3_FLAG_NVRAM;
11658 if (tg3_nvram_lock(tp)) {
11659 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11660 "tg3_nvram_init failed.\n", tp->dev->name);
11663 tg3_enable_nvram_access(tp);
11665 tp->nvram_size = 0;
11667 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11668 tg3_get_5752_nvram_info(tp);
11669 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11670 tg3_get_5755_nvram_info(tp);
11671 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11674 tg3_get_5787_nvram_info(tp);
11675 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11676 tg3_get_5761_nvram_info(tp);
11677 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11678 tg3_get_5906_nvram_info(tp);
11679 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11680 tg3_get_57780_nvram_info(tp);
11681 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11682 tg3_get_5717_nvram_info(tp);
11684 tg3_get_nvram_info(tp);
11686 if (tp->nvram_size == 0)
11687 tg3_get_nvram_size(tp);
11689 tg3_disable_nvram_access(tp);
11690 tg3_nvram_unlock(tp);
11693 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11695 tg3_get_eeprom_size(tp);
11699 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11700 u32 offset, u32 len, u8 *buf)
11705 for (i = 0; i < len; i += 4) {
11711 memcpy(&data, buf + i, 4);
11714 * The SEEPROM interface expects the data to always be opposite
11715 * the native endian format. We accomplish this by reversing
11716 * all the operations that would have been performed on the
11717 * data from a call to tg3_nvram_read_be32().
11719 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11721 val = tr32(GRC_EEPROM_ADDR);
11722 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11724 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11726 tw32(GRC_EEPROM_ADDR, val |
11727 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11728 (addr & EEPROM_ADDR_ADDR_MASK) |
11729 EEPROM_ADDR_START |
11730 EEPROM_ADDR_WRITE);
11732 for (j = 0; j < 1000; j++) {
11733 val = tr32(GRC_EEPROM_ADDR);
11735 if (val & EEPROM_ADDR_COMPLETE)
11739 if (!(val & EEPROM_ADDR_COMPLETE)) {
11748 /* offset and length are dword aligned */
11749 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11753 u32 pagesize = tp->nvram_pagesize;
11754 u32 pagemask = pagesize - 1;
11758 tmp = kmalloc(pagesize, GFP_KERNEL);
11764 u32 phy_addr, page_off, size;
11766 phy_addr = offset & ~pagemask;
11768 for (j = 0; j < pagesize; j += 4) {
11769 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11770 (__be32 *) (tmp + j));
11777 page_off = offset & pagemask;
11784 memcpy(tmp + page_off, buf, size);
11786 offset = offset + (pagesize - page_off);
11788 tg3_enable_nvram_access(tp);
11791 * Before we can erase the flash page, we need
11792 * to issue a special "write enable" command.
11794 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11796 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11799 /* Erase the target page */
11800 tw32(NVRAM_ADDR, phy_addr);
11802 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11803 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11805 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11808 /* Issue another write enable to start the write. */
11809 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11811 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11814 for (j = 0; j < pagesize; j += 4) {
11817 data = *((__be32 *) (tmp + j));
11819 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11821 tw32(NVRAM_ADDR, phy_addr + j);
11823 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11827 nvram_cmd |= NVRAM_CMD_FIRST;
11828 else if (j == (pagesize - 4))
11829 nvram_cmd |= NVRAM_CMD_LAST;
11831 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11838 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11839 tg3_nvram_exec_cmd(tp, nvram_cmd);
11846 /* offset and length are dword aligned */
11847 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11852 for (i = 0; i < len; i += 4, offset += 4) {
11853 u32 page_off, phy_addr, nvram_cmd;
11856 memcpy(&data, buf + i, 4);
11857 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11859 page_off = offset % tp->nvram_pagesize;
11861 phy_addr = tg3_nvram_phys_addr(tp, offset);
11863 tw32(NVRAM_ADDR, phy_addr);
11865 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11867 if ((page_off == 0) || (i == 0))
11868 nvram_cmd |= NVRAM_CMD_FIRST;
11869 if (page_off == (tp->nvram_pagesize - 4))
11870 nvram_cmd |= NVRAM_CMD_LAST;
11872 if (i == (len - 4))
11873 nvram_cmd |= NVRAM_CMD_LAST;
11875 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11876 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11877 (tp->nvram_jedecnum == JEDEC_ST) &&
11878 (nvram_cmd & NVRAM_CMD_FIRST)) {
11880 if ((ret = tg3_nvram_exec_cmd(tp,
11881 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11886 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11887 /* We always do complete word writes to eeprom. */
11888 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11891 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11897 /* offset and length are dword aligned */
11898 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11902 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11903 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11904 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11908 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11909 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11914 ret = tg3_nvram_lock(tp);
11918 tg3_enable_nvram_access(tp);
11919 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11920 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11921 tw32(NVRAM_WRITE1, 0x406);
11923 grc_mode = tr32(GRC_MODE);
11924 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11926 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11927 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11929 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11933 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11937 grc_mode = tr32(GRC_MODE);
11938 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11940 tg3_disable_nvram_access(tp);
11941 tg3_nvram_unlock(tp);
11944 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11945 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11952 struct subsys_tbl_ent {
11953 u16 subsys_vendor, subsys_devid;
11957 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11958 /* Broadcom boards. */
11959 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11960 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11961 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11962 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11963 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11964 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11965 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11966 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11967 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11968 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11969 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11972 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11973 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11974 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11975 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11976 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11979 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11980 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11981 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11982 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11984 /* Compaq boards. */
11985 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11986 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11987 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11988 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11989 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11992 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11995 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11999 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12000 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12001 tp->pdev->subsystem_vendor) &&
12002 (subsys_id_to_phy_id[i].subsys_devid ==
12003 tp->pdev->subsystem_device))
12004 return &subsys_id_to_phy_id[i];
12009 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12014 /* On some early chips the SRAM cannot be accessed in D3hot state,
12015 * so need make sure we're in D0.
12017 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12018 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12019 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12022 /* Make sure register accesses (indirect or otherwise)
12023 * will function correctly.
12025 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12026 tp->misc_host_ctrl);
12028 /* The memory arbiter has to be enabled in order for SRAM accesses
12029 * to succeed. Normally on powerup the tg3 chip firmware will make
12030 * sure it is enabled, but other entities such as system netboot
12031 * code might disable it.
12033 val = tr32(MEMARB_MODE);
12034 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12036 tp->phy_id = PHY_ID_INVALID;
12037 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12039 /* Assume an onboard device and WOL capable by default. */
12040 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12043 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12044 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12045 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12047 val = tr32(VCPU_CFGSHDW);
12048 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12049 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12050 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12051 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12052 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12056 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12057 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12058 u32 nic_cfg, led_cfg;
12059 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12060 int eeprom_phy_serdes = 0;
12062 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12063 tp->nic_sram_data_cfg = nic_cfg;
12065 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12066 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12067 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12068 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12069 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12070 (ver > 0) && (ver < 0x100))
12071 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12074 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12076 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12077 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12078 eeprom_phy_serdes = 1;
12080 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12081 if (nic_phy_id != 0) {
12082 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12083 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12085 eeprom_phy_id = (id1 >> 16) << 10;
12086 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12087 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12091 tp->phy_id = eeprom_phy_id;
12092 if (eeprom_phy_serdes) {
12093 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12094 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12096 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12099 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12100 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12101 SHASTA_EXT_LED_MODE_MASK);
12103 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12107 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12108 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12111 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12112 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12115 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12116 tp->led_ctrl = LED_CTRL_MODE_MAC;
12118 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12119 * read on some older 5700/5701 bootcode.
12121 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12123 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12125 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12129 case SHASTA_EXT_LED_SHARED:
12130 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12131 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12132 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12133 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12134 LED_CTRL_MODE_PHY_2);
12137 case SHASTA_EXT_LED_MAC:
12138 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12141 case SHASTA_EXT_LED_COMBO:
12142 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12143 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12144 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12145 LED_CTRL_MODE_PHY_2);
12150 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12152 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12153 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12155 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12156 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12158 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12159 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12160 if ((tp->pdev->subsystem_vendor ==
12161 PCI_VENDOR_ID_ARIMA) &&
12162 (tp->pdev->subsystem_device == 0x205a ||
12163 tp->pdev->subsystem_device == 0x2063))
12164 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12166 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12167 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12170 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12171 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12172 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12173 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12176 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12177 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12178 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12180 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12181 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12182 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12184 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12185 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12186 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12188 if (cfg2 & (1 << 17))
12189 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12191 /* serdes signal pre-emphasis in register 0x590 set by */
12192 /* bootcode if bit 18 is set */
12193 if (cfg2 & (1 << 18))
12194 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12196 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12197 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12198 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12199 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12201 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12204 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12205 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12206 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12209 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12210 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12211 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12212 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12213 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12214 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12217 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12218 device_set_wakeup_enable(&tp->pdev->dev,
12219 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12222 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12227 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12228 tw32(OTP_CTRL, cmd);
12230 /* Wait for up to 1 ms for command to execute. */
12231 for (i = 0; i < 100; i++) {
12232 val = tr32(OTP_STATUS);
12233 if (val & OTP_STATUS_CMD_DONE)
12238 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12241 /* Read the gphy configuration from the OTP region of the chip. The gphy
12242 * configuration is a 32-bit value that straddles the alignment boundary.
12243 * We do two 32-bit reads and then shift and merge the results.
12245 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12247 u32 bhalf_otp, thalf_otp;
12249 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12251 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12254 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12256 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12259 thalf_otp = tr32(OTP_READ_DATA);
12261 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12263 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12266 bhalf_otp = tr32(OTP_READ_DATA);
12268 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12271 static int __devinit tg3_phy_probe(struct tg3 *tp)
12273 u32 hw_phy_id_1, hw_phy_id_2;
12274 u32 hw_phy_id, hw_phy_id_masked;
12277 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12278 return tg3_phy_init(tp);
12280 /* Reading the PHY ID register can conflict with ASF
12281 * firmware access to the PHY hardware.
12284 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12285 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12286 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12288 /* Now read the physical PHY_ID from the chip and verify
12289 * that it is sane. If it doesn't look good, we fall back
12290 * to either the hard-coded table based PHY_ID and failing
12291 * that the value found in the eeprom area.
12293 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12294 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12296 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12297 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12298 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12300 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12303 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12304 tp->phy_id = hw_phy_id;
12305 if (hw_phy_id_masked == PHY_ID_BCM8002)
12306 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12308 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12310 if (tp->phy_id != PHY_ID_INVALID) {
12311 /* Do nothing, phy ID already set up in
12312 * tg3_get_eeprom_hw_cfg().
12315 struct subsys_tbl_ent *p;
12317 /* No eeprom signature? Try the hardcoded
12318 * subsys device table.
12320 p = lookup_by_subsys(tp);
12324 tp->phy_id = p->phy_id;
12326 tp->phy_id == PHY_ID_BCM8002)
12327 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12331 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12332 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12333 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12334 u32 bmsr, adv_reg, tg3_ctrl, mask;
12336 tg3_readphy(tp, MII_BMSR, &bmsr);
12337 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12338 (bmsr & BMSR_LSTATUS))
12339 goto skip_phy_reset;
12341 err = tg3_phy_reset(tp);
12345 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12346 ADVERTISE_100HALF | ADVERTISE_100FULL |
12347 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12349 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12350 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12351 MII_TG3_CTRL_ADV_1000_FULL);
12352 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12353 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12354 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12355 MII_TG3_CTRL_ENABLE_AS_MASTER);
12358 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12359 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12360 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12361 if (!tg3_copper_is_advertising_all(tp, mask)) {
12362 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12364 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12365 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12367 tg3_writephy(tp, MII_BMCR,
12368 BMCR_ANENABLE | BMCR_ANRESTART);
12370 tg3_phy_set_wirespeed(tp);
12372 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12373 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12374 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12378 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12379 err = tg3_init_5401phy_dsp(tp);
12384 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12385 err = tg3_init_5401phy_dsp(tp);
12388 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12389 tp->link_config.advertising =
12390 (ADVERTISED_1000baseT_Half |
12391 ADVERTISED_1000baseT_Full |
12392 ADVERTISED_Autoneg |
12394 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12395 tp->link_config.advertising &=
12396 ~(ADVERTISED_1000baseT_Half |
12397 ADVERTISED_1000baseT_Full);
12402 static void __devinit tg3_read_partno(struct tg3 *tp)
12404 unsigned char vpd_data[256]; /* in little-endian format */
12408 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12409 tg3_nvram_read(tp, 0x0, &magic))
12410 goto out_not_found;
12412 if (magic == TG3_EEPROM_MAGIC) {
12413 for (i = 0; i < 256; i += 4) {
12416 /* The data is in little-endian format in NVRAM.
12417 * Use the big-endian read routines to preserve
12418 * the byte order as it exists in NVRAM.
12420 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12421 goto out_not_found;
12423 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12428 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12429 for (i = 0; i < 256; i += 4) {
12434 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12436 while (j++ < 100) {
12437 pci_read_config_word(tp->pdev, vpd_cap +
12438 PCI_VPD_ADDR, &tmp16);
12439 if (tmp16 & 0x8000)
12443 if (!(tmp16 & 0x8000))
12444 goto out_not_found;
12446 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12448 v = cpu_to_le32(tmp);
12449 memcpy(&vpd_data[i], &v, sizeof(v));
12453 /* Now parse and find the part number. */
12454 for (i = 0; i < 254; ) {
12455 unsigned char val = vpd_data[i];
12456 unsigned int block_end;
12458 if (val == 0x82 || val == 0x91) {
12461 (vpd_data[i + 2] << 8)));
12466 goto out_not_found;
12468 block_end = (i + 3 +
12470 (vpd_data[i + 2] << 8)));
12473 if (block_end > 256)
12474 goto out_not_found;
12476 while (i < (block_end - 2)) {
12477 if (vpd_data[i + 0] == 'P' &&
12478 vpd_data[i + 1] == 'N') {
12479 int partno_len = vpd_data[i + 2];
12482 if (partno_len > 24 || (partno_len + i) > 256)
12483 goto out_not_found;
12485 memcpy(tp->board_part_number,
12486 &vpd_data[i], partno_len);
12491 i += 3 + vpd_data[i + 2];
12494 /* Part number not found. */
12495 goto out_not_found;
12499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12500 strcpy(tp->board_part_number, "BCM95906");
12501 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12502 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12503 strcpy(tp->board_part_number, "BCM57780");
12504 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12505 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12506 strcpy(tp->board_part_number, "BCM57760");
12507 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12508 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12509 strcpy(tp->board_part_number, "BCM57790");
12510 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12511 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12512 strcpy(tp->board_part_number, "BCM57788");
12514 strcpy(tp->board_part_number, "none");
12517 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12521 if (tg3_nvram_read(tp, offset, &val) ||
12522 (val & 0xfc000000) != 0x0c000000 ||
12523 tg3_nvram_read(tp, offset + 4, &val) ||
12530 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12532 u32 val, offset, start, ver_offset;
12534 bool newver = false;
12536 if (tg3_nvram_read(tp, 0xc, &offset) ||
12537 tg3_nvram_read(tp, 0x4, &start))
12540 offset = tg3_nvram_logical_addr(tp, offset);
12542 if (tg3_nvram_read(tp, offset, &val))
12545 if ((val & 0xfc000000) == 0x0c000000) {
12546 if (tg3_nvram_read(tp, offset + 4, &val))
12554 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12557 offset = offset + ver_offset - start;
12558 for (i = 0; i < 16; i += 4) {
12560 if (tg3_nvram_read_be32(tp, offset + i, &v))
12563 memcpy(tp->fw_ver + i, &v, sizeof(v));
12568 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12571 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12572 TG3_NVM_BCVER_MAJSFT;
12573 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12574 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12578 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12580 u32 val, major, minor;
12582 /* Use native endian representation */
12583 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12586 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12587 TG3_NVM_HWSB_CFG1_MAJSFT;
12588 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12589 TG3_NVM_HWSB_CFG1_MINSFT;
12591 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12594 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12596 u32 offset, major, minor, build;
12598 tp->fw_ver[0] = 's';
12599 tp->fw_ver[1] = 'b';
12600 tp->fw_ver[2] = '\0';
12602 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12605 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12606 case TG3_EEPROM_SB_REVISION_0:
12607 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12609 case TG3_EEPROM_SB_REVISION_2:
12610 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12612 case TG3_EEPROM_SB_REVISION_3:
12613 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12619 if (tg3_nvram_read(tp, offset, &val))
12622 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12623 TG3_EEPROM_SB_EDH_BLD_SHFT;
12624 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12625 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12626 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12628 if (minor > 99 || build > 26)
12631 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12634 tp->fw_ver[8] = 'a' + build - 1;
12635 tp->fw_ver[9] = '\0';
12639 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12641 u32 val, offset, start;
12644 for (offset = TG3_NVM_DIR_START;
12645 offset < TG3_NVM_DIR_END;
12646 offset += TG3_NVM_DIRENT_SIZE) {
12647 if (tg3_nvram_read(tp, offset, &val))
12650 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12654 if (offset == TG3_NVM_DIR_END)
12657 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12658 start = 0x08000000;
12659 else if (tg3_nvram_read(tp, offset - 4, &start))
12662 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12663 !tg3_fw_img_is_valid(tp, offset) ||
12664 tg3_nvram_read(tp, offset + 8, &val))
12667 offset += val - start;
12669 vlen = strlen(tp->fw_ver);
12671 tp->fw_ver[vlen++] = ',';
12672 tp->fw_ver[vlen++] = ' ';
12674 for (i = 0; i < 4; i++) {
12676 if (tg3_nvram_read_be32(tp, offset, &v))
12679 offset += sizeof(v);
12681 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12682 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12686 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12691 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12696 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12697 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12700 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12701 if (apedata != APE_SEG_SIG_MAGIC)
12704 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12705 if (!(apedata & APE_FW_STATUS_READY))
12708 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12710 vlen = strlen(tp->fw_ver);
12712 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12713 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12714 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12715 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12716 (apedata & APE_FW_VERSION_BLDMSK));
12719 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12723 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12724 tp->fw_ver[0] = 's';
12725 tp->fw_ver[1] = 'b';
12726 tp->fw_ver[2] = '\0';
12731 if (tg3_nvram_read(tp, 0, &val))
12734 if (val == TG3_EEPROM_MAGIC)
12735 tg3_read_bc_ver(tp);
12736 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12737 tg3_read_sb_ver(tp, val);
12738 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12739 tg3_read_hwsb_ver(tp);
12743 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12744 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12747 tg3_read_mgmtfw_ver(tp);
12749 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12752 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12754 static int __devinit tg3_get_invariants(struct tg3 *tp)
12756 static struct pci_device_id write_reorder_chipsets[] = {
12757 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12758 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12759 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12760 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12761 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12762 PCI_DEVICE_ID_VIA_8385_0) },
12766 u32 pci_state_reg, grc_misc_cfg;
12771 /* Force memory write invalidate off. If we leave it on,
12772 * then on 5700_BX chips we have to enable a workaround.
12773 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12774 * to match the cacheline size. The Broadcom driver have this
12775 * workaround but turns MWI off all the times so never uses
12776 * it. This seems to suggest that the workaround is insufficient.
12778 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12779 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12780 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12782 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12783 * has the register indirect write enable bit set before
12784 * we try to access any of the MMIO registers. It is also
12785 * critical that the PCI-X hw workaround situation is decided
12786 * before that as well.
12788 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12791 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12792 MISC_HOST_CTRL_CHIPREV_SHIFT);
12793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12794 u32 prod_id_asic_rev;
12796 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12797 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12799 pci_read_config_dword(tp->pdev,
12800 TG3PCI_GEN2_PRODID_ASICREV,
12801 &prod_id_asic_rev);
12803 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12804 &prod_id_asic_rev);
12806 tp->pci_chip_rev_id = prod_id_asic_rev;
12809 /* Wrong chip ID in 5752 A0. This code can be removed later
12810 * as A0 is not in production.
12812 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12813 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12815 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12816 * we need to disable memory and use config. cycles
12817 * only to access all registers. The 5702/03 chips
12818 * can mistakenly decode the special cycles from the
12819 * ICH chipsets as memory write cycles, causing corruption
12820 * of register and memory space. Only certain ICH bridges
12821 * will drive special cycles with non-zero data during the
12822 * address phase which can fall within the 5703's address
12823 * range. This is not an ICH bug as the PCI spec allows
12824 * non-zero address during special cycles. However, only
12825 * these ICH bridges are known to drive non-zero addresses
12826 * during special cycles.
12828 * Since special cycles do not cross PCI bridges, we only
12829 * enable this workaround if the 5703 is on the secondary
12830 * bus of these ICH bridges.
12832 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12833 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12834 static struct tg3_dev_id {
12838 } ich_chipsets[] = {
12839 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12841 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12843 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12845 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12849 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12850 struct pci_dev *bridge = NULL;
12852 while (pci_id->vendor != 0) {
12853 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12859 if (pci_id->rev != PCI_ANY_ID) {
12860 if (bridge->revision > pci_id->rev)
12863 if (bridge->subordinate &&
12864 (bridge->subordinate->number ==
12865 tp->pdev->bus->number)) {
12867 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12868 pci_dev_put(bridge);
12874 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12875 static struct tg3_dev_id {
12878 } bridge_chipsets[] = {
12879 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12880 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12883 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12884 struct pci_dev *bridge = NULL;
12886 while (pci_id->vendor != 0) {
12887 bridge = pci_get_device(pci_id->vendor,
12894 if (bridge->subordinate &&
12895 (bridge->subordinate->number <=
12896 tp->pdev->bus->number) &&
12897 (bridge->subordinate->subordinate >=
12898 tp->pdev->bus->number)) {
12899 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12900 pci_dev_put(bridge);
12906 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12907 * DMA addresses > 40-bit. This bridge may have other additional
12908 * 57xx devices behind it in some 4-port NIC designs for example.
12909 * Any tg3 device found behind the bridge will also need the 40-bit
12912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12913 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12914 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12915 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12916 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12919 struct pci_dev *bridge = NULL;
12922 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12923 PCI_DEVICE_ID_SERVERWORKS_EPB,
12925 if (bridge && bridge->subordinate &&
12926 (bridge->subordinate->number <=
12927 tp->pdev->bus->number) &&
12928 (bridge->subordinate->subordinate >=
12929 tp->pdev->bus->number)) {
12930 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12931 pci_dev_put(bridge);
12937 /* Initialize misc host control in PCI block. */
12938 tp->misc_host_ctrl |= (misc_ctrl_reg &
12939 MISC_HOST_CTRL_CHIPREV);
12940 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12941 tp->misc_host_ctrl);
12943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12946 tp->pdev_peer = tg3_find_peer(tp);
12948 /* Intentionally exclude ASIC_REV_5906 */
12949 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12956 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12959 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12961 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12962 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12963 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12965 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12966 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12967 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12969 /* 5700 B0 chips do not support checksumming correctly due
12970 * to hardware bugs.
12972 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12973 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12975 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12976 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12977 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12978 tp->dev->features |= NETIF_F_IPV6_CSUM;
12981 /* Determine TSO capabilities */
12982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12983 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12984 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12985 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12986 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12987 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12988 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12990 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12991 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12992 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12993 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12994 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12995 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12997 tp->fw_needed = FIRMWARE_TG3TSO5;
12999 tp->fw_needed = FIRMWARE_TG3TSO;
13004 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13005 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13006 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13007 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13008 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13009 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13010 tp->pdev_peer == tp->pdev))
13011 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13013 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13015 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13019 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13020 tp->irq_max = TG3_IRQ_MAX_VECS;
13024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13026 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13027 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13028 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13029 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13032 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13033 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13035 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13037 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13040 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13041 if (tp->pcie_cap != 0) {
13044 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13046 pcie_set_readrq(tp->pdev, 4096);
13048 pci_read_config_word(tp->pdev,
13049 tp->pcie_cap + PCI_EXP_LNKCTL,
13051 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13053 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13055 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13056 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13057 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13058 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13060 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13061 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13062 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13063 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13064 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13065 if (!tp->pcix_cap) {
13066 printk(KERN_ERR PFX "Cannot find PCI-X "
13067 "capability, aborting.\n");
13071 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13072 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13075 /* If we have an AMD 762 or VIA K8T800 chipset, write
13076 * reordering to the mailbox registers done by the host
13077 * controller can cause major troubles. We read back from
13078 * every mailbox register write to force the writes to be
13079 * posted to the chip in order.
13081 if (pci_dev_present(write_reorder_chipsets) &&
13082 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13083 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13085 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13086 &tp->pci_cacheline_sz);
13087 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13088 &tp->pci_lat_timer);
13089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13090 tp->pci_lat_timer < 64) {
13091 tp->pci_lat_timer = 64;
13092 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13093 tp->pci_lat_timer);
13096 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13097 /* 5700 BX chips need to have their TX producer index
13098 * mailboxes written twice to workaround a bug.
13100 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13102 /* If we are in PCI-X mode, enable register write workaround.
13104 * The workaround is to use indirect register accesses
13105 * for all chip writes not to mailbox registers.
13107 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13110 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13112 /* The chip can have it's power management PCI config
13113 * space registers clobbered due to this bug.
13114 * So explicitly force the chip into D0 here.
13116 pci_read_config_dword(tp->pdev,
13117 tp->pm_cap + PCI_PM_CTRL,
13119 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13120 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13121 pci_write_config_dword(tp->pdev,
13122 tp->pm_cap + PCI_PM_CTRL,
13125 /* Also, force SERR#/PERR# in PCI command. */
13126 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13127 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13128 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13132 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13133 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13134 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13135 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13137 /* Chip-specific fixup from Broadcom driver */
13138 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13139 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13140 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13141 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13144 /* Default fast path register access methods */
13145 tp->read32 = tg3_read32;
13146 tp->write32 = tg3_write32;
13147 tp->read32_mbox = tg3_read32;
13148 tp->write32_mbox = tg3_write32;
13149 tp->write32_tx_mbox = tg3_write32;
13150 tp->write32_rx_mbox = tg3_write32;
13152 /* Various workaround register access methods */
13153 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13154 tp->write32 = tg3_write_indirect_reg32;
13155 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13156 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13157 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13159 * Back to back register writes can cause problems on these
13160 * chips, the workaround is to read back all reg writes
13161 * except those to mailbox regs.
13163 * See tg3_write_indirect_reg32().
13165 tp->write32 = tg3_write_flush_reg32;
13168 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13169 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13170 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13171 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13172 tp->write32_rx_mbox = tg3_write_flush_reg32;
13175 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13176 tp->read32 = tg3_read_indirect_reg32;
13177 tp->write32 = tg3_write_indirect_reg32;
13178 tp->read32_mbox = tg3_read_indirect_mbox;
13179 tp->write32_mbox = tg3_write_indirect_mbox;
13180 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13181 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13186 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13187 pci_cmd &= ~PCI_COMMAND_MEMORY;
13188 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13191 tp->read32_mbox = tg3_read32_mbox_5906;
13192 tp->write32_mbox = tg3_write32_mbox_5906;
13193 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13194 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13197 if (tp->write32 == tg3_write_indirect_reg32 ||
13198 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13199 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13200 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13201 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13203 /* Get eeprom hw config before calling tg3_set_power_state().
13204 * In particular, the TG3_FLG2_IS_NIC flag must be
13205 * determined before calling tg3_set_power_state() so that
13206 * we know whether or not to switch out of Vaux power.
13207 * When the flag is set, it means that GPIO1 is used for eeprom
13208 * write protect and also implies that it is a LOM where GPIOs
13209 * are not used to switch power.
13211 tg3_get_eeprom_hw_cfg(tp);
13213 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13214 /* Allow reads and writes to the
13215 * APE register and memory space.
13217 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13218 PCISTATE_ALLOW_APE_SHMEM_WR;
13219 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13228 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13230 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13231 * GPIO1 driven high will bring 5700's external PHY out of reset.
13232 * It is also used as eeprom write protect on LOMs.
13234 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13235 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13236 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13237 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13238 GRC_LCLCTRL_GPIO_OUTPUT1);
13239 /* Unused GPIO3 must be driven as output on 5752 because there
13240 * are no pull-up resistors on unused GPIO pins.
13242 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13243 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13247 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13249 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13250 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13251 /* Turn off the debug UART. */
13252 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13253 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13254 /* Keep VMain power. */
13255 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13256 GRC_LCLCTRL_GPIO_OUTPUT0;
13259 /* Force the chip into D0. */
13260 err = tg3_set_power_state(tp, PCI_D0);
13262 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13263 pci_name(tp->pdev));
13267 /* Derive initial jumbo mode from MTU assigned in
13268 * ether_setup() via the alloc_etherdev() call
13270 if (tp->dev->mtu > ETH_DATA_LEN &&
13271 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13272 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13274 /* Determine WakeOnLan speed to use. */
13275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13276 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13277 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13278 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13279 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13281 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13285 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13287 /* A few boards don't want Ethernet@WireSpeed phy feature */
13288 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13289 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13290 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13291 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13292 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13293 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13294 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13296 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13297 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13298 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13299 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13300 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13302 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13303 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13304 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13305 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13311 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13312 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13313 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13314 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13315 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13317 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13320 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13321 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13322 tp->phy_otp = tg3_read_otp_phycfg(tp);
13323 if (tp->phy_otp == 0)
13324 tp->phy_otp = TG3_OTP_DEFAULT;
13327 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13328 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13330 tp->mi_mode = MAC_MI_MODE_BASE;
13332 tp->coalesce_mode = 0;
13333 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13334 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13335 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13337 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13338 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13339 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13341 err = tg3_mdio_init(tp);
13345 /* Initialize data/descriptor byte/word swapping. */
13346 val = tr32(GRC_MODE);
13347 val &= GRC_MODE_HOST_STACKUP;
13348 tw32(GRC_MODE, val | tp->grc_mode);
13350 tg3_switch_clocks(tp);
13352 /* Clear this out for sanity. */
13353 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13355 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13357 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13358 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13359 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13361 if (chiprevid == CHIPREV_ID_5701_A0 ||
13362 chiprevid == CHIPREV_ID_5701_B0 ||
13363 chiprevid == CHIPREV_ID_5701_B2 ||
13364 chiprevid == CHIPREV_ID_5701_B5) {
13365 void __iomem *sram_base;
13367 /* Write some dummy words into the SRAM status block
13368 * area, see if it reads back correctly. If the return
13369 * value is bad, force enable the PCIX workaround.
13371 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13373 writel(0x00000000, sram_base);
13374 writel(0x00000000, sram_base + 4);
13375 writel(0xffffffff, sram_base + 4);
13376 if (readl(sram_base) != 0x00000000)
13377 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13382 tg3_nvram_init(tp);
13384 grc_misc_cfg = tr32(GRC_MISC_CFG);
13385 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13387 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13388 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13389 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13390 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13392 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13393 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13394 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13395 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13396 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13397 HOSTCC_MODE_CLRTICK_TXBD);
13399 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13400 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13401 tp->misc_host_ctrl);
13404 /* Preserve the APE MAC_MODE bits */
13405 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13406 tp->mac_mode = tr32(MAC_MODE) |
13407 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13409 tp->mac_mode = TG3_DEF_MAC_MODE;
13411 /* these are limited to 10/100 only */
13412 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13413 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13414 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13415 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13416 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13417 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13418 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13419 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13420 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13421 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13422 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13423 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13424 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13425 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13427 err = tg3_phy_probe(tp);
13429 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13430 pci_name(tp->pdev), err);
13431 /* ... but do not return immediately ... */
13435 tg3_read_partno(tp);
13436 tg3_read_fw_ver(tp);
13438 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13439 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13442 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13444 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13447 /* 5700 {AX,BX} chips have a broken status block link
13448 * change bit implementation, so we must use the
13449 * status register in those cases.
13451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13452 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13454 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13456 /* The led_ctrl is set during tg3_phy_probe, here we might
13457 * have to force the link status polling mechanism based
13458 * upon subsystem IDs.
13460 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13461 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13462 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13463 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13464 TG3_FLAG_USE_LINKCHG_REG);
13467 /* For all SERDES we poll the MAC status register. */
13468 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13469 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13471 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13473 tp->rx_offset = NET_IP_ALIGN;
13474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13475 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13478 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13480 /* Increment the rx prod index on the rx std ring by at most
13481 * 8 for these chips to workaround hw errata.
13483 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13484 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13486 tp->rx_std_max_post = 8;
13488 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13489 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13490 PCIE_PWR_MGMT_L1_THRESH_MSK;
13495 #ifdef CONFIG_SPARC
13496 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13498 struct net_device *dev = tp->dev;
13499 struct pci_dev *pdev = tp->pdev;
13500 struct device_node *dp = pci_device_to_OF_node(pdev);
13501 const unsigned char *addr;
13504 addr = of_get_property(dp, "local-mac-address", &len);
13505 if (addr && len == 6) {
13506 memcpy(dev->dev_addr, addr, 6);
13507 memcpy(dev->perm_addr, dev->dev_addr, 6);
13513 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13515 struct net_device *dev = tp->dev;
13517 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13518 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13523 static int __devinit tg3_get_device_address(struct tg3 *tp)
13525 struct net_device *dev = tp->dev;
13526 u32 hi, lo, mac_offset;
13529 #ifdef CONFIG_SPARC
13530 if (!tg3_get_macaddr_sparc(tp))
13535 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13536 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13537 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13539 if (tg3_nvram_lock(tp))
13540 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13542 tg3_nvram_unlock(tp);
13543 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13544 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13546 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13549 /* First try to get it from MAC address mailbox. */
13550 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13551 if ((hi >> 16) == 0x484b) {
13552 dev->dev_addr[0] = (hi >> 8) & 0xff;
13553 dev->dev_addr[1] = (hi >> 0) & 0xff;
13555 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13556 dev->dev_addr[2] = (lo >> 24) & 0xff;
13557 dev->dev_addr[3] = (lo >> 16) & 0xff;
13558 dev->dev_addr[4] = (lo >> 8) & 0xff;
13559 dev->dev_addr[5] = (lo >> 0) & 0xff;
13561 /* Some old bootcode may report a 0 MAC address in SRAM */
13562 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13565 /* Next, try NVRAM. */
13566 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13567 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13568 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13569 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13570 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13572 /* Finally just fetch it out of the MAC control regs. */
13574 hi = tr32(MAC_ADDR_0_HIGH);
13575 lo = tr32(MAC_ADDR_0_LOW);
13577 dev->dev_addr[5] = lo & 0xff;
13578 dev->dev_addr[4] = (lo >> 8) & 0xff;
13579 dev->dev_addr[3] = (lo >> 16) & 0xff;
13580 dev->dev_addr[2] = (lo >> 24) & 0xff;
13581 dev->dev_addr[1] = hi & 0xff;
13582 dev->dev_addr[0] = (hi >> 8) & 0xff;
13586 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13587 #ifdef CONFIG_SPARC
13588 if (!tg3_get_default_macaddr_sparc(tp))
13593 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13597 #define BOUNDARY_SINGLE_CACHELINE 1
13598 #define BOUNDARY_MULTI_CACHELINE 2
13600 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13602 int cacheline_size;
13606 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13608 cacheline_size = 1024;
13610 cacheline_size = (int) byte * 4;
13612 /* On 5703 and later chips, the boundary bits have no
13615 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13616 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13617 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13620 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13621 goal = BOUNDARY_MULTI_CACHELINE;
13623 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13624 goal = BOUNDARY_SINGLE_CACHELINE;
13630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13631 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13638 /* PCI controllers on most RISC systems tend to disconnect
13639 * when a device tries to burst across a cache-line boundary.
13640 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13642 * Unfortunately, for PCI-E there are only limited
13643 * write-side controls for this, and thus for reads
13644 * we will still get the disconnects. We'll also waste
13645 * these PCI cycles for both read and write for chips
13646 * other than 5700 and 5701 which do not implement the
13649 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13650 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13651 switch (cacheline_size) {
13656 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13657 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13658 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13660 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13661 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13666 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13667 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13671 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13672 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13675 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13676 switch (cacheline_size) {
13680 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13681 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13682 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13688 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13689 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13693 switch (cacheline_size) {
13695 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13696 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13697 DMA_RWCTRL_WRITE_BNDRY_16);
13702 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13703 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13704 DMA_RWCTRL_WRITE_BNDRY_32);
13709 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13710 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13711 DMA_RWCTRL_WRITE_BNDRY_64);
13716 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13717 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13718 DMA_RWCTRL_WRITE_BNDRY_128);
13723 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13724 DMA_RWCTRL_WRITE_BNDRY_256);
13727 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13728 DMA_RWCTRL_WRITE_BNDRY_512);
13732 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13733 DMA_RWCTRL_WRITE_BNDRY_1024);
13742 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13744 struct tg3_internal_buffer_desc test_desc;
13745 u32 sram_dma_descs;
13748 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13750 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13751 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13752 tw32(RDMAC_STATUS, 0);
13753 tw32(WDMAC_STATUS, 0);
13755 tw32(BUFMGR_MODE, 0);
13756 tw32(FTQ_RESET, 0);
13758 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13759 test_desc.addr_lo = buf_dma & 0xffffffff;
13760 test_desc.nic_mbuf = 0x00002100;
13761 test_desc.len = size;
13764 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13765 * the *second* time the tg3 driver was getting loaded after an
13768 * Broadcom tells me:
13769 * ...the DMA engine is connected to the GRC block and a DMA
13770 * reset may affect the GRC block in some unpredictable way...
13771 * The behavior of resets to individual blocks has not been tested.
13773 * Broadcom noted the GRC reset will also reset all sub-components.
13776 test_desc.cqid_sqid = (13 << 8) | 2;
13778 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13781 test_desc.cqid_sqid = (16 << 8) | 7;
13783 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13786 test_desc.flags = 0x00000005;
13788 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13791 val = *(((u32 *)&test_desc) + i);
13792 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13793 sram_dma_descs + (i * sizeof(u32)));
13794 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13796 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13799 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13801 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13805 for (i = 0; i < 40; i++) {
13809 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13811 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13812 if ((val & 0xffff) == sram_dma_descs) {
13823 #define TEST_BUFFER_SIZE 0x2000
13825 static int __devinit tg3_test_dma(struct tg3 *tp)
13827 dma_addr_t buf_dma;
13828 u32 *buf, saved_dma_rwctrl;
13831 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13837 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13838 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13840 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13842 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13845 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13846 /* DMA read watermark not used on PCIE */
13847 tp->dma_rwctrl |= 0x00180000;
13848 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13850 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13851 tp->dma_rwctrl |= 0x003f0000;
13853 tp->dma_rwctrl |= 0x003f000f;
13855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13856 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13857 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13858 u32 read_water = 0x7;
13860 /* If the 5704 is behind the EPB bridge, we can
13861 * do the less restrictive ONE_DMA workaround for
13862 * better performance.
13864 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13866 tp->dma_rwctrl |= 0x8000;
13867 else if (ccval == 0x6 || ccval == 0x7)
13868 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13870 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13872 /* Set bit 23 to enable PCIX hw bug fix */
13874 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13875 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13877 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13878 /* 5780 always in PCIX mode */
13879 tp->dma_rwctrl |= 0x00144000;
13880 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13881 /* 5714 always in PCIX mode */
13882 tp->dma_rwctrl |= 0x00148000;
13884 tp->dma_rwctrl |= 0x001b000f;
13888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13890 tp->dma_rwctrl &= 0xfffffff0;
13892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13894 /* Remove this if it causes problems for some boards. */
13895 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13897 /* On 5700/5701 chips, we need to set this bit.
13898 * Otherwise the chip will issue cacheline transactions
13899 * to streamable DMA memory with not all the byte
13900 * enables turned on. This is an error on several
13901 * RISC PCI controllers, in particular sparc64.
13903 * On 5703/5704 chips, this bit has been reassigned
13904 * a different meaning. In particular, it is used
13905 * on those chips to enable a PCI-X workaround.
13907 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13910 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13913 /* Unneeded, already done by tg3_get_invariants. */
13914 tg3_switch_clocks(tp);
13917 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13918 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13921 /* It is best to perform DMA test with maximum write burst size
13922 * to expose the 5700/5701 write DMA bug.
13924 saved_dma_rwctrl = tp->dma_rwctrl;
13925 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13926 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13931 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13934 /* Send the buffer to the chip. */
13935 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13937 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13942 /* validate data reached card RAM correctly. */
13943 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13945 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13946 if (le32_to_cpu(val) != p[i]) {
13947 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13948 /* ret = -ENODEV here? */
13953 /* Now read it back. */
13954 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13956 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13962 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13966 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13967 DMA_RWCTRL_WRITE_BNDRY_16) {
13968 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13969 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13970 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13973 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13979 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13985 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13986 DMA_RWCTRL_WRITE_BNDRY_16) {
13987 static struct pci_device_id dma_wait_state_chipsets[] = {
13988 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13989 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13993 /* DMA test passed without adjusting DMA boundary,
13994 * now look for chipsets that are known to expose the
13995 * DMA bug without failing the test.
13997 if (pci_dev_present(dma_wait_state_chipsets)) {
13998 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13999 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14002 /* Safe to use the calculated DMA boundary. */
14003 tp->dma_rwctrl = saved_dma_rwctrl;
14005 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14009 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14014 static void __devinit tg3_init_link_config(struct tg3 *tp)
14016 tp->link_config.advertising =
14017 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14018 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14019 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14020 ADVERTISED_Autoneg | ADVERTISED_MII);
14021 tp->link_config.speed = SPEED_INVALID;
14022 tp->link_config.duplex = DUPLEX_INVALID;
14023 tp->link_config.autoneg = AUTONEG_ENABLE;
14024 tp->link_config.active_speed = SPEED_INVALID;
14025 tp->link_config.active_duplex = DUPLEX_INVALID;
14026 tp->link_config.phy_is_low_power = 0;
14027 tp->link_config.orig_speed = SPEED_INVALID;
14028 tp->link_config.orig_duplex = DUPLEX_INVALID;
14029 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14032 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14034 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
14035 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
14036 tp->bufmgr_config.mbuf_read_dma_low_water =
14037 DEFAULT_MB_RDMA_LOW_WATER_5705;
14038 tp->bufmgr_config.mbuf_mac_rx_low_water =
14039 DEFAULT_MB_MACRX_LOW_WATER_5705;
14040 tp->bufmgr_config.mbuf_high_water =
14041 DEFAULT_MB_HIGH_WATER_5705;
14042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14043 tp->bufmgr_config.mbuf_mac_rx_low_water =
14044 DEFAULT_MB_MACRX_LOW_WATER_5906;
14045 tp->bufmgr_config.mbuf_high_water =
14046 DEFAULT_MB_HIGH_WATER_5906;
14049 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14050 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14051 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14052 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14053 tp->bufmgr_config.mbuf_high_water_jumbo =
14054 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14056 tp->bufmgr_config.mbuf_read_dma_low_water =
14057 DEFAULT_MB_RDMA_LOW_WATER;
14058 tp->bufmgr_config.mbuf_mac_rx_low_water =
14059 DEFAULT_MB_MACRX_LOW_WATER;
14060 tp->bufmgr_config.mbuf_high_water =
14061 DEFAULT_MB_HIGH_WATER;
14063 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14064 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14065 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14066 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14067 tp->bufmgr_config.mbuf_high_water_jumbo =
14068 DEFAULT_MB_HIGH_WATER_JUMBO;
14071 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14072 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14075 static char * __devinit tg3_phy_string(struct tg3 *tp)
14077 switch (tp->phy_id & PHY_ID_MASK) {
14078 case PHY_ID_BCM5400: return "5400";
14079 case PHY_ID_BCM5401: return "5401";
14080 case PHY_ID_BCM5411: return "5411";
14081 case PHY_ID_BCM5701: return "5701";
14082 case PHY_ID_BCM5703: return "5703";
14083 case PHY_ID_BCM5704: return "5704";
14084 case PHY_ID_BCM5705: return "5705";
14085 case PHY_ID_BCM5750: return "5750";
14086 case PHY_ID_BCM5752: return "5752";
14087 case PHY_ID_BCM5714: return "5714";
14088 case PHY_ID_BCM5780: return "5780";
14089 case PHY_ID_BCM5755: return "5755";
14090 case PHY_ID_BCM5787: return "5787";
14091 case PHY_ID_BCM5784: return "5784";
14092 case PHY_ID_BCM5756: return "5722/5756";
14093 case PHY_ID_BCM5906: return "5906";
14094 case PHY_ID_BCM5761: return "5761";
14095 case PHY_ID_BCM5717: return "5717";
14096 case PHY_ID_BCM8002: return "8002/serdes";
14097 case 0: return "serdes";
14098 default: return "unknown";
14102 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14104 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14105 strcpy(str, "PCI Express");
14107 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14108 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14110 strcpy(str, "PCIX:");
14112 if ((clock_ctrl == 7) ||
14113 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14114 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14115 strcat(str, "133MHz");
14116 else if (clock_ctrl == 0)
14117 strcat(str, "33MHz");
14118 else if (clock_ctrl == 2)
14119 strcat(str, "50MHz");
14120 else if (clock_ctrl == 4)
14121 strcat(str, "66MHz");
14122 else if (clock_ctrl == 6)
14123 strcat(str, "100MHz");
14125 strcpy(str, "PCI:");
14126 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14127 strcat(str, "66MHz");
14129 strcat(str, "33MHz");
14131 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14132 strcat(str, ":32-bit");
14134 strcat(str, ":64-bit");
14138 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14140 struct pci_dev *peer;
14141 unsigned int func, devnr = tp->pdev->devfn & ~7;
14143 for (func = 0; func < 8; func++) {
14144 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14145 if (peer && peer != tp->pdev)
14149 /* 5704 can be configured in single-port mode, set peer to
14150 * tp->pdev in that case.
14158 * We don't need to keep the refcount elevated; there's no way
14159 * to remove one half of this device without removing the other
14166 static void __devinit tg3_init_coal(struct tg3 *tp)
14168 struct ethtool_coalesce *ec = &tp->coal;
14170 memset(ec, 0, sizeof(*ec));
14171 ec->cmd = ETHTOOL_GCOALESCE;
14172 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14173 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14174 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14175 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14176 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14177 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14178 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14179 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14180 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14182 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14183 HOSTCC_MODE_CLRTICK_TXBD)) {
14184 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14185 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14186 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14187 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14190 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14191 ec->rx_coalesce_usecs_irq = 0;
14192 ec->tx_coalesce_usecs_irq = 0;
14193 ec->stats_block_coalesce_usecs = 0;
14197 static const struct net_device_ops tg3_netdev_ops = {
14198 .ndo_open = tg3_open,
14199 .ndo_stop = tg3_close,
14200 .ndo_start_xmit = tg3_start_xmit,
14201 .ndo_get_stats = tg3_get_stats,
14202 .ndo_validate_addr = eth_validate_addr,
14203 .ndo_set_multicast_list = tg3_set_rx_mode,
14204 .ndo_set_mac_address = tg3_set_mac_addr,
14205 .ndo_do_ioctl = tg3_ioctl,
14206 .ndo_tx_timeout = tg3_tx_timeout,
14207 .ndo_change_mtu = tg3_change_mtu,
14208 #if TG3_VLAN_TAG_USED
14209 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14211 #ifdef CONFIG_NET_POLL_CONTROLLER
14212 .ndo_poll_controller = tg3_poll_controller,
14216 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14217 .ndo_open = tg3_open,
14218 .ndo_stop = tg3_close,
14219 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14220 .ndo_get_stats = tg3_get_stats,
14221 .ndo_validate_addr = eth_validate_addr,
14222 .ndo_set_multicast_list = tg3_set_rx_mode,
14223 .ndo_set_mac_address = tg3_set_mac_addr,
14224 .ndo_do_ioctl = tg3_ioctl,
14225 .ndo_tx_timeout = tg3_tx_timeout,
14226 .ndo_change_mtu = tg3_change_mtu,
14227 #if TG3_VLAN_TAG_USED
14228 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14230 #ifdef CONFIG_NET_POLL_CONTROLLER
14231 .ndo_poll_controller = tg3_poll_controller,
14235 static int __devinit tg3_init_one(struct pci_dev *pdev,
14236 const struct pci_device_id *ent)
14238 static int tg3_version_printed = 0;
14239 struct net_device *dev;
14241 int i, err, pm_cap;
14242 u32 sndmbx, rcvmbx, intmbx;
14244 u64 dma_mask, persist_dma_mask;
14246 if (tg3_version_printed++ == 0)
14247 printk(KERN_INFO "%s", version);
14249 err = pci_enable_device(pdev);
14251 printk(KERN_ERR PFX "Cannot enable PCI device, "
14256 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14258 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14260 goto err_out_disable_pdev;
14263 pci_set_master(pdev);
14265 /* Find power-management capability. */
14266 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14268 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14271 goto err_out_free_res;
14274 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14276 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14278 goto err_out_free_res;
14281 SET_NETDEV_DEV(dev, &pdev->dev);
14283 #if TG3_VLAN_TAG_USED
14284 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14287 tp = netdev_priv(dev);
14290 tp->pm_cap = pm_cap;
14291 tp->rx_mode = TG3_DEF_RX_MODE;
14292 tp->tx_mode = TG3_DEF_TX_MODE;
14295 tp->msg_enable = tg3_debug;
14297 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14299 /* The word/byte swap controls here control register access byte
14300 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14303 tp->misc_host_ctrl =
14304 MISC_HOST_CTRL_MASK_PCI_INT |
14305 MISC_HOST_CTRL_WORD_SWAP |
14306 MISC_HOST_CTRL_INDIR_ACCESS |
14307 MISC_HOST_CTRL_PCISTATE_RW;
14309 /* The NONFRM (non-frame) byte/word swap controls take effect
14310 * on descriptor entries, anything which isn't packet data.
14312 * The StrongARM chips on the board (one for tx, one for rx)
14313 * are running in big-endian mode.
14315 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14316 GRC_MODE_WSWAP_NONFRM_DATA);
14317 #ifdef __BIG_ENDIAN
14318 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14320 spin_lock_init(&tp->lock);
14321 spin_lock_init(&tp->indirect_lock);
14322 INIT_WORK(&tp->reset_task, tg3_reset_task);
14324 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14326 printk(KERN_ERR PFX "Cannot map device registers, "
14329 goto err_out_free_dev;
14332 tg3_init_link_config(tp);
14334 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14335 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14337 dev->ethtool_ops = &tg3_ethtool_ops;
14338 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14339 dev->irq = pdev->irq;
14341 err = tg3_get_invariants(tp);
14343 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14345 goto err_out_iounmap;
14348 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14349 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14350 dev->netdev_ops = &tg3_netdev_ops;
14352 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14355 /* The EPB bridge inside 5714, 5715, and 5780 and any
14356 * device behind the EPB cannot support DMA addresses > 40-bit.
14357 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14358 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14359 * do DMA address check in tg3_start_xmit().
14361 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14362 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14363 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14364 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14365 #ifdef CONFIG_HIGHMEM
14366 dma_mask = DMA_BIT_MASK(64);
14369 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14371 /* Configure DMA attributes. */
14372 if (dma_mask > DMA_BIT_MASK(32)) {
14373 err = pci_set_dma_mask(pdev, dma_mask);
14375 dev->features |= NETIF_F_HIGHDMA;
14376 err = pci_set_consistent_dma_mask(pdev,
14379 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14380 "DMA for consistent allocations\n");
14381 goto err_out_iounmap;
14385 if (err || dma_mask == DMA_BIT_MASK(32)) {
14386 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14388 printk(KERN_ERR PFX "No usable DMA configuration, "
14390 goto err_out_iounmap;
14394 tg3_init_bufmgr_config(tp);
14396 /* Selectively allow TSO based on operating conditions */
14397 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14398 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14399 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14401 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14402 tp->fw_needed = NULL;
14405 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14406 tp->fw_needed = FIRMWARE_TG3;
14408 /* TSO is on by default on chips that support hardware TSO.
14409 * Firmware TSO on older chips gives lower performance, so it
14410 * is off by default, but can be enabled using ethtool.
14412 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14413 (dev->features & NETIF_F_IP_CSUM))
14414 dev->features |= NETIF_F_TSO;
14416 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14417 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14418 if (dev->features & NETIF_F_IPV6_CSUM)
14419 dev->features |= NETIF_F_TSO6;
14420 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14422 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14423 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14426 dev->features |= NETIF_F_TSO_ECN;
14429 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14430 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14431 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14432 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14433 tp->rx_pending = 63;
14436 err = tg3_get_device_address(tp);
14438 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14444 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14445 if (!tp->aperegs) {
14446 printk(KERN_ERR PFX "Cannot map APE registers, "
14452 tg3_ape_lock_init(tp);
14454 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14455 tg3_read_dash_ver(tp);
14459 * Reset chip in case UNDI or EFI driver did not shutdown
14460 * DMA self test will enable WDMAC and we'll see (spurious)
14461 * pending DMA on the PCI bus at that point.
14463 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14464 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14465 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14466 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14469 err = tg3_test_dma(tp);
14471 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14472 goto err_out_apeunmap;
14475 /* flow control autonegotiation is default behavior */
14476 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14477 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14479 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14480 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14481 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14482 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14483 struct tg3_napi *tnapi = &tp->napi[i];
14486 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14488 tnapi->int_mbox = intmbx;
14494 tnapi->consmbox = rcvmbx;
14495 tnapi->prodmbox = sndmbx;
14498 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14499 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14501 tnapi->coal_now = HOSTCC_MODE_NOW;
14502 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14505 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14509 * If we support MSIX, we'll be using RSS. If we're using
14510 * RSS, the first vector only handles link interrupts and the
14511 * remaining vectors handle rx and tx interrupts. Reuse the
14512 * mailbox values for the next iteration. The values we setup
14513 * above are still useful for the single vectored mode.
14528 pci_set_drvdata(pdev, dev);
14530 err = register_netdev(dev);
14532 printk(KERN_ERR PFX "Cannot register net device, "
14534 goto err_out_apeunmap;
14537 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14539 tp->board_part_number,
14540 tp->pci_chip_rev_id,
14541 tg3_bus_string(tp, str),
14544 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14545 struct phy_device *phydev;
14546 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14548 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14549 tp->dev->name, phydev->drv->name,
14550 dev_name(&phydev->dev));
14553 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14554 tp->dev->name, tg3_phy_string(tp),
14555 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14556 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14557 "10/100/1000Base-T")),
14558 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14560 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14562 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14563 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14564 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14565 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14566 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14567 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14568 dev->name, tp->dma_rwctrl,
14569 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14570 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14576 iounmap(tp->aperegs);
14577 tp->aperegs = NULL;
14582 release_firmware(tp->fw);
14594 pci_release_regions(pdev);
14596 err_out_disable_pdev:
14597 pci_disable_device(pdev);
14598 pci_set_drvdata(pdev, NULL);
14602 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14604 struct net_device *dev = pci_get_drvdata(pdev);
14607 struct tg3 *tp = netdev_priv(dev);
14610 release_firmware(tp->fw);
14612 flush_scheduled_work();
14614 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14619 unregister_netdev(dev);
14621 iounmap(tp->aperegs);
14622 tp->aperegs = NULL;
14629 pci_release_regions(pdev);
14630 pci_disable_device(pdev);
14631 pci_set_drvdata(pdev, NULL);
14635 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14637 struct net_device *dev = pci_get_drvdata(pdev);
14638 struct tg3 *tp = netdev_priv(dev);
14639 pci_power_t target_state;
14642 /* PCI register 4 needs to be saved whether netif_running() or not.
14643 * MSI address and data need to be saved if using MSI and
14646 pci_save_state(pdev);
14648 if (!netif_running(dev))
14651 flush_scheduled_work();
14653 tg3_netif_stop(tp);
14655 del_timer_sync(&tp->timer);
14657 tg3_full_lock(tp, 1);
14658 tg3_disable_ints(tp);
14659 tg3_full_unlock(tp);
14661 netif_device_detach(dev);
14663 tg3_full_lock(tp, 0);
14664 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14665 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14666 tg3_full_unlock(tp);
14668 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14670 err = tg3_set_power_state(tp, target_state);
14674 tg3_full_lock(tp, 0);
14676 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14677 err2 = tg3_restart_hw(tp, 1);
14681 tp->timer.expires = jiffies + tp->timer_offset;
14682 add_timer(&tp->timer);
14684 netif_device_attach(dev);
14685 tg3_netif_start(tp);
14688 tg3_full_unlock(tp);
14697 static int tg3_resume(struct pci_dev *pdev)
14699 struct net_device *dev = pci_get_drvdata(pdev);
14700 struct tg3 *tp = netdev_priv(dev);
14703 pci_restore_state(tp->pdev);
14705 if (!netif_running(dev))
14708 err = tg3_set_power_state(tp, PCI_D0);
14712 netif_device_attach(dev);
14714 tg3_full_lock(tp, 0);
14716 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14717 err = tg3_restart_hw(tp, 1);
14721 tp->timer.expires = jiffies + tp->timer_offset;
14722 add_timer(&tp->timer);
14724 tg3_netif_start(tp);
14727 tg3_full_unlock(tp);
14735 static struct pci_driver tg3_driver = {
14736 .name = DRV_MODULE_NAME,
14737 .id_table = tg3_pci_tbl,
14738 .probe = tg3_init_one,
14739 .remove = __devexit_p(tg3_remove_one),
14740 .suspend = tg3_suspend,
14741 .resume = tg3_resume
14744 static int __init tg3_init(void)
14746 return pci_register_driver(&tg3_driver);
14749 static void __exit tg3_cleanup(void)
14751 pci_unregister_driver(&tg3_driver);
14754 module_init(tg3_init);
14755 module_exit(tg3_cleanup);