SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.103"
  72 #define DRV_MODULE_RELDATE      "November 2, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105 #define TG3_RSS_INDIR_TBL_SIZE 128
 106
 107 /* Do not place this n-ring entries value into the tp struct itself,
 108  * we really want to expose these constants to GCC so that modulo et
 109  * al.  operations are done with shifts and masks instead of with
 110  * hw multiply/modulo instructions.  Another solution would be to
 111  * replace things like '% foo' with '& (foo - 1)'.
 112  */
 113 #define TG3_RX_RCB_RING_SIZE(tp)        \
 114         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 115           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 116
 117 #define TG3_TX_RING_SIZE                512
 118 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 119
 120 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_RING_SIZE)
 122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 123                                  TG3_RX_JUMBO_RING_SIZE)
 124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 125                                  TG3_RX_RCB_RING_SIZE(tp))
 126 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 127                                  TG3_TX_RING_SIZE)
 128 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 129
 130 #define TG3_DMA_BYTE_ENAB               64
 131
 132 #define TG3_RX_STD_DMA_SZ               1536
 133 #define TG3_RX_JMB_DMA_SZ               9046
 134
 135 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 136
 137 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 138 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 139
 140 #define TG3_RX_STD_BUFF_RING_SIZE \
 141         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 142
 143 #define TG3_RX_JMB_BUFF_RING_SIZE \
 144         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 145
 146 /* minimum number of free TX descriptors required to wake up TX process */
 147 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 148
 149 #define TG3_RAW_IP_ALIGN 2
 150
 151 /* number of ETHTOOL_GSTATS u64's */
 152 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 153
 154 #define TG3_NUM_TEST            6
 155
 156 #define FIRMWARE_TG3            "tigon/tg3.bin"
 157 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 158 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 159
 160 static char version[] __devinitdata =
 161         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 162
 163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 165 MODULE_LICENSE("GPL");
 166 MODULE_VERSION(DRV_MODULE_VERSION);
 167 MODULE_FIRMWARE(FIRMWARE_TG3);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 170
 171 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 172
 173 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 174 module_param(tg3_debug, int, 0);
 175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 176
 177 static struct pci_device_id tg3_pci_tbl[] = {
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 251         {}
 252 };
 253
 254 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 255
 256 static const struct {
 257         const char string[ETH_GSTRING_LEN];
 258 } ethtool_stats_keys[TG3_NUM_STATS] = {
 259         { "rx_octets" },
 260         { "rx_fragments" },
 261         { "rx_ucast_packets" },
 262         { "rx_mcast_packets" },
 263         { "rx_bcast_packets" },
 264         { "rx_fcs_errors" },
 265         { "rx_align_errors" },
 266         { "rx_xon_pause_rcvd" },
 267         { "rx_xoff_pause_rcvd" },
 268         { "rx_mac_ctrl_rcvd" },
 269         { "rx_xoff_entered" },
 270         { "rx_frame_too_long_errors" },
 271         { "rx_jabbers" },
 272         { "rx_undersize_packets" },
 273         { "rx_in_length_errors" },
 274         { "rx_out_length_errors" },
 275         { "rx_64_or_less_octet_packets" },
 276         { "rx_65_to_127_octet_packets" },
 277         { "rx_128_to_255_octet_packets" },
 278         { "rx_256_to_511_octet_packets" },
 279         { "rx_512_to_1023_octet_packets" },
 280         { "rx_1024_to_1522_octet_packets" },
 281         { "rx_1523_to_2047_octet_packets" },
 282         { "rx_2048_to_4095_octet_packets" },
 283         { "rx_4096_to_8191_octet_packets" },
 284         { "rx_8192_to_9022_octet_packets" },
 285
 286         { "tx_octets" },
 287         { "tx_collisions" },
 288
 289         { "tx_xon_sent" },
 290         { "tx_xoff_sent" },
 291         { "tx_flow_control" },
 292         { "tx_mac_errors" },
 293         { "tx_single_collisions" },
 294         { "tx_mult_collisions" },
 295         { "tx_deferred" },
 296         { "tx_excessive_collisions" },
 297         { "tx_late_collisions" },
 298         { "tx_collide_2times" },
 299         { "tx_collide_3times" },
 300         { "tx_collide_4times" },
 301         { "tx_collide_5times" },
 302         { "tx_collide_6times" },
 303         { "tx_collide_7times" },
 304         { "tx_collide_8times" },
 305         { "tx_collide_9times" },
 306         { "tx_collide_10times" },
 307         { "tx_collide_11times" },
 308         { "tx_collide_12times" },
 309         { "tx_collide_13times" },
 310         { "tx_collide_14times" },
 311         { "tx_collide_15times" },
 312         { "tx_ucast_packets" },
 313         { "tx_mcast_packets" },
 314         { "tx_bcast_packets" },
 315         { "tx_carrier_sense_errors" },
 316         { "tx_discards" },
 317         { "tx_errors" },
 318
 319         { "dma_writeq_full" },
 320         { "dma_write_prioq_full" },
 321         { "rxbds_empty" },
 322         { "rx_discards" },
 323         { "rx_errors" },
 324         { "rx_threshold_hit" },
 325
 326         { "dma_readq_full" },
 327         { "dma_read_prioq_full" },
 328         { "tx_comp_queue_full" },
 329
 330         { "ring_set_send_prod_index" },
 331         { "ring_status_update" },
 332         { "nic_irqs" },
 333         { "nic_avoided_irqs" },
 334         { "nic_tx_threshold_hit" }
 335 };
 336
 337 static const struct {
 338         const char string[ETH_GSTRING_LEN];
 339 } ethtool_test_keys[TG3_NUM_TEST] = {
 340         { "nvram test     (online) " },
 341         { "link test      (online) " },
 342         { "register test  (offline)" },
 343         { "memory test    (offline)" },
 344         { "loopback test  (offline)" },
 345         { "interrupt test (offline)" },
 346 };
 347
 348 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 349 {
 350         writel(val, tp->regs + off);
 351 }
 352
 353 static u32 tg3_read32(struct tg3 *tp, u32 off)
 354 {
 355         return (readl(tp->regs + off));
 356 }
 357
 358 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 359 {
 360         writel(val, tp->aperegs + off);
 361 }
 362
 363 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 364 {
 365         return (readl(tp->aperegs + off));
 366 }
 367
 368 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 369 {
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&tp->indirect_lock, flags);
 373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 374         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 376 }
 377
 378 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 379 {
 380         writel(val, tp->regs + off);
 381         readl(tp->regs + off);
 382 }
 383
 384 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 385 {
 386         unsigned long flags;
 387         u32 val;
 388
 389         spin_lock_irqsave(&tp->indirect_lock, flags);
 390         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 391         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 392         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 393         return val;
 394 }
 395
 396 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 397 {
 398         unsigned long flags;
 399
 400         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 401                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 402                                        TG3_64BIT_REG_LOW, val);
 403                 return;
 404         }
 405         if (off == TG3_RX_STD_PROD_IDX_REG) {
 406                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 407                                        TG3_64BIT_REG_LOW, val);
 408                 return;
 409         }
 410
 411         spin_lock_irqsave(&tp->indirect_lock, flags);
 412         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 413         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 414         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 415
 416         /* In indirect mode when disabling interrupts, we also need
 417          * to clear the interrupt bit in the GRC local ctrl register.
 418          */
 419         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 420             (val == 0x1)) {
 421                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 422                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 423         }
 424 }
 425
 426 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 427 {
 428         unsigned long flags;
 429         u32 val;
 430
 431         spin_lock_irqsave(&tp->indirect_lock, flags);
 432         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 433         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 434         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 435         return val;
 436 }
 437
 438 /* usec_wait specifies the wait time in usec when writing to certain registers
 439  * where it is unsafe to read back the register without some delay.
 440  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 441  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 442  */
 443 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 444 {
 445         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 446             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 447                 /* Non-posted methods */
 448                 tp->write32(tp, off, val);
 449         else {
 450                 /* Posted method */
 451                 tg3_write32(tp, off, val);
 452                 if (usec_wait)
 453                         udelay(usec_wait);
 454                 tp->read32(tp, off);
 455         }
 456         /* Wait again after the read for the posted method to guarantee that
 457          * the wait time is met.
 458          */
 459         if (usec_wait)
 460                 udelay(usec_wait);
 461 }
 462
 463 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 464 {
 465         tp->write32_mbox(tp, off, val);
 466         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 467             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 468                 tp->read32_mbox(tp, off);
 469 }
 470
 471 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 472 {
 473         void __iomem *mbox = tp->regs + off;
 474         writel(val, mbox);
 475         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 476                 writel(val, mbox);
 477         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 478                 readl(mbox);
 479 }
 480
 481 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 482 {
 483         return (readl(tp->regs + off + GRCMBOX_BASE));
 484 }
 485
 486 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 487 {
 488         writel(val, tp->regs + off + GRCMBOX_BASE);
 489 }
 490
 491 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 492 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 493 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 494 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 495 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 496
 497 #define tw32(reg,val)           tp->write32(tp, reg, val)
 498 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 499 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 500 #define tr32(reg)               tp->read32(tp, reg)
 501
 502 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         unsigned long flags;
 505
 506         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 507             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 508                 return;
 509
 510         spin_lock_irqsave(&tp->indirect_lock, flags);
 511         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 512                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 513                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 514
 515                 /* Always leave this as zero. */
 516                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 517         } else {
 518                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 519                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 520
 521                 /* Always leave this as zero. */
 522                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 523         }
 524         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 525 }
 526
 527 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 528 {
 529         unsigned long flags;
 530
 531         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 532             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 533                 *val = 0;
 534                 return;
 535         }
 536
 537         spin_lock_irqsave(&tp->indirect_lock, flags);
 538         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 539                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 540                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 541
 542                 /* Always leave this as zero. */
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 544         } else {
 545                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 546                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 547
 548                 /* Always leave this as zero. */
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 550         }
 551         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 552 }
 553
 554 static void tg3_ape_lock_init(struct tg3 *tp)
 555 {
 556         int i;
 557
 558         /* Make sure the driver hasn't any stale locks. */
 559         for (i = 0; i < 8; i++)
 560                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 561                                 APE_LOCK_GRANT_DRIVER);
 562 }
 563
 564 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 565 {
 566         int i, off;
 567         int ret = 0;
 568         u32 status;
 569
 570         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 571                 return 0;
 572
 573         switch (locknum) {
 574                 case TG3_APE_LOCK_GRC:
 575                 case TG3_APE_LOCK_MEM:
 576                         break;
 577                 default:
 578                         return -EINVAL;
 579         }
 580
 581         off = 4 * locknum;
 582
 583         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 584
 585         /* Wait for up to 1 millisecond to acquire lock. */
 586         for (i = 0; i < 100; i++) {
 587                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 588                 if (status == APE_LOCK_GRANT_DRIVER)
 589                         break;
 590                 udelay(10);
 591         }
 592
 593         if (status != APE_LOCK_GRANT_DRIVER) {
 594                 /* Revoke the lock request. */
 595                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 596                                 APE_LOCK_GRANT_DRIVER);
 597
 598                 ret = -EBUSY;
 599         }
 600
 601         return ret;
 602 }
 603
 604 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 605 {
 606         int off;
 607
 608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 609                 return;
 610
 611         switch (locknum) {
 612                 case TG3_APE_LOCK_GRC:
 613                 case TG3_APE_LOCK_MEM:
 614                         break;
 615                 default:
 616                         return;
 617         }
 618
 619         off = 4 * locknum;
 620         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 621 }
 622
 623 static void tg3_disable_ints(struct tg3 *tp)
 624 {
 625         int i;
 626
 627         tw32(TG3PCI_MISC_HOST_CTRL,
 628              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 629         for (i = 0; i < tp->irq_max; i++)
 630                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 631 }
 632
 633 static void tg3_enable_ints(struct tg3 *tp)
 634 {
 635         int i;
 636         u32 coal_now = 0;
 637
 638         tp->irq_sync = 0;
 639         wmb();
 640
 641         tw32(TG3PCI_MISC_HOST_CTRL,
 642              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 643
 644         for (i = 0; i < tp->irq_cnt; i++) {
 645                 struct tg3_napi *tnapi = &tp->napi[i];
 646                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 647                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 648                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 649
 650                 coal_now |= tnapi->coal_now;
 651         }
 652
 653         /* Force an initial interrupt */
 654         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 655             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 656                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 657         else
 658                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 659                      HOSTCC_MODE_ENABLE | coal_now);
 660 }
 661
 662 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 663 {
 664         struct tg3 *tp = tnapi->tp;
 665         struct tg3_hw_status *sblk = tnapi->hw_status;
 666         unsigned int work_exists = 0;
 667
 668         /* check for phy events */
 669         if (!(tp->tg3_flags &
 670               (TG3_FLAG_USE_LINKCHG_REG |
 671                TG3_FLAG_POLL_SERDES))) {
 672                 if (sblk->status & SD_STATUS_LINK_CHG)
 673                         work_exists = 1;
 674         }
 675         /* check for RX/TX work to do */
 676         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 677             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 678                 work_exists = 1;
 679
 680         return work_exists;
 681 }
 682
 683 /* tg3_int_reenable
 684  *  similar to tg3_enable_ints, but it accurately determines whether there
 685  *  is new work pending and can return without flushing the PIO write
 686  *  which reenables interrupts
 687  */
 688 static void tg3_int_reenable(struct tg3_napi *tnapi)
 689 {
 690         struct tg3 *tp = tnapi->tp;
 691
 692         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 693         mmiowb();
 694
 695         /* When doing tagged status, this work check is unnecessary.
 696          * The last_tag we write above tells the chip which piece of
 697          * work we've completed.
 698          */
 699         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 700             tg3_has_work(tnapi))
 701                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 702                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 703 }
 704
 705 static void tg3_napi_disable(struct tg3 *tp)
 706 {
 707         int i;
 708
 709         for (i = tp->irq_cnt - 1; i >= 0; i--)
 710                 napi_disable(&tp->napi[i].napi);
 711 }
 712
 713 static void tg3_napi_enable(struct tg3 *tp)
 714 {
 715         int i;
 716
 717         for (i = 0; i < tp->irq_cnt; i++)
 718                 napi_enable(&tp->napi[i].napi);
 719 }
 720
 721 static inline void tg3_netif_stop(struct tg3 *tp)
 722 {
 723         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 724         tg3_napi_disable(tp);
 725         netif_tx_disable(tp->dev);
 726 }
 727
 728 static inline void tg3_netif_start(struct tg3 *tp)
 729 {
 730         /* NOTE: unconditional netif_tx_wake_all_queues is only
 731          * appropriate so long as all callers are assured to
 732          * have free tx slots (such as after tg3_init_hw)
 733          */
 734         netif_tx_wake_all_queues(tp->dev);
 735
 736         tg3_napi_enable(tp);
 737         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 738         tg3_enable_ints(tp);
 739 }
 740
 741 static void tg3_switch_clocks(struct tg3 *tp)
 742 {
 743         u32 clock_ctrl;
 744         u32 orig_clock_ctrl;
 745
 746         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 747             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 748                 return;
 749
 750         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 751
 752         orig_clock_ctrl = clock_ctrl;
 753         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 754                        CLOCK_CTRL_CLKRUN_OENABLE |
 755                        0x1f);
 756         tp->pci_clock_ctrl = clock_ctrl;
 757
 758         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 759                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 760                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 761                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 762                 }
 763         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 764                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 765                             clock_ctrl |
 766                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 767                             40);
 768                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 769                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 770                             40);
 771         }
 772         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 773 }
 774
 775 #define PHY_BUSY_LOOPS  5000
 776
 777 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 778 {
 779         u32 frame_val;
 780         unsigned int loops;
 781         int ret;
 782
 783         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 784                 tw32_f(MAC_MI_MODE,
 785                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 786                 udelay(80);
 787         }
 788
 789         *val = 0x0;
 790
 791         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 792                       MI_COM_PHY_ADDR_MASK);
 793         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 794                       MI_COM_REG_ADDR_MASK);
 795         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 796
 797         tw32_f(MAC_MI_COM, frame_val);
 798
 799         loops = PHY_BUSY_LOOPS;
 800         while (loops != 0) {
 801                 udelay(10);
 802                 frame_val = tr32(MAC_MI_COM);
 803
 804                 if ((frame_val & MI_COM_BUSY) == 0) {
 805                         udelay(5);
 806                         frame_val = tr32(MAC_MI_COM);
 807                         break;
 808                 }
 809                 loops -= 1;
 810         }
 811
 812         ret = -EBUSY;
 813         if (loops != 0) {
 814                 *val = frame_val & MI_COM_DATA_MASK;
 815                 ret = 0;
 816         }
 817
 818         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 819                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 820                 udelay(80);
 821         }
 822
 823         return ret;
 824 }
 825
 826 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 827 {
 828         u32 frame_val;
 829         unsigned int loops;
 830         int ret;
 831
 832         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 833             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 834                 return 0;
 835
 836         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 837                 tw32_f(MAC_MI_MODE,
 838                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 839                 udelay(80);
 840         }
 841
 842         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 843                       MI_COM_PHY_ADDR_MASK);
 844         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 845                       MI_COM_REG_ADDR_MASK);
 846         frame_val |= (val & MI_COM_DATA_MASK);
 847         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 848
 849         tw32_f(MAC_MI_COM, frame_val);
 850
 851         loops = PHY_BUSY_LOOPS;
 852         while (loops != 0) {
 853                 udelay(10);
 854                 frame_val = tr32(MAC_MI_COM);
 855                 if ((frame_val & MI_COM_BUSY) == 0) {
 856                         udelay(5);
 857                         frame_val = tr32(MAC_MI_COM);
 858                         break;
 859                 }
 860                 loops -= 1;
 861         }
 862
 863         ret = -EBUSY;
 864         if (loops != 0)
 865                 ret = 0;
 866
 867         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 868                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 869                 udelay(80);
 870         }
 871
 872         return ret;
 873 }
 874
 875 static int tg3_bmcr_reset(struct tg3 *tp)
 876 {
 877         u32 phy_control;
 878         int limit, err;
 879
 880         /* OK, reset it, and poll the BMCR_RESET bit until it
 881          * clears or we time out.
 882          */
 883         phy_control = BMCR_RESET;
 884         err = tg3_writephy(tp, MII_BMCR, phy_control);
 885         if (err != 0)
 886                 return -EBUSY;
 887
 888         limit = 5000;
 889         while (limit--) {
 890                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 891                 if (err != 0)
 892                         return -EBUSY;
 893
 894                 if ((phy_control & BMCR_RESET) == 0) {
 895                         udelay(40);
 896                         break;
 897                 }
 898                 udelay(10);
 899         }
 900         if (limit < 0)
 901                 return -EBUSY;
 902
 903         return 0;
 904 }
 905
 906 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 907 {
 908         struct tg3 *tp = bp->priv;
 909         u32 val;
 910
 911         spin_lock_bh(&tp->lock);
 912
 913         if (tg3_readphy(tp, reg, &val))
 914                 val = -EIO;
 915
 916         spin_unlock_bh(&tp->lock);
 917
 918         return val;
 919 }
 920
 921 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 922 {
 923         struct tg3 *tp = bp->priv;
 924         u32 ret = 0;
 925
 926         spin_lock_bh(&tp->lock);
 927
 928         if (tg3_writephy(tp, reg, val))
 929                 ret = -EIO;
 930
 931         spin_unlock_bh(&tp->lock);
 932
 933         return ret;
 934 }
 935
 936 static int tg3_mdio_reset(struct mii_bus *bp)
 937 {
 938         return 0;
 939 }
 940
 941 static void tg3_mdio_config_5785(struct tg3 *tp)
 942 {
 943         u32 val;
 944         struct phy_device *phydev;
 945
 946         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 947         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 948         case TG3_PHY_ID_BCM50610:
 949         case TG3_PHY_ID_BCM50610M:
 950                 val = MAC_PHYCFG2_50610_LED_MODES;
 951                 break;
 952         case TG3_PHY_ID_BCMAC131:
 953                 val = MAC_PHYCFG2_AC131_LED_MODES;
 954                 break;
 955         case TG3_PHY_ID_RTL8211C:
 956                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 957                 break;
 958         case TG3_PHY_ID_RTL8201E:
 959                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 960                 break;
 961         default:
 962                 return;
 963         }
 964
 965         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 966                 tw32(MAC_PHYCFG2, val);
 967
 968                 val = tr32(MAC_PHYCFG1);
 969                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 970                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 971                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 972                 tw32(MAC_PHYCFG1, val);
 973
 974                 return;
 975         }
 976
 977         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 978                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 979                        MAC_PHYCFG2_FMODE_MASK_MASK |
 980                        MAC_PHYCFG2_GMODE_MASK_MASK |
 981                        MAC_PHYCFG2_ACT_MASK_MASK   |
 982                        MAC_PHYCFG2_QUAL_MASK_MASK |
 983                        MAC_PHYCFG2_INBAND_ENABLE;
 984
 985         tw32(MAC_PHYCFG2, val);
 986
 987         val = tr32(MAC_PHYCFG1);
 988         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 989                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 990         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 991                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 992                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 993                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 994                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 995         }
 996         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 997                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 998         tw32(MAC_PHYCFG1, val);
 999
1000         val = tr32(MAC_EXT_RGMII_MODE);
1001         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1002                  MAC_RGMII_MODE_RX_QUALITY |
1003                  MAC_RGMII_MODE_RX_ACTIVITY |
1004                  MAC_RGMII_MODE_RX_ENG_DET |
1005                  MAC_RGMII_MODE_TX_ENABLE |
1006                  MAC_RGMII_MODE_TX_LOWPWR |
1007                  MAC_RGMII_MODE_TX_RESET);
1008         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1010                         val |= MAC_RGMII_MODE_RX_INT_B |
1011                                MAC_RGMII_MODE_RX_QUALITY |
1012                                MAC_RGMII_MODE_RX_ACTIVITY |
1013                                MAC_RGMII_MODE_RX_ENG_DET;
1014                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1015                         val |= MAC_RGMII_MODE_TX_ENABLE |
1016                                MAC_RGMII_MODE_TX_LOWPWR |
1017                                MAC_RGMII_MODE_TX_RESET;
1018         }
1019         tw32(MAC_EXT_RGMII_MODE, val);
1020 }
1021
1022 static void tg3_mdio_start(struct tg3 *tp)
1023 {
1024         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1025         tw32_f(MAC_MI_MODE, tp->mi_mode);
1026         udelay(80);
1027
1028         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1029                 u32 funcnum, is_serdes;
1030
1031                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1032                 if (funcnum)
1033                         tp->phy_addr = 2;
1034                 else
1035                         tp->phy_addr = 1;
1036
1037                 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1038                 if (is_serdes)
1039                         tp->phy_addr += 7;
1040         } else
1041                 tp->phy_addr = TG3_PHY_MII_ADDR;
1042
1043         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1045                 tg3_mdio_config_5785(tp);
1046 }
1047
1048 static int tg3_mdio_init(struct tg3 *tp)
1049 {
1050         int i;
1051         u32 reg;
1052         struct phy_device *phydev;
1053
1054         tg3_mdio_start(tp);
1055
1056         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1057             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1058                 return 0;
1059
1060         tp->mdio_bus = mdiobus_alloc();
1061         if (tp->mdio_bus == NULL)
1062                 return -ENOMEM;
1063
1064         tp->mdio_bus->name     = "tg3 mdio bus";
1065         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1066                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1067         tp->mdio_bus->priv     = tp;
1068         tp->mdio_bus->parent   = &tp->pdev->dev;
1069         tp->mdio_bus->read     = &tg3_mdio_read;
1070         tp->mdio_bus->write    = &tg3_mdio_write;
1071         tp->mdio_bus->reset    = &tg3_mdio_reset;
1072         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1073         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1074
1075         for (i = 0; i < PHY_MAX_ADDR; i++)
1076                 tp->mdio_bus->irq[i] = PHY_POLL;
1077
1078         /* The bus registration will look for all the PHYs on the mdio bus.
1079          * Unfortunately, it does not ensure the PHY is powered up before
1080          * accessing the PHY ID registers.  A chip reset is the
1081          * quickest way to bring the device back to an operational state..
1082          */
1083         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1084                 tg3_bmcr_reset(tp);
1085
1086         i = mdiobus_register(tp->mdio_bus);
1087         if (i) {
1088                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1089                         tp->dev->name, i);
1090                 mdiobus_free(tp->mdio_bus);
1091                 return i;
1092         }
1093
1094         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1095
1096         if (!phydev || !phydev->drv) {
1097                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1098                 mdiobus_unregister(tp->mdio_bus);
1099                 mdiobus_free(tp->mdio_bus);
1100                 return -ENODEV;
1101         }
1102
1103         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1104         case TG3_PHY_ID_BCM57780:
1105                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1106                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1107                 break;
1108         case TG3_PHY_ID_BCM50610:
1109         case TG3_PHY_ID_BCM50610M:
1110                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1111                                      PHY_BRCM_RX_REFCLK_UNUSED |
1112                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1113                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1114                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1115                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1116                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1117                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1118                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1119                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1120                 /* fallthru */
1121         case TG3_PHY_ID_RTL8211C:
1122                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1123                 break;
1124         case TG3_PHY_ID_RTL8201E:
1125         case TG3_PHY_ID_BCMAC131:
1126                 phydev->interface = PHY_INTERFACE_MODE_MII;
1127                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1128                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1129                 break;
1130         }
1131
1132         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1133
1134         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1135                 tg3_mdio_config_5785(tp);
1136
1137         return 0;
1138 }
1139
1140 static void tg3_mdio_fini(struct tg3 *tp)
1141 {
1142         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1143                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1144                 mdiobus_unregister(tp->mdio_bus);
1145                 mdiobus_free(tp->mdio_bus);
1146         }
1147 }
1148
1149 /* tp->lock is held. */
1150 static inline void tg3_generate_fw_event(struct tg3 *tp)
1151 {
1152         u32 val;
1153
1154         val = tr32(GRC_RX_CPU_EVENT);
1155         val |= GRC_RX_CPU_DRIVER_EVENT;
1156         tw32_f(GRC_RX_CPU_EVENT, val);
1157
1158         tp->last_event_jiffies = jiffies;
1159 }
1160
1161 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1162
1163 /* tp->lock is held. */
1164 static void tg3_wait_for_event_ack(struct tg3 *tp)
1165 {
1166         int i;
1167         unsigned int delay_cnt;
1168         long time_remain;
1169
1170         /* If enough time has passed, no wait is necessary. */
1171         time_remain = (long)(tp->last_event_jiffies + 1 +
1172                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1173                       (long)jiffies;
1174         if (time_remain < 0)
1175                 return;
1176
1177         /* Check if we can shorten the wait time. */
1178         delay_cnt = jiffies_to_usecs(time_remain);
1179         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1180                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1181         delay_cnt = (delay_cnt >> 3) + 1;
1182
1183         for (i = 0; i < delay_cnt; i++) {
1184                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1185                         break;
1186                 udelay(8);
1187         }
1188 }
1189
1190 /* tp->lock is held. */
1191 static void tg3_ump_link_report(struct tg3 *tp)
1192 {
1193         u32 reg;
1194         u32 val;
1195
1196         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1197             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1198                 return;
1199
1200         tg3_wait_for_event_ack(tp);
1201
1202         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1203
1204         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1205
1206         val = 0;
1207         if (!tg3_readphy(tp, MII_BMCR, &reg))
1208                 val = reg << 16;
1209         if (!tg3_readphy(tp, MII_BMSR, &reg))
1210                 val |= (reg & 0xffff);
1211         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1212
1213         val = 0;
1214         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1215                 val = reg << 16;
1216         if (!tg3_readphy(tp, MII_LPA, &reg))
1217                 val |= (reg & 0xffff);
1218         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1219
1220         val = 0;
1221         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1222                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1223                         val = reg << 16;
1224                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1225                         val |= (reg & 0xffff);
1226         }
1227         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1228
1229         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1230                 val = reg << 16;
1231         else
1232                 val = 0;
1233         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1234
1235         tg3_generate_fw_event(tp);
1236 }
1237
1238 static void tg3_link_report(struct tg3 *tp)
1239 {
1240         if (!netif_carrier_ok(tp->dev)) {
1241                 if (netif_msg_link(tp))
1242                         printk(KERN_INFO PFX "%s: Link is down.\n",
1243                                tp->dev->name);
1244                 tg3_ump_link_report(tp);
1245         } else if (netif_msg_link(tp)) {
1246                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1247                        tp->dev->name,
1248                        (tp->link_config.active_speed == SPEED_1000 ?
1249                         1000 :
1250                         (tp->link_config.active_speed == SPEED_100 ?
1251                          100 : 10)),
1252                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1253                         "full" : "half"));
1254
1255                 printk(KERN_INFO PFX
1256                        "%s: Flow control is %s for TX and %s for RX.\n",
1257                        tp->dev->name,
1258                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1259                        "on" : "off",
1260                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1261                        "on" : "off");
1262                 tg3_ump_link_report(tp);
1263         }
1264 }
1265
1266 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1267 {
1268         u16 miireg;
1269
1270         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1271                 miireg = ADVERTISE_PAUSE_CAP;
1272         else if (flow_ctrl & FLOW_CTRL_TX)
1273                 miireg = ADVERTISE_PAUSE_ASYM;
1274         else if (flow_ctrl & FLOW_CTRL_RX)
1275                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1276         else
1277                 miireg = 0;
1278
1279         return miireg;
1280 }
1281
1282 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1283 {
1284         u16 miireg;
1285
1286         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1287                 miireg = ADVERTISE_1000XPAUSE;
1288         else if (flow_ctrl & FLOW_CTRL_TX)
1289                 miireg = ADVERTISE_1000XPSE_ASYM;
1290         else if (flow_ctrl & FLOW_CTRL_RX)
1291                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1292         else
1293                 miireg = 0;
1294
1295         return miireg;
1296 }
1297
1298 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1299 {
1300         u8 cap = 0;
1301
1302         if (lcladv & ADVERTISE_1000XPAUSE) {
1303                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1304                         if (rmtadv & LPA_1000XPAUSE)
1305                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1306                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1307                                 cap = FLOW_CTRL_RX;
1308                 } else {
1309                         if (rmtadv & LPA_1000XPAUSE)
1310                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1311                 }
1312         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1313                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1314                         cap = FLOW_CTRL_TX;
1315         }
1316
1317         return cap;
1318 }
1319
1320 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1321 {
1322         u8 autoneg;
1323         u8 flowctrl = 0;
1324         u32 old_rx_mode = tp->rx_mode;
1325         u32 old_tx_mode = tp->tx_mode;
1326
1327         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1328                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1329         else
1330                 autoneg = tp->link_config.autoneg;
1331
1332         if (autoneg == AUTONEG_ENABLE &&
1333             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1334                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1335                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1336                 else
1337                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1338         } else
1339                 flowctrl = tp->link_config.flowctrl;
1340
1341         tp->link_config.active_flowctrl = flowctrl;
1342
1343         if (flowctrl & FLOW_CTRL_RX)
1344                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1345         else
1346                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1347
1348         if (old_rx_mode != tp->rx_mode)
1349                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1350
1351         if (flowctrl & FLOW_CTRL_TX)
1352                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1353         else
1354                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1355
1356         if (old_tx_mode != tp->tx_mode)
1357                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1358 }
1359
1360 static void tg3_adjust_link(struct net_device *dev)
1361 {
1362         u8 oldflowctrl, linkmesg = 0;
1363         u32 mac_mode, lcl_adv, rmt_adv;
1364         struct tg3 *tp = netdev_priv(dev);
1365         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1366
1367         spin_lock_bh(&tp->lock);
1368
1369         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1370                                     MAC_MODE_HALF_DUPLEX);
1371
1372         oldflowctrl = tp->link_config.active_flowctrl;
1373
1374         if (phydev->link) {
1375                 lcl_adv = 0;
1376                 rmt_adv = 0;
1377
1378                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1379                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1380                 else if (phydev->speed == SPEED_1000 ||
1381                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1382                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1383                 else
1384                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1385
1386                 if (phydev->duplex == DUPLEX_HALF)
1387                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1388                 else {
1389                         lcl_adv = tg3_advert_flowctrl_1000T(
1390                                   tp->link_config.flowctrl);
1391
1392                         if (phydev->pause)
1393                                 rmt_adv = LPA_PAUSE_CAP;
1394                         if (phydev->asym_pause)
1395                                 rmt_adv |= LPA_PAUSE_ASYM;
1396                 }
1397
1398                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1399         } else
1400                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1401
1402         if (mac_mode != tp->mac_mode) {
1403                 tp->mac_mode = mac_mode;
1404                 tw32_f(MAC_MODE, tp->mac_mode);
1405                 udelay(40);
1406         }
1407
1408         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1409                 if (phydev->speed == SPEED_10)
1410                         tw32(MAC_MI_STAT,
1411                              MAC_MI_STAT_10MBPS_MODE |
1412                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1413                 else
1414                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1415         }
1416
1417         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1418                 tw32(MAC_TX_LENGTHS,
1419                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1420                       (6 << TX_LENGTHS_IPG_SHIFT) |
1421                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1422         else
1423                 tw32(MAC_TX_LENGTHS,
1424                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1425                       (6 << TX_LENGTHS_IPG_SHIFT) |
1426                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1427
1428         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1429             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1430             phydev->speed != tp->link_config.active_speed ||
1431             phydev->duplex != tp->link_config.active_duplex ||
1432             oldflowctrl != tp->link_config.active_flowctrl)
1433             linkmesg = 1;
1434
1435         tp->link_config.active_speed = phydev->speed;
1436         tp->link_config.active_duplex = phydev->duplex;
1437
1438         spin_unlock_bh(&tp->lock);
1439
1440         if (linkmesg)
1441                 tg3_link_report(tp);
1442 }
1443
1444 static int tg3_phy_init(struct tg3 *tp)
1445 {
1446         struct phy_device *phydev;
1447
1448         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1449                 return 0;
1450
1451         /* Bring the PHY back to a known state. */
1452         tg3_bmcr_reset(tp);
1453
1454         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1455
1456         /* Attach the MAC to the PHY. */
1457         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1458                              phydev->dev_flags, phydev->interface);
1459         if (IS_ERR(phydev)) {
1460                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1461                 return PTR_ERR(phydev);
1462         }
1463
1464         /* Mask with MAC supported features. */
1465         switch (phydev->interface) {
1466         case PHY_INTERFACE_MODE_GMII:
1467         case PHY_INTERFACE_MODE_RGMII:
1468                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1469                         phydev->supported &= (PHY_GBIT_FEATURES |
1470                                               SUPPORTED_Pause |
1471                                               SUPPORTED_Asym_Pause);
1472                         break;
1473                 }
1474                 /* fallthru */
1475         case PHY_INTERFACE_MODE_MII:
1476                 phydev->supported &= (PHY_BASIC_FEATURES |
1477                                       SUPPORTED_Pause |
1478                                       SUPPORTED_Asym_Pause);
1479                 break;
1480         default:
1481                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1482                 return -EINVAL;
1483         }
1484
1485         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1486
1487         phydev->advertising = phydev->supported;
1488
1489         return 0;
1490 }
1491
1492 static void tg3_phy_start(struct tg3 *tp)
1493 {
1494         struct phy_device *phydev;
1495
1496         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1497                 return;
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         if (tp->link_config.phy_is_low_power) {
1502                 tp->link_config.phy_is_low_power = 0;
1503                 phydev->speed = tp->link_config.orig_speed;
1504                 phydev->duplex = tp->link_config.orig_duplex;
1505                 phydev->autoneg = tp->link_config.orig_autoneg;
1506                 phydev->advertising = tp->link_config.orig_advertising;
1507         }
1508
1509         phy_start(phydev);
1510
1511         phy_start_aneg(phydev);
1512 }
1513
1514 static void tg3_phy_stop(struct tg3 *tp)
1515 {
1516         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1517                 return;
1518
1519         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1520 }
1521
1522 static void tg3_phy_fini(struct tg3 *tp)
1523 {
1524         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1525                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1526                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1527         }
1528 }
1529
1530 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1531 {
1532         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1533         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1534 }
1535
1536 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1537 {
1538         u32 phytest;
1539
1540         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1541                 u32 phy;
1542
1543                 tg3_writephy(tp, MII_TG3_FET_TEST,
1544                              phytest | MII_TG3_FET_SHADOW_EN);
1545                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1546                         if (enable)
1547                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1548                         else
1549                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1550                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1551                 }
1552                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1553         }
1554 }
1555
1556 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1557 {
1558         u32 reg;
1559
1560         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1561                 return;
1562
1563         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1564                 tg3_phy_fet_toggle_apd(tp, enable);
1565                 return;
1566         }
1567
1568         reg = MII_TG3_MISC_SHDW_WREN |
1569               MII_TG3_MISC_SHDW_SCR5_SEL |
1570               MII_TG3_MISC_SHDW_SCR5_LPED |
1571               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1572               MII_TG3_MISC_SHDW_SCR5_SDTL |
1573               MII_TG3_MISC_SHDW_SCR5_C125OE;
1574         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1575                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1576
1577         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1578
1579
1580         reg = MII_TG3_MISC_SHDW_WREN |
1581               MII_TG3_MISC_SHDW_APD_SEL |
1582               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1583         if (enable)
1584                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1585
1586         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1587 }
1588
1589 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1590 {
1591         u32 phy;
1592
1593         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1594             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1595                 return;
1596
1597         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1598                 u32 ephy;
1599
1600                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1601                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1602
1603                         tg3_writephy(tp, MII_TG3_FET_TEST,
1604                                      ephy | MII_TG3_FET_SHADOW_EN);
1605                         if (!tg3_readphy(tp, reg, &phy)) {
1606                                 if (enable)
1607                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1608                                 else
1609                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1610                                 tg3_writephy(tp, reg, phy);
1611                         }
1612                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1613                 }
1614         } else {
1615                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1616                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1617                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1618                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1621                         else
1622                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1623                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1624                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1625                 }
1626         }
1627 }
1628
1629 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1630 {
1631         u32 val;
1632
1633         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1634                 return;
1635
1636         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1637             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1638                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1639                              (val | (1 << 15) | (1 << 4)));
1640 }
1641
1642 static void tg3_phy_apply_otp(struct tg3 *tp)
1643 {
1644         u32 otp, phy;
1645
1646         if (!tp->phy_otp)
1647                 return;
1648
1649         otp = tp->phy_otp;
1650
1651         /* Enable SM_DSP clock and tx 6dB coding. */
1652         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1653               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1654               MII_TG3_AUXCTL_ACTL_TX_6DB;
1655         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1656
1657         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1658         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1659         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1660
1661         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1662               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1663         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1664
1665         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1666         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1667         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1668
1669         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1670         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1671
1672         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1673         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1674
1675         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1676               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1677         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1678
1679         /* Turn off SM_DSP clock. */
1680         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1681               MII_TG3_AUXCTL_ACTL_TX_6DB;
1682         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1683 }
1684
1685 static int tg3_wait_macro_done(struct tg3 *tp)
1686 {
1687         int limit = 100;
1688
1689         while (limit--) {
1690                 u32 tmp32;
1691
1692                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1693                         if ((tmp32 & 0x1000) == 0)
1694                                 break;
1695                 }
1696         }
1697         if (limit < 0)
1698                 return -EBUSY;
1699
1700         return 0;
1701 }
1702
1703 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1704 {
1705         static const u32 test_pat[4][6] = {
1706         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1707         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1708         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1709         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1710         };
1711         int chan;
1712
1713         for (chan = 0; chan < 4; chan++) {
1714                 int i;
1715
1716                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1717                              (chan * 0x2000) | 0x0200);
1718                 tg3_writephy(tp, 0x16, 0x0002);
1719
1720                 for (i = 0; i < 6; i++)
1721                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1722                                      test_pat[chan][i]);
1723
1724                 tg3_writephy(tp, 0x16, 0x0202);
1725                 if (tg3_wait_macro_done(tp)) {
1726                         *resetp = 1;
1727                         return -EBUSY;
1728                 }
1729
1730                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1731                              (chan * 0x2000) | 0x0200);
1732                 tg3_writephy(tp, 0x16, 0x0082);
1733                 if (tg3_wait_macro_done(tp)) {
1734                         *resetp = 1;
1735                         return -EBUSY;
1736                 }
1737
1738                 tg3_writephy(tp, 0x16, 0x0802);
1739                 if (tg3_wait_macro_done(tp)) {
1740                         *resetp = 1;
1741                         return -EBUSY;
1742                 }
1743
1744                 for (i = 0; i < 6; i += 2) {
1745                         u32 low, high;
1746
1747                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1748                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1749                             tg3_wait_macro_done(tp)) {
1750                                 *resetp = 1;
1751                                 return -EBUSY;
1752                         }
1753                         low &= 0x7fff;
1754                         high &= 0x000f;
1755                         if (low != test_pat[chan][i] ||
1756                             high != test_pat[chan][i+1]) {
1757                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1758                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1759                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1760
1761                                 return -EBUSY;
1762                         }
1763                 }
1764         }
1765
1766         return 0;
1767 }
1768
1769 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1770 {
1771         int chan;
1772
1773         for (chan = 0; chan < 4; chan++) {
1774                 int i;
1775
1776                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1777                              (chan * 0x2000) | 0x0200);
1778                 tg3_writephy(tp, 0x16, 0x0002);
1779                 for (i = 0; i < 6; i++)
1780                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1781                 tg3_writephy(tp, 0x16, 0x0202);
1782                 if (tg3_wait_macro_done(tp))
1783                         return -EBUSY;
1784         }
1785
1786         return 0;
1787 }
1788
1789 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1790 {
1791         u32 reg32, phy9_orig;
1792         int retries, do_phy_reset, err;
1793
1794         retries = 10;
1795         do_phy_reset = 1;
1796         do {
1797                 if (do_phy_reset) {
1798                         err = tg3_bmcr_reset(tp);
1799                         if (err)
1800                                 return err;
1801                         do_phy_reset = 0;
1802                 }
1803
1804                 /* Disable transmitter and interrupt.  */
1805                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1806                         continue;
1807
1808                 reg32 |= 0x3000;
1809                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1810
1811                 /* Set full-duplex, 1000 mbps.  */
1812                 tg3_writephy(tp, MII_BMCR,
1813                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1814
1815                 /* Set to master mode.  */
1816                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1817                         continue;
1818
1819                 tg3_writephy(tp, MII_TG3_CTRL,
1820                              (MII_TG3_CTRL_AS_MASTER |
1821                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1822
1823                 /* Enable SM_DSP_CLOCK and 6dB.  */
1824                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1825
1826                 /* Block the PHY control access.  */
1827                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1828                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1829
1830                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1831                 if (!err)
1832                         break;
1833         } while (--retries);
1834
1835         err = tg3_phy_reset_chanpat(tp);
1836         if (err)
1837                 return err;
1838
1839         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1840         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1841
1842         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1843         tg3_writephy(tp, 0x16, 0x0000);
1844
1845         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1846             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1847                 /* Set Extended packet length bit for jumbo frames */
1848                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1849         }
1850         else {
1851                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1852         }
1853
1854         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1855
1856         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1857                 reg32 &= ~0x3000;
1858                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1859         } else if (!err)
1860                 err = -EBUSY;
1861
1862         return err;
1863 }
1864
1865 /* This will reset the tigon3 PHY if there is no valid
1866  * link unless the FORCE argument is non-zero.
1867  */
1868 static int tg3_phy_reset(struct tg3 *tp)
1869 {
1870         u32 cpmuctrl;
1871         u32 phy_status;
1872         int err;
1873
1874         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1875                 u32 val;
1876
1877                 val = tr32(GRC_MISC_CFG);
1878                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1879                 udelay(40);
1880         }
1881         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1882         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1883         if (err != 0)
1884                 return -EBUSY;
1885
1886         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1887                 netif_carrier_off(tp->dev);
1888                 tg3_link_report(tp);
1889         }
1890
1891         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1892             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1893             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1894                 err = tg3_phy_reset_5703_4_5(tp);
1895                 if (err)
1896                         return err;
1897                 goto out;
1898         }
1899
1900         cpmuctrl = 0;
1901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1902             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1903                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1904                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1905                         tw32(TG3_CPMU_CTRL,
1906                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1907         }
1908
1909         err = tg3_bmcr_reset(tp);
1910         if (err)
1911                 return err;
1912
1913         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1914                 u32 phy;
1915
1916                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1917                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1918
1919                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1920         }
1921
1922         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1923             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1924                 u32 val;
1925
1926                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1927                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1928                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1929                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1930                         udelay(40);
1931                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1932                 }
1933         }
1934
1935         tg3_phy_apply_otp(tp);
1936
1937         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1938                 tg3_phy_toggle_apd(tp, true);
1939         else
1940                 tg3_phy_toggle_apd(tp, false);
1941
1942 out:
1943         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1944                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1945                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1946                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1947                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1948                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1949                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1950         }
1951         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1952                 tg3_writephy(tp, 0x1c, 0x8d68);
1953                 tg3_writephy(tp, 0x1c, 0x8d68);
1954         }
1955         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1956                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1957                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1958                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1959                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1960                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1961                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1962                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1964         }
1965         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1967                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1968                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1969                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1970                         tg3_writephy(tp, MII_TG3_TEST1,
1971                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1972                 } else
1973                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1974                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1975         }
1976         /* Set Extended packet length bit (bit 14) on all chips that */
1977         /* support jumbo frames */
1978         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1979                 /* Cannot do read-modify-write on 5401 */
1980                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1981         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1982                 u32 phy_reg;
1983
1984                 /* Set bit 14 with read-modify-write to preserve other bits */
1985                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1986                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1987                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1988         }
1989
1990         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1991          * jumbo frames transmission.
1992          */
1993         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1994                 u32 phy_reg;
1995
1996                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1997                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1998                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1999         }
2000
2001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2002                 /* adjust output voltage */
2003                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2004         }
2005
2006         tg3_phy_toggle_automdix(tp, 1);
2007         tg3_phy_set_wirespeed(tp);
2008         return 0;
2009 }
2010
2011 static void tg3_frob_aux_power(struct tg3 *tp)
2012 {
2013         struct tg3 *tp_peer = tp;
2014
2015         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2016                 return;
2017
2018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2021                 struct net_device *dev_peer;
2022
2023                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2024                 /* remove_one() may have been run on the peer. */
2025                 if (!dev_peer)
2026                         tp_peer = tp;
2027                 else
2028                         tp_peer = netdev_priv(dev_peer);
2029         }
2030
2031         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2032             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2033             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2034             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2035                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2036                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2037                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2038                                     (GRC_LCLCTRL_GPIO_OE0 |
2039                                      GRC_LCLCTRL_GPIO_OE1 |
2040                                      GRC_LCLCTRL_GPIO_OE2 |
2041                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2042                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2043                                     100);
2044                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2045                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2046                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2047                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2048                                              GRC_LCLCTRL_GPIO_OE1 |
2049                                              GRC_LCLCTRL_GPIO_OE2 |
2050                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2051                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2052                                              tp->grc_local_ctrl;
2053                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2054
2055                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2056                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2057
2058                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2059                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2060                 } else {
2061                         u32 no_gpio2;
2062                         u32 grc_local_ctrl = 0;
2063
2064                         if (tp_peer != tp &&
2065                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2066                                 return;
2067
2068                         /* Workaround to prevent overdrawing Amps. */
2069                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2070                             ASIC_REV_5714) {
2071                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2072                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073                                             grc_local_ctrl, 100);
2074                         }
2075
2076                         /* On 5753 and variants, GPIO2 cannot be used. */
2077                         no_gpio2 = tp->nic_sram_data_cfg &
2078                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2079
2080                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2081                                          GRC_LCLCTRL_GPIO_OE1 |
2082                                          GRC_LCLCTRL_GPIO_OE2 |
2083                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2084                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2085                         if (no_gpio2) {
2086                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2087                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2088                         }
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                                     grc_local_ctrl, 100);
2091
2092                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2093
2094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                                     grc_local_ctrl, 100);
2096
2097                         if (!no_gpio2) {
2098                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2099                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2100                                             grc_local_ctrl, 100);
2101                         }
2102                 }
2103         } else {
2104                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2105                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2106                         if (tp_peer != tp &&
2107                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2108                                 return;
2109
2110                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2111                                     (GRC_LCLCTRL_GPIO_OE1 |
2112                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2113
2114                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115                                     GRC_LCLCTRL_GPIO_OE1, 100);
2116
2117                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2118                                     (GRC_LCLCTRL_GPIO_OE1 |
2119                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2120                 }
2121         }
2122 }
2123
2124 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2125 {
2126         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2127                 return 1;
2128         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2129                 if (speed != SPEED_10)
2130                         return 1;
2131         } else if (speed == SPEED_10)
2132                 return 1;
2133
2134         return 0;
2135 }
2136
2137 static int tg3_setup_phy(struct tg3 *, int);
2138
2139 #define RESET_KIND_SHUTDOWN     0
2140 #define RESET_KIND_INIT         1
2141 #define RESET_KIND_SUSPEND      2
2142
2143 static void tg3_write_sig_post_reset(struct tg3 *, int);
2144 static int tg3_halt_cpu(struct tg3 *, u32);
2145
2146 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2147 {
2148         u32 val;
2149
2150         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2151                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2152                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2153                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2154
2155                         sg_dig_ctrl |=
2156                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2157                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2158                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2159                 }
2160                 return;
2161         }
2162
2163         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2164                 tg3_bmcr_reset(tp);
2165                 val = tr32(GRC_MISC_CFG);
2166                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2167                 udelay(40);
2168                 return;
2169         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2170                 u32 phytest;
2171                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2172                         u32 phy;
2173
2174                         tg3_writephy(tp, MII_ADVERTISE, 0);
2175                         tg3_writephy(tp, MII_BMCR,
2176                                      BMCR_ANENABLE | BMCR_ANRESTART);
2177
2178                         tg3_writephy(tp, MII_TG3_FET_TEST,
2179                                      phytest | MII_TG3_FET_SHADOW_EN);
2180                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2181                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2182                                 tg3_writephy(tp,
2183                                              MII_TG3_FET_SHDW_AUXMODE4,
2184                                              phy);
2185                         }
2186                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2187                 }
2188                 return;
2189         } else if (do_low_power) {
2190                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2191                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2192
2193                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2194                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2195                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2196                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2197                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2198         }
2199
2200         /* The PHY should not be powered down on some chips because
2201          * of bugs.
2202          */
2203         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2204             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2205             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2206              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2207                 return;
2208
2209         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2210             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2211                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2212                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2213                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2214                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2215         }
2216
2217         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2218 }
2219
2220 /* tp->lock is held. */
2221 static int tg3_nvram_lock(struct tg3 *tp)
2222 {
2223         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2224                 int i;
2225
2226                 if (tp->nvram_lock_cnt == 0) {
2227                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2228                         for (i = 0; i < 8000; i++) {
2229                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2230                                         break;
2231                                 udelay(20);
2232                         }
2233                         if (i == 8000) {
2234                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2235                                 return -ENODEV;
2236                         }
2237                 }
2238                 tp->nvram_lock_cnt++;
2239         }
2240         return 0;
2241 }
2242
2243 /* tp->lock is held. */
2244 static void tg3_nvram_unlock(struct tg3 *tp)
2245 {
2246         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2247                 if (tp->nvram_lock_cnt > 0)
2248                         tp->nvram_lock_cnt--;
2249                 if (tp->nvram_lock_cnt == 0)
2250                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2251         }
2252 }
2253
2254 /* tp->lock is held. */
2255 static void tg3_enable_nvram_access(struct tg3 *tp)
2256 {
2257         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2258             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2259                 u32 nvaccess = tr32(NVRAM_ACCESS);
2260
2261                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2262         }
2263 }
2264
2265 /* tp->lock is held. */
2266 static void tg3_disable_nvram_access(struct tg3 *tp)
2267 {
2268         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2269             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2270                 u32 nvaccess = tr32(NVRAM_ACCESS);
2271
2272                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2273         }
2274 }
2275
2276 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2277                                         u32 offset, u32 *val)
2278 {
2279         u32 tmp;
2280         int i;
2281
2282         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2283                 return -EINVAL;
2284
2285         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2286                                         EEPROM_ADDR_DEVID_MASK |
2287                                         EEPROM_ADDR_READ);
2288         tw32(GRC_EEPROM_ADDR,
2289              tmp |
2290              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2291              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2292               EEPROM_ADDR_ADDR_MASK) |
2293              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2294
2295         for (i = 0; i < 1000; i++) {
2296                 tmp = tr32(GRC_EEPROM_ADDR);
2297
2298                 if (tmp & EEPROM_ADDR_COMPLETE)
2299                         break;
2300                 msleep(1);
2301         }
2302         if (!(tmp & EEPROM_ADDR_COMPLETE))
2303                 return -EBUSY;
2304
2305         tmp = tr32(GRC_EEPROM_DATA);
2306
2307         /*
2308          * The data will always be opposite the native endian
2309          * format.  Perform a blind byteswap to compensate.
2310          */
2311         *val = swab32(tmp);
2312
2313         return 0;
2314 }
2315
2316 #define NVRAM_CMD_TIMEOUT 10000
2317
2318 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2319 {
2320         int i;
2321
2322         tw32(NVRAM_CMD, nvram_cmd);
2323         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2324                 udelay(10);
2325                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2326                         udelay(10);
2327                         break;
2328                 }
2329         }
2330
2331         if (i == NVRAM_CMD_TIMEOUT)
2332                 return -EBUSY;
2333
2334         return 0;
2335 }
2336
2337 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2338 {
2339         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2340             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2341             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2342            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2343             (tp->nvram_jedecnum == JEDEC_ATMEL))
2344
2345                 addr = ((addr / tp->nvram_pagesize) <<
2346                         ATMEL_AT45DB0X1B_PAGE_POS) +
2347                        (addr % tp->nvram_pagesize);
2348
2349         return addr;
2350 }
2351
2352 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2353 {
2354         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2355             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2356             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2357            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2358             (tp->nvram_jedecnum == JEDEC_ATMEL))
2359
2360                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2361                         tp->nvram_pagesize) +
2362                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2363
2364         return addr;
2365 }
2366
2367 /* NOTE: Data read in from NVRAM is byteswapped according to
2368  * the byteswapping settings for all other register accesses.
2369  * tg3 devices are BE devices, so on a BE machine, the data
2370  * returned will be exactly as it is seen in NVRAM.  On a LE
2371  * machine, the 32-bit value will be byteswapped.
2372  */
2373 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2374 {
2375         int ret;
2376
2377         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2378                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2379
2380         offset = tg3_nvram_phys_addr(tp, offset);
2381
2382         if (offset > NVRAM_ADDR_MSK)
2383                 return -EINVAL;
2384
2385         ret = tg3_nvram_lock(tp);
2386         if (ret)
2387                 return ret;
2388
2389         tg3_enable_nvram_access(tp);
2390
2391         tw32(NVRAM_ADDR, offset);
2392         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2393                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2394
2395         if (ret == 0)
2396                 *val = tr32(NVRAM_RDDATA);
2397
2398         tg3_disable_nvram_access(tp);
2399
2400         tg3_nvram_unlock(tp);
2401
2402         return ret;
2403 }
2404
2405 /* Ensures NVRAM data is in bytestream format. */
2406 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2407 {
2408         u32 v;
2409         int res = tg3_nvram_read(tp, offset, &v);
2410         if (!res)
2411                 *val = cpu_to_be32(v);
2412         return res;
2413 }
2414
2415 /* tp->lock is held. */
2416 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2417 {
2418         u32 addr_high, addr_low;
2419         int i;
2420
2421         addr_high = ((tp->dev->dev_addr[0] << 8) |
2422                      tp->dev->dev_addr[1]);
2423         addr_low = ((tp->dev->dev_addr[2] << 24) |
2424                     (tp->dev->dev_addr[3] << 16) |
2425                     (tp->dev->dev_addr[4] <<  8) |
2426                     (tp->dev->dev_addr[5] <<  0));
2427         for (i = 0; i < 4; i++) {
2428                 if (i == 1 && skip_mac_1)
2429                         continue;
2430                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2431                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2432         }
2433
2434         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2435             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2436                 for (i = 0; i < 12; i++) {
2437                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2438                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2439                 }
2440         }
2441
2442         addr_high = (tp->dev->dev_addr[0] +
2443                      tp->dev->dev_addr[1] +
2444                      tp->dev->dev_addr[2] +
2445                      tp->dev->dev_addr[3] +
2446                      tp->dev->dev_addr[4] +
2447                      tp->dev->dev_addr[5]) &
2448                 TX_BACKOFF_SEED_MASK;
2449         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2450 }
2451
2452 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2453 {
2454         u32 misc_host_ctrl;
2455         bool device_should_wake, do_low_power;
2456
2457         /* Make sure register accesses (indirect or otherwise)
2458          * will function correctly.
2459          */
2460         pci_write_config_dword(tp->pdev,
2461                                TG3PCI_MISC_HOST_CTRL,
2462                                tp->misc_host_ctrl);
2463
2464         switch (state) {
2465         case PCI_D0:
2466                 pci_enable_wake(tp->pdev, state, false);
2467                 pci_set_power_state(tp->pdev, PCI_D0);
2468
2469                 /* Switch out of Vaux if it is a NIC */
2470                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2471                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2472
2473                 return 0;
2474
2475         case PCI_D1:
2476         case PCI_D2:
2477         case PCI_D3hot:
2478                 break;
2479
2480         default:
2481                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2482                         tp->dev->name, state);
2483                 return -EINVAL;
2484         }
2485
2486         /* Restore the CLKREQ setting. */
2487         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2488                 u16 lnkctl;
2489
2490                 pci_read_config_word(tp->pdev,
2491                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2492                                      &lnkctl);
2493                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2494                 pci_write_config_word(tp->pdev,
2495                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2496                                       lnkctl);
2497         }
2498
2499         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2500         tw32(TG3PCI_MISC_HOST_CTRL,
2501              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2502
2503         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2504                              device_may_wakeup(&tp->pdev->dev) &&
2505                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2506
2507         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2508                 do_low_power = false;
2509                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2510                     !tp->link_config.phy_is_low_power) {
2511                         struct phy_device *phydev;
2512                         u32 phyid, advertising;
2513
2514                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2515
2516                         tp->link_config.phy_is_low_power = 1;
2517
2518                         tp->link_config.orig_speed = phydev->speed;
2519                         tp->link_config.orig_duplex = phydev->duplex;
2520                         tp->link_config.orig_autoneg = phydev->autoneg;
2521                         tp->link_config.orig_advertising = phydev->advertising;
2522
2523                         advertising = ADVERTISED_TP |
2524                                       ADVERTISED_Pause |
2525                                       ADVERTISED_Autoneg |
2526                                       ADVERTISED_10baseT_Half;
2527
2528                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2529                             device_should_wake) {
2530                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2531                                         advertising |=
2532                                                 ADVERTISED_100baseT_Half |
2533                                                 ADVERTISED_100baseT_Full |
2534                                                 ADVERTISED_10baseT_Full;
2535                                 else
2536                                         advertising |= ADVERTISED_10baseT_Full;
2537                         }
2538
2539                         phydev->advertising = advertising;
2540
2541                         phy_start_aneg(phydev);
2542
2543                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2544                         if (phyid != TG3_PHY_ID_BCMAC131) {
2545                                 phyid &= TG3_PHY_OUI_MASK;
2546                                 if (phyid == TG3_PHY_OUI_1 ||
2547                                     phyid == TG3_PHY_OUI_2 ||
2548                                     phyid == TG3_PHY_OUI_3)
2549                                         do_low_power = true;
2550                         }
2551                 }
2552         } else {
2553                 do_low_power = true;
2554
2555                 if (tp->link_config.phy_is_low_power == 0) {
2556                         tp->link_config.phy_is_low_power = 1;
2557                         tp->link_config.orig_speed = tp->link_config.speed;
2558                         tp->link_config.orig_duplex = tp->link_config.duplex;
2559                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2560                 }
2561
2562                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2563                         tp->link_config.speed = SPEED_10;
2564                         tp->link_config.duplex = DUPLEX_HALF;
2565                         tp->link_config.autoneg = AUTONEG_ENABLE;
2566                         tg3_setup_phy(tp, 0);
2567                 }
2568         }
2569
2570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2571                 u32 val;
2572
2573                 val = tr32(GRC_VCPU_EXT_CTRL);
2574                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2575         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2576                 int i;
2577                 u32 val;
2578
2579                 for (i = 0; i < 200; i++) {
2580                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2581                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2582                                 break;
2583                         msleep(1);
2584                 }
2585         }
2586         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2587                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2588                                                      WOL_DRV_STATE_SHUTDOWN |
2589                                                      WOL_DRV_WOL |
2590                                                      WOL_SET_MAGIC_PKT);
2591
2592         if (device_should_wake) {
2593                 u32 mac_mode;
2594
2595                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2596                         if (do_low_power) {
2597                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2598                                 udelay(40);
2599                         }
2600
2601                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2602                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2603                         else
2604                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2605
2606                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2607                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2608                             ASIC_REV_5700) {
2609                                 u32 speed = (tp->tg3_flags &
2610                                              TG3_FLAG_WOL_SPEED_100MB) ?
2611                                              SPEED_100 : SPEED_10;
2612                                 if (tg3_5700_link_polarity(tp, speed))
2613                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2614                                 else
2615                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2616                         }
2617                 } else {
2618                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2619                 }
2620
2621                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2622                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2623
2624                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2625                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2626                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2627                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2628                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2629                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2630
2631                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2632                         mac_mode |= tp->mac_mode &
2633                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2634                         if (mac_mode & MAC_MODE_APE_TX_EN)
2635                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2636                 }
2637
2638                 tw32_f(MAC_MODE, mac_mode);
2639                 udelay(100);
2640
2641                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2642                 udelay(10);
2643         }
2644
2645         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2646             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2647              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2648                 u32 base_val;
2649
2650                 base_val = tp->pci_clock_ctrl;
2651                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2652                              CLOCK_CTRL_TXCLK_DISABLE);
2653
2654                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2655                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2656         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2657                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2658                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2659                 /* do nothing */
2660         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2661                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2662                 u32 newbits1, newbits2;
2663
2664                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2665                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2666                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2667                                     CLOCK_CTRL_TXCLK_DISABLE |
2668                                     CLOCK_CTRL_ALTCLK);
2669                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2670                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2671                         newbits1 = CLOCK_CTRL_625_CORE;
2672                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2673                 } else {
2674                         newbits1 = CLOCK_CTRL_ALTCLK;
2675                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2676                 }
2677
2678                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2679                             40);
2680
2681                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2682                             40);
2683
2684                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2685                         u32 newbits3;
2686
2687                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2688                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2689                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2690                                             CLOCK_CTRL_TXCLK_DISABLE |
2691                                             CLOCK_CTRL_44MHZ_CORE);
2692                         } else {
2693                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2694                         }
2695
2696                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2697                                     tp->pci_clock_ctrl | newbits3, 40);
2698                 }
2699         }
2700
2701         if (!(device_should_wake) &&
2702             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2703                 tg3_power_down_phy(tp, do_low_power);
2704
2705         tg3_frob_aux_power(tp);
2706
2707         /* Workaround for unstable PLL clock */
2708         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2709             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2710                 u32 val = tr32(0x7d00);
2711
2712                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2713                 tw32(0x7d00, val);
2714                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2715                         int err;
2716
2717                         err = tg3_nvram_lock(tp);
2718                         tg3_halt_cpu(tp, RX_CPU_BASE);
2719                         if (!err)
2720                                 tg3_nvram_unlock(tp);
2721                 }
2722         }
2723
2724         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2725
2726         if (device_should_wake)
2727                 pci_enable_wake(tp->pdev, state, true);
2728
2729         /* Finally, set the new power state. */
2730         pci_set_power_state(tp->pdev, state);
2731
2732         return 0;
2733 }
2734
2735 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2736 {
2737         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2738         case MII_TG3_AUX_STAT_10HALF:
2739                 *speed = SPEED_10;
2740                 *duplex = DUPLEX_HALF;
2741                 break;
2742
2743         case MII_TG3_AUX_STAT_10FULL:
2744                 *speed = SPEED_10;
2745                 *duplex = DUPLEX_FULL;
2746                 break;
2747
2748         case MII_TG3_AUX_STAT_100HALF:
2749                 *speed = SPEED_100;
2750                 *duplex = DUPLEX_HALF;
2751                 break;
2752
2753         case MII_TG3_AUX_STAT_100FULL:
2754                 *speed = SPEED_100;
2755                 *duplex = DUPLEX_FULL;
2756                 break;
2757
2758         case MII_TG3_AUX_STAT_1000HALF:
2759                 *speed = SPEED_1000;
2760                 *duplex = DUPLEX_HALF;
2761                 break;
2762
2763         case MII_TG3_AUX_STAT_1000FULL:
2764                 *speed = SPEED_1000;
2765                 *duplex = DUPLEX_FULL;
2766                 break;
2767
2768         default:
2769                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2770                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2771                                  SPEED_10;
2772                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2773                                   DUPLEX_HALF;
2774                         break;
2775                 }
2776                 *speed = SPEED_INVALID;
2777                 *duplex = DUPLEX_INVALID;
2778                 break;
2779         }
2780 }
2781
2782 static void tg3_phy_copper_begin(struct tg3 *tp)
2783 {
2784         u32 new_adv;
2785         int i;
2786
2787         if (tp->link_config.phy_is_low_power) {
2788                 /* Entering low power mode.  Disable gigabit and
2789                  * 100baseT advertisements.
2790                  */
2791                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2792
2793                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2794                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2795                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2796                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2797
2798                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2799         } else if (tp->link_config.speed == SPEED_INVALID) {
2800                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2801                         tp->link_config.advertising &=
2802                                 ~(ADVERTISED_1000baseT_Half |
2803                                   ADVERTISED_1000baseT_Full);
2804
2805                 new_adv = ADVERTISE_CSMA;
2806                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2807                         new_adv |= ADVERTISE_10HALF;
2808                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2809                         new_adv |= ADVERTISE_10FULL;
2810                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2811                         new_adv |= ADVERTISE_100HALF;
2812                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2813                         new_adv |= ADVERTISE_100FULL;
2814
2815                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2816
2817                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2818
2819                 if (tp->link_config.advertising &
2820                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2821                         new_adv = 0;
2822                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2823                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2824                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2825                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2826                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2827                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2828                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2829                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2830                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2831                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2832                 } else {
2833                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2834                 }
2835         } else {
2836                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2837                 new_adv |= ADVERTISE_CSMA;
2838
2839                 /* Asking for a specific link mode. */
2840                 if (tp->link_config.speed == SPEED_1000) {
2841                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2842
2843                         if (tp->link_config.duplex == DUPLEX_FULL)
2844                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2845                         else
2846                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2847                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2848                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2849                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2850                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2851                 } else {
2852                         if (tp->link_config.speed == SPEED_100) {
2853                                 if (tp->link_config.duplex == DUPLEX_FULL)
2854                                         new_adv |= ADVERTISE_100FULL;
2855                                 else
2856                                         new_adv |= ADVERTISE_100HALF;
2857                         } else {
2858                                 if (tp->link_config.duplex == DUPLEX_FULL)
2859                                         new_adv |= ADVERTISE_10FULL;
2860                                 else
2861                                         new_adv |= ADVERTISE_10HALF;
2862                         }
2863                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2864
2865                         new_adv = 0;
2866                 }
2867
2868                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2869         }
2870
2871         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2872             tp->link_config.speed != SPEED_INVALID) {
2873                 u32 bmcr, orig_bmcr;
2874
2875                 tp->link_config.active_speed = tp->link_config.speed;
2876                 tp->link_config.active_duplex = tp->link_config.duplex;
2877
2878                 bmcr = 0;
2879                 switch (tp->link_config.speed) {
2880                 default:
2881                 case SPEED_10:
2882                         break;
2883
2884                 case SPEED_100:
2885                         bmcr |= BMCR_SPEED100;
2886                         break;
2887
2888                 case SPEED_1000:
2889                         bmcr |= TG3_BMCR_SPEED1000;
2890                         break;
2891                 }
2892
2893                 if (tp->link_config.duplex == DUPLEX_FULL)
2894                         bmcr |= BMCR_FULLDPLX;
2895
2896                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2897                     (bmcr != orig_bmcr)) {
2898                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2899                         for (i = 0; i < 1500; i++) {
2900                                 u32 tmp;
2901
2902                                 udelay(10);
2903                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2904                                     tg3_readphy(tp, MII_BMSR, &tmp))
2905                                         continue;
2906                                 if (!(tmp & BMSR_LSTATUS)) {
2907                                         udelay(40);
2908                                         break;
2909                                 }
2910                         }
2911                         tg3_writephy(tp, MII_BMCR, bmcr);
2912                         udelay(40);
2913                 }
2914         } else {
2915                 tg3_writephy(tp, MII_BMCR,
2916                              BMCR_ANENABLE | BMCR_ANRESTART);
2917         }
2918 }
2919
2920 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2921 {
2922         int err;
2923
2924         /* Turn off tap power management. */
2925         /* Set Extended packet length bit */
2926         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2927
2928         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2929         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2930
2931         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2932         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2933
2934         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2935         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2936
2937         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2938         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2939
2940         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2941         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2942
2943         udelay(40);
2944
2945         return err;
2946 }
2947
2948 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2949 {
2950         u32 adv_reg, all_mask = 0;
2951
2952         if (mask & ADVERTISED_10baseT_Half)
2953                 all_mask |= ADVERTISE_10HALF;
2954         if (mask & ADVERTISED_10baseT_Full)
2955                 all_mask |= ADVERTISE_10FULL;
2956         if (mask & ADVERTISED_100baseT_Half)
2957                 all_mask |= ADVERTISE_100HALF;
2958         if (mask & ADVERTISED_100baseT_Full)
2959                 all_mask |= ADVERTISE_100FULL;
2960
2961         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2962                 return 0;
2963
2964         if ((adv_reg & all_mask) != all_mask)
2965                 return 0;
2966         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2967                 u32 tg3_ctrl;
2968
2969                 all_mask = 0;
2970                 if (mask & ADVERTISED_1000baseT_Half)
2971                         all_mask |= ADVERTISE_1000HALF;
2972                 if (mask & ADVERTISED_1000baseT_Full)
2973                         all_mask |= ADVERTISE_1000FULL;
2974
2975                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2976                         return 0;
2977
2978                 if ((tg3_ctrl & all_mask) != all_mask)
2979                         return 0;
2980         }
2981         return 1;
2982 }
2983
2984 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2985 {
2986         u32 curadv, reqadv;
2987
2988         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2989                 return 1;
2990
2991         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2992         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2993
2994         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2995                 if (curadv != reqadv)
2996                         return 0;
2997
2998                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2999                         tg3_readphy(tp, MII_LPA, rmtadv);
3000         } else {
3001                 /* Reprogram the advertisement register, even if it
3002                  * does not affect the current link.  If the link
3003                  * gets renegotiated in the future, we can save an
3004                  * additional renegotiation cycle by advertising
3005                  * it correctly in the first place.
3006                  */
3007                 if (curadv != reqadv) {
3008                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3009                                      ADVERTISE_PAUSE_ASYM);
3010                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3011                 }
3012         }
3013
3014         return 1;
3015 }
3016
3017 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3018 {
3019         int current_link_up;
3020         u32 bmsr, dummy;
3021         u32 lcl_adv, rmt_adv;
3022         u16 current_speed;
3023         u8 current_duplex;
3024         int i, err;
3025
3026         tw32(MAC_EVENT, 0);
3027
3028         tw32_f(MAC_STATUS,
3029              (MAC_STATUS_SYNC_CHANGED |
3030               MAC_STATUS_CFG_CHANGED |
3031               MAC_STATUS_MI_COMPLETION |
3032               MAC_STATUS_LNKSTATE_CHANGED));
3033         udelay(40);
3034
3035         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3036                 tw32_f(MAC_MI_MODE,
3037                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3038                 udelay(80);
3039         }
3040
3041         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3042
3043         /* Some third-party PHYs need to be reset on link going
3044          * down.
3045          */
3046         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3047              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3048              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3049             netif_carrier_ok(tp->dev)) {
3050                 tg3_readphy(tp, MII_BMSR, &bmsr);
3051                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3052                     !(bmsr & BMSR_LSTATUS))
3053                         force_reset = 1;
3054         }
3055         if (force_reset)
3056                 tg3_phy_reset(tp);
3057
3058         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3059                 tg3_readphy(tp, MII_BMSR, &bmsr);
3060                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3061                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3062                         bmsr = 0;
3063
3064                 if (!(bmsr & BMSR_LSTATUS)) {
3065                         err = tg3_init_5401phy_dsp(tp);
3066                         if (err)
3067                                 return err;
3068
3069                         tg3_readphy(tp, MII_BMSR, &bmsr);
3070                         for (i = 0; i < 1000; i++) {
3071                                 udelay(10);
3072                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3073                                     (bmsr & BMSR_LSTATUS)) {
3074                                         udelay(40);
3075                                         break;
3076                                 }
3077                         }
3078
3079                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3080                             !(bmsr & BMSR_LSTATUS) &&
3081                             tp->link_config.active_speed == SPEED_1000) {
3082                                 err = tg3_phy_reset(tp);
3083                                 if (!err)
3084                                         err = tg3_init_5401phy_dsp(tp);
3085                                 if (err)
3086                                         return err;
3087                         }
3088                 }
3089         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3090                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3091                 /* 5701 {A0,B0} CRC bug workaround */
3092                 tg3_writephy(tp, 0x15, 0x0a75);
3093                 tg3_writephy(tp, 0x1c, 0x8c68);
3094                 tg3_writephy(tp, 0x1c, 0x8d68);
3095                 tg3_writephy(tp, 0x1c, 0x8c68);
3096         }
3097
3098         /* Clear pending interrupts... */
3099         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3100         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3101
3102         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3103                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3104         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3105                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3106
3107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3109                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3110                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3111                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3112                 else
3113                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3114         }
3115
3116         current_link_up = 0;
3117         current_speed = SPEED_INVALID;
3118         current_duplex = DUPLEX_INVALID;
3119
3120         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3121                 u32 val;
3122
3123                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3124                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3125                 if (!(val & (1 << 10))) {
3126                         val |= (1 << 10);
3127                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3128                         goto relink;
3129                 }
3130         }
3131
3132         bmsr = 0;
3133         for (i = 0; i < 100; i++) {
3134                 tg3_readphy(tp, MII_BMSR, &bmsr);
3135                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3136                     (bmsr & BMSR_LSTATUS))
3137                         break;
3138                 udelay(40);
3139         }
3140
3141         if (bmsr & BMSR_LSTATUS) {
3142                 u32 aux_stat, bmcr;
3143
3144                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3145                 for (i = 0; i < 2000; i++) {
3146                         udelay(10);
3147                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3148                             aux_stat)
3149                                 break;
3150                 }
3151
3152                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3153                                              &current_speed,
3154                                              &current_duplex);
3155
3156                 bmcr = 0;
3157                 for (i = 0; i < 200; i++) {
3158                         tg3_readphy(tp, MII_BMCR, &bmcr);
3159                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3160                                 continue;
3161                         if (bmcr && bmcr != 0x7fff)
3162                                 break;
3163                         udelay(10);
3164                 }
3165
3166                 lcl_adv = 0;
3167                 rmt_adv = 0;
3168
3169                 tp->link_config.active_speed = current_speed;
3170                 tp->link_config.active_duplex = current_duplex;
3171
3172                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3173                         if ((bmcr & BMCR_ANENABLE) &&
3174                             tg3_copper_is_advertising_all(tp,
3175                                                 tp->link_config.advertising)) {
3176                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3177                                                                   &rmt_adv))
3178                                         current_link_up = 1;
3179                         }
3180                 } else {
3181                         if (!(bmcr & BMCR_ANENABLE) &&
3182                             tp->link_config.speed == current_speed &&
3183                             tp->link_config.duplex == current_duplex &&
3184                             tp->link_config.flowctrl ==
3185                             tp->link_config.active_flowctrl) {
3186                                 current_link_up = 1;
3187                         }
3188                 }
3189
3190                 if (current_link_up == 1 &&
3191                     tp->link_config.active_duplex == DUPLEX_FULL)
3192                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3193         }
3194
3195 relink:
3196         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3197                 u32 tmp;
3198
3199                 tg3_phy_copper_begin(tp);
3200
3201                 tg3_readphy(tp, MII_BMSR, &tmp);
3202                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3203                     (tmp & BMSR_LSTATUS))
3204                         current_link_up = 1;
3205         }
3206
3207         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3208         if (current_link_up == 1) {
3209                 if (tp->link_config.active_speed == SPEED_100 ||
3210                     tp->link_config.active_speed == SPEED_10)
3211                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3212                 else
3213                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3214         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3215                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3216         else
3217                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3218
3219         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3220         if (tp->link_config.active_duplex == DUPLEX_HALF)
3221                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3222
3223         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3224                 if (current_link_up == 1 &&
3225                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3226                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3227                 else
3228                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3229         }
3230
3231         /* ??? Without this setting Netgear GA302T PHY does not
3232          * ??? send/receive packets...
3233          */
3234         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3235             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3236                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3237                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3238                 udelay(80);
3239         }
3240
3241         tw32_f(MAC_MODE, tp->mac_mode);
3242         udelay(40);
3243
3244         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3245                 /* Polled via timer. */
3246                 tw32_f(MAC_EVENT, 0);
3247         } else {
3248                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3249         }
3250         udelay(40);
3251
3252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3253             current_link_up == 1 &&
3254             tp->link_config.active_speed == SPEED_1000 &&
3255             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3256              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3257                 udelay(120);
3258                 tw32_f(MAC_STATUS,
3259                      (MAC_STATUS_SYNC_CHANGED |
3260                       MAC_STATUS_CFG_CHANGED));
3261                 udelay(40);
3262                 tg3_write_mem(tp,
3263                               NIC_SRAM_FIRMWARE_MBOX,
3264                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3265         }
3266
3267         /* Prevent send BD corruption. */
3268         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3269                 u16 oldlnkctl, newlnkctl;
3270
3271                 pci_read_config_word(tp->pdev,
3272                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3273                                      &oldlnkctl);
3274                 if (tp->link_config.active_speed == SPEED_100 ||
3275                     tp->link_config.active_speed == SPEED_10)
3276                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3277                 else
3278                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3279                 if (newlnkctl != oldlnkctl)
3280                         pci_write_config_word(tp->pdev,
3281                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3282                                               newlnkctl);
3283         }
3284
3285         if (current_link_up != netif_carrier_ok(tp->dev)) {
3286                 if (current_link_up)
3287                         netif_carrier_on(tp->dev);
3288                 else
3289                         netif_carrier_off(tp->dev);
3290                 tg3_link_report(tp);
3291         }
3292
3293         return 0;
3294 }
3295
3296 struct tg3_fiber_aneginfo {
3297         int state;
3298 #define ANEG_STATE_UNKNOWN              0
3299 #define ANEG_STATE_AN_ENABLE            1
3300 #define ANEG_STATE_RESTART_INIT         2
3301 #define ANEG_STATE_RESTART              3
3302 #define ANEG_STATE_DISABLE_LINK_OK      4
3303 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3304 #define ANEG_STATE_ABILITY_DETECT       6
3305 #define ANEG_STATE_ACK_DETECT_INIT      7
3306 #define ANEG_STATE_ACK_DETECT           8
3307 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3308 #define ANEG_STATE_COMPLETE_ACK         10
3309 #define ANEG_STATE_IDLE_DETECT_INIT     11
3310 #define ANEG_STATE_IDLE_DETECT          12
3311 #define ANEG_STATE_LINK_OK              13
3312 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3313 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3314
3315         u32 flags;
3316 #define MR_AN_ENABLE            0x00000001
3317 #define MR_RESTART_AN           0x00000002
3318 #define MR_AN_COMPLETE          0x00000004
3319 #define MR_PAGE_RX              0x00000008
3320 #define MR_NP_LOADED            0x00000010
3321 #define MR_TOGGLE_TX            0x00000020
3322 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3323 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3324 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3325 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3326 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3327 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3328 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3329 #define MR_TOGGLE_RX            0x00002000
3330 #define MR_NP_RX                0x00004000
3331
3332 #define MR_LINK_OK              0x80000000
3333
3334         unsigned long link_time, cur_time;
3335
3336         u32 ability_match_cfg;
3337         int ability_match_count;
3338
3339         char ability_match, idle_match, ack_match;
3340
3341         u32 txconfig, rxconfig;
3342 #define ANEG_CFG_NP             0x00000080
3343 #define ANEG_CFG_ACK            0x00000040
3344 #define ANEG_CFG_RF2            0x00000020
3345 #define ANEG_CFG_RF1            0x00000010
3346 #define ANEG_CFG_PS2            0x00000001
3347 #define ANEG_CFG_PS1            0x00008000
3348 #define ANEG_CFG_HD             0x00004000
3349 #define ANEG_CFG_FD             0x00002000
3350 #define ANEG_CFG_INVAL          0x00001f06
3351
3352 };
3353 #define ANEG_OK         0
3354 #define ANEG_DONE       1
3355 #define ANEG_TIMER_ENAB 2
3356 #define ANEG_FAILED     -1
3357
3358 #define ANEG_STATE_SETTLE_TIME  10000
3359
3360 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3361                                    struct tg3_fiber_aneginfo *ap)
3362 {
3363         u16 flowctrl;
3364         unsigned long delta;
3365         u32 rx_cfg_reg;
3366         int ret;
3367
3368         if (ap->state == ANEG_STATE_UNKNOWN) {
3369                 ap->rxconfig = 0;
3370                 ap->link_time = 0;
3371                 ap->cur_time = 0;
3372                 ap->ability_match_cfg = 0;
3373                 ap->ability_match_count = 0;
3374                 ap->ability_match = 0;
3375                 ap->idle_match = 0;
3376                 ap->ack_match = 0;
3377         }
3378         ap->cur_time++;
3379
3380         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3381                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3382
3383                 if (rx_cfg_reg != ap->ability_match_cfg) {
3384                         ap->ability_match_cfg = rx_cfg_reg;
3385                         ap->ability_match = 0;
3386                         ap->ability_match_count = 0;
3387                 } else {
3388                         if (++ap->ability_match_count > 1) {
3389                                 ap->ability_match = 1;
3390                                 ap->ability_match_cfg = rx_cfg_reg;
3391                         }
3392                 }
3393                 if (rx_cfg_reg & ANEG_CFG_ACK)
3394                         ap->ack_match = 1;
3395                 else
3396                         ap->ack_match = 0;
3397
3398                 ap->idle_match = 0;
3399         } else {
3400                 ap->idle_match = 1;
3401                 ap->ability_match_cfg = 0;
3402                 ap->ability_match_count = 0;
3403                 ap->ability_match = 0;
3404                 ap->ack_match = 0;
3405
3406                 rx_cfg_reg = 0;
3407         }
3408
3409         ap->rxconfig = rx_cfg_reg;
3410         ret = ANEG_OK;
3411
3412         switch(ap->state) {
3413         case ANEG_STATE_UNKNOWN:
3414                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3415                         ap->state = ANEG_STATE_AN_ENABLE;
3416
3417                 /* fallthru */
3418         case ANEG_STATE_AN_ENABLE:
3419                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3420                 if (ap->flags & MR_AN_ENABLE) {
3421                         ap->link_time = 0;
3422                         ap->cur_time = 0;
3423                         ap->ability_match_cfg = 0;
3424                         ap->ability_match_count = 0;
3425                         ap->ability_match = 0;
3426                         ap->idle_match = 0;
3427                         ap->ack_match = 0;
3428
3429                         ap->state = ANEG_STATE_RESTART_INIT;
3430                 } else {
3431                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3432                 }
3433                 break;
3434
3435         case ANEG_STATE_RESTART_INIT:
3436                 ap->link_time = ap->cur_time;
3437                 ap->flags &= ~(MR_NP_LOADED);
3438                 ap->txconfig = 0;
3439                 tw32(MAC_TX_AUTO_NEG, 0);
3440                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3441                 tw32_f(MAC_MODE, tp->mac_mode);
3442                 udelay(40);
3443
3444                 ret = ANEG_TIMER_ENAB;
3445                 ap->state = ANEG_STATE_RESTART;
3446
3447                 /* fallthru */
3448         case ANEG_STATE_RESTART:
3449                 delta = ap->cur_time - ap->link_time;
3450                 if (delta > ANEG_STATE_SETTLE_TIME) {
3451                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3452                 } else {
3453                         ret = ANEG_TIMER_ENAB;
3454                 }
3455                 break;
3456
3457         case ANEG_STATE_DISABLE_LINK_OK:
3458                 ret = ANEG_DONE;
3459                 break;
3460
3461         case ANEG_STATE_ABILITY_DETECT_INIT:
3462                 ap->flags &= ~(MR_TOGGLE_TX);
3463                 ap->txconfig = ANEG_CFG_FD;
3464                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3465                 if (flowctrl & ADVERTISE_1000XPAUSE)
3466                         ap->txconfig |= ANEG_CFG_PS1;
3467                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3468                         ap->txconfig |= ANEG_CFG_PS2;
3469                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3470                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3471                 tw32_f(MAC_MODE, tp->mac_mode);
3472                 udelay(40);
3473
3474                 ap->state = ANEG_STATE_ABILITY_DETECT;
3475                 break;
3476
3477         case ANEG_STATE_ABILITY_DETECT:
3478                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3479                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3480                 }
3481                 break;
3482
3483         case ANEG_STATE_ACK_DETECT_INIT:
3484                 ap->txconfig |= ANEG_CFG_ACK;
3485                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487                 tw32_f(MAC_MODE, tp->mac_mode);
3488                 udelay(40);
3489
3490                 ap->state = ANEG_STATE_ACK_DETECT;
3491
3492                 /* fallthru */
3493         case ANEG_STATE_ACK_DETECT:
3494                 if (ap->ack_match != 0) {
3495                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3496                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3497                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3498                         } else {
3499                                 ap->state = ANEG_STATE_AN_ENABLE;
3500                         }
3501                 } else if (ap->ability_match != 0 &&
3502                            ap->rxconfig == 0) {
3503                         ap->state = ANEG_STATE_AN_ENABLE;
3504                 }
3505                 break;
3506
3507         case ANEG_STATE_COMPLETE_ACK_INIT:
3508                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3509                         ret = ANEG_FAILED;
3510                         break;
3511                 }
3512                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3513                                MR_LP_ADV_HALF_DUPLEX |
3514                                MR_LP_ADV_SYM_PAUSE |
3515                                MR_LP_ADV_ASYM_PAUSE |
3516                                MR_LP_ADV_REMOTE_FAULT1 |
3517                                MR_LP_ADV_REMOTE_FAULT2 |
3518                                MR_LP_ADV_NEXT_PAGE |
3519                                MR_TOGGLE_RX |
3520                                MR_NP_RX);
3521                 if (ap->rxconfig & ANEG_CFG_FD)
3522                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3523                 if (ap->rxconfig & ANEG_CFG_HD)
3524                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3525                 if (ap->rxconfig & ANEG_CFG_PS1)
3526                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3527                 if (ap->rxconfig & ANEG_CFG_PS2)
3528                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3529                 if (ap->rxconfig & ANEG_CFG_RF1)
3530                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3531                 if (ap->rxconfig & ANEG_CFG_RF2)
3532                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3533                 if (ap->rxconfig & ANEG_CFG_NP)
3534                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3535
3536                 ap->link_time = ap->cur_time;
3537
3538                 ap->flags ^= (MR_TOGGLE_TX);
3539                 if (ap->rxconfig & 0x0008)
3540                         ap->flags |= MR_TOGGLE_RX;
3541                 if (ap->rxconfig & ANEG_CFG_NP)
3542                         ap->flags |= MR_NP_RX;
3543                 ap->flags |= MR_PAGE_RX;
3544
3545                 ap->state = ANEG_STATE_COMPLETE_ACK;
3546                 ret = ANEG_TIMER_ENAB;
3547                 break;
3548
3549         case ANEG_STATE_COMPLETE_ACK:
3550                 if (ap->ability_match != 0 &&
3551                     ap->rxconfig == 0) {
3552                         ap->state = ANEG_STATE_AN_ENABLE;
3553                         break;
3554                 }
3555                 delta = ap->cur_time - ap->link_time;
3556                 if (delta > ANEG_STATE_SETTLE_TIME) {
3557                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3558                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3559                         } else {
3560                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3561                                     !(ap->flags & MR_NP_RX)) {
3562                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3563                                 } else {
3564                                         ret = ANEG_FAILED;
3565                                 }
3566                         }
3567                 }
3568                 break;
3569
3570         case ANEG_STATE_IDLE_DETECT_INIT:
3571                 ap->link_time = ap->cur_time;
3572                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3573                 tw32_f(MAC_MODE, tp->mac_mode);
3574                 udelay(40);
3575
3576                 ap->state = ANEG_STATE_IDLE_DETECT;
3577                 ret = ANEG_TIMER_ENAB;
3578                 break;
3579
3580         case ANEG_STATE_IDLE_DETECT:
3581                 if (ap->ability_match != 0 &&
3582                     ap->rxconfig == 0) {
3583                         ap->state = ANEG_STATE_AN_ENABLE;
3584                         break;
3585                 }
3586                 delta = ap->cur_time - ap->link_time;
3587                 if (delta > ANEG_STATE_SETTLE_TIME) {
3588                         /* XXX another gem from the Broadcom driver :( */
3589                         ap->state = ANEG_STATE_LINK_OK;
3590                 }
3591                 break;
3592
3593         case ANEG_STATE_LINK_OK:
3594                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3595                 ret = ANEG_DONE;
3596                 break;
3597
3598         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3599                 /* ??? unimplemented */
3600                 break;
3601
3602         case ANEG_STATE_NEXT_PAGE_WAIT:
3603                 /* ??? unimplemented */
3604                 break;
3605
3606         default:
3607                 ret = ANEG_FAILED;
3608                 break;
3609         }
3610
3611         return ret;
3612 }
3613
3614 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3615 {
3616         int res = 0;
3617         struct tg3_fiber_aneginfo aninfo;
3618         int status = ANEG_FAILED;
3619         unsigned int tick;
3620         u32 tmp;
3621
3622         tw32_f(MAC_TX_AUTO_NEG, 0);
3623
3624         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3625         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3626         udelay(40);
3627
3628         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3629         udelay(40);
3630
3631         memset(&aninfo, 0, sizeof(aninfo));
3632         aninfo.flags |= MR_AN_ENABLE;
3633         aninfo.state = ANEG_STATE_UNKNOWN;
3634         aninfo.cur_time = 0;
3635         tick = 0;
3636         while (++tick < 195000) {
3637                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3638                 if (status == ANEG_DONE || status == ANEG_FAILED)
3639                         break;
3640
3641                 udelay(1);
3642         }
3643
3644         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3645         tw32_f(MAC_MODE, tp->mac_mode);
3646         udelay(40);
3647
3648         *txflags = aninfo.txconfig;
3649         *rxflags = aninfo.flags;
3650
3651         if (status == ANEG_DONE &&
3652             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3653                              MR_LP_ADV_FULL_DUPLEX)))
3654                 res = 1;
3655
3656         return res;
3657 }
3658
3659 static void tg3_init_bcm8002(struct tg3 *tp)
3660 {
3661         u32 mac_status = tr32(MAC_STATUS);
3662         int i;
3663
3664         /* Reset when initting first time or we have a link. */
3665         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3666             !(mac_status & MAC_STATUS_PCS_SYNCED))
3667                 return;
3668
3669         /* Set PLL lock range. */
3670         tg3_writephy(tp, 0x16, 0x8007);
3671
3672         /* SW reset */
3673         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3674
3675         /* Wait for reset to complete. */
3676         /* XXX schedule_timeout() ... */
3677         for (i = 0; i < 500; i++)
3678                 udelay(10);
3679
3680         /* Config mode; select PMA/Ch 1 regs. */
3681         tg3_writephy(tp, 0x10, 0x8411);
3682
3683         /* Enable auto-lock and comdet, select txclk for tx. */
3684         tg3_writephy(tp, 0x11, 0x0a10);
3685
3686         tg3_writephy(tp, 0x18, 0x00a0);
3687         tg3_writephy(tp, 0x16, 0x41ff);
3688
3689         /* Assert and deassert POR. */
3690         tg3_writephy(tp, 0x13, 0x0400);
3691         udelay(40);
3692         tg3_writephy(tp, 0x13, 0x0000);
3693
3694         tg3_writephy(tp, 0x11, 0x0a50);
3695         udelay(40);
3696         tg3_writephy(tp, 0x11, 0x0a10);
3697
3698         /* Wait for signal to stabilize */
3699         /* XXX schedule_timeout() ... */
3700         for (i = 0; i < 15000; i++)
3701                 udelay(10);
3702
3703         /* Deselect the channel register so we can read the PHYID
3704          * later.
3705          */
3706         tg3_writephy(tp, 0x10, 0x8011);
3707 }
3708
3709 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3710 {
3711         u16 flowctrl;
3712         u32 sg_dig_ctrl, sg_dig_status;
3713         u32 serdes_cfg, expected_sg_dig_ctrl;
3714         int workaround, port_a;
3715         int current_link_up;
3716
3717         serdes_cfg = 0;
3718         expected_sg_dig_ctrl = 0;
3719         workaround = 0;
3720         port_a = 1;
3721         current_link_up = 0;
3722
3723         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3724             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3725                 workaround = 1;
3726                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3727                         port_a = 0;
3728
3729                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3730                 /* preserve bits 20-23 for voltage regulator */
3731                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3732         }
3733
3734         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3735
3736         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3737                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3738                         if (workaround) {
3739                                 u32 val = serdes_cfg;
3740
3741                                 if (port_a)
3742                                         val |= 0xc010000;
3743                                 else
3744                                         val |= 0x4010000;
3745                                 tw32_f(MAC_SERDES_CFG, val);
3746                         }
3747
3748                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3749                 }
3750                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3751                         tg3_setup_flow_control(tp, 0, 0);
3752                         current_link_up = 1;
3753                 }
3754                 goto out;
3755         }
3756
3757         /* Want auto-negotiation.  */
3758         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3759
3760         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3761         if (flowctrl & ADVERTISE_1000XPAUSE)
3762                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3763         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3764                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3765
3766         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3767                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3768                     tp->serdes_counter &&
3769                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3770                                     MAC_STATUS_RCVD_CFG)) ==
3771                      MAC_STATUS_PCS_SYNCED)) {
3772                         tp->serdes_counter--;
3773                         current_link_up = 1;
3774                         goto out;
3775                 }
3776 restart_autoneg:
3777                 if (workaround)
3778                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3779                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3780                 udelay(5);
3781                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3782
3783                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3784                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3785         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3786                                  MAC_STATUS_SIGNAL_DET)) {
3787                 sg_dig_status = tr32(SG_DIG_STATUS);
3788                 mac_status = tr32(MAC_STATUS);
3789
3790                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3791                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3792                         u32 local_adv = 0, remote_adv = 0;
3793
3794                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3795                                 local_adv |= ADVERTISE_1000XPAUSE;
3796                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3797                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3798
3799                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3800                                 remote_adv |= LPA_1000XPAUSE;
3801                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3802                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3803
3804                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3805                         current_link_up = 1;
3806                         tp->serdes_counter = 0;
3807                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3808                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3809                         if (tp->serdes_counter)
3810                                 tp->serdes_counter--;
3811                         else {
3812                                 if (workaround) {
3813                                         u32 val = serdes_cfg;
3814
3815                                         if (port_a)
3816                                                 val |= 0xc010000;
3817                                         else
3818                                                 val |= 0x4010000;
3819
3820                                         tw32_f(MAC_SERDES_CFG, val);
3821                                 }
3822
3823                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3824                                 udelay(40);
3825
3826                                 /* Link parallel detection - link is up */
3827                                 /* only if we have PCS_SYNC and not */
3828                                 /* receiving config code words */
3829                                 mac_status = tr32(MAC_STATUS);
3830                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3831                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3832                                         tg3_setup_flow_control(tp, 0, 0);
3833                                         current_link_up = 1;
3834                                         tp->tg3_flags2 |=
3835                                                 TG3_FLG2_PARALLEL_DETECT;
3836                                         tp->serdes_counter =
3837                                                 SERDES_PARALLEL_DET_TIMEOUT;
3838                                 } else
3839                                         goto restart_autoneg;
3840                         }
3841                 }
3842         } else {
3843                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3844                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3845         }
3846
3847 out:
3848         return current_link_up;
3849 }
3850
3851 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3852 {
3853         int current_link_up = 0;
3854
3855         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3856                 goto out;
3857
3858         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3859                 u32 txflags, rxflags;
3860                 int i;
3861
3862                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3863                         u32 local_adv = 0, remote_adv = 0;
3864
3865                         if (txflags & ANEG_CFG_PS1)
3866                                 local_adv |= ADVERTISE_1000XPAUSE;
3867                         if (txflags & ANEG_CFG_PS2)
3868                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3869
3870                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3871                                 remote_adv |= LPA_1000XPAUSE;
3872                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3873                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3874
3875                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3876
3877                         current_link_up = 1;
3878                 }
3879                 for (i = 0; i < 30; i++) {
3880                         udelay(20);
3881                         tw32_f(MAC_STATUS,
3882                                (MAC_STATUS_SYNC_CHANGED |
3883                                 MAC_STATUS_CFG_CHANGED));
3884                         udelay(40);
3885                         if ((tr32(MAC_STATUS) &
3886                              (MAC_STATUS_SYNC_CHANGED |
3887                               MAC_STATUS_CFG_CHANGED)) == 0)
3888                                 break;
3889                 }
3890
3891                 mac_status = tr32(MAC_STATUS);
3892                 if (current_link_up == 0 &&
3893                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3894                     !(mac_status & MAC_STATUS_RCVD_CFG))
3895                         current_link_up = 1;
3896         } else {
3897                 tg3_setup_flow_control(tp, 0, 0);
3898
3899                 /* Forcing 1000FD link up. */
3900                 current_link_up = 1;
3901
3902                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3903                 udelay(40);
3904
3905                 tw32_f(MAC_MODE, tp->mac_mode);
3906                 udelay(40);
3907         }
3908
3909 out:
3910         return current_link_up;
3911 }
3912
3913 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3914 {
3915         u32 orig_pause_cfg;
3916         u16 orig_active_speed;
3917         u8 orig_active_duplex;
3918         u32 mac_status;
3919         int current_link_up;
3920         int i;
3921
3922         orig_pause_cfg = tp->link_config.active_flowctrl;
3923         orig_active_speed = tp->link_config.active_speed;
3924         orig_active_duplex = tp->link_config.active_duplex;
3925
3926         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3927             netif_carrier_ok(tp->dev) &&
3928             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3929                 mac_status = tr32(MAC_STATUS);
3930                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3931                                MAC_STATUS_SIGNAL_DET |
3932                                MAC_STATUS_CFG_CHANGED |
3933                                MAC_STATUS_RCVD_CFG);
3934                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3935                                    MAC_STATUS_SIGNAL_DET)) {
3936                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3937                                             MAC_STATUS_CFG_CHANGED));
3938                         return 0;
3939                 }
3940         }
3941
3942         tw32_f(MAC_TX_AUTO_NEG, 0);
3943
3944         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3945         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3946         tw32_f(MAC_MODE, tp->mac_mode);
3947         udelay(40);
3948
3949         if (tp->phy_id == PHY_ID_BCM8002)
3950                 tg3_init_bcm8002(tp);
3951
3952         /* Enable link change event even when serdes polling.  */
3953         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3954         udelay(40);
3955
3956         current_link_up = 0;
3957         mac_status = tr32(MAC_STATUS);
3958
3959         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3960                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3961         else
3962                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3963
3964         tp->napi[0].hw_status->status =
3965                 (SD_STATUS_UPDATED |
3966                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3967
3968         for (i = 0; i < 100; i++) {
3969                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3970                                     MAC_STATUS_CFG_CHANGED));
3971                 udelay(5);
3972                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3973                                          MAC_STATUS_CFG_CHANGED |
3974                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3975                         break;
3976         }
3977
3978         mac_status = tr32(MAC_STATUS);
3979         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3980                 current_link_up = 0;
3981                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3982                     tp->serdes_counter == 0) {
3983                         tw32_f(MAC_MODE, (tp->mac_mode |
3984                                           MAC_MODE_SEND_CONFIGS));
3985                         udelay(1);
3986                         tw32_f(MAC_MODE, tp->mac_mode);
3987                 }
3988         }
3989
3990         if (current_link_up == 1) {
3991                 tp->link_config.active_speed = SPEED_1000;
3992                 tp->link_config.active_duplex = DUPLEX_FULL;
3993                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3994                                     LED_CTRL_LNKLED_OVERRIDE |
3995                                     LED_CTRL_1000MBPS_ON));
3996         } else {
3997                 tp->link_config.active_speed = SPEED_INVALID;
3998                 tp->link_config.active_duplex = DUPLEX_INVALID;
3999                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4000                                     LED_CTRL_LNKLED_OVERRIDE |
4001                                     LED_CTRL_TRAFFIC_OVERRIDE));
4002         }
4003
4004         if (current_link_up != netif_carrier_ok(tp->dev)) {
4005                 if (current_link_up)
4006                         netif_carrier_on(tp->dev);
4007                 else
4008                         netif_carrier_off(tp->dev);
4009                 tg3_link_report(tp);
4010         } else {
4011                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4012                 if (orig_pause_cfg != now_pause_cfg ||
4013                     orig_active_speed != tp->link_config.active_speed ||
4014                     orig_active_duplex != tp->link_config.active_duplex)
4015                         tg3_link_report(tp);
4016         }
4017
4018         return 0;
4019 }
4020
4021 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4022 {
4023         int current_link_up, err = 0;
4024         u32 bmsr, bmcr;
4025         u16 current_speed;
4026         u8 current_duplex;
4027         u32 local_adv, remote_adv;
4028
4029         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4030         tw32_f(MAC_MODE, tp->mac_mode);
4031         udelay(40);
4032
4033         tw32(MAC_EVENT, 0);
4034
4035         tw32_f(MAC_STATUS,
4036              (MAC_STATUS_SYNC_CHANGED |
4037               MAC_STATUS_CFG_CHANGED |
4038               MAC_STATUS_MI_COMPLETION |
4039               MAC_STATUS_LNKSTATE_CHANGED));
4040         udelay(40);
4041
4042         if (force_reset)
4043                 tg3_phy_reset(tp);
4044
4045         current_link_up = 0;
4046         current_speed = SPEED_INVALID;
4047         current_duplex = DUPLEX_INVALID;
4048
4049         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4050         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4052                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4053                         bmsr |= BMSR_LSTATUS;
4054                 else
4055                         bmsr &= ~BMSR_LSTATUS;
4056         }
4057
4058         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4059
4060         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4061             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4062                 /* do nothing, just check for link up at the end */
4063         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4064                 u32 adv, new_adv;
4065
4066                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4067                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4068                                   ADVERTISE_1000XPAUSE |
4069                                   ADVERTISE_1000XPSE_ASYM |
4070                                   ADVERTISE_SLCT);
4071
4072                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4073
4074                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4075                         new_adv |= ADVERTISE_1000XHALF;
4076                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4077                         new_adv |= ADVERTISE_1000XFULL;
4078
4079                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4080                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4081                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4082                         tg3_writephy(tp, MII_BMCR, bmcr);
4083
4084                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4085                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4086                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4087
4088                         return err;
4089                 }
4090         } else {
4091                 u32 new_bmcr;
4092
4093                 bmcr &= ~BMCR_SPEED1000;
4094                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4095
4096                 if (tp->link_config.duplex == DUPLEX_FULL)
4097                         new_bmcr |= BMCR_FULLDPLX;
4098
4099                 if (new_bmcr != bmcr) {
4100                         /* BMCR_SPEED1000 is a reserved bit that needs
4101                          * to be set on write.
4102                          */
4103                         new_bmcr |= BMCR_SPEED1000;
4104
4105                         /* Force a linkdown */
4106                         if (netif_carrier_ok(tp->dev)) {
4107                                 u32 adv;
4108
4109                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4110                                 adv &= ~(ADVERTISE_1000XFULL |
4111                                          ADVERTISE_1000XHALF |
4112                                          ADVERTISE_SLCT);
4113                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4114                                 tg3_writephy(tp, MII_BMCR, bmcr |
4115                                                            BMCR_ANRESTART |
4116                                                            BMCR_ANENABLE);
4117                                 udelay(10);
4118                                 netif_carrier_off(tp->dev);
4119                         }
4120                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4121                         bmcr = new_bmcr;
4122                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4123                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4124                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4125                             ASIC_REV_5714) {
4126                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4127                                         bmsr |= BMSR_LSTATUS;
4128                                 else
4129                                         bmsr &= ~BMSR_LSTATUS;
4130                         }
4131                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4132                 }
4133         }
4134
4135         if (bmsr & BMSR_LSTATUS) {
4136                 current_speed = SPEED_1000;
4137                 current_link_up = 1;
4138                 if (bmcr & BMCR_FULLDPLX)
4139                         current_duplex = DUPLEX_FULL;
4140                 else
4141                         current_duplex = DUPLEX_HALF;
4142
4143                 local_adv = 0;
4144                 remote_adv = 0;
4145
4146                 if (bmcr & BMCR_ANENABLE) {
4147                         u32 common;
4148
4149                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4150                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4151                         common = local_adv & remote_adv;
4152                         if (common & (ADVERTISE_1000XHALF |
4153                                       ADVERTISE_1000XFULL)) {
4154                                 if (common & ADVERTISE_1000XFULL)
4155                                         current_duplex = DUPLEX_FULL;
4156                                 else
4157                                         current_duplex = DUPLEX_HALF;
4158                         }
4159                         else
4160                                 current_link_up = 0;
4161                 }
4162         }
4163
4164         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4165                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4166
4167         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4168         if (tp->link_config.active_duplex == DUPLEX_HALF)
4169                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4170
4171         tw32_f(MAC_MODE, tp->mac_mode);
4172         udelay(40);
4173
4174         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4175
4176         tp->link_config.active_speed = current_speed;
4177         tp->link_config.active_duplex = current_duplex;
4178
4179         if (current_link_up != netif_carrier_ok(tp->dev)) {
4180                 if (current_link_up)
4181                         netif_carrier_on(tp->dev);
4182                 else {
4183                         netif_carrier_off(tp->dev);
4184                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4185                 }
4186                 tg3_link_report(tp);
4187         }
4188         return err;
4189 }
4190
4191 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4192 {
4193         if (tp->serdes_counter) {
4194                 /* Give autoneg time to complete. */
4195                 tp->serdes_counter--;
4196                 return;
4197         }
4198         if (!netif_carrier_ok(tp->dev) &&
4199             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4200                 u32 bmcr;
4201
4202                 tg3_readphy(tp, MII_BMCR, &bmcr);
4203                 if (bmcr & BMCR_ANENABLE) {
4204                         u32 phy1, phy2;
4205
4206                         /* Select shadow register 0x1f */
4207                         tg3_writephy(tp, 0x1c, 0x7c00);
4208                         tg3_readphy(tp, 0x1c, &phy1);
4209
4210                         /* Select expansion interrupt status register */
4211                         tg3_writephy(tp, 0x17, 0x0f01);
4212                         tg3_readphy(tp, 0x15, &phy2);
4213                         tg3_readphy(tp, 0x15, &phy2);
4214
4215                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4216                                 /* We have signal detect and not receiving
4217                                  * config code words, link is up by parallel
4218                                  * detection.
4219                                  */
4220
4221                                 bmcr &= ~BMCR_ANENABLE;
4222                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4223                                 tg3_writephy(tp, MII_BMCR, bmcr);
4224                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4225                         }
4226                 }
4227         }
4228         else if (netif_carrier_ok(tp->dev) &&
4229                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4230                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4231                 u32 phy2;
4232
4233                 /* Select expansion interrupt status register */
4234                 tg3_writephy(tp, 0x17, 0x0f01);
4235                 tg3_readphy(tp, 0x15, &phy2);
4236                 if (phy2 & 0x20) {
4237                         u32 bmcr;
4238
4239                         /* Config code words received, turn on autoneg. */
4240                         tg3_readphy(tp, MII_BMCR, &bmcr);
4241                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4242
4243                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4244
4245                 }
4246         }
4247 }
4248
4249 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4250 {
4251         int err;
4252
4253         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4254                 err = tg3_setup_fiber_phy(tp, force_reset);
4255         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4256                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4257         } else {
4258                 err = tg3_setup_copper_phy(tp, force_reset);
4259         }
4260
4261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4262                 u32 val, scale;
4263
4264                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4265                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4266                         scale = 65;
4267                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4268                         scale = 6;
4269                 else
4270                         scale = 12;
4271
4272                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4273                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4274                 tw32(GRC_MISC_CFG, val);
4275         }
4276
4277         if (tp->link_config.active_speed == SPEED_1000 &&
4278             tp->link_config.active_duplex == DUPLEX_HALF)
4279                 tw32(MAC_TX_LENGTHS,
4280                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4281                       (6 << TX_LENGTHS_IPG_SHIFT) |
4282                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4283         else
4284                 tw32(MAC_TX_LENGTHS,
4285                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4286                       (6 << TX_LENGTHS_IPG_SHIFT) |
4287                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4288
4289         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4290                 if (netif_carrier_ok(tp->dev)) {
4291                         tw32(HOSTCC_STAT_COAL_TICKS,
4292                              tp->coal.stats_block_coalesce_usecs);
4293                 } else {
4294                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4295                 }
4296         }
4297
4298         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4299                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4300                 if (!netif_carrier_ok(tp->dev))
4301                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4302                               tp->pwrmgmt_thresh;
4303                 else
4304                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4305                 tw32(PCIE_PWR_MGMT_THRESH, val);
4306         }
4307
4308         return err;
4309 }
4310
4311 /* This is called whenever we suspect that the system chipset is re-
4312  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4313  * is bogus tx completions. We try to recover by setting the
4314  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4315  * in the workqueue.
4316  */
4317 static void tg3_tx_recover(struct tg3 *tp)
4318 {
4319         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4320                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4321
4322         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4323                "mapped I/O cycles to the network device, attempting to "
4324                "recover. Please report the problem to the driver maintainer "
4325                "and include system chipset information.\n", tp->dev->name);
4326
4327         spin_lock(&tp->lock);
4328         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4329         spin_unlock(&tp->lock);
4330 }
4331
4332 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4333 {
4334         smp_mb();
4335         return tnapi->tx_pending -
4336                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4337 }
4338
4339 /* Tigon3 never reports partial packet sends.  So we do not
4340  * need special logic to handle SKBs that have not had all
4341  * of their frags sent yet, like SunGEM does.
4342  */
4343 static void tg3_tx(struct tg3_napi *tnapi)
4344 {
4345         struct tg3 *tp = tnapi->tp;
4346         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4347         u32 sw_idx = tnapi->tx_cons;
4348         struct netdev_queue *txq;
4349         int index = tnapi - tp->napi;
4350
4351         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4352                 index--;
4353
4354         txq = netdev_get_tx_queue(tp->dev, index);
4355
4356         while (sw_idx != hw_idx) {
4357                 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4358                 struct sk_buff *skb = ri->skb;
4359                 int i, tx_bug = 0;
4360
4361                 if (unlikely(skb == NULL)) {
4362                         tg3_tx_recover(tp);
4363                         return;
4364                 }
4365
4366                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4367
4368                 ri->skb = NULL;
4369
4370                 sw_idx = NEXT_TX(sw_idx);
4371
4372                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4373                         ri = &tnapi->tx_buffers[sw_idx];
4374                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4375                                 tx_bug = 1;
4376                         sw_idx = NEXT_TX(sw_idx);
4377                 }
4378
4379                 dev_kfree_skb(skb);
4380
4381                 if (unlikely(tx_bug)) {
4382                         tg3_tx_recover(tp);
4383                         return;
4384                 }
4385         }
4386
4387         tnapi->tx_cons = sw_idx;
4388
4389         /* Need to make the tx_cons update visible to tg3_start_xmit()
4390          * before checking for netif_queue_stopped().  Without the
4391          * memory barrier, there is a small possibility that tg3_start_xmit()
4392          * will miss it and cause the queue to be stopped forever.
4393          */
4394         smp_mb();
4395
4396         if (unlikely(netif_tx_queue_stopped(txq) &&
4397                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4398                 __netif_tx_lock(txq, smp_processor_id());
4399                 if (netif_tx_queue_stopped(txq) &&
4400                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4401                         netif_tx_wake_queue(txq);
4402                 __netif_tx_unlock(txq);
4403         }
4404 }
4405
4406 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4407 {
4408         if (!ri->skb)
4409                 return;
4410
4411         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4412                          map_sz, PCI_DMA_FROMDEVICE);
4413         dev_kfree_skb_any(ri->skb);
4414         ri->skb = NULL;
4415 }
4416
4417 /* Returns size of skb allocated or < 0 on error.
4418  *
4419  * We only need to fill in the address because the other members
4420  * of the RX descriptor are invariant, see tg3_init_rings.
4421  *
4422  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4423  * posting buffers we only dirty the first cache line of the RX
4424  * descriptor (containing the address).  Whereas for the RX status
4425  * buffers the cpu only reads the last cacheline of the RX descriptor
4426  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4427  */
4428 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4429                             u32 opaque_key, u32 dest_idx_unmasked)
4430 {
4431         struct tg3_rx_buffer_desc *desc;
4432         struct ring_info *map, *src_map;
4433         struct sk_buff *skb;
4434         dma_addr_t mapping;
4435         int skb_size, dest_idx;
4436
4437         src_map = NULL;
4438         switch (opaque_key) {
4439         case RXD_OPAQUE_RING_STD:
4440                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4441                 desc = &tpr->rx_std[dest_idx];
4442                 map = &tpr->rx_std_buffers[dest_idx];
4443                 skb_size = tp->rx_pkt_map_sz;
4444                 break;
4445
4446         case RXD_OPAQUE_RING_JUMBO:
4447                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4448                 desc = &tpr->rx_jmb[dest_idx].std;
4449                 map = &tpr->rx_jmb_buffers[dest_idx];
4450                 skb_size = TG3_RX_JMB_MAP_SZ;
4451                 break;
4452
4453         default:
4454                 return -EINVAL;
4455         }
4456
4457         /* Do not overwrite any of the map or rp information
4458          * until we are sure we can commit to a new buffer.
4459          *
4460          * Callers depend upon this behavior and assume that
4461          * we leave everything unchanged if we fail.
4462          */
4463         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4464         if (skb == NULL)
4465                 return -ENOMEM;
4466
4467         skb_reserve(skb, tp->rx_offset);
4468
4469         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4470                                  PCI_DMA_FROMDEVICE);
4471         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4472                 dev_kfree_skb(skb);
4473                 return -EIO;
4474         }
4475
4476         map->skb = skb;
4477         pci_unmap_addr_set(map, mapping, mapping);
4478
4479         desc->addr_hi = ((u64)mapping >> 32);
4480         desc->addr_lo = ((u64)mapping & 0xffffffff);
4481
4482         return skb_size;
4483 }
4484
4485 /* We only need to move over in the address because the other
4486  * members of the RX descriptor are invariant.  See notes above
4487  * tg3_alloc_rx_skb for full details.
4488  */
4489 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4490                            struct tg3_rx_prodring_set *dpr,
4491                            u32 opaque_key, int src_idx,
4492                            u32 dest_idx_unmasked)
4493 {
4494         struct tg3 *tp = tnapi->tp;
4495         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4496         struct ring_info *src_map, *dest_map;
4497         int dest_idx;
4498         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4499
4500         switch (opaque_key) {
4501         case RXD_OPAQUE_RING_STD:
4502                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4503                 dest_desc = &dpr->rx_std[dest_idx];
4504                 dest_map = &dpr->rx_std_buffers[dest_idx];
4505                 src_desc = &spr->rx_std[src_idx];
4506                 src_map = &spr->rx_std_buffers[src_idx];
4507                 break;
4508
4509         case RXD_OPAQUE_RING_JUMBO:
4510                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4511                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4512                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4513                 src_desc = &spr->rx_jmb[src_idx].std;
4514                 src_map = &spr->rx_jmb_buffers[src_idx];
4515                 break;
4516
4517         default:
4518                 return;
4519         }
4520
4521         dest_map->skb = src_map->skb;
4522         pci_unmap_addr_set(dest_map, mapping,
4523                            pci_unmap_addr(src_map, mapping));
4524         dest_desc->addr_hi = src_desc->addr_hi;
4525         dest_desc->addr_lo = src_desc->addr_lo;
4526         src_map->skb = NULL;
4527 }
4528
4529 /* The RX ring scheme is composed of multiple rings which post fresh
4530  * buffers to the chip, and one special ring the chip uses to report
4531  * status back to the host.
4532  *
4533  * The special ring reports the status of received packets to the
4534  * host.  The chip does not write into the original descriptor the
4535  * RX buffer was obtained from.  The chip simply takes the original
4536  * descriptor as provided by the host, updates the status and length
4537  * field, then writes this into the next status ring entry.
4538  *
4539  * Each ring the host uses to post buffers to the chip is described
4540  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4541  * it is first placed into the on-chip ram.  When the packet's length
4542  * is known, it walks down the TG3_BDINFO entries to select the ring.
4543  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4544  * which is within the range of the new packet's length is chosen.
4545  *
4546  * The "separate ring for rx status" scheme may sound queer, but it makes
4547  * sense from a cache coherency perspective.  If only the host writes
4548  * to the buffer post rings, and only the chip writes to the rx status
4549  * rings, then cache lines never move beyond shared-modified state.
4550  * If both the host and chip were to write into the same ring, cache line
4551  * eviction could occur since both entities want it in an exclusive state.
4552  */
4553 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4554 {
4555         struct tg3 *tp = tnapi->tp;
4556         u32 work_mask, rx_std_posted = 0;
4557         u32 std_prod_idx, jmb_prod_idx;
4558         u32 sw_idx = tnapi->rx_rcb_ptr;
4559         u16 hw_idx;
4560         int received;
4561         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4562
4563         hw_idx = *(tnapi->rx_rcb_prod_idx);
4564         /*
4565          * We need to order the read of hw_idx and the read of
4566          * the opaque cookie.
4567          */
4568         rmb();
4569         work_mask = 0;
4570         received = 0;
4571         std_prod_idx = tpr->rx_std_prod_idx;
4572         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4573         while (sw_idx != hw_idx && budget > 0) {
4574                 struct ring_info *ri;
4575                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4576                 unsigned int len;
4577                 struct sk_buff *skb;
4578                 dma_addr_t dma_addr;
4579                 u32 opaque_key, desc_idx, *post_ptr;
4580
4581                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4582                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4583                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4584                         ri = &tpr->rx_std_buffers[desc_idx];
4585                         dma_addr = pci_unmap_addr(ri, mapping);
4586                         skb = ri->skb;
4587                         post_ptr = &std_prod_idx;
4588                         rx_std_posted++;
4589                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4590                         ri = &tpr->rx_jmb_buffers[desc_idx];
4591                         dma_addr = pci_unmap_addr(ri, mapping);
4592                         skb = ri->skb;
4593                         post_ptr = &jmb_prod_idx;
4594                 } else
4595                         goto next_pkt_nopost;
4596
4597                 work_mask |= opaque_key;
4598
4599                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4600                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4601                 drop_it:
4602                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4603                                        desc_idx, *post_ptr);
4604                 drop_it_no_recycle:
4605                         /* Other statistics kept track of by card. */
4606                         tp->net_stats.rx_dropped++;
4607                         goto next_pkt;
4608                 }
4609
4610                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4611                       ETH_FCS_LEN;
4612
4613                 if (len > RX_COPY_THRESHOLD
4614                         && tp->rx_offset == NET_IP_ALIGN
4615                         /* rx_offset will likely not equal NET_IP_ALIGN
4616                          * if this is a 5701 card running in PCI-X mode
4617                          * [see tg3_get_invariants()]
4618                          */
4619                 ) {
4620                         int skb_size;
4621
4622                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4623                                                     *post_ptr);
4624                         if (skb_size < 0)
4625                                 goto drop_it;
4626
4627                         ri->skb = NULL;
4628
4629                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4630                                          PCI_DMA_FROMDEVICE);
4631
4632                         skb_put(skb, len);
4633                 } else {
4634                         struct sk_buff *copy_skb;
4635
4636                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4637                                        desc_idx, *post_ptr);
4638
4639                         copy_skb = netdev_alloc_skb(tp->dev,
4640                                                     len + TG3_RAW_IP_ALIGN);
4641                         if (copy_skb == NULL)
4642                                 goto drop_it_no_recycle;
4643
4644                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4645                         skb_put(copy_skb, len);
4646                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4647                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4648                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4649
4650                         /* We'll reuse the original ring buffer. */
4651                         skb = copy_skb;
4652                 }
4653
4654                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4655                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4656                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4657                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4658                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4659                 else
4660                         skb->ip_summed = CHECKSUM_NONE;
4661
4662                 skb->protocol = eth_type_trans(skb, tp->dev);
4663
4664                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4665                     skb->protocol != htons(ETH_P_8021Q)) {
4666                         dev_kfree_skb(skb);
4667                         goto next_pkt;
4668                 }
4669
4670 #if TG3_VLAN_TAG_USED
4671                 if (tp->vlgrp != NULL &&
4672                     desc->type_flags & RXD_FLAG_VLAN) {
4673                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4674                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4675                 } else
4676 #endif
4677                         napi_gro_receive(&tnapi->napi, skb);
4678
4679                 received++;
4680                 budget--;
4681
4682 next_pkt:
4683                 (*post_ptr)++;
4684
4685                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4686                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4687                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4688                         work_mask &= ~RXD_OPAQUE_RING_STD;
4689                         rx_std_posted = 0;
4690                 }
4691 next_pkt_nopost:
4692                 sw_idx++;
4693                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4694
4695                 /* Refresh hw_idx to see if there is new work */
4696                 if (sw_idx == hw_idx) {
4697                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4698                         rmb();
4699                 }
4700         }
4701
4702         /* ACK the status ring. */
4703         tnapi->rx_rcb_ptr = sw_idx;
4704         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4705
4706         /* Refill RX ring(s). */
4707         if (work_mask & RXD_OPAQUE_RING_STD) {
4708                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4709                 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
4710         }
4711         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4712                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4713                 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
4714         }
4715         mmiowb();
4716
4717         return received;
4718 }
4719
4720 static void tg3_poll_link(struct tg3 *tp)
4721 {
4722         /* handle link change and other phy events */
4723         if (!(tp->tg3_flags &
4724               (TG3_FLAG_USE_LINKCHG_REG |
4725                TG3_FLAG_POLL_SERDES))) {
4726                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4727
4728                 if (sblk->status & SD_STATUS_LINK_CHG) {
4729                         sblk->status = SD_STATUS_UPDATED |
4730                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4731                         spin_lock(&tp->lock);
4732                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4733                                 tw32_f(MAC_STATUS,
4734                                      (MAC_STATUS_SYNC_CHANGED |
4735                                       MAC_STATUS_CFG_CHANGED |
4736                                       MAC_STATUS_MI_COMPLETION |
4737                                       MAC_STATUS_LNKSTATE_CHANGED));
4738                                 udelay(40);
4739                         } else
4740                                 tg3_setup_phy(tp, 0);
4741                         spin_unlock(&tp->lock);
4742                 }
4743         }
4744 }
4745
4746 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4747 {
4748         struct tg3 *tp = tnapi->tp;
4749
4750         /* run TX completion thread */
4751         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4752                 tg3_tx(tnapi);
4753                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4754                         return work_done;
4755         }
4756
4757         /* run RX thread, within the bounds set by NAPI.
4758          * All RX "locking" is done by ensuring outside
4759          * code synchronizes with tg3->napi.poll()
4760          */
4761         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4762                 work_done += tg3_rx(tnapi, budget - work_done);
4763
4764         return work_done;
4765 }
4766
4767 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4768 {
4769         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4770         struct tg3 *tp = tnapi->tp;
4771         int work_done = 0;
4772         struct tg3_hw_status *sblk = tnapi->hw_status;
4773
4774         while (1) {
4775                 work_done = tg3_poll_work(tnapi, work_done, budget);
4776
4777                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4778                         goto tx_recovery;
4779
4780                 if (unlikely(work_done >= budget))
4781                         break;
4782
4783                 /* tp->last_tag is used in tg3_restart_ints() below
4784                  * to tell the hw how much work has been processed,
4785                  * so we must read it before checking for more work.
4786                  */
4787                 tnapi->last_tag = sblk->status_tag;
4788                 tnapi->last_irq_tag = tnapi->last_tag;
4789                 rmb();
4790
4791                 /* check for RX/TX work to do */
4792                 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4793                     *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4794                         napi_complete(napi);
4795                         /* Reenable interrupts. */
4796                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4797                         mmiowb();
4798                         break;
4799                 }
4800         }
4801
4802         return work_done;
4803
4804 tx_recovery:
4805         /* work_done is guaranteed to be less than budget. */
4806         napi_complete(napi);
4807         schedule_work(&tp->reset_task);
4808         return work_done;
4809 }
4810
4811 static int tg3_poll(struct napi_struct *napi, int budget)
4812 {
4813         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4814         struct tg3 *tp = tnapi->tp;
4815         int work_done = 0;
4816         struct tg3_hw_status *sblk = tnapi->hw_status;
4817
4818         while (1) {
4819                 tg3_poll_link(tp);
4820
4821                 work_done = tg3_poll_work(tnapi, work_done, budget);
4822
4823                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4824                         goto tx_recovery;
4825
4826                 if (unlikely(work_done >= budget))
4827                         break;
4828
4829                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4830                         /* tp->last_tag is used in tg3_int_reenable() below
4831                          * to tell the hw how much work has been processed,
4832                          * so we must read it before checking for more work.
4833                          */
4834                         tnapi->last_tag = sblk->status_tag;
4835                         tnapi->last_irq_tag = tnapi->last_tag;
4836                         rmb();
4837                 } else
4838                         sblk->status &= ~SD_STATUS_UPDATED;
4839
4840                 if (likely(!tg3_has_work(tnapi))) {
4841                         napi_complete(napi);
4842                         tg3_int_reenable(tnapi);
4843                         break;
4844                 }
4845         }
4846
4847         return work_done;
4848
4849 tx_recovery:
4850         /* work_done is guaranteed to be less than budget. */
4851         napi_complete(napi);
4852         schedule_work(&tp->reset_task);
4853         return work_done;
4854 }
4855
4856 static void tg3_irq_quiesce(struct tg3 *tp)
4857 {
4858         int i;
4859
4860         BUG_ON(tp->irq_sync);
4861
4862         tp->irq_sync = 1;
4863         smp_mb();
4864
4865         for (i = 0; i < tp->irq_cnt; i++)
4866                 synchronize_irq(tp->napi[i].irq_vec);
4867 }
4868
4869 static inline int tg3_irq_sync(struct tg3 *tp)
4870 {
4871         return tp->irq_sync;
4872 }
4873
4874 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4875  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4876  * with as well.  Most of the time, this is not necessary except when
4877  * shutting down the device.
4878  */
4879 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4880 {
4881         spin_lock_bh(&tp->lock);
4882         if (irq_sync)
4883                 tg3_irq_quiesce(tp);
4884 }
4885
4886 static inline void tg3_full_unlock(struct tg3 *tp)
4887 {
4888         spin_unlock_bh(&tp->lock);
4889 }
4890
4891 /* One-shot MSI handler - Chip automatically disables interrupt
4892  * after sending MSI so driver doesn't have to do it.
4893  */
4894 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4895 {
4896         struct tg3_napi *tnapi = dev_id;
4897         struct tg3 *tp = tnapi->tp;
4898
4899         prefetch(tnapi->hw_status);
4900         if (tnapi->rx_rcb)
4901                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4902
4903         if (likely(!tg3_irq_sync(tp)))
4904                 napi_schedule(&tnapi->napi);
4905
4906         return IRQ_HANDLED;
4907 }
4908
4909 /* MSI ISR - No need to check for interrupt sharing and no need to
4910  * flush status block and interrupt mailbox. PCI ordering rules
4911  * guarantee that MSI will arrive after the status block.
4912  */
4913 static irqreturn_t tg3_msi(int irq, void *dev_id)
4914 {
4915         struct tg3_napi *tnapi = dev_id;
4916         struct tg3 *tp = tnapi->tp;
4917
4918         prefetch(tnapi->hw_status);
4919         if (tnapi->rx_rcb)
4920                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4921         /*
4922          * Writing any value to intr-mbox-0 clears PCI INTA# and
4923          * chip-internal interrupt pending events.
4924          * Writing non-zero to intr-mbox-0 additional tells the
4925          * NIC to stop sending us irqs, engaging "in-intr-handler"
4926          * event coalescing.
4927          */
4928         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4929         if (likely(!tg3_irq_sync(tp)))
4930                 napi_schedule(&tnapi->napi);
4931
4932         return IRQ_RETVAL(1);
4933 }
4934
4935 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4936 {
4937         struct tg3_napi *tnapi = dev_id;
4938         struct tg3 *tp = tnapi->tp;
4939         struct tg3_hw_status *sblk = tnapi->hw_status;
4940         unsigned int handled = 1;
4941
4942         /* In INTx mode, it is possible for the interrupt to arrive at
4943          * the CPU before the status block posted prior to the interrupt.
4944          * Reading the PCI State register will confirm whether the
4945          * interrupt is ours and will flush the status block.
4946          */
4947         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4948                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4949                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4950                         handled = 0;
4951                         goto out;
4952                 }
4953         }
4954
4955         /*
4956          * Writing any value to intr-mbox-0 clears PCI INTA# and
4957          * chip-internal interrupt pending events.
4958          * Writing non-zero to intr-mbox-0 additional tells the
4959          * NIC to stop sending us irqs, engaging "in-intr-handler"
4960          * event coalescing.
4961          *
4962          * Flush the mailbox to de-assert the IRQ immediately to prevent
4963          * spurious interrupts.  The flush impacts performance but
4964          * excessive spurious interrupts can be worse in some cases.
4965          */
4966         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4967         if (tg3_irq_sync(tp))
4968                 goto out;
4969         sblk->status &= ~SD_STATUS_UPDATED;
4970         if (likely(tg3_has_work(tnapi))) {
4971                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4972                 napi_schedule(&tnapi->napi);
4973         } else {
4974                 /* No work, shared interrupt perhaps?  re-enable
4975                  * interrupts, and flush that PCI write
4976                  */
4977                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4978                                0x00000000);
4979         }
4980 out:
4981         return IRQ_RETVAL(handled);
4982 }
4983
4984 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4985 {
4986         struct tg3_napi *tnapi = dev_id;
4987         struct tg3 *tp = tnapi->tp;
4988         struct tg3_hw_status *sblk = tnapi->hw_status;
4989         unsigned int handled = 1;
4990
4991         /* In INTx mode, it is possible for the interrupt to arrive at
4992          * the CPU before the status block posted prior to the interrupt.
4993          * Reading the PCI State register will confirm whether the
4994          * interrupt is ours and will flush the status block.
4995          */
4996         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4997                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4998                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4999                         handled = 0;
5000                         goto out;
5001                 }
5002         }
5003
5004         /*
5005          * writing any value to intr-mbox-0 clears PCI INTA# and
5006          * chip-internal interrupt pending events.
5007          * writing non-zero to intr-mbox-0 additional tells the
5008          * NIC to stop sending us irqs, engaging "in-intr-handler"
5009          * event coalescing.
5010          *
5011          * Flush the mailbox to de-assert the IRQ immediately to prevent
5012          * spurious interrupts.  The flush impacts performance but
5013          * excessive spurious interrupts can be worse in some cases.
5014          */
5015         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5016
5017         /*
5018          * In a shared interrupt configuration, sometimes other devices'
5019          * interrupts will scream.  We record the current status tag here
5020          * so that the above check can report that the screaming interrupts
5021          * are unhandled.  Eventually they will be silenced.
5022          */
5023         tnapi->last_irq_tag = sblk->status_tag;
5024
5025         if (tg3_irq_sync(tp))
5026                 goto out;
5027
5028         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5029
5030         napi_schedule(&tnapi->napi);
5031
5032 out:
5033         return IRQ_RETVAL(handled);
5034 }
5035
5036 /* ISR for interrupt test */
5037 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5038 {
5039         struct tg3_napi *tnapi = dev_id;
5040         struct tg3 *tp = tnapi->tp;
5041         struct tg3_hw_status *sblk = tnapi->hw_status;
5042
5043         if ((sblk->status & SD_STATUS_UPDATED) ||
5044             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5045                 tg3_disable_ints(tp);
5046                 return IRQ_RETVAL(1);
5047         }
5048         return IRQ_RETVAL(0);
5049 }
5050
5051 static int tg3_init_hw(struct tg3 *, int);
5052 static int tg3_halt(struct tg3 *, int, int);
5053
5054 /* Restart hardware after configuration changes, self-test, etc.
5055  * Invoked with tp->lock held.
5056  */
5057 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5058         __releases(tp->lock)
5059         __acquires(tp->lock)
5060 {
5061         int err;
5062
5063         err = tg3_init_hw(tp, reset_phy);
5064         if (err) {
5065                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5066                        "aborting.\n", tp->dev->name);
5067                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5068                 tg3_full_unlock(tp);
5069                 del_timer_sync(&tp->timer);
5070                 tp->irq_sync = 0;
5071                 tg3_napi_enable(tp);
5072                 dev_close(tp->dev);
5073                 tg3_full_lock(tp, 0);
5074         }
5075         return err;
5076 }
5077
5078 #ifdef CONFIG_NET_POLL_CONTROLLER
5079 static void tg3_poll_controller(struct net_device *dev)
5080 {
5081         int i;
5082         struct tg3 *tp = netdev_priv(dev);
5083
5084         for (i = 0; i < tp->irq_cnt; i++)
5085                 tg3_interrupt(tp->napi[i].irq_vec, dev);
5086 }
5087 #endif
5088
5089 static void tg3_reset_task(struct work_struct *work)
5090 {
5091         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5092         int err;
5093         unsigned int restart_timer;
5094
5095         tg3_full_lock(tp, 0);
5096
5097         if (!netif_running(tp->dev)) {
5098                 tg3_full_unlock(tp);
5099                 return;
5100         }
5101
5102         tg3_full_unlock(tp);
5103
5104         tg3_phy_stop(tp);
5105
5106         tg3_netif_stop(tp);
5107
5108         tg3_full_lock(tp, 1);
5109
5110         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5111         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5112
5113         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5114                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5115                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5116                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5117                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5118         }
5119
5120         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5121         err = tg3_init_hw(tp, 1);
5122         if (err)
5123                 goto out;
5124
5125         tg3_netif_start(tp);
5126
5127         if (restart_timer)
5128                 mod_timer(&tp->timer, jiffies + 1);
5129
5130 out:
5131         tg3_full_unlock(tp);
5132
5133         if (!err)
5134                 tg3_phy_start(tp);
5135 }
5136
5137 static void tg3_dump_short_state(struct tg3 *tp)
5138 {
5139         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5140                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5141         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5142                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5143 }
5144
5145 static void tg3_tx_timeout(struct net_device *dev)
5146 {
5147         struct tg3 *tp = netdev_priv(dev);
5148
5149         if (netif_msg_tx_err(tp)) {
5150                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5151                        dev->name);
5152                 tg3_dump_short_state(tp);
5153         }
5154
5155         schedule_work(&tp->reset_task);
5156 }
5157
5158 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5159 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5160 {
5161         u32 base = (u32) mapping & 0xffffffff;
5162
5163         return ((base > 0xffffdcc0) &&
5164                 (base + len + 8 < base));
5165 }
5166
5167 /* Test for DMA addresses > 40-bit */
5168 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5169                                           int len)
5170 {
5171 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5172         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5173                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5174         return 0;
5175 #else
5176         return 0;
5177 #endif
5178 }
5179
5180 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5181
5182 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5183 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5184                                        struct sk_buff *skb, u32 last_plus_one,
5185                                        u32 *start, u32 base_flags, u32 mss)
5186 {
5187         struct tg3 *tp = tnapi->tp;
5188         struct sk_buff *new_skb;
5189         dma_addr_t new_addr = 0;
5190         u32 entry = *start;
5191         int i, ret = 0;
5192
5193         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5194                 new_skb = skb_copy(skb, GFP_ATOMIC);
5195         else {
5196                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5197
5198                 new_skb = skb_copy_expand(skb,
5199                                           skb_headroom(skb) + more_headroom,
5200                                           skb_tailroom(skb), GFP_ATOMIC);
5201         }
5202
5203         if (!new_skb) {
5204                 ret = -1;
5205         } else {
5206                 /* New SKB is guaranteed to be linear. */
5207                 entry = *start;
5208                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5209                 new_addr = skb_shinfo(new_skb)->dma_head;
5210
5211                 /* Make sure new skb does not cross any 4G boundaries.
5212                  * Drop the packet if it does.
5213                  */
5214                 if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5215                             tg3_4g_overflow_test(new_addr, new_skb->len))) {
5216                         if (!ret)
5217                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5218                                               DMA_TO_DEVICE);
5219                         ret = -1;
5220                         dev_kfree_skb(new_skb);
5221                         new_skb = NULL;
5222                 } else {
5223                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5224                                     base_flags, 1 | (mss << 1));
5225                         *start = NEXT_TX(entry);
5226                 }
5227         }
5228
5229         /* Now clean up the sw ring entries. */
5230         i = 0;
5231         while (entry != last_plus_one) {
5232                 if (i == 0)
5233                         tnapi->tx_buffers[entry].skb = new_skb;
5234                 else
5235                         tnapi->tx_buffers[entry].skb = NULL;
5236                 entry = NEXT_TX(entry);
5237                 i++;
5238         }
5239
5240         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5241         dev_kfree_skb(skb);
5242
5243         return ret;
5244 }
5245
5246 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5247                         dma_addr_t mapping, int len, u32 flags,
5248                         u32 mss_and_is_end)
5249 {
5250         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5251         int is_end = (mss_and_is_end & 0x1);
5252         u32 mss = (mss_and_is_end >> 1);
5253         u32 vlan_tag = 0;
5254
5255         if (is_end)
5256                 flags |= TXD_FLAG_END;
5257         if (flags & TXD_FLAG_VLAN) {
5258                 vlan_tag = flags >> 16;
5259                 flags &= 0xffff;
5260         }
5261         vlan_tag |= (mss << TXD_MSS_SHIFT);
5262
5263         txd->addr_hi = ((u64) mapping >> 32);
5264         txd->addr_lo = ((u64) mapping & 0xffffffff);
5265         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5266         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5267 }
5268
5269 /* hard_start_xmit for devices that don't have any bugs and
5270  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5271  */
5272 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5273                                   struct net_device *dev)
5274 {
5275         struct tg3 *tp = netdev_priv(dev);
5276         u32 len, entry, base_flags, mss;
5277         struct skb_shared_info *sp;
5278         dma_addr_t mapping;
5279         struct tg3_napi *tnapi;
5280         struct netdev_queue *txq;
5281
5282         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5283         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5284         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5285                 tnapi++;
5286
5287         /* We are running in BH disabled context with netif_tx_lock
5288          * and TX reclaim runs via tp->napi.poll inside of a software
5289          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5290          * no IRQ context deadlocks to worry about either.  Rejoice!
5291          */
5292         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5293                 if (!netif_tx_queue_stopped(txq)) {
5294                         netif_tx_stop_queue(txq);
5295
5296                         /* This is a hard error, log it. */
5297                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5298                                "queue awake!\n", dev->name);
5299                 }
5300                 return NETDEV_TX_BUSY;
5301         }
5302
5303         entry = tnapi->tx_prod;
5304         base_flags = 0;
5305         mss = 0;
5306         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5307                 int tcp_opt_len, ip_tcp_len;
5308                 u32 hdrlen;
5309
5310                 if (skb_header_cloned(skb) &&
5311                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5312                         dev_kfree_skb(skb);
5313                         goto out_unlock;
5314                 }
5315
5316                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5317                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5318                 else {
5319                         struct iphdr *iph = ip_hdr(skb);
5320
5321                         tcp_opt_len = tcp_optlen(skb);
5322                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5323
5324                         iph->check = 0;
5325                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5326                         hdrlen = ip_tcp_len + tcp_opt_len;
5327                 }
5328
5329                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5330                         mss |= (hdrlen & 0xc) << 12;
5331                         if (hdrlen & 0x10)
5332                                 base_flags |= 0x00000010;
5333                         base_flags |= (hdrlen & 0x3e0) << 5;
5334                 } else
5335                         mss |= hdrlen << 9;
5336
5337                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5338                                TXD_FLAG_CPU_POST_DMA);
5339
5340                 tcp_hdr(skb)->check = 0;
5341
5342         }
5343         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5344                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5345 #if TG3_VLAN_TAG_USED
5346         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5347                 base_flags |= (TXD_FLAG_VLAN |
5348                                (vlan_tx_tag_get(skb) << 16));
5349 #endif
5350
5351         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5352                 dev_kfree_skb(skb);
5353                 goto out_unlock;
5354         }
5355
5356         sp = skb_shinfo(skb);
5357
5358         mapping = sp->dma_head;
5359
5360         tnapi->tx_buffers[entry].skb = skb;
5361
5362         len = skb_headlen(skb);
5363
5364         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5365             !mss && skb->len > ETH_DATA_LEN)
5366                 base_flags |= TXD_FLAG_JMB_PKT;
5367
5368         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5369                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5370
5371         entry = NEXT_TX(entry);
5372
5373         /* Now loop through additional data fragments, and queue them. */
5374         if (skb_shinfo(skb)->nr_frags > 0) {
5375                 unsigned int i, last;
5376
5377                 last = skb_shinfo(skb)->nr_frags - 1;
5378                 for (i = 0; i <= last; i++) {
5379                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5380
5381                         len = frag->size;
5382                         mapping = sp->dma_maps[i];
5383                         tnapi->tx_buffers[entry].skb = NULL;
5384
5385                         tg3_set_txd(tnapi, entry, mapping, len,
5386                                     base_flags, (i == last) | (mss << 1));
5387
5388                         entry = NEXT_TX(entry);
5389                 }
5390         }
5391
5392         /* Packets are ready, update Tx producer idx local and on card. */
5393         tw32_tx_mbox(tnapi->prodmbox, entry);
5394
5395         tnapi->tx_prod = entry;
5396         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5397                 netif_tx_stop_queue(txq);
5398                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5399                         netif_tx_wake_queue(txq);
5400         }
5401
5402 out_unlock:
5403         mmiowb();
5404
5405         return NETDEV_TX_OK;
5406 }
5407
5408 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5409                                           struct net_device *);
5410
5411 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5412  * TSO header is greater than 80 bytes.
5413  */
5414 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5415 {
5416         struct sk_buff *segs, *nskb;
5417         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5418
5419         /* Estimate the number of fragments in the worst case */
5420         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5421                 netif_stop_queue(tp->dev);
5422                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5423                         return NETDEV_TX_BUSY;
5424
5425                 netif_wake_queue(tp->dev);
5426         }
5427
5428         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5429         if (IS_ERR(segs))
5430                 goto tg3_tso_bug_end;
5431
5432         do {
5433                 nskb = segs;
5434                 segs = segs->next;
5435                 nskb->next = NULL;
5436                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5437         } while (segs);
5438
5439 tg3_tso_bug_end:
5440         dev_kfree_skb(skb);
5441
5442         return NETDEV_TX_OK;
5443 }
5444
5445 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5446  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5447  */
5448 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5449                                           struct net_device *dev)
5450 {
5451         struct tg3 *tp = netdev_priv(dev);
5452         u32 len, entry, base_flags, mss;
5453         struct skb_shared_info *sp;
5454         int would_hit_hwbug;
5455         dma_addr_t mapping;
5456         struct tg3_napi *tnapi;
5457         struct netdev_queue *txq;
5458
5459         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5460         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5461         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5462                 tnapi++;
5463
5464         /* We are running in BH disabled context with netif_tx_lock
5465          * and TX reclaim runs via tp->napi.poll inside of a software
5466          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5467          * no IRQ context deadlocks to worry about either.  Rejoice!
5468          */
5469         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5470                 if (!netif_tx_queue_stopped(txq)) {
5471                         netif_tx_stop_queue(txq);
5472
5473                         /* This is a hard error, log it. */
5474                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5475                                "queue awake!\n", dev->name);
5476                 }
5477                 return NETDEV_TX_BUSY;
5478         }
5479
5480         entry = tnapi->tx_prod;
5481         base_flags = 0;
5482         if (skb->ip_summed == CHECKSUM_PARTIAL)
5483                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5484
5485         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5486                 struct iphdr *iph;
5487                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5488
5489                 if (skb_header_cloned(skb) &&
5490                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5491                         dev_kfree_skb(skb);
5492                         goto out_unlock;
5493                 }
5494
5495                 tcp_opt_len = tcp_optlen(skb);
5496                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5497
5498                 hdr_len = ip_tcp_len + tcp_opt_len;
5499                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5500                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5501                         return (tg3_tso_bug(tp, skb));
5502
5503                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5504                                TXD_FLAG_CPU_POST_DMA);
5505
5506                 iph = ip_hdr(skb);
5507                 iph->check = 0;
5508                 iph->tot_len = htons(mss + hdr_len);
5509                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5510                         tcp_hdr(skb)->check = 0;
5511                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5512                 } else
5513                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5514                                                                  iph->daddr, 0,
5515                                                                  IPPROTO_TCP,
5516                                                                  0);
5517
5518                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5519                         mss |= (hdr_len & 0xc) << 12;
5520                         if (hdr_len & 0x10)
5521                                 base_flags |= 0x00000010;
5522                         base_flags |= (hdr_len & 0x3e0) << 5;
5523                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5524                         mss |= hdr_len << 9;
5525                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5526                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5527                         if (tcp_opt_len || iph->ihl > 5) {
5528                                 int tsflags;
5529
5530                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5531                                 mss |= (tsflags << 11);
5532                         }
5533                 } else {
5534                         if (tcp_opt_len || iph->ihl > 5) {
5535                                 int tsflags;
5536
5537                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5538                                 base_flags |= tsflags << 12;
5539                         }
5540                 }
5541         }
5542 #if TG3_VLAN_TAG_USED
5543         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5544                 base_flags |= (TXD_FLAG_VLAN |
5545                                (vlan_tx_tag_get(skb) << 16));
5546 #endif
5547
5548         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5549             !mss && skb->len > ETH_DATA_LEN)
5550                 base_flags |= TXD_FLAG_JMB_PKT;
5551
5552         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5553                 dev_kfree_skb(skb);
5554                 goto out_unlock;
5555         }
5556
5557         sp = skb_shinfo(skb);
5558
5559         mapping = sp->dma_head;
5560
5561         tnapi->tx_buffers[entry].skb = skb;
5562
5563         would_hit_hwbug = 0;
5564
5565         len = skb_headlen(skb);
5566
5567         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5568                 would_hit_hwbug = 1;
5569
5570         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5571             tg3_4g_overflow_test(mapping, len))
5572                 would_hit_hwbug = 1;
5573
5574         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5575             tg3_40bit_overflow_test(tp, mapping, len))
5576                 would_hit_hwbug = 1;
5577
5578         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5579                 would_hit_hwbug = 1;
5580
5581         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5582                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5583
5584         entry = NEXT_TX(entry);
5585
5586         /* Now loop through additional data fragments, and queue them. */
5587         if (skb_shinfo(skb)->nr_frags > 0) {
5588                 unsigned int i, last;
5589
5590                 last = skb_shinfo(skb)->nr_frags - 1;
5591                 for (i = 0; i <= last; i++) {
5592                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5593
5594                         len = frag->size;
5595                         mapping = sp->dma_maps[i];
5596
5597                         tnapi->tx_buffers[entry].skb = NULL;
5598
5599                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5600                             len <= 8)
5601                                 would_hit_hwbug = 1;
5602
5603                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5604                             tg3_4g_overflow_test(mapping, len))
5605                                 would_hit_hwbug = 1;
5606
5607                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5608                             tg3_40bit_overflow_test(tp, mapping, len))
5609                                 would_hit_hwbug = 1;
5610
5611                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5612                                 tg3_set_txd(tnapi, entry, mapping, len,
5613                                             base_flags, (i == last)|(mss << 1));
5614                         else
5615                                 tg3_set_txd(tnapi, entry, mapping, len,
5616                                             base_flags, (i == last));
5617
5618                         entry = NEXT_TX(entry);
5619                 }
5620         }
5621
5622         if (would_hit_hwbug) {
5623                 u32 last_plus_one = entry;
5624                 u32 start;
5625
5626                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5627                 start &= (TG3_TX_RING_SIZE - 1);
5628
5629                 /* If the workaround fails due to memory/mapping
5630                  * failure, silently drop this packet.
5631                  */
5632                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5633                                                 &start, base_flags, mss))
5634                         goto out_unlock;
5635
5636                 entry = start;
5637         }
5638
5639         /* Packets are ready, update Tx producer idx local and on card. */
5640         tw32_tx_mbox(tnapi->prodmbox, entry);
5641
5642         tnapi->tx_prod = entry;
5643         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5644                 netif_tx_stop_queue(txq);
5645                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5646                         netif_tx_wake_queue(txq);
5647         }
5648
5649 out_unlock:
5650         mmiowb();
5651
5652         return NETDEV_TX_OK;
5653 }
5654
5655 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5656                                int new_mtu)
5657 {
5658         dev->mtu = new_mtu;
5659
5660         if (new_mtu > ETH_DATA_LEN) {
5661                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5662                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5663                         ethtool_op_set_tso(dev, 0);
5664                 }
5665                 else
5666                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5667         } else {
5668                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5669                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5670                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5671         }
5672 }
5673
5674 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5675 {
5676         struct tg3 *tp = netdev_priv(dev);
5677         int err;
5678
5679         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5680                 return -EINVAL;
5681
5682         if (!netif_running(dev)) {
5683                 /* We'll just catch it later when the
5684                  * device is up'd.
5685                  */
5686                 tg3_set_mtu(dev, tp, new_mtu);
5687                 return 0;
5688         }
5689
5690         tg3_phy_stop(tp);
5691
5692         tg3_netif_stop(tp);
5693
5694         tg3_full_lock(tp, 1);
5695
5696         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5697
5698         tg3_set_mtu(dev, tp, new_mtu);
5699
5700         err = tg3_restart_hw(tp, 0);
5701
5702         if (!err)
5703                 tg3_netif_start(tp);
5704
5705         tg3_full_unlock(tp);
5706
5707         if (!err)
5708                 tg3_phy_start(tp);
5709
5710         return err;
5711 }
5712
5713 static void tg3_rx_prodring_free(struct tg3 *tp,
5714                                  struct tg3_rx_prodring_set *tpr)
5715 {
5716         int i;
5717
5718         if (tpr != &tp->prodring[0])
5719                 return;
5720
5721         for (i = 0; i < TG3_RX_RING_SIZE; i++)
5722                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5723                                 tp->rx_pkt_map_sz);
5724
5725         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5726                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5727                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5728                                         TG3_RX_JMB_MAP_SZ);
5729         }
5730 }
5731
5732 /* Initialize tx/rx rings for packet processing.
5733  *
5734  * The chip has been shut down and the driver detached from
5735  * the networking, so no interrupts or new tx packets will
5736  * end up in the driver.  tp->{tx,}lock are held and thus
5737  * we may not sleep.
5738  */
5739 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5740                                  struct tg3_rx_prodring_set *tpr)
5741 {
5742         u32 i, rx_pkt_dma_sz;
5743
5744         if (tpr != &tp->prodring[0]) {
5745                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5746                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5747                         memset(&tpr->rx_jmb_buffers[0], 0,
5748                                TG3_RX_JMB_BUFF_RING_SIZE);
5749                 goto done;
5750         }
5751
5752         /* Zero out all descriptors. */
5753         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5754
5755         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5756         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5757             tp->dev->mtu > ETH_DATA_LEN)
5758                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5759         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5760
5761         /* Initialize invariants of the rings, we only set this
5762          * stuff once.  This works because the card does not
5763          * write into the rx buffer posting rings.
5764          */
5765         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5766                 struct tg3_rx_buffer_desc *rxd;
5767
5768                 rxd = &tpr->rx_std[i];
5769                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5770                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5771                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5772                                (i << RXD_OPAQUE_INDEX_SHIFT));
5773         }
5774
5775         /* Now allocate fresh SKBs for each rx ring. */
5776         for (i = 0; i < tp->rx_pending; i++) {
5777                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
5778                         printk(KERN_WARNING PFX
5779                                "%s: Using a smaller RX standard ring, "
5780                                "only %d out of %d buffers were allocated "
5781                                "successfully.\n",
5782                                tp->dev->name, i, tp->rx_pending);
5783                         if (i == 0)
5784                                 goto initfail;
5785                         tp->rx_pending = i;
5786                         break;
5787                 }
5788         }
5789
5790         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5791                 goto done;
5792
5793         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5794
5795         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5796                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5797                         struct tg3_rx_buffer_desc *rxd;
5798
5799                         rxd = &tpr->rx_jmb[i].std;
5800                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5801                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5802                                 RXD_FLAG_JUMBO;
5803                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5804                                (i << RXD_OPAQUE_INDEX_SHIFT));
5805                 }
5806
5807                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5808                         if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
5809                                              i) < 0) {
5810                                 printk(KERN_WARNING PFX
5811                                        "%s: Using a smaller RX jumbo ring, "
5812                                        "only %d out of %d buffers were "
5813                                        "allocated successfully.\n",
5814                                        tp->dev->name, i, tp->rx_jumbo_pending);
5815                                 if (i == 0)
5816                                         goto initfail;
5817                                 tp->rx_jumbo_pending = i;
5818                                 break;
5819                         }
5820                 }
5821         }
5822
5823 done:
5824         return 0;
5825
5826 initfail:
5827         tg3_rx_prodring_free(tp, tpr);
5828         return -ENOMEM;
5829 }
5830
5831 static void tg3_rx_prodring_fini(struct tg3 *tp,
5832                                  struct tg3_rx_prodring_set *tpr)
5833 {
5834         kfree(tpr->rx_std_buffers);
5835         tpr->rx_std_buffers = NULL;
5836         kfree(tpr->rx_jmb_buffers);
5837         tpr->rx_jmb_buffers = NULL;
5838         if (tpr->rx_std) {
5839                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5840                                     tpr->rx_std, tpr->rx_std_mapping);
5841                 tpr->rx_std = NULL;
5842         }
5843         if (tpr->rx_jmb) {
5844                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5845                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5846                 tpr->rx_jmb = NULL;
5847         }
5848 }
5849
5850 static int tg3_rx_prodring_init(struct tg3 *tp,
5851                                 struct tg3_rx_prodring_set *tpr)
5852 {
5853         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
5854         if (!tpr->rx_std_buffers)
5855                 return -ENOMEM;
5856
5857         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5858                                            &tpr->rx_std_mapping);
5859         if (!tpr->rx_std)
5860                 goto err_out;
5861
5862         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5863                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
5864                                               GFP_KERNEL);
5865                 if (!tpr->rx_jmb_buffers)
5866                         goto err_out;
5867
5868                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5869                                                    TG3_RX_JUMBO_RING_BYTES,
5870                                                    &tpr->rx_jmb_mapping);
5871                 if (!tpr->rx_jmb)
5872                         goto err_out;
5873         }
5874
5875         return 0;
5876
5877 err_out:
5878         tg3_rx_prodring_fini(tp, tpr);
5879         return -ENOMEM;
5880 }
5881
5882 /* Free up pending packets in all rx/tx rings.
5883  *
5884  * The chip has been shut down and the driver detached from
5885  * the networking, so no interrupts or new tx packets will
5886  * end up in the driver.  tp->{tx,}lock is not held and we are not
5887  * in an interrupt context and thus may sleep.
5888  */
5889 static void tg3_free_rings(struct tg3 *tp)
5890 {
5891         int i, j;
5892
5893         for (j = 0; j < tp->irq_cnt; j++) {
5894                 struct tg3_napi *tnapi = &tp->napi[j];
5895
5896                 if (!tnapi->tx_buffers)
5897                         continue;
5898
5899                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5900                         struct tx_ring_info *txp;
5901                         struct sk_buff *skb;
5902
5903                         txp = &tnapi->tx_buffers[i];
5904                         skb = txp->skb;
5905
5906                         if (skb == NULL) {
5907                                 i++;
5908                                 continue;
5909                         }
5910
5911                         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5912
5913                         txp->skb = NULL;
5914
5915                         i += skb_shinfo(skb)->nr_frags + 1;
5916
5917                         dev_kfree_skb_any(skb);
5918                 }
5919
5920                 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
5921                         tg3_rx_prodring_free(tp, &tp->prodring[j]);
5922         }
5923 }
5924
5925 /* Initialize tx/rx rings for packet processing.
5926  *
5927  * The chip has been shut down and the driver detached from
5928  * the networking, so no interrupts or new tx packets will
5929  * end up in the driver.  tp->{tx,}lock are held and thus
5930  * we may not sleep.
5931  */
5932 static int tg3_init_rings(struct tg3 *tp)
5933 {
5934         int i;
5935
5936         /* Free up all the SKBs. */
5937         tg3_free_rings(tp);
5938
5939         for (i = 0; i < tp->irq_cnt; i++) {
5940                 struct tg3_napi *tnapi = &tp->napi[i];
5941
5942                 tnapi->last_tag = 0;
5943                 tnapi->last_irq_tag = 0;
5944                 tnapi->hw_status->status = 0;
5945                 tnapi->hw_status->status_tag = 0;
5946                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5947
5948                 tnapi->tx_prod = 0;
5949                 tnapi->tx_cons = 0;
5950                 if (tnapi->tx_ring)
5951                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5952
5953                 tnapi->rx_rcb_ptr = 0;
5954                 if (tnapi->rx_rcb)
5955                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5956
5957                 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
5958                         tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
5959                         return -ENOMEM;
5960         }
5961
5962         return 0;
5963 }
5964
5965 /*
5966  * Must not be invoked with interrupt sources disabled and
5967  * the hardware shutdown down.
5968  */
5969 static void tg3_free_consistent(struct tg3 *tp)
5970 {
5971         int i;
5972
5973         for (i = 0; i < tp->irq_cnt; i++) {
5974                 struct tg3_napi *tnapi = &tp->napi[i];
5975
5976                 if (tnapi->tx_ring) {
5977                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5978                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
5979                         tnapi->tx_ring = NULL;
5980                 }
5981
5982                 kfree(tnapi->tx_buffers);
5983                 tnapi->tx_buffers = NULL;
5984
5985                 if (tnapi->rx_rcb) {
5986                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5987                                             tnapi->rx_rcb,
5988                                             tnapi->rx_rcb_mapping);
5989                         tnapi->rx_rcb = NULL;
5990                 }
5991
5992                 if (tnapi->hw_status) {
5993                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5994                                             tnapi->hw_status,
5995                                             tnapi->status_mapping);
5996                         tnapi->hw_status = NULL;
5997                 }
5998         }
5999
6000         if (tp->hw_stats) {
6001                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6002                                     tp->hw_stats, tp->stats_mapping);
6003                 tp->hw_stats = NULL;
6004         }
6005
6006         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6007                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6008 }
6009
6010 /*
6011  * Must not be invoked with interrupt sources disabled and
6012  * the hardware shutdown down.  Can sleep.
6013  */
6014 static int tg3_alloc_consistent(struct tg3 *tp)
6015 {
6016         int i;
6017
6018         for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6019                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6020                         goto err_out;
6021         }
6022
6023         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6024                                             sizeof(struct tg3_hw_stats),
6025                                             &tp->stats_mapping);
6026         if (!tp->hw_stats)
6027                 goto err_out;
6028
6029         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6030
6031         for (i = 0; i < tp->irq_cnt; i++) {
6032                 struct tg3_napi *tnapi = &tp->napi[i];
6033                 struct tg3_hw_status *sblk;
6034
6035                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6036                                                         TG3_HW_STATUS_SIZE,
6037                                                         &tnapi->status_mapping);
6038                 if (!tnapi->hw_status)
6039                         goto err_out;
6040
6041                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6042                 sblk = tnapi->hw_status;
6043
6044                 /*
6045                  * When RSS is enabled, the status block format changes
6046                  * slightly.  The "rx_jumbo_consumer", "reserved",
6047                  * and "rx_mini_consumer" members get mapped to the
6048                  * other three rx return ring producer indexes.
6049                  */
6050                 switch (i) {
6051                 default:
6052                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6053                         break;
6054                 case 2:
6055                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6056                         break;
6057                 case 3:
6058                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6059                         break;
6060                 case 4:
6061                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6062                         break;
6063                 }
6064
6065                 /*
6066                  * If multivector RSS is enabled, vector 0 does not handle
6067                  * rx or tx interrupts.  Don't allocate any resources for it.
6068                  */
6069                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6070                         continue;
6071
6072                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6073                                                      TG3_RX_RCB_RING_BYTES(tp),
6074                                                      &tnapi->rx_rcb_mapping);
6075                 if (!tnapi->rx_rcb)
6076                         goto err_out;
6077
6078                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6079
6080                 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
6081                                             TG3_TX_RING_SIZE, GFP_KERNEL);
6082                 if (!tnapi->tx_buffers)
6083                         goto err_out;
6084
6085                 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6086                                                       TG3_TX_RING_BYTES,
6087                                                       &tnapi->tx_desc_mapping);
6088                 if (!tnapi->tx_ring)
6089                         goto err_out;
6090         }
6091
6092         return 0;
6093
6094 err_out:
6095         tg3_free_consistent(tp);
6096         return -ENOMEM;
6097 }
6098
6099 #define MAX_WAIT_CNT 1000
6100
6101 /* To stop a block, clear the enable bit and poll till it
6102  * clears.  tp->lock is held.
6103  */
6104 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6105 {
6106         unsigned int i;
6107         u32 val;
6108
6109         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6110                 switch (ofs) {
6111                 case RCVLSC_MODE:
6112                 case DMAC_MODE:
6113                 case MBFREE_MODE:
6114                 case BUFMGR_MODE:
6115                 case MEMARB_MODE:
6116                         /* We can't enable/disable these bits of the
6117                          * 5705/5750, just say success.
6118                          */
6119                         return 0;
6120
6121                 default:
6122                         break;
6123                 }
6124         }
6125
6126         val = tr32(ofs);
6127         val &= ~enable_bit;
6128         tw32_f(ofs, val);
6129
6130         for (i = 0; i < MAX_WAIT_CNT; i++) {
6131                 udelay(100);
6132                 val = tr32(ofs);
6133                 if ((val & enable_bit) == 0)
6134                         break;
6135         }
6136
6137         if (i == MAX_WAIT_CNT && !silent) {
6138                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6139                        "ofs=%lx enable_bit=%x\n",
6140                        ofs, enable_bit);
6141                 return -ENODEV;
6142         }
6143
6144         return 0;
6145 }
6146
6147 /* tp->lock is held. */
6148 static int tg3_abort_hw(struct tg3 *tp, int silent)
6149 {
6150         int i, err;
6151
6152         tg3_disable_ints(tp);
6153
6154         tp->rx_mode &= ~RX_MODE_ENABLE;
6155         tw32_f(MAC_RX_MODE, tp->rx_mode);
6156         udelay(10);
6157
6158         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6159         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6160         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6161         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6162         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6163         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6164
6165         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6166         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6167         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6168         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6169         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6170         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6171         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6172
6173         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6174         tw32_f(MAC_MODE, tp->mac_mode);
6175         udelay(40);
6176
6177         tp->tx_mode &= ~TX_MODE_ENABLE;
6178         tw32_f(MAC_TX_MODE, tp->tx_mode);
6179
6180         for (i = 0; i < MAX_WAIT_CNT; i++) {
6181                 udelay(100);
6182                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6183                         break;
6184         }
6185         if (i >= MAX_WAIT_CNT) {
6186                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6187                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6188                        tp->dev->name, tr32(MAC_TX_MODE));
6189                 err |= -ENODEV;
6190         }
6191
6192         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6193         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6194         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6195
6196         tw32(FTQ_RESET, 0xffffffff);
6197         tw32(FTQ_RESET, 0x00000000);
6198
6199         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6200         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6201
6202         for (i = 0; i < tp->irq_cnt; i++) {
6203                 struct tg3_napi *tnapi = &tp->napi[i];
6204                 if (tnapi->hw_status)
6205                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6206         }
6207         if (tp->hw_stats)
6208                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6209
6210         return err;
6211 }
6212
6213 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6214 {
6215         int i;
6216         u32 apedata;
6217
6218         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6219         if (apedata != APE_SEG_SIG_MAGIC)
6220                 return;
6221
6222         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6223         if (!(apedata & APE_FW_STATUS_READY))
6224                 return;
6225
6226         /* Wait for up to 1 millisecond for APE to service previous event. */
6227         for (i = 0; i < 10; i++) {
6228                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6229                         return;
6230
6231                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6232
6233                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6234                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6235                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6236
6237                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6238
6239                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6240                         break;
6241
6242                 udelay(100);
6243         }
6244
6245         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6246                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6247 }
6248
6249 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6250 {
6251         u32 event;
6252         u32 apedata;
6253
6254         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6255                 return;
6256
6257         switch (kind) {
6258                 case RESET_KIND_INIT:
6259                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6260                                         APE_HOST_SEG_SIG_MAGIC);
6261                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6262                                         APE_HOST_SEG_LEN_MAGIC);
6263                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6264                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6265                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6266                                         APE_HOST_DRIVER_ID_MAGIC);
6267                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6268                                         APE_HOST_BEHAV_NO_PHYLOCK);
6269
6270                         event = APE_EVENT_STATUS_STATE_START;
6271                         break;
6272                 case RESET_KIND_SHUTDOWN:
6273                         /* With the interface we are currently using,
6274                          * APE does not track driver state.  Wiping
6275                          * out the HOST SEGMENT SIGNATURE forces
6276                          * the APE to assume OS absent status.
6277                          */
6278                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6279
6280                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6281                         break;
6282                 case RESET_KIND_SUSPEND:
6283                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6284                         break;
6285                 default:
6286                         return;
6287         }
6288
6289         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6290
6291         tg3_ape_send_event(tp, event);
6292 }
6293
6294 /* tp->lock is held. */
6295 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6296 {
6297         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6298                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6299
6300         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6301                 switch (kind) {
6302                 case RESET_KIND_INIT:
6303                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6304                                       DRV_STATE_START);
6305                         break;
6306
6307                 case RESET_KIND_SHUTDOWN:
6308                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6309                                       DRV_STATE_UNLOAD);
6310                         break;
6311
6312                 case RESET_KIND_SUSPEND:
6313                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6314                                       DRV_STATE_SUSPEND);
6315                         break;
6316
6317                 default:
6318                         break;
6319                 }
6320         }
6321
6322         if (kind == RESET_KIND_INIT ||
6323             kind == RESET_KIND_SUSPEND)
6324                 tg3_ape_driver_state_change(tp, kind);
6325 }
6326
6327 /* tp->lock is held. */
6328 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6329 {
6330         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6331                 switch (kind) {
6332                 case RESET_KIND_INIT:
6333                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6334                                       DRV_STATE_START_DONE);
6335                         break;
6336
6337                 case RESET_KIND_SHUTDOWN:
6338                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6339                                       DRV_STATE_UNLOAD_DONE);
6340                         break;
6341
6342                 default:
6343                         break;
6344                 }
6345         }
6346
6347         if (kind == RESET_KIND_SHUTDOWN)
6348                 tg3_ape_driver_state_change(tp, kind);
6349 }
6350
6351 /* tp->lock is held. */
6352 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6353 {
6354         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6355                 switch (kind) {
6356                 case RESET_KIND_INIT:
6357                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6358                                       DRV_STATE_START);
6359                         break;
6360
6361                 case RESET_KIND_SHUTDOWN:
6362                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6363                                       DRV_STATE_UNLOAD);
6364                         break;
6365
6366                 case RESET_KIND_SUSPEND:
6367                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6368                                       DRV_STATE_SUSPEND);
6369                         break;
6370
6371                 default:
6372                         break;
6373                 }
6374         }
6375 }
6376
6377 static int tg3_poll_fw(struct tg3 *tp)
6378 {
6379         int i;
6380         u32 val;
6381
6382         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6383                 /* Wait up to 20ms for init done. */
6384                 for (i = 0; i < 200; i++) {
6385                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6386                                 return 0;
6387                         udelay(100);
6388                 }
6389                 return -ENODEV;
6390         }
6391
6392         /* Wait for firmware initialization to complete. */
6393         for (i = 0; i < 100000; i++) {
6394                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6395                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6396                         break;
6397                 udelay(10);
6398         }
6399
6400         /* Chip might not be fitted with firmware.  Some Sun onboard
6401          * parts are configured like that.  So don't signal the timeout
6402          * of the above loop as an error, but do report the lack of
6403          * running firmware once.
6404          */
6405         if (i >= 100000 &&
6406             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6407                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6408
6409                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6410                        tp->dev->name);
6411         }
6412
6413         return 0;
6414 }
6415
6416 /* Save PCI command register before chip reset */
6417 static void tg3_save_pci_state(struct tg3 *tp)
6418 {
6419         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6420 }
6421
6422 /* Restore PCI state after chip reset */
6423 static void tg3_restore_pci_state(struct tg3 *tp)
6424 {
6425         u32 val;
6426
6427         /* Re-enable indirect register accesses. */
6428         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6429                                tp->misc_host_ctrl);
6430
6431         /* Set MAX PCI retry to zero. */
6432         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6433         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6434             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6435                 val |= PCISTATE_RETRY_SAME_DMA;
6436         /* Allow reads and writes to the APE register and memory space. */
6437         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6438                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6439                        PCISTATE_ALLOW_APE_SHMEM_WR;
6440         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6441
6442         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6443
6444         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6445                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6446                         pcie_set_readrq(tp->pdev, 4096);
6447                 else {
6448                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6449                                               tp->pci_cacheline_sz);
6450                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6451                                               tp->pci_lat_timer);
6452                 }
6453         }
6454
6455         /* Make sure PCI-X relaxed ordering bit is clear. */
6456         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6457                 u16 pcix_cmd;
6458
6459                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6460                                      &pcix_cmd);
6461                 pcix_cmd &= ~PCI_X_CMD_ERO;
6462                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6463                                       pcix_cmd);
6464         }
6465
6466         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6467
6468                 /* Chip reset on 5780 will reset MSI enable bit,
6469                  * so need to restore it.
6470                  */
6471                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6472                         u16 ctrl;
6473
6474                         pci_read_config_word(tp->pdev,
6475                                              tp->msi_cap + PCI_MSI_FLAGS,
6476                                              &ctrl);
6477                         pci_write_config_word(tp->pdev,
6478                                               tp->msi_cap + PCI_MSI_FLAGS,
6479                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6480                         val = tr32(MSGINT_MODE);
6481                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6482                 }
6483         }
6484 }
6485
6486 static void tg3_stop_fw(struct tg3 *);
6487
6488 /* tp->lock is held. */
6489 static int tg3_chip_reset(struct tg3 *tp)
6490 {
6491         u32 val;
6492         void (*write_op)(struct tg3 *, u32, u32);
6493         int i, err;
6494
6495         tg3_nvram_lock(tp);
6496
6497         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6498
6499         /* No matching tg3_nvram_unlock() after this because
6500          * chip reset below will undo the nvram lock.
6501          */
6502         tp->nvram_lock_cnt = 0;
6503
6504         /* GRC_MISC_CFG core clock reset will clear the memory
6505          * enable bit in PCI register 4 and the MSI enable bit
6506          * on some chips, so we save relevant registers here.
6507          */
6508         tg3_save_pci_state(tp);
6509
6510         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6511             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6512                 tw32(GRC_FASTBOOT_PC, 0);
6513
6514         /*
6515          * We must avoid the readl() that normally takes place.
6516          * It locks machines, causes machine checks, and other
6517          * fun things.  So, temporarily disable the 5701
6518          * hardware workaround, while we do the reset.
6519          */
6520         write_op = tp->write32;
6521         if (write_op == tg3_write_flush_reg32)
6522                 tp->write32 = tg3_write32;
6523
6524         /* Prevent the irq handler from reading or writing PCI registers
6525          * during chip reset when the memory enable bit in the PCI command
6526          * register may be cleared.  The chip does not generate interrupt
6527          * at this time, but the irq handler may still be called due to irq
6528          * sharing or irqpoll.
6529          */
6530         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6531         for (i = 0; i < tp->irq_cnt; i++) {
6532                 struct tg3_napi *tnapi = &tp->napi[i];
6533                 if (tnapi->hw_status) {
6534                         tnapi->hw_status->status = 0;
6535                         tnapi->hw_status->status_tag = 0;
6536                 }
6537                 tnapi->last_tag = 0;
6538                 tnapi->last_irq_tag = 0;
6539         }
6540         smp_mb();
6541
6542         for (i = 0; i < tp->irq_cnt; i++)
6543                 synchronize_irq(tp->napi[i].irq_vec);
6544
6545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6546                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6547                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6548         }
6549
6550         /* do the reset */
6551         val = GRC_MISC_CFG_CORECLK_RESET;
6552
6553         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6554                 if (tr32(0x7e2c) == 0x60) {
6555                         tw32(0x7e2c, 0x20);
6556                 }
6557                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6558                         tw32(GRC_MISC_CFG, (1 << 29));
6559                         val |= (1 << 29);
6560                 }
6561         }
6562
6563         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6564                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6565                 tw32(GRC_VCPU_EXT_CTRL,
6566                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6567         }
6568
6569         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6570                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6571         tw32(GRC_MISC_CFG, val);
6572
6573         /* restore 5701 hardware bug workaround write method */
6574         tp->write32 = write_op;
6575
6576         /* Unfortunately, we have to delay before the PCI read back.
6577          * Some 575X chips even will not respond to a PCI cfg access
6578          * when the reset command is given to the chip.
6579          *
6580          * How do these hardware designers expect things to work
6581          * properly if the PCI write is posted for a long period
6582          * of time?  It is always necessary to have some method by
6583          * which a register read back can occur to push the write
6584          * out which does the reset.
6585          *
6586          * For most tg3 variants the trick below was working.
6587          * Ho hum...
6588          */
6589         udelay(120);
6590
6591         /* Flush PCI posted writes.  The normal MMIO registers
6592          * are inaccessible at this time so this is the only
6593          * way to make this reliably (actually, this is no longer
6594          * the case, see above).  I tried to use indirect
6595          * register read/write but this upset some 5701 variants.
6596          */
6597         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6598
6599         udelay(120);
6600
6601         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6602                 u16 val16;
6603
6604                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6605                         int i;
6606                         u32 cfg_val;
6607
6608                         /* Wait for link training to complete.  */
6609                         for (i = 0; i < 5000; i++)
6610                                 udelay(100);
6611
6612                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6613                         pci_write_config_dword(tp->pdev, 0xc4,
6614                                                cfg_val | (1 << 15));
6615                 }
6616
6617                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6618                 pci_read_config_word(tp->pdev,
6619                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6620                                      &val16);
6621                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6622                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6623                 /*
6624                  * Older PCIe devices only support the 128 byte
6625                  * MPS setting.  Enforce the restriction.
6626                  */
6627                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6628                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6629                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6630                 pci_write_config_word(tp->pdev,
6631                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6632                                       val16);
6633
6634                 pcie_set_readrq(tp->pdev, 4096);
6635
6636                 /* Clear error status */
6637                 pci_write_config_word(tp->pdev,
6638                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6639                                       PCI_EXP_DEVSTA_CED |
6640                                       PCI_EXP_DEVSTA_NFED |
6641                                       PCI_EXP_DEVSTA_FED |
6642                                       PCI_EXP_DEVSTA_URD);
6643         }
6644
6645         tg3_restore_pci_state(tp);
6646
6647         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6648
6649         val = 0;
6650         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6651                 val = tr32(MEMARB_MODE);
6652         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6653
6654         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6655                 tg3_stop_fw(tp);
6656                 tw32(0x5000, 0x400);
6657         }
6658
6659         tw32(GRC_MODE, tp->grc_mode);
6660
6661         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6662                 val = tr32(0xc4);
6663
6664                 tw32(0xc4, val | (1 << 15));
6665         }
6666
6667         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6668             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6669                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6670                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6671                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6672                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6673         }
6674
6675         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6676                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6677                 tw32_f(MAC_MODE, tp->mac_mode);
6678         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6679                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6680                 tw32_f(MAC_MODE, tp->mac_mode);
6681         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6682                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6683                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6684                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6685                 tw32_f(MAC_MODE, tp->mac_mode);
6686         } else
6687                 tw32_f(MAC_MODE, 0);
6688         udelay(40);
6689
6690         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6691
6692         err = tg3_poll_fw(tp);
6693         if (err)
6694                 return err;
6695
6696         tg3_mdio_start(tp);
6697
6698         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6699                 u8 phy_addr;
6700
6701                 phy_addr = tp->phy_addr;
6702                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6703
6704                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6705                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6706                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6707                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6708                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
6709                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6710                 udelay(10);
6711
6712                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6713                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6714                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6715                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6716                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6717                 udelay(10);
6718
6719                 tp->phy_addr = phy_addr;
6720         }
6721
6722         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6723             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6724             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6725             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6726                 val = tr32(0x7c00);
6727
6728                 tw32(0x7c00, val | (1 << 25));
6729         }
6730
6731         /* Reprobe ASF enable state.  */
6732         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6733         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6734         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6735         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6736                 u32 nic_cfg;
6737
6738                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6739                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6740                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6741                         tp->last_event_jiffies = jiffies;
6742                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6743                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6744                 }
6745         }
6746
6747         return 0;
6748 }
6749
6750 /* tp->lock is held. */
6751 static void tg3_stop_fw(struct tg3 *tp)
6752 {
6753         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6754            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6755                 /* Wait for RX cpu to ACK the previous event. */
6756                 tg3_wait_for_event_ack(tp);
6757
6758                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6759
6760                 tg3_generate_fw_event(tp);
6761
6762                 /* Wait for RX cpu to ACK this event. */
6763                 tg3_wait_for_event_ack(tp);
6764         }
6765 }
6766
6767 /* tp->lock is held. */
6768 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6769 {
6770         int err;
6771
6772         tg3_stop_fw(tp);
6773
6774         tg3_write_sig_pre_reset(tp, kind);
6775
6776         tg3_abort_hw(tp, silent);
6777         err = tg3_chip_reset(tp);
6778
6779         __tg3_set_mac_addr(tp, 0);
6780
6781         tg3_write_sig_legacy(tp, kind);
6782         tg3_write_sig_post_reset(tp, kind);
6783
6784         if (err)
6785                 return err;
6786
6787         return 0;
6788 }
6789
6790 #define RX_CPU_SCRATCH_BASE     0x30000
6791 #define RX_CPU_SCRATCH_SIZE     0x04000
6792 #define TX_CPU_SCRATCH_BASE     0x34000
6793 #define TX_CPU_SCRATCH_SIZE     0x04000
6794
6795 /* tp->lock is held. */
6796 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6797 {
6798         int i;
6799
6800         BUG_ON(offset == TX_CPU_BASE &&
6801             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6802
6803         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6804                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6805
6806                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6807                 return 0;
6808         }
6809         if (offset == RX_CPU_BASE) {
6810                 for (i = 0; i < 10000; i++) {
6811                         tw32(offset + CPU_STATE, 0xffffffff);
6812                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6813                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6814                                 break;
6815                 }
6816
6817                 tw32(offset + CPU_STATE, 0xffffffff);
6818                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6819                 udelay(10);
6820         } else {
6821                 for (i = 0; i < 10000; i++) {
6822                         tw32(offset + CPU_STATE, 0xffffffff);
6823                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6824                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6825                                 break;
6826                 }
6827         }
6828
6829         if (i >= 10000) {
6830                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6831                        "and %s CPU\n",
6832                        tp->dev->name,
6833                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6834                 return -ENODEV;
6835         }
6836
6837         /* Clear firmware's nvram arbitration. */
6838         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6839                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6840         return 0;
6841 }
6842
6843 struct fw_info {
6844         unsigned int fw_base;
6845         unsigned int fw_len;
6846         const __be32 *fw_data;
6847 };
6848
6849 /* tp->lock is held. */
6850 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6851                                  int cpu_scratch_size, struct fw_info *info)
6852 {
6853         int err, lock_err, i;
6854         void (*write_op)(struct tg3 *, u32, u32);
6855
6856         if (cpu_base == TX_CPU_BASE &&
6857             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6858                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6859                        "TX cpu firmware on %s which is 5705.\n",
6860                        tp->dev->name);
6861                 return -EINVAL;
6862         }
6863
6864         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6865                 write_op = tg3_write_mem;
6866         else
6867                 write_op = tg3_write_indirect_reg32;
6868
6869         /* It is possible that bootcode is still loading at this point.
6870          * Get the nvram lock first before halting the cpu.
6871          */
6872         lock_err = tg3_nvram_lock(tp);
6873         err = tg3_halt_cpu(tp, cpu_base);
6874         if (!lock_err)
6875                 tg3_nvram_unlock(tp);
6876         if (err)
6877                 goto out;
6878
6879         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6880                 write_op(tp, cpu_scratch_base + i, 0);
6881         tw32(cpu_base + CPU_STATE, 0xffffffff);
6882         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6883         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6884                 write_op(tp, (cpu_scratch_base +
6885                               (info->fw_base & 0xffff) +
6886                               (i * sizeof(u32))),
6887                               be32_to_cpu(info->fw_data[i]));
6888
6889         err = 0;
6890
6891 out:
6892         return err;
6893 }
6894
6895 /* tp->lock is held. */
6896 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6897 {
6898         struct fw_info info;
6899         const __be32 *fw_data;
6900         int err, i;
6901
6902         fw_data = (void *)tp->fw->data;
6903
6904         /* Firmware blob starts with version numbers, followed by
6905            start address and length. We are setting complete length.
6906            length = end_address_of_bss - start_address_of_text.
6907            Remainder is the blob to be loaded contiguously
6908            from start address. */
6909
6910         info.fw_base = be32_to_cpu(fw_data[1]);
6911         info.fw_len = tp->fw->size - 12;
6912         info.fw_data = &fw_data[3];
6913
6914         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6915                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6916                                     &info);
6917         if (err)
6918                 return err;
6919
6920         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6921                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6922                                     &info);
6923         if (err)
6924                 return err;
6925
6926         /* Now startup only the RX cpu. */
6927         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6928         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6929
6930         for (i = 0; i < 5; i++) {
6931                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6932                         break;
6933                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6934                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6935                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6936                 udelay(1000);
6937         }
6938         if (i >= 5) {
6939                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6940                        "to set RX CPU PC, is %08x should be %08x\n",
6941                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6942                        info.fw_base);
6943                 return -ENODEV;
6944         }
6945         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6946         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6947
6948         return 0;
6949 }
6950
6951 /* 5705 needs a special version of the TSO firmware.  */
6952
6953 /* tp->lock is held. */
6954 static int tg3_load_tso_firmware(struct tg3 *tp)
6955 {
6956         struct fw_info info;
6957         const __be32 *fw_data;
6958         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6959         int err, i;
6960
6961         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6962                 return 0;
6963
6964         fw_data = (void *)tp->fw->data;
6965
6966         /* Firmware blob starts with version numbers, followed by
6967            start address and length. We are setting complete length.
6968            length = end_address_of_bss - start_address_of_text.
6969            Remainder is the blob to be loaded contiguously
6970            from start address. */
6971
6972         info.fw_base = be32_to_cpu(fw_data[1]);
6973         cpu_scratch_size = tp->fw_len;
6974         info.fw_len = tp->fw->size - 12;
6975         info.fw_data = &fw_data[3];
6976
6977         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6978                 cpu_base = RX_CPU_BASE;
6979                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6980         } else {
6981                 cpu_base = TX_CPU_BASE;
6982                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6983                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6984         }
6985
6986         err = tg3_load_firmware_cpu(tp, cpu_base,
6987                                     cpu_scratch_base, cpu_scratch_size,
6988                                     &info);
6989         if (err)
6990                 return err;
6991
6992         /* Now startup the cpu. */
6993         tw32(cpu_base + CPU_STATE, 0xffffffff);
6994         tw32_f(cpu_base + CPU_PC, info.fw_base);
6995
6996         for (i = 0; i < 5; i++) {
6997                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6998                         break;
6999                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7000                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7001                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7002                 udelay(1000);
7003         }
7004         if (i >= 5) {
7005                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7006                        "to set CPU PC, is %08x should be %08x\n",
7007                        tp->dev->name, tr32(cpu_base + CPU_PC),
7008                        info.fw_base);
7009                 return -ENODEV;
7010         }
7011         tw32(cpu_base + CPU_STATE, 0xffffffff);
7012         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7013         return 0;
7014 }
7015
7016
7017 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7018 {
7019         struct tg3 *tp = netdev_priv(dev);
7020         struct sockaddr *addr = p;
7021         int err = 0, skip_mac_1 = 0;
7022
7023         if (!is_valid_ether_addr(addr->sa_data))
7024                 return -EINVAL;
7025
7026         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7027
7028         if (!netif_running(dev))
7029                 return 0;
7030
7031         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7032                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7033
7034                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7035                 addr0_low = tr32(MAC_ADDR_0_LOW);
7036                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7037                 addr1_low = tr32(MAC_ADDR_1_LOW);
7038
7039                 /* Skip MAC addr 1 if ASF is using it. */
7040                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7041                     !(addr1_high == 0 && addr1_low == 0))
7042                         skip_mac_1 = 1;
7043         }
7044         spin_lock_bh(&tp->lock);
7045         __tg3_set_mac_addr(tp, skip_mac_1);
7046         spin_unlock_bh(&tp->lock);
7047
7048         return err;
7049 }
7050
7051 /* tp->lock is held. */
7052 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7053                            dma_addr_t mapping, u32 maxlen_flags,
7054                            u32 nic_addr)
7055 {
7056         tg3_write_mem(tp,
7057                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7058                       ((u64) mapping >> 32));
7059         tg3_write_mem(tp,
7060                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7061                       ((u64) mapping & 0xffffffff));
7062         tg3_write_mem(tp,
7063                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7064                        maxlen_flags);
7065
7066         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7067                 tg3_write_mem(tp,
7068                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7069                               nic_addr);
7070 }
7071
7072 static void __tg3_set_rx_mode(struct net_device *);
7073 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7074 {
7075         int i;
7076
7077         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7078                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7079                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7080                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7081
7082                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7083                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7084                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7085         } else {
7086                 tw32(HOSTCC_TXCOL_TICKS, 0);
7087                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7088                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7089
7090                 tw32(HOSTCC_RXCOL_TICKS, 0);
7091                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7092                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7093         }
7094
7095         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7096                 u32 val = ec->stats_block_coalesce_usecs;
7097
7098                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7099                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7100
7101                 if (!netif_carrier_ok(tp->dev))
7102                         val = 0;
7103
7104                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7105         }
7106
7107         for (i = 0; i < tp->irq_cnt - 1; i++) {
7108                 u32 reg;
7109
7110                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7111                 tw32(reg, ec->rx_coalesce_usecs);
7112                 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7113                 tw32(reg, ec->tx_coalesce_usecs);
7114                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7115                 tw32(reg, ec->rx_max_coalesced_frames);
7116                 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7117                 tw32(reg, ec->tx_max_coalesced_frames);
7118                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7119                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7120                 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7121                 tw32(reg, ec->tx_max_coalesced_frames_irq);
7122         }
7123
7124         for (; i < tp->irq_max - 1; i++) {
7125                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7126                 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7127                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7128                 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7129                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7130                 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7131         }
7132 }
7133
7134 /* tp->lock is held. */
7135 static void tg3_rings_reset(struct tg3 *tp)
7136 {
7137         int i;
7138         u32 stblk, txrcb, rxrcb, limit;
7139         struct tg3_napi *tnapi = &tp->napi[0];
7140
7141         /* Disable all transmit rings but the first. */
7142         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7143                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7144         else
7145                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7146
7147         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7148              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7149                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7150                               BDINFO_FLAGS_DISABLED);
7151
7152
7153         /* Disable all receive return rings but the first. */
7154         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7155                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7156         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7157                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7158         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7159                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7160         else
7161                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7162
7163         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7164              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7165                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7166                               BDINFO_FLAGS_DISABLED);
7167
7168         /* Disable interrupts */
7169         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7170
7171         /* Zero mailbox registers. */
7172         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7173                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7174                         tp->napi[i].tx_prod = 0;
7175                         tp->napi[i].tx_cons = 0;
7176                         tw32_mailbox(tp->napi[i].prodmbox, 0);
7177                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7178                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7179                 }
7180         } else {
7181                 tp->napi[0].tx_prod = 0;
7182                 tp->napi[0].tx_cons = 0;
7183                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7184                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7185         }
7186
7187         /* Make sure the NIC-based send BD rings are disabled. */
7188         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7189                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7190                 for (i = 0; i < 16; i++)
7191                         tw32_tx_mbox(mbox + i * 8, 0);
7192         }
7193
7194         txrcb = NIC_SRAM_SEND_RCB;
7195         rxrcb = NIC_SRAM_RCV_RET_RCB;
7196
7197         /* Clear status block in ram. */
7198         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7199
7200         /* Set status block DMA address */
7201         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7202              ((u64) tnapi->status_mapping >> 32));
7203         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7204              ((u64) tnapi->status_mapping & 0xffffffff));
7205
7206         if (tnapi->tx_ring) {
7207                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7208                                (TG3_TX_RING_SIZE <<
7209                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7210                                NIC_SRAM_TX_BUFFER_DESC);
7211                 txrcb += TG3_BDINFO_SIZE;
7212         }
7213
7214         if (tnapi->rx_rcb) {
7215                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7216                                (TG3_RX_RCB_RING_SIZE(tp) <<
7217                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7218                 rxrcb += TG3_BDINFO_SIZE;
7219         }
7220
7221         stblk = HOSTCC_STATBLCK_RING1;
7222
7223         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7224                 u64 mapping = (u64)tnapi->status_mapping;
7225                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7226                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7227
7228                 /* Clear status block in ram. */
7229                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7230
7231                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7232                                (TG3_TX_RING_SIZE <<
7233                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7234                                NIC_SRAM_TX_BUFFER_DESC);
7235
7236                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7237                                (TG3_RX_RCB_RING_SIZE(tp) <<
7238                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7239
7240                 stblk += 8;
7241                 txrcb += TG3_BDINFO_SIZE;
7242                 rxrcb += TG3_BDINFO_SIZE;
7243         }
7244 }
7245
7246 /* tp->lock is held. */
7247 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7248 {
7249         u32 val, rdmac_mode;
7250         int i, err, limit;
7251         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7252
7253         tg3_disable_ints(tp);
7254
7255         tg3_stop_fw(tp);
7256
7257         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7258
7259         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7260                 tg3_abort_hw(tp, 1);
7261         }
7262
7263         if (reset_phy &&
7264             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7265                 tg3_phy_reset(tp);
7266
7267         err = tg3_chip_reset(tp);
7268         if (err)
7269                 return err;
7270
7271         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7272
7273         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7274                 val = tr32(TG3_CPMU_CTRL);
7275                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7276                 tw32(TG3_CPMU_CTRL, val);
7277
7278                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7279                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7280                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7281                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7282
7283                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7284                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7285                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7286                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7287
7288                 val = tr32(TG3_CPMU_HST_ACC);
7289                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7290                 val |= CPMU_HST_ACC_MACCLK_6_25;
7291                 tw32(TG3_CPMU_HST_ACC, val);
7292         }
7293
7294         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7295                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7296                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7297                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7298                 tw32(PCIE_PWR_MGMT_THRESH, val);
7299
7300                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7301                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7302
7303                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7304
7305                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7306                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7307         }
7308
7309         /* This works around an issue with Athlon chipsets on
7310          * B3 tigon3 silicon.  This bit has no effect on any
7311          * other revision.  But do not set this on PCI Express
7312          * chips and don't even touch the clocks if the CPMU is present.
7313          */
7314         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7315                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7316                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7317                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7318         }
7319
7320         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7321             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7322                 val = tr32(TG3PCI_PCISTATE);
7323                 val |= PCISTATE_RETRY_SAME_DMA;
7324                 tw32(TG3PCI_PCISTATE, val);
7325         }
7326
7327         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7328                 /* Allow reads and writes to the
7329                  * APE register and memory space.
7330                  */
7331                 val = tr32(TG3PCI_PCISTATE);
7332                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7333                        PCISTATE_ALLOW_APE_SHMEM_WR;
7334                 tw32(TG3PCI_PCISTATE, val);
7335         }
7336
7337         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7338                 /* Enable some hw fixes.  */
7339                 val = tr32(TG3PCI_MSI_DATA);
7340                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7341                 tw32(TG3PCI_MSI_DATA, val);
7342         }
7343
7344         /* Descriptor ring init may make accesses to the
7345          * NIC SRAM area to setup the TX descriptors, so we
7346          * can only do this after the hardware has been
7347          * successfully reset.
7348          */
7349         err = tg3_init_rings(tp);
7350         if (err)
7351                 return err;
7352
7353         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7354                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7355                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7356                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7357         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7358                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7359                 /* This value is determined during the probe time DMA
7360                  * engine test, tg3_test_dma.
7361                  */
7362                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7363         }
7364
7365         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7366                           GRC_MODE_4X_NIC_SEND_RINGS |
7367                           GRC_MODE_NO_TX_PHDR_CSUM |
7368                           GRC_MODE_NO_RX_PHDR_CSUM);
7369         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7370
7371         /* Pseudo-header checksum is done by hardware logic and not
7372          * the offload processers, so make the chip do the pseudo-
7373          * header checksums on receive.  For transmit it is more
7374          * convenient to do the pseudo-header checksum in software
7375          * as Linux does that on transmit for us in all cases.
7376          */
7377         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7378
7379         tw32(GRC_MODE,
7380              tp->grc_mode |
7381              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7382
7383         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7384         val = tr32(GRC_MISC_CFG);
7385         val &= ~0xff;
7386         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7387         tw32(GRC_MISC_CFG, val);
7388
7389         /* Initialize MBUF/DESC pool. */
7390         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7391                 /* Do nothing.  */
7392         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7393                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7394                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7395                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7396                 else
7397                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7398                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7399                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7400         }
7401         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7402                 int fw_len;
7403
7404                 fw_len = tp->fw_len;
7405                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7406                 tw32(BUFMGR_MB_POOL_ADDR,
7407                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7408                 tw32(BUFMGR_MB_POOL_SIZE,
7409                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7410         }
7411
7412         if (tp->dev->mtu <= ETH_DATA_LEN) {
7413                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7414                      tp->bufmgr_config.mbuf_read_dma_low_water);
7415                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7416                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7417                 tw32(BUFMGR_MB_HIGH_WATER,
7418                      tp->bufmgr_config.mbuf_high_water);
7419         } else {
7420                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7421                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7422                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7423                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7424                 tw32(BUFMGR_MB_HIGH_WATER,
7425                      tp->bufmgr_config.mbuf_high_water_jumbo);
7426         }
7427         tw32(BUFMGR_DMA_LOW_WATER,
7428              tp->bufmgr_config.dma_low_water);
7429         tw32(BUFMGR_DMA_HIGH_WATER,
7430              tp->bufmgr_config.dma_high_water);
7431
7432         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7433         for (i = 0; i < 2000; i++) {
7434                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7435                         break;
7436                 udelay(10);
7437         }
7438         if (i >= 2000) {
7439                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7440                        tp->dev->name);
7441                 return -ENODEV;
7442         }
7443
7444         /* Setup replenish threshold. */
7445         val = tp->rx_pending / 8;
7446         if (val == 0)
7447                 val = 1;
7448         else if (val > tp->rx_std_max_post)
7449                 val = tp->rx_std_max_post;
7450         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7451                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7452                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7453
7454                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7455                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7456         }
7457
7458         tw32(RCVBDI_STD_THRESH, val);
7459
7460         /* Initialize TG3_BDINFO's at:
7461          *  RCVDBDI_STD_BD:     standard eth size rx ring
7462          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7463          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7464          *
7465          * like so:
7466          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7467          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7468          *                              ring attribute flags
7469          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7470          *
7471          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7472          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7473          *
7474          * The size of each ring is fixed in the firmware, but the location is
7475          * configurable.
7476          */
7477         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7478              ((u64) tpr->rx_std_mapping >> 32));
7479         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7480              ((u64) tpr->rx_std_mapping & 0xffffffff));
7481         if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7482                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7483                      NIC_SRAM_RX_BUFFER_DESC);
7484
7485         /* Disable the mini ring */
7486         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7487                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7488                      BDINFO_FLAGS_DISABLED);
7489
7490         /* Program the jumbo buffer descriptor ring control
7491          * blocks on those devices that have them.
7492          */
7493         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7494             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7495                 /* Setup replenish threshold. */
7496                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7497
7498                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7499                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7500                              ((u64) tpr->rx_jmb_mapping >> 32));
7501                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7502                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7503                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7504                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7505                              BDINFO_FLAGS_USE_EXT_RECV);
7506                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7507                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7508                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7509                 } else {
7510                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7511                              BDINFO_FLAGS_DISABLED);
7512                 }
7513
7514                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7515                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7516                               (RX_STD_MAX_SIZE << 2);
7517                 else
7518                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7519         } else
7520                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7521
7522         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7523
7524         tpr->rx_std_prod_idx = tp->rx_pending;
7525         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7526
7527         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7528                           tp->rx_jumbo_pending : 0;
7529         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7530
7531         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7532                 tw32(STD_REPLENISH_LWM, 32);
7533                 tw32(JMB_REPLENISH_LWM, 16);
7534         }
7535
7536         tg3_rings_reset(tp);
7537
7538         /* Initialize MAC address and backoff seed. */
7539         __tg3_set_mac_addr(tp, 0);
7540
7541         /* MTU + ethernet header + FCS + optional VLAN tag */
7542         tw32(MAC_RX_MTU_SIZE,
7543              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7544
7545         /* The slot time is changed by tg3_setup_phy if we
7546          * run at gigabit with half duplex.
7547          */
7548         tw32(MAC_TX_LENGTHS,
7549              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7550              (6 << TX_LENGTHS_IPG_SHIFT) |
7551              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7552
7553         /* Receive rules. */
7554         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7555         tw32(RCVLPC_CONFIG, 0x0181);
7556
7557         /* Calculate RDMAC_MODE setting early, we need it to determine
7558          * the RCVLPC_STATE_ENABLE mask.
7559          */
7560         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7561                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7562                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7563                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7564                       RDMAC_MODE_LNGREAD_ENAB);
7565
7566         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7568             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7569                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7570                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7571                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7572
7573         /* If statement applies to 5705 and 5750 PCI devices only */
7574         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7575              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7576             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7577                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7578                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7579                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7580                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7581                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7582                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7583                 }
7584         }
7585
7586         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7587                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7588
7589         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7590                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7591
7592         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7593             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7594             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7595                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7596
7597         /* Receive/send statistics. */
7598         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7599                 val = tr32(RCVLPC_STATS_ENABLE);
7600                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7601                 tw32(RCVLPC_STATS_ENABLE, val);
7602         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7603                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7604                 val = tr32(RCVLPC_STATS_ENABLE);
7605                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7606                 tw32(RCVLPC_STATS_ENABLE, val);
7607         } else {
7608                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7609         }
7610         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7611         tw32(SNDDATAI_STATSENAB, 0xffffff);
7612         tw32(SNDDATAI_STATSCTRL,
7613              (SNDDATAI_SCTRL_ENABLE |
7614               SNDDATAI_SCTRL_FASTUPD));
7615
7616         /* Setup host coalescing engine. */
7617         tw32(HOSTCC_MODE, 0);
7618         for (i = 0; i < 2000; i++) {
7619                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7620                         break;
7621                 udelay(10);
7622         }
7623
7624         __tg3_set_coalesce(tp, &tp->coal);
7625
7626         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7627                 /* Status/statistics block address.  See tg3_timer,
7628                  * the tg3_periodic_fetch_stats call there, and
7629                  * tg3_get_stats to see how this works for 5705/5750 chips.
7630                  */
7631                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7632                      ((u64) tp->stats_mapping >> 32));
7633                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7634                      ((u64) tp->stats_mapping & 0xffffffff));
7635                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7636
7637                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7638
7639                 /* Clear statistics and status block memory areas */
7640                 for (i = NIC_SRAM_STATS_BLK;
7641                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7642                      i += sizeof(u32)) {
7643                         tg3_write_mem(tp, i, 0);
7644                         udelay(40);
7645                 }
7646         }
7647
7648         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7649
7650         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7651         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7652         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7653                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7654
7655         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7656                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7657                 /* reset to prevent losing 1st rx packet intermittently */
7658                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7659                 udelay(10);
7660         }
7661
7662         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7663                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7664         else
7665                 tp->mac_mode = 0;
7666         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7667                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7668         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7669             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7670             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7671                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7672         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7673         udelay(40);
7674
7675         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7676          * If TG3_FLG2_IS_NIC is zero, we should read the
7677          * register to preserve the GPIO settings for LOMs. The GPIOs,
7678          * whether used as inputs or outputs, are set by boot code after
7679          * reset.
7680          */
7681         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7682                 u32 gpio_mask;
7683
7684                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7685                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7686                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7687
7688                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7689                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7690                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7691
7692                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7693                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7694
7695                 tp->grc_local_ctrl &= ~gpio_mask;
7696                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7697
7698                 /* GPIO1 must be driven high for eeprom write protect */
7699                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7700                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7701                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7702         }
7703         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7704         udelay(100);
7705
7706         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7707                 val = tr32(MSGINT_MODE);
7708                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7709                 tw32(MSGINT_MODE, val);
7710         }
7711
7712         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7713                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7714                 udelay(40);
7715         }
7716
7717         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7718                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7719                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7720                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7721                WDMAC_MODE_LNGREAD_ENAB);
7722
7723         /* If statement applies to 5705 and 5750 PCI devices only */
7724         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7725              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7726             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7727                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7728                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7729                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7730                         /* nothing */
7731                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7732                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7733                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7734                         val |= WDMAC_MODE_RX_ACCEL;
7735                 }
7736         }
7737
7738         /* Enable host coalescing bug fix */
7739         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7740                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7741
7742         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7743                 val |= WDMAC_MODE_BURST_ALL_DATA;
7744
7745         tw32_f(WDMAC_MODE, val);
7746         udelay(40);
7747
7748         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7749                 u16 pcix_cmd;
7750
7751                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7752                                      &pcix_cmd);
7753                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7754                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7755                         pcix_cmd |= PCI_X_CMD_READ_2K;
7756                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7757                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7758                         pcix_cmd |= PCI_X_CMD_READ_2K;
7759                 }
7760                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7761                                       pcix_cmd);
7762         }
7763
7764         tw32_f(RDMAC_MODE, rdmac_mode);
7765         udelay(40);
7766
7767         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7768         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7769                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7770
7771         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7772                 tw32(SNDDATAC_MODE,
7773                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7774         else
7775                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7776
7777         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7778         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7779         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7780         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7781         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7782                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7783         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7784         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7785                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7786         tw32(SNDBDI_MODE, val);
7787         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7788
7789         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7790                 err = tg3_load_5701_a0_firmware_fix(tp);
7791                 if (err)
7792                         return err;
7793         }
7794
7795         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7796                 err = tg3_load_tso_firmware(tp);
7797                 if (err)
7798                         return err;
7799         }
7800
7801         tp->tx_mode = TX_MODE_ENABLE;
7802         tw32_f(MAC_TX_MODE, tp->tx_mode);
7803         udelay(100);
7804
7805         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7806                 u32 reg = MAC_RSS_INDIR_TBL_0;
7807                 u8 *ent = (u8 *)&val;
7808
7809                 /* Setup the indirection table */
7810                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7811                         int idx = i % sizeof(val);
7812
7813                         ent[idx] = i % (tp->irq_cnt - 1);
7814                         if (idx == sizeof(val) - 1) {
7815                                 tw32(reg, val);
7816                                 reg += 4;
7817                         }
7818                 }
7819
7820                 /* Setup the "secret" hash key. */
7821                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7822                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7823                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7824                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7825                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7826                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7827                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7828                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7829                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7830                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7831         }
7832
7833         tp->rx_mode = RX_MODE_ENABLE;
7834         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7835                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7836
7837         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7838                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7839                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
7840                                RX_MODE_RSS_IPV6_HASH_EN |
7841                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
7842                                RX_MODE_RSS_IPV4_HASH_EN |
7843                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
7844
7845         tw32_f(MAC_RX_MODE, tp->rx_mode);
7846         udelay(10);
7847
7848         tw32(MAC_LED_CTRL, tp->led_ctrl);
7849
7850         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7851         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7852                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7853                 udelay(10);
7854         }
7855         tw32_f(MAC_RX_MODE, tp->rx_mode);
7856         udelay(10);
7857
7858         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7859                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7860                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7861                         /* Set drive transmission level to 1.2V  */
7862                         /* only if the signal pre-emphasis bit is not set  */
7863                         val = tr32(MAC_SERDES_CFG);
7864                         val &= 0xfffff000;
7865                         val |= 0x880;
7866                         tw32(MAC_SERDES_CFG, val);
7867                 }
7868                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7869                         tw32(MAC_SERDES_CFG, 0x616000);
7870         }
7871
7872         /* Prevent chip from dropping frames when flow control
7873          * is enabled.
7874          */
7875         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7876
7877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7878             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7879                 /* Use hardware link auto-negotiation */
7880                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7881         }
7882
7883         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7884             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7885                 u32 tmp;
7886
7887                 tmp = tr32(SERDES_RX_CTRL);
7888                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7889                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7890                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7891                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7892         }
7893
7894         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7895                 if (tp->link_config.phy_is_low_power) {
7896                         tp->link_config.phy_is_low_power = 0;
7897                         tp->link_config.speed = tp->link_config.orig_speed;
7898                         tp->link_config.duplex = tp->link_config.orig_duplex;
7899                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7900                 }
7901
7902                 err = tg3_setup_phy(tp, 0);
7903                 if (err)
7904                         return err;
7905
7906                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7907                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7908                         u32 tmp;
7909
7910                         /* Clear CRC stats. */
7911                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7912                                 tg3_writephy(tp, MII_TG3_TEST1,
7913                                              tmp | MII_TG3_TEST1_CRC_EN);
7914                                 tg3_readphy(tp, 0x14, &tmp);
7915                         }
7916                 }
7917         }
7918
7919         __tg3_set_rx_mode(tp->dev);
7920
7921         /* Initialize receive rules. */
7922         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7923         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7924         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7925         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7926
7927         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7928             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7929                 limit = 8;
7930         else
7931                 limit = 16;
7932         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7933                 limit -= 4;
7934         switch (limit) {
7935         case 16:
7936                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7937         case 15:
7938                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7939         case 14:
7940                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7941         case 13:
7942                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7943         case 12:
7944                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7945         case 11:
7946                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7947         case 10:
7948                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7949         case 9:
7950                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7951         case 8:
7952                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7953         case 7:
7954                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7955         case 6:
7956                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7957         case 5:
7958                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7959         case 4:
7960                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7961         case 3:
7962                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7963         case 2:
7964         case 1:
7965
7966         default:
7967                 break;
7968         }
7969
7970         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7971                 /* Write our heartbeat update interval to APE. */
7972                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7973                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7974
7975         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7976
7977         return 0;
7978 }
7979
7980 /* Called at device open time to get the chip ready for
7981  * packet processing.  Invoked with tp->lock held.
7982  */
7983 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7984 {
7985         tg3_switch_clocks(tp);
7986
7987         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7988
7989         return tg3_reset_hw(tp, reset_phy);
7990 }
7991
7992 #define TG3_STAT_ADD32(PSTAT, REG) \
7993 do {    u32 __val = tr32(REG); \
7994         (PSTAT)->low += __val; \
7995         if ((PSTAT)->low < __val) \
7996                 (PSTAT)->high += 1; \
7997 } while (0)
7998
7999 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8000 {
8001         struct tg3_hw_stats *sp = tp->hw_stats;
8002
8003         if (!netif_carrier_ok(tp->dev))
8004                 return;
8005
8006         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8007         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8008         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8009         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8010         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8011         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8012         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8013         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8014         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8015         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8016         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8017         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8018         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8019
8020         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8021         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8022         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8023         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8024         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8025         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8026         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8027         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8028         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8029         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8030         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8031         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8032         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8033         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8034
8035         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8036         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8037         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8038 }
8039
8040 static void tg3_timer(unsigned long __opaque)
8041 {
8042         struct tg3 *tp = (struct tg3 *) __opaque;
8043
8044         if (tp->irq_sync)
8045                 goto restart_timer;
8046
8047         spin_lock(&tp->lock);
8048
8049         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8050                 /* All of this garbage is because when using non-tagged
8051                  * IRQ status the mailbox/status_block protocol the chip
8052                  * uses with the cpu is race prone.
8053                  */
8054                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8055                         tw32(GRC_LOCAL_CTRL,
8056                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8057                 } else {
8058                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8059                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8060                 }
8061
8062                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8063                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8064                         spin_unlock(&tp->lock);
8065                         schedule_work(&tp->reset_task);
8066                         return;
8067                 }
8068         }
8069
8070         /* This part only runs once per second. */
8071         if (!--tp->timer_counter) {
8072                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8073                         tg3_periodic_fetch_stats(tp);
8074
8075                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8076                         u32 mac_stat;
8077                         int phy_event;
8078
8079                         mac_stat = tr32(MAC_STATUS);
8080
8081                         phy_event = 0;
8082                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8083                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8084                                         phy_event = 1;
8085                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8086                                 phy_event = 1;
8087
8088                         if (phy_event)
8089                                 tg3_setup_phy(tp, 0);
8090                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8091                         u32 mac_stat = tr32(MAC_STATUS);
8092                         int need_setup = 0;
8093
8094                         if (netif_carrier_ok(tp->dev) &&
8095                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8096                                 need_setup = 1;
8097                         }
8098                         if (! netif_carrier_ok(tp->dev) &&
8099                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8100                                          MAC_STATUS_SIGNAL_DET))) {
8101                                 need_setup = 1;
8102                         }
8103                         if (need_setup) {
8104                                 if (!tp->serdes_counter) {
8105                                         tw32_f(MAC_MODE,
8106                                              (tp->mac_mode &
8107                                               ~MAC_MODE_PORT_MODE_MASK));
8108                                         udelay(40);
8109                                         tw32_f(MAC_MODE, tp->mac_mode);
8110                                         udelay(40);
8111                                 }
8112                                 tg3_setup_phy(tp, 0);
8113                         }
8114                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8115                         tg3_serdes_parallel_detect(tp);
8116
8117                 tp->timer_counter = tp->timer_multiplier;
8118         }
8119
8120         /* Heartbeat is only sent once every 2 seconds.
8121          *
8122          * The heartbeat is to tell the ASF firmware that the host
8123          * driver is still alive.  In the event that the OS crashes,
8124          * ASF needs to reset the hardware to free up the FIFO space
8125          * that may be filled with rx packets destined for the host.
8126          * If the FIFO is full, ASF will no longer function properly.
8127          *
8128          * Unintended resets have been reported on real time kernels
8129          * where the timer doesn't run on time.  Netpoll will also have
8130          * same problem.
8131          *
8132          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8133          * to check the ring condition when the heartbeat is expiring
8134          * before doing the reset.  This will prevent most unintended
8135          * resets.
8136          */
8137         if (!--tp->asf_counter) {
8138                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8139                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8140                         tg3_wait_for_event_ack(tp);
8141
8142                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8143                                       FWCMD_NICDRV_ALIVE3);
8144                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8145                         /* 5 seconds timeout */
8146                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8147
8148                         tg3_generate_fw_event(tp);
8149                 }
8150                 tp->asf_counter = tp->asf_multiplier;
8151         }
8152
8153         spin_unlock(&tp->lock);
8154
8155 restart_timer:
8156         tp->timer.expires = jiffies + tp->timer_offset;
8157         add_timer(&tp->timer);
8158 }
8159
8160 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8161 {
8162         irq_handler_t fn;
8163         unsigned long flags;
8164         char *name;
8165         struct tg3_napi *tnapi = &tp->napi[irq_num];
8166
8167         if (tp->irq_cnt == 1)
8168                 name = tp->dev->name;
8169         else {
8170                 name = &tnapi->irq_lbl[0];
8171                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8172                 name[IFNAMSIZ-1] = 0;
8173         }
8174
8175         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8176                 fn = tg3_msi;
8177                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8178                         fn = tg3_msi_1shot;
8179                 flags = IRQF_SAMPLE_RANDOM;
8180         } else {
8181                 fn = tg3_interrupt;
8182                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8183                         fn = tg3_interrupt_tagged;
8184                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8185         }
8186
8187         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8188 }
8189
8190 static int tg3_test_interrupt(struct tg3 *tp)
8191 {
8192         struct tg3_napi *tnapi = &tp->napi[0];
8193         struct net_device *dev = tp->dev;
8194         int err, i, intr_ok = 0;
8195         u32 val;
8196
8197         if (!netif_running(dev))
8198                 return -ENODEV;
8199
8200         tg3_disable_ints(tp);
8201
8202         free_irq(tnapi->irq_vec, tnapi);
8203
8204         /*
8205          * Turn off MSI one shot mode.  Otherwise this test has no
8206          * observable way to know whether the interrupt was delivered.
8207          */
8208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8209             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8210                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8211                 tw32(MSGINT_MODE, val);
8212         }
8213
8214         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8215                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8216         if (err)
8217                 return err;
8218
8219         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8220         tg3_enable_ints(tp);
8221
8222         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8223                tnapi->coal_now);
8224
8225         for (i = 0; i < 5; i++) {
8226                 u32 int_mbox, misc_host_ctrl;
8227
8228                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8229                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8230
8231                 if ((int_mbox != 0) ||
8232                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8233                         intr_ok = 1;
8234                         break;
8235                 }
8236
8237                 msleep(10);
8238         }
8239
8240         tg3_disable_ints(tp);
8241
8242         free_irq(tnapi->irq_vec, tnapi);
8243
8244         err = tg3_request_irq(tp, 0);
8245
8246         if (err)
8247                 return err;
8248
8249         if (intr_ok) {
8250                 /* Reenable MSI one shot mode. */
8251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8252                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8253                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8254                         tw32(MSGINT_MODE, val);
8255                 }
8256                 return 0;
8257         }
8258
8259         return -EIO;
8260 }
8261
8262 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8263  * successfully restored
8264  */
8265 static int tg3_test_msi(struct tg3 *tp)
8266 {
8267         int err;
8268         u16 pci_cmd;
8269
8270         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8271                 return 0;
8272
8273         /* Turn off SERR reporting in case MSI terminates with Master
8274          * Abort.
8275          */
8276         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8277         pci_write_config_word(tp->pdev, PCI_COMMAND,
8278                               pci_cmd & ~PCI_COMMAND_SERR);
8279
8280         err = tg3_test_interrupt(tp);
8281
8282         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8283
8284         if (!err)
8285                 return 0;
8286
8287         /* other failures */
8288         if (err != -EIO)
8289                 return err;
8290
8291         /* MSI test failed, go back to INTx mode */
8292         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8293                "switching to INTx mode. Please report this failure to "
8294                "the PCI maintainer and include system chipset information.\n",
8295                        tp->dev->name);
8296
8297         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8298
8299         pci_disable_msi(tp->pdev);
8300
8301         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8302
8303         err = tg3_request_irq(tp, 0);
8304         if (err)
8305                 return err;
8306
8307         /* Need to reset the chip because the MSI cycle may have terminated
8308          * with Master Abort.
8309          */
8310         tg3_full_lock(tp, 1);
8311
8312         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8313         err = tg3_init_hw(tp, 1);
8314
8315         tg3_full_unlock(tp);
8316
8317         if (err)
8318                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8319
8320         return err;
8321 }
8322
8323 static int tg3_request_firmware(struct tg3 *tp)
8324 {
8325         const __be32 *fw_data;
8326
8327         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8328                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8329                        tp->dev->name, tp->fw_needed);
8330                 return -ENOENT;
8331         }
8332
8333         fw_data = (void *)tp->fw->data;
8334
8335         /* Firmware blob starts with version numbers, followed by
8336          * start address and _full_ length including BSS sections
8337          * (which must be longer than the actual data, of course
8338          */
8339
8340         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8341         if (tp->fw_len < (tp->fw->size - 12)) {
8342                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8343                        tp->dev->name, tp->fw_len, tp->fw_needed);
8344                 release_firmware(tp->fw);
8345                 tp->fw = NULL;
8346                 return -EINVAL;
8347         }
8348
8349         /* We no longer need firmware; we have it. */
8350         tp->fw_needed = NULL;
8351         return 0;
8352 }
8353
8354 static bool tg3_enable_msix(struct tg3 *tp)
8355 {
8356         int i, rc, cpus = num_online_cpus();
8357         struct msix_entry msix_ent[tp->irq_max];
8358
8359         if (cpus == 1)
8360                 /* Just fallback to the simpler MSI mode. */
8361                 return false;
8362
8363         /*
8364          * We want as many rx rings enabled as there are cpus.
8365          * The first MSIX vector only deals with link interrupts, etc,
8366          * so we add one to the number of vectors we are requesting.
8367          */
8368         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8369
8370         for (i = 0; i < tp->irq_max; i++) {
8371                 msix_ent[i].entry  = i;
8372                 msix_ent[i].vector = 0;
8373         }
8374
8375         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8376         if (rc != 0) {
8377                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8378                         return false;
8379                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8380                         return false;
8381                 printk(KERN_NOTICE
8382                        "%s: Requested %d MSI-X vectors, received %d\n",
8383                        tp->dev->name, tp->irq_cnt, rc);
8384                 tp->irq_cnt = rc;
8385         }
8386
8387         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8388
8389         for (i = 0; i < tp->irq_max; i++)
8390                 tp->napi[i].irq_vec = msix_ent[i].vector;
8391
8392         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8393
8394         return true;
8395 }
8396
8397 static void tg3_ints_init(struct tg3 *tp)
8398 {
8399         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8400             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8401                 /* All MSI supporting chips should support tagged
8402                  * status.  Assert that this is the case.
8403                  */
8404                 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8405                        "Not using MSI.\n", tp->dev->name);
8406                 goto defcfg;
8407         }
8408
8409         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8410                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8411         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8412                  pci_enable_msi(tp->pdev) == 0)
8413                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8414
8415         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8416                 u32 msi_mode = tr32(MSGINT_MODE);
8417                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8418                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8419                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8420         }
8421 defcfg:
8422         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8423                 tp->irq_cnt = 1;
8424                 tp->napi[0].irq_vec = tp->pdev->irq;
8425                 tp->dev->real_num_tx_queues = 1;
8426         }
8427 }
8428
8429 static void tg3_ints_fini(struct tg3 *tp)
8430 {
8431         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8432                 pci_disable_msix(tp->pdev);
8433         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8434                 pci_disable_msi(tp->pdev);
8435         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8436         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8437 }
8438
8439 static int tg3_open(struct net_device *dev)
8440 {
8441         struct tg3 *tp = netdev_priv(dev);
8442         int i, err;
8443
8444         if (tp->fw_needed) {
8445                 err = tg3_request_firmware(tp);
8446                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8447                         if (err)
8448                                 return err;
8449                 } else if (err) {
8450                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
8451                                tp->dev->name);
8452                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8453                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8454                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
8455                                tp->dev->name);
8456                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8457                 }
8458         }
8459
8460         netif_carrier_off(tp->dev);
8461
8462         err = tg3_set_power_state(tp, PCI_D0);
8463         if (err)
8464                 return err;
8465
8466         tg3_full_lock(tp, 0);
8467
8468         tg3_disable_ints(tp);
8469         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8470
8471         tg3_full_unlock(tp);
8472
8473         /*
8474          * Setup interrupts first so we know how
8475          * many NAPI resources to allocate
8476          */
8477         tg3_ints_init(tp);
8478
8479         /* The placement of this call is tied
8480          * to the setup and use of Host TX descriptors.
8481          */
8482         err = tg3_alloc_consistent(tp);
8483         if (err)
8484                 goto err_out1;
8485
8486         tg3_napi_enable(tp);
8487
8488         for (i = 0; i < tp->irq_cnt; i++) {
8489                 struct tg3_napi *tnapi = &tp->napi[i];
8490                 err = tg3_request_irq(tp, i);
8491                 if (err) {
8492                         for (i--; i >= 0; i--)
8493                                 free_irq(tnapi->irq_vec, tnapi);
8494                         break;
8495                 }
8496         }
8497
8498         if (err)
8499                 goto err_out2;
8500
8501         tg3_full_lock(tp, 0);
8502
8503         err = tg3_init_hw(tp, 1);
8504         if (err) {
8505                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8506                 tg3_free_rings(tp);
8507         } else {
8508                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8509                         tp->timer_offset = HZ;
8510                 else
8511                         tp->timer_offset = HZ / 10;
8512
8513                 BUG_ON(tp->timer_offset > HZ);
8514                 tp->timer_counter = tp->timer_multiplier =
8515                         (HZ / tp->timer_offset);
8516                 tp->asf_counter = tp->asf_multiplier =
8517                         ((HZ / tp->timer_offset) * 2);
8518
8519                 init_timer(&tp->timer);
8520                 tp->timer.expires = jiffies + tp->timer_offset;
8521                 tp->timer.data = (unsigned long) tp;
8522                 tp->timer.function = tg3_timer;
8523         }
8524
8525         tg3_full_unlock(tp);
8526
8527         if (err)
8528                 goto err_out3;
8529
8530         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8531                 err = tg3_test_msi(tp);
8532
8533                 if (err) {
8534                         tg3_full_lock(tp, 0);
8535                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8536                         tg3_free_rings(tp);
8537                         tg3_full_unlock(tp);
8538
8539                         goto err_out2;
8540                 }
8541
8542                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8543                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8544                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8545                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8546
8547                         tw32(PCIE_TRANSACTION_CFG,
8548                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8549                 }
8550         }
8551
8552         tg3_phy_start(tp);
8553
8554         tg3_full_lock(tp, 0);
8555
8556         add_timer(&tp->timer);
8557         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8558         tg3_enable_ints(tp);
8559
8560         tg3_full_unlock(tp);
8561
8562         netif_tx_start_all_queues(dev);
8563
8564         return 0;
8565
8566 err_out3:
8567         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8568                 struct tg3_napi *tnapi = &tp->napi[i];
8569                 free_irq(tnapi->irq_vec, tnapi);
8570         }
8571
8572 err_out2:
8573         tg3_napi_disable(tp);
8574         tg3_free_consistent(tp);
8575
8576 err_out1:
8577         tg3_ints_fini(tp);
8578         return err;
8579 }
8580
8581 #if 0
8582 /*static*/ void tg3_dump_state(struct tg3 *tp)
8583 {
8584         u32 val32, val32_2, val32_3, val32_4, val32_5;
8585         u16 val16;
8586         int i;
8587         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8588
8589         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8590         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8591         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8592                val16, val32);
8593
8594         /* MAC block */
8595         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8596                tr32(MAC_MODE), tr32(MAC_STATUS));
8597         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8598                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8599         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8600                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8601         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8602                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8603
8604         /* Send data initiator control block */
8605         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8606                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8607         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8608                tr32(SNDDATAI_STATSCTRL));
8609
8610         /* Send data completion control block */
8611         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8612
8613         /* Send BD ring selector block */
8614         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8615                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8616
8617         /* Send BD initiator control block */
8618         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8619                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8620
8621         /* Send BD completion control block */
8622         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8623
8624         /* Receive list placement control block */
8625         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8626                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8627         printk("       RCVLPC_STATSCTRL[%08x]\n",
8628                tr32(RCVLPC_STATSCTRL));
8629
8630         /* Receive data and receive BD initiator control block */
8631         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8632                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8633
8634         /* Receive data completion control block */
8635         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8636                tr32(RCVDCC_MODE));
8637
8638         /* Receive BD initiator control block */
8639         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8640                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8641
8642         /* Receive BD completion control block */
8643         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8644                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8645
8646         /* Receive list selector control block */
8647         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8648                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8649
8650         /* Mbuf cluster free block */
8651         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8652                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8653
8654         /* Host coalescing control block */
8655         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8656                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8657         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8658                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8659                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8660         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8661                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8662                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8663         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8664                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8665         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8666                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8667
8668         /* Memory arbiter control block */
8669         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8670                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8671
8672         /* Buffer manager control block */
8673         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8674                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8675         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8676                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8677         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8678                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8679                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8680                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8681
8682         /* Read DMA control block */
8683         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8684                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8685
8686         /* Write DMA control block */
8687         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8688                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8689
8690         /* DMA completion block */
8691         printk("DEBUG: DMAC_MODE[%08x]\n",
8692                tr32(DMAC_MODE));
8693
8694         /* GRC block */
8695         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8696                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8697         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8698                tr32(GRC_LOCAL_CTRL));
8699
8700         /* TG3_BDINFOs */
8701         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8702                tr32(RCVDBDI_JUMBO_BD + 0x0),
8703                tr32(RCVDBDI_JUMBO_BD + 0x4),
8704                tr32(RCVDBDI_JUMBO_BD + 0x8),
8705                tr32(RCVDBDI_JUMBO_BD + 0xc));
8706         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8707                tr32(RCVDBDI_STD_BD + 0x0),
8708                tr32(RCVDBDI_STD_BD + 0x4),
8709                tr32(RCVDBDI_STD_BD + 0x8),
8710                tr32(RCVDBDI_STD_BD + 0xc));
8711         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8712                tr32(RCVDBDI_MINI_BD + 0x0),
8713                tr32(RCVDBDI_MINI_BD + 0x4),
8714                tr32(RCVDBDI_MINI_BD + 0x8),
8715                tr32(RCVDBDI_MINI_BD + 0xc));
8716
8717         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8718         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8719         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8720         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8721         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8722                val32, val32_2, val32_3, val32_4);
8723
8724         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8725         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8726         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8727         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8728         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8729                val32, val32_2, val32_3, val32_4);
8730
8731         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8732         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8733         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8734         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8735         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8736         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8737                val32, val32_2, val32_3, val32_4, val32_5);
8738
8739         /* SW status block */
8740         printk(KERN_DEBUG
8741          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8742                sblk->status,
8743                sblk->status_tag,
8744                sblk->rx_jumbo_consumer,
8745                sblk->rx_consumer,
8746                sblk->rx_mini_consumer,
8747                sblk->idx[0].rx_producer,
8748                sblk->idx[0].tx_consumer);
8749
8750         /* SW statistics block */
8751         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8752                ((u32 *)tp->hw_stats)[0],
8753                ((u32 *)tp->hw_stats)[1],
8754                ((u32 *)tp->hw_stats)[2],
8755                ((u32 *)tp->hw_stats)[3]);
8756
8757         /* Mailboxes */
8758         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8759                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8760                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8761                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8762                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8763
8764         /* NIC side send descriptors. */
8765         for (i = 0; i < 6; i++) {
8766                 unsigned long txd;
8767
8768                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8769                         + (i * sizeof(struct tg3_tx_buffer_desc));
8770                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8771                        i,
8772                        readl(txd + 0x0), readl(txd + 0x4),
8773                        readl(txd + 0x8), readl(txd + 0xc));
8774         }
8775
8776         /* NIC side RX descriptors. */
8777         for (i = 0; i < 6; i++) {
8778                 unsigned long rxd;
8779
8780                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8781                         + (i * sizeof(struct tg3_rx_buffer_desc));
8782                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8783                        i,
8784                        readl(rxd + 0x0), readl(rxd + 0x4),
8785                        readl(rxd + 0x8), readl(rxd + 0xc));
8786                 rxd += (4 * sizeof(u32));
8787                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8788                        i,
8789                        readl(rxd + 0x0), readl(rxd + 0x4),
8790                        readl(rxd + 0x8), readl(rxd + 0xc));
8791         }
8792
8793         for (i = 0; i < 6; i++) {
8794                 unsigned long rxd;
8795
8796                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8797                         + (i * sizeof(struct tg3_rx_buffer_desc));
8798                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8799                        i,
8800                        readl(rxd + 0x0), readl(rxd + 0x4),
8801                        readl(rxd + 0x8), readl(rxd + 0xc));
8802                 rxd += (4 * sizeof(u32));
8803                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8804                        i,
8805                        readl(rxd + 0x0), readl(rxd + 0x4),
8806                        readl(rxd + 0x8), readl(rxd + 0xc));
8807         }
8808 }
8809 #endif
8810
8811 static struct net_device_stats *tg3_get_stats(struct net_device *);
8812 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8813
8814 static int tg3_close(struct net_device *dev)
8815 {
8816         int i;
8817         struct tg3 *tp = netdev_priv(dev);
8818
8819         tg3_napi_disable(tp);
8820         cancel_work_sync(&tp->reset_task);
8821
8822         netif_tx_stop_all_queues(dev);
8823
8824         del_timer_sync(&tp->timer);
8825
8826         tg3_phy_stop(tp);
8827
8828         tg3_full_lock(tp, 1);
8829 #if 0
8830         tg3_dump_state(tp);
8831 #endif
8832
8833         tg3_disable_ints(tp);
8834
8835         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8836         tg3_free_rings(tp);
8837         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8838
8839         tg3_full_unlock(tp);
8840
8841         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8842                 struct tg3_napi *tnapi = &tp->napi[i];
8843                 free_irq(tnapi->irq_vec, tnapi);
8844         }
8845
8846         tg3_ints_fini(tp);
8847
8848         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8849                sizeof(tp->net_stats_prev));
8850         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8851                sizeof(tp->estats_prev));
8852
8853         tg3_free_consistent(tp);
8854
8855         tg3_set_power_state(tp, PCI_D3hot);
8856
8857         netif_carrier_off(tp->dev);
8858
8859         return 0;
8860 }
8861
8862 static inline unsigned long get_stat64(tg3_stat64_t *val)
8863 {
8864         unsigned long ret;
8865
8866 #if (BITS_PER_LONG == 32)
8867         ret = val->low;
8868 #else
8869         ret = ((u64)val->high << 32) | ((u64)val->low);
8870 #endif
8871         return ret;
8872 }
8873
8874 static inline u64 get_estat64(tg3_stat64_t *val)
8875 {
8876        return ((u64)val->high << 32) | ((u64)val->low);
8877 }
8878
8879 static unsigned long calc_crc_errors(struct tg3 *tp)
8880 {
8881         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8882
8883         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8884             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8885              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8886                 u32 val;
8887
8888                 spin_lock_bh(&tp->lock);
8889                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8890                         tg3_writephy(tp, MII_TG3_TEST1,
8891                                      val | MII_TG3_TEST1_CRC_EN);
8892                         tg3_readphy(tp, 0x14, &val);
8893                 } else
8894                         val = 0;
8895                 spin_unlock_bh(&tp->lock);
8896
8897                 tp->phy_crc_errors += val;
8898
8899                 return tp->phy_crc_errors;
8900         }
8901
8902         return get_stat64(&hw_stats->rx_fcs_errors);
8903 }
8904
8905 #define ESTAT_ADD(member) \
8906         estats->member =        old_estats->member + \
8907                                 get_estat64(&hw_stats->member)
8908
8909 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8910 {
8911         struct tg3_ethtool_stats *estats = &tp->estats;
8912         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8913         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8914
8915         if (!hw_stats)
8916                 return old_estats;
8917
8918         ESTAT_ADD(rx_octets);
8919         ESTAT_ADD(rx_fragments);
8920         ESTAT_ADD(rx_ucast_packets);
8921         ESTAT_ADD(rx_mcast_packets);
8922         ESTAT_ADD(rx_bcast_packets);
8923         ESTAT_ADD(rx_fcs_errors);
8924         ESTAT_ADD(rx_align_errors);
8925         ESTAT_ADD(rx_xon_pause_rcvd);
8926         ESTAT_ADD(rx_xoff_pause_rcvd);
8927         ESTAT_ADD(rx_mac_ctrl_rcvd);
8928         ESTAT_ADD(rx_xoff_entered);
8929         ESTAT_ADD(rx_frame_too_long_errors);
8930         ESTAT_ADD(rx_jabbers);
8931         ESTAT_ADD(rx_undersize_packets);
8932         ESTAT_ADD(rx_in_length_errors);
8933         ESTAT_ADD(rx_out_length_errors);
8934         ESTAT_ADD(rx_64_or_less_octet_packets);
8935         ESTAT_ADD(rx_65_to_127_octet_packets);
8936         ESTAT_ADD(rx_128_to_255_octet_packets);
8937         ESTAT_ADD(rx_256_to_511_octet_packets);
8938         ESTAT_ADD(rx_512_to_1023_octet_packets);
8939         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8940         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8941         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8942         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8943         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8944
8945         ESTAT_ADD(tx_octets);
8946         ESTAT_ADD(tx_collisions);
8947         ESTAT_ADD(tx_xon_sent);
8948         ESTAT_ADD(tx_xoff_sent);
8949         ESTAT_ADD(tx_flow_control);
8950         ESTAT_ADD(tx_mac_errors);
8951         ESTAT_ADD(tx_single_collisions);
8952         ESTAT_ADD(tx_mult_collisions);
8953         ESTAT_ADD(tx_deferred);
8954         ESTAT_ADD(tx_excessive_collisions);
8955         ESTAT_ADD(tx_late_collisions);
8956         ESTAT_ADD(tx_collide_2times);
8957         ESTAT_ADD(tx_collide_3times);
8958         ESTAT_ADD(tx_collide_4times);
8959         ESTAT_ADD(tx_collide_5times);
8960         ESTAT_ADD(tx_collide_6times);
8961         ESTAT_ADD(tx_collide_7times);
8962         ESTAT_ADD(tx_collide_8times);
8963         ESTAT_ADD(tx_collide_9times);
8964         ESTAT_ADD(tx_collide_10times);
8965         ESTAT_ADD(tx_collide_11times);
8966         ESTAT_ADD(tx_collide_12times);
8967         ESTAT_ADD(tx_collide_13times);
8968         ESTAT_ADD(tx_collide_14times);
8969         ESTAT_ADD(tx_collide_15times);
8970         ESTAT_ADD(tx_ucast_packets);
8971         ESTAT_ADD(tx_mcast_packets);
8972         ESTAT_ADD(tx_bcast_packets);
8973         ESTAT_ADD(tx_carrier_sense_errors);
8974         ESTAT_ADD(tx_discards);
8975         ESTAT_ADD(tx_errors);
8976
8977         ESTAT_ADD(dma_writeq_full);
8978         ESTAT_ADD(dma_write_prioq_full);
8979         ESTAT_ADD(rxbds_empty);
8980         ESTAT_ADD(rx_discards);
8981         ESTAT_ADD(rx_errors);
8982         ESTAT_ADD(rx_threshold_hit);
8983
8984         ESTAT_ADD(dma_readq_full);
8985         ESTAT_ADD(dma_read_prioq_full);
8986         ESTAT_ADD(tx_comp_queue_full);
8987
8988         ESTAT_ADD(ring_set_send_prod_index);
8989         ESTAT_ADD(ring_status_update);
8990         ESTAT_ADD(nic_irqs);
8991         ESTAT_ADD(nic_avoided_irqs);
8992         ESTAT_ADD(nic_tx_threshold_hit);
8993
8994         return estats;
8995 }
8996
8997 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8998 {
8999         struct tg3 *tp = netdev_priv(dev);
9000         struct net_device_stats *stats = &tp->net_stats;
9001         struct net_device_stats *old_stats = &tp->net_stats_prev;
9002         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9003
9004         if (!hw_stats)
9005                 return old_stats;
9006
9007         stats->rx_packets = old_stats->rx_packets +
9008                 get_stat64(&hw_stats->rx_ucast_packets) +
9009                 get_stat64(&hw_stats->rx_mcast_packets) +
9010                 get_stat64(&hw_stats->rx_bcast_packets);
9011
9012         stats->tx_packets = old_stats->tx_packets +
9013                 get_stat64(&hw_stats->tx_ucast_packets) +
9014                 get_stat64(&hw_stats->tx_mcast_packets) +
9015                 get_stat64(&hw_stats->tx_bcast_packets);
9016
9017         stats->rx_bytes = old_stats->rx_bytes +
9018                 get_stat64(&hw_stats->rx_octets);
9019         stats->tx_bytes = old_stats->tx_bytes +
9020                 get_stat64(&hw_stats->tx_octets);
9021
9022         stats->rx_errors = old_stats->rx_errors +
9023                 get_stat64(&hw_stats->rx_errors);
9024         stats->tx_errors = old_stats->tx_errors +
9025                 get_stat64(&hw_stats->tx_errors) +
9026                 get_stat64(&hw_stats->tx_mac_errors) +
9027                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9028                 get_stat64(&hw_stats->tx_discards);
9029
9030         stats->multicast = old_stats->multicast +
9031                 get_stat64(&hw_stats->rx_mcast_packets);
9032         stats->collisions = old_stats->collisions +
9033                 get_stat64(&hw_stats->tx_collisions);
9034
9035         stats->rx_length_errors = old_stats->rx_length_errors +
9036                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9037                 get_stat64(&hw_stats->rx_undersize_packets);
9038
9039         stats->rx_over_errors = old_stats->rx_over_errors +
9040                 get_stat64(&hw_stats->rxbds_empty);
9041         stats->rx_frame_errors = old_stats->rx_frame_errors +
9042                 get_stat64(&hw_stats->rx_align_errors);
9043         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9044                 get_stat64(&hw_stats->tx_discards);
9045         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9046                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9047
9048         stats->rx_crc_errors = old_stats->rx_crc_errors +
9049                 calc_crc_errors(tp);
9050
9051         stats->rx_missed_errors = old_stats->rx_missed_errors +
9052                 get_stat64(&hw_stats->rx_discards);
9053
9054         return stats;
9055 }
9056
9057 static inline u32 calc_crc(unsigned char *buf, int len)
9058 {
9059         u32 reg;
9060         u32 tmp;
9061         int j, k;
9062
9063         reg = 0xffffffff;
9064
9065         for (j = 0; j < len; j++) {
9066                 reg ^= buf[j];
9067
9068                 for (k = 0; k < 8; k++) {
9069                         tmp = reg & 0x01;
9070
9071                         reg >>= 1;
9072
9073                         if (tmp) {
9074                                 reg ^= 0xedb88320;
9075                         }
9076                 }
9077         }
9078
9079         return ~reg;
9080 }
9081
9082 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9083 {
9084         /* accept or reject all multicast frames */
9085         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9086         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9087         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9088         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9089 }
9090
9091 static void __tg3_set_rx_mode(struct net_device *dev)
9092 {
9093         struct tg3 *tp = netdev_priv(dev);
9094         u32 rx_mode;
9095
9096         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9097                                   RX_MODE_KEEP_VLAN_TAG);
9098
9099         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9100          * flag clear.
9101          */
9102 #if TG3_VLAN_TAG_USED
9103         if (!tp->vlgrp &&
9104             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9105                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9106 #else
9107         /* By definition, VLAN is disabled always in this
9108          * case.
9109          */
9110         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9111                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9112 #endif
9113
9114         if (dev->flags & IFF_PROMISC) {
9115                 /* Promiscuous mode. */
9116                 rx_mode |= RX_MODE_PROMISC;
9117         } else if (dev->flags & IFF_ALLMULTI) {
9118                 /* Accept all multicast. */
9119                 tg3_set_multi (tp, 1);
9120         } else if (dev->mc_count < 1) {
9121                 /* Reject all multicast. */
9122                 tg3_set_multi (tp, 0);
9123         } else {
9124                 /* Accept one or more multicast(s). */
9125                 struct dev_mc_list *mclist;
9126                 unsigned int i;
9127                 u32 mc_filter[4] = { 0, };
9128                 u32 regidx;
9129                 u32 bit;
9130                 u32 crc;
9131
9132                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9133                      i++, mclist = mclist->next) {
9134
9135                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9136                         bit = ~crc & 0x7f;
9137                         regidx = (bit & 0x60) >> 5;
9138                         bit &= 0x1f;
9139                         mc_filter[regidx] |= (1 << bit);
9140                 }
9141
9142                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9143                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9144                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9145                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9146         }
9147
9148         if (rx_mode != tp->rx_mode) {
9149                 tp->rx_mode = rx_mode;
9150                 tw32_f(MAC_RX_MODE, rx_mode);
9151                 udelay(10);
9152         }
9153 }
9154
9155 static void tg3_set_rx_mode(struct net_device *dev)
9156 {
9157         struct tg3 *tp = netdev_priv(dev);
9158
9159         if (!netif_running(dev))
9160                 return;
9161
9162         tg3_full_lock(tp, 0);
9163         __tg3_set_rx_mode(dev);
9164         tg3_full_unlock(tp);
9165 }
9166
9167 #define TG3_REGDUMP_LEN         (32 * 1024)
9168
9169 static int tg3_get_regs_len(struct net_device *dev)
9170 {
9171         return TG3_REGDUMP_LEN;
9172 }
9173
9174 static void tg3_get_regs(struct net_device *dev,
9175                 struct ethtool_regs *regs, void *_p)
9176 {
9177         u32 *p = _p;
9178         struct tg3 *tp = netdev_priv(dev);
9179         u8 *orig_p = _p;
9180         int i;
9181
9182         regs->version = 0;
9183
9184         memset(p, 0, TG3_REGDUMP_LEN);
9185
9186         if (tp->link_config.phy_is_low_power)
9187                 return;
9188
9189         tg3_full_lock(tp, 0);
9190
9191 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9192 #define GET_REG32_LOOP(base,len)                \
9193 do {    p = (u32 *)(orig_p + (base));           \
9194         for (i = 0; i < len; i += 4)            \
9195                 __GET_REG32((base) + i);        \
9196 } while (0)
9197 #define GET_REG32_1(reg)                        \
9198 do {    p = (u32 *)(orig_p + (reg));            \
9199         __GET_REG32((reg));                     \
9200 } while (0)
9201
9202         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9203         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9204         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9205         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9206         GET_REG32_1(SNDDATAC_MODE);
9207         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9208         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9209         GET_REG32_1(SNDBDC_MODE);
9210         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9211         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9212         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9213         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9214         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9215         GET_REG32_1(RCVDCC_MODE);
9216         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9217         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9218         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9219         GET_REG32_1(MBFREE_MODE);
9220         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9221         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9222         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9223         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9224         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9225         GET_REG32_1(RX_CPU_MODE);
9226         GET_REG32_1(RX_CPU_STATE);
9227         GET_REG32_1(RX_CPU_PGMCTR);
9228         GET_REG32_1(RX_CPU_HWBKPT);
9229         GET_REG32_1(TX_CPU_MODE);
9230         GET_REG32_1(TX_CPU_STATE);
9231         GET_REG32_1(TX_CPU_PGMCTR);
9232         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9233         GET_REG32_LOOP(FTQ_RESET, 0x120);
9234         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9235         GET_REG32_1(DMAC_MODE);
9236         GET_REG32_LOOP(GRC_MODE, 0x4c);
9237         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9238                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9239
9240 #undef __GET_REG32
9241 #undef GET_REG32_LOOP
9242 #undef GET_REG32_1
9243
9244         tg3_full_unlock(tp);
9245 }
9246
9247 static int tg3_get_eeprom_len(struct net_device *dev)
9248 {
9249         struct tg3 *tp = netdev_priv(dev);
9250
9251         return tp->nvram_size;
9252 }
9253
9254 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9255 {
9256         struct tg3 *tp = netdev_priv(dev);
9257         int ret;
9258         u8  *pd;
9259         u32 i, offset, len, b_offset, b_count;
9260         __be32 val;
9261
9262         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9263                 return -EINVAL;
9264
9265         if (tp->link_config.phy_is_low_power)
9266                 return -EAGAIN;
9267
9268         offset = eeprom->offset;
9269         len = eeprom->len;
9270         eeprom->len = 0;
9271
9272         eeprom->magic = TG3_EEPROM_MAGIC;
9273
9274         if (offset & 3) {
9275                 /* adjustments to start on required 4 byte boundary */
9276                 b_offset = offset & 3;
9277                 b_count = 4 - b_offset;
9278                 if (b_count > len) {
9279                         /* i.e. offset=1 len=2 */
9280                         b_count = len;
9281                 }
9282                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9283                 if (ret)
9284                         return ret;
9285                 memcpy(data, ((char*)&val) + b_offset, b_count);
9286                 len -= b_count;
9287                 offset += b_count;
9288                 eeprom->len += b_count;
9289         }
9290
9291         /* read bytes upto the last 4 byte boundary */
9292         pd = &data[eeprom->len];
9293         for (i = 0; i < (len - (len & 3)); i += 4) {
9294                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9295                 if (ret) {
9296                         eeprom->len += i;
9297                         return ret;
9298                 }
9299                 memcpy(pd + i, &val, 4);
9300         }
9301         eeprom->len += i;
9302
9303         if (len & 3) {
9304                 /* read last bytes not ending on 4 byte boundary */
9305                 pd = &data[eeprom->len];
9306                 b_count = len & 3;
9307                 b_offset = offset + len - b_count;
9308                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9309                 if (ret)
9310                         return ret;
9311                 memcpy(pd, &val, b_count);
9312                 eeprom->len += b_count;
9313         }
9314         return 0;
9315 }
9316
9317 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9318
9319 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9320 {
9321         struct tg3 *tp = netdev_priv(dev);
9322         int ret;
9323         u32 offset, len, b_offset, odd_len;
9324         u8 *buf;
9325         __be32 start, end;
9326
9327         if (tp->link_config.phy_is_low_power)
9328                 return -EAGAIN;
9329
9330         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9331             eeprom->magic != TG3_EEPROM_MAGIC)
9332                 return -EINVAL;
9333
9334         offset = eeprom->offset;
9335         len = eeprom->len;
9336
9337         if ((b_offset = (offset & 3))) {
9338                 /* adjustments to start on required 4 byte boundary */
9339                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9340                 if (ret)
9341                         return ret;
9342                 len += b_offset;
9343                 offset &= ~3;
9344                 if (len < 4)
9345                         len = 4;
9346         }
9347
9348         odd_len = 0;
9349         if (len & 3) {
9350                 /* adjustments to end on required 4 byte boundary */
9351                 odd_len = 1;
9352                 len = (len + 3) & ~3;
9353                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9354                 if (ret)
9355                         return ret;
9356         }
9357
9358         buf = data;
9359         if (b_offset || odd_len) {
9360                 buf = kmalloc(len, GFP_KERNEL);
9361                 if (!buf)
9362                         return -ENOMEM;
9363                 if (b_offset)
9364                         memcpy(buf, &start, 4);
9365                 if (odd_len)
9366                         memcpy(buf+len-4, &end, 4);
9367                 memcpy(buf + b_offset, data, eeprom->len);
9368         }
9369
9370         ret = tg3_nvram_write_block(tp, offset, len, buf);
9371
9372         if (buf != data)
9373                 kfree(buf);
9374
9375         return ret;
9376 }
9377
9378 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9379 {
9380         struct tg3 *tp = netdev_priv(dev);
9381
9382         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9383                 struct phy_device *phydev;
9384                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9385                         return -EAGAIN;
9386                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9387                 return phy_ethtool_gset(phydev, cmd);
9388         }
9389
9390         cmd->supported = (SUPPORTED_Autoneg);
9391
9392         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9393                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9394                                    SUPPORTED_1000baseT_Full);
9395
9396         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9397                 cmd->supported |= (SUPPORTED_100baseT_Half |
9398                                   SUPPORTED_100baseT_Full |
9399                                   SUPPORTED_10baseT_Half |
9400                                   SUPPORTED_10baseT_Full |
9401                                   SUPPORTED_TP);
9402                 cmd->port = PORT_TP;
9403         } else {
9404                 cmd->supported |= SUPPORTED_FIBRE;
9405                 cmd->port = PORT_FIBRE;
9406         }
9407
9408         cmd->advertising = tp->link_config.advertising;
9409         if (netif_running(dev)) {
9410                 cmd->speed = tp->link_config.active_speed;
9411                 cmd->duplex = tp->link_config.active_duplex;
9412         }
9413         cmd->phy_address = tp->phy_addr;
9414         cmd->transceiver = XCVR_INTERNAL;
9415         cmd->autoneg = tp->link_config.autoneg;
9416         cmd->maxtxpkt = 0;
9417         cmd->maxrxpkt = 0;
9418         return 0;
9419 }
9420
9421 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9422 {
9423         struct tg3 *tp = netdev_priv(dev);
9424
9425         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9426                 struct phy_device *phydev;
9427                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9428                         return -EAGAIN;
9429                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9430                 return phy_ethtool_sset(phydev, cmd);
9431         }
9432
9433         if (cmd->autoneg != AUTONEG_ENABLE &&
9434             cmd->autoneg != AUTONEG_DISABLE)
9435                 return -EINVAL;
9436
9437         if (cmd->autoneg == AUTONEG_DISABLE &&
9438             cmd->duplex != DUPLEX_FULL &&
9439             cmd->duplex != DUPLEX_HALF)
9440                 return -EINVAL;
9441
9442         if (cmd->autoneg == AUTONEG_ENABLE) {
9443                 u32 mask = ADVERTISED_Autoneg |
9444                            ADVERTISED_Pause |
9445                            ADVERTISED_Asym_Pause;
9446
9447                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9448                         mask |= ADVERTISED_1000baseT_Half |
9449                                 ADVERTISED_1000baseT_Full;
9450
9451                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9452                         mask |= ADVERTISED_100baseT_Half |
9453                                 ADVERTISED_100baseT_Full |
9454                                 ADVERTISED_10baseT_Half |
9455                                 ADVERTISED_10baseT_Full |
9456                                 ADVERTISED_TP;
9457                 else
9458                         mask |= ADVERTISED_FIBRE;
9459
9460                 if (cmd->advertising & ~mask)
9461                         return -EINVAL;
9462
9463                 mask &= (ADVERTISED_1000baseT_Half |
9464                          ADVERTISED_1000baseT_Full |
9465                          ADVERTISED_100baseT_Half |
9466                          ADVERTISED_100baseT_Full |
9467                          ADVERTISED_10baseT_Half |
9468                          ADVERTISED_10baseT_Full);
9469
9470                 cmd->advertising &= mask;
9471         } else {
9472                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9473                         if (cmd->speed != SPEED_1000)
9474                                 return -EINVAL;
9475
9476                         if (cmd->duplex != DUPLEX_FULL)
9477                                 return -EINVAL;
9478                 } else {
9479                         if (cmd->speed != SPEED_100 &&
9480                             cmd->speed != SPEED_10)
9481                                 return -EINVAL;
9482                 }
9483         }
9484
9485         tg3_full_lock(tp, 0);
9486
9487         tp->link_config.autoneg = cmd->autoneg;
9488         if (cmd->autoneg == AUTONEG_ENABLE) {
9489                 tp->link_config.advertising = (cmd->advertising |
9490                                               ADVERTISED_Autoneg);
9491                 tp->link_config.speed = SPEED_INVALID;
9492                 tp->link_config.duplex = DUPLEX_INVALID;
9493         } else {
9494                 tp->link_config.advertising = 0;
9495                 tp->link_config.speed = cmd->speed;
9496                 tp->link_config.duplex = cmd->duplex;
9497         }
9498
9499         tp->link_config.orig_speed = tp->link_config.speed;
9500         tp->link_config.orig_duplex = tp->link_config.duplex;
9501         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9502
9503         if (netif_running(dev))
9504                 tg3_setup_phy(tp, 1);
9505
9506         tg3_full_unlock(tp);
9507
9508         return 0;
9509 }
9510
9511 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9512 {
9513         struct tg3 *tp = netdev_priv(dev);
9514
9515         strcpy(info->driver, DRV_MODULE_NAME);
9516         strcpy(info->version, DRV_MODULE_VERSION);
9517         strcpy(info->fw_version, tp->fw_ver);
9518         strcpy(info->bus_info, pci_name(tp->pdev));
9519 }
9520
9521 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9522 {
9523         struct tg3 *tp = netdev_priv(dev);
9524
9525         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9526             device_can_wakeup(&tp->pdev->dev))
9527                 wol->supported = WAKE_MAGIC;
9528         else
9529                 wol->supported = 0;
9530         wol->wolopts = 0;
9531         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9532             device_can_wakeup(&tp->pdev->dev))
9533                 wol->wolopts = WAKE_MAGIC;
9534         memset(&wol->sopass, 0, sizeof(wol->sopass));
9535 }
9536
9537 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9538 {
9539         struct tg3 *tp = netdev_priv(dev);
9540         struct device *dp = &tp->pdev->dev;
9541
9542         if (wol->wolopts & ~WAKE_MAGIC)
9543                 return -EINVAL;
9544         if ((wol->wolopts & WAKE_MAGIC) &&
9545             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9546                 return -EINVAL;
9547
9548         spin_lock_bh(&tp->lock);
9549         if (wol->wolopts & WAKE_MAGIC) {
9550                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9551                 device_set_wakeup_enable(dp, true);
9552         } else {
9553                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9554                 device_set_wakeup_enable(dp, false);
9555         }
9556         spin_unlock_bh(&tp->lock);
9557
9558         return 0;
9559 }
9560
9561 static u32 tg3_get_msglevel(struct net_device *dev)
9562 {
9563         struct tg3 *tp = netdev_priv(dev);
9564         return tp->msg_enable;
9565 }
9566
9567 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9568 {
9569         struct tg3 *tp = netdev_priv(dev);
9570         tp->msg_enable = value;
9571 }
9572
9573 static int tg3_set_tso(struct net_device *dev, u32 value)
9574 {
9575         struct tg3 *tp = netdev_priv(dev);
9576
9577         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9578                 if (value)
9579                         return -EINVAL;
9580                 return 0;
9581         }
9582         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9583             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9584              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9585                 if (value) {
9586                         dev->features |= NETIF_F_TSO6;
9587                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9588                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9589                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9590                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9591                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9592                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9593                                 dev->features |= NETIF_F_TSO_ECN;
9594                 } else
9595                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9596         }
9597         return ethtool_op_set_tso(dev, value);
9598 }
9599
9600 static int tg3_nway_reset(struct net_device *dev)
9601 {
9602         struct tg3 *tp = netdev_priv(dev);
9603         int r;
9604
9605         if (!netif_running(dev))
9606                 return -EAGAIN;
9607
9608         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9609                 return -EINVAL;
9610
9611         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9612                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9613                         return -EAGAIN;
9614                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9615         } else {
9616                 u32 bmcr;
9617
9618                 spin_lock_bh(&tp->lock);
9619                 r = -EINVAL;
9620                 tg3_readphy(tp, MII_BMCR, &bmcr);
9621                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9622                     ((bmcr & BMCR_ANENABLE) ||
9623                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9624                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9625                                                    BMCR_ANENABLE);
9626                         r = 0;
9627                 }
9628                 spin_unlock_bh(&tp->lock);
9629         }
9630
9631         return r;
9632 }
9633
9634 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9635 {
9636         struct tg3 *tp = netdev_priv(dev);
9637
9638         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9639         ering->rx_mini_max_pending = 0;
9640         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9641                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9642         else
9643                 ering->rx_jumbo_max_pending = 0;
9644
9645         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9646
9647         ering->rx_pending = tp->rx_pending;
9648         ering->rx_mini_pending = 0;
9649         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9650                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9651         else
9652                 ering->rx_jumbo_pending = 0;
9653
9654         ering->tx_pending = tp->napi[0].tx_pending;
9655 }
9656
9657 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9658 {
9659         struct tg3 *tp = netdev_priv(dev);
9660         int i, irq_sync = 0, err = 0;
9661
9662         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9663             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9664             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9665             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9666             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9667              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9668                 return -EINVAL;
9669
9670         if (netif_running(dev)) {
9671                 tg3_phy_stop(tp);
9672                 tg3_netif_stop(tp);
9673                 irq_sync = 1;
9674         }
9675
9676         tg3_full_lock(tp, irq_sync);
9677
9678         tp->rx_pending = ering->rx_pending;
9679
9680         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9681             tp->rx_pending > 63)
9682                 tp->rx_pending = 63;
9683         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9684
9685         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9686                 tp->napi[i].tx_pending = ering->tx_pending;
9687
9688         if (netif_running(dev)) {
9689                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9690                 err = tg3_restart_hw(tp, 1);
9691                 if (!err)
9692                         tg3_netif_start(tp);
9693         }
9694
9695         tg3_full_unlock(tp);
9696
9697         if (irq_sync && !err)
9698                 tg3_phy_start(tp);
9699
9700         return err;
9701 }
9702
9703 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9704 {
9705         struct tg3 *tp = netdev_priv(dev);
9706
9707         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9708
9709         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9710                 epause->rx_pause = 1;
9711         else
9712                 epause->rx_pause = 0;
9713
9714         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9715                 epause->tx_pause = 1;
9716         else
9717                 epause->tx_pause = 0;
9718 }
9719
9720 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9721 {
9722         struct tg3 *tp = netdev_priv(dev);
9723         int err = 0;
9724
9725         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9726                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9727                         return -EAGAIN;
9728
9729                 if (epause->autoneg) {
9730                         u32 newadv;
9731                         struct phy_device *phydev;
9732
9733                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9734
9735                         if (epause->rx_pause) {
9736                                 if (epause->tx_pause)
9737                                         newadv = ADVERTISED_Pause;
9738                                 else
9739                                         newadv = ADVERTISED_Pause |
9740                                                  ADVERTISED_Asym_Pause;
9741                         } else if (epause->tx_pause) {
9742                                 newadv = ADVERTISED_Asym_Pause;
9743                         } else
9744                                 newadv = 0;
9745
9746                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9747                                 u32 oldadv = phydev->advertising &
9748                                              (ADVERTISED_Pause |
9749                                               ADVERTISED_Asym_Pause);
9750                                 if (oldadv != newadv) {
9751                                         phydev->advertising &=
9752                                                 ~(ADVERTISED_Pause |
9753                                                   ADVERTISED_Asym_Pause);
9754                                         phydev->advertising |= newadv;
9755                                         err = phy_start_aneg(phydev);
9756                                 }
9757                         } else {
9758                                 tp->link_config.advertising &=
9759                                                 ~(ADVERTISED_Pause |
9760                                                   ADVERTISED_Asym_Pause);
9761                                 tp->link_config.advertising |= newadv;
9762                         }
9763                 } else {
9764                         if (epause->rx_pause)
9765                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9766                         else
9767                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9768
9769                         if (epause->tx_pause)
9770                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9771                         else
9772                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9773
9774                         if (netif_running(dev))
9775                                 tg3_setup_flow_control(tp, 0, 0);
9776                 }
9777         } else {
9778                 int irq_sync = 0;
9779
9780                 if (netif_running(dev)) {
9781                         tg3_netif_stop(tp);
9782                         irq_sync = 1;
9783                 }
9784
9785                 tg3_full_lock(tp, irq_sync);
9786
9787                 if (epause->autoneg)
9788                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9789                 else
9790                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9791                 if (epause->rx_pause)
9792                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9793                 else
9794                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9795                 if (epause->tx_pause)
9796                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9797                 else
9798                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9799
9800                 if (netif_running(dev)) {
9801                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9802                         err = tg3_restart_hw(tp, 1);
9803                         if (!err)
9804                                 tg3_netif_start(tp);
9805                 }
9806
9807                 tg3_full_unlock(tp);
9808         }
9809
9810         return err;
9811 }
9812
9813 static u32 tg3_get_rx_csum(struct net_device *dev)
9814 {
9815         struct tg3 *tp = netdev_priv(dev);
9816         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9817 }
9818
9819 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9820 {
9821         struct tg3 *tp = netdev_priv(dev);
9822
9823         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9824                 if (data != 0)
9825                         return -EINVAL;
9826                 return 0;
9827         }
9828
9829         spin_lock_bh(&tp->lock);
9830         if (data)
9831                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9832         else
9833                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9834         spin_unlock_bh(&tp->lock);
9835
9836         return 0;
9837 }
9838
9839 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9840 {
9841         struct tg3 *tp = netdev_priv(dev);
9842
9843         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9844                 if (data != 0)
9845                         return -EINVAL;
9846                 return 0;
9847         }
9848
9849         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9850                 ethtool_op_set_tx_ipv6_csum(dev, data);
9851         else
9852                 ethtool_op_set_tx_csum(dev, data);
9853
9854         return 0;
9855 }
9856
9857 static int tg3_get_sset_count (struct net_device *dev, int sset)
9858 {
9859         switch (sset) {
9860         case ETH_SS_TEST:
9861                 return TG3_NUM_TEST;
9862         case ETH_SS_STATS:
9863                 return TG3_NUM_STATS;
9864         default:
9865                 return -EOPNOTSUPP;
9866         }
9867 }
9868
9869 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9870 {
9871         switch (stringset) {
9872         case ETH_SS_STATS:
9873                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9874                 break;
9875         case ETH_SS_TEST:
9876                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9877                 break;
9878         default:
9879                 WARN_ON(1);     /* we need a WARN() */
9880                 break;
9881         }
9882 }
9883
9884 static int tg3_phys_id(struct net_device *dev, u32 data)
9885 {
9886         struct tg3 *tp = netdev_priv(dev);
9887         int i;
9888
9889         if (!netif_running(tp->dev))
9890                 return -EAGAIN;
9891
9892         if (data == 0)
9893                 data = UINT_MAX / 2;
9894
9895         for (i = 0; i < (data * 2); i++) {
9896                 if ((i % 2) == 0)
9897                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9898                                            LED_CTRL_1000MBPS_ON |
9899                                            LED_CTRL_100MBPS_ON |
9900                                            LED_CTRL_10MBPS_ON |
9901                                            LED_CTRL_TRAFFIC_OVERRIDE |
9902                                            LED_CTRL_TRAFFIC_BLINK |
9903                                            LED_CTRL_TRAFFIC_LED);
9904
9905                 else
9906                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9907                                            LED_CTRL_TRAFFIC_OVERRIDE);
9908
9909                 if (msleep_interruptible(500))
9910                         break;
9911         }
9912         tw32(MAC_LED_CTRL, tp->led_ctrl);
9913         return 0;
9914 }
9915
9916 static void tg3_get_ethtool_stats (struct net_device *dev,
9917                                    struct ethtool_stats *estats, u64 *tmp_stats)
9918 {
9919         struct tg3 *tp = netdev_priv(dev);
9920         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9921 }
9922
9923 #define NVRAM_TEST_SIZE 0x100
9924 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9925 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9926 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9927 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9928 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9929
9930 static int tg3_test_nvram(struct tg3 *tp)
9931 {
9932         u32 csum, magic;
9933         __be32 *buf;
9934         int i, j, k, err = 0, size;
9935
9936         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9937                 return 0;
9938
9939         if (tg3_nvram_read(tp, 0, &magic) != 0)
9940                 return -EIO;
9941
9942         if (magic == TG3_EEPROM_MAGIC)
9943                 size = NVRAM_TEST_SIZE;
9944         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9945                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9946                     TG3_EEPROM_SB_FORMAT_1) {
9947                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9948                         case TG3_EEPROM_SB_REVISION_0:
9949                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9950                                 break;
9951                         case TG3_EEPROM_SB_REVISION_2:
9952                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9953                                 break;
9954                         case TG3_EEPROM_SB_REVISION_3:
9955                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9956                                 break;
9957                         default:
9958                                 return 0;
9959                         }
9960                 } else
9961                         return 0;
9962         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9963                 size = NVRAM_SELFBOOT_HW_SIZE;
9964         else
9965                 return -EIO;
9966
9967         buf = kmalloc(size, GFP_KERNEL);
9968         if (buf == NULL)
9969                 return -ENOMEM;
9970
9971         err = -EIO;
9972         for (i = 0, j = 0; i < size; i += 4, j++) {
9973                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9974                 if (err)
9975                         break;
9976         }
9977         if (i < size)
9978                 goto out;
9979
9980         /* Selfboot format */
9981         magic = be32_to_cpu(buf[0]);
9982         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9983             TG3_EEPROM_MAGIC_FW) {
9984                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9985
9986                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9987                     TG3_EEPROM_SB_REVISION_2) {
9988                         /* For rev 2, the csum doesn't include the MBA. */
9989                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9990                                 csum8 += buf8[i];
9991                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9992                                 csum8 += buf8[i];
9993                 } else {
9994                         for (i = 0; i < size; i++)
9995                                 csum8 += buf8[i];
9996                 }
9997
9998                 if (csum8 == 0) {
9999                         err = 0;
10000                         goto out;
10001                 }
10002
10003                 err = -EIO;
10004                 goto out;
10005         }
10006
10007         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10008             TG3_EEPROM_MAGIC_HW) {
10009                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10010                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10011                 u8 *buf8 = (u8 *) buf;
10012
10013                 /* Separate the parity bits and the data bytes.  */
10014                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10015                         if ((i == 0) || (i == 8)) {
10016                                 int l;
10017                                 u8 msk;
10018
10019                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10020                                         parity[k++] = buf8[i] & msk;
10021                                 i++;
10022                         }
10023                         else if (i == 16) {
10024                                 int l;
10025                                 u8 msk;
10026
10027                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10028                                         parity[k++] = buf8[i] & msk;
10029                                 i++;
10030
10031                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10032                                         parity[k++] = buf8[i] & msk;
10033                                 i++;
10034                         }
10035                         data[j++] = buf8[i];
10036                 }
10037
10038                 err = -EIO;
10039                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10040                         u8 hw8 = hweight8(data[i]);
10041
10042                         if ((hw8 & 0x1) && parity[i])
10043                                 goto out;
10044                         else if (!(hw8 & 0x1) && !parity[i])
10045                                 goto out;
10046                 }
10047                 err = 0;
10048                 goto out;
10049         }
10050
10051         /* Bootstrap checksum at offset 0x10 */
10052         csum = calc_crc((unsigned char *) buf, 0x10);
10053         if (csum != be32_to_cpu(buf[0x10/4]))
10054                 goto out;
10055
10056         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10057         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10058         if (csum != be32_to_cpu(buf[0xfc/4]))
10059                 goto out;
10060
10061         err = 0;
10062
10063 out:
10064         kfree(buf);
10065         return err;
10066 }
10067
10068 #define TG3_SERDES_TIMEOUT_SEC  2
10069 #define TG3_COPPER_TIMEOUT_SEC  6
10070
10071 static int tg3_test_link(struct tg3 *tp)
10072 {
10073         int i, max;
10074
10075         if (!netif_running(tp->dev))
10076                 return -ENODEV;
10077
10078         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10079                 max = TG3_SERDES_TIMEOUT_SEC;
10080         else
10081                 max = TG3_COPPER_TIMEOUT_SEC;
10082
10083         for (i = 0; i < max; i++) {
10084                 if (netif_carrier_ok(tp->dev))
10085                         return 0;
10086
10087                 if (msleep_interruptible(1000))
10088                         break;
10089         }
10090
10091         return -EIO;
10092 }
10093
10094 /* Only test the commonly used registers */
10095 static int tg3_test_registers(struct tg3 *tp)
10096 {
10097         int i, is_5705, is_5750;
10098         u32 offset, read_mask, write_mask, val, save_val, read_val;
10099         static struct {
10100                 u16 offset;
10101                 u16 flags;
10102 #define TG3_FL_5705     0x1
10103 #define TG3_FL_NOT_5705 0x2
10104 #define TG3_FL_NOT_5788 0x4
10105 #define TG3_FL_NOT_5750 0x8
10106                 u32 read_mask;
10107                 u32 write_mask;
10108         } reg_tbl[] = {
10109                 /* MAC Control Registers */
10110                 { MAC_MODE, TG3_FL_NOT_5705,
10111                         0x00000000, 0x00ef6f8c },
10112                 { MAC_MODE, TG3_FL_5705,
10113                         0x00000000, 0x01ef6b8c },
10114                 { MAC_STATUS, TG3_FL_NOT_5705,
10115                         0x03800107, 0x00000000 },
10116                 { MAC_STATUS, TG3_FL_5705,
10117                         0x03800100, 0x00000000 },
10118                 { MAC_ADDR_0_HIGH, 0x0000,
10119                         0x00000000, 0x0000ffff },
10120                 { MAC_ADDR_0_LOW, 0x0000,
10121                         0x00000000, 0xffffffff },
10122                 { MAC_RX_MTU_SIZE, 0x0000,
10123                         0x00000000, 0x0000ffff },
10124                 { MAC_TX_MODE, 0x0000,
10125                         0x00000000, 0x00000070 },
10126                 { MAC_TX_LENGTHS, 0x0000,
10127                         0x00000000, 0x00003fff },
10128                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10129                         0x00000000, 0x000007fc },
10130                 { MAC_RX_MODE, TG3_FL_5705,
10131                         0x00000000, 0x000007dc },
10132                 { MAC_HASH_REG_0, 0x0000,
10133                         0x00000000, 0xffffffff },
10134                 { MAC_HASH_REG_1, 0x0000,
10135                         0x00000000, 0xffffffff },
10136                 { MAC_HASH_REG_2, 0x0000,
10137                         0x00000000, 0xffffffff },
10138                 { MAC_HASH_REG_3, 0x0000,
10139                         0x00000000, 0xffffffff },
10140
10141                 /* Receive Data and Receive BD Initiator Control Registers. */
10142                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10143                         0x00000000, 0xffffffff },
10144                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10145                         0x00000000, 0xffffffff },
10146                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10147                         0x00000000, 0x00000003 },
10148                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10149                         0x00000000, 0xffffffff },
10150                 { RCVDBDI_STD_BD+0, 0x0000,
10151                         0x00000000, 0xffffffff },
10152                 { RCVDBDI_STD_BD+4, 0x0000,
10153                         0x00000000, 0xffffffff },
10154                 { RCVDBDI_STD_BD+8, 0x0000,
10155                         0x00000000, 0xffff0002 },
10156                 { RCVDBDI_STD_BD+0xc, 0x0000,
10157                         0x00000000, 0xffffffff },
10158
10159                 /* Receive BD Initiator Control Registers. */
10160                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10161                         0x00000000, 0xffffffff },
10162                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10163                         0x00000000, 0x000003ff },
10164                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10165                         0x00000000, 0xffffffff },
10166
10167                 /* Host Coalescing Control Registers. */
10168                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10169                         0x00000000, 0x00000004 },
10170                 { HOSTCC_MODE, TG3_FL_5705,
10171                         0x00000000, 0x000000f6 },
10172                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10173                         0x00000000, 0xffffffff },
10174                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10175                         0x00000000, 0x000003ff },
10176                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10177                         0x00000000, 0xffffffff },
10178                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10179                         0x00000000, 0x000003ff },
10180                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10181                         0x00000000, 0xffffffff },
10182                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10183                         0x00000000, 0x000000ff },
10184                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10185                         0x00000000, 0xffffffff },
10186                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10187                         0x00000000, 0x000000ff },
10188                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10189                         0x00000000, 0xffffffff },
10190                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10191                         0x00000000, 0xffffffff },
10192                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10193                         0x00000000, 0xffffffff },
10194                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10195                         0x00000000, 0x000000ff },
10196                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10197                         0x00000000, 0xffffffff },
10198                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10199                         0x00000000, 0x000000ff },
10200                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10201                         0x00000000, 0xffffffff },
10202                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10203                         0x00000000, 0xffffffff },
10204                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10205                         0x00000000, 0xffffffff },
10206                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10207                         0x00000000, 0xffffffff },
10208                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10209                         0x00000000, 0xffffffff },
10210                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10211                         0xffffffff, 0x00000000 },
10212                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10213                         0xffffffff, 0x00000000 },
10214
10215                 /* Buffer Manager Control Registers. */
10216                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10217                         0x00000000, 0x007fff80 },
10218                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10219                         0x00000000, 0x007fffff },
10220                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10221                         0x00000000, 0x0000003f },
10222                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10223                         0x00000000, 0x000001ff },
10224                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10225                         0x00000000, 0x000001ff },
10226                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10227                         0xffffffff, 0x00000000 },
10228                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10229                         0xffffffff, 0x00000000 },
10230
10231                 /* Mailbox Registers */
10232                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10233                         0x00000000, 0x000001ff },
10234                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10235                         0x00000000, 0x000001ff },
10236                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10237                         0x00000000, 0x000007ff },
10238                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10239                         0x00000000, 0x000001ff },
10240
10241                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10242         };
10243
10244         is_5705 = is_5750 = 0;
10245         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10246                 is_5705 = 1;
10247                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10248                         is_5750 = 1;
10249         }
10250
10251         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10252                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10253                         continue;
10254
10255                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10256                         continue;
10257
10258                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10259                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10260                         continue;
10261
10262                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10263                         continue;
10264
10265                 offset = (u32) reg_tbl[i].offset;
10266                 read_mask = reg_tbl[i].read_mask;
10267                 write_mask = reg_tbl[i].write_mask;
10268
10269                 /* Save the original register content */
10270                 save_val = tr32(offset);
10271
10272                 /* Determine the read-only value. */
10273                 read_val = save_val & read_mask;
10274
10275                 /* Write zero to the register, then make sure the read-only bits
10276                  * are not changed and the read/write bits are all zeros.
10277                  */
10278                 tw32(offset, 0);
10279
10280                 val = tr32(offset);
10281
10282                 /* Test the read-only and read/write bits. */
10283                 if (((val & read_mask) != read_val) || (val & write_mask))
10284                         goto out;
10285
10286                 /* Write ones to all the bits defined by RdMask and WrMask, then
10287                  * make sure the read-only bits are not changed and the
10288                  * read/write bits are all ones.
10289                  */
10290                 tw32(offset, read_mask | write_mask);
10291
10292                 val = tr32(offset);
10293
10294                 /* Test the read-only bits. */
10295                 if ((val & read_mask) != read_val)
10296                         goto out;
10297
10298                 /* Test the read/write bits. */
10299                 if ((val & write_mask) != write_mask)
10300                         goto out;
10301
10302                 tw32(offset, save_val);
10303         }
10304
10305         return 0;
10306
10307 out:
10308         if (netif_msg_hw(tp))
10309                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10310                        offset);
10311         tw32(offset, save_val);
10312         return -EIO;
10313 }
10314
10315 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10316 {
10317         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10318         int i;
10319         u32 j;
10320
10321         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10322                 for (j = 0; j < len; j += 4) {
10323                         u32 val;
10324
10325                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10326                         tg3_read_mem(tp, offset + j, &val);
10327                         if (val != test_pattern[i])
10328                                 return -EIO;
10329                 }
10330         }
10331         return 0;
10332 }
10333
10334 static int tg3_test_memory(struct tg3 *tp)
10335 {
10336         static struct mem_entry {
10337                 u32 offset;
10338                 u32 len;
10339         } mem_tbl_570x[] = {
10340                 { 0x00000000, 0x00b50},
10341                 { 0x00002000, 0x1c000},
10342                 { 0xffffffff, 0x00000}
10343         }, mem_tbl_5705[] = {
10344                 { 0x00000100, 0x0000c},
10345                 { 0x00000200, 0x00008},
10346                 { 0x00004000, 0x00800},
10347                 { 0x00006000, 0x01000},
10348                 { 0x00008000, 0x02000},
10349                 { 0x00010000, 0x0e000},
10350                 { 0xffffffff, 0x00000}
10351         }, mem_tbl_5755[] = {
10352                 { 0x00000200, 0x00008},
10353                 { 0x00004000, 0x00800},
10354                 { 0x00006000, 0x00800},
10355                 { 0x00008000, 0x02000},
10356                 { 0x00010000, 0x0c000},
10357                 { 0xffffffff, 0x00000}
10358         }, mem_tbl_5906[] = {
10359                 { 0x00000200, 0x00008},
10360                 { 0x00004000, 0x00400},
10361                 { 0x00006000, 0x00400},
10362                 { 0x00008000, 0x01000},
10363                 { 0x00010000, 0x01000},
10364                 { 0xffffffff, 0x00000}
10365         };
10366         struct mem_entry *mem_tbl;
10367         int err = 0;
10368         int i;
10369
10370         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10371                 mem_tbl = mem_tbl_5755;
10372         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10373                 mem_tbl = mem_tbl_5906;
10374         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10375                 mem_tbl = mem_tbl_5705;
10376         else
10377                 mem_tbl = mem_tbl_570x;
10378
10379         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10380                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10381                     mem_tbl[i].len)) != 0)
10382                         break;
10383         }
10384
10385         return err;
10386 }
10387
10388 #define TG3_MAC_LOOPBACK        0
10389 #define TG3_PHY_LOOPBACK        1
10390
10391 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10392 {
10393         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10394         u32 desc_idx, coal_now;
10395         struct sk_buff *skb, *rx_skb;
10396         u8 *tx_data;
10397         dma_addr_t map;
10398         int num_pkts, tx_len, rx_len, i, err;
10399         struct tg3_rx_buffer_desc *desc;
10400         struct tg3_napi *tnapi, *rnapi;
10401         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10402
10403         if (tp->irq_cnt > 1) {
10404                 tnapi = &tp->napi[1];
10405                 rnapi = &tp->napi[1];
10406         } else {
10407                 tnapi = &tp->napi[0];
10408                 rnapi = &tp->napi[0];
10409         }
10410         coal_now = tnapi->coal_now | rnapi->coal_now;
10411
10412         if (loopback_mode == TG3_MAC_LOOPBACK) {
10413                 /* HW errata - mac loopback fails in some cases on 5780.
10414                  * Normal traffic and PHY loopback are not affected by
10415                  * errata.
10416                  */
10417                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10418                         return 0;
10419
10420                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10421                            MAC_MODE_PORT_INT_LPBACK;
10422                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10423                         mac_mode |= MAC_MODE_LINK_POLARITY;
10424                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10425                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10426                 else
10427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10428                 tw32(MAC_MODE, mac_mode);
10429         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10430                 u32 val;
10431
10432                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10433                         tg3_phy_fet_toggle_apd(tp, false);
10434                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10435                 } else
10436                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10437
10438                 tg3_phy_toggle_automdix(tp, 0);
10439
10440                 tg3_writephy(tp, MII_BMCR, val);
10441                 udelay(40);
10442
10443                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10444                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10445                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10446                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10447                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10448                 } else
10449                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10450
10451                 /* reset to prevent losing 1st rx packet intermittently */
10452                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10453                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10454                         udelay(10);
10455                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10456                 }
10457                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10458                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10459                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10460                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10461                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10462                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10463                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10464                 }
10465                 tw32(MAC_MODE, mac_mode);
10466         }
10467         else
10468                 return -EINVAL;
10469
10470         err = -EIO;
10471
10472         tx_len = 1514;
10473         skb = netdev_alloc_skb(tp->dev, tx_len);
10474         if (!skb)
10475                 return -ENOMEM;
10476
10477         tx_data = skb_put(skb, tx_len);
10478         memcpy(tx_data, tp->dev->dev_addr, 6);
10479         memset(tx_data + 6, 0x0, 8);
10480
10481         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10482
10483         for (i = 14; i < tx_len; i++)
10484                 tx_data[i] = (u8) (i & 0xff);
10485
10486         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
10487                 dev_kfree_skb(skb);
10488                 return -EIO;
10489         }
10490
10491         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10492                rnapi->coal_now);
10493
10494         udelay(10);
10495
10496         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10497
10498         num_pkts = 0;
10499
10500         tg3_set_txd(tnapi, tnapi->tx_prod,
10501                     skb_shinfo(skb)->dma_head, tx_len, 0, 1);
10502
10503         tnapi->tx_prod++;
10504         num_pkts++;
10505
10506         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10507         tr32_mailbox(tnapi->prodmbox);
10508
10509         udelay(10);
10510
10511         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10512         for (i = 0; i < 35; i++) {
10513                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10514                        coal_now);
10515
10516                 udelay(10);
10517
10518                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10519                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10520                 if ((tx_idx == tnapi->tx_prod) &&
10521                     (rx_idx == (rx_start_idx + num_pkts)))
10522                         break;
10523         }
10524
10525         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
10526         dev_kfree_skb(skb);
10527
10528         if (tx_idx != tnapi->tx_prod)
10529                 goto out;
10530
10531         if (rx_idx != rx_start_idx + num_pkts)
10532                 goto out;
10533
10534         desc = &rnapi->rx_rcb[rx_start_idx];
10535         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10536         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10537         if (opaque_key != RXD_OPAQUE_RING_STD)
10538                 goto out;
10539
10540         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10541             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10542                 goto out;
10543
10544         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10545         if (rx_len != tx_len)
10546                 goto out;
10547
10548         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10549
10550         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10551         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10552
10553         for (i = 14; i < tx_len; i++) {
10554                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10555                         goto out;
10556         }
10557         err = 0;
10558
10559         /* tg3_free_rings will unmap and free the rx_skb */
10560 out:
10561         return err;
10562 }
10563
10564 #define TG3_MAC_LOOPBACK_FAILED         1
10565 #define TG3_PHY_LOOPBACK_FAILED         2
10566 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10567                                          TG3_PHY_LOOPBACK_FAILED)
10568
10569 static int tg3_test_loopback(struct tg3 *tp)
10570 {
10571         int err = 0;
10572         u32 cpmuctrl = 0;
10573
10574         if (!netif_running(tp->dev))
10575                 return TG3_LOOPBACK_FAILED;
10576
10577         err = tg3_reset_hw(tp, 1);
10578         if (err)
10579                 return TG3_LOOPBACK_FAILED;
10580
10581         /* Turn off gphy autopowerdown. */
10582         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10583                 tg3_phy_toggle_apd(tp, false);
10584
10585         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10586                 int i;
10587                 u32 status;
10588
10589                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10590
10591                 /* Wait for up to 40 microseconds to acquire lock. */
10592                 for (i = 0; i < 4; i++) {
10593                         status = tr32(TG3_CPMU_MUTEX_GNT);
10594                         if (status == CPMU_MUTEX_GNT_DRIVER)
10595                                 break;
10596                         udelay(10);
10597                 }
10598
10599                 if (status != CPMU_MUTEX_GNT_DRIVER)
10600                         return TG3_LOOPBACK_FAILED;
10601
10602                 /* Turn off link-based power management. */
10603                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10604                 tw32(TG3_CPMU_CTRL,
10605                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10606                                   CPMU_CTRL_LINK_AWARE_MODE));
10607         }
10608
10609         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10610                 err |= TG3_MAC_LOOPBACK_FAILED;
10611
10612         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10613                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10614
10615                 /* Release the mutex */
10616                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10617         }
10618
10619         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10620             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10621                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10622                         err |= TG3_PHY_LOOPBACK_FAILED;
10623         }
10624
10625         /* Re-enable gphy autopowerdown. */
10626         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10627                 tg3_phy_toggle_apd(tp, true);
10628
10629         return err;
10630 }
10631
10632 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10633                           u64 *data)
10634 {
10635         struct tg3 *tp = netdev_priv(dev);
10636
10637         if (tp->link_config.phy_is_low_power)
10638                 tg3_set_power_state(tp, PCI_D0);
10639
10640         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10641
10642         if (tg3_test_nvram(tp) != 0) {
10643                 etest->flags |= ETH_TEST_FL_FAILED;
10644                 data[0] = 1;
10645         }
10646         if (tg3_test_link(tp) != 0) {
10647                 etest->flags |= ETH_TEST_FL_FAILED;
10648                 data[1] = 1;
10649         }
10650         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10651                 int err, err2 = 0, irq_sync = 0;
10652
10653                 if (netif_running(dev)) {
10654                         tg3_phy_stop(tp);
10655                         tg3_netif_stop(tp);
10656                         irq_sync = 1;
10657                 }
10658
10659                 tg3_full_lock(tp, irq_sync);
10660
10661                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10662                 err = tg3_nvram_lock(tp);
10663                 tg3_halt_cpu(tp, RX_CPU_BASE);
10664                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10665                         tg3_halt_cpu(tp, TX_CPU_BASE);
10666                 if (!err)
10667                         tg3_nvram_unlock(tp);
10668
10669                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10670                         tg3_phy_reset(tp);
10671
10672                 if (tg3_test_registers(tp) != 0) {
10673                         etest->flags |= ETH_TEST_FL_FAILED;
10674                         data[2] = 1;
10675                 }
10676                 if (tg3_test_memory(tp) != 0) {
10677                         etest->flags |= ETH_TEST_FL_FAILED;
10678                         data[3] = 1;
10679                 }
10680                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10681                         etest->flags |= ETH_TEST_FL_FAILED;
10682
10683                 tg3_full_unlock(tp);
10684
10685                 if (tg3_test_interrupt(tp) != 0) {
10686                         etest->flags |= ETH_TEST_FL_FAILED;
10687                         data[5] = 1;
10688                 }
10689
10690                 tg3_full_lock(tp, 0);
10691
10692                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10693                 if (netif_running(dev)) {
10694                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10695                         err2 = tg3_restart_hw(tp, 1);
10696                         if (!err2)
10697                                 tg3_netif_start(tp);
10698                 }
10699
10700                 tg3_full_unlock(tp);
10701
10702                 if (irq_sync && !err2)
10703                         tg3_phy_start(tp);
10704         }
10705         if (tp->link_config.phy_is_low_power)
10706                 tg3_set_power_state(tp, PCI_D3hot);
10707
10708 }
10709
10710 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10711 {
10712         struct mii_ioctl_data *data = if_mii(ifr);
10713         struct tg3 *tp = netdev_priv(dev);
10714         int err;
10715
10716         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10717                 struct phy_device *phydev;
10718                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10719                         return -EAGAIN;
10720                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10721                 return phy_mii_ioctl(phydev, data, cmd);
10722         }
10723
10724         switch(cmd) {
10725         case SIOCGMIIPHY:
10726                 data->phy_id = tp->phy_addr;
10727
10728                 /* fallthru */
10729         case SIOCGMIIREG: {
10730                 u32 mii_regval;
10731
10732                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10733                         break;                  /* We have no PHY */
10734
10735                 if (tp->link_config.phy_is_low_power)
10736                         return -EAGAIN;
10737
10738                 spin_lock_bh(&tp->lock);
10739                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10740                 spin_unlock_bh(&tp->lock);
10741
10742                 data->val_out = mii_regval;
10743
10744                 return err;
10745         }
10746
10747         case SIOCSMIIREG:
10748                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10749                         break;                  /* We have no PHY */
10750
10751                 if (tp->link_config.phy_is_low_power)
10752                         return -EAGAIN;
10753
10754                 spin_lock_bh(&tp->lock);
10755                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10756                 spin_unlock_bh(&tp->lock);
10757
10758                 return err;
10759
10760         default:
10761                 /* do nothing */
10762                 break;
10763         }
10764         return -EOPNOTSUPP;
10765 }
10766
10767 #if TG3_VLAN_TAG_USED
10768 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10769 {
10770         struct tg3 *tp = netdev_priv(dev);
10771
10772         if (!netif_running(dev)) {
10773                 tp->vlgrp = grp;
10774                 return;
10775         }
10776
10777         tg3_netif_stop(tp);
10778
10779         tg3_full_lock(tp, 0);
10780
10781         tp->vlgrp = grp;
10782
10783         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10784         __tg3_set_rx_mode(dev);
10785
10786         tg3_netif_start(tp);
10787
10788         tg3_full_unlock(tp);
10789 }
10790 #endif
10791
10792 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10793 {
10794         struct tg3 *tp = netdev_priv(dev);
10795
10796         memcpy(ec, &tp->coal, sizeof(*ec));
10797         return 0;
10798 }
10799
10800 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10801 {
10802         struct tg3 *tp = netdev_priv(dev);
10803         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10804         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10805
10806         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10807                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10808                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10809                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10810                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10811         }
10812
10813         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10814             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10815             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10816             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10817             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10818             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10819             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10820             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10821             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10822             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10823                 return -EINVAL;
10824
10825         /* No rx interrupts will be generated if both are zero */
10826         if ((ec->rx_coalesce_usecs == 0) &&
10827             (ec->rx_max_coalesced_frames == 0))
10828                 return -EINVAL;
10829
10830         /* No tx interrupts will be generated if both are zero */
10831         if ((ec->tx_coalesce_usecs == 0) &&
10832             (ec->tx_max_coalesced_frames == 0))
10833                 return -EINVAL;
10834
10835         /* Only copy relevant parameters, ignore all others. */
10836         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10837         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10838         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10839         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10840         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10841         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10842         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10843         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10844         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10845
10846         if (netif_running(dev)) {
10847                 tg3_full_lock(tp, 0);
10848                 __tg3_set_coalesce(tp, &tp->coal);
10849                 tg3_full_unlock(tp);
10850         }
10851         return 0;
10852 }
10853
10854 static const struct ethtool_ops tg3_ethtool_ops = {
10855         .get_settings           = tg3_get_settings,
10856         .set_settings           = tg3_set_settings,
10857         .get_drvinfo            = tg3_get_drvinfo,
10858         .get_regs_len           = tg3_get_regs_len,
10859         .get_regs               = tg3_get_regs,
10860         .get_wol                = tg3_get_wol,
10861         .set_wol                = tg3_set_wol,
10862         .get_msglevel           = tg3_get_msglevel,
10863         .set_msglevel           = tg3_set_msglevel,
10864         .nway_reset             = tg3_nway_reset,
10865         .get_link               = ethtool_op_get_link,
10866         .get_eeprom_len         = tg3_get_eeprom_len,
10867         .get_eeprom             = tg3_get_eeprom,
10868         .set_eeprom             = tg3_set_eeprom,
10869         .get_ringparam          = tg3_get_ringparam,
10870         .set_ringparam          = tg3_set_ringparam,
10871         .get_pauseparam         = tg3_get_pauseparam,
10872         .set_pauseparam         = tg3_set_pauseparam,
10873         .get_rx_csum            = tg3_get_rx_csum,
10874         .set_rx_csum            = tg3_set_rx_csum,
10875         .set_tx_csum            = tg3_set_tx_csum,
10876         .set_sg                 = ethtool_op_set_sg,
10877         .set_tso                = tg3_set_tso,
10878         .self_test              = tg3_self_test,
10879         .get_strings            = tg3_get_strings,
10880         .phys_id                = tg3_phys_id,
10881         .get_ethtool_stats      = tg3_get_ethtool_stats,
10882         .get_coalesce           = tg3_get_coalesce,
10883         .set_coalesce           = tg3_set_coalesce,
10884         .get_sset_count         = tg3_get_sset_count,
10885 };
10886
10887 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10888 {
10889         u32 cursize, val, magic;
10890
10891         tp->nvram_size = EEPROM_CHIP_SIZE;
10892
10893         if (tg3_nvram_read(tp, 0, &magic) != 0)
10894                 return;
10895
10896         if ((magic != TG3_EEPROM_MAGIC) &&
10897             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10898             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10899                 return;
10900
10901         /*
10902          * Size the chip by reading offsets at increasing powers of two.
10903          * When we encounter our validation signature, we know the addressing
10904          * has wrapped around, and thus have our chip size.
10905          */
10906         cursize = 0x10;
10907
10908         while (cursize < tp->nvram_size) {
10909                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10910                         return;
10911
10912                 if (val == magic)
10913                         break;
10914
10915                 cursize <<= 1;
10916         }
10917
10918         tp->nvram_size = cursize;
10919 }
10920
10921 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10922 {
10923         u32 val;
10924
10925         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10926             tg3_nvram_read(tp, 0, &val) != 0)
10927                 return;
10928
10929         /* Selfboot format */
10930         if (val != TG3_EEPROM_MAGIC) {
10931                 tg3_get_eeprom_size(tp);
10932                 return;
10933         }
10934
10935         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10936                 if (val != 0) {
10937                         /* This is confusing.  We want to operate on the
10938                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10939                          * call will read from NVRAM and byteswap the data
10940                          * according to the byteswapping settings for all
10941                          * other register accesses.  This ensures the data we
10942                          * want will always reside in the lower 16-bits.
10943                          * However, the data in NVRAM is in LE format, which
10944                          * means the data from the NVRAM read will always be
10945                          * opposite the endianness of the CPU.  The 16-bit
10946                          * byteswap then brings the data to CPU endianness.
10947                          */
10948                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10949                         return;
10950                 }
10951         }
10952         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10953 }
10954
10955 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10956 {
10957         u32 nvcfg1;
10958
10959         nvcfg1 = tr32(NVRAM_CFG1);
10960         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10961                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10962         } else {
10963                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10964                 tw32(NVRAM_CFG1, nvcfg1);
10965         }
10966
10967         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10968             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10969                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10970                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10971                         tp->nvram_jedecnum = JEDEC_ATMEL;
10972                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10973                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10974                         break;
10975                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10976                         tp->nvram_jedecnum = JEDEC_ATMEL;
10977                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10978                         break;
10979                 case FLASH_VENDOR_ATMEL_EEPROM:
10980                         tp->nvram_jedecnum = JEDEC_ATMEL;
10981                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10982                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10983                         break;
10984                 case FLASH_VENDOR_ST:
10985                         tp->nvram_jedecnum = JEDEC_ST;
10986                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10987                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10988                         break;
10989                 case FLASH_VENDOR_SAIFUN:
10990                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10991                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10992                         break;
10993                 case FLASH_VENDOR_SST_SMALL:
10994                 case FLASH_VENDOR_SST_LARGE:
10995                         tp->nvram_jedecnum = JEDEC_SST;
10996                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10997                         break;
10998                 }
10999         } else {
11000                 tp->nvram_jedecnum = JEDEC_ATMEL;
11001                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11002                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11003         }
11004 }
11005
11006 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11007 {
11008         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11009         case FLASH_5752PAGE_SIZE_256:
11010                 tp->nvram_pagesize = 256;
11011                 break;
11012         case FLASH_5752PAGE_SIZE_512:
11013                 tp->nvram_pagesize = 512;
11014                 break;
11015         case FLASH_5752PAGE_SIZE_1K:
11016                 tp->nvram_pagesize = 1024;
11017                 break;
11018         case FLASH_5752PAGE_SIZE_2K:
11019                 tp->nvram_pagesize = 2048;
11020                 break;
11021         case FLASH_5752PAGE_SIZE_4K:
11022                 tp->nvram_pagesize = 4096;
11023                 break;
11024         case FLASH_5752PAGE_SIZE_264:
11025                 tp->nvram_pagesize = 264;
11026                 break;
11027         case FLASH_5752PAGE_SIZE_528:
11028                 tp->nvram_pagesize = 528;
11029                 break;
11030         }
11031 }
11032
11033 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11034 {
11035         u32 nvcfg1;
11036
11037         nvcfg1 = tr32(NVRAM_CFG1);
11038
11039         /* NVRAM protection for TPM */
11040         if (nvcfg1 & (1 << 27))
11041                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11042
11043         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11044         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11045         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11046                 tp->nvram_jedecnum = JEDEC_ATMEL;
11047                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11048                 break;
11049         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11050                 tp->nvram_jedecnum = JEDEC_ATMEL;
11051                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11052                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11053                 break;
11054         case FLASH_5752VENDOR_ST_M45PE10:
11055         case FLASH_5752VENDOR_ST_M45PE20:
11056         case FLASH_5752VENDOR_ST_M45PE40:
11057                 tp->nvram_jedecnum = JEDEC_ST;
11058                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11059                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11060                 break;
11061         }
11062
11063         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11064                 tg3_nvram_get_pagesize(tp, nvcfg1);
11065         } else {
11066                 /* For eeprom, set pagesize to maximum eeprom size */
11067                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11068
11069                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11070                 tw32(NVRAM_CFG1, nvcfg1);
11071         }
11072 }
11073
11074 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11075 {
11076         u32 nvcfg1, protect = 0;
11077
11078         nvcfg1 = tr32(NVRAM_CFG1);
11079
11080         /* NVRAM protection for TPM */
11081         if (nvcfg1 & (1 << 27)) {
11082                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11083                 protect = 1;
11084         }
11085
11086         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11087         switch (nvcfg1) {
11088         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11089         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11090         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11091         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11092                 tp->nvram_jedecnum = JEDEC_ATMEL;
11093                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11094                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11095                 tp->nvram_pagesize = 264;
11096                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11097                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11098                         tp->nvram_size = (protect ? 0x3e200 :
11099                                           TG3_NVRAM_SIZE_512KB);
11100                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11101                         tp->nvram_size = (protect ? 0x1f200 :
11102                                           TG3_NVRAM_SIZE_256KB);
11103                 else
11104                         tp->nvram_size = (protect ? 0x1f200 :
11105                                           TG3_NVRAM_SIZE_128KB);
11106                 break;
11107         case FLASH_5752VENDOR_ST_M45PE10:
11108         case FLASH_5752VENDOR_ST_M45PE20:
11109         case FLASH_5752VENDOR_ST_M45PE40:
11110                 tp->nvram_jedecnum = JEDEC_ST;
11111                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11112                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11113                 tp->nvram_pagesize = 256;
11114                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11115                         tp->nvram_size = (protect ?
11116                                           TG3_NVRAM_SIZE_64KB :
11117                                           TG3_NVRAM_SIZE_128KB);
11118                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11119                         tp->nvram_size = (protect ?
11120                                           TG3_NVRAM_SIZE_64KB :
11121                                           TG3_NVRAM_SIZE_256KB);
11122                 else
11123                         tp->nvram_size = (protect ?
11124                                           TG3_NVRAM_SIZE_128KB :
11125                                           TG3_NVRAM_SIZE_512KB);
11126                 break;
11127         }
11128 }
11129
11130 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11131 {
11132         u32 nvcfg1;
11133
11134         nvcfg1 = tr32(NVRAM_CFG1);
11135
11136         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11137         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11138         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11139         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11140         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11141                 tp->nvram_jedecnum = JEDEC_ATMEL;
11142                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11143                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11144
11145                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11146                 tw32(NVRAM_CFG1, nvcfg1);
11147                 break;
11148         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11149         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11150         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11151         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11152                 tp->nvram_jedecnum = JEDEC_ATMEL;
11153                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11154                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11155                 tp->nvram_pagesize = 264;
11156                 break;
11157         case FLASH_5752VENDOR_ST_M45PE10:
11158         case FLASH_5752VENDOR_ST_M45PE20:
11159         case FLASH_5752VENDOR_ST_M45PE40:
11160                 tp->nvram_jedecnum = JEDEC_ST;
11161                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11162                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11163                 tp->nvram_pagesize = 256;
11164                 break;
11165         }
11166 }
11167
11168 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11169 {
11170         u32 nvcfg1, protect = 0;
11171
11172         nvcfg1 = tr32(NVRAM_CFG1);
11173
11174         /* NVRAM protection for TPM */
11175         if (nvcfg1 & (1 << 27)) {
11176                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11177                 protect = 1;
11178         }
11179
11180         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11181         switch (nvcfg1) {
11182         case FLASH_5761VENDOR_ATMEL_ADB021D:
11183         case FLASH_5761VENDOR_ATMEL_ADB041D:
11184         case FLASH_5761VENDOR_ATMEL_ADB081D:
11185         case FLASH_5761VENDOR_ATMEL_ADB161D:
11186         case FLASH_5761VENDOR_ATMEL_MDB021D:
11187         case FLASH_5761VENDOR_ATMEL_MDB041D:
11188         case FLASH_5761VENDOR_ATMEL_MDB081D:
11189         case FLASH_5761VENDOR_ATMEL_MDB161D:
11190                 tp->nvram_jedecnum = JEDEC_ATMEL;
11191                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11192                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11193                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11194                 tp->nvram_pagesize = 256;
11195                 break;
11196         case FLASH_5761VENDOR_ST_A_M45PE20:
11197         case FLASH_5761VENDOR_ST_A_M45PE40:
11198         case FLASH_5761VENDOR_ST_A_M45PE80:
11199         case FLASH_5761VENDOR_ST_A_M45PE16:
11200         case FLASH_5761VENDOR_ST_M_M45PE20:
11201         case FLASH_5761VENDOR_ST_M_M45PE40:
11202         case FLASH_5761VENDOR_ST_M_M45PE80:
11203         case FLASH_5761VENDOR_ST_M_M45PE16:
11204                 tp->nvram_jedecnum = JEDEC_ST;
11205                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11206                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11207                 tp->nvram_pagesize = 256;
11208                 break;
11209         }
11210
11211         if (protect) {
11212                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11213         } else {
11214                 switch (nvcfg1) {
11215                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11216                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11217                 case FLASH_5761VENDOR_ST_A_M45PE16:
11218                 case FLASH_5761VENDOR_ST_M_M45PE16:
11219                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11220                         break;
11221                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11222                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11223                 case FLASH_5761VENDOR_ST_A_M45PE80:
11224                 case FLASH_5761VENDOR_ST_M_M45PE80:
11225                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11226                         break;
11227                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11228                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11229                 case FLASH_5761VENDOR_ST_A_M45PE40:
11230                 case FLASH_5761VENDOR_ST_M_M45PE40:
11231                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11232                         break;
11233                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11234                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11235                 case FLASH_5761VENDOR_ST_A_M45PE20:
11236                 case FLASH_5761VENDOR_ST_M_M45PE20:
11237                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11238                         break;
11239                 }
11240         }
11241 }
11242
11243 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11244 {
11245         tp->nvram_jedecnum = JEDEC_ATMEL;
11246         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11247         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11248 }
11249
11250 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11251 {
11252         u32 nvcfg1;
11253
11254         nvcfg1 = tr32(NVRAM_CFG1);
11255
11256         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11257         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11258         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11259                 tp->nvram_jedecnum = JEDEC_ATMEL;
11260                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11262
11263                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11264                 tw32(NVRAM_CFG1, nvcfg1);
11265                 return;
11266         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11267         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11268         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11269         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11270         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11271         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11272         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11273                 tp->nvram_jedecnum = JEDEC_ATMEL;
11274                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11275                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11276
11277                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11278                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11279                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11280                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11281                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11282                         break;
11283                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11284                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11285                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11286                         break;
11287                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11288                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11289                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11290                         break;
11291                 }
11292                 break;
11293         case FLASH_5752VENDOR_ST_M45PE10:
11294         case FLASH_5752VENDOR_ST_M45PE20:
11295         case FLASH_5752VENDOR_ST_M45PE40:
11296                 tp->nvram_jedecnum = JEDEC_ST;
11297                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11298                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11299
11300                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11301                 case FLASH_5752VENDOR_ST_M45PE10:
11302                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11303                         break;
11304                 case FLASH_5752VENDOR_ST_M45PE20:
11305                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11306                         break;
11307                 case FLASH_5752VENDOR_ST_M45PE40:
11308                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11309                         break;
11310                 }
11311                 break;
11312         default:
11313                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11314                 return;
11315         }
11316
11317         tg3_nvram_get_pagesize(tp, nvcfg1);
11318         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11319                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11320 }
11321
11322
11323 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11324 {
11325         u32 nvcfg1;
11326
11327         nvcfg1 = tr32(NVRAM_CFG1);
11328
11329         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11330         case FLASH_5717VENDOR_ATMEL_EEPROM:
11331         case FLASH_5717VENDOR_MICRO_EEPROM:
11332                 tp->nvram_jedecnum = JEDEC_ATMEL;
11333                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11334                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11335
11336                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11337                 tw32(NVRAM_CFG1, nvcfg1);
11338                 return;
11339         case FLASH_5717VENDOR_ATMEL_MDB011D:
11340         case FLASH_5717VENDOR_ATMEL_ADB011B:
11341         case FLASH_5717VENDOR_ATMEL_ADB011D:
11342         case FLASH_5717VENDOR_ATMEL_MDB021D:
11343         case FLASH_5717VENDOR_ATMEL_ADB021B:
11344         case FLASH_5717VENDOR_ATMEL_ADB021D:
11345         case FLASH_5717VENDOR_ATMEL_45USPT:
11346                 tp->nvram_jedecnum = JEDEC_ATMEL;
11347                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11348                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11349
11350                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11351                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11352                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11353                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11354                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11355                         break;
11356                 default:
11357                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11358                         break;
11359                 }
11360                 break;
11361         case FLASH_5717VENDOR_ST_M_M25PE10:
11362         case FLASH_5717VENDOR_ST_A_M25PE10:
11363         case FLASH_5717VENDOR_ST_M_M45PE10:
11364         case FLASH_5717VENDOR_ST_A_M45PE10:
11365         case FLASH_5717VENDOR_ST_M_M25PE20:
11366         case FLASH_5717VENDOR_ST_A_M25PE20:
11367         case FLASH_5717VENDOR_ST_M_M45PE20:
11368         case FLASH_5717VENDOR_ST_A_M45PE20:
11369         case FLASH_5717VENDOR_ST_25USPT:
11370         case FLASH_5717VENDOR_ST_45USPT:
11371                 tp->nvram_jedecnum = JEDEC_ST;
11372                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11373                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11374
11375                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11376                 case FLASH_5717VENDOR_ST_M_M25PE20:
11377                 case FLASH_5717VENDOR_ST_A_M25PE20:
11378                 case FLASH_5717VENDOR_ST_M_M45PE20:
11379                 case FLASH_5717VENDOR_ST_A_M45PE20:
11380                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11381                         break;
11382                 default:
11383                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11384                         break;
11385                 }
11386                 break;
11387         default:
11388                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11389                 return;
11390         }
11391
11392         tg3_nvram_get_pagesize(tp, nvcfg1);
11393         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11394                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11395 }
11396
11397 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11398 static void __devinit tg3_nvram_init(struct tg3 *tp)
11399 {
11400         tw32_f(GRC_EEPROM_ADDR,
11401              (EEPROM_ADDR_FSM_RESET |
11402               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11403                EEPROM_ADDR_CLKPERD_SHIFT)));
11404
11405         msleep(1);
11406
11407         /* Enable seeprom accesses. */
11408         tw32_f(GRC_LOCAL_CTRL,
11409              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11410         udelay(100);
11411
11412         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11413             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11414                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11415
11416                 if (tg3_nvram_lock(tp)) {
11417                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11418                                "tg3_nvram_init failed.\n", tp->dev->name);
11419                         return;
11420                 }
11421                 tg3_enable_nvram_access(tp);
11422
11423                 tp->nvram_size = 0;
11424
11425                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11426                         tg3_get_5752_nvram_info(tp);
11427                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11428                         tg3_get_5755_nvram_info(tp);
11429                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11430                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11431                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11432                         tg3_get_5787_nvram_info(tp);
11433                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11434                         tg3_get_5761_nvram_info(tp);
11435                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11436                         tg3_get_5906_nvram_info(tp);
11437                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11438                         tg3_get_57780_nvram_info(tp);
11439                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11440                         tg3_get_5717_nvram_info(tp);
11441                 else
11442                         tg3_get_nvram_info(tp);
11443
11444                 if (tp->nvram_size == 0)
11445                         tg3_get_nvram_size(tp);
11446
11447                 tg3_disable_nvram_access(tp);
11448                 tg3_nvram_unlock(tp);
11449
11450         } else {
11451                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11452
11453                 tg3_get_eeprom_size(tp);
11454         }
11455 }
11456
11457 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11458                                     u32 offset, u32 len, u8 *buf)
11459 {
11460         int i, j, rc = 0;
11461         u32 val;
11462
11463         for (i = 0; i < len; i += 4) {
11464                 u32 addr;
11465                 __be32 data;
11466
11467                 addr = offset + i;
11468
11469                 memcpy(&data, buf + i, 4);
11470
11471                 /*
11472                  * The SEEPROM interface expects the data to always be opposite
11473                  * the native endian format.  We accomplish this by reversing
11474                  * all the operations that would have been performed on the
11475                  * data from a call to tg3_nvram_read_be32().
11476                  */
11477                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11478
11479                 val = tr32(GRC_EEPROM_ADDR);
11480                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11481
11482                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11483                         EEPROM_ADDR_READ);
11484                 tw32(GRC_EEPROM_ADDR, val |
11485                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11486                         (addr & EEPROM_ADDR_ADDR_MASK) |
11487                         EEPROM_ADDR_START |
11488                         EEPROM_ADDR_WRITE);
11489
11490                 for (j = 0; j < 1000; j++) {
11491                         val = tr32(GRC_EEPROM_ADDR);
11492
11493                         if (val & EEPROM_ADDR_COMPLETE)
11494                                 break;
11495                         msleep(1);
11496                 }
11497                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11498                         rc = -EBUSY;
11499                         break;
11500                 }
11501         }
11502
11503         return rc;
11504 }
11505
11506 /* offset and length are dword aligned */
11507 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11508                 u8 *buf)
11509 {
11510         int ret = 0;
11511         u32 pagesize = tp->nvram_pagesize;
11512         u32 pagemask = pagesize - 1;
11513         u32 nvram_cmd;
11514         u8 *tmp;
11515
11516         tmp = kmalloc(pagesize, GFP_KERNEL);
11517         if (tmp == NULL)
11518                 return -ENOMEM;
11519
11520         while (len) {
11521                 int j;
11522                 u32 phy_addr, page_off, size;
11523
11524                 phy_addr = offset & ~pagemask;
11525
11526                 for (j = 0; j < pagesize; j += 4) {
11527                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11528                                                   (__be32 *) (tmp + j));
11529                         if (ret)
11530                                 break;
11531                 }
11532                 if (ret)
11533                         break;
11534
11535                 page_off = offset & pagemask;
11536                 size = pagesize;
11537                 if (len < size)
11538                         size = len;
11539
11540                 len -= size;
11541
11542                 memcpy(tmp + page_off, buf, size);
11543
11544                 offset = offset + (pagesize - page_off);
11545
11546                 tg3_enable_nvram_access(tp);
11547
11548                 /*
11549                  * Before we can erase the flash page, we need
11550                  * to issue a special "write enable" command.
11551                  */
11552                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11553
11554                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11555                         break;
11556
11557                 /* Erase the target page */
11558                 tw32(NVRAM_ADDR, phy_addr);
11559
11560                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11561                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11562
11563                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11564                         break;
11565
11566                 /* Issue another write enable to start the write. */
11567                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11568
11569                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11570                         break;
11571
11572                 for (j = 0; j < pagesize; j += 4) {
11573                         __be32 data;
11574
11575                         data = *((__be32 *) (tmp + j));
11576
11577                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11578
11579                         tw32(NVRAM_ADDR, phy_addr + j);
11580
11581                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11582                                 NVRAM_CMD_WR;
11583
11584                         if (j == 0)
11585                                 nvram_cmd |= NVRAM_CMD_FIRST;
11586                         else if (j == (pagesize - 4))
11587                                 nvram_cmd |= NVRAM_CMD_LAST;
11588
11589                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11590                                 break;
11591                 }
11592                 if (ret)
11593                         break;
11594         }
11595
11596         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11597         tg3_nvram_exec_cmd(tp, nvram_cmd);
11598
11599         kfree(tmp);
11600
11601         return ret;
11602 }
11603
11604 /* offset and length are dword aligned */
11605 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11606                 u8 *buf)
11607 {
11608         int i, ret = 0;
11609
11610         for (i = 0; i < len; i += 4, offset += 4) {
11611                 u32 page_off, phy_addr, nvram_cmd;
11612                 __be32 data;
11613
11614                 memcpy(&data, buf + i, 4);
11615                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11616
11617                 page_off = offset % tp->nvram_pagesize;
11618
11619                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11620
11621                 tw32(NVRAM_ADDR, phy_addr);
11622
11623                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11624
11625                 if ((page_off == 0) || (i == 0))
11626                         nvram_cmd |= NVRAM_CMD_FIRST;
11627                 if (page_off == (tp->nvram_pagesize - 4))
11628                         nvram_cmd |= NVRAM_CMD_LAST;
11629
11630                 if (i == (len - 4))
11631                         nvram_cmd |= NVRAM_CMD_LAST;
11632
11633                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11634                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11635                     (tp->nvram_jedecnum == JEDEC_ST) &&
11636                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11637
11638                         if ((ret = tg3_nvram_exec_cmd(tp,
11639                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11640                                 NVRAM_CMD_DONE)))
11641
11642                                 break;
11643                 }
11644                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11645                         /* We always do complete word writes to eeprom. */
11646                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11647                 }
11648
11649                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11650                         break;
11651         }
11652         return ret;
11653 }
11654
11655 /* offset and length are dword aligned */
11656 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11657 {
11658         int ret;
11659
11660         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11661                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11662                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11663                 udelay(40);
11664         }
11665
11666         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11667                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11668         }
11669         else {
11670                 u32 grc_mode;
11671
11672                 ret = tg3_nvram_lock(tp);
11673                 if (ret)
11674                         return ret;
11675
11676                 tg3_enable_nvram_access(tp);
11677                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11678                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11679                         tw32(NVRAM_WRITE1, 0x406);
11680
11681                 grc_mode = tr32(GRC_MODE);
11682                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11683
11684                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11685                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11686
11687                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11688                                 buf);
11689                 }
11690                 else {
11691                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11692                                 buf);
11693                 }
11694
11695                 grc_mode = tr32(GRC_MODE);
11696                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11697
11698                 tg3_disable_nvram_access(tp);
11699                 tg3_nvram_unlock(tp);
11700         }
11701
11702         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11703                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11704                 udelay(40);
11705         }
11706
11707         return ret;
11708 }
11709
11710 struct subsys_tbl_ent {
11711         u16 subsys_vendor, subsys_devid;
11712         u32 phy_id;
11713 };
11714
11715 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11716         /* Broadcom boards. */
11717         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11718         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11719         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11720         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11721         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11722         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11723         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11724         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11725         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11726         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11727         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11728
11729         /* 3com boards. */
11730         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11731         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11732         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11733         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11734         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11735
11736         /* DELL boards. */
11737         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11738         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11739         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11740         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11741
11742         /* Compaq boards. */
11743         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11744         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11745         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11746         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11747         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11748
11749         /* IBM boards. */
11750         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11751 };
11752
11753 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11754 {
11755         int i;
11756
11757         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11758                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11759                      tp->pdev->subsystem_vendor) &&
11760                     (subsys_id_to_phy_id[i].subsys_devid ==
11761                      tp->pdev->subsystem_device))
11762                         return &subsys_id_to_phy_id[i];
11763         }
11764         return NULL;
11765 }
11766
11767 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11768 {
11769         u32 val;
11770         u16 pmcsr;
11771
11772         /* On some early chips the SRAM cannot be accessed in D3hot state,
11773          * so need make sure we're in D0.
11774          */
11775         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11776         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11777         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11778         msleep(1);
11779
11780         /* Make sure register accesses (indirect or otherwise)
11781          * will function correctly.
11782          */
11783         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11784                                tp->misc_host_ctrl);
11785
11786         /* The memory arbiter has to be enabled in order for SRAM accesses
11787          * to succeed.  Normally on powerup the tg3 chip firmware will make
11788          * sure it is enabled, but other entities such as system netboot
11789          * code might disable it.
11790          */
11791         val = tr32(MEMARB_MODE);
11792         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11793
11794         tp->phy_id = PHY_ID_INVALID;
11795         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11796
11797         /* Assume an onboard device and WOL capable by default.  */
11798         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11799
11800         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11801                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11802                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11803                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11804                 }
11805                 val = tr32(VCPU_CFGSHDW);
11806                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11807                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11808                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11809                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11810                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11811                 goto done;
11812         }
11813
11814         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11815         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11816                 u32 nic_cfg, led_cfg;
11817                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11818                 int eeprom_phy_serdes = 0;
11819
11820                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11821                 tp->nic_sram_data_cfg = nic_cfg;
11822
11823                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11824                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11825                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11826                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11827                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11828                     (ver > 0) && (ver < 0x100))
11829                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11830
11831                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11832                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11833
11834                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11835                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11836                         eeprom_phy_serdes = 1;
11837
11838                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11839                 if (nic_phy_id != 0) {
11840                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11841                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11842
11843                         eeprom_phy_id  = (id1 >> 16) << 10;
11844                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11845                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11846                 } else
11847                         eeprom_phy_id = 0;
11848
11849                 tp->phy_id = eeprom_phy_id;
11850                 if (eeprom_phy_serdes) {
11851                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11852                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11853                         else
11854                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11855                 }
11856
11857                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11858                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11859                                     SHASTA_EXT_LED_MODE_MASK);
11860                 else
11861                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11862
11863                 switch (led_cfg) {
11864                 default:
11865                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11866                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11867                         break;
11868
11869                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11870                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11871                         break;
11872
11873                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11874                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11875
11876                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11877                          * read on some older 5700/5701 bootcode.
11878                          */
11879                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11880                             ASIC_REV_5700 ||
11881                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11882                             ASIC_REV_5701)
11883                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11884
11885                         break;
11886
11887                 case SHASTA_EXT_LED_SHARED:
11888                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11889                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11890                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11891                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11892                                                  LED_CTRL_MODE_PHY_2);
11893                         break;
11894
11895                 case SHASTA_EXT_LED_MAC:
11896                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11897                         break;
11898
11899                 case SHASTA_EXT_LED_COMBO:
11900                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11901                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11902                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11903                                                  LED_CTRL_MODE_PHY_2);
11904                         break;
11905
11906                 }
11907
11908                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11909                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11910                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11911                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11912
11913                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11914                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11915
11916                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11917                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11918                         if ((tp->pdev->subsystem_vendor ==
11919                              PCI_VENDOR_ID_ARIMA) &&
11920                             (tp->pdev->subsystem_device == 0x205a ||
11921                              tp->pdev->subsystem_device == 0x2063))
11922                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11923                 } else {
11924                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11925                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11926                 }
11927
11928                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11929                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11930                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11931                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11932                 }
11933
11934                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11935                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11936                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11937
11938                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11939                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11940                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11941
11942                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11943                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11944                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11945
11946                 if (cfg2 & (1 << 17))
11947                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11948
11949                 /* serdes signal pre-emphasis in register 0x590 set by */
11950                 /* bootcode if bit 18 is set */
11951                 if (cfg2 & (1 << 18))
11952                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11953
11954                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11955                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11956                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11957                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11958
11959                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11960                         u32 cfg3;
11961
11962                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11963                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11964                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11965                 }
11966
11967                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11968                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11969                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11970                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11971                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11972                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11973         }
11974 done:
11975         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11976         device_set_wakeup_enable(&tp->pdev->dev,
11977                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11978 }
11979
11980 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11981 {
11982         int i;
11983         u32 val;
11984
11985         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11986         tw32(OTP_CTRL, cmd);
11987
11988         /* Wait for up to 1 ms for command to execute. */
11989         for (i = 0; i < 100; i++) {
11990                 val = tr32(OTP_STATUS);
11991                 if (val & OTP_STATUS_CMD_DONE)
11992                         break;
11993                 udelay(10);
11994         }
11995
11996         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11997 }
11998
11999 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12000  * configuration is a 32-bit value that straddles the alignment boundary.
12001  * We do two 32-bit reads and then shift and merge the results.
12002  */
12003 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12004 {
12005         u32 bhalf_otp, thalf_otp;
12006
12007         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12008
12009         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12010                 return 0;
12011
12012         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12013
12014         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12015                 return 0;
12016
12017         thalf_otp = tr32(OTP_READ_DATA);
12018
12019         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12020
12021         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12022                 return 0;
12023
12024         bhalf_otp = tr32(OTP_READ_DATA);
12025
12026         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12027 }
12028
12029 static int __devinit tg3_phy_probe(struct tg3 *tp)
12030 {
12031         u32 hw_phy_id_1, hw_phy_id_2;
12032         u32 hw_phy_id, hw_phy_id_masked;
12033         int err;
12034
12035         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12036                 return tg3_phy_init(tp);
12037
12038         /* Reading the PHY ID register can conflict with ASF
12039          * firmware access to the PHY hardware.
12040          */
12041         err = 0;
12042         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12043             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12044                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12045         } else {
12046                 /* Now read the physical PHY_ID from the chip and verify
12047                  * that it is sane.  If it doesn't look good, we fall back
12048                  * to either the hard-coded table based PHY_ID and failing
12049                  * that the value found in the eeprom area.
12050                  */
12051                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12052                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12053
12054                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12055                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12056                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12057
12058                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12059         }
12060
12061         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12062                 tp->phy_id = hw_phy_id;
12063                 if (hw_phy_id_masked == PHY_ID_BCM8002)
12064                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12065                 else
12066                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12067         } else {
12068                 if (tp->phy_id != PHY_ID_INVALID) {
12069                         /* Do nothing, phy ID already set up in
12070                          * tg3_get_eeprom_hw_cfg().
12071                          */
12072                 } else {
12073                         struct subsys_tbl_ent *p;
12074
12075                         /* No eeprom signature?  Try the hardcoded
12076                          * subsys device table.
12077                          */
12078                         p = lookup_by_subsys(tp);
12079                         if (!p)
12080                                 return -ENODEV;
12081
12082                         tp->phy_id = p->phy_id;
12083                         if (!tp->phy_id ||
12084                             tp->phy_id == PHY_ID_BCM8002)
12085                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12086                 }
12087         }
12088
12089         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12090             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12091             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12092                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12093
12094                 tg3_readphy(tp, MII_BMSR, &bmsr);
12095                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12096                     (bmsr & BMSR_LSTATUS))
12097                         goto skip_phy_reset;
12098
12099                 err = tg3_phy_reset(tp);
12100                 if (err)
12101                         return err;
12102
12103                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12104                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12105                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12106                 tg3_ctrl = 0;
12107                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12108                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12109                                     MII_TG3_CTRL_ADV_1000_FULL);
12110                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12111                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12112                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12113                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12114                 }
12115
12116                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12117                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12118                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12119                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12120                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12121
12122                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12123                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12124
12125                         tg3_writephy(tp, MII_BMCR,
12126                                      BMCR_ANENABLE | BMCR_ANRESTART);
12127                 }
12128                 tg3_phy_set_wirespeed(tp);
12129
12130                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12131                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12132                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12133         }
12134
12135 skip_phy_reset:
12136         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12137                 err = tg3_init_5401phy_dsp(tp);
12138                 if (err)
12139                         return err;
12140         }
12141
12142         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12143                 err = tg3_init_5401phy_dsp(tp);
12144         }
12145
12146         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12147                 tp->link_config.advertising =
12148                         (ADVERTISED_1000baseT_Half |
12149                          ADVERTISED_1000baseT_Full |
12150                          ADVERTISED_Autoneg |
12151                          ADVERTISED_FIBRE);
12152         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12153                 tp->link_config.advertising &=
12154                         ~(ADVERTISED_1000baseT_Half |
12155                           ADVERTISED_1000baseT_Full);
12156
12157         return err;
12158 }
12159
12160 static void __devinit tg3_read_partno(struct tg3 *tp)
12161 {
12162         unsigned char vpd_data[256];   /* in little-endian format */
12163         unsigned int i;
12164         u32 magic;
12165
12166         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12167             tg3_nvram_read(tp, 0x0, &magic))
12168                 goto out_not_found;
12169
12170         if (magic == TG3_EEPROM_MAGIC) {
12171                 for (i = 0; i < 256; i += 4) {
12172                         u32 tmp;
12173
12174                         /* The data is in little-endian format in NVRAM.
12175                          * Use the big-endian read routines to preserve
12176                          * the byte order as it exists in NVRAM.
12177                          */
12178                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12179                                 goto out_not_found;
12180
12181                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12182                 }
12183         } else {
12184                 int vpd_cap;
12185
12186                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12187                 for (i = 0; i < 256; i += 4) {
12188                         u32 tmp, j = 0;
12189                         __le32 v;
12190                         u16 tmp16;
12191
12192                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12193                                               i);
12194                         while (j++ < 100) {
12195                                 pci_read_config_word(tp->pdev, vpd_cap +
12196                                                      PCI_VPD_ADDR, &tmp16);
12197                                 if (tmp16 & 0x8000)
12198                                         break;
12199                                 msleep(1);
12200                         }
12201                         if (!(tmp16 & 0x8000))
12202                                 goto out_not_found;
12203
12204                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12205                                               &tmp);
12206                         v = cpu_to_le32(tmp);
12207                         memcpy(&vpd_data[i], &v, sizeof(v));
12208                 }
12209         }
12210
12211         /* Now parse and find the part number. */
12212         for (i = 0; i < 254; ) {
12213                 unsigned char val = vpd_data[i];
12214                 unsigned int block_end;
12215
12216                 if (val == 0x82 || val == 0x91) {
12217                         i = (i + 3 +
12218                              (vpd_data[i + 1] +
12219                               (vpd_data[i + 2] << 8)));
12220                         continue;
12221                 }
12222
12223                 if (val != 0x90)
12224                         goto out_not_found;
12225
12226                 block_end = (i + 3 +
12227                              (vpd_data[i + 1] +
12228                               (vpd_data[i + 2] << 8)));
12229                 i += 3;
12230
12231                 if (block_end > 256)
12232                         goto out_not_found;
12233
12234                 while (i < (block_end - 2)) {
12235                         if (vpd_data[i + 0] == 'P' &&
12236                             vpd_data[i + 1] == 'N') {
12237                                 int partno_len = vpd_data[i + 2];
12238
12239                                 i += 3;
12240                                 if (partno_len > 24 || (partno_len + i) > 256)
12241                                         goto out_not_found;
12242
12243                                 memcpy(tp->board_part_number,
12244                                        &vpd_data[i], partno_len);
12245
12246                                 /* Success. */
12247                                 return;
12248                         }
12249                         i += 3 + vpd_data[i + 2];
12250                 }
12251
12252                 /* Part number not found. */
12253                 goto out_not_found;
12254         }
12255
12256 out_not_found:
12257         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12258                 strcpy(tp->board_part_number, "BCM95906");
12259         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12260                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12261                 strcpy(tp->board_part_number, "BCM57780");
12262         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12263                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12264                 strcpy(tp->board_part_number, "BCM57760");
12265         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12266                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12267                 strcpy(tp->board_part_number, "BCM57790");
12268         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12269                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12270                 strcpy(tp->board_part_number, "BCM57788");
12271         else
12272                 strcpy(tp->board_part_number, "none");
12273 }
12274
12275 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12276 {
12277         u32 val;
12278
12279         if (tg3_nvram_read(tp, offset, &val) ||
12280             (val & 0xfc000000) != 0x0c000000 ||
12281             tg3_nvram_read(tp, offset + 4, &val) ||
12282             val != 0)
12283                 return 0;
12284
12285         return 1;
12286 }
12287
12288 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12289 {
12290         u32 val, offset, start, ver_offset;
12291         int i;
12292         bool newver = false;
12293
12294         if (tg3_nvram_read(tp, 0xc, &offset) ||
12295             tg3_nvram_read(tp, 0x4, &start))
12296                 return;
12297
12298         offset = tg3_nvram_logical_addr(tp, offset);
12299
12300         if (tg3_nvram_read(tp, offset, &val))
12301                 return;
12302
12303         if ((val & 0xfc000000) == 0x0c000000) {
12304                 if (tg3_nvram_read(tp, offset + 4, &val))
12305                         return;
12306
12307                 if (val == 0)
12308                         newver = true;
12309         }
12310
12311         if (newver) {
12312                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12313                         return;
12314
12315                 offset = offset + ver_offset - start;
12316                 for (i = 0; i < 16; i += 4) {
12317                         __be32 v;
12318                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12319                                 return;
12320
12321                         memcpy(tp->fw_ver + i, &v, sizeof(v));
12322                 }
12323         } else {
12324                 u32 major, minor;
12325
12326                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12327                         return;
12328
12329                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12330                         TG3_NVM_BCVER_MAJSFT;
12331                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12332                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12333         }
12334 }
12335
12336 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12337 {
12338         u32 val, major, minor;
12339
12340         /* Use native endian representation */
12341         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12342                 return;
12343
12344         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12345                 TG3_NVM_HWSB_CFG1_MAJSFT;
12346         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12347                 TG3_NVM_HWSB_CFG1_MINSFT;
12348
12349         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12350 }
12351
12352 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12353 {
12354         u32 offset, major, minor, build;
12355
12356         tp->fw_ver[0] = 's';
12357         tp->fw_ver[1] = 'b';
12358         tp->fw_ver[2] = '\0';
12359
12360         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12361                 return;
12362
12363         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12364         case TG3_EEPROM_SB_REVISION_0:
12365                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12366                 break;
12367         case TG3_EEPROM_SB_REVISION_2:
12368                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12369                 break;
12370         case TG3_EEPROM_SB_REVISION_3:
12371                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12372                 break;
12373         default:
12374                 return;
12375         }
12376
12377         if (tg3_nvram_read(tp, offset, &val))
12378                 return;
12379
12380         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12381                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12382         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12383                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12384         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12385
12386         if (minor > 99 || build > 26)
12387                 return;
12388
12389         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12390
12391         if (build > 0) {
12392                 tp->fw_ver[8] = 'a' + build - 1;
12393                 tp->fw_ver[9] = '\0';
12394         }
12395 }
12396
12397 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12398 {
12399         u32 val, offset, start;
12400         int i, vlen;
12401
12402         for (offset = TG3_NVM_DIR_START;
12403              offset < TG3_NVM_DIR_END;
12404              offset += TG3_NVM_DIRENT_SIZE) {
12405                 if (tg3_nvram_read(tp, offset, &val))
12406                         return;
12407
12408                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12409                         break;
12410         }
12411
12412         if (offset == TG3_NVM_DIR_END)
12413                 return;
12414
12415         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12416                 start = 0x08000000;
12417         else if (tg3_nvram_read(tp, offset - 4, &start))
12418                 return;
12419
12420         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12421             !tg3_fw_img_is_valid(tp, offset) ||
12422             tg3_nvram_read(tp, offset + 8, &val))
12423                 return;
12424
12425         offset += val - start;
12426
12427         vlen = strlen(tp->fw_ver);
12428
12429         tp->fw_ver[vlen++] = ',';
12430         tp->fw_ver[vlen++] = ' ';
12431
12432         for (i = 0; i < 4; i++) {
12433                 __be32 v;
12434                 if (tg3_nvram_read_be32(tp, offset, &v))
12435                         return;
12436
12437                 offset += sizeof(v);
12438
12439                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12440                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12441                         break;
12442                 }
12443
12444                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12445                 vlen += sizeof(v);
12446         }
12447 }
12448
12449 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12450 {
12451         int vlen;
12452         u32 apedata;
12453
12454         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12455             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12456                 return;
12457
12458         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12459         if (apedata != APE_SEG_SIG_MAGIC)
12460                 return;
12461
12462         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12463         if (!(apedata & APE_FW_STATUS_READY))
12464                 return;
12465
12466         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12467
12468         vlen = strlen(tp->fw_ver);
12469
12470         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12471                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12472                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12473                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12474                  (apedata & APE_FW_VERSION_BLDMSK));
12475 }
12476
12477 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12478 {
12479         u32 val;
12480
12481         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12482                 tp->fw_ver[0] = 's';
12483                 tp->fw_ver[1] = 'b';
12484                 tp->fw_ver[2] = '\0';
12485
12486                 return;
12487         }
12488
12489         if (tg3_nvram_read(tp, 0, &val))
12490                 return;
12491
12492         if (val == TG3_EEPROM_MAGIC)
12493                 tg3_read_bc_ver(tp);
12494         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12495                 tg3_read_sb_ver(tp, val);
12496         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12497                 tg3_read_hwsb_ver(tp);
12498         else
12499                 return;
12500
12501         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12502              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12503                 return;
12504
12505         tg3_read_mgmtfw_ver(tp);
12506
12507         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12508 }
12509
12510 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12511
12512 static int __devinit tg3_get_invariants(struct tg3 *tp)
12513 {
12514         static struct pci_device_id write_reorder_chipsets[] = {
12515                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12516                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12517                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12518                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12519                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12520                              PCI_DEVICE_ID_VIA_8385_0) },
12521                 { },
12522         };
12523         u32 misc_ctrl_reg;
12524         u32 pci_state_reg, grc_misc_cfg;
12525         u32 val;
12526         u16 pci_cmd;
12527         int err;
12528
12529         /* Force memory write invalidate off.  If we leave it on,
12530          * then on 5700_BX chips we have to enable a workaround.
12531          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12532          * to match the cacheline size.  The Broadcom driver have this
12533          * workaround but turns MWI off all the times so never uses
12534          * it.  This seems to suggest that the workaround is insufficient.
12535          */
12536         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12537         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12538         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12539
12540         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12541          * has the register indirect write enable bit set before
12542          * we try to access any of the MMIO registers.  It is also
12543          * critical that the PCI-X hw workaround situation is decided
12544          * before that as well.
12545          */
12546         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12547                               &misc_ctrl_reg);
12548
12549         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12550                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12552                 u32 prod_id_asic_rev;
12553
12554                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12555                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12556                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12557                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12558                         pci_read_config_dword(tp->pdev,
12559                                               TG3PCI_GEN2_PRODID_ASICREV,
12560                                               &prod_id_asic_rev);
12561                 else
12562                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12563                                               &prod_id_asic_rev);
12564
12565                 tp->pci_chip_rev_id = prod_id_asic_rev;
12566         }
12567
12568         /* Wrong chip ID in 5752 A0. This code can be removed later
12569          * as A0 is not in production.
12570          */
12571         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12572                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12573
12574         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12575          * we need to disable memory and use config. cycles
12576          * only to access all registers. The 5702/03 chips
12577          * can mistakenly decode the special cycles from the
12578          * ICH chipsets as memory write cycles, causing corruption
12579          * of register and memory space. Only certain ICH bridges
12580          * will drive special cycles with non-zero data during the
12581          * address phase which can fall within the 5703's address
12582          * range. This is not an ICH bug as the PCI spec allows
12583          * non-zero address during special cycles. However, only
12584          * these ICH bridges are known to drive non-zero addresses
12585          * during special cycles.
12586          *
12587          * Since special cycles do not cross PCI bridges, we only
12588          * enable this workaround if the 5703 is on the secondary
12589          * bus of these ICH bridges.
12590          */
12591         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12592             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12593                 static struct tg3_dev_id {
12594                         u32     vendor;
12595                         u32     device;
12596                         u32     rev;
12597                 } ich_chipsets[] = {
12598                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12599                           PCI_ANY_ID },
12600                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12601                           PCI_ANY_ID },
12602                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12603                           0xa },
12604                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12605                           PCI_ANY_ID },
12606                         { },
12607                 };
12608                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12609                 struct pci_dev *bridge = NULL;
12610
12611                 while (pci_id->vendor != 0) {
12612                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12613                                                 bridge);
12614                         if (!bridge) {
12615                                 pci_id++;
12616                                 continue;
12617                         }
12618                         if (pci_id->rev != PCI_ANY_ID) {
12619                                 if (bridge->revision > pci_id->rev)
12620                                         continue;
12621                         }
12622                         if (bridge->subordinate &&
12623                             (bridge->subordinate->number ==
12624                              tp->pdev->bus->number)) {
12625
12626                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12627                                 pci_dev_put(bridge);
12628                                 break;
12629                         }
12630                 }
12631         }
12632
12633         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12634                 static struct tg3_dev_id {
12635                         u32     vendor;
12636                         u32     device;
12637                 } bridge_chipsets[] = {
12638                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12639                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12640                         { },
12641                 };
12642                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12643                 struct pci_dev *bridge = NULL;
12644
12645                 while (pci_id->vendor != 0) {
12646                         bridge = pci_get_device(pci_id->vendor,
12647                                                 pci_id->device,
12648                                                 bridge);
12649                         if (!bridge) {
12650                                 pci_id++;
12651                                 continue;
12652                         }
12653                         if (bridge->subordinate &&
12654                             (bridge->subordinate->number <=
12655                              tp->pdev->bus->number) &&
12656                             (bridge->subordinate->subordinate >=
12657                              tp->pdev->bus->number)) {
12658                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12659                                 pci_dev_put(bridge);
12660                                 break;
12661                         }
12662                 }
12663         }
12664
12665         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12666          * DMA addresses > 40-bit. This bridge may have other additional
12667          * 57xx devices behind it in some 4-port NIC designs for example.
12668          * Any tg3 device found behind the bridge will also need the 40-bit
12669          * DMA workaround.
12670          */
12671         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12672             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12673                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12674                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12675                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12676         }
12677         else {
12678                 struct pci_dev *bridge = NULL;
12679
12680                 do {
12681                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12682                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12683                                                 bridge);
12684                         if (bridge && bridge->subordinate &&
12685                             (bridge->subordinate->number <=
12686                              tp->pdev->bus->number) &&
12687                             (bridge->subordinate->subordinate >=
12688                              tp->pdev->bus->number)) {
12689                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12690                                 pci_dev_put(bridge);
12691                                 break;
12692                         }
12693                 } while (bridge);
12694         }
12695
12696         /* Initialize misc host control in PCI block. */
12697         tp->misc_host_ctrl |= (misc_ctrl_reg &
12698                                MISC_HOST_CTRL_CHIPREV);
12699         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12700                                tp->misc_host_ctrl);
12701
12702         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12703             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12704             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12705                 tp->pdev_peer = tg3_find_peer(tp);
12706
12707         /* Intentionally exclude ASIC_REV_5906 */
12708         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12709             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12710             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12711             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12712             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12713             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12714             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12715                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12716
12717         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12718             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12719             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12720             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12721             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12722                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12723
12724         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12725             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12726                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12727
12728         /* 5700 B0 chips do not support checksumming correctly due
12729          * to hardware bugs.
12730          */
12731         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12732                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12733         else {
12734                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12735                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12736                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12737                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12738         }
12739
12740         /* Determine TSO capabilities */
12741         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12742                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12743         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12744                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12745                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12746         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12747                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12748                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12749                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12750                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12751         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12752                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12753                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12754                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12755                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12756                         tp->fw_needed = FIRMWARE_TG3TSO5;
12757                 else
12758                         tp->fw_needed = FIRMWARE_TG3TSO;
12759         }
12760
12761         tp->irq_max = 1;
12762
12763         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12764                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12765                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12766                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12767                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12768                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12769                      tp->pdev_peer == tp->pdev))
12770                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12771
12772                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12773                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12774                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12775                 }
12776
12777                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12778                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12779                         tp->irq_max = TG3_IRQ_MAX_VECS;
12780                 }
12781         }
12782
12783         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12784             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12785                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12786         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
12787                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
12788                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
12789         }
12790
12791         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12792              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12793             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12794                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12795
12796         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12797                               &pci_state_reg);
12798
12799         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12800         if (tp->pcie_cap != 0) {
12801                 u16 lnkctl;
12802
12803                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12804
12805                 pcie_set_readrq(tp->pdev, 4096);
12806
12807                 pci_read_config_word(tp->pdev,
12808                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12809                                      &lnkctl);
12810                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12811                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12812                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12813                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12814                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12815                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12816                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12817                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12818                 }
12819         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12820                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12821         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12822                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12823                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12824                 if (!tp->pcix_cap) {
12825                         printk(KERN_ERR PFX "Cannot find PCI-X "
12826                                             "capability, aborting.\n");
12827                         return -EIO;
12828                 }
12829
12830                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12831                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12832         }
12833
12834         /* If we have an AMD 762 or VIA K8T800 chipset, write
12835          * reordering to the mailbox registers done by the host
12836          * controller can cause major troubles.  We read back from
12837          * every mailbox register write to force the writes to be
12838          * posted to the chip in order.
12839          */
12840         if (pci_dev_present(write_reorder_chipsets) &&
12841             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12842                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12843
12844         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12845                              &tp->pci_cacheline_sz);
12846         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12847                              &tp->pci_lat_timer);
12848         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12849             tp->pci_lat_timer < 64) {
12850                 tp->pci_lat_timer = 64;
12851                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12852                                       tp->pci_lat_timer);
12853         }
12854
12855         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12856                 /* 5700 BX chips need to have their TX producer index
12857                  * mailboxes written twice to workaround a bug.
12858                  */
12859                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12860
12861                 /* If we are in PCI-X mode, enable register write workaround.
12862                  *
12863                  * The workaround is to use indirect register accesses
12864                  * for all chip writes not to mailbox registers.
12865                  */
12866                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12867                         u32 pm_reg;
12868
12869                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12870
12871                         /* The chip can have it's power management PCI config
12872                          * space registers clobbered due to this bug.
12873                          * So explicitly force the chip into D0 here.
12874                          */
12875                         pci_read_config_dword(tp->pdev,
12876                                               tp->pm_cap + PCI_PM_CTRL,
12877                                               &pm_reg);
12878                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12879                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12880                         pci_write_config_dword(tp->pdev,
12881                                                tp->pm_cap + PCI_PM_CTRL,
12882                                                pm_reg);
12883
12884                         /* Also, force SERR#/PERR# in PCI command. */
12885                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12886                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12887                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12888                 }
12889         }
12890
12891         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12892                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12893         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12894                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12895
12896         /* Chip-specific fixup from Broadcom driver */
12897         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12898             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12899                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12900                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12901         }
12902
12903         /* Default fast path register access methods */
12904         tp->read32 = tg3_read32;
12905         tp->write32 = tg3_write32;
12906         tp->read32_mbox = tg3_read32;
12907         tp->write32_mbox = tg3_write32;
12908         tp->write32_tx_mbox = tg3_write32;
12909         tp->write32_rx_mbox = tg3_write32;
12910
12911         /* Various workaround register access methods */
12912         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12913                 tp->write32 = tg3_write_indirect_reg32;
12914         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12915                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12916                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12917                 /*
12918                  * Back to back register writes can cause problems on these
12919                  * chips, the workaround is to read back all reg writes
12920                  * except those to mailbox regs.
12921                  *
12922                  * See tg3_write_indirect_reg32().
12923                  */
12924                 tp->write32 = tg3_write_flush_reg32;
12925         }
12926
12927         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12928             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12929                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12930                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12931                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12932         }
12933
12934         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12935                 tp->read32 = tg3_read_indirect_reg32;
12936                 tp->write32 = tg3_write_indirect_reg32;
12937                 tp->read32_mbox = tg3_read_indirect_mbox;
12938                 tp->write32_mbox = tg3_write_indirect_mbox;
12939                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12940                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12941
12942                 iounmap(tp->regs);
12943                 tp->regs = NULL;
12944
12945                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12946                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12947                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12948         }
12949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12950                 tp->read32_mbox = tg3_read32_mbox_5906;
12951                 tp->write32_mbox = tg3_write32_mbox_5906;
12952                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12953                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12954         }
12955
12956         if (tp->write32 == tg3_write_indirect_reg32 ||
12957             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12958              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12959               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12960                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12961
12962         /* Get eeprom hw config before calling tg3_set_power_state().
12963          * In particular, the TG3_FLG2_IS_NIC flag must be
12964          * determined before calling tg3_set_power_state() so that
12965          * we know whether or not to switch out of Vaux power.
12966          * When the flag is set, it means that GPIO1 is used for eeprom
12967          * write protect and also implies that it is a LOM where GPIOs
12968          * are not used to switch power.
12969          */
12970         tg3_get_eeprom_hw_cfg(tp);
12971
12972         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12973                 /* Allow reads and writes to the
12974                  * APE register and memory space.
12975                  */
12976                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12977                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12978                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12979                                        pci_state_reg);
12980         }
12981
12982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12983             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12987                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12988
12989         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12990          * GPIO1 driven high will bring 5700's external PHY out of reset.
12991          * It is also used as eeprom write protect on LOMs.
12992          */
12993         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12994         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12995             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12996                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12997                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12998         /* Unused GPIO3 must be driven as output on 5752 because there
12999          * are no pull-up resistors on unused GPIO pins.
13000          */
13001         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13002                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13003
13004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13006                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13007
13008         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13009             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13010                 /* Turn off the debug UART. */
13011                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13012                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13013                         /* Keep VMain power. */
13014                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13015                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13016         }
13017
13018         /* Force the chip into D0. */
13019         err = tg3_set_power_state(tp, PCI_D0);
13020         if (err) {
13021                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13022                        pci_name(tp->pdev));
13023                 return err;
13024         }
13025
13026         /* Derive initial jumbo mode from MTU assigned in
13027          * ether_setup() via the alloc_etherdev() call
13028          */
13029         if (tp->dev->mtu > ETH_DATA_LEN &&
13030             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13031                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13032
13033         /* Determine WakeOnLan speed to use. */
13034         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13035             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13036             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13037             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13038                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13039         } else {
13040                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13041         }
13042
13043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13044                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13045
13046         /* A few boards don't want Ethernet@WireSpeed phy feature */
13047         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13048             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13049              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13050              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13051             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13052             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13053                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13054
13055         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13056             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13057                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13058         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13059                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13060
13061         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13062             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13063             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13064             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13065             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13066                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13067                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13068                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13069                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13070                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13071                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13072                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13073                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13074                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13075                 } else
13076                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13077         }
13078
13079         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13080             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13081                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13082                 if (tp->phy_otp == 0)
13083                         tp->phy_otp = TG3_OTP_DEFAULT;
13084         }
13085
13086         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13087                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13088         else
13089                 tp->mi_mode = MAC_MI_MODE_BASE;
13090
13091         tp->coalesce_mode = 0;
13092         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13093             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13094                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13095
13096         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13097             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13098                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13099
13100         err = tg3_mdio_init(tp);
13101         if (err)
13102                 return err;
13103
13104         /* Initialize data/descriptor byte/word swapping. */
13105         val = tr32(GRC_MODE);
13106         val &= GRC_MODE_HOST_STACKUP;
13107         tw32(GRC_MODE, val | tp->grc_mode);
13108
13109         tg3_switch_clocks(tp);
13110
13111         /* Clear this out for sanity. */
13112         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13113
13114         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13115                               &pci_state_reg);
13116         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13117             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13118                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13119
13120                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13121                     chiprevid == CHIPREV_ID_5701_B0 ||
13122                     chiprevid == CHIPREV_ID_5701_B2 ||
13123                     chiprevid == CHIPREV_ID_5701_B5) {
13124                         void __iomem *sram_base;
13125
13126                         /* Write some dummy words into the SRAM status block
13127                          * area, see if it reads back correctly.  If the return
13128                          * value is bad, force enable the PCIX workaround.
13129                          */
13130                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13131
13132                         writel(0x00000000, sram_base);
13133                         writel(0x00000000, sram_base + 4);
13134                         writel(0xffffffff, sram_base + 4);
13135                         if (readl(sram_base) != 0x00000000)
13136                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13137                 }
13138         }
13139
13140         udelay(50);
13141         tg3_nvram_init(tp);
13142
13143         grc_misc_cfg = tr32(GRC_MISC_CFG);
13144         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13145
13146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13147             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13148              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13149                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13150
13151         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13152             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13153                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13154         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13155                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13156                                       HOSTCC_MODE_CLRTICK_TXBD);
13157
13158                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13159                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13160                                        tp->misc_host_ctrl);
13161         }
13162
13163         /* Preserve the APE MAC_MODE bits */
13164         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13165                 tp->mac_mode = tr32(MAC_MODE) |
13166                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13167         else
13168                 tp->mac_mode = TG3_DEF_MAC_MODE;
13169
13170         /* these are limited to 10/100 only */
13171         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13172              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13173             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13174              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13175              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13176               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13177               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13178             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13179              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13180               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13181               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13182             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13183             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13184                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13185
13186         err = tg3_phy_probe(tp);
13187         if (err) {
13188                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13189                        pci_name(tp->pdev), err);
13190                 /* ... but do not return immediately ... */
13191                 tg3_mdio_fini(tp);
13192         }
13193
13194         tg3_read_partno(tp);
13195         tg3_read_fw_ver(tp);
13196
13197         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13198                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13199         } else {
13200                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13201                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13202                 else
13203                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13204         }
13205
13206         /* 5700 {AX,BX} chips have a broken status block link
13207          * change bit implementation, so we must use the
13208          * status register in those cases.
13209          */
13210         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13211                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13212         else
13213                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13214
13215         /* The led_ctrl is set during tg3_phy_probe, here we might
13216          * have to force the link status polling mechanism based
13217          * upon subsystem IDs.
13218          */
13219         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13220             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13221             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13222                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13223                                   TG3_FLAG_USE_LINKCHG_REG);
13224         }
13225
13226         /* For all SERDES we poll the MAC status register. */
13227         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13228                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13229         else
13230                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13231
13232         tp->rx_offset = NET_IP_ALIGN;
13233         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13234             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13235                 tp->rx_offset = 0;
13236
13237         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13238
13239         /* Increment the rx prod index on the rx std ring by at most
13240          * 8 for these chips to workaround hw errata.
13241          */
13242         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13243             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13244             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13245                 tp->rx_std_max_post = 8;
13246
13247         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13248                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13249                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13250
13251         return err;
13252 }
13253
13254 #ifdef CONFIG_SPARC
13255 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13256 {
13257         struct net_device *dev = tp->dev;
13258         struct pci_dev *pdev = tp->pdev;
13259         struct device_node *dp = pci_device_to_OF_node(pdev);
13260         const unsigned char *addr;
13261         int len;
13262
13263         addr = of_get_property(dp, "local-mac-address", &len);
13264         if (addr && len == 6) {
13265                 memcpy(dev->dev_addr, addr, 6);
13266                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13267                 return 0;
13268         }
13269         return -ENODEV;
13270 }
13271
13272 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13273 {
13274         struct net_device *dev = tp->dev;
13275
13276         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13277         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13278         return 0;
13279 }
13280 #endif
13281
13282 static int __devinit tg3_get_device_address(struct tg3 *tp)
13283 {
13284         struct net_device *dev = tp->dev;
13285         u32 hi, lo, mac_offset;
13286         int addr_ok = 0;
13287
13288 #ifdef CONFIG_SPARC
13289         if (!tg3_get_macaddr_sparc(tp))
13290                 return 0;
13291 #endif
13292
13293         mac_offset = 0x7c;
13294         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13295             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13296                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13297                         mac_offset = 0xcc;
13298                 if (tg3_nvram_lock(tp))
13299                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13300                 else
13301                         tg3_nvram_unlock(tp);
13302         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13303                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13304                         mac_offset = 0xcc;
13305         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13306                 mac_offset = 0x10;
13307
13308         /* First try to get it from MAC address mailbox. */
13309         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13310         if ((hi >> 16) == 0x484b) {
13311                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13312                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13313
13314                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13315                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13316                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13317                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13318                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13319
13320                 /* Some old bootcode may report a 0 MAC address in SRAM */
13321                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13322         }
13323         if (!addr_ok) {
13324                 /* Next, try NVRAM. */
13325                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13326                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13327                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13328                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13329                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13330                 }
13331                 /* Finally just fetch it out of the MAC control regs. */
13332                 else {
13333                         hi = tr32(MAC_ADDR_0_HIGH);
13334                         lo = tr32(MAC_ADDR_0_LOW);
13335
13336                         dev->dev_addr[5] = lo & 0xff;
13337                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13338                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13339                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13340                         dev->dev_addr[1] = hi & 0xff;
13341                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13342                 }
13343         }
13344
13345         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13346 #ifdef CONFIG_SPARC
13347                 if (!tg3_get_default_macaddr_sparc(tp))
13348                         return 0;
13349 #endif
13350                 return -EINVAL;
13351         }
13352         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13353         return 0;
13354 }
13355
13356 #define BOUNDARY_SINGLE_CACHELINE       1
13357 #define BOUNDARY_MULTI_CACHELINE        2
13358
13359 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13360 {
13361         int cacheline_size;
13362         u8 byte;
13363         int goal;
13364
13365         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13366         if (byte == 0)
13367                 cacheline_size = 1024;
13368         else
13369                 cacheline_size = (int) byte * 4;
13370
13371         /* On 5703 and later chips, the boundary bits have no
13372          * effect.
13373          */
13374         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13375             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13376             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13377                 goto out;
13378
13379 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13380         goal = BOUNDARY_MULTI_CACHELINE;
13381 #else
13382 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13383         goal = BOUNDARY_SINGLE_CACHELINE;
13384 #else
13385         goal = 0;
13386 #endif
13387 #endif
13388
13389         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13390                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13391                 goto out;
13392         }
13393
13394         if (!goal)
13395                 goto out;
13396
13397         /* PCI controllers on most RISC systems tend to disconnect
13398          * when a device tries to burst across a cache-line boundary.
13399          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13400          *
13401          * Unfortunately, for PCI-E there are only limited
13402          * write-side controls for this, and thus for reads
13403          * we will still get the disconnects.  We'll also waste
13404          * these PCI cycles for both read and write for chips
13405          * other than 5700 and 5701 which do not implement the
13406          * boundary bits.
13407          */
13408         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13409             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13410                 switch (cacheline_size) {
13411                 case 16:
13412                 case 32:
13413                 case 64:
13414                 case 128:
13415                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13416                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13417                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13418                         } else {
13419                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13420                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13421                         }
13422                         break;
13423
13424                 case 256:
13425                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13426                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13427                         break;
13428
13429                 default:
13430                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13431                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13432                         break;
13433                 }
13434         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13435                 switch (cacheline_size) {
13436                 case 16:
13437                 case 32:
13438                 case 64:
13439                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13440                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13441                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13442                                 break;
13443                         }
13444                         /* fallthrough */
13445                 case 128:
13446                 default:
13447                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13448                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13449                         break;
13450                 }
13451         } else {
13452                 switch (cacheline_size) {
13453                 case 16:
13454                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13455                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13456                                         DMA_RWCTRL_WRITE_BNDRY_16);
13457                                 break;
13458                         }
13459                         /* fallthrough */
13460                 case 32:
13461                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13462                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13463                                         DMA_RWCTRL_WRITE_BNDRY_32);
13464                                 break;
13465                         }
13466                         /* fallthrough */
13467                 case 64:
13468                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13469                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13470                                         DMA_RWCTRL_WRITE_BNDRY_64);
13471                                 break;
13472                         }
13473                         /* fallthrough */
13474                 case 128:
13475                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13476                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13477                                         DMA_RWCTRL_WRITE_BNDRY_128);
13478                                 break;
13479                         }
13480                         /* fallthrough */
13481                 case 256:
13482                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13483                                 DMA_RWCTRL_WRITE_BNDRY_256);
13484                         break;
13485                 case 512:
13486                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13487                                 DMA_RWCTRL_WRITE_BNDRY_512);
13488                         break;
13489                 case 1024:
13490                 default:
13491                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13492                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13493                         break;
13494                 }
13495         }
13496
13497 out:
13498         return val;
13499 }
13500
13501 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13502 {
13503         struct tg3_internal_buffer_desc test_desc;
13504         u32 sram_dma_descs;
13505         int i, ret;
13506
13507         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13508
13509         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13510         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13511         tw32(RDMAC_STATUS, 0);
13512         tw32(WDMAC_STATUS, 0);
13513
13514         tw32(BUFMGR_MODE, 0);
13515         tw32(FTQ_RESET, 0);
13516
13517         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13518         test_desc.addr_lo = buf_dma & 0xffffffff;
13519         test_desc.nic_mbuf = 0x00002100;
13520         test_desc.len = size;
13521
13522         /*
13523          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13524          * the *second* time the tg3 driver was getting loaded after an
13525          * initial scan.
13526          *
13527          * Broadcom tells me:
13528          *   ...the DMA engine is connected to the GRC block and a DMA
13529          *   reset may affect the GRC block in some unpredictable way...
13530          *   The behavior of resets to individual blocks has not been tested.
13531          *
13532          * Broadcom noted the GRC reset will also reset all sub-components.
13533          */
13534         if (to_device) {
13535                 test_desc.cqid_sqid = (13 << 8) | 2;
13536
13537                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13538                 udelay(40);
13539         } else {
13540                 test_desc.cqid_sqid = (16 << 8) | 7;
13541
13542                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13543                 udelay(40);
13544         }
13545         test_desc.flags = 0x00000005;
13546
13547         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13548                 u32 val;
13549
13550                 val = *(((u32 *)&test_desc) + i);
13551                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13552                                        sram_dma_descs + (i * sizeof(u32)));
13553                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13554         }
13555         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13556
13557         if (to_device) {
13558                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13559         } else {
13560                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13561         }
13562
13563         ret = -ENODEV;
13564         for (i = 0; i < 40; i++) {
13565                 u32 val;
13566
13567                 if (to_device)
13568                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13569                 else
13570                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13571                 if ((val & 0xffff) == sram_dma_descs) {
13572                         ret = 0;
13573                         break;
13574                 }
13575
13576                 udelay(100);
13577         }
13578
13579         return ret;
13580 }
13581
13582 #define TEST_BUFFER_SIZE        0x2000
13583
13584 static int __devinit tg3_test_dma(struct tg3 *tp)
13585 {
13586         dma_addr_t buf_dma;
13587         u32 *buf, saved_dma_rwctrl;
13588         int ret = 0;
13589
13590         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13591         if (!buf) {
13592                 ret = -ENOMEM;
13593                 goto out_nofree;
13594         }
13595
13596         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13597                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13598
13599         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13600
13601         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13602                 goto out;
13603
13604         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13605                 /* DMA read watermark not used on PCIE */
13606                 tp->dma_rwctrl |= 0x00180000;
13607         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13608                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13609                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13610                         tp->dma_rwctrl |= 0x003f0000;
13611                 else
13612                         tp->dma_rwctrl |= 0x003f000f;
13613         } else {
13614                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13615                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13616                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13617                         u32 read_water = 0x7;
13618
13619                         /* If the 5704 is behind the EPB bridge, we can
13620                          * do the less restrictive ONE_DMA workaround for
13621                          * better performance.
13622                          */
13623                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13624                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13625                                 tp->dma_rwctrl |= 0x8000;
13626                         else if (ccval == 0x6 || ccval == 0x7)
13627                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13628
13629                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13630                                 read_water = 4;
13631                         /* Set bit 23 to enable PCIX hw bug fix */
13632                         tp->dma_rwctrl |=
13633                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13634                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13635                                 (1 << 23);
13636                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13637                         /* 5780 always in PCIX mode */
13638                         tp->dma_rwctrl |= 0x00144000;
13639                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13640                         /* 5714 always in PCIX mode */
13641                         tp->dma_rwctrl |= 0x00148000;
13642                 } else {
13643                         tp->dma_rwctrl |= 0x001b000f;
13644                 }
13645         }
13646
13647         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13648             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13649                 tp->dma_rwctrl &= 0xfffffff0;
13650
13651         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13652             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13653                 /* Remove this if it causes problems for some boards. */
13654                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13655
13656                 /* On 5700/5701 chips, we need to set this bit.
13657                  * Otherwise the chip will issue cacheline transactions
13658                  * to streamable DMA memory with not all the byte
13659                  * enables turned on.  This is an error on several
13660                  * RISC PCI controllers, in particular sparc64.
13661                  *
13662                  * On 5703/5704 chips, this bit has been reassigned
13663                  * a different meaning.  In particular, it is used
13664                  * on those chips to enable a PCI-X workaround.
13665                  */
13666                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13667         }
13668
13669         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13670
13671 #if 0
13672         /* Unneeded, already done by tg3_get_invariants.  */
13673         tg3_switch_clocks(tp);
13674 #endif
13675
13676         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13677             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13678                 goto out;
13679
13680         /* It is best to perform DMA test with maximum write burst size
13681          * to expose the 5700/5701 write DMA bug.
13682          */
13683         saved_dma_rwctrl = tp->dma_rwctrl;
13684         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13685         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13686
13687         while (1) {
13688                 u32 *p = buf, i;
13689
13690                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13691                         p[i] = i;
13692
13693                 /* Send the buffer to the chip. */
13694                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13695                 if (ret) {
13696                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13697                         break;
13698                 }
13699
13700 #if 0
13701                 /* validate data reached card RAM correctly. */
13702                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13703                         u32 val;
13704                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13705                         if (le32_to_cpu(val) != p[i]) {
13706                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13707                                 /* ret = -ENODEV here? */
13708                         }
13709                         p[i] = 0;
13710                 }
13711 #endif
13712                 /* Now read it back. */
13713                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13714                 if (ret) {
13715                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13716
13717                         break;
13718                 }
13719
13720                 /* Verify it. */
13721                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13722                         if (p[i] == i)
13723                                 continue;
13724
13725                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13726                             DMA_RWCTRL_WRITE_BNDRY_16) {
13727                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13728                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13729                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13730                                 break;
13731                         } else {
13732                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13733                                 ret = -ENODEV;
13734                                 goto out;
13735                         }
13736                 }
13737
13738                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13739                         /* Success. */
13740                         ret = 0;
13741                         break;
13742                 }
13743         }
13744         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13745             DMA_RWCTRL_WRITE_BNDRY_16) {
13746                 static struct pci_device_id dma_wait_state_chipsets[] = {
13747                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13748                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13749                         { },
13750                 };
13751
13752                 /* DMA test passed without adjusting DMA boundary,
13753                  * now look for chipsets that are known to expose the
13754                  * DMA bug without failing the test.
13755                  */
13756                 if (pci_dev_present(dma_wait_state_chipsets)) {
13757                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13758                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13759                 }
13760                 else
13761                         /* Safe to use the calculated DMA boundary. */
13762                         tp->dma_rwctrl = saved_dma_rwctrl;
13763
13764                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13765         }
13766
13767 out:
13768         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13769 out_nofree:
13770         return ret;
13771 }
13772
13773 static void __devinit tg3_init_link_config(struct tg3 *tp)
13774 {
13775         tp->link_config.advertising =
13776                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13777                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13778                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13779                  ADVERTISED_Autoneg | ADVERTISED_MII);
13780         tp->link_config.speed = SPEED_INVALID;
13781         tp->link_config.duplex = DUPLEX_INVALID;
13782         tp->link_config.autoneg = AUTONEG_ENABLE;
13783         tp->link_config.active_speed = SPEED_INVALID;
13784         tp->link_config.active_duplex = DUPLEX_INVALID;
13785         tp->link_config.phy_is_low_power = 0;
13786         tp->link_config.orig_speed = SPEED_INVALID;
13787         tp->link_config.orig_duplex = DUPLEX_INVALID;
13788         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13789 }
13790
13791 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13792 {
13793         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13794             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13795                 tp->bufmgr_config.mbuf_read_dma_low_water =
13796                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13797                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13798                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13799                 tp->bufmgr_config.mbuf_high_water =
13800                         DEFAULT_MB_HIGH_WATER_5705;
13801                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13802                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13803                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13804                         tp->bufmgr_config.mbuf_high_water =
13805                                 DEFAULT_MB_HIGH_WATER_5906;
13806                 }
13807
13808                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13809                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13810                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13811                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13812                 tp->bufmgr_config.mbuf_high_water_jumbo =
13813                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13814         } else {
13815                 tp->bufmgr_config.mbuf_read_dma_low_water =
13816                         DEFAULT_MB_RDMA_LOW_WATER;
13817                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13818                         DEFAULT_MB_MACRX_LOW_WATER;
13819                 tp->bufmgr_config.mbuf_high_water =
13820                         DEFAULT_MB_HIGH_WATER;
13821
13822                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13823                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13824                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13825                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13826                 tp->bufmgr_config.mbuf_high_water_jumbo =
13827                         DEFAULT_MB_HIGH_WATER_JUMBO;
13828         }
13829
13830         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13831         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13832 }
13833
13834 static char * __devinit tg3_phy_string(struct tg3 *tp)
13835 {
13836         switch (tp->phy_id & PHY_ID_MASK) {
13837         case PHY_ID_BCM5400:    return "5400";
13838         case PHY_ID_BCM5401:    return "5401";
13839         case PHY_ID_BCM5411:    return "5411";
13840         case PHY_ID_BCM5701:    return "5701";
13841         case PHY_ID_BCM5703:    return "5703";
13842         case PHY_ID_BCM5704:    return "5704";
13843         case PHY_ID_BCM5705:    return "5705";
13844         case PHY_ID_BCM5750:    return "5750";
13845         case PHY_ID_BCM5752:    return "5752";
13846         case PHY_ID_BCM5714:    return "5714";
13847         case PHY_ID_BCM5780:    return "5780";
13848         case PHY_ID_BCM5755:    return "5755";
13849         case PHY_ID_BCM5787:    return "5787";
13850         case PHY_ID_BCM5784:    return "5784";
13851         case PHY_ID_BCM5756:    return "5722/5756";
13852         case PHY_ID_BCM5906:    return "5906";
13853         case PHY_ID_BCM5761:    return "5761";
13854         case PHY_ID_BCM5717:    return "5717";
13855         case PHY_ID_BCM8002:    return "8002/serdes";
13856         case 0:                 return "serdes";
13857         default:                return "unknown";
13858         }
13859 }
13860
13861 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13862 {
13863         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13864                 strcpy(str, "PCI Express");
13865                 return str;
13866         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13867                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13868
13869                 strcpy(str, "PCIX:");
13870
13871                 if ((clock_ctrl == 7) ||
13872                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13873                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13874                         strcat(str, "133MHz");
13875                 else if (clock_ctrl == 0)
13876                         strcat(str, "33MHz");
13877                 else if (clock_ctrl == 2)
13878                         strcat(str, "50MHz");
13879                 else if (clock_ctrl == 4)
13880                         strcat(str, "66MHz");
13881                 else if (clock_ctrl == 6)
13882                         strcat(str, "100MHz");
13883         } else {
13884                 strcpy(str, "PCI:");
13885                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13886                         strcat(str, "66MHz");
13887                 else
13888                         strcat(str, "33MHz");
13889         }
13890         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13891                 strcat(str, ":32-bit");
13892         else
13893                 strcat(str, ":64-bit");
13894         return str;
13895 }
13896
13897 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13898 {
13899         struct pci_dev *peer;
13900         unsigned int func, devnr = tp->pdev->devfn & ~7;
13901
13902         for (func = 0; func < 8; func++) {
13903                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13904                 if (peer && peer != tp->pdev)
13905                         break;
13906                 pci_dev_put(peer);
13907         }
13908         /* 5704 can be configured in single-port mode, set peer to
13909          * tp->pdev in that case.
13910          */
13911         if (!peer) {
13912                 peer = tp->pdev;
13913                 return peer;
13914         }
13915
13916         /*
13917          * We don't need to keep the refcount elevated; there's no way
13918          * to remove one half of this device without removing the other
13919          */
13920         pci_dev_put(peer);
13921
13922         return peer;
13923 }
13924
13925 static void __devinit tg3_init_coal(struct tg3 *tp)
13926 {
13927         struct ethtool_coalesce *ec = &tp->coal;
13928
13929         memset(ec, 0, sizeof(*ec));
13930         ec->cmd = ETHTOOL_GCOALESCE;
13931         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13932         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13933         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13934         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13935         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13936         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13937         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13938         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13939         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13940
13941         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13942                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13943                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13944                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13945                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13946                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13947         }
13948
13949         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13950                 ec->rx_coalesce_usecs_irq = 0;
13951                 ec->tx_coalesce_usecs_irq = 0;
13952                 ec->stats_block_coalesce_usecs = 0;
13953         }
13954 }
13955
13956 static const struct net_device_ops tg3_netdev_ops = {
13957         .ndo_open               = tg3_open,
13958         .ndo_stop               = tg3_close,
13959         .ndo_start_xmit         = tg3_start_xmit,
13960         .ndo_get_stats          = tg3_get_stats,
13961         .ndo_validate_addr      = eth_validate_addr,
13962         .ndo_set_multicast_list = tg3_set_rx_mode,
13963         .ndo_set_mac_address    = tg3_set_mac_addr,
13964         .ndo_do_ioctl           = tg3_ioctl,
13965         .ndo_tx_timeout         = tg3_tx_timeout,
13966         .ndo_change_mtu         = tg3_change_mtu,
13967 #if TG3_VLAN_TAG_USED
13968         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13969 #endif
13970 #ifdef CONFIG_NET_POLL_CONTROLLER
13971         .ndo_poll_controller    = tg3_poll_controller,
13972 #endif
13973 };
13974
13975 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13976         .ndo_open               = tg3_open,
13977         .ndo_stop               = tg3_close,
13978         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13979         .ndo_get_stats          = tg3_get_stats,
13980         .ndo_validate_addr      = eth_validate_addr,
13981         .ndo_set_multicast_list = tg3_set_rx_mode,
13982         .ndo_set_mac_address    = tg3_set_mac_addr,
13983         .ndo_do_ioctl           = tg3_ioctl,
13984         .ndo_tx_timeout         = tg3_tx_timeout,
13985         .ndo_change_mtu         = tg3_change_mtu,
13986 #if TG3_VLAN_TAG_USED
13987         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13988 #endif
13989 #ifdef CONFIG_NET_POLL_CONTROLLER
13990         .ndo_poll_controller    = tg3_poll_controller,
13991 #endif
13992 };
13993
13994 static int __devinit tg3_init_one(struct pci_dev *pdev,
13995                                   const struct pci_device_id *ent)
13996 {
13997         static int tg3_version_printed = 0;
13998         struct net_device *dev;
13999         struct tg3 *tp;
14000         int i, err, pm_cap;
14001         u32 sndmbx, rcvmbx, intmbx;
14002         char str[40];
14003         u64 dma_mask, persist_dma_mask;
14004
14005         if (tg3_version_printed++ == 0)
14006                 printk(KERN_INFO "%s", version);
14007
14008         err = pci_enable_device(pdev);
14009         if (err) {
14010                 printk(KERN_ERR PFX "Cannot enable PCI device, "
14011                        "aborting.\n");
14012                 return err;
14013         }
14014
14015         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14016         if (err) {
14017                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14018                        "aborting.\n");
14019                 goto err_out_disable_pdev;
14020         }
14021
14022         pci_set_master(pdev);
14023
14024         /* Find power-management capability. */
14025         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14026         if (pm_cap == 0) {
14027                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14028                        "aborting.\n");
14029                 err = -EIO;
14030                 goto err_out_free_res;
14031         }
14032
14033         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14034         if (!dev) {
14035                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14036                 err = -ENOMEM;
14037                 goto err_out_free_res;
14038         }
14039
14040         SET_NETDEV_DEV(dev, &pdev->dev);
14041
14042 #if TG3_VLAN_TAG_USED
14043         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14044 #endif
14045
14046         tp = netdev_priv(dev);
14047         tp->pdev = pdev;
14048         tp->dev = dev;
14049         tp->pm_cap = pm_cap;
14050         tp->rx_mode = TG3_DEF_RX_MODE;
14051         tp->tx_mode = TG3_DEF_TX_MODE;
14052
14053         if (tg3_debug > 0)
14054                 tp->msg_enable = tg3_debug;
14055         else
14056                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14057
14058         /* The word/byte swap controls here control register access byte
14059          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14060          * setting below.
14061          */
14062         tp->misc_host_ctrl =
14063                 MISC_HOST_CTRL_MASK_PCI_INT |
14064                 MISC_HOST_CTRL_WORD_SWAP |
14065                 MISC_HOST_CTRL_INDIR_ACCESS |
14066                 MISC_HOST_CTRL_PCISTATE_RW;
14067
14068         /* The NONFRM (non-frame) byte/word swap controls take effect
14069          * on descriptor entries, anything which isn't packet data.
14070          *
14071          * The StrongARM chips on the board (one for tx, one for rx)
14072          * are running in big-endian mode.
14073          */
14074         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14075                         GRC_MODE_WSWAP_NONFRM_DATA);
14076 #ifdef __BIG_ENDIAN
14077         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14078 #endif
14079         spin_lock_init(&tp->lock);
14080         spin_lock_init(&tp->indirect_lock);
14081         INIT_WORK(&tp->reset_task, tg3_reset_task);
14082
14083         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14084         if (!tp->regs) {
14085                 printk(KERN_ERR PFX "Cannot map device registers, "
14086                        "aborting.\n");
14087                 err = -ENOMEM;
14088                 goto err_out_free_dev;
14089         }
14090
14091         tg3_init_link_config(tp);
14092
14093         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14094         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14095
14096         dev->ethtool_ops = &tg3_ethtool_ops;
14097         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14098         dev->irq = pdev->irq;
14099
14100         err = tg3_get_invariants(tp);
14101         if (err) {
14102                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14103                        "aborting.\n");
14104                 goto err_out_iounmap;
14105         }
14106
14107         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14108             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14109                 dev->netdev_ops = &tg3_netdev_ops;
14110         else
14111                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14112
14113
14114         /* The EPB bridge inside 5714, 5715, and 5780 and any
14115          * device behind the EPB cannot support DMA addresses > 40-bit.
14116          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14117          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14118          * do DMA address check in tg3_start_xmit().
14119          */
14120         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14121                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14122         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14123                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14124 #ifdef CONFIG_HIGHMEM
14125                 dma_mask = DMA_BIT_MASK(64);
14126 #endif
14127         } else
14128                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14129
14130         /* Configure DMA attributes. */
14131         if (dma_mask > DMA_BIT_MASK(32)) {
14132                 err = pci_set_dma_mask(pdev, dma_mask);
14133                 if (!err) {
14134                         dev->features |= NETIF_F_HIGHDMA;
14135                         err = pci_set_consistent_dma_mask(pdev,
14136                                                           persist_dma_mask);
14137                         if (err < 0) {
14138                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14139                                        "DMA for consistent allocations\n");
14140                                 goto err_out_iounmap;
14141                         }
14142                 }
14143         }
14144         if (err || dma_mask == DMA_BIT_MASK(32)) {
14145                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14146                 if (err) {
14147                         printk(KERN_ERR PFX "No usable DMA configuration, "
14148                                "aborting.\n");
14149                         goto err_out_iounmap;
14150                 }
14151         }
14152
14153         tg3_init_bufmgr_config(tp);
14154
14155         /* Selectively allow TSO based on operating conditions */
14156         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14157             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14158                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14159         else {
14160                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14161                 tp->fw_needed = NULL;
14162         }
14163
14164         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14165                 tp->fw_needed = FIRMWARE_TG3;
14166
14167         /* TSO is on by default on chips that support hardware TSO.
14168          * Firmware TSO on older chips gives lower performance, so it
14169          * is off by default, but can be enabled using ethtool.
14170          */
14171         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14172             (dev->features & NETIF_F_IP_CSUM))
14173                 dev->features |= NETIF_F_TSO;
14174
14175         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14176             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14177                 if (dev->features & NETIF_F_IPV6_CSUM)
14178                         dev->features |= NETIF_F_TSO6;
14179                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14180                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14181                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14182                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14183                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14184                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14185                         dev->features |= NETIF_F_TSO_ECN;
14186         }
14187
14188         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14189             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14190             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14191                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14192                 tp->rx_pending = 63;
14193         }
14194
14195         err = tg3_get_device_address(tp);
14196         if (err) {
14197                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14198                        "aborting.\n");
14199                 goto err_out_fw;
14200         }
14201
14202         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14203                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14204                 if (!tp->aperegs) {
14205                         printk(KERN_ERR PFX "Cannot map APE registers, "
14206                                "aborting.\n");
14207                         err = -ENOMEM;
14208                         goto err_out_fw;
14209                 }
14210
14211                 tg3_ape_lock_init(tp);
14212
14213                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14214                         tg3_read_dash_ver(tp);
14215         }
14216
14217         /*
14218          * Reset chip in case UNDI or EFI driver did not shutdown
14219          * DMA self test will enable WDMAC and we'll see (spurious)
14220          * pending DMA on the PCI bus at that point.
14221          */
14222         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14223             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14224                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14225                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14226         }
14227
14228         err = tg3_test_dma(tp);
14229         if (err) {
14230                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14231                 goto err_out_apeunmap;
14232         }
14233
14234         /* flow control autonegotiation is default behavior */
14235         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14236         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14237
14238         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14239         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14240         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14241         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14242                 struct tg3_napi *tnapi = &tp->napi[i];
14243
14244                 tnapi->tp = tp;
14245                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14246
14247                 tnapi->int_mbox = intmbx;
14248                 if (i < 4)
14249                         intmbx += 0x8;
14250                 else
14251                         intmbx += 0x4;
14252
14253                 tnapi->consmbox = rcvmbx;
14254                 tnapi->prodmbox = sndmbx;
14255
14256                 if (i) {
14257                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14258                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14259                 } else {
14260                         tnapi->coal_now = HOSTCC_MODE_NOW;
14261                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14262                 }
14263
14264                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14265                         break;
14266
14267                 /*
14268                  * If we support MSIX, we'll be using RSS.  If we're using
14269                  * RSS, the first vector only handles link interrupts and the
14270                  * remaining vectors handle rx and tx interrupts.  Reuse the
14271                  * mailbox values for the next iteration.  The values we setup
14272                  * above are still useful for the single vectored mode.
14273                  */
14274                 if (!i)
14275                         continue;
14276
14277                 rcvmbx += 0x8;
14278
14279                 if (sndmbx & 0x4)
14280                         sndmbx -= 0x4;
14281                 else
14282                         sndmbx += 0xc;
14283         }
14284
14285         tg3_init_coal(tp);
14286
14287         pci_set_drvdata(pdev, dev);
14288
14289         err = register_netdev(dev);
14290         if (err) {
14291                 printk(KERN_ERR PFX "Cannot register net device, "
14292                        "aborting.\n");
14293                 goto err_out_apeunmap;
14294         }
14295
14296         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14297                dev->name,
14298                tp->board_part_number,
14299                tp->pci_chip_rev_id,
14300                tg3_bus_string(tp, str),
14301                dev->dev_addr);
14302
14303         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14304                 struct phy_device *phydev;
14305                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14306                 printk(KERN_INFO
14307                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14308                        tp->dev->name, phydev->drv->name,
14309                        dev_name(&phydev->dev));
14310         } else
14311                 printk(KERN_INFO
14312                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14313                        tp->dev->name, tg3_phy_string(tp),
14314                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14315                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14316                          "10/100/1000Base-T")),
14317                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14318
14319         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14320                dev->name,
14321                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14322                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14323                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14324                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14325                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14326         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14327                dev->name, tp->dma_rwctrl,
14328                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14329                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14330
14331         return 0;
14332
14333 err_out_apeunmap:
14334         if (tp->aperegs) {
14335                 iounmap(tp->aperegs);
14336                 tp->aperegs = NULL;
14337         }
14338
14339 err_out_fw:
14340         if (tp->fw)
14341                 release_firmware(tp->fw);
14342
14343 err_out_iounmap:
14344         if (tp->regs) {
14345                 iounmap(tp->regs);
14346                 tp->regs = NULL;
14347         }
14348
14349 err_out_free_dev:
14350         free_netdev(dev);
14351
14352 err_out_free_res:
14353         pci_release_regions(pdev);
14354
14355 err_out_disable_pdev:
14356         pci_disable_device(pdev);
14357         pci_set_drvdata(pdev, NULL);
14358         return err;
14359 }
14360
14361 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14362 {
14363         struct net_device *dev = pci_get_drvdata(pdev);
14364
14365         if (dev) {
14366                 struct tg3 *tp = netdev_priv(dev);
14367
14368                 if (tp->fw)
14369                         release_firmware(tp->fw);
14370
14371                 flush_scheduled_work();
14372
14373                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14374                         tg3_phy_fini(tp);
14375                         tg3_mdio_fini(tp);
14376                 }
14377
14378                 unregister_netdev(dev);
14379                 if (tp->aperegs) {
14380                         iounmap(tp->aperegs);
14381                         tp->aperegs = NULL;
14382                 }
14383                 if (tp->regs) {
14384                         iounmap(tp->regs);
14385                         tp->regs = NULL;
14386                 }
14387                 free_netdev(dev);
14388                 pci_release_regions(pdev);
14389                 pci_disable_device(pdev);
14390                 pci_set_drvdata(pdev, NULL);
14391         }
14392 }
14393
14394 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14395 {
14396         struct net_device *dev = pci_get_drvdata(pdev);
14397         struct tg3 *tp = netdev_priv(dev);
14398         pci_power_t target_state;
14399         int err;
14400
14401         /* PCI register 4 needs to be saved whether netif_running() or not.
14402          * MSI address and data need to be saved if using MSI and
14403          * netif_running().
14404          */
14405         pci_save_state(pdev);
14406
14407         if (!netif_running(dev))
14408                 return 0;
14409
14410         flush_scheduled_work();
14411         tg3_phy_stop(tp);
14412         tg3_netif_stop(tp);
14413
14414         del_timer_sync(&tp->timer);
14415
14416         tg3_full_lock(tp, 1);
14417         tg3_disable_ints(tp);
14418         tg3_full_unlock(tp);
14419
14420         netif_device_detach(dev);
14421
14422         tg3_full_lock(tp, 0);
14423         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14424         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14425         tg3_full_unlock(tp);
14426
14427         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14428
14429         err = tg3_set_power_state(tp, target_state);
14430         if (err) {
14431                 int err2;
14432
14433                 tg3_full_lock(tp, 0);
14434
14435                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14436                 err2 = tg3_restart_hw(tp, 1);
14437                 if (err2)
14438                         goto out;
14439
14440                 tp->timer.expires = jiffies + tp->timer_offset;
14441                 add_timer(&tp->timer);
14442
14443                 netif_device_attach(dev);
14444                 tg3_netif_start(tp);
14445
14446 out:
14447                 tg3_full_unlock(tp);
14448
14449                 if (!err2)
14450                         tg3_phy_start(tp);
14451         }
14452
14453         return err;
14454 }
14455
14456 static int tg3_resume(struct pci_dev *pdev)
14457 {
14458         struct net_device *dev = pci_get_drvdata(pdev);
14459         struct tg3 *tp = netdev_priv(dev);
14460         int err;
14461
14462         pci_restore_state(tp->pdev);
14463
14464         if (!netif_running(dev))
14465                 return 0;
14466
14467         err = tg3_set_power_state(tp, PCI_D0);
14468         if (err)
14469                 return err;
14470
14471         netif_device_attach(dev);
14472
14473         tg3_full_lock(tp, 0);
14474
14475         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14476         err = tg3_restart_hw(tp, 1);
14477         if (err)
14478                 goto out;
14479
14480         tp->timer.expires = jiffies + tp->timer_offset;
14481         add_timer(&tp->timer);
14482
14483         tg3_netif_start(tp);
14484
14485 out:
14486         tg3_full_unlock(tp);
14487
14488         if (!err)
14489                 tg3_phy_start(tp);
14490
14491         return err;
14492 }
14493
14494 static struct pci_driver tg3_driver = {
14495         .name           = DRV_MODULE_NAME,
14496         .id_table       = tg3_pci_tbl,
14497         .probe          = tg3_init_one,
14498         .remove         = __devexit_p(tg3_remove_one),
14499         .suspend        = tg3_suspend,
14500         .resume         = tg3_resume
14501 };
14502
14503 static int __init tg3_init(void)
14504 {
14505         return pci_register_driver(&tg3_driver);
14506 }
14507
14508 static void __exit tg3_cleanup(void)
14509 {
14510         pci_unregister_driver(&tg3_driver);
14511 }
14512
14513 module_init(tg3_init);
14514 module_exit(tg3_cleanup);