SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.99"
  72 #define DRV_MODULE_RELDATE      "April 20, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 #define TG3_RAW_IP_ALIGN 2
 135
 136 /* number of ETHTOOL_GSTATS u64's */
 137 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 138
 139 #define TG3_NUM_TEST            6
 140
 141 #define FIRMWARE_TG3            "tigon/tg3.bin"
 142 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 143 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 144
 145 static char version[] __devinitdata =
 146         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 147
 148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 150 MODULE_LICENSE("GPL");
 151 MODULE_VERSION(DRV_MODULE_VERSION);
 152 MODULE_FIRMWARE(FIRMWARE_TG3);
 153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 155
 156
 157 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 158 module_param(tg3_debug, int, 0);
 159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 160
 161 static struct pci_device_id tg3_pci_tbl[] = {
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 234         {}
 235 };
 236
 237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 238
 239 static const struct {
 240         const char string[ETH_GSTRING_LEN];
 241 } ethtool_stats_keys[TG3_NUM_STATS] = {
 242         { "rx_octets" },
 243         { "rx_fragments" },
 244         { "rx_ucast_packets" },
 245         { "rx_mcast_packets" },
 246         { "rx_bcast_packets" },
 247         { "rx_fcs_errors" },
 248         { "rx_align_errors" },
 249         { "rx_xon_pause_rcvd" },
 250         { "rx_xoff_pause_rcvd" },
 251         { "rx_mac_ctrl_rcvd" },
 252         { "rx_xoff_entered" },
 253         { "rx_frame_too_long_errors" },
 254         { "rx_jabbers" },
 255         { "rx_undersize_packets" },
 256         { "rx_in_length_errors" },
 257         { "rx_out_length_errors" },
 258         { "rx_64_or_less_octet_packets" },
 259         { "rx_65_to_127_octet_packets" },
 260         { "rx_128_to_255_octet_packets" },
 261         { "rx_256_to_511_octet_packets" },
 262         { "rx_512_to_1023_octet_packets" },
 263         { "rx_1024_to_1522_octet_packets" },
 264         { "rx_1523_to_2047_octet_packets" },
 265         { "rx_2048_to_4095_octet_packets" },
 266         { "rx_4096_to_8191_octet_packets" },
 267         { "rx_8192_to_9022_octet_packets" },
 268
 269         { "tx_octets" },
 270         { "tx_collisions" },
 271
 272         { "tx_xon_sent" },
 273         { "tx_xoff_sent" },
 274         { "tx_flow_control" },
 275         { "tx_mac_errors" },
 276         { "tx_single_collisions" },
 277         { "tx_mult_collisions" },
 278         { "tx_deferred" },
 279         { "tx_excessive_collisions" },
 280         { "tx_late_collisions" },
 281         { "tx_collide_2times" },
 282         { "tx_collide_3times" },
 283         { "tx_collide_4times" },
 284         { "tx_collide_5times" },
 285         { "tx_collide_6times" },
 286         { "tx_collide_7times" },
 287         { "tx_collide_8times" },
 288         { "tx_collide_9times" },
 289         { "tx_collide_10times" },
 290         { "tx_collide_11times" },
 291         { "tx_collide_12times" },
 292         { "tx_collide_13times" },
 293         { "tx_collide_14times" },
 294         { "tx_collide_15times" },
 295         { "tx_ucast_packets" },
 296         { "tx_mcast_packets" },
 297         { "tx_bcast_packets" },
 298         { "tx_carrier_sense_errors" },
 299         { "tx_discards" },
 300         { "tx_errors" },
 301
 302         { "dma_writeq_full" },
 303         { "dma_write_prioq_full" },
 304         { "rxbds_empty" },
 305         { "rx_discards" },
 306         { "rx_errors" },
 307         { "rx_threshold_hit" },
 308
 309         { "dma_readq_full" },
 310         { "dma_read_prioq_full" },
 311         { "tx_comp_queue_full" },
 312
 313         { "ring_set_send_prod_index" },
 314         { "ring_status_update" },
 315         { "nic_irqs" },
 316         { "nic_avoided_irqs" },
 317         { "nic_tx_threshold_hit" }
 318 };
 319
 320 static const struct {
 321         const char string[ETH_GSTRING_LEN];
 322 } ethtool_test_keys[TG3_NUM_TEST] = {
 323         { "nvram test     (online) " },
 324         { "link test      (online) " },
 325         { "register test  (offline)" },
 326         { "memory test    (offline)" },
 327         { "loopback test  (offline)" },
 328         { "interrupt test (offline)" },
 329 };
 330
 331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 332 {
 333         writel(val, tp->regs + off);
 334 }
 335
 336 static u32 tg3_read32(struct tg3 *tp, u32 off)
 337 {
 338         return (readl(tp->regs + off));
 339 }
 340
 341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 342 {
 343         writel(val, tp->aperegs + off);
 344 }
 345
 346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 347 {
 348         return (readl(tp->aperegs + off));
 349 }
 350
 351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 352 {
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&tp->indirect_lock, flags);
 356         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 357         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 358         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 359 }
 360
 361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         writel(val, tp->regs + off);
 364         readl(tp->regs + off);
 365 }
 366
 367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 368 {
 369         unsigned long flags;
 370         u32 val;
 371
 372         spin_lock_irqsave(&tp->indirect_lock, flags);
 373         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 374         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 375         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 376         return val;
 377 }
 378
 379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         unsigned long flags;
 382
 383         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 384                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 385                                        TG3_64BIT_REG_LOW, val);
 386                 return;
 387         }
 388         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 389                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 390                                        TG3_64BIT_REG_LOW, val);
 391                 return;
 392         }
 393
 394         spin_lock_irqsave(&tp->indirect_lock, flags);
 395         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 396         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 397         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 398
 399         /* In indirect mode when disabling interrupts, we also need
 400          * to clear the interrupt bit in the GRC local ctrl register.
 401          */
 402         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 403             (val == 0x1)) {
 404                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 405                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 406         }
 407 }
 408
 409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 410 {
 411         unsigned long flags;
 412         u32 val;
 413
 414         spin_lock_irqsave(&tp->indirect_lock, flags);
 415         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 416         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418         return val;
 419 }
 420
 421 /* usec_wait specifies the wait time in usec when writing to certain registers
 422  * where it is unsafe to read back the register without some delay.
 423  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 424  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 425  */
 426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 427 {
 428         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 429             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 430                 /* Non-posted methods */
 431                 tp->write32(tp, off, val);
 432         else {
 433                 /* Posted method */
 434                 tg3_write32(tp, off, val);
 435                 if (usec_wait)
 436                         udelay(usec_wait);
 437                 tp->read32(tp, off);
 438         }
 439         /* Wait again after the read for the posted method to guarantee that
 440          * the wait time is met.
 441          */
 442         if (usec_wait)
 443                 udelay(usec_wait);
 444 }
 445
 446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 447 {
 448         tp->write32_mbox(tp, off, val);
 449         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 450             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 451                 tp->read32_mbox(tp, off);
 452 }
 453
 454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         void __iomem *mbox = tp->regs + off;
 457         writel(val, mbox);
 458         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 459                 writel(val, mbox);
 460         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 461                 readl(mbox);
 462 }
 463
 464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 465 {
 466         return (readl(tp->regs + off + GRCMBOX_BASE));
 467 }
 468
 469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 470 {
 471         writel(val, tp->regs + off + GRCMBOX_BASE);
 472 }
 473
 474 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 475 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 476 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 477 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 478 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 479
 480 #define tw32(reg,val)           tp->write32(tp, reg, val)
 481 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 483 #define tr32(reg)               tp->read32(tp, reg)
 484
 485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 486 {
 487         unsigned long flags;
 488
 489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 490             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 491                 return;
 492
 493         spin_lock_irqsave(&tp->indirect_lock, flags);
 494         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 495                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 496                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 497
 498                 /* Always leave this as zero. */
 499                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 500         } else {
 501                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 502                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 503
 504                 /* Always leave this as zero. */
 505                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 506         }
 507         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 508 }
 509
 510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 511 {
 512         unsigned long flags;
 513
 514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 516                 *val = 0;
 517                 return;
 518         }
 519
 520         spin_lock_irqsave(&tp->indirect_lock, flags);
 521         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 522                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 523                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 524
 525                 /* Always leave this as zero. */
 526                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 527         } else {
 528                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 529                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 530
 531                 /* Always leave this as zero. */
 532                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 533         }
 534         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 535 }
 536
 537 static void tg3_ape_lock_init(struct tg3 *tp)
 538 {
 539         int i;
 540
 541         /* Make sure the driver hasn't any stale locks. */
 542         for (i = 0; i < 8; i++)
 543                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 544                                 APE_LOCK_GRANT_DRIVER);
 545 }
 546
 547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 548 {
 549         int i, off;
 550         int ret = 0;
 551         u32 status;
 552
 553         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 554                 return 0;
 555
 556         switch (locknum) {
 557                 case TG3_APE_LOCK_GRC:
 558                 case TG3_APE_LOCK_MEM:
 559                         break;
 560                 default:
 561                         return -EINVAL;
 562         }
 563
 564         off = 4 * locknum;
 565
 566         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 567
 568         /* Wait for up to 1 millisecond to acquire lock. */
 569         for (i = 0; i < 100; i++) {
 570                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 571                 if (status == APE_LOCK_GRANT_DRIVER)
 572                         break;
 573                 udelay(10);
 574         }
 575
 576         if (status != APE_LOCK_GRANT_DRIVER) {
 577                 /* Revoke the lock request. */
 578                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 579                                 APE_LOCK_GRANT_DRIVER);
 580
 581                 ret = -EBUSY;
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 588 {
 589         int off;
 590
 591         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 592                 return;
 593
 594         switch (locknum) {
 595                 case TG3_APE_LOCK_GRC:
 596                 case TG3_APE_LOCK_MEM:
 597                         break;
 598                 default:
 599                         return;
 600         }
 601
 602         off = 4 * locknum;
 603         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 604 }
 605
 606 static void tg3_disable_ints(struct tg3 *tp)
 607 {
 608         tw32(TG3PCI_MISC_HOST_CTRL,
 609              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 611 }
 612
 613 static inline void tg3_cond_int(struct tg3 *tp)
 614 {
 615         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 616             (tp->hw_status->status & SD_STATUS_UPDATED))
 617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 618         else
 619                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 620                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 621 }
 622
 623 static void tg3_enable_ints(struct tg3 *tp)
 624 {
 625         tp->irq_sync = 0;
 626         wmb();
 627
 628         tw32(TG3PCI_MISC_HOST_CTRL,
 629              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 630         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 631                        (tp->last_tag << 24));
 632         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 633                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 634                                (tp->last_tag << 24));
 635         tg3_cond_int(tp);
 636 }
 637
 638 static inline unsigned int tg3_has_work(struct tg3 *tp)
 639 {
 640         struct tg3_hw_status *sblk = tp->hw_status;
 641         unsigned int work_exists = 0;
 642
 643         /* check for phy events */
 644         if (!(tp->tg3_flags &
 645               (TG3_FLAG_USE_LINKCHG_REG |
 646                TG3_FLAG_POLL_SERDES))) {
 647                 if (sblk->status & SD_STATUS_LINK_CHG)
 648                         work_exists = 1;
 649         }
 650         /* check for RX/TX work to do */
 651         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 652             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 653                 work_exists = 1;
 654
 655         return work_exists;
 656 }
 657
 658 /* tg3_restart_ints
 659  *  similar to tg3_enable_ints, but it accurately determines whether there
 660  *  is new work pending and can return without flushing the PIO write
 661  *  which reenables interrupts
 662  */
 663 static void tg3_restart_ints(struct tg3 *tp)
 664 {
 665         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 666                      tp->last_tag << 24);
 667         mmiowb();
 668
 669         /* When doing tagged status, this work check is unnecessary.
 670          * The last_tag we write above tells the chip which piece of
 671          * work we've completed.
 672          */
 673         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 674             tg3_has_work(tp))
 675                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 676                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 677 }
 678
 679 static inline void tg3_netif_stop(struct tg3 *tp)
 680 {
 681         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 682         napi_disable(&tp->napi);
 683         netif_tx_disable(tp->dev);
 684 }
 685
 686 static inline void tg3_netif_start(struct tg3 *tp)
 687 {
 688         netif_wake_queue(tp->dev);
 689         /* NOTE: unconditional netif_wake_queue is only appropriate
 690          * so long as all callers are assured to have free tx slots
 691          * (such as after tg3_init_hw)
 692          */
 693         napi_enable(&tp->napi);
 694         tp->hw_status->status |= SD_STATUS_UPDATED;
 695         tg3_enable_ints(tp);
 696 }
 697
 698 static void tg3_switch_clocks(struct tg3 *tp)
 699 {
 700         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 701         u32 orig_clock_ctrl;
 702
 703         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 704             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 705                 return;
 706
 707         orig_clock_ctrl = clock_ctrl;
 708         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 709                        CLOCK_CTRL_CLKRUN_OENABLE |
 710                        0x1f);
 711         tp->pci_clock_ctrl = clock_ctrl;
 712
 713         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 714                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 715                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 716                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 717                 }
 718         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 719                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 720                             clock_ctrl |
 721                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 722                             40);
 723                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 724                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 725                             40);
 726         }
 727         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 728 }
 729
 730 #define PHY_BUSY_LOOPS  5000
 731
 732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 733 {
 734         u32 frame_val;
 735         unsigned int loops;
 736         int ret;
 737
 738         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 739                 tw32_f(MAC_MI_MODE,
 740                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 741                 udelay(80);
 742         }
 743
 744         *val = 0x0;
 745
 746         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 747                       MI_COM_PHY_ADDR_MASK);
 748         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 749                       MI_COM_REG_ADDR_MASK);
 750         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 751
 752         tw32_f(MAC_MI_COM, frame_val);
 753
 754         loops = PHY_BUSY_LOOPS;
 755         while (loops != 0) {
 756                 udelay(10);
 757                 frame_val = tr32(MAC_MI_COM);
 758
 759                 if ((frame_val & MI_COM_BUSY) == 0) {
 760                         udelay(5);
 761                         frame_val = tr32(MAC_MI_COM);
 762                         break;
 763                 }
 764                 loops -= 1;
 765         }
 766
 767         ret = -EBUSY;
 768         if (loops != 0) {
 769                 *val = frame_val & MI_COM_DATA_MASK;
 770                 ret = 0;
 771         }
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 775                 udelay(80);
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 782 {
 783         u32 frame_val;
 784         unsigned int loops;
 785         int ret;
 786
 787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 788             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 789                 return 0;
 790
 791         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 792                 tw32_f(MAC_MI_MODE,
 793                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 794                 udelay(80);
 795         }
 796
 797         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 798                       MI_COM_PHY_ADDR_MASK);
 799         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 800                       MI_COM_REG_ADDR_MASK);
 801         frame_val |= (val & MI_COM_DATA_MASK);
 802         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 803
 804         tw32_f(MAC_MI_COM, frame_val);
 805
 806         loops = PHY_BUSY_LOOPS;
 807         while (loops != 0) {
 808                 udelay(10);
 809                 frame_val = tr32(MAC_MI_COM);
 810                 if ((frame_val & MI_COM_BUSY) == 0) {
 811                         udelay(5);
 812                         frame_val = tr32(MAC_MI_COM);
 813                         break;
 814                 }
 815                 loops -= 1;
 816         }
 817
 818         ret = -EBUSY;
 819         if (loops != 0)
 820                 ret = 0;
 821
 822         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 823                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 824                 udelay(80);
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int tg3_bmcr_reset(struct tg3 *tp)
 831 {
 832         u32 phy_control;
 833         int limit, err;
 834
 835         /* OK, reset it, and poll the BMCR_RESET bit until it
 836          * clears or we time out.
 837          */
 838         phy_control = BMCR_RESET;
 839         err = tg3_writephy(tp, MII_BMCR, phy_control);
 840         if (err != 0)
 841                 return -EBUSY;
 842
 843         limit = 5000;
 844         while (limit--) {
 845                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 846                 if (err != 0)
 847                         return -EBUSY;
 848
 849                 if ((phy_control & BMCR_RESET) == 0) {
 850                         udelay(40);
 851                         break;
 852                 }
 853                 udelay(10);
 854         }
 855         if (limit < 0)
 856                 return -EBUSY;
 857
 858         return 0;
 859 }
 860
 861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 862 {
 863         struct tg3 *tp = bp->priv;
 864         u32 val;
 865
 866         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 867                 return -EAGAIN;
 868
 869         if (tg3_readphy(tp, reg, &val))
 870                 return -EIO;
 871
 872         return val;
 873 }
 874
 875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 876 {
 877         struct tg3 *tp = bp->priv;
 878
 879         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 880                 return -EAGAIN;
 881
 882         if (tg3_writephy(tp, reg, val))
 883                 return -EIO;
 884
 885         return 0;
 886 }
 887
 888 static int tg3_mdio_reset(struct mii_bus *bp)
 889 {
 890         return 0;
 891 }
 892
 893 static void tg3_mdio_config_5785(struct tg3 *tp)
 894 {
 895         u32 val;
 896         struct phy_device *phydev;
 897
 898         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 899         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 900         case TG3_PHY_ID_BCM50610:
 901                 val = MAC_PHYCFG2_50610_LED_MODES;
 902                 break;
 903         case TG3_PHY_ID_BCMAC131:
 904                 val = MAC_PHYCFG2_AC131_LED_MODES;
 905                 break;
 906         case TG3_PHY_ID_RTL8211C:
 907                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 908                 break;
 909         case TG3_PHY_ID_RTL8201E:
 910                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 911                 break;
 912         default:
 913                 return;
 914         }
 915
 916         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 917                 tw32(MAC_PHYCFG2, val);
 918
 919                 val = tr32(MAC_PHYCFG1);
 920                 val &= ~MAC_PHYCFG1_RGMII_INT;
 921                 tw32(MAC_PHYCFG1, val);
 922
 923                 return;
 924         }
 925
 926         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 927                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 928                        MAC_PHYCFG2_FMODE_MASK_MASK |
 929                        MAC_PHYCFG2_GMODE_MASK_MASK |
 930                        MAC_PHYCFG2_ACT_MASK_MASK   |
 931                        MAC_PHYCFG2_QUAL_MASK_MASK |
 932                        MAC_PHYCFG2_INBAND_ENABLE;
 933
 934         tw32(MAC_PHYCFG2, val);
 935
 936         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 937                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 938         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 939                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 940                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 941                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 942                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 943         }
 944         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 945
 946         val = tr32(MAC_EXT_RGMII_MODE);
 947         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 948                  MAC_RGMII_MODE_RX_QUALITY |
 949                  MAC_RGMII_MODE_RX_ACTIVITY |
 950                  MAC_RGMII_MODE_RX_ENG_DET |
 951                  MAC_RGMII_MODE_TX_ENABLE |
 952                  MAC_RGMII_MODE_TX_LOWPWR |
 953                  MAC_RGMII_MODE_TX_RESET);
 954         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 956                         val |= MAC_RGMII_MODE_RX_INT_B |
 957                                MAC_RGMII_MODE_RX_QUALITY |
 958                                MAC_RGMII_MODE_RX_ACTIVITY |
 959                                MAC_RGMII_MODE_RX_ENG_DET;
 960                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 961                         val |= MAC_RGMII_MODE_TX_ENABLE |
 962                                MAC_RGMII_MODE_TX_LOWPWR |
 963                                MAC_RGMII_MODE_TX_RESET;
 964         }
 965         tw32(MAC_EXT_RGMII_MODE, val);
 966 }
 967
 968 static void tg3_mdio_start(struct tg3 *tp)
 969 {
 970         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 971                 mutex_lock(&tp->mdio_bus->mdio_lock);
 972                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 973                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 974         }
 975
 976         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 977         tw32_f(MAC_MI_MODE, tp->mi_mode);
 978         udelay(80);
 979
 980         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 982                 tg3_mdio_config_5785(tp);
 983 }
 984
 985 static void tg3_mdio_stop(struct tg3 *tp)
 986 {
 987         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 988                 mutex_lock(&tp->mdio_bus->mdio_lock);
 989                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 990                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 991         }
 992 }
 993
 994 static int tg3_mdio_init(struct tg3 *tp)
 995 {
 996         int i;
 997         u32 reg;
 998         struct phy_device *phydev;
 999
1000         tg3_mdio_start(tp);
1001
1002         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004                 return 0;
1005
1006         tp->mdio_bus = mdiobus_alloc();
1007         if (tp->mdio_bus == NULL)
1008                 return -ENOMEM;
1009
1010         tp->mdio_bus->name     = "tg3 mdio bus";
1011         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013         tp->mdio_bus->priv     = tp;
1014         tp->mdio_bus->parent   = &tp->pdev->dev;
1015         tp->mdio_bus->read     = &tg3_mdio_read;
1016         tp->mdio_bus->write    = &tg3_mdio_write;
1017         tp->mdio_bus->reset    = &tg3_mdio_reset;
1018         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1020
1021         for (i = 0; i < PHY_MAX_ADDR; i++)
1022                 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024         /* The bus registration will look for all the PHYs on the mdio bus.
1025          * Unfortunately, it does not ensure the PHY is powered up before
1026          * accessing the PHY ID registers.  A chip reset is the
1027          * quickest way to bring the device back to an operational state..
1028          */
1029         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030                 tg3_bmcr_reset(tp);
1031
1032         i = mdiobus_register(tp->mdio_bus);
1033         if (i) {
1034                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035                         tp->dev->name, i);
1036                 mdiobus_free(tp->mdio_bus);
1037                 return i;
1038         }
1039
1040         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042         if (!phydev || !phydev->drv) {
1043                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044                 mdiobus_unregister(tp->mdio_bus);
1045                 mdiobus_free(tp->mdio_bus);
1046                 return -ENODEV;
1047         }
1048
1049         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050         case TG3_PHY_ID_BCM57780:
1051                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052                 break;
1053         case TG3_PHY_ID_BCM50610:
1054                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060                 /* fallthru */
1061         case TG3_PHY_ID_RTL8211C:
1062                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063                 break;
1064         case TG3_PHY_ID_RTL8201E:
1065         case TG3_PHY_ID_BCMAC131:
1066                 phydev->interface = PHY_INTERFACE_MODE_MII;
1067                 break;
1068         }
1069
1070         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073                 tg3_mdio_config_5785(tp);
1074
1075         return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082                 mdiobus_unregister(tp->mdio_bus);
1083                 mdiobus_free(tp->mdio_bus);
1084                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085         }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091         u32 val;
1092
1093         val = tr32(GRC_RX_CPU_EVENT);
1094         val |= GRC_RX_CPU_DRIVER_EVENT;
1095         tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097         tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105         int i;
1106         unsigned int delay_cnt;
1107         long time_remain;
1108
1109         /* If enough time has passed, no wait is necessary. */
1110         time_remain = (long)(tp->last_event_jiffies + 1 +
1111                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112                       (long)jiffies;
1113         if (time_remain < 0)
1114                 return;
1115
1116         /* Check if we can shorten the wait time. */
1117         delay_cnt = jiffies_to_usecs(time_remain);
1118         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120         delay_cnt = (delay_cnt >> 3) + 1;
1121
1122         for (i = 0; i < delay_cnt; i++) {
1123                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124                         break;
1125                 udelay(8);
1126         }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132         u32 reg;
1133         u32 val;
1134
1135         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1137                 return;
1138
1139         tg3_wait_for_event_ack(tp);
1140
1141         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145         val = 0;
1146         if (!tg3_readphy(tp, MII_BMCR, &reg))
1147                 val = reg << 16;
1148         if (!tg3_readphy(tp, MII_BMSR, &reg))
1149                 val |= (reg & 0xffff);
1150         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152         val = 0;
1153         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154                 val = reg << 16;
1155         if (!tg3_readphy(tp, MII_LPA, &reg))
1156                 val |= (reg & 0xffff);
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159         val = 0;
1160         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162                         val = reg << 16;
1163                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164                         val |= (reg & 0xffff);
1165         }
1166         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169                 val = reg << 16;
1170         else
1171                 val = 0;
1172         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174         tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179         if (!netif_carrier_ok(tp->dev)) {
1180                 if (netif_msg_link(tp))
1181                         printk(KERN_INFO PFX "%s: Link is down.\n",
1182                                tp->dev->name);
1183                 tg3_ump_link_report(tp);
1184         } else if (netif_msg_link(tp)) {
1185                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186                        tp->dev->name,
1187                        (tp->link_config.active_speed == SPEED_1000 ?
1188                         1000 :
1189                         (tp->link_config.active_speed == SPEED_100 ?
1190                          100 : 10)),
1191                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1192                         "full" : "half"));
1193
1194                 printk(KERN_INFO PFX
1195                        "%s: Flow control is %s for TX and %s for RX.\n",
1196                        tp->dev->name,
1197                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198                        "on" : "off",
1199                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200                        "on" : "off");
1201                 tg3_ump_link_report(tp);
1202         }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207         u16 miireg;
1208
1209         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210                 miireg = ADVERTISE_PAUSE_CAP;
1211         else if (flow_ctrl & FLOW_CTRL_TX)
1212                 miireg = ADVERTISE_PAUSE_ASYM;
1213         else if (flow_ctrl & FLOW_CTRL_RX)
1214                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215         else
1216                 miireg = 0;
1217
1218         return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223         u16 miireg;
1224
1225         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226                 miireg = ADVERTISE_1000XPAUSE;
1227         else if (flow_ctrl & FLOW_CTRL_TX)
1228                 miireg = ADVERTISE_1000XPSE_ASYM;
1229         else if (flow_ctrl & FLOW_CTRL_RX)
1230                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231         else
1232                 miireg = 0;
1233
1234         return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239         u8 cap = 0;
1240
1241         if (lcladv & ADVERTISE_1000XPAUSE) {
1242                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243                         if (rmtadv & LPA_1000XPAUSE)
1244                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246                                 cap = FLOW_CTRL_RX;
1247                 } else {
1248                         if (rmtadv & LPA_1000XPAUSE)
1249                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250                 }
1251         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253                         cap = FLOW_CTRL_TX;
1254         }
1255
1256         return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261         u8 autoneg;
1262         u8 flowctrl = 0;
1263         u32 old_rx_mode = tp->rx_mode;
1264         u32 old_tx_mode = tp->tx_mode;
1265
1266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268         else
1269                 autoneg = tp->link_config.autoneg;
1270
1271         if (autoneg == AUTONEG_ENABLE &&
1272             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275                 else
1276                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277         } else
1278                 flowctrl = tp->link_config.flowctrl;
1279
1280         tp->link_config.active_flowctrl = flowctrl;
1281
1282         if (flowctrl & FLOW_CTRL_RX)
1283                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284         else
1285                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287         if (old_rx_mode != tp->rx_mode)
1288                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290         if (flowctrl & FLOW_CTRL_TX)
1291                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292         else
1293                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295         if (old_tx_mode != tp->tx_mode)
1296                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301         u8 oldflowctrl, linkmesg = 0;
1302         u32 mac_mode, lcl_adv, rmt_adv;
1303         struct tg3 *tp = netdev_priv(dev);
1304         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306         spin_lock(&tp->lock);
1307
1308         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309                                     MAC_MODE_HALF_DUPLEX);
1310
1311         oldflowctrl = tp->link_config.active_flowctrl;
1312
1313         if (phydev->link) {
1314                 lcl_adv = 0;
1315                 rmt_adv = 0;
1316
1317                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1319                 else
1320                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322                 if (phydev->duplex == DUPLEX_HALF)
1323                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1324                 else {
1325                         lcl_adv = tg3_advert_flowctrl_1000T(
1326                                   tp->link_config.flowctrl);
1327
1328                         if (phydev->pause)
1329                                 rmt_adv = LPA_PAUSE_CAP;
1330                         if (phydev->asym_pause)
1331                                 rmt_adv |= LPA_PAUSE_ASYM;
1332                 }
1333
1334                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335         } else
1336                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338         if (mac_mode != tp->mac_mode) {
1339                 tp->mac_mode = mac_mode;
1340                 tw32_f(MAC_MODE, tp->mac_mode);
1341                 udelay(40);
1342         }
1343
1344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345                 if (phydev->speed == SPEED_10)
1346                         tw32(MAC_MI_STAT,
1347                              MAC_MI_STAT_10MBPS_MODE |
1348                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349                 else
1350                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351         }
1352
1353         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354                 tw32(MAC_TX_LENGTHS,
1355                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356                       (6 << TX_LENGTHS_IPG_SHIFT) |
1357                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358         else
1359                 tw32(MAC_TX_LENGTHS,
1360                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361                       (6 << TX_LENGTHS_IPG_SHIFT) |
1362                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366             phydev->speed != tp->link_config.active_speed ||
1367             phydev->duplex != tp->link_config.active_duplex ||
1368             oldflowctrl != tp->link_config.active_flowctrl)
1369             linkmesg = 1;
1370
1371         tp->link_config.active_speed = phydev->speed;
1372         tp->link_config.active_duplex = phydev->duplex;
1373
1374         spin_unlock(&tp->lock);
1375
1376         if (linkmesg)
1377                 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382         struct phy_device *phydev;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385                 return 0;
1386
1387         /* Bring the PHY back to a known state. */
1388         tg3_bmcr_reset(tp);
1389
1390         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392         /* Attach the MAC to the PHY. */
1393         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394                              phydev->dev_flags, phydev->interface);
1395         if (IS_ERR(phydev)) {
1396                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397                 return PTR_ERR(phydev);
1398         }
1399
1400         /* Mask with MAC supported features. */
1401         switch (phydev->interface) {
1402         case PHY_INTERFACE_MODE_GMII:
1403         case PHY_INTERFACE_MODE_RGMII:
1404                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405                         phydev->supported &= (PHY_GBIT_FEATURES |
1406                                               SUPPORTED_Pause |
1407                                               SUPPORTED_Asym_Pause);
1408                         break;
1409                 }
1410                 /* fallthru */
1411         case PHY_INTERFACE_MODE_MII:
1412                 phydev->supported &= (PHY_BASIC_FEATURES |
1413                                       SUPPORTED_Pause |
1414                                       SUPPORTED_Asym_Pause);
1415                 break;
1416         default:
1417                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418                 return -EINVAL;
1419         }
1420
1421         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423         phydev->advertising = phydev->supported;
1424
1425         return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430         struct phy_device *phydev;
1431
1432         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433                 return;
1434
1435         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437         if (tp->link_config.phy_is_low_power) {
1438                 tp->link_config.phy_is_low_power = 0;
1439                 phydev->speed = tp->link_config.orig_speed;
1440                 phydev->duplex = tp->link_config.orig_duplex;
1441                 phydev->autoneg = tp->link_config.orig_autoneg;
1442                 phydev->advertising = tp->link_config.orig_advertising;
1443         }
1444
1445         phy_start(phydev);
1446
1447         phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453                 return;
1454
1455         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463         }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474         u32 reg;
1475
1476         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478                 return;
1479
1480         reg = MII_TG3_MISC_SHDW_WREN |
1481               MII_TG3_MISC_SHDW_SCR5_SEL |
1482               MII_TG3_MISC_SHDW_SCR5_LPED |
1483               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484               MII_TG3_MISC_SHDW_SCR5_SDTL |
1485               MII_TG3_MISC_SHDW_SCR5_C125OE;
1486         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492         reg = MII_TG3_MISC_SHDW_WREN |
1493               MII_TG3_MISC_SHDW_APD_SEL |
1494               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495         if (enable)
1496                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503         u32 phy;
1504
1505         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507                 return;
1508
1509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510                 u32 ephy;
1511
1512                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1515                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516                                 if (enable)
1517                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518                                 else
1519                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521                         }
1522                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523                 }
1524         } else {
1525                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1527                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529                         if (enable)
1530                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531                         else
1532                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1534                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535                 }
1536         }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541         u32 val;
1542
1543         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544                 return;
1545
1546         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549                              (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554         u32 otp, phy;
1555
1556         if (!tp->phy_otp)
1557                 return;
1558
1559         otp = tp->phy_otp;
1560
1561         /* Enable SM_DSP clock and tx 6dB coding. */
1562         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564               MII_TG3_AUXCTL_ACTL_TX_6DB;
1565         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589         /* Turn off SM_DSP clock. */
1590         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591               MII_TG3_AUXCTL_ACTL_TX_6DB;
1592         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597         int limit = 100;
1598
1599         while (limit--) {
1600                 u32 tmp32;
1601
1602                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603                         if ((tmp32 & 0x1000) == 0)
1604                                 break;
1605                 }
1606         }
1607         if (limit < 0)
1608                 return -EBUSY;
1609
1610         return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615         static const u32 test_pat[4][6] = {
1616         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620         };
1621         int chan;
1622
1623         for (chan = 0; chan < 4; chan++) {
1624                 int i;
1625
1626                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627                              (chan * 0x2000) | 0x0200);
1628                 tg3_writephy(tp, 0x16, 0x0002);
1629
1630                 for (i = 0; i < 6; i++)
1631                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632                                      test_pat[chan][i]);
1633
1634                 tg3_writephy(tp, 0x16, 0x0202);
1635                 if (tg3_wait_macro_done(tp)) {
1636                         *resetp = 1;
1637                         return -EBUSY;
1638                 }
1639
1640                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641                              (chan * 0x2000) | 0x0200);
1642                 tg3_writephy(tp, 0x16, 0x0082);
1643                 if (tg3_wait_macro_done(tp)) {
1644                         *resetp = 1;
1645                         return -EBUSY;
1646                 }
1647
1648                 tg3_writephy(tp, 0x16, 0x0802);
1649                 if (tg3_wait_macro_done(tp)) {
1650                         *resetp = 1;
1651                         return -EBUSY;
1652                 }
1653
1654                 for (i = 0; i < 6; i += 2) {
1655                         u32 low, high;
1656
1657                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659                             tg3_wait_macro_done(tp)) {
1660                                 *resetp = 1;
1661                                 return -EBUSY;
1662                         }
1663                         low &= 0x7fff;
1664                         high &= 0x000f;
1665                         if (low != test_pat[chan][i] ||
1666                             high != test_pat[chan][i+1]) {
1667                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671                                 return -EBUSY;
1672                         }
1673                 }
1674         }
1675
1676         return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681         int chan;
1682
1683         for (chan = 0; chan < 4; chan++) {
1684                 int i;
1685
1686                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687                              (chan * 0x2000) | 0x0200);
1688                 tg3_writephy(tp, 0x16, 0x0002);
1689                 for (i = 0; i < 6; i++)
1690                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691                 tg3_writephy(tp, 0x16, 0x0202);
1692                 if (tg3_wait_macro_done(tp))
1693                         return -EBUSY;
1694         }
1695
1696         return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701         u32 reg32, phy9_orig;
1702         int retries, do_phy_reset, err;
1703
1704         retries = 10;
1705         do_phy_reset = 1;
1706         do {
1707                 if (do_phy_reset) {
1708                         err = tg3_bmcr_reset(tp);
1709                         if (err)
1710                                 return err;
1711                         do_phy_reset = 0;
1712                 }
1713
1714                 /* Disable transmitter and interrupt.  */
1715                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716                         continue;
1717
1718                 reg32 |= 0x3000;
1719                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721                 /* Set full-duplex, 1000 mbps.  */
1722                 tg3_writephy(tp, MII_BMCR,
1723                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725                 /* Set to master mode.  */
1726                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727                         continue;
1728
1729                 tg3_writephy(tp, MII_TG3_CTRL,
1730                              (MII_TG3_CTRL_AS_MASTER |
1731                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733                 /* Enable SM_DSP_CLOCK and 6dB.  */
1734                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736                 /* Block the PHY control access.  */
1737                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741                 if (!err)
1742                         break;
1743         } while (--retries);
1744
1745         err = tg3_phy_reset_chanpat(tp);
1746         if (err)
1747                 return err;
1748
1749         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753         tg3_writephy(tp, 0x16, 0x0000);
1754
1755         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757                 /* Set Extended packet length bit for jumbo frames */
1758                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759         }
1760         else {
1761                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762         }
1763
1764         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767                 reg32 &= ~0x3000;
1768                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769         } else if (!err)
1770                 err = -EBUSY;
1771
1772         return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776  * link unless the FORCE argument is non-zero.
1777  */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780         u32 cpmuctrl;
1781         u32 phy_status;
1782         int err;
1783
1784         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785                 u32 val;
1786
1787                 val = tr32(GRC_MISC_CFG);
1788                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789                 udelay(40);
1790         }
1791         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1792         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793         if (err != 0)
1794                 return -EBUSY;
1795
1796         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797                 netif_carrier_off(tp->dev);
1798                 tg3_link_report(tp);
1799         }
1800
1801         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804                 err = tg3_phy_reset_5703_4_5(tp);
1805                 if (err)
1806                         return err;
1807                 goto out;
1808         }
1809
1810         cpmuctrl = 0;
1811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815                         tw32(TG3_CPMU_CTRL,
1816                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817         }
1818
1819         err = tg3_bmcr_reset(tp);
1820         if (err)
1821                 return err;
1822
1823         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824                 u32 phy;
1825
1826                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830         }
1831
1832         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834                 u32 val;
1835
1836                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1839                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840                         udelay(40);
1841                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842                 }
1843         }
1844
1845         tg3_phy_apply_otp(tp);
1846
1847         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848                 tg3_phy_toggle_apd(tp, true);
1849         else
1850                 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860         }
1861         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862                 tg3_writephy(tp, 0x1c, 0x8d68);
1863                 tg3_writephy(tp, 0x1c, 0x8d68);
1864         }
1865         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874         }
1875         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880                         tg3_writephy(tp, MII_TG3_TEST1,
1881                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1882                 } else
1883                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885         }
1886         /* Set Extended packet length bit (bit 14) on all chips that */
1887         /* support jumbo frames */
1888         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889                 /* Cannot do read-modify-write on 5401 */
1890                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892                 u32 phy_reg;
1893
1894                 /* Set bit 14 with read-modify-write to preserve other bits */
1895                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898         }
1899
1900         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901          * jumbo frames transmission.
1902          */
1903         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904                 u32 phy_reg;
1905
1906                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909         }
1910
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912                 /* adjust output voltage */
1913                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914         }
1915
1916         tg3_phy_toggle_automdix(tp, 1);
1917         tg3_phy_set_wirespeed(tp);
1918         return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923         struct tg3 *tp_peer = tp;
1924
1925         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926                 return;
1927
1928         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930                 struct net_device *dev_peer;
1931
1932                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933                 /* remove_one() may have been run on the peer. */
1934                 if (!dev_peer)
1935                         tp_peer = tp;
1936                 else
1937                         tp_peer = netdev_priv(dev_peer);
1938         }
1939
1940         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947                                     (GRC_LCLCTRL_GPIO_OE0 |
1948                                      GRC_LCLCTRL_GPIO_OE1 |
1949                                      GRC_LCLCTRL_GPIO_OE2 |
1950                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1951                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1952                                     100);
1953                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1954                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1955                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1956                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1957                                              GRC_LCLCTRL_GPIO_OE1 |
1958                                              GRC_LCLCTRL_GPIO_OE2 |
1959                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1960                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1961                                              tp->grc_local_ctrl;
1962                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1963
1964                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1965                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1966
1967                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1968                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1969                 } else {
1970                         u32 no_gpio2;
1971                         u32 grc_local_ctrl = 0;
1972
1973                         if (tp_peer != tp &&
1974                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1975                                 return;
1976
1977                         /* Workaround to prevent overdrawing Amps. */
1978                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1979                             ASIC_REV_5714) {
1980                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1981                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1982                                             grc_local_ctrl, 100);
1983                         }
1984
1985                         /* On 5753 and variants, GPIO2 cannot be used. */
1986                         no_gpio2 = tp->nic_sram_data_cfg &
1987                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1988
1989                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1990                                          GRC_LCLCTRL_GPIO_OE1 |
1991                                          GRC_LCLCTRL_GPIO_OE2 |
1992                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1993                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1994                         if (no_gpio2) {
1995                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1996                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1997                         }
1998                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1999                                                     grc_local_ctrl, 100);
2000
2001                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2002
2003                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2004                                                     grc_local_ctrl, 100);
2005
2006                         if (!no_gpio2) {
2007                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2008                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2009                                             grc_local_ctrl, 100);
2010                         }
2011                 }
2012         } else {
2013                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2014                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2015                         if (tp_peer != tp &&
2016                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017                                 return;
2018
2019                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2020                                     (GRC_LCLCTRL_GPIO_OE1 |
2021                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2022
2023                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024                                     GRC_LCLCTRL_GPIO_OE1, 100);
2025
2026                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027                                     (GRC_LCLCTRL_GPIO_OE1 |
2028                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2029                 }
2030         }
2031 }
2032
2033 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2034 {
2035         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2036                 return 1;
2037         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2038                 if (speed != SPEED_10)
2039                         return 1;
2040         } else if (speed == SPEED_10)
2041                 return 1;
2042
2043         return 0;
2044 }
2045
2046 static int tg3_setup_phy(struct tg3 *, int);
2047
2048 #define RESET_KIND_SHUTDOWN     0
2049 #define RESET_KIND_INIT         1
2050 #define RESET_KIND_SUSPEND      2
2051
2052 static void tg3_write_sig_post_reset(struct tg3 *, int);
2053 static int tg3_halt_cpu(struct tg3 *, u32);
2054
2055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056 {
2057         u32 val;
2058
2059         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064                         sg_dig_ctrl |=
2065                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068                 }
2069                 return;
2070         }
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2073                 tg3_bmcr_reset(tp);
2074                 val = tr32(GRC_MISC_CFG);
2075                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076                 udelay(40);
2077                 return;
2078         } else if (do_low_power) {
2079                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081
2082                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2087         }
2088
2089         /* The PHY should not be powered down on some chips because
2090          * of bugs.
2091          */
2092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096                 return;
2097
2098         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104         }
2105
2106         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107 }
2108
2109 /* tp->lock is held. */
2110 static int tg3_nvram_lock(struct tg3 *tp)
2111 {
2112         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2113                 int i;
2114
2115                 if (tp->nvram_lock_cnt == 0) {
2116                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2117                         for (i = 0; i < 8000; i++) {
2118                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2119                                         break;
2120                                 udelay(20);
2121                         }
2122                         if (i == 8000) {
2123                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2124                                 return -ENODEV;
2125                         }
2126                 }
2127                 tp->nvram_lock_cnt++;
2128         }
2129         return 0;
2130 }
2131
2132 /* tp->lock is held. */
2133 static void tg3_nvram_unlock(struct tg3 *tp)
2134 {
2135         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2136                 if (tp->nvram_lock_cnt > 0)
2137                         tp->nvram_lock_cnt--;
2138                 if (tp->nvram_lock_cnt == 0)
2139                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2140         }
2141 }
2142
2143 /* tp->lock is held. */
2144 static void tg3_enable_nvram_access(struct tg3 *tp)
2145 {
2146         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2147             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2148                 u32 nvaccess = tr32(NVRAM_ACCESS);
2149
2150                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2151         }
2152 }
2153
2154 /* tp->lock is held. */
2155 static void tg3_disable_nvram_access(struct tg3 *tp)
2156 {
2157         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2158             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2159                 u32 nvaccess = tr32(NVRAM_ACCESS);
2160
2161                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2162         }
2163 }
2164
2165 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2166                                         u32 offset, u32 *val)
2167 {
2168         u32 tmp;
2169         int i;
2170
2171         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2172                 return -EINVAL;
2173
2174         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2175                                         EEPROM_ADDR_DEVID_MASK |
2176                                         EEPROM_ADDR_READ);
2177         tw32(GRC_EEPROM_ADDR,
2178              tmp |
2179              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2180              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2181               EEPROM_ADDR_ADDR_MASK) |
2182              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2183
2184         for (i = 0; i < 1000; i++) {
2185                 tmp = tr32(GRC_EEPROM_ADDR);
2186
2187                 if (tmp & EEPROM_ADDR_COMPLETE)
2188                         break;
2189                 msleep(1);
2190         }
2191         if (!(tmp & EEPROM_ADDR_COMPLETE))
2192                 return -EBUSY;
2193
2194         tmp = tr32(GRC_EEPROM_DATA);
2195
2196         /*
2197          * The data will always be opposite the native endian
2198          * format.  Perform a blind byteswap to compensate.
2199          */
2200         *val = swab32(tmp);
2201
2202         return 0;
2203 }
2204
2205 #define NVRAM_CMD_TIMEOUT 10000
2206
2207 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2208 {
2209         int i;
2210
2211         tw32(NVRAM_CMD, nvram_cmd);
2212         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2213                 udelay(10);
2214                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2215                         udelay(10);
2216                         break;
2217                 }
2218         }
2219
2220         if (i == NVRAM_CMD_TIMEOUT)
2221                 return -EBUSY;
2222
2223         return 0;
2224 }
2225
2226 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2227 {
2228         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2229             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2230             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2231            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2232             (tp->nvram_jedecnum == JEDEC_ATMEL))
2233
2234                 addr = ((addr / tp->nvram_pagesize) <<
2235                         ATMEL_AT45DB0X1B_PAGE_POS) +
2236                        (addr % tp->nvram_pagesize);
2237
2238         return addr;
2239 }
2240
2241 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2242 {
2243         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2244             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2245             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2246            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2247             (tp->nvram_jedecnum == JEDEC_ATMEL))
2248
2249                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2250                         tp->nvram_pagesize) +
2251                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2252
2253         return addr;
2254 }
2255
2256 /* NOTE: Data read in from NVRAM is byteswapped according to
2257  * the byteswapping settings for all other register accesses.
2258  * tg3 devices are BE devices, so on a BE machine, the data
2259  * returned will be exactly as it is seen in NVRAM.  On a LE
2260  * machine, the 32-bit value will be byteswapped.
2261  */
2262 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2263 {
2264         int ret;
2265
2266         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2267                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2268
2269         offset = tg3_nvram_phys_addr(tp, offset);
2270
2271         if (offset > NVRAM_ADDR_MSK)
2272                 return -EINVAL;
2273
2274         ret = tg3_nvram_lock(tp);
2275         if (ret)
2276                 return ret;
2277
2278         tg3_enable_nvram_access(tp);
2279
2280         tw32(NVRAM_ADDR, offset);
2281         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2282                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2283
2284         if (ret == 0)
2285                 *val = tr32(NVRAM_RDDATA);
2286
2287         tg3_disable_nvram_access(tp);
2288
2289         tg3_nvram_unlock(tp);
2290
2291         return ret;
2292 }
2293
2294 /* Ensures NVRAM data is in bytestream format. */
2295 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2296 {
2297         u32 v;
2298         int res = tg3_nvram_read(tp, offset, &v);
2299         if (!res)
2300                 *val = cpu_to_be32(v);
2301         return res;
2302 }
2303
2304 /* tp->lock is held. */
2305 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2306 {
2307         u32 addr_high, addr_low;
2308         int i;
2309
2310         addr_high = ((tp->dev->dev_addr[0] << 8) |
2311                      tp->dev->dev_addr[1]);
2312         addr_low = ((tp->dev->dev_addr[2] << 24) |
2313                     (tp->dev->dev_addr[3] << 16) |
2314                     (tp->dev->dev_addr[4] <<  8) |
2315                     (tp->dev->dev_addr[5] <<  0));
2316         for (i = 0; i < 4; i++) {
2317                 if (i == 1 && skip_mac_1)
2318                         continue;
2319                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2320                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2321         }
2322
2323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2324             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2325                 for (i = 0; i < 12; i++) {
2326                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2327                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2328                 }
2329         }
2330
2331         addr_high = (tp->dev->dev_addr[0] +
2332                      tp->dev->dev_addr[1] +
2333                      tp->dev->dev_addr[2] +
2334                      tp->dev->dev_addr[3] +
2335                      tp->dev->dev_addr[4] +
2336                      tp->dev->dev_addr[5]) &
2337                 TX_BACKOFF_SEED_MASK;
2338         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2339 }
2340
2341 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2342 {
2343         u32 misc_host_ctrl;
2344         bool device_should_wake, do_low_power;
2345
2346         /* Make sure register accesses (indirect or otherwise)
2347          * will function correctly.
2348          */
2349         pci_write_config_dword(tp->pdev,
2350                                TG3PCI_MISC_HOST_CTRL,
2351                                tp->misc_host_ctrl);
2352
2353         switch (state) {
2354         case PCI_D0:
2355                 pci_enable_wake(tp->pdev, state, false);
2356                 pci_set_power_state(tp->pdev, PCI_D0);
2357
2358                 /* Switch out of Vaux if it is a NIC */
2359                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2360                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2361
2362                 return 0;
2363
2364         case PCI_D1:
2365         case PCI_D2:
2366         case PCI_D3hot:
2367                 break;
2368
2369         default:
2370                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2371                         tp->dev->name, state);
2372                 return -EINVAL;
2373         }
2374
2375         /* Restore the CLKREQ setting. */
2376         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2377                 u16 lnkctl;
2378
2379                 pci_read_config_word(tp->pdev,
2380                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2381                                      &lnkctl);
2382                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2383                 pci_write_config_word(tp->pdev,
2384                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2385                                       lnkctl);
2386         }
2387
2388         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2389         tw32(TG3PCI_MISC_HOST_CTRL,
2390              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2391
2392         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2393                              device_may_wakeup(&tp->pdev->dev) &&
2394                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2395
2396         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2397                 do_low_power = false;
2398                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2399                     !tp->link_config.phy_is_low_power) {
2400                         struct phy_device *phydev;
2401                         u32 phyid, advertising;
2402
2403                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2404
2405                         tp->link_config.phy_is_low_power = 1;
2406
2407                         tp->link_config.orig_speed = phydev->speed;
2408                         tp->link_config.orig_duplex = phydev->duplex;
2409                         tp->link_config.orig_autoneg = phydev->autoneg;
2410                         tp->link_config.orig_advertising = phydev->advertising;
2411
2412                         advertising = ADVERTISED_TP |
2413                                       ADVERTISED_Pause |
2414                                       ADVERTISED_Autoneg |
2415                                       ADVERTISED_10baseT_Half;
2416
2417                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2418                             device_should_wake) {
2419                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2420                                         advertising |=
2421                                                 ADVERTISED_100baseT_Half |
2422                                                 ADVERTISED_100baseT_Full |
2423                                                 ADVERTISED_10baseT_Full;
2424                                 else
2425                                         advertising |= ADVERTISED_10baseT_Full;
2426                         }
2427
2428                         phydev->advertising = advertising;
2429
2430                         phy_start_aneg(phydev);
2431
2432                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2433                         if (phyid != TG3_PHY_ID_BCMAC131) {
2434                                 phyid &= TG3_PHY_OUI_MASK;
2435                                 if (phyid == TG3_PHY_OUI_1 ||
2436                                     phyid == TG3_PHY_OUI_2 ||
2437                                     phyid == TG3_PHY_OUI_3)
2438                                         do_low_power = true;
2439                         }
2440                 }
2441         } else {
2442                 do_low_power = true;
2443
2444                 if (tp->link_config.phy_is_low_power == 0) {
2445                         tp->link_config.phy_is_low_power = 1;
2446                         tp->link_config.orig_speed = tp->link_config.speed;
2447                         tp->link_config.orig_duplex = tp->link_config.duplex;
2448                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2449                 }
2450
2451                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2452                         tp->link_config.speed = SPEED_10;
2453                         tp->link_config.duplex = DUPLEX_HALF;
2454                         tp->link_config.autoneg = AUTONEG_ENABLE;
2455                         tg3_setup_phy(tp, 0);
2456                 }
2457         }
2458
2459         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2460                 u32 val;
2461
2462                 val = tr32(GRC_VCPU_EXT_CTRL);
2463                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2464         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2465                 int i;
2466                 u32 val;
2467
2468                 for (i = 0; i < 200; i++) {
2469                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2470                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2471                                 break;
2472                         msleep(1);
2473                 }
2474         }
2475         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2476                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2477                                                      WOL_DRV_STATE_SHUTDOWN |
2478                                                      WOL_DRV_WOL |
2479                                                      WOL_SET_MAGIC_PKT);
2480
2481         if (device_should_wake) {
2482                 u32 mac_mode;
2483
2484                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2485                         if (do_low_power) {
2486                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2487                                 udelay(40);
2488                         }
2489
2490                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2491                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2492                         else
2493                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2494
2495                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2496                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2497                             ASIC_REV_5700) {
2498                                 u32 speed = (tp->tg3_flags &
2499                                              TG3_FLAG_WOL_SPEED_100MB) ?
2500                                              SPEED_100 : SPEED_10;
2501                                 if (tg3_5700_link_polarity(tp, speed))
2502                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2503                                 else
2504                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2505                         }
2506                 } else {
2507                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2508                 }
2509
2510                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2511                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2512
2513                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2514                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2515                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2516                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2517                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2518                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2519
2520                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2521                         mac_mode |= tp->mac_mode &
2522                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2523                         if (mac_mode & MAC_MODE_APE_TX_EN)
2524                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2525                 }
2526
2527                 tw32_f(MAC_MODE, mac_mode);
2528                 udelay(100);
2529
2530                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2531                 udelay(10);
2532         }
2533
2534         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2535             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2536              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2537                 u32 base_val;
2538
2539                 base_val = tp->pci_clock_ctrl;
2540                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2541                              CLOCK_CTRL_TXCLK_DISABLE);
2542
2543                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2544                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2545         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2546                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2547                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2548                 /* do nothing */
2549         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2550                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2551                 u32 newbits1, newbits2;
2552
2553                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2554                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2555                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2556                                     CLOCK_CTRL_TXCLK_DISABLE |
2557                                     CLOCK_CTRL_ALTCLK);
2558                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2559                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2560                         newbits1 = CLOCK_CTRL_625_CORE;
2561                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2562                 } else {
2563                         newbits1 = CLOCK_CTRL_ALTCLK;
2564                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2565                 }
2566
2567                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2568                             40);
2569
2570                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2571                             40);
2572
2573                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2574                         u32 newbits3;
2575
2576                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2577                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2578                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2579                                             CLOCK_CTRL_TXCLK_DISABLE |
2580                                             CLOCK_CTRL_44MHZ_CORE);
2581                         } else {
2582                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2583                         }
2584
2585                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2586                                     tp->pci_clock_ctrl | newbits3, 40);
2587                 }
2588         }
2589
2590         if (!(device_should_wake) &&
2591             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2592                 tg3_power_down_phy(tp, do_low_power);
2593
2594         tg3_frob_aux_power(tp);
2595
2596         /* Workaround for unstable PLL clock */
2597         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2598             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2599                 u32 val = tr32(0x7d00);
2600
2601                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2602                 tw32(0x7d00, val);
2603                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2604                         int err;
2605
2606                         err = tg3_nvram_lock(tp);
2607                         tg3_halt_cpu(tp, RX_CPU_BASE);
2608                         if (!err)
2609                                 tg3_nvram_unlock(tp);
2610                 }
2611         }
2612
2613         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2614
2615         if (device_should_wake)
2616                 pci_enable_wake(tp->pdev, state, true);
2617
2618         /* Finally, set the new power state. */
2619         pci_set_power_state(tp->pdev, state);
2620
2621         return 0;
2622 }
2623
2624 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2625 {
2626         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2627         case MII_TG3_AUX_STAT_10HALF:
2628                 *speed = SPEED_10;
2629                 *duplex = DUPLEX_HALF;
2630                 break;
2631
2632         case MII_TG3_AUX_STAT_10FULL:
2633                 *speed = SPEED_10;
2634                 *duplex = DUPLEX_FULL;
2635                 break;
2636
2637         case MII_TG3_AUX_STAT_100HALF:
2638                 *speed = SPEED_100;
2639                 *duplex = DUPLEX_HALF;
2640                 break;
2641
2642         case MII_TG3_AUX_STAT_100FULL:
2643                 *speed = SPEED_100;
2644                 *duplex = DUPLEX_FULL;
2645                 break;
2646
2647         case MII_TG3_AUX_STAT_1000HALF:
2648                 *speed = SPEED_1000;
2649                 *duplex = DUPLEX_HALF;
2650                 break;
2651
2652         case MII_TG3_AUX_STAT_1000FULL:
2653                 *speed = SPEED_1000;
2654                 *duplex = DUPLEX_FULL;
2655                 break;
2656
2657         default:
2658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2659                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2660                                  SPEED_10;
2661                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2662                                   DUPLEX_HALF;
2663                         break;
2664                 }
2665                 *speed = SPEED_INVALID;
2666                 *duplex = DUPLEX_INVALID;
2667                 break;
2668         }
2669 }
2670
2671 static void tg3_phy_copper_begin(struct tg3 *tp)
2672 {
2673         u32 new_adv;
2674         int i;
2675
2676         if (tp->link_config.phy_is_low_power) {
2677                 /* Entering low power mode.  Disable gigabit and
2678                  * 100baseT advertisements.
2679                  */
2680                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2681
2682                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2683                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2684                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2685                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2686
2687                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2688         } else if (tp->link_config.speed == SPEED_INVALID) {
2689                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2690                         tp->link_config.advertising &=
2691                                 ~(ADVERTISED_1000baseT_Half |
2692                                   ADVERTISED_1000baseT_Full);
2693
2694                 new_adv = ADVERTISE_CSMA;
2695                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2696                         new_adv |= ADVERTISE_10HALF;
2697                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2698                         new_adv |= ADVERTISE_10FULL;
2699                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2700                         new_adv |= ADVERTISE_100HALF;
2701                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2702                         new_adv |= ADVERTISE_100FULL;
2703
2704                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2705
2706                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2707
2708                 if (tp->link_config.advertising &
2709                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2710                         new_adv = 0;
2711                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2712                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2713                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2714                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2715                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2716                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2717                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2718                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2719                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2720                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2721                 } else {
2722                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2723                 }
2724         } else {
2725                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2726                 new_adv |= ADVERTISE_CSMA;
2727
2728                 /* Asking for a specific link mode. */
2729                 if (tp->link_config.speed == SPEED_1000) {
2730                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2731
2732                         if (tp->link_config.duplex == DUPLEX_FULL)
2733                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2734                         else
2735                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2736                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2737                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2738                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2739                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2740                 } else {
2741                         if (tp->link_config.speed == SPEED_100) {
2742                                 if (tp->link_config.duplex == DUPLEX_FULL)
2743                                         new_adv |= ADVERTISE_100FULL;
2744                                 else
2745                                         new_adv |= ADVERTISE_100HALF;
2746                         } else {
2747                                 if (tp->link_config.duplex == DUPLEX_FULL)
2748                                         new_adv |= ADVERTISE_10FULL;
2749                                 else
2750                                         new_adv |= ADVERTISE_10HALF;
2751                         }
2752                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2753
2754                         new_adv = 0;
2755                 }
2756
2757                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2758         }
2759
2760         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2761             tp->link_config.speed != SPEED_INVALID) {
2762                 u32 bmcr, orig_bmcr;
2763
2764                 tp->link_config.active_speed = tp->link_config.speed;
2765                 tp->link_config.active_duplex = tp->link_config.duplex;
2766
2767                 bmcr = 0;
2768                 switch (tp->link_config.speed) {
2769                 default:
2770                 case SPEED_10:
2771                         break;
2772
2773                 case SPEED_100:
2774                         bmcr |= BMCR_SPEED100;
2775                         break;
2776
2777                 case SPEED_1000:
2778                         bmcr |= TG3_BMCR_SPEED1000;
2779                         break;
2780                 }
2781
2782                 if (tp->link_config.duplex == DUPLEX_FULL)
2783                         bmcr |= BMCR_FULLDPLX;
2784
2785                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2786                     (bmcr != orig_bmcr)) {
2787                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2788                         for (i = 0; i < 1500; i++) {
2789                                 u32 tmp;
2790
2791                                 udelay(10);
2792                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2793                                     tg3_readphy(tp, MII_BMSR, &tmp))
2794                                         continue;
2795                                 if (!(tmp & BMSR_LSTATUS)) {
2796                                         udelay(40);
2797                                         break;
2798                                 }
2799                         }
2800                         tg3_writephy(tp, MII_BMCR, bmcr);
2801                         udelay(40);
2802                 }
2803         } else {
2804                 tg3_writephy(tp, MII_BMCR,
2805                              BMCR_ANENABLE | BMCR_ANRESTART);
2806         }
2807 }
2808
2809 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2810 {
2811         int err;
2812
2813         /* Turn off tap power management. */
2814         /* Set Extended packet length bit */
2815         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2816
2817         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2818         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2819
2820         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2821         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2822
2823         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2824         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2825
2826         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2827         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2828
2829         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2830         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2831
2832         udelay(40);
2833
2834         return err;
2835 }
2836
2837 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2838 {
2839         u32 adv_reg, all_mask = 0;
2840
2841         if (mask & ADVERTISED_10baseT_Half)
2842                 all_mask |= ADVERTISE_10HALF;
2843         if (mask & ADVERTISED_10baseT_Full)
2844                 all_mask |= ADVERTISE_10FULL;
2845         if (mask & ADVERTISED_100baseT_Half)
2846                 all_mask |= ADVERTISE_100HALF;
2847         if (mask & ADVERTISED_100baseT_Full)
2848                 all_mask |= ADVERTISE_100FULL;
2849
2850         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2851                 return 0;
2852
2853         if ((adv_reg & all_mask) != all_mask)
2854                 return 0;
2855         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2856                 u32 tg3_ctrl;
2857
2858                 all_mask = 0;
2859                 if (mask & ADVERTISED_1000baseT_Half)
2860                         all_mask |= ADVERTISE_1000HALF;
2861                 if (mask & ADVERTISED_1000baseT_Full)
2862                         all_mask |= ADVERTISE_1000FULL;
2863
2864                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2865                         return 0;
2866
2867                 if ((tg3_ctrl & all_mask) != all_mask)
2868                         return 0;
2869         }
2870         return 1;
2871 }
2872
2873 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2874 {
2875         u32 curadv, reqadv;
2876
2877         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2878                 return 1;
2879
2880         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2881         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2882
2883         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2884                 if (curadv != reqadv)
2885                         return 0;
2886
2887                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2888                         tg3_readphy(tp, MII_LPA, rmtadv);
2889         } else {
2890                 /* Reprogram the advertisement register, even if it
2891                  * does not affect the current link.  If the link
2892                  * gets renegotiated in the future, we can save an
2893                  * additional renegotiation cycle by advertising
2894                  * it correctly in the first place.
2895                  */
2896                 if (curadv != reqadv) {
2897                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2898                                      ADVERTISE_PAUSE_ASYM);
2899                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2900                 }
2901         }
2902
2903         return 1;
2904 }
2905
2906 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2907 {
2908         int current_link_up;
2909         u32 bmsr, dummy;
2910         u32 lcl_adv, rmt_adv;
2911         u16 current_speed;
2912         u8 current_duplex;
2913         int i, err;
2914
2915         tw32(MAC_EVENT, 0);
2916
2917         tw32_f(MAC_STATUS,
2918              (MAC_STATUS_SYNC_CHANGED |
2919               MAC_STATUS_CFG_CHANGED |
2920               MAC_STATUS_MI_COMPLETION |
2921               MAC_STATUS_LNKSTATE_CHANGED));
2922         udelay(40);
2923
2924         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2925                 tw32_f(MAC_MI_MODE,
2926                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2927                 udelay(80);
2928         }
2929
2930         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2931
2932         /* Some third-party PHYs need to be reset on link going
2933          * down.
2934          */
2935         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2936              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2937              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2938             netif_carrier_ok(tp->dev)) {
2939                 tg3_readphy(tp, MII_BMSR, &bmsr);
2940                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2941                     !(bmsr & BMSR_LSTATUS))
2942                         force_reset = 1;
2943         }
2944         if (force_reset)
2945                 tg3_phy_reset(tp);
2946
2947         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2948                 tg3_readphy(tp, MII_BMSR, &bmsr);
2949                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2950                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2951                         bmsr = 0;
2952
2953                 if (!(bmsr & BMSR_LSTATUS)) {
2954                         err = tg3_init_5401phy_dsp(tp);
2955                         if (err)
2956                                 return err;
2957
2958                         tg3_readphy(tp, MII_BMSR, &bmsr);
2959                         for (i = 0; i < 1000; i++) {
2960                                 udelay(10);
2961                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2962                                     (bmsr & BMSR_LSTATUS)) {
2963                                         udelay(40);
2964                                         break;
2965                                 }
2966                         }
2967
2968                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2969                             !(bmsr & BMSR_LSTATUS) &&
2970                             tp->link_config.active_speed == SPEED_1000) {
2971                                 err = tg3_phy_reset(tp);
2972                                 if (!err)
2973                                         err = tg3_init_5401phy_dsp(tp);
2974                                 if (err)
2975                                         return err;
2976                         }
2977                 }
2978         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2979                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2980                 /* 5701 {A0,B0} CRC bug workaround */
2981                 tg3_writephy(tp, 0x15, 0x0a75);
2982                 tg3_writephy(tp, 0x1c, 0x8c68);
2983                 tg3_writephy(tp, 0x1c, 0x8d68);
2984                 tg3_writephy(tp, 0x1c, 0x8c68);
2985         }
2986
2987         /* Clear pending interrupts... */
2988         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2989         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2990
2991         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2992                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2993         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2994                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2995
2996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2998                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2999                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3000                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3001                 else
3002                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3003         }
3004
3005         current_link_up = 0;
3006         current_speed = SPEED_INVALID;
3007         current_duplex = DUPLEX_INVALID;
3008
3009         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3010                 u32 val;
3011
3012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3013                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3014                 if (!(val & (1 << 10))) {
3015                         val |= (1 << 10);
3016                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3017                         goto relink;
3018                 }
3019         }
3020
3021         bmsr = 0;
3022         for (i = 0; i < 100; i++) {
3023                 tg3_readphy(tp, MII_BMSR, &bmsr);
3024                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3025                     (bmsr & BMSR_LSTATUS))
3026                         break;
3027                 udelay(40);
3028         }
3029
3030         if (bmsr & BMSR_LSTATUS) {
3031                 u32 aux_stat, bmcr;
3032
3033                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3034                 for (i = 0; i < 2000; i++) {
3035                         udelay(10);
3036                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3037                             aux_stat)
3038                                 break;
3039                 }
3040
3041                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3042                                              &current_speed,
3043                                              &current_duplex);
3044
3045                 bmcr = 0;
3046                 for (i = 0; i < 200; i++) {
3047                         tg3_readphy(tp, MII_BMCR, &bmcr);
3048                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3049                                 continue;
3050                         if (bmcr && bmcr != 0x7fff)
3051                                 break;
3052                         udelay(10);
3053                 }
3054
3055                 lcl_adv = 0;
3056                 rmt_adv = 0;
3057
3058                 tp->link_config.active_speed = current_speed;
3059                 tp->link_config.active_duplex = current_duplex;
3060
3061                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3062                         if ((bmcr & BMCR_ANENABLE) &&
3063                             tg3_copper_is_advertising_all(tp,
3064                                                 tp->link_config.advertising)) {
3065                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3066                                                                   &rmt_adv))
3067                                         current_link_up = 1;
3068                         }
3069                 } else {
3070                         if (!(bmcr & BMCR_ANENABLE) &&
3071                             tp->link_config.speed == current_speed &&
3072                             tp->link_config.duplex == current_duplex &&
3073                             tp->link_config.flowctrl ==
3074                             tp->link_config.active_flowctrl) {
3075                                 current_link_up = 1;
3076                         }
3077                 }
3078
3079                 if (current_link_up == 1 &&
3080                     tp->link_config.active_duplex == DUPLEX_FULL)
3081                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3082         }
3083
3084 relink:
3085         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3086                 u32 tmp;
3087
3088                 tg3_phy_copper_begin(tp);
3089
3090                 tg3_readphy(tp, MII_BMSR, &tmp);
3091                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3092                     (tmp & BMSR_LSTATUS))
3093                         current_link_up = 1;
3094         }
3095
3096         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3097         if (current_link_up == 1) {
3098                 if (tp->link_config.active_speed == SPEED_100 ||
3099                     tp->link_config.active_speed == SPEED_10)
3100                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3101                 else
3102                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3103         } else
3104                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3105
3106         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3107         if (tp->link_config.active_duplex == DUPLEX_HALF)
3108                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3109
3110         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3111                 if (current_link_up == 1 &&
3112                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3113                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3114                 else
3115                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3116         }
3117
3118         /* ??? Without this setting Netgear GA302T PHY does not
3119          * ??? send/receive packets...
3120          */
3121         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3122             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3123                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3124                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3125                 udelay(80);
3126         }
3127
3128         tw32_f(MAC_MODE, tp->mac_mode);
3129         udelay(40);
3130
3131         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3132                 /* Polled via timer. */
3133                 tw32_f(MAC_EVENT, 0);
3134         } else {
3135                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3136         }
3137         udelay(40);
3138
3139         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3140             current_link_up == 1 &&
3141             tp->link_config.active_speed == SPEED_1000 &&
3142             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3143              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3144                 udelay(120);
3145                 tw32_f(MAC_STATUS,
3146                      (MAC_STATUS_SYNC_CHANGED |
3147                       MAC_STATUS_CFG_CHANGED));
3148                 udelay(40);
3149                 tg3_write_mem(tp,
3150                               NIC_SRAM_FIRMWARE_MBOX,
3151                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3152         }
3153
3154         /* Prevent send BD corruption. */
3155         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3156                 u16 oldlnkctl, newlnkctl;
3157
3158                 pci_read_config_word(tp->pdev,
3159                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3160                                      &oldlnkctl);
3161                 if (tp->link_config.active_speed == SPEED_100 ||
3162                     tp->link_config.active_speed == SPEED_10)
3163                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3164                 else
3165                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3166                 if (newlnkctl != oldlnkctl)
3167                         pci_write_config_word(tp->pdev,
3168                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3169                                               newlnkctl);
3170         }
3171
3172         if (current_link_up != netif_carrier_ok(tp->dev)) {
3173                 if (current_link_up)
3174                         netif_carrier_on(tp->dev);
3175                 else
3176                         netif_carrier_off(tp->dev);
3177                 tg3_link_report(tp);
3178         }
3179
3180         return 0;
3181 }
3182
3183 struct tg3_fiber_aneginfo {
3184         int state;
3185 #define ANEG_STATE_UNKNOWN              0
3186 #define ANEG_STATE_AN_ENABLE            1
3187 #define ANEG_STATE_RESTART_INIT         2
3188 #define ANEG_STATE_RESTART              3
3189 #define ANEG_STATE_DISABLE_LINK_OK      4
3190 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3191 #define ANEG_STATE_ABILITY_DETECT       6
3192 #define ANEG_STATE_ACK_DETECT_INIT      7
3193 #define ANEG_STATE_ACK_DETECT           8
3194 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3195 #define ANEG_STATE_COMPLETE_ACK         10
3196 #define ANEG_STATE_IDLE_DETECT_INIT     11
3197 #define ANEG_STATE_IDLE_DETECT          12
3198 #define ANEG_STATE_LINK_OK              13
3199 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3200 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3201
3202         u32 flags;
3203 #define MR_AN_ENABLE            0x00000001
3204 #define MR_RESTART_AN           0x00000002
3205 #define MR_AN_COMPLETE          0x00000004
3206 #define MR_PAGE_RX              0x00000008
3207 #define MR_NP_LOADED            0x00000010
3208 #define MR_TOGGLE_TX            0x00000020
3209 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3210 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3211 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3212 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3213 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3214 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3215 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3216 #define MR_TOGGLE_RX            0x00002000
3217 #define MR_NP_RX                0x00004000
3218
3219 #define MR_LINK_OK              0x80000000
3220
3221         unsigned long link_time, cur_time;
3222
3223         u32 ability_match_cfg;
3224         int ability_match_count;
3225
3226         char ability_match, idle_match, ack_match;
3227
3228         u32 txconfig, rxconfig;
3229 #define ANEG_CFG_NP             0x00000080
3230 #define ANEG_CFG_ACK            0x00000040
3231 #define ANEG_CFG_RF2            0x00000020
3232 #define ANEG_CFG_RF1            0x00000010
3233 #define ANEG_CFG_PS2            0x00000001
3234 #define ANEG_CFG_PS1            0x00008000
3235 #define ANEG_CFG_HD             0x00004000
3236 #define ANEG_CFG_FD             0x00002000
3237 #define ANEG_CFG_INVAL          0x00001f06
3238
3239 };
3240 #define ANEG_OK         0
3241 #define ANEG_DONE       1
3242 #define ANEG_TIMER_ENAB 2
3243 #define ANEG_FAILED     -1
3244
3245 #define ANEG_STATE_SETTLE_TIME  10000
3246
3247 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3248                                    struct tg3_fiber_aneginfo *ap)
3249 {
3250         u16 flowctrl;
3251         unsigned long delta;
3252         u32 rx_cfg_reg;
3253         int ret;
3254
3255         if (ap->state == ANEG_STATE_UNKNOWN) {
3256                 ap->rxconfig = 0;
3257                 ap->link_time = 0;
3258                 ap->cur_time = 0;
3259                 ap->ability_match_cfg = 0;
3260                 ap->ability_match_count = 0;
3261                 ap->ability_match = 0;
3262                 ap->idle_match = 0;
3263                 ap->ack_match = 0;
3264         }
3265         ap->cur_time++;
3266
3267         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3268                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3269
3270                 if (rx_cfg_reg != ap->ability_match_cfg) {
3271                         ap->ability_match_cfg = rx_cfg_reg;
3272                         ap->ability_match = 0;
3273                         ap->ability_match_count = 0;
3274                 } else {
3275                         if (++ap->ability_match_count > 1) {
3276                                 ap->ability_match = 1;
3277                                 ap->ability_match_cfg = rx_cfg_reg;
3278                         }
3279                 }
3280                 if (rx_cfg_reg & ANEG_CFG_ACK)
3281                         ap->ack_match = 1;
3282                 else
3283                         ap->ack_match = 0;
3284
3285                 ap->idle_match = 0;
3286         } else {
3287                 ap->idle_match = 1;
3288                 ap->ability_match_cfg = 0;
3289                 ap->ability_match_count = 0;
3290                 ap->ability_match = 0;
3291                 ap->ack_match = 0;
3292
3293                 rx_cfg_reg = 0;
3294         }
3295
3296         ap->rxconfig = rx_cfg_reg;
3297         ret = ANEG_OK;
3298
3299         switch(ap->state) {
3300         case ANEG_STATE_UNKNOWN:
3301                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3302                         ap->state = ANEG_STATE_AN_ENABLE;
3303
3304                 /* fallthru */
3305         case ANEG_STATE_AN_ENABLE:
3306                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3307                 if (ap->flags & MR_AN_ENABLE) {
3308                         ap->link_time = 0;
3309                         ap->cur_time = 0;
3310                         ap->ability_match_cfg = 0;
3311                         ap->ability_match_count = 0;
3312                         ap->ability_match = 0;
3313                         ap->idle_match = 0;
3314                         ap->ack_match = 0;
3315
3316                         ap->state = ANEG_STATE_RESTART_INIT;
3317                 } else {
3318                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3319                 }
3320                 break;
3321
3322         case ANEG_STATE_RESTART_INIT:
3323                 ap->link_time = ap->cur_time;
3324                 ap->flags &= ~(MR_NP_LOADED);
3325                 ap->txconfig = 0;
3326                 tw32(MAC_TX_AUTO_NEG, 0);
3327                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3328                 tw32_f(MAC_MODE, tp->mac_mode);
3329                 udelay(40);
3330
3331                 ret = ANEG_TIMER_ENAB;
3332                 ap->state = ANEG_STATE_RESTART;
3333
3334                 /* fallthru */
3335         case ANEG_STATE_RESTART:
3336                 delta = ap->cur_time - ap->link_time;
3337                 if (delta > ANEG_STATE_SETTLE_TIME) {
3338                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3339                 } else {
3340                         ret = ANEG_TIMER_ENAB;
3341                 }
3342                 break;
3343
3344         case ANEG_STATE_DISABLE_LINK_OK:
3345                 ret = ANEG_DONE;
3346                 break;
3347
3348         case ANEG_STATE_ABILITY_DETECT_INIT:
3349                 ap->flags &= ~(MR_TOGGLE_TX);
3350                 ap->txconfig = ANEG_CFG_FD;
3351                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3352                 if (flowctrl & ADVERTISE_1000XPAUSE)
3353                         ap->txconfig |= ANEG_CFG_PS1;
3354                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3355                         ap->txconfig |= ANEG_CFG_PS2;
3356                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3357                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3358                 tw32_f(MAC_MODE, tp->mac_mode);
3359                 udelay(40);
3360
3361                 ap->state = ANEG_STATE_ABILITY_DETECT;
3362                 break;
3363
3364         case ANEG_STATE_ABILITY_DETECT:
3365                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3366                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3367                 }
3368                 break;
3369
3370         case ANEG_STATE_ACK_DETECT_INIT:
3371                 ap->txconfig |= ANEG_CFG_ACK;
3372                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3373                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3374                 tw32_f(MAC_MODE, tp->mac_mode);
3375                 udelay(40);
3376
3377                 ap->state = ANEG_STATE_ACK_DETECT;
3378
3379                 /* fallthru */
3380         case ANEG_STATE_ACK_DETECT:
3381                 if (ap->ack_match != 0) {
3382                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3383                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3384                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3385                         } else {
3386                                 ap->state = ANEG_STATE_AN_ENABLE;
3387                         }
3388                 } else if (ap->ability_match != 0 &&
3389                            ap->rxconfig == 0) {
3390                         ap->state = ANEG_STATE_AN_ENABLE;
3391                 }
3392                 break;
3393
3394         case ANEG_STATE_COMPLETE_ACK_INIT:
3395                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3396                         ret = ANEG_FAILED;
3397                         break;
3398                 }
3399                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3400                                MR_LP_ADV_HALF_DUPLEX |
3401                                MR_LP_ADV_SYM_PAUSE |
3402                                MR_LP_ADV_ASYM_PAUSE |
3403                                MR_LP_ADV_REMOTE_FAULT1 |
3404                                MR_LP_ADV_REMOTE_FAULT2 |
3405                                MR_LP_ADV_NEXT_PAGE |
3406                                MR_TOGGLE_RX |
3407                                MR_NP_RX);
3408                 if (ap->rxconfig & ANEG_CFG_FD)
3409                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3410                 if (ap->rxconfig & ANEG_CFG_HD)
3411                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3412                 if (ap->rxconfig & ANEG_CFG_PS1)
3413                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3414                 if (ap->rxconfig & ANEG_CFG_PS2)
3415                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3416                 if (ap->rxconfig & ANEG_CFG_RF1)
3417                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3418                 if (ap->rxconfig & ANEG_CFG_RF2)
3419                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3420                 if (ap->rxconfig & ANEG_CFG_NP)
3421                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3422
3423                 ap->link_time = ap->cur_time;
3424
3425                 ap->flags ^= (MR_TOGGLE_TX);
3426                 if (ap->rxconfig & 0x0008)
3427                         ap->flags |= MR_TOGGLE_RX;
3428                 if (ap->rxconfig & ANEG_CFG_NP)
3429                         ap->flags |= MR_NP_RX;
3430                 ap->flags |= MR_PAGE_RX;
3431
3432                 ap->state = ANEG_STATE_COMPLETE_ACK;
3433                 ret = ANEG_TIMER_ENAB;
3434                 break;
3435
3436         case ANEG_STATE_COMPLETE_ACK:
3437                 if (ap->ability_match != 0 &&
3438                     ap->rxconfig == 0) {
3439                         ap->state = ANEG_STATE_AN_ENABLE;
3440                         break;
3441                 }
3442                 delta = ap->cur_time - ap->link_time;
3443                 if (delta > ANEG_STATE_SETTLE_TIME) {
3444                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3445                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3446                         } else {
3447                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3448                                     !(ap->flags & MR_NP_RX)) {
3449                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3450                                 } else {
3451                                         ret = ANEG_FAILED;
3452                                 }
3453                         }
3454                 }
3455                 break;
3456
3457         case ANEG_STATE_IDLE_DETECT_INIT:
3458                 ap->link_time = ap->cur_time;
3459                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3460                 tw32_f(MAC_MODE, tp->mac_mode);
3461                 udelay(40);
3462
3463                 ap->state = ANEG_STATE_IDLE_DETECT;
3464                 ret = ANEG_TIMER_ENAB;
3465                 break;
3466
3467         case ANEG_STATE_IDLE_DETECT:
3468                 if (ap->ability_match != 0 &&
3469                     ap->rxconfig == 0) {
3470                         ap->state = ANEG_STATE_AN_ENABLE;
3471                         break;
3472                 }
3473                 delta = ap->cur_time - ap->link_time;
3474                 if (delta > ANEG_STATE_SETTLE_TIME) {
3475                         /* XXX another gem from the Broadcom driver :( */
3476                         ap->state = ANEG_STATE_LINK_OK;
3477                 }
3478                 break;
3479
3480         case ANEG_STATE_LINK_OK:
3481                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3482                 ret = ANEG_DONE;
3483                 break;
3484
3485         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3486                 /* ??? unimplemented */
3487                 break;
3488
3489         case ANEG_STATE_NEXT_PAGE_WAIT:
3490                 /* ??? unimplemented */
3491                 break;
3492
3493         default:
3494                 ret = ANEG_FAILED;
3495                 break;
3496         }
3497
3498         return ret;
3499 }
3500
3501 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3502 {
3503         int res = 0;
3504         struct tg3_fiber_aneginfo aninfo;
3505         int status = ANEG_FAILED;
3506         unsigned int tick;
3507         u32 tmp;
3508
3509         tw32_f(MAC_TX_AUTO_NEG, 0);
3510
3511         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3512         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3513         udelay(40);
3514
3515         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3516         udelay(40);
3517
3518         memset(&aninfo, 0, sizeof(aninfo));
3519         aninfo.flags |= MR_AN_ENABLE;
3520         aninfo.state = ANEG_STATE_UNKNOWN;
3521         aninfo.cur_time = 0;
3522         tick = 0;
3523         while (++tick < 195000) {
3524                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3525                 if (status == ANEG_DONE || status == ANEG_FAILED)
3526                         break;
3527
3528                 udelay(1);
3529         }
3530
3531         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3532         tw32_f(MAC_MODE, tp->mac_mode);
3533         udelay(40);
3534
3535         *txflags = aninfo.txconfig;
3536         *rxflags = aninfo.flags;
3537
3538         if (status == ANEG_DONE &&
3539             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3540                              MR_LP_ADV_FULL_DUPLEX)))
3541                 res = 1;
3542
3543         return res;
3544 }
3545
3546 static void tg3_init_bcm8002(struct tg3 *tp)
3547 {
3548         u32 mac_status = tr32(MAC_STATUS);
3549         int i;
3550
3551         /* Reset when initting first time or we have a link. */
3552         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3553             !(mac_status & MAC_STATUS_PCS_SYNCED))
3554                 return;
3555
3556         /* Set PLL lock range. */
3557         tg3_writephy(tp, 0x16, 0x8007);
3558
3559         /* SW reset */
3560         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3561
3562         /* Wait for reset to complete. */
3563         /* XXX schedule_timeout() ... */
3564         for (i = 0; i < 500; i++)
3565                 udelay(10);
3566
3567         /* Config mode; select PMA/Ch 1 regs. */
3568         tg3_writephy(tp, 0x10, 0x8411);
3569
3570         /* Enable auto-lock and comdet, select txclk for tx. */
3571         tg3_writephy(tp, 0x11, 0x0a10);
3572
3573         tg3_writephy(tp, 0x18, 0x00a0);
3574         tg3_writephy(tp, 0x16, 0x41ff);
3575
3576         /* Assert and deassert POR. */
3577         tg3_writephy(tp, 0x13, 0x0400);
3578         udelay(40);
3579         tg3_writephy(tp, 0x13, 0x0000);
3580
3581         tg3_writephy(tp, 0x11, 0x0a50);
3582         udelay(40);
3583         tg3_writephy(tp, 0x11, 0x0a10);
3584
3585         /* Wait for signal to stabilize */
3586         /* XXX schedule_timeout() ... */
3587         for (i = 0; i < 15000; i++)
3588                 udelay(10);
3589
3590         /* Deselect the channel register so we can read the PHYID
3591          * later.
3592          */
3593         tg3_writephy(tp, 0x10, 0x8011);
3594 }
3595
3596 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3597 {
3598         u16 flowctrl;
3599         u32 sg_dig_ctrl, sg_dig_status;
3600         u32 serdes_cfg, expected_sg_dig_ctrl;
3601         int workaround, port_a;
3602         int current_link_up;
3603
3604         serdes_cfg = 0;
3605         expected_sg_dig_ctrl = 0;
3606         workaround = 0;
3607         port_a = 1;
3608         current_link_up = 0;
3609
3610         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3611             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3612                 workaround = 1;
3613                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3614                         port_a = 0;
3615
3616                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3617                 /* preserve bits 20-23 for voltage regulator */
3618                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3619         }
3620
3621         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3622
3623         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3624                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3625                         if (workaround) {
3626                                 u32 val = serdes_cfg;
3627
3628                                 if (port_a)
3629                                         val |= 0xc010000;
3630                                 else
3631                                         val |= 0x4010000;
3632                                 tw32_f(MAC_SERDES_CFG, val);
3633                         }
3634
3635                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3636                 }
3637                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3638                         tg3_setup_flow_control(tp, 0, 0);
3639                         current_link_up = 1;
3640                 }
3641                 goto out;
3642         }
3643
3644         /* Want auto-negotiation.  */
3645         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3646
3647         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3648         if (flowctrl & ADVERTISE_1000XPAUSE)
3649                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3650         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3651                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3652
3653         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3654                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3655                     tp->serdes_counter &&
3656                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3657                                     MAC_STATUS_RCVD_CFG)) ==
3658                      MAC_STATUS_PCS_SYNCED)) {
3659                         tp->serdes_counter--;
3660                         current_link_up = 1;
3661                         goto out;
3662                 }
3663 restart_autoneg:
3664                 if (workaround)
3665                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3666                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3667                 udelay(5);
3668                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3669
3670                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3671                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3672         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3673                                  MAC_STATUS_SIGNAL_DET)) {
3674                 sg_dig_status = tr32(SG_DIG_STATUS);
3675                 mac_status = tr32(MAC_STATUS);
3676
3677                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3678                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3679                         u32 local_adv = 0, remote_adv = 0;
3680
3681                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3682                                 local_adv |= ADVERTISE_1000XPAUSE;
3683                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3684                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3685
3686                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3687                                 remote_adv |= LPA_1000XPAUSE;
3688                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3689                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3690
3691                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3692                         current_link_up = 1;
3693                         tp->serdes_counter = 0;
3694                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3695                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3696                         if (tp->serdes_counter)
3697                                 tp->serdes_counter--;
3698                         else {
3699                                 if (workaround) {
3700                                         u32 val = serdes_cfg;
3701
3702                                         if (port_a)
3703                                                 val |= 0xc010000;
3704                                         else
3705                                                 val |= 0x4010000;
3706
3707                                         tw32_f(MAC_SERDES_CFG, val);
3708                                 }
3709
3710                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3711                                 udelay(40);
3712
3713                                 /* Link parallel detection - link is up */
3714                                 /* only if we have PCS_SYNC and not */
3715                                 /* receiving config code words */
3716                                 mac_status = tr32(MAC_STATUS);
3717                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3718                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3719                                         tg3_setup_flow_control(tp, 0, 0);
3720                                         current_link_up = 1;
3721                                         tp->tg3_flags2 |=
3722                                                 TG3_FLG2_PARALLEL_DETECT;
3723                                         tp->serdes_counter =
3724                                                 SERDES_PARALLEL_DET_TIMEOUT;
3725                                 } else
3726                                         goto restart_autoneg;
3727                         }
3728                 }
3729         } else {
3730                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3731                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3732         }
3733
3734 out:
3735         return current_link_up;
3736 }
3737
3738 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3739 {
3740         int current_link_up = 0;
3741
3742         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3743                 goto out;
3744
3745         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3746                 u32 txflags, rxflags;
3747                 int i;
3748
3749                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3750                         u32 local_adv = 0, remote_adv = 0;
3751
3752                         if (txflags & ANEG_CFG_PS1)
3753                                 local_adv |= ADVERTISE_1000XPAUSE;
3754                         if (txflags & ANEG_CFG_PS2)
3755                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3756
3757                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3758                                 remote_adv |= LPA_1000XPAUSE;
3759                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3760                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3761
3762                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3763
3764                         current_link_up = 1;
3765                 }
3766                 for (i = 0; i < 30; i++) {
3767                         udelay(20);
3768                         tw32_f(MAC_STATUS,
3769                                (MAC_STATUS_SYNC_CHANGED |
3770                                 MAC_STATUS_CFG_CHANGED));
3771                         udelay(40);
3772                         if ((tr32(MAC_STATUS) &
3773                              (MAC_STATUS_SYNC_CHANGED |
3774                               MAC_STATUS_CFG_CHANGED)) == 0)
3775                                 break;
3776                 }
3777
3778                 mac_status = tr32(MAC_STATUS);
3779                 if (current_link_up == 0 &&
3780                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3781                     !(mac_status & MAC_STATUS_RCVD_CFG))
3782                         current_link_up = 1;
3783         } else {
3784                 tg3_setup_flow_control(tp, 0, 0);
3785
3786                 /* Forcing 1000FD link up. */
3787                 current_link_up = 1;
3788
3789                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3790                 udelay(40);
3791
3792                 tw32_f(MAC_MODE, tp->mac_mode);
3793                 udelay(40);
3794         }
3795
3796 out:
3797         return current_link_up;
3798 }
3799
3800 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3801 {
3802         u32 orig_pause_cfg;
3803         u16 orig_active_speed;
3804         u8 orig_active_duplex;
3805         u32 mac_status;
3806         int current_link_up;
3807         int i;
3808
3809         orig_pause_cfg = tp->link_config.active_flowctrl;
3810         orig_active_speed = tp->link_config.active_speed;
3811         orig_active_duplex = tp->link_config.active_duplex;
3812
3813         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3814             netif_carrier_ok(tp->dev) &&
3815             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3816                 mac_status = tr32(MAC_STATUS);
3817                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3818                                MAC_STATUS_SIGNAL_DET |
3819                                MAC_STATUS_CFG_CHANGED |
3820                                MAC_STATUS_RCVD_CFG);
3821                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3822                                    MAC_STATUS_SIGNAL_DET)) {
3823                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3824                                             MAC_STATUS_CFG_CHANGED));
3825                         return 0;
3826                 }
3827         }
3828
3829         tw32_f(MAC_TX_AUTO_NEG, 0);
3830
3831         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3832         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3833         tw32_f(MAC_MODE, tp->mac_mode);
3834         udelay(40);
3835
3836         if (tp->phy_id == PHY_ID_BCM8002)
3837                 tg3_init_bcm8002(tp);
3838
3839         /* Enable link change event even when serdes polling.  */
3840         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3841         udelay(40);
3842
3843         current_link_up = 0;
3844         mac_status = tr32(MAC_STATUS);
3845
3846         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3847                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3848         else
3849                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3850
3851         tp->hw_status->status =
3852                 (SD_STATUS_UPDATED |
3853                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3854
3855         for (i = 0; i < 100; i++) {
3856                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3857                                     MAC_STATUS_CFG_CHANGED));
3858                 udelay(5);
3859                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3860                                          MAC_STATUS_CFG_CHANGED |
3861                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3862                         break;
3863         }
3864
3865         mac_status = tr32(MAC_STATUS);
3866         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3867                 current_link_up = 0;
3868                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3869                     tp->serdes_counter == 0) {
3870                         tw32_f(MAC_MODE, (tp->mac_mode |
3871                                           MAC_MODE_SEND_CONFIGS));
3872                         udelay(1);
3873                         tw32_f(MAC_MODE, tp->mac_mode);
3874                 }
3875         }
3876
3877         if (current_link_up == 1) {
3878                 tp->link_config.active_speed = SPEED_1000;
3879                 tp->link_config.active_duplex = DUPLEX_FULL;
3880                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3881                                     LED_CTRL_LNKLED_OVERRIDE |
3882                                     LED_CTRL_1000MBPS_ON));
3883         } else {
3884                 tp->link_config.active_speed = SPEED_INVALID;
3885                 tp->link_config.active_duplex = DUPLEX_INVALID;
3886                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3887                                     LED_CTRL_LNKLED_OVERRIDE |
3888                                     LED_CTRL_TRAFFIC_OVERRIDE));
3889         }
3890
3891         if (current_link_up != netif_carrier_ok(tp->dev)) {
3892                 if (current_link_up)
3893                         netif_carrier_on(tp->dev);
3894                 else
3895                         netif_carrier_off(tp->dev);
3896                 tg3_link_report(tp);
3897         } else {
3898                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3899                 if (orig_pause_cfg != now_pause_cfg ||
3900                     orig_active_speed != tp->link_config.active_speed ||
3901                     orig_active_duplex != tp->link_config.active_duplex)
3902                         tg3_link_report(tp);
3903         }
3904
3905         return 0;
3906 }
3907
3908 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3909 {
3910         int current_link_up, err = 0;
3911         u32 bmsr, bmcr;
3912         u16 current_speed;
3913         u8 current_duplex;
3914         u32 local_adv, remote_adv;
3915
3916         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3917         tw32_f(MAC_MODE, tp->mac_mode);
3918         udelay(40);
3919
3920         tw32(MAC_EVENT, 0);
3921
3922         tw32_f(MAC_STATUS,
3923              (MAC_STATUS_SYNC_CHANGED |
3924               MAC_STATUS_CFG_CHANGED |
3925               MAC_STATUS_MI_COMPLETION |
3926               MAC_STATUS_LNKSTATE_CHANGED));
3927         udelay(40);
3928
3929         if (force_reset)
3930                 tg3_phy_reset(tp);
3931
3932         current_link_up = 0;
3933         current_speed = SPEED_INVALID;
3934         current_duplex = DUPLEX_INVALID;
3935
3936         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3937         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3939                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3940                         bmsr |= BMSR_LSTATUS;
3941                 else
3942                         bmsr &= ~BMSR_LSTATUS;
3943         }
3944
3945         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3946
3947         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3948             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3949                 /* do nothing, just check for link up at the end */
3950         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3951                 u32 adv, new_adv;
3952
3953                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3954                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3955                                   ADVERTISE_1000XPAUSE |
3956                                   ADVERTISE_1000XPSE_ASYM |
3957                                   ADVERTISE_SLCT);
3958
3959                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3960
3961                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3962                         new_adv |= ADVERTISE_1000XHALF;
3963                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3964                         new_adv |= ADVERTISE_1000XFULL;
3965
3966                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3967                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3968                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3969                         tg3_writephy(tp, MII_BMCR, bmcr);
3970
3971                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3972                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3973                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3974
3975                         return err;
3976                 }
3977         } else {
3978                 u32 new_bmcr;
3979
3980                 bmcr &= ~BMCR_SPEED1000;
3981                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3982
3983                 if (tp->link_config.duplex == DUPLEX_FULL)
3984                         new_bmcr |= BMCR_FULLDPLX;
3985
3986                 if (new_bmcr != bmcr) {
3987                         /* BMCR_SPEED1000 is a reserved bit that needs
3988                          * to be set on write.
3989                          */
3990                         new_bmcr |= BMCR_SPEED1000;
3991
3992                         /* Force a linkdown */
3993                         if (netif_carrier_ok(tp->dev)) {
3994                                 u32 adv;
3995
3996                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3997                                 adv &= ~(ADVERTISE_1000XFULL |
3998                                          ADVERTISE_1000XHALF |
3999                                          ADVERTISE_SLCT);
4000                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4001                                 tg3_writephy(tp, MII_BMCR, bmcr |
4002                                                            BMCR_ANRESTART |
4003                                                            BMCR_ANENABLE);
4004                                 udelay(10);
4005                                 netif_carrier_off(tp->dev);
4006                         }
4007                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4008                         bmcr = new_bmcr;
4009                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4010                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4011                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4012                             ASIC_REV_5714) {
4013                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4014                                         bmsr |= BMSR_LSTATUS;
4015                                 else
4016                                         bmsr &= ~BMSR_LSTATUS;
4017                         }
4018                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4019                 }
4020         }
4021
4022         if (bmsr & BMSR_LSTATUS) {
4023                 current_speed = SPEED_1000;
4024                 current_link_up = 1;
4025                 if (bmcr & BMCR_FULLDPLX)
4026                         current_duplex = DUPLEX_FULL;
4027                 else
4028                         current_duplex = DUPLEX_HALF;
4029
4030                 local_adv = 0;
4031                 remote_adv = 0;
4032
4033                 if (bmcr & BMCR_ANENABLE) {
4034                         u32 common;
4035
4036                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4037                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4038                         common = local_adv & remote_adv;
4039                         if (common & (ADVERTISE_1000XHALF |
4040                                       ADVERTISE_1000XFULL)) {
4041                                 if (common & ADVERTISE_1000XFULL)
4042                                         current_duplex = DUPLEX_FULL;
4043                                 else
4044                                         current_duplex = DUPLEX_HALF;
4045                         }
4046                         else
4047                                 current_link_up = 0;
4048                 }
4049         }
4050
4051         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4052                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4053
4054         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4055         if (tp->link_config.active_duplex == DUPLEX_HALF)
4056                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4057
4058         tw32_f(MAC_MODE, tp->mac_mode);
4059         udelay(40);
4060
4061         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4062
4063         tp->link_config.active_speed = current_speed;
4064         tp->link_config.active_duplex = current_duplex;
4065
4066         if (current_link_up != netif_carrier_ok(tp->dev)) {
4067                 if (current_link_up)
4068                         netif_carrier_on(tp->dev);
4069                 else {
4070                         netif_carrier_off(tp->dev);
4071                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4072                 }
4073                 tg3_link_report(tp);
4074         }
4075         return err;
4076 }
4077
4078 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4079 {
4080         if (tp->serdes_counter) {
4081                 /* Give autoneg time to complete. */
4082                 tp->serdes_counter--;
4083                 return;
4084         }
4085         if (!netif_carrier_ok(tp->dev) &&
4086             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4087                 u32 bmcr;
4088
4089                 tg3_readphy(tp, MII_BMCR, &bmcr);
4090                 if (bmcr & BMCR_ANENABLE) {
4091                         u32 phy1, phy2;
4092
4093                         /* Select shadow register 0x1f */
4094                         tg3_writephy(tp, 0x1c, 0x7c00);
4095                         tg3_readphy(tp, 0x1c, &phy1);
4096
4097                         /* Select expansion interrupt status register */
4098                         tg3_writephy(tp, 0x17, 0x0f01);
4099                         tg3_readphy(tp, 0x15, &phy2);
4100                         tg3_readphy(tp, 0x15, &phy2);
4101
4102                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4103                                 /* We have signal detect and not receiving
4104                                  * config code words, link is up by parallel
4105                                  * detection.
4106                                  */
4107
4108                                 bmcr &= ~BMCR_ANENABLE;
4109                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4110                                 tg3_writephy(tp, MII_BMCR, bmcr);
4111                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4112                         }
4113                 }
4114         }
4115         else if (netif_carrier_ok(tp->dev) &&
4116                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4117                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4118                 u32 phy2;
4119
4120                 /* Select expansion interrupt status register */
4121                 tg3_writephy(tp, 0x17, 0x0f01);
4122                 tg3_readphy(tp, 0x15, &phy2);
4123                 if (phy2 & 0x20) {
4124                         u32 bmcr;
4125
4126                         /* Config code words received, turn on autoneg. */
4127                         tg3_readphy(tp, MII_BMCR, &bmcr);
4128                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4129
4130                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4131
4132                 }
4133         }
4134 }
4135
4136 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4137 {
4138         int err;
4139
4140         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4141                 err = tg3_setup_fiber_phy(tp, force_reset);
4142         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4143                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4144         } else {
4145                 err = tg3_setup_copper_phy(tp, force_reset);
4146         }
4147
4148         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4149                 u32 val, scale;
4150
4151                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4152                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4153                         scale = 65;
4154                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4155                         scale = 6;
4156                 else
4157                         scale = 12;
4158
4159                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4160                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4161                 tw32(GRC_MISC_CFG, val);
4162         }
4163
4164         if (tp->link_config.active_speed == SPEED_1000 &&
4165             tp->link_config.active_duplex == DUPLEX_HALF)
4166                 tw32(MAC_TX_LENGTHS,
4167                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4168                       (6 << TX_LENGTHS_IPG_SHIFT) |
4169                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4170         else
4171                 tw32(MAC_TX_LENGTHS,
4172                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4173                       (6 << TX_LENGTHS_IPG_SHIFT) |
4174                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4175
4176         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4177                 if (netif_carrier_ok(tp->dev)) {
4178                         tw32(HOSTCC_STAT_COAL_TICKS,
4179                              tp->coal.stats_block_coalesce_usecs);
4180                 } else {
4181                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4182                 }
4183         }
4184
4185         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4186                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4187                 if (!netif_carrier_ok(tp->dev))
4188                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4189                               tp->pwrmgmt_thresh;
4190                 else
4191                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4192                 tw32(PCIE_PWR_MGMT_THRESH, val);
4193         }
4194
4195         return err;
4196 }
4197
4198 /* This is called whenever we suspect that the system chipset is re-
4199  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4200  * is bogus tx completions. We try to recover by setting the
4201  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4202  * in the workqueue.
4203  */
4204 static void tg3_tx_recover(struct tg3 *tp)
4205 {
4206         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4207                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4208
4209         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4210                "mapped I/O cycles to the network device, attempting to "
4211                "recover. Please report the problem to the driver maintainer "
4212                "and include system chipset information.\n", tp->dev->name);
4213
4214         spin_lock(&tp->lock);
4215         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4216         spin_unlock(&tp->lock);
4217 }
4218
4219 static inline u32 tg3_tx_avail(struct tg3 *tp)
4220 {
4221         smp_mb();
4222         return (tp->tx_pending -
4223                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4224 }
4225
4226 /* Tigon3 never reports partial packet sends.  So we do not
4227  * need special logic to handle SKBs that have not had all
4228  * of their frags sent yet, like SunGEM does.
4229  */
4230 static void tg3_tx(struct tg3 *tp)
4231 {
4232         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4233         u32 sw_idx = tp->tx_cons;
4234
4235         while (sw_idx != hw_idx) {
4236                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4237                 struct sk_buff *skb = ri->skb;
4238                 int i, tx_bug = 0;
4239
4240                 if (unlikely(skb == NULL)) {
4241                         tg3_tx_recover(tp);
4242                         return;
4243                 }
4244
4245                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4246
4247                 ri->skb = NULL;
4248
4249                 sw_idx = NEXT_TX(sw_idx);
4250
4251                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4252                         ri = &tp->tx_buffers[sw_idx];
4253                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4254                                 tx_bug = 1;
4255                         sw_idx = NEXT_TX(sw_idx);
4256                 }
4257
4258                 dev_kfree_skb(skb);
4259
4260                 if (unlikely(tx_bug)) {
4261                         tg3_tx_recover(tp);
4262                         return;
4263                 }
4264         }
4265
4266         tp->tx_cons = sw_idx;
4267
4268         /* Need to make the tx_cons update visible to tg3_start_xmit()
4269          * before checking for netif_queue_stopped().  Without the
4270          * memory barrier, there is a small possibility that tg3_start_xmit()
4271          * will miss it and cause the queue to be stopped forever.
4272          */
4273         smp_mb();
4274
4275         if (unlikely(netif_queue_stopped(tp->dev) &&
4276                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4277                 netif_tx_lock(tp->dev);
4278                 if (netif_queue_stopped(tp->dev) &&
4279                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4280                         netif_wake_queue(tp->dev);
4281                 netif_tx_unlock(tp->dev);
4282         }
4283 }
4284
4285 /* Returns size of skb allocated or < 0 on error.
4286  *
4287  * We only need to fill in the address because the other members
4288  * of the RX descriptor are invariant, see tg3_init_rings.
4289  *
4290  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4291  * posting buffers we only dirty the first cache line of the RX
4292  * descriptor (containing the address).  Whereas for the RX status
4293  * buffers the cpu only reads the last cacheline of the RX descriptor
4294  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4295  */
4296 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4297                             int src_idx, u32 dest_idx_unmasked)
4298 {
4299         struct tg3_rx_buffer_desc *desc;
4300         struct ring_info *map, *src_map;
4301         struct sk_buff *skb;
4302         dma_addr_t mapping;
4303         int skb_size, dest_idx;
4304
4305         src_map = NULL;
4306         switch (opaque_key) {
4307         case RXD_OPAQUE_RING_STD:
4308                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4309                 desc = &tp->rx_std[dest_idx];
4310                 map = &tp->rx_std_buffers[dest_idx];
4311                 if (src_idx >= 0)
4312                         src_map = &tp->rx_std_buffers[src_idx];
4313                 skb_size = tp->rx_pkt_buf_sz;
4314                 break;
4315
4316         case RXD_OPAQUE_RING_JUMBO:
4317                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4318                 desc = &tp->rx_jumbo[dest_idx];
4319                 map = &tp->rx_jumbo_buffers[dest_idx];
4320                 if (src_idx >= 0)
4321                         src_map = &tp->rx_jumbo_buffers[src_idx];
4322                 skb_size = RX_JUMBO_PKT_BUF_SZ;
4323                 break;
4324
4325         default:
4326                 return -EINVAL;
4327         }
4328
4329         /* Do not overwrite any of the map or rp information
4330          * until we are sure we can commit to a new buffer.
4331          *
4332          * Callers depend upon this behavior and assume that
4333          * we leave everything unchanged if we fail.
4334          */
4335         skb = netdev_alloc_skb(tp->dev, skb_size);
4336         if (skb == NULL)
4337                 return -ENOMEM;
4338
4339         skb_reserve(skb, tp->rx_offset);
4340
4341         mapping = pci_map_single(tp->pdev, skb->data,
4342                                  skb_size - tp->rx_offset,
4343                                  PCI_DMA_FROMDEVICE);
4344
4345         map->skb = skb;
4346         pci_unmap_addr_set(map, mapping, mapping);
4347
4348         if (src_map != NULL)
4349                 src_map->skb = NULL;
4350
4351         desc->addr_hi = ((u64)mapping >> 32);
4352         desc->addr_lo = ((u64)mapping & 0xffffffff);
4353
4354         return skb_size;
4355 }
4356
4357 /* We only need to move over in the address because the other
4358  * members of the RX descriptor are invariant.  See notes above
4359  * tg3_alloc_rx_skb for full details.
4360  */
4361 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4362                            int src_idx, u32 dest_idx_unmasked)
4363 {
4364         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4365         struct ring_info *src_map, *dest_map;
4366         int dest_idx;
4367
4368         switch (opaque_key) {
4369         case RXD_OPAQUE_RING_STD:
4370                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4371                 dest_desc = &tp->rx_std[dest_idx];
4372                 dest_map = &tp->rx_std_buffers[dest_idx];
4373                 src_desc = &tp->rx_std[src_idx];
4374                 src_map = &tp->rx_std_buffers[src_idx];
4375                 break;
4376
4377         case RXD_OPAQUE_RING_JUMBO:
4378                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4379                 dest_desc = &tp->rx_jumbo[dest_idx];
4380                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4381                 src_desc = &tp->rx_jumbo[src_idx];
4382                 src_map = &tp->rx_jumbo_buffers[src_idx];
4383                 break;
4384
4385         default:
4386                 return;
4387         }
4388
4389         dest_map->skb = src_map->skb;
4390         pci_unmap_addr_set(dest_map, mapping,
4391                            pci_unmap_addr(src_map, mapping));
4392         dest_desc->addr_hi = src_desc->addr_hi;
4393         dest_desc->addr_lo = src_desc->addr_lo;
4394
4395         src_map->skb = NULL;
4396 }
4397
4398 #if TG3_VLAN_TAG_USED
4399 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4400 {
4401         return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4402 }
4403 #endif
4404
4405 /* The RX ring scheme is composed of multiple rings which post fresh
4406  * buffers to the chip, and one special ring the chip uses to report
4407  * status back to the host.
4408  *
4409  * The special ring reports the status of received packets to the
4410  * host.  The chip does not write into the original descriptor the
4411  * RX buffer was obtained from.  The chip simply takes the original
4412  * descriptor as provided by the host, updates the status and length
4413  * field, then writes this into the next status ring entry.
4414  *
4415  * Each ring the host uses to post buffers to the chip is described
4416  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4417  * it is first placed into the on-chip ram.  When the packet's length
4418  * is known, it walks down the TG3_BDINFO entries to select the ring.
4419  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4420  * which is within the range of the new packet's length is chosen.
4421  *
4422  * The "separate ring for rx status" scheme may sound queer, but it makes
4423  * sense from a cache coherency perspective.  If only the host writes
4424  * to the buffer post rings, and only the chip writes to the rx status
4425  * rings, then cache lines never move beyond shared-modified state.
4426  * If both the host and chip were to write into the same ring, cache line
4427  * eviction could occur since both entities want it in an exclusive state.
4428  */
4429 static int tg3_rx(struct tg3 *tp, int budget)
4430 {
4431         u32 work_mask, rx_std_posted = 0;
4432         u32 sw_idx = tp->rx_rcb_ptr;
4433         u16 hw_idx;
4434         int received;
4435
4436         hw_idx = tp->hw_status->idx[0].rx_producer;
4437         /*
4438          * We need to order the read of hw_idx and the read of
4439          * the opaque cookie.
4440          */
4441         rmb();
4442         work_mask = 0;
4443         received = 0;
4444         while (sw_idx != hw_idx && budget > 0) {
4445                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4446                 unsigned int len;
4447                 struct sk_buff *skb;
4448                 dma_addr_t dma_addr;
4449                 u32 opaque_key, desc_idx, *post_ptr;
4450
4451                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4452                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4453                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4454                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4455                                                   mapping);
4456                         skb = tp->rx_std_buffers[desc_idx].skb;
4457                         post_ptr = &tp->rx_std_ptr;
4458                         rx_std_posted++;
4459                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4460                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4461                                                   mapping);
4462                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4463                         post_ptr = &tp->rx_jumbo_ptr;
4464                 }
4465                 else {
4466                         goto next_pkt_nopost;
4467                 }
4468
4469                 work_mask |= opaque_key;
4470
4471                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4472                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4473                 drop_it:
4474                         tg3_recycle_rx(tp, opaque_key,
4475                                        desc_idx, *post_ptr);
4476                 drop_it_no_recycle:
4477                         /* Other statistics kept track of by card. */
4478                         tp->net_stats.rx_dropped++;
4479                         goto next_pkt;
4480                 }
4481
4482                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4483                       ETH_FCS_LEN;
4484
4485                 if (len > RX_COPY_THRESHOLD
4486                         && tp->rx_offset == NET_IP_ALIGN
4487                         /* rx_offset will likely not equal NET_IP_ALIGN
4488                          * if this is a 5701 card running in PCI-X mode
4489                          * [see tg3_get_invariants()]
4490                          */
4491                 ) {
4492                         int skb_size;
4493
4494                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4495                                                     desc_idx, *post_ptr);
4496                         if (skb_size < 0)
4497                                 goto drop_it;
4498
4499                         pci_unmap_single(tp->pdev, dma_addr,
4500                                          skb_size - tp->rx_offset,
4501                                          PCI_DMA_FROMDEVICE);
4502
4503                         skb_put(skb, len);
4504                 } else {
4505                         struct sk_buff *copy_skb;
4506
4507                         tg3_recycle_rx(tp, opaque_key,
4508                                        desc_idx, *post_ptr);
4509
4510                         copy_skb = netdev_alloc_skb(tp->dev,
4511                                                     len + TG3_RAW_IP_ALIGN);
4512                         if (copy_skb == NULL)
4513                                 goto drop_it_no_recycle;
4514
4515                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4516                         skb_put(copy_skb, len);
4517                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4518                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4519                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4520
4521                         /* We'll reuse the original ring buffer. */
4522                         skb = copy_skb;
4523                 }
4524
4525                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4526                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4527                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4528                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4529                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4530                 else
4531                         skb->ip_summed = CHECKSUM_NONE;
4532
4533                 skb->protocol = eth_type_trans(skb, tp->dev);
4534
4535                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4536                     skb->protocol != htons(ETH_P_8021Q)) {
4537                         dev_kfree_skb(skb);
4538                         goto next_pkt;
4539                 }
4540
4541 #if TG3_VLAN_TAG_USED
4542                 if (tp->vlgrp != NULL &&
4543                     desc->type_flags & RXD_FLAG_VLAN) {
4544                         tg3_vlan_rx(tp, skb,
4545                                     desc->err_vlan & RXD_VLAN_MASK);
4546                 } else
4547 #endif
4548                         napi_gro_receive(&tp->napi, skb);
4549
4550                 received++;
4551                 budget--;
4552
4553 next_pkt:
4554                 (*post_ptr)++;
4555
4556                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4557                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4558
4559                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4560                                      TG3_64BIT_REG_LOW, idx);
4561                         work_mask &= ~RXD_OPAQUE_RING_STD;
4562                         rx_std_posted = 0;
4563                 }
4564 next_pkt_nopost:
4565                 sw_idx++;
4566                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4567
4568                 /* Refresh hw_idx to see if there is new work */
4569                 if (sw_idx == hw_idx) {
4570                         hw_idx = tp->hw_status->idx[0].rx_producer;
4571                         rmb();
4572                 }
4573         }
4574
4575         /* ACK the status ring. */
4576         tp->rx_rcb_ptr = sw_idx;
4577         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4578
4579         /* Refill RX ring(s). */
4580         if (work_mask & RXD_OPAQUE_RING_STD) {
4581                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4582                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4583                              sw_idx);
4584         }
4585         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4586                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4587                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4588                              sw_idx);
4589         }
4590         mmiowb();
4591
4592         return received;
4593 }
4594
4595 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4596 {
4597         struct tg3_hw_status *sblk = tp->hw_status;
4598
4599         /* handle link change and other phy events */
4600         if (!(tp->tg3_flags &
4601               (TG3_FLAG_USE_LINKCHG_REG |
4602                TG3_FLAG_POLL_SERDES))) {
4603                 if (sblk->status & SD_STATUS_LINK_CHG) {
4604                         sblk->status = SD_STATUS_UPDATED |
4605                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4606                         spin_lock(&tp->lock);
4607                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4608                                 tw32_f(MAC_STATUS,
4609                                      (MAC_STATUS_SYNC_CHANGED |
4610                                       MAC_STATUS_CFG_CHANGED |
4611                                       MAC_STATUS_MI_COMPLETION |
4612                                       MAC_STATUS_LNKSTATE_CHANGED));
4613                                 udelay(40);
4614                         } else
4615                                 tg3_setup_phy(tp, 0);
4616                         spin_unlock(&tp->lock);
4617                 }
4618         }
4619
4620         /* run TX completion thread */
4621         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4622                 tg3_tx(tp);
4623                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4624                         return work_done;
4625         }
4626
4627         /* run RX thread, within the bounds set by NAPI.
4628          * All RX "locking" is done by ensuring outside
4629          * code synchronizes with tg3->napi.poll()
4630          */
4631         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4632                 work_done += tg3_rx(tp, budget - work_done);
4633
4634         return work_done;
4635 }
4636
4637 static int tg3_poll(struct napi_struct *napi, int budget)
4638 {
4639         struct tg3 *tp = container_of(napi, struct tg3, napi);
4640         int work_done = 0;
4641         struct tg3_hw_status *sblk = tp->hw_status;
4642
4643         while (1) {
4644                 work_done = tg3_poll_work(tp, work_done, budget);
4645
4646                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4647                         goto tx_recovery;
4648
4649                 if (unlikely(work_done >= budget))
4650                         break;
4651
4652                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4653                         /* tp->last_tag is used in tg3_restart_ints() below
4654                          * to tell the hw how much work has been processed,
4655                          * so we must read it before checking for more work.
4656                          */
4657                         tp->last_tag = sblk->status_tag;
4658                         tp->last_irq_tag = tp->last_tag;
4659                         rmb();
4660                 } else
4661                         sblk->status &= ~SD_STATUS_UPDATED;
4662
4663                 if (likely(!tg3_has_work(tp))) {
4664                         napi_complete(napi);
4665                         tg3_restart_ints(tp);
4666                         break;
4667                 }
4668         }
4669
4670         return work_done;
4671
4672 tx_recovery:
4673         /* work_done is guaranteed to be less than budget. */
4674         napi_complete(napi);
4675         schedule_work(&tp->reset_task);
4676         return work_done;
4677 }
4678
4679 static void tg3_irq_quiesce(struct tg3 *tp)
4680 {
4681         BUG_ON(tp->irq_sync);
4682
4683         tp->irq_sync = 1;
4684         smp_mb();
4685
4686         synchronize_irq(tp->pdev->irq);
4687 }
4688
4689 static inline int tg3_irq_sync(struct tg3 *tp)
4690 {
4691         return tp->irq_sync;
4692 }
4693
4694 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4695  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4696  * with as well.  Most of the time, this is not necessary except when
4697  * shutting down the device.
4698  */
4699 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4700 {
4701         spin_lock_bh(&tp->lock);
4702         if (irq_sync)
4703                 tg3_irq_quiesce(tp);
4704 }
4705
4706 static inline void tg3_full_unlock(struct tg3 *tp)
4707 {
4708         spin_unlock_bh(&tp->lock);
4709 }
4710
4711 /* One-shot MSI handler - Chip automatically disables interrupt
4712  * after sending MSI so driver doesn't have to do it.
4713  */
4714 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4715 {
4716         struct net_device *dev = dev_id;
4717         struct tg3 *tp = netdev_priv(dev);
4718
4719         prefetch(tp->hw_status);
4720         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4721
4722         if (likely(!tg3_irq_sync(tp)))
4723                 napi_schedule(&tp->napi);
4724
4725         return IRQ_HANDLED;
4726 }
4727
4728 /* MSI ISR - No need to check for interrupt sharing and no need to
4729  * flush status block and interrupt mailbox. PCI ordering rules
4730  * guarantee that MSI will arrive after the status block.
4731  */
4732 static irqreturn_t tg3_msi(int irq, void *dev_id)
4733 {
4734         struct net_device *dev = dev_id;
4735         struct tg3 *tp = netdev_priv(dev);
4736
4737         prefetch(tp->hw_status);
4738         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4739         /*
4740          * Writing any value to intr-mbox-0 clears PCI INTA# and
4741          * chip-internal interrupt pending events.
4742          * Writing non-zero to intr-mbox-0 additional tells the
4743          * NIC to stop sending us irqs, engaging "in-intr-handler"
4744          * event coalescing.
4745          */
4746         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4747         if (likely(!tg3_irq_sync(tp)))
4748                 napi_schedule(&tp->napi);
4749
4750         return IRQ_RETVAL(1);
4751 }
4752
4753 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4754 {
4755         struct net_device *dev = dev_id;
4756         struct tg3 *tp = netdev_priv(dev);
4757         struct tg3_hw_status *sblk = tp->hw_status;
4758         unsigned int handled = 1;
4759
4760         /* In INTx mode, it is possible for the interrupt to arrive at
4761          * the CPU before the status block posted prior to the interrupt.
4762          * Reading the PCI State register will confirm whether the
4763          * interrupt is ours and will flush the status block.
4764          */
4765         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4766                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4767                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4768                         handled = 0;
4769                         goto out;
4770                 }
4771         }
4772
4773         /*
4774          * Writing any value to intr-mbox-0 clears PCI INTA# and
4775          * chip-internal interrupt pending events.
4776          * Writing non-zero to intr-mbox-0 additional tells the
4777          * NIC to stop sending us irqs, engaging "in-intr-handler"
4778          * event coalescing.
4779          *
4780          * Flush the mailbox to de-assert the IRQ immediately to prevent
4781          * spurious interrupts.  The flush impacts performance but
4782          * excessive spurious interrupts can be worse in some cases.
4783          */
4784         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4785         if (tg3_irq_sync(tp))
4786                 goto out;
4787         sblk->status &= ~SD_STATUS_UPDATED;
4788         if (likely(tg3_has_work(tp))) {
4789                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4790                 napi_schedule(&tp->napi);
4791         } else {
4792                 /* No work, shared interrupt perhaps?  re-enable
4793                  * interrupts, and flush that PCI write
4794                  */
4795                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4796                                0x00000000);
4797         }
4798 out:
4799         return IRQ_RETVAL(handled);
4800 }
4801
4802 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4803 {
4804         struct net_device *dev = dev_id;
4805         struct tg3 *tp = netdev_priv(dev);
4806         struct tg3_hw_status *sblk = tp->hw_status;
4807         unsigned int handled = 1;
4808
4809         /* In INTx mode, it is possible for the interrupt to arrive at
4810          * the CPU before the status block posted prior to the interrupt.
4811          * Reading the PCI State register will confirm whether the
4812          * interrupt is ours and will flush the status block.
4813          */
4814         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4815                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4816                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4817                         handled = 0;
4818                         goto out;
4819                 }
4820         }
4821
4822         /*
4823          * writing any value to intr-mbox-0 clears PCI INTA# and
4824          * chip-internal interrupt pending events.
4825          * writing non-zero to intr-mbox-0 additional tells the
4826          * NIC to stop sending us irqs, engaging "in-intr-handler"
4827          * event coalescing.
4828          *
4829          * Flush the mailbox to de-assert the IRQ immediately to prevent
4830          * spurious interrupts.  The flush impacts performance but
4831          * excessive spurious interrupts can be worse in some cases.
4832          */
4833         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4834
4835         /*
4836          * In a shared interrupt configuration, sometimes other devices'
4837          * interrupts will scream.  We record the current status tag here
4838          * so that the above check can report that the screaming interrupts
4839          * are unhandled.  Eventually they will be silenced.
4840          */
4841         tp->last_irq_tag = sblk->status_tag;
4842
4843         if (tg3_irq_sync(tp))
4844                 goto out;
4845
4846         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4847
4848         napi_schedule(&tp->napi);
4849
4850 out:
4851         return IRQ_RETVAL(handled);
4852 }
4853
4854 /* ISR for interrupt test */
4855 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4856 {
4857         struct net_device *dev = dev_id;
4858         struct tg3 *tp = netdev_priv(dev);
4859         struct tg3_hw_status *sblk = tp->hw_status;
4860
4861         if ((sblk->status & SD_STATUS_UPDATED) ||
4862             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4863                 tg3_disable_ints(tp);
4864                 return IRQ_RETVAL(1);
4865         }
4866         return IRQ_RETVAL(0);
4867 }
4868
4869 static int tg3_init_hw(struct tg3 *, int);
4870 static int tg3_halt(struct tg3 *, int, int);
4871
4872 /* Restart hardware after configuration changes, self-test, etc.
4873  * Invoked with tp->lock held.
4874  */
4875 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4876         __releases(tp->lock)
4877         __acquires(tp->lock)
4878 {
4879         int err;
4880
4881         err = tg3_init_hw(tp, reset_phy);
4882         if (err) {
4883                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4884                        "aborting.\n", tp->dev->name);
4885                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4886                 tg3_full_unlock(tp);
4887                 del_timer_sync(&tp->timer);
4888                 tp->irq_sync = 0;
4889                 napi_enable(&tp->napi);
4890                 dev_close(tp->dev);
4891                 tg3_full_lock(tp, 0);
4892         }
4893         return err;
4894 }
4895
4896 #ifdef CONFIG_NET_POLL_CONTROLLER
4897 static void tg3_poll_controller(struct net_device *dev)
4898 {
4899         struct tg3 *tp = netdev_priv(dev);
4900
4901         tg3_interrupt(tp->pdev->irq, dev);
4902 }
4903 #endif
4904
4905 static void tg3_reset_task(struct work_struct *work)
4906 {
4907         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4908         int err;
4909         unsigned int restart_timer;
4910
4911         tg3_full_lock(tp, 0);
4912
4913         if (!netif_running(tp->dev)) {
4914                 tg3_full_unlock(tp);
4915                 return;
4916         }
4917
4918         tg3_full_unlock(tp);
4919
4920         tg3_phy_stop(tp);
4921
4922         tg3_netif_stop(tp);
4923
4924         tg3_full_lock(tp, 1);
4925
4926         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4927         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4928
4929         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4930                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4931                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4932                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4933                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4934         }
4935
4936         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4937         err = tg3_init_hw(tp, 1);
4938         if (err)
4939                 goto out;
4940
4941         tg3_netif_start(tp);
4942
4943         if (restart_timer)
4944                 mod_timer(&tp->timer, jiffies + 1);
4945
4946 out:
4947         tg3_full_unlock(tp);
4948
4949         if (!err)
4950                 tg3_phy_start(tp);
4951 }
4952
4953 static void tg3_dump_short_state(struct tg3 *tp)
4954 {
4955         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4956                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4957         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4958                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4959 }
4960
4961 static void tg3_tx_timeout(struct net_device *dev)
4962 {
4963         struct tg3 *tp = netdev_priv(dev);
4964
4965         if (netif_msg_tx_err(tp)) {
4966                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4967                        dev->name);
4968                 tg3_dump_short_state(tp);
4969         }
4970
4971         schedule_work(&tp->reset_task);
4972 }
4973
4974 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4975 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4976 {
4977         u32 base = (u32) mapping & 0xffffffff;
4978
4979         return ((base > 0xffffdcc0) &&
4980                 (base + len + 8 < base));
4981 }
4982
4983 /* Test for DMA addresses > 40-bit */
4984 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4985                                           int len)
4986 {
4987 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4988         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4989                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
4990         return 0;
4991 #else
4992         return 0;
4993 #endif
4994 }
4995
4996 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4997
4998 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4999 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5000                                        u32 last_plus_one, u32 *start,
5001                                        u32 base_flags, u32 mss)
5002 {
5003         struct sk_buff *new_skb;
5004         dma_addr_t new_addr = 0;
5005         u32 entry = *start;
5006         int i, ret = 0;
5007
5008         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5009                 new_skb = skb_copy(skb, GFP_ATOMIC);
5010         else {
5011                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5012
5013                 new_skb = skb_copy_expand(skb,
5014                                           skb_headroom(skb) + more_headroom,
5015                                           skb_tailroom(skb), GFP_ATOMIC);
5016         }
5017
5018         if (!new_skb) {
5019                 ret = -1;
5020         } else {
5021                 /* New SKB is guaranteed to be linear. */
5022                 entry = *start;
5023                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5024                 new_addr = skb_shinfo(new_skb)->dma_head;
5025
5026                 /* Make sure new skb does not cross any 4G boundaries.
5027                  * Drop the packet if it does.
5028                  */
5029                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5030                         if (!ret)
5031                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5032                                               DMA_TO_DEVICE);
5033                         ret = -1;
5034                         dev_kfree_skb(new_skb);
5035                         new_skb = NULL;
5036                 } else {
5037                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5038                                     base_flags, 1 | (mss << 1));
5039                         *start = NEXT_TX(entry);
5040                 }
5041         }
5042
5043         /* Now clean up the sw ring entries. */
5044         i = 0;
5045         while (entry != last_plus_one) {
5046                 if (i == 0) {
5047                         tp->tx_buffers[entry].skb = new_skb;
5048                 } else {
5049                         tp->tx_buffers[entry].skb = NULL;
5050                 }
5051                 entry = NEXT_TX(entry);
5052                 i++;
5053         }
5054
5055         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5056         dev_kfree_skb(skb);
5057
5058         return ret;
5059 }
5060
5061 static void tg3_set_txd(struct tg3 *tp, int entry,
5062                         dma_addr_t mapping, int len, u32 flags,
5063                         u32 mss_and_is_end)
5064 {
5065         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5066         int is_end = (mss_and_is_end & 0x1);
5067         u32 mss = (mss_and_is_end >> 1);
5068         u32 vlan_tag = 0;
5069
5070         if (is_end)
5071                 flags |= TXD_FLAG_END;
5072         if (flags & TXD_FLAG_VLAN) {
5073                 vlan_tag = flags >> 16;
5074                 flags &= 0xffff;
5075         }
5076         vlan_tag |= (mss << TXD_MSS_SHIFT);
5077
5078         txd->addr_hi = ((u64) mapping >> 32);
5079         txd->addr_lo = ((u64) mapping & 0xffffffff);
5080         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5081         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5082 }
5083
5084 /* hard_start_xmit for devices that don't have any bugs and
5085  * support TG3_FLG2_HW_TSO_2 only.
5086  */
5087 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5088 {
5089         struct tg3 *tp = netdev_priv(dev);
5090         u32 len, entry, base_flags, mss;
5091         struct skb_shared_info *sp;
5092         dma_addr_t mapping;
5093
5094         len = skb_headlen(skb);
5095
5096         /* We are running in BH disabled context with netif_tx_lock
5097          * and TX reclaim runs via tp->napi.poll inside of a software
5098          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5099          * no IRQ context deadlocks to worry about either.  Rejoice!
5100          */
5101         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5102                 if (!netif_queue_stopped(dev)) {
5103                         netif_stop_queue(dev);
5104
5105                         /* This is a hard error, log it. */
5106                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5107                                "queue awake!\n", dev->name);
5108                 }
5109                 return NETDEV_TX_BUSY;
5110         }
5111
5112         entry = tp->tx_prod;
5113         base_flags = 0;
5114         mss = 0;
5115         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5116                 int tcp_opt_len, ip_tcp_len;
5117
5118                 if (skb_header_cloned(skb) &&
5119                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5120                         dev_kfree_skb(skb);
5121                         goto out_unlock;
5122                 }
5123
5124                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5125                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5126                 else {
5127                         struct iphdr *iph = ip_hdr(skb);
5128
5129                         tcp_opt_len = tcp_optlen(skb);
5130                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5131
5132                         iph->check = 0;
5133                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5134                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5135                 }
5136
5137                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5138                                TXD_FLAG_CPU_POST_DMA);
5139
5140                 tcp_hdr(skb)->check = 0;
5141
5142         }
5143         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5144                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5145 #if TG3_VLAN_TAG_USED
5146         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5147                 base_flags |= (TXD_FLAG_VLAN |
5148                                (vlan_tx_tag_get(skb) << 16));
5149 #endif
5150
5151         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5152                 dev_kfree_skb(skb);
5153                 goto out_unlock;
5154         }
5155
5156         sp = skb_shinfo(skb);
5157
5158         mapping = sp->dma_head;
5159
5160         tp->tx_buffers[entry].skb = skb;
5161
5162         tg3_set_txd(tp, entry, mapping, len, base_flags,
5163                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5164
5165         entry = NEXT_TX(entry);
5166
5167         /* Now loop through additional data fragments, and queue them. */
5168         if (skb_shinfo(skb)->nr_frags > 0) {
5169                 unsigned int i, last;
5170
5171                 last = skb_shinfo(skb)->nr_frags - 1;
5172                 for (i = 0; i <= last; i++) {
5173                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5174
5175                         len = frag->size;
5176                         mapping = sp->dma_maps[i];
5177                         tp->tx_buffers[entry].skb = NULL;
5178
5179                         tg3_set_txd(tp, entry, mapping, len,
5180                                     base_flags, (i == last) | (mss << 1));
5181
5182                         entry = NEXT_TX(entry);
5183                 }
5184         }
5185
5186         /* Packets are ready, update Tx producer idx local and on card. */
5187         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5188
5189         tp->tx_prod = entry;
5190         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5191                 netif_stop_queue(dev);
5192                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5193                         netif_wake_queue(tp->dev);
5194         }
5195
5196 out_unlock:
5197         mmiowb();
5198
5199         return NETDEV_TX_OK;
5200 }
5201
5202 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5203
5204 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5205  * TSO header is greater than 80 bytes.
5206  */
5207 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5208 {
5209         struct sk_buff *segs, *nskb;
5210
5211         /* Estimate the number of fragments in the worst case */
5212         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5213                 netif_stop_queue(tp->dev);
5214                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5215                         return NETDEV_TX_BUSY;
5216
5217                 netif_wake_queue(tp->dev);
5218         }
5219
5220         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5221         if (IS_ERR(segs))
5222                 goto tg3_tso_bug_end;
5223
5224         do {
5225                 nskb = segs;
5226                 segs = segs->next;
5227                 nskb->next = NULL;
5228                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5229         } while (segs);
5230
5231 tg3_tso_bug_end:
5232         dev_kfree_skb(skb);
5233
5234         return NETDEV_TX_OK;
5235 }
5236
5237 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5238  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5239  */
5240 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5241 {
5242         struct tg3 *tp = netdev_priv(dev);
5243         u32 len, entry, base_flags, mss;
5244         struct skb_shared_info *sp;
5245         int would_hit_hwbug;
5246         dma_addr_t mapping;
5247
5248         len = skb_headlen(skb);
5249
5250         /* We are running in BH disabled context with netif_tx_lock
5251          * and TX reclaim runs via tp->napi.poll inside of a software
5252          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5253          * no IRQ context deadlocks to worry about either.  Rejoice!
5254          */
5255         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5256                 if (!netif_queue_stopped(dev)) {
5257                         netif_stop_queue(dev);
5258
5259                         /* This is a hard error, log it. */
5260                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5261                                "queue awake!\n", dev->name);
5262                 }
5263                 return NETDEV_TX_BUSY;
5264         }
5265
5266         entry = tp->tx_prod;
5267         base_flags = 0;
5268         if (skb->ip_summed == CHECKSUM_PARTIAL)
5269                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5270         mss = 0;
5271         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5272                 struct iphdr *iph;
5273                 int tcp_opt_len, ip_tcp_len, hdr_len;
5274
5275                 if (skb_header_cloned(skb) &&
5276                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5277                         dev_kfree_skb(skb);
5278                         goto out_unlock;
5279                 }
5280
5281                 tcp_opt_len = tcp_optlen(skb);
5282                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5283
5284                 hdr_len = ip_tcp_len + tcp_opt_len;
5285                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5286                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5287                         return (tg3_tso_bug(tp, skb));
5288
5289                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5290                                TXD_FLAG_CPU_POST_DMA);
5291
5292                 iph = ip_hdr(skb);
5293                 iph->check = 0;
5294                 iph->tot_len = htons(mss + hdr_len);
5295                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5296                         tcp_hdr(skb)->check = 0;
5297                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5298                 } else
5299                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5300                                                                  iph->daddr, 0,
5301                                                                  IPPROTO_TCP,
5302                                                                  0);
5303
5304                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5305                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5306                         if (tcp_opt_len || iph->ihl > 5) {
5307                                 int tsflags;
5308
5309                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5310                                 mss |= (tsflags << 11);
5311                         }
5312                 } else {
5313                         if (tcp_opt_len || iph->ihl > 5) {
5314                                 int tsflags;
5315
5316                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5317                                 base_flags |= tsflags << 12;
5318                         }
5319                 }
5320         }
5321 #if TG3_VLAN_TAG_USED
5322         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5323                 base_flags |= (TXD_FLAG_VLAN |
5324                                (vlan_tx_tag_get(skb) << 16));
5325 #endif
5326
5327         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5328                 dev_kfree_skb(skb);
5329                 goto out_unlock;
5330         }
5331
5332         sp = skb_shinfo(skb);
5333
5334         mapping = sp->dma_head;
5335
5336         tp->tx_buffers[entry].skb = skb;
5337
5338         would_hit_hwbug = 0;
5339
5340         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5341                 would_hit_hwbug = 1;
5342         else if (tg3_4g_overflow_test(mapping, len))
5343                 would_hit_hwbug = 1;
5344
5345         tg3_set_txd(tp, entry, mapping, len, base_flags,
5346                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5347
5348         entry = NEXT_TX(entry);
5349
5350         /* Now loop through additional data fragments, and queue them. */
5351         if (skb_shinfo(skb)->nr_frags > 0) {
5352                 unsigned int i, last;
5353
5354                 last = skb_shinfo(skb)->nr_frags - 1;
5355                 for (i = 0; i <= last; i++) {
5356                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5357
5358                         len = frag->size;
5359                         mapping = sp->dma_maps[i];
5360
5361                         tp->tx_buffers[entry].skb = NULL;
5362
5363                         if (tg3_4g_overflow_test(mapping, len))
5364                                 would_hit_hwbug = 1;
5365
5366                         if (tg3_40bit_overflow_test(tp, mapping, len))
5367                                 would_hit_hwbug = 1;
5368
5369                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5370                                 tg3_set_txd(tp, entry, mapping, len,
5371                                             base_flags, (i == last)|(mss << 1));
5372                         else
5373                                 tg3_set_txd(tp, entry, mapping, len,
5374                                             base_flags, (i == last));
5375
5376                         entry = NEXT_TX(entry);
5377                 }
5378         }
5379
5380         if (would_hit_hwbug) {
5381                 u32 last_plus_one = entry;
5382                 u32 start;
5383
5384                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5385                 start &= (TG3_TX_RING_SIZE - 1);
5386
5387                 /* If the workaround fails due to memory/mapping
5388                  * failure, silently drop this packet.
5389                  */
5390                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5391                                                 &start, base_flags, mss))
5392                         goto out_unlock;
5393
5394                 entry = start;
5395         }
5396
5397         /* Packets are ready, update Tx producer idx local and on card. */
5398         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5399
5400         tp->tx_prod = entry;
5401         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5402                 netif_stop_queue(dev);
5403                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5404                         netif_wake_queue(tp->dev);
5405         }
5406
5407 out_unlock:
5408         mmiowb();
5409
5410         return NETDEV_TX_OK;
5411 }
5412
5413 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5414                                int new_mtu)
5415 {
5416         dev->mtu = new_mtu;
5417
5418         if (new_mtu > ETH_DATA_LEN) {
5419                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5420                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5421                         ethtool_op_set_tso(dev, 0);
5422                 }
5423                 else
5424                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5425         } else {
5426                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5427                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5428                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5429         }
5430 }
5431
5432 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5433 {
5434         struct tg3 *tp = netdev_priv(dev);
5435         int err;
5436
5437         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5438                 return -EINVAL;
5439
5440         if (!netif_running(dev)) {
5441                 /* We'll just catch it later when the
5442                  * device is up'd.
5443                  */
5444                 tg3_set_mtu(dev, tp, new_mtu);
5445                 return 0;
5446         }
5447
5448         tg3_phy_stop(tp);
5449
5450         tg3_netif_stop(tp);
5451
5452         tg3_full_lock(tp, 1);
5453
5454         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5455
5456         tg3_set_mtu(dev, tp, new_mtu);
5457
5458         err = tg3_restart_hw(tp, 0);
5459
5460         if (!err)
5461                 tg3_netif_start(tp);
5462
5463         tg3_full_unlock(tp);
5464
5465         if (!err)
5466                 tg3_phy_start(tp);
5467
5468         return err;
5469 }
5470
5471 /* Free up pending packets in all rx/tx rings.
5472  *
5473  * The chip has been shut down and the driver detached from
5474  * the networking, so no interrupts or new tx packets will
5475  * end up in the driver.  tp->{tx,}lock is not held and we are not
5476  * in an interrupt context and thus may sleep.
5477  */
5478 static void tg3_free_rings(struct tg3 *tp)
5479 {
5480         struct ring_info *rxp;
5481         int i;
5482
5483         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5484                 rxp = &tp->rx_std_buffers[i];
5485
5486                 if (rxp->skb == NULL)
5487                         continue;
5488                 pci_unmap_single(tp->pdev,
5489                                  pci_unmap_addr(rxp, mapping),
5490                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5491                                  PCI_DMA_FROMDEVICE);
5492                 dev_kfree_skb_any(rxp->skb);
5493                 rxp->skb = NULL;
5494         }
5495
5496         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5497                 rxp = &tp->rx_jumbo_buffers[i];
5498
5499                 if (rxp->skb == NULL)
5500                         continue;
5501                 pci_unmap_single(tp->pdev,
5502                                  pci_unmap_addr(rxp, mapping),
5503                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5504                                  PCI_DMA_FROMDEVICE);
5505                 dev_kfree_skb_any(rxp->skb);
5506                 rxp->skb = NULL;
5507         }
5508
5509         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5510                 struct tx_ring_info *txp;
5511                 struct sk_buff *skb;
5512
5513                 txp = &tp->tx_buffers[i];
5514                 skb = txp->skb;
5515
5516                 if (skb == NULL) {
5517                         i++;
5518                         continue;
5519                 }
5520
5521                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5522
5523                 txp->skb = NULL;
5524
5525                 i += skb_shinfo(skb)->nr_frags + 1;
5526
5527                 dev_kfree_skb_any(skb);
5528         }
5529 }
5530
5531 /* Initialize tx/rx rings for packet processing.
5532  *
5533  * The chip has been shut down and the driver detached from
5534  * the networking, so no interrupts or new tx packets will
5535  * end up in the driver.  tp->{tx,}lock are held and thus
5536  * we may not sleep.
5537  */
5538 static int tg3_init_rings(struct tg3 *tp)
5539 {
5540         u32 i;
5541
5542         /* Free up all the SKBs. */
5543         tg3_free_rings(tp);
5544
5545         /* Zero out all descriptors. */
5546         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5547         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5548         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5549         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5550
5551         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5552         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5553             (tp->dev->mtu > ETH_DATA_LEN))
5554                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5555
5556         /* Initialize invariants of the rings, we only set this
5557          * stuff once.  This works because the card does not
5558          * write into the rx buffer posting rings.
5559          */
5560         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5561                 struct tg3_rx_buffer_desc *rxd;
5562
5563                 rxd = &tp->rx_std[i];
5564                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5565                         << RXD_LEN_SHIFT;
5566                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5567                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5568                                (i << RXD_OPAQUE_INDEX_SHIFT));
5569         }
5570
5571         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5572                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5573                         struct tg3_rx_buffer_desc *rxd;
5574
5575                         rxd = &tp->rx_jumbo[i];
5576                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5577                                 << RXD_LEN_SHIFT;
5578                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5579                                 RXD_FLAG_JUMBO;
5580                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5581                                (i << RXD_OPAQUE_INDEX_SHIFT));
5582                 }
5583         }
5584
5585         /* Now allocate fresh SKBs for each rx ring. */
5586         for (i = 0; i < tp->rx_pending; i++) {
5587                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5588                         printk(KERN_WARNING PFX
5589                                "%s: Using a smaller RX standard ring, "
5590                                "only %d out of %d buffers were allocated "
5591                                "successfully.\n",
5592                                tp->dev->name, i, tp->rx_pending);
5593                         if (i == 0)
5594                                 return -ENOMEM;
5595                         tp->rx_pending = i;
5596                         break;
5597                 }
5598         }
5599
5600         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5601                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5602                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5603                                              -1, i) < 0) {
5604                                 printk(KERN_WARNING PFX
5605                                        "%s: Using a smaller RX jumbo ring, "
5606                                        "only %d out of %d buffers were "
5607                                        "allocated successfully.\n",
5608                                        tp->dev->name, i, tp->rx_jumbo_pending);
5609                                 if (i == 0) {
5610                                         tg3_free_rings(tp);
5611                                         return -ENOMEM;
5612                                 }
5613                                 tp->rx_jumbo_pending = i;
5614                                 break;
5615                         }
5616                 }
5617         }
5618         return 0;
5619 }
5620
5621 /*
5622  * Must not be invoked with interrupt sources disabled and
5623  * the hardware shutdown down.
5624  */
5625 static void tg3_free_consistent(struct tg3 *tp)
5626 {
5627         kfree(tp->rx_std_buffers);
5628         tp->rx_std_buffers = NULL;
5629         if (tp->rx_std) {
5630                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5631                                     tp->rx_std, tp->rx_std_mapping);
5632                 tp->rx_std = NULL;
5633         }
5634         if (tp->rx_jumbo) {
5635                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5636                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5637                 tp->rx_jumbo = NULL;
5638         }
5639         if (tp->rx_rcb) {
5640                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5641                                     tp->rx_rcb, tp->rx_rcb_mapping);
5642                 tp->rx_rcb = NULL;
5643         }
5644         if (tp->tx_ring) {
5645                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5646                         tp->tx_ring, tp->tx_desc_mapping);
5647                 tp->tx_ring = NULL;
5648         }
5649         if (tp->hw_status) {
5650                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5651                                     tp->hw_status, tp->status_mapping);
5652                 tp->hw_status = NULL;
5653         }
5654         if (tp->hw_stats) {
5655                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5656                                     tp->hw_stats, tp->stats_mapping);
5657                 tp->hw_stats = NULL;
5658         }
5659 }
5660
5661 /*
5662  * Must not be invoked with interrupt sources disabled and
5663  * the hardware shutdown down.  Can sleep.
5664  */
5665 static int tg3_alloc_consistent(struct tg3 *tp)
5666 {
5667         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5668                                       (TG3_RX_RING_SIZE +
5669                                        TG3_RX_JUMBO_RING_SIZE)) +
5670                                      (sizeof(struct tx_ring_info) *
5671                                       TG3_TX_RING_SIZE),
5672                                      GFP_KERNEL);
5673         if (!tp->rx_std_buffers)
5674                 return -ENOMEM;
5675
5676         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5677         tp->tx_buffers = (struct tx_ring_info *)
5678                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5679
5680         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5681                                           &tp->rx_std_mapping);
5682         if (!tp->rx_std)
5683                 goto err_out;
5684
5685         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5686                                             &tp->rx_jumbo_mapping);
5687
5688         if (!tp->rx_jumbo)
5689                 goto err_out;
5690
5691         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5692                                           &tp->rx_rcb_mapping);
5693         if (!tp->rx_rcb)
5694                 goto err_out;
5695
5696         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5697                                            &tp->tx_desc_mapping);
5698         if (!tp->tx_ring)
5699                 goto err_out;
5700
5701         tp->hw_status = pci_alloc_consistent(tp->pdev,
5702                                              TG3_HW_STATUS_SIZE,
5703                                              &tp->status_mapping);
5704         if (!tp->hw_status)
5705                 goto err_out;
5706
5707         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5708                                             sizeof(struct tg3_hw_stats),
5709                                             &tp->stats_mapping);
5710         if (!tp->hw_stats)
5711                 goto err_out;
5712
5713         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5714         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5715
5716         return 0;
5717
5718 err_out:
5719         tg3_free_consistent(tp);
5720         return -ENOMEM;
5721 }
5722
5723 #define MAX_WAIT_CNT 1000
5724
5725 /* To stop a block, clear the enable bit and poll till it
5726  * clears.  tp->lock is held.
5727  */
5728 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5729 {
5730         unsigned int i;
5731         u32 val;
5732
5733         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5734                 switch (ofs) {
5735                 case RCVLSC_MODE:
5736                 case DMAC_MODE:
5737                 case MBFREE_MODE:
5738                 case BUFMGR_MODE:
5739                 case MEMARB_MODE:
5740                         /* We can't enable/disable these bits of the
5741                          * 5705/5750, just say success.
5742                          */
5743                         return 0;
5744
5745                 default:
5746                         break;
5747                 }
5748         }
5749
5750         val = tr32(ofs);
5751         val &= ~enable_bit;
5752         tw32_f(ofs, val);
5753
5754         for (i = 0; i < MAX_WAIT_CNT; i++) {
5755                 udelay(100);
5756                 val = tr32(ofs);
5757                 if ((val & enable_bit) == 0)
5758                         break;
5759         }
5760
5761         if (i == MAX_WAIT_CNT && !silent) {
5762                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5763                        "ofs=%lx enable_bit=%x\n",
5764                        ofs, enable_bit);
5765                 return -ENODEV;
5766         }
5767
5768         return 0;
5769 }
5770
5771 /* tp->lock is held. */
5772 static int tg3_abort_hw(struct tg3 *tp, int silent)
5773 {
5774         int i, err;
5775
5776         tg3_disable_ints(tp);
5777
5778         tp->rx_mode &= ~RX_MODE_ENABLE;
5779         tw32_f(MAC_RX_MODE, tp->rx_mode);
5780         udelay(10);
5781
5782         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5783         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5784         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5785         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5786         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5787         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5788
5789         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5790         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5791         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5792         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5793         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5794         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5795         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5796
5797         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5798         tw32_f(MAC_MODE, tp->mac_mode);
5799         udelay(40);
5800
5801         tp->tx_mode &= ~TX_MODE_ENABLE;
5802         tw32_f(MAC_TX_MODE, tp->tx_mode);
5803
5804         for (i = 0; i < MAX_WAIT_CNT; i++) {
5805                 udelay(100);
5806                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5807                         break;
5808         }
5809         if (i >= MAX_WAIT_CNT) {
5810                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5811                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5812                        tp->dev->name, tr32(MAC_TX_MODE));
5813                 err |= -ENODEV;
5814         }
5815
5816         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5817         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5818         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5819
5820         tw32(FTQ_RESET, 0xffffffff);
5821         tw32(FTQ_RESET, 0x00000000);
5822
5823         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5824         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5825
5826         if (tp->hw_status)
5827                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5828         if (tp->hw_stats)
5829                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5830
5831         return err;
5832 }
5833
5834 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5835 {
5836         int i;
5837         u32 apedata;
5838
5839         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5840         if (apedata != APE_SEG_SIG_MAGIC)
5841                 return;
5842
5843         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5844         if (!(apedata & APE_FW_STATUS_READY))
5845                 return;
5846
5847         /* Wait for up to 1 millisecond for APE to service previous event. */
5848         for (i = 0; i < 10; i++) {
5849                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5850                         return;
5851
5852                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5853
5854                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5855                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5856                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5857
5858                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5859
5860                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5861                         break;
5862
5863                 udelay(100);
5864         }
5865
5866         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5867                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5868 }
5869
5870 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5871 {
5872         u32 event;
5873         u32 apedata;
5874
5875         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5876                 return;
5877
5878         switch (kind) {
5879                 case RESET_KIND_INIT:
5880                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5881                                         APE_HOST_SEG_SIG_MAGIC);
5882                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5883                                         APE_HOST_SEG_LEN_MAGIC);
5884                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5885                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5886                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5887                                         APE_HOST_DRIVER_ID_MAGIC);
5888                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5889                                         APE_HOST_BEHAV_NO_PHYLOCK);
5890
5891                         event = APE_EVENT_STATUS_STATE_START;
5892                         break;
5893                 case RESET_KIND_SHUTDOWN:
5894                         /* With the interface we are currently using,
5895                          * APE does not track driver state.  Wiping
5896                          * out the HOST SEGMENT SIGNATURE forces
5897                          * the APE to assume OS absent status.
5898                          */
5899                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5900
5901                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5902                         break;
5903                 case RESET_KIND_SUSPEND:
5904                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5905                         break;
5906                 default:
5907                         return;
5908         }
5909
5910         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5911
5912         tg3_ape_send_event(tp, event);
5913 }
5914
5915 /* tp->lock is held. */
5916 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5917 {
5918         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5919                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5920
5921         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5922                 switch (kind) {
5923                 case RESET_KIND_INIT:
5924                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5925                                       DRV_STATE_START);
5926                         break;
5927
5928                 case RESET_KIND_SHUTDOWN:
5929                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5930                                       DRV_STATE_UNLOAD);
5931                         break;
5932
5933                 case RESET_KIND_SUSPEND:
5934                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5935                                       DRV_STATE_SUSPEND);
5936                         break;
5937
5938                 default:
5939                         break;
5940                 }
5941         }
5942
5943         if (kind == RESET_KIND_INIT ||
5944             kind == RESET_KIND_SUSPEND)
5945                 tg3_ape_driver_state_change(tp, kind);
5946 }
5947
5948 /* tp->lock is held. */
5949 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5950 {
5951         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5952                 switch (kind) {
5953                 case RESET_KIND_INIT:
5954                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5955                                       DRV_STATE_START_DONE);
5956                         break;
5957
5958                 case RESET_KIND_SHUTDOWN:
5959                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5960                                       DRV_STATE_UNLOAD_DONE);
5961                         break;
5962
5963                 default:
5964                         break;
5965                 }
5966         }
5967
5968         if (kind == RESET_KIND_SHUTDOWN)
5969                 tg3_ape_driver_state_change(tp, kind);
5970 }
5971
5972 /* tp->lock is held. */
5973 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5974 {
5975         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5976                 switch (kind) {
5977                 case RESET_KIND_INIT:
5978                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5979                                       DRV_STATE_START);
5980                         break;
5981
5982                 case RESET_KIND_SHUTDOWN:
5983                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5984                                       DRV_STATE_UNLOAD);
5985                         break;
5986
5987                 case RESET_KIND_SUSPEND:
5988                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5989                                       DRV_STATE_SUSPEND);
5990                         break;
5991
5992                 default:
5993                         break;
5994                 }
5995         }
5996 }
5997
5998 static int tg3_poll_fw(struct tg3 *tp)
5999 {
6000         int i;
6001         u32 val;
6002
6003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6004                 /* Wait up to 20ms for init done. */
6005                 for (i = 0; i < 200; i++) {
6006                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6007                                 return 0;
6008                         udelay(100);
6009                 }
6010                 return -ENODEV;
6011         }
6012
6013         /* Wait for firmware initialization to complete. */
6014         for (i = 0; i < 100000; i++) {
6015                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6016                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6017                         break;
6018                 udelay(10);
6019         }
6020
6021         /* Chip might not be fitted with firmware.  Some Sun onboard
6022          * parts are configured like that.  So don't signal the timeout
6023          * of the above loop as an error, but do report the lack of
6024          * running firmware once.
6025          */
6026         if (i >= 100000 &&
6027             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6028                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6029
6030                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6031                        tp->dev->name);
6032         }
6033
6034         return 0;
6035 }
6036
6037 /* Save PCI command register before chip reset */
6038 static void tg3_save_pci_state(struct tg3 *tp)
6039 {
6040         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6041 }
6042
6043 /* Restore PCI state after chip reset */
6044 static void tg3_restore_pci_state(struct tg3 *tp)
6045 {
6046         u32 val;
6047
6048         /* Re-enable indirect register accesses. */
6049         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6050                                tp->misc_host_ctrl);
6051
6052         /* Set MAX PCI retry to zero. */
6053         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6054         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6055             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6056                 val |= PCISTATE_RETRY_SAME_DMA;
6057         /* Allow reads and writes to the APE register and memory space. */
6058         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6059                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6060                        PCISTATE_ALLOW_APE_SHMEM_WR;
6061         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6062
6063         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6064
6065         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6066                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6067                         pcie_set_readrq(tp->pdev, 4096);
6068                 else {
6069                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6070                                               tp->pci_cacheline_sz);
6071                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6072                                               tp->pci_lat_timer);
6073                 }
6074         }
6075
6076         /* Make sure PCI-X relaxed ordering bit is clear. */
6077         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6078                 u16 pcix_cmd;
6079
6080                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6081                                      &pcix_cmd);
6082                 pcix_cmd &= ~PCI_X_CMD_ERO;
6083                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6084                                       pcix_cmd);
6085         }
6086
6087         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6088
6089                 /* Chip reset on 5780 will reset MSI enable bit,
6090                  * so need to restore it.
6091                  */
6092                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6093                         u16 ctrl;
6094
6095                         pci_read_config_word(tp->pdev,
6096                                              tp->msi_cap + PCI_MSI_FLAGS,
6097                                              &ctrl);
6098                         pci_write_config_word(tp->pdev,
6099                                               tp->msi_cap + PCI_MSI_FLAGS,
6100                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6101                         val = tr32(MSGINT_MODE);
6102                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6103                 }
6104         }
6105 }
6106
6107 static void tg3_stop_fw(struct tg3 *);
6108
6109 /* tp->lock is held. */
6110 static int tg3_chip_reset(struct tg3 *tp)
6111 {
6112         u32 val;
6113         void (*write_op)(struct tg3 *, u32, u32);
6114         int err;
6115
6116         tg3_nvram_lock(tp);
6117
6118         tg3_mdio_stop(tp);
6119
6120         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6121
6122         /* No matching tg3_nvram_unlock() after this because
6123          * chip reset below will undo the nvram lock.
6124          */
6125         tp->nvram_lock_cnt = 0;
6126
6127         /* GRC_MISC_CFG core clock reset will clear the memory
6128          * enable bit in PCI register 4 and the MSI enable bit
6129          * on some chips, so we save relevant registers here.
6130          */
6131         tg3_save_pci_state(tp);
6132
6133         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6134             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6135                 tw32(GRC_FASTBOOT_PC, 0);
6136
6137         /*
6138          * We must avoid the readl() that normally takes place.
6139          * It locks machines, causes machine checks, and other
6140          * fun things.  So, temporarily disable the 5701
6141          * hardware workaround, while we do the reset.
6142          */
6143         write_op = tp->write32;
6144         if (write_op == tg3_write_flush_reg32)
6145                 tp->write32 = tg3_write32;
6146
6147         /* Prevent the irq handler from reading or writing PCI registers
6148          * during chip reset when the memory enable bit in the PCI command
6149          * register may be cleared.  The chip does not generate interrupt
6150          * at this time, but the irq handler may still be called due to irq
6151          * sharing or irqpoll.
6152          */
6153         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6154         if (tp->hw_status) {
6155                 tp->hw_status->status = 0;
6156                 tp->hw_status->status_tag = 0;
6157         }
6158         tp->last_tag = 0;
6159         tp->last_irq_tag = 0;
6160         smp_mb();
6161         synchronize_irq(tp->pdev->irq);
6162
6163         /* do the reset */
6164         val = GRC_MISC_CFG_CORECLK_RESET;
6165
6166         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6167                 if (tr32(0x7e2c) == 0x60) {
6168                         tw32(0x7e2c, 0x20);
6169                 }
6170                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6171                         tw32(GRC_MISC_CFG, (1 << 29));
6172                         val |= (1 << 29);
6173                 }
6174         }
6175
6176         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6177                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6178                 tw32(GRC_VCPU_EXT_CTRL,
6179                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6180         }
6181
6182         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6183                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6184         tw32(GRC_MISC_CFG, val);
6185
6186         /* restore 5701 hardware bug workaround write method */
6187         tp->write32 = write_op;
6188
6189         /* Unfortunately, we have to delay before the PCI read back.
6190          * Some 575X chips even will not respond to a PCI cfg access
6191          * when the reset command is given to the chip.
6192          *
6193          * How do these hardware designers expect things to work
6194          * properly if the PCI write is posted for a long period
6195          * of time?  It is always necessary to have some method by
6196          * which a register read back can occur to push the write
6197          * out which does the reset.
6198          *
6199          * For most tg3 variants the trick below was working.
6200          * Ho hum...
6201          */
6202         udelay(120);
6203
6204         /* Flush PCI posted writes.  The normal MMIO registers
6205          * are inaccessible at this time so this is the only
6206          * way to make this reliably (actually, this is no longer
6207          * the case, see above).  I tried to use indirect
6208          * register read/write but this upset some 5701 variants.
6209          */
6210         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6211
6212         udelay(120);
6213
6214         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6215                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6216                         int i;
6217                         u32 cfg_val;
6218
6219                         /* Wait for link training to complete.  */
6220                         for (i = 0; i < 5000; i++)
6221                                 udelay(100);
6222
6223                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6224                         pci_write_config_dword(tp->pdev, 0xc4,
6225                                                cfg_val | (1 << 15));
6226                 }
6227
6228                 /* Set PCIE max payload size to 128 bytes and
6229                  * clear the "no snoop" and "relaxed ordering" bits.
6230                  */
6231                 pci_write_config_word(tp->pdev,
6232                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6233                                       0);
6234
6235                 pcie_set_readrq(tp->pdev, 4096);
6236
6237                 /* Clear error status */
6238                 pci_write_config_word(tp->pdev,
6239                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6240                                       PCI_EXP_DEVSTA_CED |
6241                                       PCI_EXP_DEVSTA_NFED |
6242                                       PCI_EXP_DEVSTA_FED |
6243                                       PCI_EXP_DEVSTA_URD);
6244         }
6245
6246         tg3_restore_pci_state(tp);
6247
6248         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6249
6250         val = 0;
6251         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6252                 val = tr32(MEMARB_MODE);
6253         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6254
6255         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6256                 tg3_stop_fw(tp);
6257                 tw32(0x5000, 0x400);
6258         }
6259
6260         tw32(GRC_MODE, tp->grc_mode);
6261
6262         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6263                 val = tr32(0xc4);
6264
6265                 tw32(0xc4, val | (1 << 15));
6266         }
6267
6268         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6269             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6270                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6271                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6272                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6273                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6274         }
6275
6276         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6277                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6278                 tw32_f(MAC_MODE, tp->mac_mode);
6279         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6280                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6281                 tw32_f(MAC_MODE, tp->mac_mode);
6282         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6283                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6284                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6285                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6286                 tw32_f(MAC_MODE, tp->mac_mode);
6287         } else
6288                 tw32_f(MAC_MODE, 0);
6289         udelay(40);
6290
6291         tg3_mdio_start(tp);
6292
6293         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6294
6295         err = tg3_poll_fw(tp);
6296         if (err)
6297                 return err;
6298
6299         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6300             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6301                 val = tr32(0x7c00);
6302
6303                 tw32(0x7c00, val | (1 << 25));
6304         }
6305
6306         /* Reprobe ASF enable state.  */
6307         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6308         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6309         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6310         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6311                 u32 nic_cfg;
6312
6313                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6314                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6315                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6316                         tp->last_event_jiffies = jiffies;
6317                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6318                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6319                 }
6320         }
6321
6322         return 0;
6323 }
6324
6325 /* tp->lock is held. */
6326 static void tg3_stop_fw(struct tg3 *tp)
6327 {
6328         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6329            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6330                 /* Wait for RX cpu to ACK the previous event. */
6331                 tg3_wait_for_event_ack(tp);
6332
6333                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6334
6335                 tg3_generate_fw_event(tp);
6336
6337                 /* Wait for RX cpu to ACK this event. */
6338                 tg3_wait_for_event_ack(tp);
6339         }
6340 }
6341
6342 /* tp->lock is held. */
6343 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6344 {
6345         int err;
6346
6347         tg3_stop_fw(tp);
6348
6349         tg3_write_sig_pre_reset(tp, kind);
6350
6351         tg3_abort_hw(tp, silent);
6352         err = tg3_chip_reset(tp);
6353
6354         __tg3_set_mac_addr(tp, 0);
6355
6356         tg3_write_sig_legacy(tp, kind);
6357         tg3_write_sig_post_reset(tp, kind);
6358
6359         if (err)
6360                 return err;
6361
6362         return 0;
6363 }
6364
6365 #define RX_CPU_SCRATCH_BASE     0x30000
6366 #define RX_CPU_SCRATCH_SIZE     0x04000
6367 #define TX_CPU_SCRATCH_BASE     0x34000
6368 #define TX_CPU_SCRATCH_SIZE     0x04000
6369
6370 /* tp->lock is held. */
6371 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6372 {
6373         int i;
6374
6375         BUG_ON(offset == TX_CPU_BASE &&
6376             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6377
6378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6379                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6380
6381                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6382                 return 0;
6383         }
6384         if (offset == RX_CPU_BASE) {
6385                 for (i = 0; i < 10000; i++) {
6386                         tw32(offset + CPU_STATE, 0xffffffff);
6387                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6388                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6389                                 break;
6390                 }
6391
6392                 tw32(offset + CPU_STATE, 0xffffffff);
6393                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6394                 udelay(10);
6395         } else {
6396                 for (i = 0; i < 10000; i++) {
6397                         tw32(offset + CPU_STATE, 0xffffffff);
6398                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6399                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6400                                 break;
6401                 }
6402         }
6403
6404         if (i >= 10000) {
6405                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6406                        "and %s CPU\n",
6407                        tp->dev->name,
6408                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6409                 return -ENODEV;
6410         }
6411
6412         /* Clear firmware's nvram arbitration. */
6413         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6414                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6415         return 0;
6416 }
6417
6418 struct fw_info {
6419         unsigned int fw_base;
6420         unsigned int fw_len;
6421         const __be32 *fw_data;
6422 };
6423
6424 /* tp->lock is held. */
6425 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6426                                  int cpu_scratch_size, struct fw_info *info)
6427 {
6428         int err, lock_err, i;
6429         void (*write_op)(struct tg3 *, u32, u32);
6430
6431         if (cpu_base == TX_CPU_BASE &&
6432             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6433                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6434                        "TX cpu firmware on %s which is 5705.\n",
6435                        tp->dev->name);
6436                 return -EINVAL;
6437         }
6438
6439         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6440                 write_op = tg3_write_mem;
6441         else
6442                 write_op = tg3_write_indirect_reg32;
6443
6444         /* It is possible that bootcode is still loading at this point.
6445          * Get the nvram lock first before halting the cpu.
6446          */
6447         lock_err = tg3_nvram_lock(tp);
6448         err = tg3_halt_cpu(tp, cpu_base);
6449         if (!lock_err)
6450                 tg3_nvram_unlock(tp);
6451         if (err)
6452                 goto out;
6453
6454         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6455                 write_op(tp, cpu_scratch_base + i, 0);
6456         tw32(cpu_base + CPU_STATE, 0xffffffff);
6457         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6458         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6459                 write_op(tp, (cpu_scratch_base +
6460                               (info->fw_base & 0xffff) +
6461                               (i * sizeof(u32))),
6462                               be32_to_cpu(info->fw_data[i]));
6463
6464         err = 0;
6465
6466 out:
6467         return err;
6468 }
6469
6470 /* tp->lock is held. */
6471 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6472 {
6473         struct fw_info info;
6474         const __be32 *fw_data;
6475         int err, i;
6476
6477         fw_data = (void *)tp->fw->data;
6478
6479         /* Firmware blob starts with version numbers, followed by
6480            start address and length. We are setting complete length.
6481            length = end_address_of_bss - start_address_of_text.
6482            Remainder is the blob to be loaded contiguously
6483            from start address. */
6484
6485         info.fw_base = be32_to_cpu(fw_data[1]);
6486         info.fw_len = tp->fw->size - 12;
6487         info.fw_data = &fw_data[3];
6488
6489         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6490                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6491                                     &info);
6492         if (err)
6493                 return err;
6494
6495         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6496                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6497                                     &info);
6498         if (err)
6499                 return err;
6500
6501         /* Now startup only the RX cpu. */
6502         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6503         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6504
6505         for (i = 0; i < 5; i++) {
6506                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6507                         break;
6508                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6509                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6510                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6511                 udelay(1000);
6512         }
6513         if (i >= 5) {
6514                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6515                        "to set RX CPU PC, is %08x should be %08x\n",
6516                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6517                        info.fw_base);
6518                 return -ENODEV;
6519         }
6520         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6521         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6522
6523         return 0;
6524 }
6525
6526 /* 5705 needs a special version of the TSO firmware.  */
6527
6528 /* tp->lock is held. */
6529 static int tg3_load_tso_firmware(struct tg3 *tp)
6530 {
6531         struct fw_info info;
6532         const __be32 *fw_data;
6533         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6534         int err, i;
6535
6536         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6537                 return 0;
6538
6539         fw_data = (void *)tp->fw->data;
6540
6541         /* Firmware blob starts with version numbers, followed by
6542            start address and length. We are setting complete length.
6543            length = end_address_of_bss - start_address_of_text.
6544            Remainder is the blob to be loaded contiguously
6545            from start address. */
6546
6547         info.fw_base = be32_to_cpu(fw_data[1]);
6548         cpu_scratch_size = tp->fw_len;
6549         info.fw_len = tp->fw->size - 12;
6550         info.fw_data = &fw_data[3];
6551
6552         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6553                 cpu_base = RX_CPU_BASE;
6554                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6555         } else {
6556                 cpu_base = TX_CPU_BASE;
6557                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6558                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6559         }
6560
6561         err = tg3_load_firmware_cpu(tp, cpu_base,
6562                                     cpu_scratch_base, cpu_scratch_size,
6563                                     &info);
6564         if (err)
6565                 return err;
6566
6567         /* Now startup the cpu. */
6568         tw32(cpu_base + CPU_STATE, 0xffffffff);
6569         tw32_f(cpu_base + CPU_PC, info.fw_base);
6570
6571         for (i = 0; i < 5; i++) {
6572                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6573                         break;
6574                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6575                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6576                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6577                 udelay(1000);
6578         }
6579         if (i >= 5) {
6580                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6581                        "to set CPU PC, is %08x should be %08x\n",
6582                        tp->dev->name, tr32(cpu_base + CPU_PC),
6583                        info.fw_base);
6584                 return -ENODEV;
6585         }
6586         tw32(cpu_base + CPU_STATE, 0xffffffff);
6587         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6588         return 0;
6589 }
6590
6591
6592 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6593 {
6594         struct tg3 *tp = netdev_priv(dev);
6595         struct sockaddr *addr = p;
6596         int err = 0, skip_mac_1 = 0;
6597
6598         if (!is_valid_ether_addr(addr->sa_data))
6599                 return -EINVAL;
6600
6601         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6602
6603         if (!netif_running(dev))
6604                 return 0;
6605
6606         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6607                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6608
6609                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6610                 addr0_low = tr32(MAC_ADDR_0_LOW);
6611                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6612                 addr1_low = tr32(MAC_ADDR_1_LOW);
6613
6614                 /* Skip MAC addr 1 if ASF is using it. */
6615                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6616                     !(addr1_high == 0 && addr1_low == 0))
6617                         skip_mac_1 = 1;
6618         }
6619         spin_lock_bh(&tp->lock);
6620         __tg3_set_mac_addr(tp, skip_mac_1);
6621         spin_unlock_bh(&tp->lock);
6622
6623         return err;
6624 }
6625
6626 /* tp->lock is held. */
6627 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6628                            dma_addr_t mapping, u32 maxlen_flags,
6629                            u32 nic_addr)
6630 {
6631         tg3_write_mem(tp,
6632                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6633                       ((u64) mapping >> 32));
6634         tg3_write_mem(tp,
6635                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6636                       ((u64) mapping & 0xffffffff));
6637         tg3_write_mem(tp,
6638                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6639                        maxlen_flags);
6640
6641         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6642                 tg3_write_mem(tp,
6643                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6644                               nic_addr);
6645 }
6646
6647 static void __tg3_set_rx_mode(struct net_device *);
6648 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6649 {
6650         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6651         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6652         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6653         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6654         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6655                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6656                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6657         }
6658         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6659         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6660         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6661                 u32 val = ec->stats_block_coalesce_usecs;
6662
6663                 if (!netif_carrier_ok(tp->dev))
6664                         val = 0;
6665
6666                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6667         }
6668 }
6669
6670 /* tp->lock is held. */
6671 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6672 {
6673         u32 val, rdmac_mode;
6674         int i, err, limit;
6675
6676         tg3_disable_ints(tp);
6677
6678         tg3_stop_fw(tp);
6679
6680         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6681
6682         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6683                 tg3_abort_hw(tp, 1);
6684         }
6685
6686         if (reset_phy &&
6687             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6688                 tg3_phy_reset(tp);
6689
6690         err = tg3_chip_reset(tp);
6691         if (err)
6692                 return err;
6693
6694         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6695
6696         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6697                 val = tr32(TG3_CPMU_CTRL);
6698                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6699                 tw32(TG3_CPMU_CTRL, val);
6700
6701                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6702                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6703                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6704                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6705
6706                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6707                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6708                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6709                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6710
6711                 val = tr32(TG3_CPMU_HST_ACC);
6712                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6713                 val |= CPMU_HST_ACC_MACCLK_6_25;
6714                 tw32(TG3_CPMU_HST_ACC, val);
6715         }
6716
6717         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6718                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6719                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6720                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6721                 tw32(PCIE_PWR_MGMT_THRESH, val);
6722
6723                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6724                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6725
6726                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6727         }
6728
6729         /* This works around an issue with Athlon chipsets on
6730          * B3 tigon3 silicon.  This bit has no effect on any
6731          * other revision.  But do not set this on PCI Express
6732          * chips and don't even touch the clocks if the CPMU is present.
6733          */
6734         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6735                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6736                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6737                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6738         }
6739
6740         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6741             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6742                 val = tr32(TG3PCI_PCISTATE);
6743                 val |= PCISTATE_RETRY_SAME_DMA;
6744                 tw32(TG3PCI_PCISTATE, val);
6745         }
6746
6747         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6748                 /* Allow reads and writes to the
6749                  * APE register and memory space.
6750                  */
6751                 val = tr32(TG3PCI_PCISTATE);
6752                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6753                        PCISTATE_ALLOW_APE_SHMEM_WR;
6754                 tw32(TG3PCI_PCISTATE, val);
6755         }
6756
6757         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6758                 /* Enable some hw fixes.  */
6759                 val = tr32(TG3PCI_MSI_DATA);
6760                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6761                 tw32(TG3PCI_MSI_DATA, val);
6762         }
6763
6764         /* Descriptor ring init may make accesses to the
6765          * NIC SRAM area to setup the TX descriptors, so we
6766          * can only do this after the hardware has been
6767          * successfully reset.
6768          */
6769         err = tg3_init_rings(tp);
6770         if (err)
6771                 return err;
6772
6773         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6774             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6775                 /* This value is determined during the probe time DMA
6776                  * engine test, tg3_test_dma.
6777                  */
6778                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6779         }
6780
6781         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6782                           GRC_MODE_4X_NIC_SEND_RINGS |
6783                           GRC_MODE_NO_TX_PHDR_CSUM |
6784                           GRC_MODE_NO_RX_PHDR_CSUM);
6785         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6786
6787         /* Pseudo-header checksum is done by hardware logic and not
6788          * the offload processers, so make the chip do the pseudo-
6789          * header checksums on receive.  For transmit it is more
6790          * convenient to do the pseudo-header checksum in software
6791          * as Linux does that on transmit for us in all cases.
6792          */
6793         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6794
6795         tw32(GRC_MODE,
6796              tp->grc_mode |
6797              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6798
6799         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6800         val = tr32(GRC_MISC_CFG);
6801         val &= ~0xff;
6802         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6803         tw32(GRC_MISC_CFG, val);
6804
6805         /* Initialize MBUF/DESC pool. */
6806         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6807                 /* Do nothing.  */
6808         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6809                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6810                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6811                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6812                 else
6813                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6814                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6815                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6816         }
6817         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6818                 int fw_len;
6819
6820                 fw_len = tp->fw_len;
6821                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6822                 tw32(BUFMGR_MB_POOL_ADDR,
6823                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6824                 tw32(BUFMGR_MB_POOL_SIZE,
6825                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6826         }
6827
6828         if (tp->dev->mtu <= ETH_DATA_LEN) {
6829                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6830                      tp->bufmgr_config.mbuf_read_dma_low_water);
6831                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6832                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6833                 tw32(BUFMGR_MB_HIGH_WATER,
6834                      tp->bufmgr_config.mbuf_high_water);
6835         } else {
6836                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6837                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6838                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6839                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6840                 tw32(BUFMGR_MB_HIGH_WATER,
6841                      tp->bufmgr_config.mbuf_high_water_jumbo);
6842         }
6843         tw32(BUFMGR_DMA_LOW_WATER,
6844              tp->bufmgr_config.dma_low_water);
6845         tw32(BUFMGR_DMA_HIGH_WATER,
6846              tp->bufmgr_config.dma_high_water);
6847
6848         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6849         for (i = 0; i < 2000; i++) {
6850                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6851                         break;
6852                 udelay(10);
6853         }
6854         if (i >= 2000) {
6855                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6856                        tp->dev->name);
6857                 return -ENODEV;
6858         }
6859
6860         /* Setup replenish threshold. */
6861         val = tp->rx_pending / 8;
6862         if (val == 0)
6863                 val = 1;
6864         else if (val > tp->rx_std_max_post)
6865                 val = tp->rx_std_max_post;
6866         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6867                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6868                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6869
6870                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6871                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6872         }
6873
6874         tw32(RCVBDI_STD_THRESH, val);
6875
6876         /* Initialize TG3_BDINFO's at:
6877          *  RCVDBDI_STD_BD:     standard eth size rx ring
6878          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6879          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6880          *
6881          * like so:
6882          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6883          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6884          *                              ring attribute flags
6885          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6886          *
6887          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6888          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6889          *
6890          * The size of each ring is fixed in the firmware, but the location is
6891          * configurable.
6892          */
6893         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6894              ((u64) tp->rx_std_mapping >> 32));
6895         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6896              ((u64) tp->rx_std_mapping & 0xffffffff));
6897         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6898              NIC_SRAM_RX_BUFFER_DESC);
6899
6900         /* Don't even try to program the JUMBO/MINI buffer descriptor
6901          * configs on 5705.
6902          */
6903         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6904                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6905                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6906         } else {
6907                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6908                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6909
6910                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6911                      BDINFO_FLAGS_DISABLED);
6912
6913                 /* Setup replenish threshold. */
6914                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6915
6916                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6917                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6918                              ((u64) tp->rx_jumbo_mapping >> 32));
6919                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6920                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6921                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6922                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6923                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6924                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6925                 } else {
6926                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6927                              BDINFO_FLAGS_DISABLED);
6928                 }
6929
6930         }
6931
6932         /* There is only one send ring on 5705/5750, no need to explicitly
6933          * disable the others.
6934          */
6935         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6936                 /* Clear out send RCB ring in SRAM. */
6937                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6938                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6939                                       BDINFO_FLAGS_DISABLED);
6940         }
6941
6942         tp->tx_prod = 0;
6943         tp->tx_cons = 0;
6944         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6945         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6946
6947         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6948                        tp->tx_desc_mapping,
6949                        (TG3_TX_RING_SIZE <<
6950                         BDINFO_FLAGS_MAXLEN_SHIFT),
6951                        NIC_SRAM_TX_BUFFER_DESC);
6952
6953         /* There is only one receive return ring on 5705/5750, no need
6954          * to explicitly disable the others.
6955          */
6956         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6957                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6958                      i += TG3_BDINFO_SIZE) {
6959                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6960                                       BDINFO_FLAGS_DISABLED);
6961                 }
6962         }
6963
6964         tp->rx_rcb_ptr = 0;
6965         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6966
6967         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6968                        tp->rx_rcb_mapping,
6969                        (TG3_RX_RCB_RING_SIZE(tp) <<
6970                         BDINFO_FLAGS_MAXLEN_SHIFT),
6971                        0);
6972
6973         tp->rx_std_ptr = tp->rx_pending;
6974         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6975                      tp->rx_std_ptr);
6976
6977         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6978                                                 tp->rx_jumbo_pending : 0;
6979         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6980                      tp->rx_jumbo_ptr);
6981
6982         /* Initialize MAC address and backoff seed. */
6983         __tg3_set_mac_addr(tp, 0);
6984
6985         /* MTU + ethernet header + FCS + optional VLAN tag */
6986         tw32(MAC_RX_MTU_SIZE,
6987              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
6988
6989         /* The slot time is changed by tg3_setup_phy if we
6990          * run at gigabit with half duplex.
6991          */
6992         tw32(MAC_TX_LENGTHS,
6993              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6994              (6 << TX_LENGTHS_IPG_SHIFT) |
6995              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6996
6997         /* Receive rules. */
6998         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6999         tw32(RCVLPC_CONFIG, 0x0181);
7000
7001         /* Calculate RDMAC_MODE setting early, we need it to determine
7002          * the RCVLPC_STATE_ENABLE mask.
7003          */
7004         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7005                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7006                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7007                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7008                       RDMAC_MODE_LNGREAD_ENAB);
7009
7010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7013                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7014                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7015                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7016
7017         /* If statement applies to 5705 and 5750 PCI devices only */
7018         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7019              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7020             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7021                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7022                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7023                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7024                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7025                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7026                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7027                 }
7028         }
7029
7030         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7031                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7032
7033         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7034                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7035
7036         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7038                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7039
7040         /* Receive/send statistics. */
7041         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7042                 val = tr32(RCVLPC_STATS_ENABLE);
7043                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7044                 tw32(RCVLPC_STATS_ENABLE, val);
7045         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7046                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7047                 val = tr32(RCVLPC_STATS_ENABLE);
7048                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7049                 tw32(RCVLPC_STATS_ENABLE, val);
7050         } else {
7051                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7052         }
7053         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7054         tw32(SNDDATAI_STATSENAB, 0xffffff);
7055         tw32(SNDDATAI_STATSCTRL,
7056              (SNDDATAI_SCTRL_ENABLE |
7057               SNDDATAI_SCTRL_FASTUPD));
7058
7059         /* Setup host coalescing engine. */
7060         tw32(HOSTCC_MODE, 0);
7061         for (i = 0; i < 2000; i++) {
7062                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7063                         break;
7064                 udelay(10);
7065         }
7066
7067         __tg3_set_coalesce(tp, &tp->coal);
7068
7069         /* set status block DMA address */
7070         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7071              ((u64) tp->status_mapping >> 32));
7072         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7073              ((u64) tp->status_mapping & 0xffffffff));
7074
7075         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7076                 /* Status/statistics block address.  See tg3_timer,
7077                  * the tg3_periodic_fetch_stats call there, and
7078                  * tg3_get_stats to see how this works for 5705/5750 chips.
7079                  */
7080                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7081                      ((u64) tp->stats_mapping >> 32));
7082                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7083                      ((u64) tp->stats_mapping & 0xffffffff));
7084                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7085                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7086         }
7087
7088         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7089
7090         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7091         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7092         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7093                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7094
7095         /* Clear statistics/status block in chip, and status block in ram. */
7096         for (i = NIC_SRAM_STATS_BLK;
7097              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7098              i += sizeof(u32)) {
7099                 tg3_write_mem(tp, i, 0);
7100                 udelay(40);
7101         }
7102         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7103
7104         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7105                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7106                 /* reset to prevent losing 1st rx packet intermittently */
7107                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7108                 udelay(10);
7109         }
7110
7111         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7112                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7113         else
7114                 tp->mac_mode = 0;
7115         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7116                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7117         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7118             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7119             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7120                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7121         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7122         udelay(40);
7123
7124         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7125          * If TG3_FLG2_IS_NIC is zero, we should read the
7126          * register to preserve the GPIO settings for LOMs. The GPIOs,
7127          * whether used as inputs or outputs, are set by boot code after
7128          * reset.
7129          */
7130         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7131                 u32 gpio_mask;
7132
7133                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7134                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7135                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7136
7137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7138                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7139                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7140
7141                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7142                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7143
7144                 tp->grc_local_ctrl &= ~gpio_mask;
7145                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7146
7147                 /* GPIO1 must be driven high for eeprom write protect */
7148                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7149                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7150                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7151         }
7152         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7153         udelay(100);
7154
7155         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7156
7157         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7158                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7159                 udelay(40);
7160         }
7161
7162         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7163                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7164                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7165                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7166                WDMAC_MODE_LNGREAD_ENAB);
7167
7168         /* If statement applies to 5705 and 5750 PCI devices only */
7169         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7170              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7171             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7172                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7173                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7174                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7175                         /* nothing */
7176                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7177                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7178                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7179                         val |= WDMAC_MODE_RX_ACCEL;
7180                 }
7181         }
7182
7183         /* Enable host coalescing bug fix */
7184         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7185                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7186
7187         tw32_f(WDMAC_MODE, val);
7188         udelay(40);
7189
7190         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7191                 u16 pcix_cmd;
7192
7193                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7194                                      &pcix_cmd);
7195                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7196                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7197                         pcix_cmd |= PCI_X_CMD_READ_2K;
7198                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7199                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7200                         pcix_cmd |= PCI_X_CMD_READ_2K;
7201                 }
7202                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7203                                       pcix_cmd);
7204         }
7205
7206         tw32_f(RDMAC_MODE, rdmac_mode);
7207         udelay(40);
7208
7209         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7210         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7211                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7212
7213         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7214                 tw32(SNDDATAC_MODE,
7215                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7216         else
7217                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7218
7219         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7220         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7221         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7222         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7223         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7224                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7225         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7226         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7227
7228         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7229                 err = tg3_load_5701_a0_firmware_fix(tp);
7230                 if (err)
7231                         return err;
7232         }
7233
7234         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7235                 err = tg3_load_tso_firmware(tp);
7236                 if (err)
7237                         return err;
7238         }
7239
7240         tp->tx_mode = TX_MODE_ENABLE;
7241         tw32_f(MAC_TX_MODE, tp->tx_mode);
7242         udelay(100);
7243
7244         tp->rx_mode = RX_MODE_ENABLE;
7245         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7246                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7247
7248         tw32_f(MAC_RX_MODE, tp->rx_mode);
7249         udelay(10);
7250
7251         tw32(MAC_LED_CTRL, tp->led_ctrl);
7252
7253         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7254         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7255                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7256                 udelay(10);
7257         }
7258         tw32_f(MAC_RX_MODE, tp->rx_mode);
7259         udelay(10);
7260
7261         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7262                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7263                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7264                         /* Set drive transmission level to 1.2V  */
7265                         /* only if the signal pre-emphasis bit is not set  */
7266                         val = tr32(MAC_SERDES_CFG);
7267                         val &= 0xfffff000;
7268                         val |= 0x880;
7269                         tw32(MAC_SERDES_CFG, val);
7270                 }
7271                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7272                         tw32(MAC_SERDES_CFG, 0x616000);
7273         }
7274
7275         /* Prevent chip from dropping frames when flow control
7276          * is enabled.
7277          */
7278         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7279
7280         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7281             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7282                 /* Use hardware link auto-negotiation */
7283                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7284         }
7285
7286         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7287             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7288                 u32 tmp;
7289
7290                 tmp = tr32(SERDES_RX_CTRL);
7291                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7292                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7293                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7294                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7295         }
7296
7297         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7298                 if (tp->link_config.phy_is_low_power) {
7299                         tp->link_config.phy_is_low_power = 0;
7300                         tp->link_config.speed = tp->link_config.orig_speed;
7301                         tp->link_config.duplex = tp->link_config.orig_duplex;
7302                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7303                 }
7304
7305                 err = tg3_setup_phy(tp, 0);
7306                 if (err)
7307                         return err;
7308
7309                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7310                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7311                         u32 tmp;
7312
7313                         /* Clear CRC stats. */
7314                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7315                                 tg3_writephy(tp, MII_TG3_TEST1,
7316                                              tmp | MII_TG3_TEST1_CRC_EN);
7317                                 tg3_readphy(tp, 0x14, &tmp);
7318                         }
7319                 }
7320         }
7321
7322         __tg3_set_rx_mode(tp->dev);
7323
7324         /* Initialize receive rules. */
7325         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7326         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7327         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7328         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7329
7330         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7331             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7332                 limit = 8;
7333         else
7334                 limit = 16;
7335         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7336                 limit -= 4;
7337         switch (limit) {
7338         case 16:
7339                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7340         case 15:
7341                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7342         case 14:
7343                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7344         case 13:
7345                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7346         case 12:
7347                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7348         case 11:
7349                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7350         case 10:
7351                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7352         case 9:
7353                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7354         case 8:
7355                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7356         case 7:
7357                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7358         case 6:
7359                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7360         case 5:
7361                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7362         case 4:
7363                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7364         case 3:
7365                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7366         case 2:
7367         case 1:
7368
7369         default:
7370                 break;
7371         }
7372
7373         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7374                 /* Write our heartbeat update interval to APE. */
7375                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7376                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7377
7378         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7379
7380         return 0;
7381 }
7382
7383 /* Called at device open time to get the chip ready for
7384  * packet processing.  Invoked with tp->lock held.
7385  */
7386 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7387 {
7388         tg3_switch_clocks(tp);
7389
7390         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7391
7392         return tg3_reset_hw(tp, reset_phy);
7393 }
7394
7395 #define TG3_STAT_ADD32(PSTAT, REG) \
7396 do {    u32 __val = tr32(REG); \
7397         (PSTAT)->low += __val; \
7398         if ((PSTAT)->low < __val) \
7399                 (PSTAT)->high += 1; \
7400 } while (0)
7401
7402 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7403 {
7404         struct tg3_hw_stats *sp = tp->hw_stats;
7405
7406         if (!netif_carrier_ok(tp->dev))
7407                 return;
7408
7409         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7410         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7411         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7412         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7413         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7414         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7415         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7416         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7417         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7418         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7419         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7420         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7421         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7422
7423         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7424         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7425         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7426         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7427         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7428         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7429         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7430         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7431         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7432         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7433         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7434         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7435         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7436         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7437
7438         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7439         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7440         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7441 }
7442
7443 static void tg3_timer(unsigned long __opaque)
7444 {
7445         struct tg3 *tp = (struct tg3 *) __opaque;
7446
7447         if (tp->irq_sync)
7448                 goto restart_timer;
7449
7450         spin_lock(&tp->lock);
7451
7452         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7453                 /* All of this garbage is because when using non-tagged
7454                  * IRQ status the mailbox/status_block protocol the chip
7455                  * uses with the cpu is race prone.
7456                  */
7457                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7458                         tw32(GRC_LOCAL_CTRL,
7459                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7460                 } else {
7461                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7462                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7463                 }
7464
7465                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7466                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7467                         spin_unlock(&tp->lock);
7468                         schedule_work(&tp->reset_task);
7469                         return;
7470                 }
7471         }
7472
7473         /* This part only runs once per second. */
7474         if (!--tp->timer_counter) {
7475                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7476                         tg3_periodic_fetch_stats(tp);
7477
7478                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7479                         u32 mac_stat;
7480                         int phy_event;
7481
7482                         mac_stat = tr32(MAC_STATUS);
7483
7484                         phy_event = 0;
7485                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7486                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7487                                         phy_event = 1;
7488                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7489                                 phy_event = 1;
7490
7491                         if (phy_event)
7492                                 tg3_setup_phy(tp, 0);
7493                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7494                         u32 mac_stat = tr32(MAC_STATUS);
7495                         int need_setup = 0;
7496
7497                         if (netif_carrier_ok(tp->dev) &&
7498                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7499                                 need_setup = 1;
7500                         }
7501                         if (! netif_carrier_ok(tp->dev) &&
7502                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7503                                          MAC_STATUS_SIGNAL_DET))) {
7504                                 need_setup = 1;
7505                         }
7506                         if (need_setup) {
7507                                 if (!tp->serdes_counter) {
7508                                         tw32_f(MAC_MODE,
7509                                              (tp->mac_mode &
7510                                               ~MAC_MODE_PORT_MODE_MASK));
7511                                         udelay(40);
7512                                         tw32_f(MAC_MODE, tp->mac_mode);
7513                                         udelay(40);
7514                                 }
7515                                 tg3_setup_phy(tp, 0);
7516                         }
7517                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7518                         tg3_serdes_parallel_detect(tp);
7519
7520                 tp->timer_counter = tp->timer_multiplier;
7521         }
7522
7523         /* Heartbeat is only sent once every 2 seconds.
7524          *
7525          * The heartbeat is to tell the ASF firmware that the host
7526          * driver is still alive.  In the event that the OS crashes,
7527          * ASF needs to reset the hardware to free up the FIFO space
7528          * that may be filled with rx packets destined for the host.
7529          * If the FIFO is full, ASF will no longer function properly.
7530          *
7531          * Unintended resets have been reported on real time kernels
7532          * where the timer doesn't run on time.  Netpoll will also have
7533          * same problem.
7534          *
7535          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7536          * to check the ring condition when the heartbeat is expiring
7537          * before doing the reset.  This will prevent most unintended
7538          * resets.
7539          */
7540         if (!--tp->asf_counter) {
7541                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7542                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7543                         tg3_wait_for_event_ack(tp);
7544
7545                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7546                                       FWCMD_NICDRV_ALIVE3);
7547                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7548                         /* 5 seconds timeout */
7549                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7550
7551                         tg3_generate_fw_event(tp);
7552                 }
7553                 tp->asf_counter = tp->asf_multiplier;
7554         }
7555
7556         spin_unlock(&tp->lock);
7557
7558 restart_timer:
7559         tp->timer.expires = jiffies + tp->timer_offset;
7560         add_timer(&tp->timer);
7561 }
7562
7563 static int tg3_request_irq(struct tg3 *tp)
7564 {
7565         irq_handler_t fn;
7566         unsigned long flags;
7567         struct net_device *dev = tp->dev;
7568
7569         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7570                 fn = tg3_msi;
7571                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7572                         fn = tg3_msi_1shot;
7573                 flags = IRQF_SAMPLE_RANDOM;
7574         } else {
7575                 fn = tg3_interrupt;
7576                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7577                         fn = tg3_interrupt_tagged;
7578                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7579         }
7580         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7581 }
7582
7583 static int tg3_test_interrupt(struct tg3 *tp)
7584 {
7585         struct net_device *dev = tp->dev;
7586         int err, i, intr_ok = 0;
7587
7588         if (!netif_running(dev))
7589                 return -ENODEV;
7590
7591         tg3_disable_ints(tp);
7592
7593         free_irq(tp->pdev->irq, dev);
7594
7595         err = request_irq(tp->pdev->irq, tg3_test_isr,
7596                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7597         if (err)
7598                 return err;
7599
7600         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7601         tg3_enable_ints(tp);
7602
7603         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7604                HOSTCC_MODE_NOW);
7605
7606         for (i = 0; i < 5; i++) {
7607                 u32 int_mbox, misc_host_ctrl;
7608
7609                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7610                                         TG3_64BIT_REG_LOW);
7611                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7612
7613                 if ((int_mbox != 0) ||
7614                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7615                         intr_ok = 1;
7616                         break;
7617                 }
7618
7619                 msleep(10);
7620         }
7621
7622         tg3_disable_ints(tp);
7623
7624         free_irq(tp->pdev->irq, dev);
7625
7626         err = tg3_request_irq(tp);
7627
7628         if (err)
7629                 return err;
7630
7631         if (intr_ok)
7632                 return 0;
7633
7634         return -EIO;
7635 }
7636
7637 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7638  * successfully restored
7639  */
7640 static int tg3_test_msi(struct tg3 *tp)
7641 {
7642         struct net_device *dev = tp->dev;
7643         int err;
7644         u16 pci_cmd;
7645
7646         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7647                 return 0;
7648
7649         /* Turn off SERR reporting in case MSI terminates with Master
7650          * Abort.
7651          */
7652         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7653         pci_write_config_word(tp->pdev, PCI_COMMAND,
7654                               pci_cmd & ~PCI_COMMAND_SERR);
7655
7656         err = tg3_test_interrupt(tp);
7657
7658         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7659
7660         if (!err)
7661                 return 0;
7662
7663         /* other failures */
7664         if (err != -EIO)
7665                 return err;
7666
7667         /* MSI test failed, go back to INTx mode */
7668         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7669                "switching to INTx mode. Please report this failure to "
7670                "the PCI maintainer and include system chipset information.\n",
7671                        tp->dev->name);
7672
7673         free_irq(tp->pdev->irq, dev);
7674         pci_disable_msi(tp->pdev);
7675
7676         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7677
7678         err = tg3_request_irq(tp);
7679         if (err)
7680                 return err;
7681
7682         /* Need to reset the chip because the MSI cycle may have terminated
7683          * with Master Abort.
7684          */
7685         tg3_full_lock(tp, 1);
7686
7687         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7688         err = tg3_init_hw(tp, 1);
7689
7690         tg3_full_unlock(tp);
7691
7692         if (err)
7693                 free_irq(tp->pdev->irq, dev);
7694
7695         return err;
7696 }
7697
7698 static int tg3_request_firmware(struct tg3 *tp)
7699 {
7700         const __be32 *fw_data;
7701
7702         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7703                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7704                        tp->dev->name, tp->fw_needed);
7705                 return -ENOENT;
7706         }
7707
7708         fw_data = (void *)tp->fw->data;
7709
7710         /* Firmware blob starts with version numbers, followed by
7711          * start address and _full_ length including BSS sections
7712          * (which must be longer than the actual data, of course
7713          */
7714
7715         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7716         if (tp->fw_len < (tp->fw->size - 12)) {
7717                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7718                        tp->dev->name, tp->fw_len, tp->fw_needed);
7719                 release_firmware(tp->fw);
7720                 tp->fw = NULL;
7721                 return -EINVAL;
7722         }
7723
7724         /* We no longer need firmware; we have it. */
7725         tp->fw_needed = NULL;
7726         return 0;
7727 }
7728
7729 static int tg3_open(struct net_device *dev)
7730 {
7731         struct tg3 *tp = netdev_priv(dev);
7732         int err;
7733
7734         if (tp->fw_needed) {
7735                 err = tg3_request_firmware(tp);
7736                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7737                         if (err)
7738                                 return err;
7739                 } else if (err) {
7740                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7741                                tp->dev->name);
7742                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7743                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7744                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7745                                tp->dev->name);
7746                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7747                 }
7748         }
7749
7750         netif_carrier_off(tp->dev);
7751
7752         err = tg3_set_power_state(tp, PCI_D0);
7753         if (err)
7754                 return err;
7755
7756         tg3_full_lock(tp, 0);
7757
7758         tg3_disable_ints(tp);
7759         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7760
7761         tg3_full_unlock(tp);
7762
7763         /* The placement of this call is tied
7764          * to the setup and use of Host TX descriptors.
7765          */
7766         err = tg3_alloc_consistent(tp);
7767         if (err)
7768                 return err;
7769
7770         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7771                 /* All MSI supporting chips should support tagged
7772                  * status.  Assert that this is the case.
7773                  */
7774                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7775                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7776                                "Not using MSI.\n", tp->dev->name);
7777                 } else if (pci_enable_msi(tp->pdev) == 0) {
7778                         u32 msi_mode;
7779
7780                         msi_mode = tr32(MSGINT_MODE);
7781                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7782                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7783                 }
7784         }
7785         err = tg3_request_irq(tp);
7786
7787         if (err) {
7788                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7789                         pci_disable_msi(tp->pdev);
7790                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7791                 }
7792                 tg3_free_consistent(tp);
7793                 return err;
7794         }
7795
7796         napi_enable(&tp->napi);
7797
7798         tg3_full_lock(tp, 0);
7799
7800         err = tg3_init_hw(tp, 1);
7801         if (err) {
7802                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7803                 tg3_free_rings(tp);
7804         } else {
7805                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7806                         tp->timer_offset = HZ;
7807                 else
7808                         tp->timer_offset = HZ / 10;
7809
7810                 BUG_ON(tp->timer_offset > HZ);
7811                 tp->timer_counter = tp->timer_multiplier =
7812                         (HZ / tp->timer_offset);
7813                 tp->asf_counter = tp->asf_multiplier =
7814                         ((HZ / tp->timer_offset) * 2);
7815
7816                 init_timer(&tp->timer);
7817                 tp->timer.expires = jiffies + tp->timer_offset;
7818                 tp->timer.data = (unsigned long) tp;
7819                 tp->timer.function = tg3_timer;
7820         }
7821
7822         tg3_full_unlock(tp);
7823
7824         if (err) {
7825                 napi_disable(&tp->napi);
7826                 free_irq(tp->pdev->irq, dev);
7827                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7828                         pci_disable_msi(tp->pdev);
7829                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7830                 }
7831                 tg3_free_consistent(tp);
7832                 return err;
7833         }
7834
7835         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7836                 err = tg3_test_msi(tp);
7837
7838                 if (err) {
7839                         tg3_full_lock(tp, 0);
7840
7841                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7842                                 pci_disable_msi(tp->pdev);
7843                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7844                         }
7845                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7846                         tg3_free_rings(tp);
7847                         tg3_free_consistent(tp);
7848
7849                         tg3_full_unlock(tp);
7850
7851                         napi_disable(&tp->napi);
7852
7853                         return err;
7854                 }
7855
7856                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7857                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7858                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7859
7860                                 tw32(PCIE_TRANSACTION_CFG,
7861                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7862                         }
7863                 }
7864         }
7865
7866         tg3_phy_start(tp);
7867
7868         tg3_full_lock(tp, 0);
7869
7870         add_timer(&tp->timer);
7871         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7872         tg3_enable_ints(tp);
7873
7874         tg3_full_unlock(tp);
7875
7876         netif_start_queue(dev);
7877
7878         return 0;
7879 }
7880
7881 #if 0
7882 /*static*/ void tg3_dump_state(struct tg3 *tp)
7883 {
7884         u32 val32, val32_2, val32_3, val32_4, val32_5;
7885         u16 val16;
7886         int i;
7887
7888         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7889         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7890         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7891                val16, val32);
7892
7893         /* MAC block */
7894         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7895                tr32(MAC_MODE), tr32(MAC_STATUS));
7896         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7897                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7898         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7899                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7900         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7901                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7902
7903         /* Send data initiator control block */
7904         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7905                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7906         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7907                tr32(SNDDATAI_STATSCTRL));
7908
7909         /* Send data completion control block */
7910         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7911
7912         /* Send BD ring selector block */
7913         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7914                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7915
7916         /* Send BD initiator control block */
7917         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7918                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7919
7920         /* Send BD completion control block */
7921         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7922
7923         /* Receive list placement control block */
7924         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7925                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7926         printk("       RCVLPC_STATSCTRL[%08x]\n",
7927                tr32(RCVLPC_STATSCTRL));
7928
7929         /* Receive data and receive BD initiator control block */
7930         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7931                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7932
7933         /* Receive data completion control block */
7934         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7935                tr32(RCVDCC_MODE));
7936
7937         /* Receive BD initiator control block */
7938         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7939                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7940
7941         /* Receive BD completion control block */
7942         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7943                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7944
7945         /* Receive list selector control block */
7946         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7947                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7948
7949         /* Mbuf cluster free block */
7950         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7951                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7952
7953         /* Host coalescing control block */
7954         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7955                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7956         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7957                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7958                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7959         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7960                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7961                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7962         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7963                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7964         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7965                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7966
7967         /* Memory arbiter control block */
7968         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7969                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7970
7971         /* Buffer manager control block */
7972         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7973                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7974         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7975                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7976         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7977                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7978                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7979                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7980
7981         /* Read DMA control block */
7982         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7983                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7984
7985         /* Write DMA control block */
7986         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7987                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7988
7989         /* DMA completion block */
7990         printk("DEBUG: DMAC_MODE[%08x]\n",
7991                tr32(DMAC_MODE));
7992
7993         /* GRC block */
7994         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7995                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7996         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7997                tr32(GRC_LOCAL_CTRL));
7998
7999         /* TG3_BDINFOs */
8000         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8001                tr32(RCVDBDI_JUMBO_BD + 0x0),
8002                tr32(RCVDBDI_JUMBO_BD + 0x4),
8003                tr32(RCVDBDI_JUMBO_BD + 0x8),
8004                tr32(RCVDBDI_JUMBO_BD + 0xc));
8005         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8006                tr32(RCVDBDI_STD_BD + 0x0),
8007                tr32(RCVDBDI_STD_BD + 0x4),
8008                tr32(RCVDBDI_STD_BD + 0x8),
8009                tr32(RCVDBDI_STD_BD + 0xc));
8010         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8011                tr32(RCVDBDI_MINI_BD + 0x0),
8012                tr32(RCVDBDI_MINI_BD + 0x4),
8013                tr32(RCVDBDI_MINI_BD + 0x8),
8014                tr32(RCVDBDI_MINI_BD + 0xc));
8015
8016         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8017         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8018         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8019         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8020         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8021                val32, val32_2, val32_3, val32_4);
8022
8023         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8024         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8025         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8026         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8027         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8028                val32, val32_2, val32_3, val32_4);
8029
8030         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8031         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8032         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8033         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8034         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8035         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8036                val32, val32_2, val32_3, val32_4, val32_5);
8037
8038         /* SW status block */
8039         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8040                tp->hw_status->status,
8041                tp->hw_status->status_tag,
8042                tp->hw_status->rx_jumbo_consumer,
8043                tp->hw_status->rx_consumer,
8044                tp->hw_status->rx_mini_consumer,
8045                tp->hw_status->idx[0].rx_producer,
8046                tp->hw_status->idx[0].tx_consumer);
8047
8048         /* SW statistics block */
8049         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8050                ((u32 *)tp->hw_stats)[0],
8051                ((u32 *)tp->hw_stats)[1],
8052                ((u32 *)tp->hw_stats)[2],
8053                ((u32 *)tp->hw_stats)[3]);
8054
8055         /* Mailboxes */
8056         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8057                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8058                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8059                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8060                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8061
8062         /* NIC side send descriptors. */
8063         for (i = 0; i < 6; i++) {
8064                 unsigned long txd;
8065
8066                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8067                         + (i * sizeof(struct tg3_tx_buffer_desc));
8068                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8069                        i,
8070                        readl(txd + 0x0), readl(txd + 0x4),
8071                        readl(txd + 0x8), readl(txd + 0xc));
8072         }
8073
8074         /* NIC side RX descriptors. */
8075         for (i = 0; i < 6; i++) {
8076                 unsigned long rxd;
8077
8078                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8079                         + (i * sizeof(struct tg3_rx_buffer_desc));
8080                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8081                        i,
8082                        readl(rxd + 0x0), readl(rxd + 0x4),
8083                        readl(rxd + 0x8), readl(rxd + 0xc));
8084                 rxd += (4 * sizeof(u32));
8085                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8086                        i,
8087                        readl(rxd + 0x0), readl(rxd + 0x4),
8088                        readl(rxd + 0x8), readl(rxd + 0xc));
8089         }
8090
8091         for (i = 0; i < 6; i++) {
8092                 unsigned long rxd;
8093
8094                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8095                         + (i * sizeof(struct tg3_rx_buffer_desc));
8096                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8097                        i,
8098                        readl(rxd + 0x0), readl(rxd + 0x4),
8099                        readl(rxd + 0x8), readl(rxd + 0xc));
8100                 rxd += (4 * sizeof(u32));
8101                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8102                        i,
8103                        readl(rxd + 0x0), readl(rxd + 0x4),
8104                        readl(rxd + 0x8), readl(rxd + 0xc));
8105         }
8106 }
8107 #endif
8108
8109 static struct net_device_stats *tg3_get_stats(struct net_device *);
8110 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8111
8112 static int tg3_close(struct net_device *dev)
8113 {
8114         struct tg3 *tp = netdev_priv(dev);
8115
8116         napi_disable(&tp->napi);
8117         cancel_work_sync(&tp->reset_task);
8118
8119         netif_stop_queue(dev);
8120
8121         del_timer_sync(&tp->timer);
8122
8123         tg3_full_lock(tp, 1);
8124 #if 0
8125         tg3_dump_state(tp);
8126 #endif
8127
8128         tg3_disable_ints(tp);
8129
8130         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8131         tg3_free_rings(tp);
8132         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8133
8134         tg3_full_unlock(tp);
8135
8136         free_irq(tp->pdev->irq, dev);
8137         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8138                 pci_disable_msi(tp->pdev);
8139                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8140         }
8141
8142         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8143                sizeof(tp->net_stats_prev));
8144         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8145                sizeof(tp->estats_prev));
8146
8147         tg3_free_consistent(tp);
8148
8149         tg3_set_power_state(tp, PCI_D3hot);
8150
8151         netif_carrier_off(tp->dev);
8152
8153         return 0;
8154 }
8155
8156 static inline unsigned long get_stat64(tg3_stat64_t *val)
8157 {
8158         unsigned long ret;
8159
8160 #if (BITS_PER_LONG == 32)
8161         ret = val->low;
8162 #else
8163         ret = ((u64)val->high << 32) | ((u64)val->low);
8164 #endif
8165         return ret;
8166 }
8167
8168 static inline u64 get_estat64(tg3_stat64_t *val)
8169 {
8170        return ((u64)val->high << 32) | ((u64)val->low);
8171 }
8172
8173 static unsigned long calc_crc_errors(struct tg3 *tp)
8174 {
8175         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8176
8177         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8178             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8179              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8180                 u32 val;
8181
8182                 spin_lock_bh(&tp->lock);
8183                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8184                         tg3_writephy(tp, MII_TG3_TEST1,
8185                                      val | MII_TG3_TEST1_CRC_EN);
8186                         tg3_readphy(tp, 0x14, &val);
8187                 } else
8188                         val = 0;
8189                 spin_unlock_bh(&tp->lock);
8190
8191                 tp->phy_crc_errors += val;
8192
8193                 return tp->phy_crc_errors;
8194         }
8195
8196         return get_stat64(&hw_stats->rx_fcs_errors);
8197 }
8198
8199 #define ESTAT_ADD(member) \
8200         estats->member =        old_estats->member + \
8201                                 get_estat64(&hw_stats->member)
8202
8203 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8204 {
8205         struct tg3_ethtool_stats *estats = &tp->estats;
8206         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8207         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8208
8209         if (!hw_stats)
8210                 return old_estats;
8211
8212         ESTAT_ADD(rx_octets);
8213         ESTAT_ADD(rx_fragments);
8214         ESTAT_ADD(rx_ucast_packets);
8215         ESTAT_ADD(rx_mcast_packets);
8216         ESTAT_ADD(rx_bcast_packets);
8217         ESTAT_ADD(rx_fcs_errors);
8218         ESTAT_ADD(rx_align_errors);
8219         ESTAT_ADD(rx_xon_pause_rcvd);
8220         ESTAT_ADD(rx_xoff_pause_rcvd);
8221         ESTAT_ADD(rx_mac_ctrl_rcvd);
8222         ESTAT_ADD(rx_xoff_entered);
8223         ESTAT_ADD(rx_frame_too_long_errors);
8224         ESTAT_ADD(rx_jabbers);
8225         ESTAT_ADD(rx_undersize_packets);
8226         ESTAT_ADD(rx_in_length_errors);
8227         ESTAT_ADD(rx_out_length_errors);
8228         ESTAT_ADD(rx_64_or_less_octet_packets);
8229         ESTAT_ADD(rx_65_to_127_octet_packets);
8230         ESTAT_ADD(rx_128_to_255_octet_packets);
8231         ESTAT_ADD(rx_256_to_511_octet_packets);
8232         ESTAT_ADD(rx_512_to_1023_octet_packets);
8233         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8234         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8235         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8236         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8237         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8238
8239         ESTAT_ADD(tx_octets);
8240         ESTAT_ADD(tx_collisions);
8241         ESTAT_ADD(tx_xon_sent);
8242         ESTAT_ADD(tx_xoff_sent);
8243         ESTAT_ADD(tx_flow_control);
8244         ESTAT_ADD(tx_mac_errors);
8245         ESTAT_ADD(tx_single_collisions);
8246         ESTAT_ADD(tx_mult_collisions);
8247         ESTAT_ADD(tx_deferred);
8248         ESTAT_ADD(tx_excessive_collisions);
8249         ESTAT_ADD(tx_late_collisions);
8250         ESTAT_ADD(tx_collide_2times);
8251         ESTAT_ADD(tx_collide_3times);
8252         ESTAT_ADD(tx_collide_4times);
8253         ESTAT_ADD(tx_collide_5times);
8254         ESTAT_ADD(tx_collide_6times);
8255         ESTAT_ADD(tx_collide_7times);
8256         ESTAT_ADD(tx_collide_8times);
8257         ESTAT_ADD(tx_collide_9times);
8258         ESTAT_ADD(tx_collide_10times);
8259         ESTAT_ADD(tx_collide_11times);
8260         ESTAT_ADD(tx_collide_12times);
8261         ESTAT_ADD(tx_collide_13times);
8262         ESTAT_ADD(tx_collide_14times);
8263         ESTAT_ADD(tx_collide_15times);
8264         ESTAT_ADD(tx_ucast_packets);
8265         ESTAT_ADD(tx_mcast_packets);
8266         ESTAT_ADD(tx_bcast_packets);
8267         ESTAT_ADD(tx_carrier_sense_errors);
8268         ESTAT_ADD(tx_discards);
8269         ESTAT_ADD(tx_errors);
8270
8271         ESTAT_ADD(dma_writeq_full);
8272         ESTAT_ADD(dma_write_prioq_full);
8273         ESTAT_ADD(rxbds_empty);
8274         ESTAT_ADD(rx_discards);
8275         ESTAT_ADD(rx_errors);
8276         ESTAT_ADD(rx_threshold_hit);
8277
8278         ESTAT_ADD(dma_readq_full);
8279         ESTAT_ADD(dma_read_prioq_full);
8280         ESTAT_ADD(tx_comp_queue_full);
8281
8282         ESTAT_ADD(ring_set_send_prod_index);
8283         ESTAT_ADD(ring_status_update);
8284         ESTAT_ADD(nic_irqs);
8285         ESTAT_ADD(nic_avoided_irqs);
8286         ESTAT_ADD(nic_tx_threshold_hit);
8287
8288         return estats;
8289 }
8290
8291 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8292 {
8293         struct tg3 *tp = netdev_priv(dev);
8294         struct net_device_stats *stats = &tp->net_stats;
8295         struct net_device_stats *old_stats = &tp->net_stats_prev;
8296         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8297
8298         if (!hw_stats)
8299                 return old_stats;
8300
8301         stats->rx_packets = old_stats->rx_packets +
8302                 get_stat64(&hw_stats->rx_ucast_packets) +
8303                 get_stat64(&hw_stats->rx_mcast_packets) +
8304                 get_stat64(&hw_stats->rx_bcast_packets);
8305
8306         stats->tx_packets = old_stats->tx_packets +
8307                 get_stat64(&hw_stats->tx_ucast_packets) +
8308                 get_stat64(&hw_stats->tx_mcast_packets) +
8309                 get_stat64(&hw_stats->tx_bcast_packets);
8310
8311         stats->rx_bytes = old_stats->rx_bytes +
8312                 get_stat64(&hw_stats->rx_octets);
8313         stats->tx_bytes = old_stats->tx_bytes +
8314                 get_stat64(&hw_stats->tx_octets);
8315
8316         stats->rx_errors = old_stats->rx_errors +
8317                 get_stat64(&hw_stats->rx_errors);
8318         stats->tx_errors = old_stats->tx_errors +
8319                 get_stat64(&hw_stats->tx_errors) +
8320                 get_stat64(&hw_stats->tx_mac_errors) +
8321                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8322                 get_stat64(&hw_stats->tx_discards);
8323
8324         stats->multicast = old_stats->multicast +
8325                 get_stat64(&hw_stats->rx_mcast_packets);
8326         stats->collisions = old_stats->collisions +
8327                 get_stat64(&hw_stats->tx_collisions);
8328
8329         stats->rx_length_errors = old_stats->rx_length_errors +
8330                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8331                 get_stat64(&hw_stats->rx_undersize_packets);
8332
8333         stats->rx_over_errors = old_stats->rx_over_errors +
8334                 get_stat64(&hw_stats->rxbds_empty);
8335         stats->rx_frame_errors = old_stats->rx_frame_errors +
8336                 get_stat64(&hw_stats->rx_align_errors);
8337         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8338                 get_stat64(&hw_stats->tx_discards);
8339         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8340                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8341
8342         stats->rx_crc_errors = old_stats->rx_crc_errors +
8343                 calc_crc_errors(tp);
8344
8345         stats->rx_missed_errors = old_stats->rx_missed_errors +
8346                 get_stat64(&hw_stats->rx_discards);
8347
8348         return stats;
8349 }
8350
8351 static inline u32 calc_crc(unsigned char *buf, int len)
8352 {
8353         u32 reg;
8354         u32 tmp;
8355         int j, k;
8356
8357         reg = 0xffffffff;
8358
8359         for (j = 0; j < len; j++) {
8360                 reg ^= buf[j];
8361
8362                 for (k = 0; k < 8; k++) {
8363                         tmp = reg & 0x01;
8364
8365                         reg >>= 1;
8366
8367                         if (tmp) {
8368                                 reg ^= 0xedb88320;
8369                         }
8370                 }
8371         }
8372
8373         return ~reg;
8374 }
8375
8376 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8377 {
8378         /* accept or reject all multicast frames */
8379         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8380         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8381         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8382         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8383 }
8384
8385 static void __tg3_set_rx_mode(struct net_device *dev)
8386 {
8387         struct tg3 *tp = netdev_priv(dev);
8388         u32 rx_mode;
8389
8390         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8391                                   RX_MODE_KEEP_VLAN_TAG);
8392
8393         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8394          * flag clear.
8395          */
8396 #if TG3_VLAN_TAG_USED
8397         if (!tp->vlgrp &&
8398             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8399                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8400 #else
8401         /* By definition, VLAN is disabled always in this
8402          * case.
8403          */
8404         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8405                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8406 #endif
8407
8408         if (dev->flags & IFF_PROMISC) {
8409                 /* Promiscuous mode. */
8410                 rx_mode |= RX_MODE_PROMISC;
8411         } else if (dev->flags & IFF_ALLMULTI) {
8412                 /* Accept all multicast. */
8413                 tg3_set_multi (tp, 1);
8414         } else if (dev->mc_count < 1) {
8415                 /* Reject all multicast. */
8416                 tg3_set_multi (tp, 0);
8417         } else {
8418                 /* Accept one or more multicast(s). */
8419                 struct dev_mc_list *mclist;
8420                 unsigned int i;
8421                 u32 mc_filter[4] = { 0, };
8422                 u32 regidx;
8423                 u32 bit;
8424                 u32 crc;
8425
8426                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8427                      i++, mclist = mclist->next) {
8428
8429                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8430                         bit = ~crc & 0x7f;
8431                         regidx = (bit & 0x60) >> 5;
8432                         bit &= 0x1f;
8433                         mc_filter[regidx] |= (1 << bit);
8434                 }
8435
8436                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8437                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8438                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8439                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8440         }
8441
8442         if (rx_mode != tp->rx_mode) {
8443                 tp->rx_mode = rx_mode;
8444                 tw32_f(MAC_RX_MODE, rx_mode);
8445                 udelay(10);
8446         }
8447 }
8448
8449 static void tg3_set_rx_mode(struct net_device *dev)
8450 {
8451         struct tg3 *tp = netdev_priv(dev);
8452
8453         if (!netif_running(dev))
8454                 return;
8455
8456         tg3_full_lock(tp, 0);
8457         __tg3_set_rx_mode(dev);
8458         tg3_full_unlock(tp);
8459 }
8460
8461 #define TG3_REGDUMP_LEN         (32 * 1024)
8462
8463 static int tg3_get_regs_len(struct net_device *dev)
8464 {
8465         return TG3_REGDUMP_LEN;
8466 }
8467
8468 static void tg3_get_regs(struct net_device *dev,
8469                 struct ethtool_regs *regs, void *_p)
8470 {
8471         u32 *p = _p;
8472         struct tg3 *tp = netdev_priv(dev);
8473         u8 *orig_p = _p;
8474         int i;
8475
8476         regs->version = 0;
8477
8478         memset(p, 0, TG3_REGDUMP_LEN);
8479
8480         if (tp->link_config.phy_is_low_power)
8481                 return;
8482
8483         tg3_full_lock(tp, 0);
8484
8485 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8486 #define GET_REG32_LOOP(base,len)                \
8487 do {    p = (u32 *)(orig_p + (base));           \
8488         for (i = 0; i < len; i += 4)            \
8489                 __GET_REG32((base) + i);        \
8490 } while (0)
8491 #define GET_REG32_1(reg)                        \
8492 do {    p = (u32 *)(orig_p + (reg));            \
8493         __GET_REG32((reg));                     \
8494 } while (0)
8495
8496         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8497         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8498         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8499         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8500         GET_REG32_1(SNDDATAC_MODE);
8501         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8502         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8503         GET_REG32_1(SNDBDC_MODE);
8504         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8505         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8506         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8507         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8508         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8509         GET_REG32_1(RCVDCC_MODE);
8510         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8511         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8512         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8513         GET_REG32_1(MBFREE_MODE);
8514         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8515         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8516         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8517         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8518         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8519         GET_REG32_1(RX_CPU_MODE);
8520         GET_REG32_1(RX_CPU_STATE);
8521         GET_REG32_1(RX_CPU_PGMCTR);
8522         GET_REG32_1(RX_CPU_HWBKPT);
8523         GET_REG32_1(TX_CPU_MODE);
8524         GET_REG32_1(TX_CPU_STATE);
8525         GET_REG32_1(TX_CPU_PGMCTR);
8526         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8527         GET_REG32_LOOP(FTQ_RESET, 0x120);
8528         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8529         GET_REG32_1(DMAC_MODE);
8530         GET_REG32_LOOP(GRC_MODE, 0x4c);
8531         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8532                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8533
8534 #undef __GET_REG32
8535 #undef GET_REG32_LOOP
8536 #undef GET_REG32_1
8537
8538         tg3_full_unlock(tp);
8539 }
8540
8541 static int tg3_get_eeprom_len(struct net_device *dev)
8542 {
8543         struct tg3 *tp = netdev_priv(dev);
8544
8545         return tp->nvram_size;
8546 }
8547
8548 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8549 {
8550         struct tg3 *tp = netdev_priv(dev);
8551         int ret;
8552         u8  *pd;
8553         u32 i, offset, len, b_offset, b_count;
8554         __be32 val;
8555
8556         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8557                 return -EINVAL;
8558
8559         if (tp->link_config.phy_is_low_power)
8560                 return -EAGAIN;
8561
8562         offset = eeprom->offset;
8563         len = eeprom->len;
8564         eeprom->len = 0;
8565
8566         eeprom->magic = TG3_EEPROM_MAGIC;
8567
8568         if (offset & 3) {
8569                 /* adjustments to start on required 4 byte boundary */
8570                 b_offset = offset & 3;
8571                 b_count = 4 - b_offset;
8572                 if (b_count > len) {
8573                         /* i.e. offset=1 len=2 */
8574                         b_count = len;
8575                 }
8576                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8577                 if (ret)
8578                         return ret;
8579                 memcpy(data, ((char*)&val) + b_offset, b_count);
8580                 len -= b_count;
8581                 offset += b_count;
8582                 eeprom->len += b_count;
8583         }
8584
8585         /* read bytes upto the last 4 byte boundary */
8586         pd = &data[eeprom->len];
8587         for (i = 0; i < (len - (len & 3)); i += 4) {
8588                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8589                 if (ret) {
8590                         eeprom->len += i;
8591                         return ret;
8592                 }
8593                 memcpy(pd + i, &val, 4);
8594         }
8595         eeprom->len += i;
8596
8597         if (len & 3) {
8598                 /* read last bytes not ending on 4 byte boundary */
8599                 pd = &data[eeprom->len];
8600                 b_count = len & 3;
8601                 b_offset = offset + len - b_count;
8602                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8603                 if (ret)
8604                         return ret;
8605                 memcpy(pd, &val, b_count);
8606                 eeprom->len += b_count;
8607         }
8608         return 0;
8609 }
8610
8611 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8612
8613 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8614 {
8615         struct tg3 *tp = netdev_priv(dev);
8616         int ret;
8617         u32 offset, len, b_offset, odd_len;
8618         u8 *buf;
8619         __be32 start, end;
8620
8621         if (tp->link_config.phy_is_low_power)
8622                 return -EAGAIN;
8623
8624         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8625             eeprom->magic != TG3_EEPROM_MAGIC)
8626                 return -EINVAL;
8627
8628         offset = eeprom->offset;
8629         len = eeprom->len;
8630
8631         if ((b_offset = (offset & 3))) {
8632                 /* adjustments to start on required 4 byte boundary */
8633                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8634                 if (ret)
8635                         return ret;
8636                 len += b_offset;
8637                 offset &= ~3;
8638                 if (len < 4)
8639                         len = 4;
8640         }
8641
8642         odd_len = 0;
8643         if (len & 3) {
8644                 /* adjustments to end on required 4 byte boundary */
8645                 odd_len = 1;
8646                 len = (len + 3) & ~3;
8647                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8648                 if (ret)
8649                         return ret;
8650         }
8651
8652         buf = data;
8653         if (b_offset || odd_len) {
8654                 buf = kmalloc(len, GFP_KERNEL);
8655                 if (!buf)
8656                         return -ENOMEM;
8657                 if (b_offset)
8658                         memcpy(buf, &start, 4);
8659                 if (odd_len)
8660                         memcpy(buf+len-4, &end, 4);
8661                 memcpy(buf + b_offset, data, eeprom->len);
8662         }
8663
8664         ret = tg3_nvram_write_block(tp, offset, len, buf);
8665
8666         if (buf != data)
8667                 kfree(buf);
8668
8669         return ret;
8670 }
8671
8672 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8673 {
8674         struct tg3 *tp = netdev_priv(dev);
8675
8676         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8677                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8678                         return -EAGAIN;
8679                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8680         }
8681
8682         cmd->supported = (SUPPORTED_Autoneg);
8683
8684         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8685                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8686                                    SUPPORTED_1000baseT_Full);
8687
8688         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8689                 cmd->supported |= (SUPPORTED_100baseT_Half |
8690                                   SUPPORTED_100baseT_Full |
8691                                   SUPPORTED_10baseT_Half |
8692                                   SUPPORTED_10baseT_Full |
8693                                   SUPPORTED_TP);
8694                 cmd->port = PORT_TP;
8695         } else {
8696                 cmd->supported |= SUPPORTED_FIBRE;
8697                 cmd->port = PORT_FIBRE;
8698         }
8699
8700         cmd->advertising = tp->link_config.advertising;
8701         if (netif_running(dev)) {
8702                 cmd->speed = tp->link_config.active_speed;
8703                 cmd->duplex = tp->link_config.active_duplex;
8704         }
8705         cmd->phy_address = PHY_ADDR;
8706         cmd->transceiver = XCVR_INTERNAL;
8707         cmd->autoneg = tp->link_config.autoneg;
8708         cmd->maxtxpkt = 0;
8709         cmd->maxrxpkt = 0;
8710         return 0;
8711 }
8712
8713 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8714 {
8715         struct tg3 *tp = netdev_priv(dev);
8716
8717         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8718                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8719                         return -EAGAIN;
8720                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8721         }
8722
8723         if (cmd->autoneg != AUTONEG_ENABLE &&
8724             cmd->autoneg != AUTONEG_DISABLE)
8725                 return -EINVAL;
8726
8727         if (cmd->autoneg == AUTONEG_DISABLE &&
8728             cmd->duplex != DUPLEX_FULL &&
8729             cmd->duplex != DUPLEX_HALF)
8730                 return -EINVAL;
8731
8732         if (cmd->autoneg == AUTONEG_ENABLE) {
8733                 u32 mask = ADVERTISED_Autoneg |
8734                            ADVERTISED_Pause |
8735                            ADVERTISED_Asym_Pause;
8736
8737                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8738                         mask |= ADVERTISED_1000baseT_Half |
8739                                 ADVERTISED_1000baseT_Full;
8740
8741                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8742                         mask |= ADVERTISED_100baseT_Half |
8743                                 ADVERTISED_100baseT_Full |
8744                                 ADVERTISED_10baseT_Half |
8745                                 ADVERTISED_10baseT_Full |
8746                                 ADVERTISED_TP;
8747                 else
8748                         mask |= ADVERTISED_FIBRE;
8749
8750                 if (cmd->advertising & ~mask)
8751                         return -EINVAL;
8752
8753                 mask &= (ADVERTISED_1000baseT_Half |
8754                          ADVERTISED_1000baseT_Full |
8755                          ADVERTISED_100baseT_Half |
8756                          ADVERTISED_100baseT_Full |
8757                          ADVERTISED_10baseT_Half |
8758                          ADVERTISED_10baseT_Full);
8759
8760                 cmd->advertising &= mask;
8761         } else {
8762                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8763                         if (cmd->speed != SPEED_1000)
8764                                 return -EINVAL;
8765
8766                         if (cmd->duplex != DUPLEX_FULL)
8767                                 return -EINVAL;
8768                 } else {
8769                         if (cmd->speed != SPEED_100 &&
8770                             cmd->speed != SPEED_10)
8771                                 return -EINVAL;
8772                 }
8773         }
8774
8775         tg3_full_lock(tp, 0);
8776
8777         tp->link_config.autoneg = cmd->autoneg;
8778         if (cmd->autoneg == AUTONEG_ENABLE) {
8779                 tp->link_config.advertising = (cmd->advertising |
8780                                               ADVERTISED_Autoneg);
8781                 tp->link_config.speed = SPEED_INVALID;
8782                 tp->link_config.duplex = DUPLEX_INVALID;
8783         } else {
8784                 tp->link_config.advertising = 0;
8785                 tp->link_config.speed = cmd->speed;
8786                 tp->link_config.duplex = cmd->duplex;
8787         }
8788
8789         tp->link_config.orig_speed = tp->link_config.speed;
8790         tp->link_config.orig_duplex = tp->link_config.duplex;
8791         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8792
8793         if (netif_running(dev))
8794                 tg3_setup_phy(tp, 1);
8795
8796         tg3_full_unlock(tp);
8797
8798         return 0;
8799 }
8800
8801 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8802 {
8803         struct tg3 *tp = netdev_priv(dev);
8804
8805         strcpy(info->driver, DRV_MODULE_NAME);
8806         strcpy(info->version, DRV_MODULE_VERSION);
8807         strcpy(info->fw_version, tp->fw_ver);
8808         strcpy(info->bus_info, pci_name(tp->pdev));
8809 }
8810
8811 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8812 {
8813         struct tg3 *tp = netdev_priv(dev);
8814
8815         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8816             device_can_wakeup(&tp->pdev->dev))
8817                 wol->supported = WAKE_MAGIC;
8818         else
8819                 wol->supported = 0;
8820         wol->wolopts = 0;
8821         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8822             device_can_wakeup(&tp->pdev->dev))
8823                 wol->wolopts = WAKE_MAGIC;
8824         memset(&wol->sopass, 0, sizeof(wol->sopass));
8825 }
8826
8827 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8828 {
8829         struct tg3 *tp = netdev_priv(dev);
8830         struct device *dp = &tp->pdev->dev;
8831
8832         if (wol->wolopts & ~WAKE_MAGIC)
8833                 return -EINVAL;
8834         if ((wol->wolopts & WAKE_MAGIC) &&
8835             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8836                 return -EINVAL;
8837
8838         spin_lock_bh(&tp->lock);
8839         if (wol->wolopts & WAKE_MAGIC) {
8840                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8841                 device_set_wakeup_enable(dp, true);
8842         } else {
8843                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8844                 device_set_wakeup_enable(dp, false);
8845         }
8846         spin_unlock_bh(&tp->lock);
8847
8848         return 0;
8849 }
8850
8851 static u32 tg3_get_msglevel(struct net_device *dev)
8852 {
8853         struct tg3 *tp = netdev_priv(dev);
8854         return tp->msg_enable;
8855 }
8856
8857 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8858 {
8859         struct tg3 *tp = netdev_priv(dev);
8860         tp->msg_enable = value;
8861 }
8862
8863 static int tg3_set_tso(struct net_device *dev, u32 value)
8864 {
8865         struct tg3 *tp = netdev_priv(dev);
8866
8867         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8868                 if (value)
8869                         return -EINVAL;
8870                 return 0;
8871         }
8872         if ((dev->features & NETIF_F_IPV6_CSUM) &&
8873             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8874                 if (value) {
8875                         dev->features |= NETIF_F_TSO6;
8876                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8877                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8878                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8879                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8880                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8881                                 dev->features |= NETIF_F_TSO_ECN;
8882                 } else
8883                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8884         }
8885         return ethtool_op_set_tso(dev, value);
8886 }
8887
8888 static int tg3_nway_reset(struct net_device *dev)
8889 {
8890         struct tg3 *tp = netdev_priv(dev);
8891         int r;
8892
8893         if (!netif_running(dev))
8894                 return -EAGAIN;
8895
8896         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8897                 return -EINVAL;
8898
8899         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8900                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8901                         return -EAGAIN;
8902                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8903         } else {
8904                 u32 bmcr;
8905
8906                 spin_lock_bh(&tp->lock);
8907                 r = -EINVAL;
8908                 tg3_readphy(tp, MII_BMCR, &bmcr);
8909                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8910                     ((bmcr & BMCR_ANENABLE) ||
8911                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8912                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8913                                                    BMCR_ANENABLE);
8914                         r = 0;
8915                 }
8916                 spin_unlock_bh(&tp->lock);
8917         }
8918
8919         return r;
8920 }
8921
8922 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8923 {
8924         struct tg3 *tp = netdev_priv(dev);
8925
8926         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8927         ering->rx_mini_max_pending = 0;
8928         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8929                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8930         else
8931                 ering->rx_jumbo_max_pending = 0;
8932
8933         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8934
8935         ering->rx_pending = tp->rx_pending;
8936         ering->rx_mini_pending = 0;
8937         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8938                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8939         else
8940                 ering->rx_jumbo_pending = 0;
8941
8942         ering->tx_pending = tp->tx_pending;
8943 }
8944
8945 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8946 {
8947         struct tg3 *tp = netdev_priv(dev);
8948         int irq_sync = 0, err = 0;
8949
8950         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8951             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8952             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8953             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8954             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8955              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8956                 return -EINVAL;
8957
8958         if (netif_running(dev)) {
8959                 tg3_phy_stop(tp);
8960                 tg3_netif_stop(tp);
8961                 irq_sync = 1;
8962         }
8963
8964         tg3_full_lock(tp, irq_sync);
8965
8966         tp->rx_pending = ering->rx_pending;
8967
8968         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8969             tp->rx_pending > 63)
8970                 tp->rx_pending = 63;
8971         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8972         tp->tx_pending = ering->tx_pending;
8973
8974         if (netif_running(dev)) {
8975                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8976                 err = tg3_restart_hw(tp, 1);
8977                 if (!err)
8978                         tg3_netif_start(tp);
8979         }
8980
8981         tg3_full_unlock(tp);
8982
8983         if (irq_sync && !err)
8984                 tg3_phy_start(tp);
8985
8986         return err;
8987 }
8988
8989 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8990 {
8991         struct tg3 *tp = netdev_priv(dev);
8992
8993         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8994
8995         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8996                 epause->rx_pause = 1;
8997         else
8998                 epause->rx_pause = 0;
8999
9000         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9001                 epause->tx_pause = 1;
9002         else
9003                 epause->tx_pause = 0;
9004 }
9005
9006 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9007 {
9008         struct tg3 *tp = netdev_priv(dev);
9009         int err = 0;
9010
9011         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9012                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9013                         return -EAGAIN;
9014
9015                 if (epause->autoneg) {
9016                         u32 newadv;
9017                         struct phy_device *phydev;
9018
9019                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9020
9021                         if (epause->rx_pause) {
9022                                 if (epause->tx_pause)
9023                                         newadv = ADVERTISED_Pause;
9024                                 else
9025                                         newadv = ADVERTISED_Pause |
9026                                                  ADVERTISED_Asym_Pause;
9027                         } else if (epause->tx_pause) {
9028                                 newadv = ADVERTISED_Asym_Pause;
9029                         } else
9030                                 newadv = 0;
9031
9032                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9033                                 u32 oldadv = phydev->advertising &
9034                                              (ADVERTISED_Pause |
9035                                               ADVERTISED_Asym_Pause);
9036                                 if (oldadv != newadv) {
9037                                         phydev->advertising &=
9038                                                 ~(ADVERTISED_Pause |
9039                                                   ADVERTISED_Asym_Pause);
9040                                         phydev->advertising |= newadv;
9041                                         err = phy_start_aneg(phydev);
9042                                 }
9043                         } else {
9044                                 tp->link_config.advertising &=
9045                                                 ~(ADVERTISED_Pause |
9046                                                   ADVERTISED_Asym_Pause);
9047                                 tp->link_config.advertising |= newadv;
9048                         }
9049                 } else {
9050                         if (epause->rx_pause)
9051                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9052                         else
9053                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9054
9055                         if (epause->tx_pause)
9056                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9057                         else
9058                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9059
9060                         if (netif_running(dev))
9061                                 tg3_setup_flow_control(tp, 0, 0);
9062                 }
9063         } else {
9064                 int irq_sync = 0;
9065
9066                 if (netif_running(dev)) {
9067                         tg3_netif_stop(tp);
9068                         irq_sync = 1;
9069                 }
9070
9071                 tg3_full_lock(tp, irq_sync);
9072
9073                 if (epause->autoneg)
9074                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9075                 else
9076                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9077                 if (epause->rx_pause)
9078                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9079                 else
9080                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9081                 if (epause->tx_pause)
9082                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9083                 else
9084                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9085
9086                 if (netif_running(dev)) {
9087                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9088                         err = tg3_restart_hw(tp, 1);
9089                         if (!err)
9090                                 tg3_netif_start(tp);
9091                 }
9092
9093                 tg3_full_unlock(tp);
9094         }
9095
9096         return err;
9097 }
9098
9099 static u32 tg3_get_rx_csum(struct net_device *dev)
9100 {
9101         struct tg3 *tp = netdev_priv(dev);
9102         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9103 }
9104
9105 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9106 {
9107         struct tg3 *tp = netdev_priv(dev);
9108
9109         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9110                 if (data != 0)
9111                         return -EINVAL;
9112                 return 0;
9113         }
9114
9115         spin_lock_bh(&tp->lock);
9116         if (data)
9117                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9118         else
9119                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9120         spin_unlock_bh(&tp->lock);
9121
9122         return 0;
9123 }
9124
9125 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9126 {
9127         struct tg3 *tp = netdev_priv(dev);
9128
9129         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9130                 if (data != 0)
9131                         return -EINVAL;
9132                 return 0;
9133         }
9134
9135         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9136                 ethtool_op_set_tx_ipv6_csum(dev, data);
9137         else
9138                 ethtool_op_set_tx_csum(dev, data);
9139
9140         return 0;
9141 }
9142
9143 static int tg3_get_sset_count (struct net_device *dev, int sset)
9144 {
9145         switch (sset) {
9146         case ETH_SS_TEST:
9147                 return TG3_NUM_TEST;
9148         case ETH_SS_STATS:
9149                 return TG3_NUM_STATS;
9150         default:
9151                 return -EOPNOTSUPP;
9152         }
9153 }
9154
9155 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9156 {
9157         switch (stringset) {
9158         case ETH_SS_STATS:
9159                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9160                 break;
9161         case ETH_SS_TEST:
9162                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9163                 break;
9164         default:
9165                 WARN_ON(1);     /* we need a WARN() */
9166                 break;
9167         }
9168 }
9169
9170 static int tg3_phys_id(struct net_device *dev, u32 data)
9171 {
9172         struct tg3 *tp = netdev_priv(dev);
9173         int i;
9174
9175         if (!netif_running(tp->dev))
9176                 return -EAGAIN;
9177
9178         if (data == 0)
9179                 data = UINT_MAX / 2;
9180
9181         for (i = 0; i < (data * 2); i++) {
9182                 if ((i % 2) == 0)
9183                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9184                                            LED_CTRL_1000MBPS_ON |
9185                                            LED_CTRL_100MBPS_ON |
9186                                            LED_CTRL_10MBPS_ON |
9187                                            LED_CTRL_TRAFFIC_OVERRIDE |
9188                                            LED_CTRL_TRAFFIC_BLINK |
9189                                            LED_CTRL_TRAFFIC_LED);
9190
9191                 else
9192                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9193                                            LED_CTRL_TRAFFIC_OVERRIDE);
9194
9195                 if (msleep_interruptible(500))
9196                         break;
9197         }
9198         tw32(MAC_LED_CTRL, tp->led_ctrl);
9199         return 0;
9200 }
9201
9202 static void tg3_get_ethtool_stats (struct net_device *dev,
9203                                    struct ethtool_stats *estats, u64 *tmp_stats)
9204 {
9205         struct tg3 *tp = netdev_priv(dev);
9206         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9207 }
9208
9209 #define NVRAM_TEST_SIZE 0x100
9210 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9211 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9212 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9213 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9214 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9215
9216 static int tg3_test_nvram(struct tg3 *tp)
9217 {
9218         u32 csum, magic;
9219         __be32 *buf;
9220         int i, j, k, err = 0, size;
9221
9222         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9223                 return 0;
9224
9225         if (tg3_nvram_read(tp, 0, &magic) != 0)
9226                 return -EIO;
9227
9228         if (magic == TG3_EEPROM_MAGIC)
9229                 size = NVRAM_TEST_SIZE;
9230         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9231                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9232                     TG3_EEPROM_SB_FORMAT_1) {
9233                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9234                         case TG3_EEPROM_SB_REVISION_0:
9235                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9236                                 break;
9237                         case TG3_EEPROM_SB_REVISION_2:
9238                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9239                                 break;
9240                         case TG3_EEPROM_SB_REVISION_3:
9241                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9242                                 break;
9243                         default:
9244                                 return 0;
9245                         }
9246                 } else
9247                         return 0;
9248         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9249                 size = NVRAM_SELFBOOT_HW_SIZE;
9250         else
9251                 return -EIO;
9252
9253         buf = kmalloc(size, GFP_KERNEL);
9254         if (buf == NULL)
9255                 return -ENOMEM;
9256
9257         err = -EIO;
9258         for (i = 0, j = 0; i < size; i += 4, j++) {
9259                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9260                 if (err)
9261                         break;
9262         }
9263         if (i < size)
9264                 goto out;
9265
9266         /* Selfboot format */
9267         magic = be32_to_cpu(buf[0]);
9268         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9269             TG3_EEPROM_MAGIC_FW) {
9270                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9271
9272                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9273                     TG3_EEPROM_SB_REVISION_2) {
9274                         /* For rev 2, the csum doesn't include the MBA. */
9275                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9276                                 csum8 += buf8[i];
9277                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9278                                 csum8 += buf8[i];
9279                 } else {
9280                         for (i = 0; i < size; i++)
9281                                 csum8 += buf8[i];
9282                 }
9283
9284                 if (csum8 == 0) {
9285                         err = 0;
9286                         goto out;
9287                 }
9288
9289                 err = -EIO;
9290                 goto out;
9291         }
9292
9293         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9294             TG3_EEPROM_MAGIC_HW) {
9295                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9296                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9297                 u8 *buf8 = (u8 *) buf;
9298
9299                 /* Separate the parity bits and the data bytes.  */
9300                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9301                         if ((i == 0) || (i == 8)) {
9302                                 int l;
9303                                 u8 msk;
9304
9305                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9306                                         parity[k++] = buf8[i] & msk;
9307                                 i++;
9308                         }
9309                         else if (i == 16) {
9310                                 int l;
9311                                 u8 msk;
9312
9313                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9314                                         parity[k++] = buf8[i] & msk;
9315                                 i++;
9316
9317                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9318                                         parity[k++] = buf8[i] & msk;
9319                                 i++;
9320                         }
9321                         data[j++] = buf8[i];
9322                 }
9323
9324                 err = -EIO;
9325                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9326                         u8 hw8 = hweight8(data[i]);
9327
9328                         if ((hw8 & 0x1) && parity[i])
9329                                 goto out;
9330                         else if (!(hw8 & 0x1) && !parity[i])
9331                                 goto out;
9332                 }
9333                 err = 0;
9334                 goto out;
9335         }
9336
9337         /* Bootstrap checksum at offset 0x10 */
9338         csum = calc_crc((unsigned char *) buf, 0x10);
9339         if (csum != be32_to_cpu(buf[0x10/4]))
9340                 goto out;
9341
9342         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9343         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9344         if (csum != be32_to_cpu(buf[0xfc/4]))
9345                 goto out;
9346
9347         err = 0;
9348
9349 out:
9350         kfree(buf);
9351         return err;
9352 }
9353
9354 #define TG3_SERDES_TIMEOUT_SEC  2
9355 #define TG3_COPPER_TIMEOUT_SEC  6
9356
9357 static int tg3_test_link(struct tg3 *tp)
9358 {
9359         int i, max;
9360
9361         if (!netif_running(tp->dev))
9362                 return -ENODEV;
9363
9364         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9365                 max = TG3_SERDES_TIMEOUT_SEC;
9366         else
9367                 max = TG3_COPPER_TIMEOUT_SEC;
9368
9369         for (i = 0; i < max; i++) {
9370                 if (netif_carrier_ok(tp->dev))
9371                         return 0;
9372
9373                 if (msleep_interruptible(1000))
9374                         break;
9375         }
9376
9377         return -EIO;
9378 }
9379
9380 /* Only test the commonly used registers */
9381 static int tg3_test_registers(struct tg3 *tp)
9382 {
9383         int i, is_5705, is_5750;
9384         u32 offset, read_mask, write_mask, val, save_val, read_val;
9385         static struct {
9386                 u16 offset;
9387                 u16 flags;
9388 #define TG3_FL_5705     0x1
9389 #define TG3_FL_NOT_5705 0x2
9390 #define TG3_FL_NOT_5788 0x4
9391 #define TG3_FL_NOT_5750 0x8
9392                 u32 read_mask;
9393                 u32 write_mask;
9394         } reg_tbl[] = {
9395                 /* MAC Control Registers */
9396                 { MAC_MODE, TG3_FL_NOT_5705,
9397                         0x00000000, 0x00ef6f8c },
9398                 { MAC_MODE, TG3_FL_5705,
9399                         0x00000000, 0x01ef6b8c },
9400                 { MAC_STATUS, TG3_FL_NOT_5705,
9401                         0x03800107, 0x00000000 },
9402                 { MAC_STATUS, TG3_FL_5705,
9403                         0x03800100, 0x00000000 },
9404                 { MAC_ADDR_0_HIGH, 0x0000,
9405                         0x00000000, 0x0000ffff },
9406                 { MAC_ADDR_0_LOW, 0x0000,
9407                         0x00000000, 0xffffffff },
9408                 { MAC_RX_MTU_SIZE, 0x0000,
9409                         0x00000000, 0x0000ffff },
9410                 { MAC_TX_MODE, 0x0000,
9411                         0x00000000, 0x00000070 },
9412                 { MAC_TX_LENGTHS, 0x0000,
9413                         0x00000000, 0x00003fff },
9414                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9415                         0x00000000, 0x000007fc },
9416                 { MAC_RX_MODE, TG3_FL_5705,
9417                         0x00000000, 0x000007dc },
9418                 { MAC_HASH_REG_0, 0x0000,
9419                         0x00000000, 0xffffffff },
9420                 { MAC_HASH_REG_1, 0x0000,
9421                         0x00000000, 0xffffffff },
9422                 { MAC_HASH_REG_2, 0x0000,
9423                         0x00000000, 0xffffffff },
9424                 { MAC_HASH_REG_3, 0x0000,
9425                         0x00000000, 0xffffffff },
9426
9427                 /* Receive Data and Receive BD Initiator Control Registers. */
9428                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9429                         0x00000000, 0xffffffff },
9430                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9431                         0x00000000, 0xffffffff },
9432                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9433                         0x00000000, 0x00000003 },
9434                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9435                         0x00000000, 0xffffffff },
9436                 { RCVDBDI_STD_BD+0, 0x0000,
9437                         0x00000000, 0xffffffff },
9438                 { RCVDBDI_STD_BD+4, 0x0000,
9439                         0x00000000, 0xffffffff },
9440                 { RCVDBDI_STD_BD+8, 0x0000,
9441                         0x00000000, 0xffff0002 },
9442                 { RCVDBDI_STD_BD+0xc, 0x0000,
9443                         0x00000000, 0xffffffff },
9444
9445                 /* Receive BD Initiator Control Registers. */
9446                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9447                         0x00000000, 0xffffffff },
9448                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9449                         0x00000000, 0x000003ff },
9450                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9451                         0x00000000, 0xffffffff },
9452
9453                 /* Host Coalescing Control Registers. */
9454                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9455                         0x00000000, 0x00000004 },
9456                 { HOSTCC_MODE, TG3_FL_5705,
9457                         0x00000000, 0x000000f6 },
9458                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9459                         0x00000000, 0xffffffff },
9460                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9461                         0x00000000, 0x000003ff },
9462                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9463                         0x00000000, 0xffffffff },
9464                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9465                         0x00000000, 0x000003ff },
9466                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9467                         0x00000000, 0xffffffff },
9468                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9469                         0x00000000, 0x000000ff },
9470                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9471                         0x00000000, 0xffffffff },
9472                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9473                         0x00000000, 0x000000ff },
9474                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9475                         0x00000000, 0xffffffff },
9476                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9477                         0x00000000, 0xffffffff },
9478                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9479                         0x00000000, 0xffffffff },
9480                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9481                         0x00000000, 0x000000ff },
9482                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9483                         0x00000000, 0xffffffff },
9484                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9485                         0x00000000, 0x000000ff },
9486                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9487                         0x00000000, 0xffffffff },
9488                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9489                         0x00000000, 0xffffffff },
9490                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9491                         0x00000000, 0xffffffff },
9492                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9493                         0x00000000, 0xffffffff },
9494                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9495                         0x00000000, 0xffffffff },
9496                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9497                         0xffffffff, 0x00000000 },
9498                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9499                         0xffffffff, 0x00000000 },
9500
9501                 /* Buffer Manager Control Registers. */
9502                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9503                         0x00000000, 0x007fff80 },
9504                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9505                         0x00000000, 0x007fffff },
9506                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9507                         0x00000000, 0x0000003f },
9508                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9509                         0x00000000, 0x000001ff },
9510                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9511                         0x00000000, 0x000001ff },
9512                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9513                         0xffffffff, 0x00000000 },
9514                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9515                         0xffffffff, 0x00000000 },
9516
9517                 /* Mailbox Registers */
9518                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9519                         0x00000000, 0x000001ff },
9520                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9521                         0x00000000, 0x000001ff },
9522                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9523                         0x00000000, 0x000007ff },
9524                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9525                         0x00000000, 0x000001ff },
9526
9527                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9528         };
9529
9530         is_5705 = is_5750 = 0;
9531         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9532                 is_5705 = 1;
9533                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9534                         is_5750 = 1;
9535         }
9536
9537         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9538                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9539                         continue;
9540
9541                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9542                         continue;
9543
9544                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9545                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9546                         continue;
9547
9548                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9549                         continue;
9550
9551                 offset = (u32) reg_tbl[i].offset;
9552                 read_mask = reg_tbl[i].read_mask;
9553                 write_mask = reg_tbl[i].write_mask;
9554
9555                 /* Save the original register content */
9556                 save_val = tr32(offset);
9557
9558                 /* Determine the read-only value. */
9559                 read_val = save_val & read_mask;
9560
9561                 /* Write zero to the register, then make sure the read-only bits
9562                  * are not changed and the read/write bits are all zeros.
9563                  */
9564                 tw32(offset, 0);
9565
9566                 val = tr32(offset);
9567
9568                 /* Test the read-only and read/write bits. */
9569                 if (((val & read_mask) != read_val) || (val & write_mask))
9570                         goto out;
9571
9572                 /* Write ones to all the bits defined by RdMask and WrMask, then
9573                  * make sure the read-only bits are not changed and the
9574                  * read/write bits are all ones.
9575                  */
9576                 tw32(offset, read_mask | write_mask);
9577
9578                 val = tr32(offset);
9579
9580                 /* Test the read-only bits. */
9581                 if ((val & read_mask) != read_val)
9582                         goto out;
9583
9584                 /* Test the read/write bits. */
9585                 if ((val & write_mask) != write_mask)
9586                         goto out;
9587
9588                 tw32(offset, save_val);
9589         }
9590
9591         return 0;
9592
9593 out:
9594         if (netif_msg_hw(tp))
9595                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9596                        offset);
9597         tw32(offset, save_val);
9598         return -EIO;
9599 }
9600
9601 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9602 {
9603         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9604         int i;
9605         u32 j;
9606
9607         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9608                 for (j = 0; j < len; j += 4) {
9609                         u32 val;
9610
9611                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9612                         tg3_read_mem(tp, offset + j, &val);
9613                         if (val != test_pattern[i])
9614                                 return -EIO;
9615                 }
9616         }
9617         return 0;
9618 }
9619
9620 static int tg3_test_memory(struct tg3 *tp)
9621 {
9622         static struct mem_entry {
9623                 u32 offset;
9624                 u32 len;
9625         } mem_tbl_570x[] = {
9626                 { 0x00000000, 0x00b50},
9627                 { 0x00002000, 0x1c000},
9628                 { 0xffffffff, 0x00000}
9629         }, mem_tbl_5705[] = {
9630                 { 0x00000100, 0x0000c},
9631                 { 0x00000200, 0x00008},
9632                 { 0x00004000, 0x00800},
9633                 { 0x00006000, 0x01000},
9634                 { 0x00008000, 0x02000},
9635                 { 0x00010000, 0x0e000},
9636                 { 0xffffffff, 0x00000}
9637         }, mem_tbl_5755[] = {
9638                 { 0x00000200, 0x00008},
9639                 { 0x00004000, 0x00800},
9640                 { 0x00006000, 0x00800},
9641                 { 0x00008000, 0x02000},
9642                 { 0x00010000, 0x0c000},
9643                 { 0xffffffff, 0x00000}
9644         }, mem_tbl_5906[] = {
9645                 { 0x00000200, 0x00008},
9646                 { 0x00004000, 0x00400},
9647                 { 0x00006000, 0x00400},
9648                 { 0x00008000, 0x01000},
9649                 { 0x00010000, 0x01000},
9650                 { 0xffffffff, 0x00000}
9651         };
9652         struct mem_entry *mem_tbl;
9653         int err = 0;
9654         int i;
9655
9656         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9657                 mem_tbl = mem_tbl_5755;
9658         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9659                 mem_tbl = mem_tbl_5906;
9660         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9661                 mem_tbl = mem_tbl_5705;
9662         else
9663                 mem_tbl = mem_tbl_570x;
9664
9665         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9666                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9667                     mem_tbl[i].len)) != 0)
9668                         break;
9669         }
9670
9671         return err;
9672 }
9673
9674 #define TG3_MAC_LOOPBACK        0
9675 #define TG3_PHY_LOOPBACK        1
9676
9677 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9678 {
9679         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9680         u32 desc_idx;
9681         struct sk_buff *skb, *rx_skb;
9682         u8 *tx_data;
9683         dma_addr_t map;
9684         int num_pkts, tx_len, rx_len, i, err;
9685         struct tg3_rx_buffer_desc *desc;
9686
9687         if (loopback_mode == TG3_MAC_LOOPBACK) {
9688                 /* HW errata - mac loopback fails in some cases on 5780.
9689                  * Normal traffic and PHY loopback are not affected by
9690                  * errata.
9691                  */
9692                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9693                         return 0;
9694
9695                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9696                            MAC_MODE_PORT_INT_LPBACK;
9697                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9698                         mac_mode |= MAC_MODE_LINK_POLARITY;
9699                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9700                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9701                 else
9702                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9703                 tw32(MAC_MODE, mac_mode);
9704         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9705                 u32 val;
9706
9707                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9708                         u32 phytest;
9709
9710                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9711                                 u32 phy;
9712
9713                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9714                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9715                                 if (!tg3_readphy(tp, 0x1b, &phy))
9716                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9717                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9718                         }
9719                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9720                 } else
9721                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9722
9723                 tg3_phy_toggle_automdix(tp, 0);
9724
9725                 tg3_writephy(tp, MII_BMCR, val);
9726                 udelay(40);
9727
9728                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9729                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9730                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9731                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9732                 } else
9733                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9734
9735                 /* reset to prevent losing 1st rx packet intermittently */
9736                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9737                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9738                         udelay(10);
9739                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9740                 }
9741                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9742                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9743                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9744                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9745                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9746                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9747                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9748                 }
9749                 tw32(MAC_MODE, mac_mode);
9750         }
9751         else
9752                 return -EINVAL;
9753
9754         err = -EIO;
9755
9756         tx_len = 1514;
9757         skb = netdev_alloc_skb(tp->dev, tx_len);
9758         if (!skb)
9759                 return -ENOMEM;
9760
9761         tx_data = skb_put(skb, tx_len);
9762         memcpy(tx_data, tp->dev->dev_addr, 6);
9763         memset(tx_data + 6, 0x0, 8);
9764
9765         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9766
9767         for (i = 14; i < tx_len; i++)
9768                 tx_data[i] = (u8) (i & 0xff);
9769
9770         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9771
9772         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9773              HOSTCC_MODE_NOW);
9774
9775         udelay(10);
9776
9777         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9778
9779         num_pkts = 0;
9780
9781         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9782
9783         tp->tx_prod++;
9784         num_pkts++;
9785
9786         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9787                      tp->tx_prod);
9788         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9789
9790         udelay(10);
9791
9792         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9793         for (i = 0; i < 25; i++) {
9794                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9795                        HOSTCC_MODE_NOW);
9796
9797                 udelay(10);
9798
9799                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9800                 rx_idx = tp->hw_status->idx[0].rx_producer;
9801                 if ((tx_idx == tp->tx_prod) &&
9802                     (rx_idx == (rx_start_idx + num_pkts)))
9803                         break;
9804         }
9805
9806         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9807         dev_kfree_skb(skb);
9808
9809         if (tx_idx != tp->tx_prod)
9810                 goto out;
9811
9812         if (rx_idx != rx_start_idx + num_pkts)
9813                 goto out;
9814
9815         desc = &tp->rx_rcb[rx_start_idx];
9816         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9817         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9818         if (opaque_key != RXD_OPAQUE_RING_STD)
9819                 goto out;
9820
9821         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9822             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9823                 goto out;
9824
9825         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9826         if (rx_len != tx_len)
9827                 goto out;
9828
9829         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9830
9831         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9832         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9833
9834         for (i = 14; i < tx_len; i++) {
9835                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9836                         goto out;
9837         }
9838         err = 0;
9839
9840         /* tg3_free_rings will unmap and free the rx_skb */
9841 out:
9842         return err;
9843 }
9844
9845 #define TG3_MAC_LOOPBACK_FAILED         1
9846 #define TG3_PHY_LOOPBACK_FAILED         2
9847 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9848                                          TG3_PHY_LOOPBACK_FAILED)
9849
9850 static int tg3_test_loopback(struct tg3 *tp)
9851 {
9852         int err = 0;
9853         u32 cpmuctrl = 0;
9854
9855         if (!netif_running(tp->dev))
9856                 return TG3_LOOPBACK_FAILED;
9857
9858         err = tg3_reset_hw(tp, 1);
9859         if (err)
9860                 return TG3_LOOPBACK_FAILED;
9861
9862         /* Turn off gphy autopowerdown. */
9863         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9864                 tg3_phy_toggle_apd(tp, false);
9865
9866         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9867                 int i;
9868                 u32 status;
9869
9870                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9871
9872                 /* Wait for up to 40 microseconds to acquire lock. */
9873                 for (i = 0; i < 4; i++) {
9874                         status = tr32(TG3_CPMU_MUTEX_GNT);
9875                         if (status == CPMU_MUTEX_GNT_DRIVER)
9876                                 break;
9877                         udelay(10);
9878                 }
9879
9880                 if (status != CPMU_MUTEX_GNT_DRIVER)
9881                         return TG3_LOOPBACK_FAILED;
9882
9883                 /* Turn off link-based power management. */
9884                 cpmuctrl = tr32(TG3_CPMU_CTRL);
9885                 tw32(TG3_CPMU_CTRL,
9886                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9887                                   CPMU_CTRL_LINK_AWARE_MODE));
9888         }
9889
9890         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9891                 err |= TG3_MAC_LOOPBACK_FAILED;
9892
9893         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9894                 tw32(TG3_CPMU_CTRL, cpmuctrl);
9895
9896                 /* Release the mutex */
9897                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9898         }
9899
9900         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9901             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9902                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9903                         err |= TG3_PHY_LOOPBACK_FAILED;
9904         }
9905
9906         /* Re-enable gphy autopowerdown. */
9907         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9908                 tg3_phy_toggle_apd(tp, true);
9909
9910         return err;
9911 }
9912
9913 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9914                           u64 *data)
9915 {
9916         struct tg3 *tp = netdev_priv(dev);
9917
9918         if (tp->link_config.phy_is_low_power)
9919                 tg3_set_power_state(tp, PCI_D0);
9920
9921         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9922
9923         if (tg3_test_nvram(tp) != 0) {
9924                 etest->flags |= ETH_TEST_FL_FAILED;
9925                 data[0] = 1;
9926         }
9927         if (tg3_test_link(tp) != 0) {
9928                 etest->flags |= ETH_TEST_FL_FAILED;
9929                 data[1] = 1;
9930         }
9931         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9932                 int err, err2 = 0, irq_sync = 0;
9933
9934                 if (netif_running(dev)) {
9935                         tg3_phy_stop(tp);
9936                         tg3_netif_stop(tp);
9937                         irq_sync = 1;
9938                 }
9939
9940                 tg3_full_lock(tp, irq_sync);
9941
9942                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9943                 err = tg3_nvram_lock(tp);
9944                 tg3_halt_cpu(tp, RX_CPU_BASE);
9945                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9946                         tg3_halt_cpu(tp, TX_CPU_BASE);
9947                 if (!err)
9948                         tg3_nvram_unlock(tp);
9949
9950                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9951                         tg3_phy_reset(tp);
9952
9953                 if (tg3_test_registers(tp) != 0) {
9954                         etest->flags |= ETH_TEST_FL_FAILED;
9955                         data[2] = 1;
9956                 }
9957                 if (tg3_test_memory(tp) != 0) {
9958                         etest->flags |= ETH_TEST_FL_FAILED;
9959                         data[3] = 1;
9960                 }
9961                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9962                         etest->flags |= ETH_TEST_FL_FAILED;
9963
9964                 tg3_full_unlock(tp);
9965
9966                 if (tg3_test_interrupt(tp) != 0) {
9967                         etest->flags |= ETH_TEST_FL_FAILED;
9968                         data[5] = 1;
9969                 }
9970
9971                 tg3_full_lock(tp, 0);
9972
9973                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9974                 if (netif_running(dev)) {
9975                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9976                         err2 = tg3_restart_hw(tp, 1);
9977                         if (!err2)
9978                                 tg3_netif_start(tp);
9979                 }
9980
9981                 tg3_full_unlock(tp);
9982
9983                 if (irq_sync && !err2)
9984                         tg3_phy_start(tp);
9985         }
9986         if (tp->link_config.phy_is_low_power)
9987                 tg3_set_power_state(tp, PCI_D3hot);
9988
9989 }
9990
9991 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9992 {
9993         struct mii_ioctl_data *data = if_mii(ifr);
9994         struct tg3 *tp = netdev_priv(dev);
9995         int err;
9996
9997         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9998                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9999                         return -EAGAIN;
10000                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10001         }
10002
10003         switch(cmd) {
10004         case SIOCGMIIPHY:
10005                 data->phy_id = PHY_ADDR;
10006
10007                 /* fallthru */
10008         case SIOCGMIIREG: {
10009                 u32 mii_regval;
10010
10011                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10012                         break;                  /* We have no PHY */
10013
10014                 if (tp->link_config.phy_is_low_power)
10015                         return -EAGAIN;
10016
10017                 spin_lock_bh(&tp->lock);
10018                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10019                 spin_unlock_bh(&tp->lock);
10020
10021                 data->val_out = mii_regval;
10022
10023                 return err;
10024         }
10025
10026         case SIOCSMIIREG:
10027                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10028                         break;                  /* We have no PHY */
10029
10030                 if (!capable(CAP_NET_ADMIN))
10031                         return -EPERM;
10032
10033                 if (tp->link_config.phy_is_low_power)
10034                         return -EAGAIN;
10035
10036                 spin_lock_bh(&tp->lock);
10037                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10038                 spin_unlock_bh(&tp->lock);
10039
10040                 return err;
10041
10042         default:
10043                 /* do nothing */
10044                 break;
10045         }
10046         return -EOPNOTSUPP;
10047 }
10048
10049 #if TG3_VLAN_TAG_USED
10050 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10051 {
10052         struct tg3 *tp = netdev_priv(dev);
10053
10054         if (!netif_running(dev)) {
10055                 tp->vlgrp = grp;
10056                 return;
10057         }
10058
10059         tg3_netif_stop(tp);
10060
10061         tg3_full_lock(tp, 0);
10062
10063         tp->vlgrp = grp;
10064
10065         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10066         __tg3_set_rx_mode(dev);
10067
10068         tg3_netif_start(tp);
10069
10070         tg3_full_unlock(tp);
10071 }
10072 #endif
10073
10074 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10075 {
10076         struct tg3 *tp = netdev_priv(dev);
10077
10078         memcpy(ec, &tp->coal, sizeof(*ec));
10079         return 0;
10080 }
10081
10082 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10083 {
10084         struct tg3 *tp = netdev_priv(dev);
10085         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10086         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10087
10088         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10089                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10090                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10091                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10092                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10093         }
10094
10095         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10096             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10097             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10098             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10099             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10100             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10101             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10102             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10103             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10104             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10105                 return -EINVAL;
10106
10107         /* No rx interrupts will be generated if both are zero */
10108         if ((ec->rx_coalesce_usecs == 0) &&
10109             (ec->rx_max_coalesced_frames == 0))
10110                 return -EINVAL;
10111
10112         /* No tx interrupts will be generated if both are zero */
10113         if ((ec->tx_coalesce_usecs == 0) &&
10114             (ec->tx_max_coalesced_frames == 0))
10115                 return -EINVAL;
10116
10117         /* Only copy relevant parameters, ignore all others. */
10118         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10119         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10120         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10121         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10122         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10123         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10124         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10125         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10126         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10127
10128         if (netif_running(dev)) {
10129                 tg3_full_lock(tp, 0);
10130                 __tg3_set_coalesce(tp, &tp->coal);
10131                 tg3_full_unlock(tp);
10132         }
10133         return 0;
10134 }
10135
10136 static const struct ethtool_ops tg3_ethtool_ops = {
10137         .get_settings           = tg3_get_settings,
10138         .set_settings           = tg3_set_settings,
10139         .get_drvinfo            = tg3_get_drvinfo,
10140         .get_regs_len           = tg3_get_regs_len,
10141         .get_regs               = tg3_get_regs,
10142         .get_wol                = tg3_get_wol,
10143         .set_wol                = tg3_set_wol,
10144         .get_msglevel           = tg3_get_msglevel,
10145         .set_msglevel           = tg3_set_msglevel,
10146         .nway_reset             = tg3_nway_reset,
10147         .get_link               = ethtool_op_get_link,
10148         .get_eeprom_len         = tg3_get_eeprom_len,
10149         .get_eeprom             = tg3_get_eeprom,
10150         .set_eeprom             = tg3_set_eeprom,
10151         .get_ringparam          = tg3_get_ringparam,
10152         .set_ringparam          = tg3_set_ringparam,
10153         .get_pauseparam         = tg3_get_pauseparam,
10154         .set_pauseparam         = tg3_set_pauseparam,
10155         .get_rx_csum            = tg3_get_rx_csum,
10156         .set_rx_csum            = tg3_set_rx_csum,
10157         .set_tx_csum            = tg3_set_tx_csum,
10158         .set_sg                 = ethtool_op_set_sg,
10159         .set_tso                = tg3_set_tso,
10160         .self_test              = tg3_self_test,
10161         .get_strings            = tg3_get_strings,
10162         .phys_id                = tg3_phys_id,
10163         .get_ethtool_stats      = tg3_get_ethtool_stats,
10164         .get_coalesce           = tg3_get_coalesce,
10165         .set_coalesce           = tg3_set_coalesce,
10166         .get_sset_count         = tg3_get_sset_count,
10167 };
10168
10169 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10170 {
10171         u32 cursize, val, magic;
10172
10173         tp->nvram_size = EEPROM_CHIP_SIZE;
10174
10175         if (tg3_nvram_read(tp, 0, &magic) != 0)
10176                 return;
10177
10178         if ((magic != TG3_EEPROM_MAGIC) &&
10179             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10180             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10181                 return;
10182
10183         /*
10184          * Size the chip by reading offsets at increasing powers of two.
10185          * When we encounter our validation signature, we know the addressing
10186          * has wrapped around, and thus have our chip size.
10187          */
10188         cursize = 0x10;
10189
10190         while (cursize < tp->nvram_size) {
10191                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10192                         return;
10193
10194                 if (val == magic)
10195                         break;
10196
10197                 cursize <<= 1;
10198         }
10199
10200         tp->nvram_size = cursize;
10201 }
10202
10203 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10204 {
10205         u32 val;
10206
10207         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10208             tg3_nvram_read(tp, 0, &val) != 0)
10209                 return;
10210
10211         /* Selfboot format */
10212         if (val != TG3_EEPROM_MAGIC) {
10213                 tg3_get_eeprom_size(tp);
10214                 return;
10215         }
10216
10217         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10218                 if (val != 0) {
10219                         /* This is confusing.  We want to operate on the
10220                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10221                          * call will read from NVRAM and byteswap the data
10222                          * according to the byteswapping settings for all
10223                          * other register accesses.  This ensures the data we
10224                          * want will always reside in the lower 16-bits.
10225                          * However, the data in NVRAM is in LE format, which
10226                          * means the data from the NVRAM read will always be
10227                          * opposite the endianness of the CPU.  The 16-bit
10228                          * byteswap then brings the data to CPU endianness.
10229                          */
10230                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10231                         return;
10232                 }
10233         }
10234         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10235 }
10236
10237 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10238 {
10239         u32 nvcfg1;
10240
10241         nvcfg1 = tr32(NVRAM_CFG1);
10242         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10243                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10244         }
10245         else {
10246                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10247                 tw32(NVRAM_CFG1, nvcfg1);
10248         }
10249
10250         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10251             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10252                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10253                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10254                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10255                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10256                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10257                                 break;
10258                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10259                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10260                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10261                                 break;
10262                         case FLASH_VENDOR_ATMEL_EEPROM:
10263                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10264                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10265                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10266                                 break;
10267                         case FLASH_VENDOR_ST:
10268                                 tp->nvram_jedecnum = JEDEC_ST;
10269                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10270                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10271                                 break;
10272                         case FLASH_VENDOR_SAIFUN:
10273                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10274                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10275                                 break;
10276                         case FLASH_VENDOR_SST_SMALL:
10277                         case FLASH_VENDOR_SST_LARGE:
10278                                 tp->nvram_jedecnum = JEDEC_SST;
10279                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10280                                 break;
10281                 }
10282         }
10283         else {
10284                 tp->nvram_jedecnum = JEDEC_ATMEL;
10285                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10286                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10287         }
10288 }
10289
10290 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10291 {
10292         u32 nvcfg1;
10293
10294         nvcfg1 = tr32(NVRAM_CFG1);
10295
10296         /* NVRAM protection for TPM */
10297         if (nvcfg1 & (1 << 27))
10298                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10299
10300         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10301                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10302                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10303                         tp->nvram_jedecnum = JEDEC_ATMEL;
10304                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10305                         break;
10306                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10307                         tp->nvram_jedecnum = JEDEC_ATMEL;
10308                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10309                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10310                         break;
10311                 case FLASH_5752VENDOR_ST_M45PE10:
10312                 case FLASH_5752VENDOR_ST_M45PE20:
10313                 case FLASH_5752VENDOR_ST_M45PE40:
10314                         tp->nvram_jedecnum = JEDEC_ST;
10315                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10316                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10317                         break;
10318         }
10319
10320         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10321                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10322                         case FLASH_5752PAGE_SIZE_256:
10323                                 tp->nvram_pagesize = 256;
10324                                 break;
10325                         case FLASH_5752PAGE_SIZE_512:
10326                                 tp->nvram_pagesize = 512;
10327                                 break;
10328                         case FLASH_5752PAGE_SIZE_1K:
10329                                 tp->nvram_pagesize = 1024;
10330                                 break;
10331                         case FLASH_5752PAGE_SIZE_2K:
10332                                 tp->nvram_pagesize = 2048;
10333                                 break;
10334                         case FLASH_5752PAGE_SIZE_4K:
10335                                 tp->nvram_pagesize = 4096;
10336                                 break;
10337                         case FLASH_5752PAGE_SIZE_264:
10338                                 tp->nvram_pagesize = 264;
10339                                 break;
10340                 }
10341         }
10342         else {
10343                 /* For eeprom, set pagesize to maximum eeprom size */
10344                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10345
10346                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10347                 tw32(NVRAM_CFG1, nvcfg1);
10348         }
10349 }
10350
10351 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10352 {
10353         u32 nvcfg1, protect = 0;
10354
10355         nvcfg1 = tr32(NVRAM_CFG1);
10356
10357         /* NVRAM protection for TPM */
10358         if (nvcfg1 & (1 << 27)) {
10359                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10360                 protect = 1;
10361         }
10362
10363         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10364         switch (nvcfg1) {
10365                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10366                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10367                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10368                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10369                         tp->nvram_jedecnum = JEDEC_ATMEL;
10370                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10371                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10372                         tp->nvram_pagesize = 264;
10373                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10374                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10375                                 tp->nvram_size = (protect ? 0x3e200 :
10376                                                   TG3_NVRAM_SIZE_512KB);
10377                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10378                                 tp->nvram_size = (protect ? 0x1f200 :
10379                                                   TG3_NVRAM_SIZE_256KB);
10380                         else
10381                                 tp->nvram_size = (protect ? 0x1f200 :
10382                                                   TG3_NVRAM_SIZE_128KB);
10383                         break;
10384                 case FLASH_5752VENDOR_ST_M45PE10:
10385                 case FLASH_5752VENDOR_ST_M45PE20:
10386                 case FLASH_5752VENDOR_ST_M45PE40:
10387                         tp->nvram_jedecnum = JEDEC_ST;
10388                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10389                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10390                         tp->nvram_pagesize = 256;
10391                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10392                                 tp->nvram_size = (protect ?
10393                                                   TG3_NVRAM_SIZE_64KB :
10394                                                   TG3_NVRAM_SIZE_128KB);
10395                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10396                                 tp->nvram_size = (protect ?
10397                                                   TG3_NVRAM_SIZE_64KB :
10398                                                   TG3_NVRAM_SIZE_256KB);
10399                         else
10400                                 tp->nvram_size = (protect ?
10401                                                   TG3_NVRAM_SIZE_128KB :
10402                                                   TG3_NVRAM_SIZE_512KB);
10403                         break;
10404         }
10405 }
10406
10407 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10408 {
10409         u32 nvcfg1;
10410
10411         nvcfg1 = tr32(NVRAM_CFG1);
10412
10413         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10414                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10415                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10416                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10417                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10418                         tp->nvram_jedecnum = JEDEC_ATMEL;
10419                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10420                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10421
10422                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10423                         tw32(NVRAM_CFG1, nvcfg1);
10424                         break;
10425                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10426                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10427                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10428                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10429                         tp->nvram_jedecnum = JEDEC_ATMEL;
10430                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10431                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10432                         tp->nvram_pagesize = 264;
10433                         break;
10434                 case FLASH_5752VENDOR_ST_M45PE10:
10435                 case FLASH_5752VENDOR_ST_M45PE20:
10436                 case FLASH_5752VENDOR_ST_M45PE40:
10437                         tp->nvram_jedecnum = JEDEC_ST;
10438                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10439                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10440                         tp->nvram_pagesize = 256;
10441                         break;
10442         }
10443 }
10444
10445 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10446 {
10447         u32 nvcfg1, protect = 0;
10448
10449         nvcfg1 = tr32(NVRAM_CFG1);
10450
10451         /* NVRAM protection for TPM */
10452         if (nvcfg1 & (1 << 27)) {
10453                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10454                 protect = 1;
10455         }
10456
10457         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10458         switch (nvcfg1) {
10459                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10460                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10461                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10462                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10463                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10464                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10465                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10466                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10467                         tp->nvram_jedecnum = JEDEC_ATMEL;
10468                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10469                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10470                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10471                         tp->nvram_pagesize = 256;
10472                         break;
10473                 case FLASH_5761VENDOR_ST_A_M45PE20:
10474                 case FLASH_5761VENDOR_ST_A_M45PE40:
10475                 case FLASH_5761VENDOR_ST_A_M45PE80:
10476                 case FLASH_5761VENDOR_ST_A_M45PE16:
10477                 case FLASH_5761VENDOR_ST_M_M45PE20:
10478                 case FLASH_5761VENDOR_ST_M_M45PE40:
10479                 case FLASH_5761VENDOR_ST_M_M45PE80:
10480                 case FLASH_5761VENDOR_ST_M_M45PE16:
10481                         tp->nvram_jedecnum = JEDEC_ST;
10482                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10483                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10484                         tp->nvram_pagesize = 256;
10485                         break;
10486         }
10487
10488         if (protect) {
10489                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10490         } else {
10491                 switch (nvcfg1) {
10492                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10493                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10494                         case FLASH_5761VENDOR_ST_A_M45PE16:
10495                         case FLASH_5761VENDOR_ST_M_M45PE16:
10496                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10497                                 break;
10498                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10499                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10500                         case FLASH_5761VENDOR_ST_A_M45PE80:
10501                         case FLASH_5761VENDOR_ST_M_M45PE80:
10502                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10503                                 break;
10504                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10505                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10506                         case FLASH_5761VENDOR_ST_A_M45PE40:
10507                         case FLASH_5761VENDOR_ST_M_M45PE40:
10508                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10509                                 break;
10510                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10511                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10512                         case FLASH_5761VENDOR_ST_A_M45PE20:
10513                         case FLASH_5761VENDOR_ST_M_M45PE20:
10514                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10515                                 break;
10516                 }
10517         }
10518 }
10519
10520 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10521 {
10522         tp->nvram_jedecnum = JEDEC_ATMEL;
10523         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10524         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10525 }
10526
10527 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10528 {
10529         u32 nvcfg1;
10530
10531         nvcfg1 = tr32(NVRAM_CFG1);
10532
10533         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10534         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10535         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10536                 tp->nvram_jedecnum = JEDEC_ATMEL;
10537                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10538                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10539
10540                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10541                 tw32(NVRAM_CFG1, nvcfg1);
10542                 return;
10543         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10544         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10545         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10546         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10547         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10548         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10549         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10550                 tp->nvram_jedecnum = JEDEC_ATMEL;
10551                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10552                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10553
10554                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10555                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10556                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10557                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10558                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10559                         break;
10560                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10561                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10562                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10563                         break;
10564                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10565                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10566                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10567                         break;
10568                 }
10569                 break;
10570         case FLASH_5752VENDOR_ST_M45PE10:
10571         case FLASH_5752VENDOR_ST_M45PE20:
10572         case FLASH_5752VENDOR_ST_M45PE40:
10573                 tp->nvram_jedecnum = JEDEC_ST;
10574                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10575                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10576
10577                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10578                 case FLASH_5752VENDOR_ST_M45PE10:
10579                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10580                         break;
10581                 case FLASH_5752VENDOR_ST_M45PE20:
10582                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10583                         break;
10584                 case FLASH_5752VENDOR_ST_M45PE40:
10585                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10586                         break;
10587                 }
10588                 break;
10589         default:
10590                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10591                 return;
10592         }
10593
10594         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10595         case FLASH_5752PAGE_SIZE_256:
10596                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10597                 tp->nvram_pagesize = 256;
10598                 break;
10599         case FLASH_5752PAGE_SIZE_512:
10600                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10601                 tp->nvram_pagesize = 512;
10602                 break;
10603         case FLASH_5752PAGE_SIZE_1K:
10604                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10605                 tp->nvram_pagesize = 1024;
10606                 break;
10607         case FLASH_5752PAGE_SIZE_2K:
10608                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10609                 tp->nvram_pagesize = 2048;
10610                 break;
10611         case FLASH_5752PAGE_SIZE_4K:
10612                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10613                 tp->nvram_pagesize = 4096;
10614                 break;
10615         case FLASH_5752PAGE_SIZE_264:
10616                 tp->nvram_pagesize = 264;
10617                 break;
10618         case FLASH_5752PAGE_SIZE_528:
10619                 tp->nvram_pagesize = 528;
10620                 break;
10621         }
10622 }
10623
10624 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10625 static void __devinit tg3_nvram_init(struct tg3 *tp)
10626 {
10627         tw32_f(GRC_EEPROM_ADDR,
10628              (EEPROM_ADDR_FSM_RESET |
10629               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10630                EEPROM_ADDR_CLKPERD_SHIFT)));
10631
10632         msleep(1);
10633
10634         /* Enable seeprom accesses. */
10635         tw32_f(GRC_LOCAL_CTRL,
10636              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10637         udelay(100);
10638
10639         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10640             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10641                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10642
10643                 if (tg3_nvram_lock(tp)) {
10644                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10645                                "tg3_nvram_init failed.\n", tp->dev->name);
10646                         return;
10647                 }
10648                 tg3_enable_nvram_access(tp);
10649
10650                 tp->nvram_size = 0;
10651
10652                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10653                         tg3_get_5752_nvram_info(tp);
10654                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10655                         tg3_get_5755_nvram_info(tp);
10656                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10657                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10658                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10659                         tg3_get_5787_nvram_info(tp);
10660                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10661                         tg3_get_5761_nvram_info(tp);
10662                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10663                         tg3_get_5906_nvram_info(tp);
10664                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10665                         tg3_get_57780_nvram_info(tp);
10666                 else
10667                         tg3_get_nvram_info(tp);
10668
10669                 if (tp->nvram_size == 0)
10670                         tg3_get_nvram_size(tp);
10671
10672                 tg3_disable_nvram_access(tp);
10673                 tg3_nvram_unlock(tp);
10674
10675         } else {
10676                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10677
10678                 tg3_get_eeprom_size(tp);
10679         }
10680 }
10681
10682 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10683                                     u32 offset, u32 len, u8 *buf)
10684 {
10685         int i, j, rc = 0;
10686         u32 val;
10687
10688         for (i = 0; i < len; i += 4) {
10689                 u32 addr;
10690                 __be32 data;
10691
10692                 addr = offset + i;
10693
10694                 memcpy(&data, buf + i, 4);
10695
10696                 /*
10697                  * The SEEPROM interface expects the data to always be opposite
10698                  * the native endian format.  We accomplish this by reversing
10699                  * all the operations that would have been performed on the
10700                  * data from a call to tg3_nvram_read_be32().
10701                  */
10702                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10703
10704                 val = tr32(GRC_EEPROM_ADDR);
10705                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10706
10707                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10708                         EEPROM_ADDR_READ);
10709                 tw32(GRC_EEPROM_ADDR, val |
10710                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10711                         (addr & EEPROM_ADDR_ADDR_MASK) |
10712                         EEPROM_ADDR_START |
10713                         EEPROM_ADDR_WRITE);
10714
10715                 for (j = 0; j < 1000; j++) {
10716                         val = tr32(GRC_EEPROM_ADDR);
10717
10718                         if (val & EEPROM_ADDR_COMPLETE)
10719                                 break;
10720                         msleep(1);
10721                 }
10722                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10723                         rc = -EBUSY;
10724                         break;
10725                 }
10726         }
10727
10728         return rc;
10729 }
10730
10731 /* offset and length are dword aligned */
10732 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10733                 u8 *buf)
10734 {
10735         int ret = 0;
10736         u32 pagesize = tp->nvram_pagesize;
10737         u32 pagemask = pagesize - 1;
10738         u32 nvram_cmd;
10739         u8 *tmp;
10740
10741         tmp = kmalloc(pagesize, GFP_KERNEL);
10742         if (tmp == NULL)
10743                 return -ENOMEM;
10744
10745         while (len) {
10746                 int j;
10747                 u32 phy_addr, page_off, size;
10748
10749                 phy_addr = offset & ~pagemask;
10750
10751                 for (j = 0; j < pagesize; j += 4) {
10752                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10753                                                   (__be32 *) (tmp + j));
10754                         if (ret)
10755                                 break;
10756                 }
10757                 if (ret)
10758                         break;
10759
10760                 page_off = offset & pagemask;
10761                 size = pagesize;
10762                 if (len < size)
10763                         size = len;
10764
10765                 len -= size;
10766
10767                 memcpy(tmp + page_off, buf, size);
10768
10769                 offset = offset + (pagesize - page_off);
10770
10771                 tg3_enable_nvram_access(tp);
10772
10773                 /*
10774                  * Before we can erase the flash page, we need
10775                  * to issue a special "write enable" command.
10776                  */
10777                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10778
10779                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10780                         break;
10781
10782                 /* Erase the target page */
10783                 tw32(NVRAM_ADDR, phy_addr);
10784
10785                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10786                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10787
10788                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10789                         break;
10790
10791                 /* Issue another write enable to start the write. */
10792                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10793
10794                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10795                         break;
10796
10797                 for (j = 0; j < pagesize; j += 4) {
10798                         __be32 data;
10799
10800                         data = *((__be32 *) (tmp + j));
10801
10802                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10803
10804                         tw32(NVRAM_ADDR, phy_addr + j);
10805
10806                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10807                                 NVRAM_CMD_WR;
10808
10809                         if (j == 0)
10810                                 nvram_cmd |= NVRAM_CMD_FIRST;
10811                         else if (j == (pagesize - 4))
10812                                 nvram_cmd |= NVRAM_CMD_LAST;
10813
10814                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10815                                 break;
10816                 }
10817                 if (ret)
10818                         break;
10819         }
10820
10821         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10822         tg3_nvram_exec_cmd(tp, nvram_cmd);
10823
10824         kfree(tmp);
10825
10826         return ret;
10827 }
10828
10829 /* offset and length are dword aligned */
10830 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10831                 u8 *buf)
10832 {
10833         int i, ret = 0;
10834
10835         for (i = 0; i < len; i += 4, offset += 4) {
10836                 u32 page_off, phy_addr, nvram_cmd;
10837                 __be32 data;
10838
10839                 memcpy(&data, buf + i, 4);
10840                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10841
10842                 page_off = offset % tp->nvram_pagesize;
10843
10844                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10845
10846                 tw32(NVRAM_ADDR, phy_addr);
10847
10848                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10849
10850                 if ((page_off == 0) || (i == 0))
10851                         nvram_cmd |= NVRAM_CMD_FIRST;
10852                 if (page_off == (tp->nvram_pagesize - 4))
10853                         nvram_cmd |= NVRAM_CMD_LAST;
10854
10855                 if (i == (len - 4))
10856                         nvram_cmd |= NVRAM_CMD_LAST;
10857
10858                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10859                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10860                     (tp->nvram_jedecnum == JEDEC_ST) &&
10861                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10862
10863                         if ((ret = tg3_nvram_exec_cmd(tp,
10864                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10865                                 NVRAM_CMD_DONE)))
10866
10867                                 break;
10868                 }
10869                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10870                         /* We always do complete word writes to eeprom. */
10871                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10872                 }
10873
10874                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10875                         break;
10876         }
10877         return ret;
10878 }
10879
10880 /* offset and length are dword aligned */
10881 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10882 {
10883         int ret;
10884
10885         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10886                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10887                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
10888                 udelay(40);
10889         }
10890
10891         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10892                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10893         }
10894         else {
10895                 u32 grc_mode;
10896
10897                 ret = tg3_nvram_lock(tp);
10898                 if (ret)
10899                         return ret;
10900
10901                 tg3_enable_nvram_access(tp);
10902                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10903                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10904                         tw32(NVRAM_WRITE1, 0x406);
10905
10906                 grc_mode = tr32(GRC_MODE);
10907                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10908
10909                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10910                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10911
10912                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
10913                                 buf);
10914                 }
10915                 else {
10916                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10917                                 buf);
10918                 }
10919
10920                 grc_mode = tr32(GRC_MODE);
10921                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10922
10923                 tg3_disable_nvram_access(tp);
10924                 tg3_nvram_unlock(tp);
10925         }
10926
10927         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10928                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10929                 udelay(40);
10930         }
10931
10932         return ret;
10933 }
10934
10935 struct subsys_tbl_ent {
10936         u16 subsys_vendor, subsys_devid;
10937         u32 phy_id;
10938 };
10939
10940 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10941         /* Broadcom boards. */
10942         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10943         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10944         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10945         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
10946         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10947         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10948         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
10949         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10950         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10951         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10952         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10953
10954         /* 3com boards. */
10955         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10956         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10957         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10958         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10959         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10960
10961         /* DELL boards. */
10962         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10963         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10964         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10965         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10966
10967         /* Compaq boards. */
10968         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10969         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10970         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
10971         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10972         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10973
10974         /* IBM boards. */
10975         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10976 };
10977
10978 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10979 {
10980         int i;
10981
10982         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10983                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10984                      tp->pdev->subsystem_vendor) &&
10985                     (subsys_id_to_phy_id[i].subsys_devid ==
10986                      tp->pdev->subsystem_device))
10987                         return &subsys_id_to_phy_id[i];
10988         }
10989         return NULL;
10990 }
10991
10992 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10993 {
10994         u32 val;
10995         u16 pmcsr;
10996
10997         /* On some early chips the SRAM cannot be accessed in D3hot state,
10998          * so need make sure we're in D0.
10999          */
11000         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11001         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11002         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11003         msleep(1);
11004
11005         /* Make sure register accesses (indirect or otherwise)
11006          * will function correctly.
11007          */
11008         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11009                                tp->misc_host_ctrl);
11010
11011         /* The memory arbiter has to be enabled in order for SRAM accesses
11012          * to succeed.  Normally on powerup the tg3 chip firmware will make
11013          * sure it is enabled, but other entities such as system netboot
11014          * code might disable it.
11015          */
11016         val = tr32(MEMARB_MODE);
11017         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11018
11019         tp->phy_id = PHY_ID_INVALID;
11020         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11021
11022         /* Assume an onboard device and WOL capable by default.  */
11023         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11024
11025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11026                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11027                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11028                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11029                 }
11030                 val = tr32(VCPU_CFGSHDW);
11031                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11032                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11033                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11034                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11035                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11036                 goto done;
11037         }
11038
11039         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11040         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11041                 u32 nic_cfg, led_cfg;
11042                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11043                 int eeprom_phy_serdes = 0;
11044
11045                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11046                 tp->nic_sram_data_cfg = nic_cfg;
11047
11048                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11049                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11050                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11051                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11052                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11053                     (ver > 0) && (ver < 0x100))
11054                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11055
11056                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11057                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11058
11059                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11060                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11061                         eeprom_phy_serdes = 1;
11062
11063                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11064                 if (nic_phy_id != 0) {
11065                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11066                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11067
11068                         eeprom_phy_id  = (id1 >> 16) << 10;
11069                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11070                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11071                 } else
11072                         eeprom_phy_id = 0;
11073
11074                 tp->phy_id = eeprom_phy_id;
11075                 if (eeprom_phy_serdes) {
11076                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11077                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11078                         else
11079                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11080                 }
11081
11082                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11083                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11084                                     SHASTA_EXT_LED_MODE_MASK);
11085                 else
11086                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11087
11088                 switch (led_cfg) {
11089                 default:
11090                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11091                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11092                         break;
11093
11094                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11095                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11096                         break;
11097
11098                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11099                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11100
11101                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11102                          * read on some older 5700/5701 bootcode.
11103                          */
11104                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11105                             ASIC_REV_5700 ||
11106                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11107                             ASIC_REV_5701)
11108                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11109
11110                         break;
11111
11112                 case SHASTA_EXT_LED_SHARED:
11113                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11114                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11115                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11116                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11117                                                  LED_CTRL_MODE_PHY_2);
11118                         break;
11119
11120                 case SHASTA_EXT_LED_MAC:
11121                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11122                         break;
11123
11124                 case SHASTA_EXT_LED_COMBO:
11125                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11126                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11127                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11128                                                  LED_CTRL_MODE_PHY_2);
11129                         break;
11130
11131                 }
11132
11133                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11134                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11135                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11136                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11137
11138                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11139                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11140
11141                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11142                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11143                         if ((tp->pdev->subsystem_vendor ==
11144                              PCI_VENDOR_ID_ARIMA) &&
11145                             (tp->pdev->subsystem_device == 0x205a ||
11146                              tp->pdev->subsystem_device == 0x2063))
11147                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11148                 } else {
11149                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11150                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11151                 }
11152
11153                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11154                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11155                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11156                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11157                 }
11158
11159                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11160                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11161                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11162
11163                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11164                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11165                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11166
11167                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11168                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11169                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11170
11171                 if (cfg2 & (1 << 17))
11172                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11173
11174                 /* serdes signal pre-emphasis in register 0x590 set by */
11175                 /* bootcode if bit 18 is set */
11176                 if (cfg2 & (1 << 18))
11177                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11178
11179                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11180                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11181                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11182                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11183
11184                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11185                         u32 cfg3;
11186
11187                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11188                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11189                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11190                 }
11191
11192                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11193                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11194                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11195                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11196                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11197                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11198         }
11199 done:
11200         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11201         device_set_wakeup_enable(&tp->pdev->dev,
11202                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11203 }
11204
11205 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11206 {
11207         int i;
11208         u32 val;
11209
11210         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11211         tw32(OTP_CTRL, cmd);
11212
11213         /* Wait for up to 1 ms for command to execute. */
11214         for (i = 0; i < 100; i++) {
11215                 val = tr32(OTP_STATUS);
11216                 if (val & OTP_STATUS_CMD_DONE)
11217                         break;
11218                 udelay(10);
11219         }
11220
11221         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11222 }
11223
11224 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11225  * configuration is a 32-bit value that straddles the alignment boundary.
11226  * We do two 32-bit reads and then shift and merge the results.
11227  */
11228 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11229 {
11230         u32 bhalf_otp, thalf_otp;
11231
11232         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11233
11234         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11235                 return 0;
11236
11237         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11238
11239         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11240                 return 0;
11241
11242         thalf_otp = tr32(OTP_READ_DATA);
11243
11244         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11245
11246         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11247                 return 0;
11248
11249         bhalf_otp = tr32(OTP_READ_DATA);
11250
11251         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11252 }
11253
11254 static int __devinit tg3_phy_probe(struct tg3 *tp)
11255 {
11256         u32 hw_phy_id_1, hw_phy_id_2;
11257         u32 hw_phy_id, hw_phy_id_masked;
11258         int err;
11259
11260         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11261                 return tg3_phy_init(tp);
11262
11263         /* Reading the PHY ID register can conflict with ASF
11264          * firmware access to the PHY hardware.
11265          */
11266         err = 0;
11267         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11268             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11269                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11270         } else {
11271                 /* Now read the physical PHY_ID from the chip and verify
11272                  * that it is sane.  If it doesn't look good, we fall back
11273                  * to either the hard-coded table based PHY_ID and failing
11274                  * that the value found in the eeprom area.
11275                  */
11276                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11277                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11278
11279                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11280                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11281                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11282
11283                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11284         }
11285
11286         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11287                 tp->phy_id = hw_phy_id;
11288                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11289                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11290                 else
11291                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11292         } else {
11293                 if (tp->phy_id != PHY_ID_INVALID) {
11294                         /* Do nothing, phy ID already set up in
11295                          * tg3_get_eeprom_hw_cfg().
11296                          */
11297                 } else {
11298                         struct subsys_tbl_ent *p;
11299
11300                         /* No eeprom signature?  Try the hardcoded
11301                          * subsys device table.
11302                          */
11303                         p = lookup_by_subsys(tp);
11304                         if (!p)
11305                                 return -ENODEV;
11306
11307                         tp->phy_id = p->phy_id;
11308                         if (!tp->phy_id ||
11309                             tp->phy_id == PHY_ID_BCM8002)
11310                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11311                 }
11312         }
11313
11314         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11315             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11316             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11317                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11318
11319                 tg3_readphy(tp, MII_BMSR, &bmsr);
11320                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11321                     (bmsr & BMSR_LSTATUS))
11322                         goto skip_phy_reset;
11323
11324                 err = tg3_phy_reset(tp);
11325                 if (err)
11326                         return err;
11327
11328                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11329                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11330                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11331                 tg3_ctrl = 0;
11332                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11333                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11334                                     MII_TG3_CTRL_ADV_1000_FULL);
11335                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11336                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11337                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11338                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11339                 }
11340
11341                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11342                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11343                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11344                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11345                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11346
11347                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11348                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11349
11350                         tg3_writephy(tp, MII_BMCR,
11351                                      BMCR_ANENABLE | BMCR_ANRESTART);
11352                 }
11353                 tg3_phy_set_wirespeed(tp);
11354
11355                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11356                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11357                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11358         }
11359
11360 skip_phy_reset:
11361         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11362                 err = tg3_init_5401phy_dsp(tp);
11363                 if (err)
11364                         return err;
11365         }
11366
11367         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11368                 err = tg3_init_5401phy_dsp(tp);
11369         }
11370
11371         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11372                 tp->link_config.advertising =
11373                         (ADVERTISED_1000baseT_Half |
11374                          ADVERTISED_1000baseT_Full |
11375                          ADVERTISED_Autoneg |
11376                          ADVERTISED_FIBRE);
11377         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11378                 tp->link_config.advertising &=
11379                         ~(ADVERTISED_1000baseT_Half |
11380                           ADVERTISED_1000baseT_Full);
11381
11382         return err;
11383 }
11384
11385 static void __devinit tg3_read_partno(struct tg3 *tp)
11386 {
11387         unsigned char vpd_data[256];   /* in little-endian format */
11388         unsigned int i;
11389         u32 magic;
11390
11391         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11392             tg3_nvram_read(tp, 0x0, &magic))
11393                 goto out_not_found;
11394
11395         if (magic == TG3_EEPROM_MAGIC) {
11396                 for (i = 0; i < 256; i += 4) {
11397                         u32 tmp;
11398
11399                         /* The data is in little-endian format in NVRAM.
11400                          * Use the big-endian read routines to preserve
11401                          * the byte order as it exists in NVRAM.
11402                          */
11403                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11404                                 goto out_not_found;
11405
11406                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11407                 }
11408         } else {
11409                 int vpd_cap;
11410
11411                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11412                 for (i = 0; i < 256; i += 4) {
11413                         u32 tmp, j = 0;
11414                         __le32 v;
11415                         u16 tmp16;
11416
11417                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11418                                               i);
11419                         while (j++ < 100) {
11420                                 pci_read_config_word(tp->pdev, vpd_cap +
11421                                                      PCI_VPD_ADDR, &tmp16);
11422                                 if (tmp16 & 0x8000)
11423                                         break;
11424                                 msleep(1);
11425                         }
11426                         if (!(tmp16 & 0x8000))
11427                                 goto out_not_found;
11428
11429                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11430                                               &tmp);
11431                         v = cpu_to_le32(tmp);
11432                         memcpy(&vpd_data[i], &v, sizeof(v));
11433                 }
11434         }
11435
11436         /* Now parse and find the part number. */
11437         for (i = 0; i < 254; ) {
11438                 unsigned char val = vpd_data[i];
11439                 unsigned int block_end;
11440
11441                 if (val == 0x82 || val == 0x91) {
11442                         i = (i + 3 +
11443                              (vpd_data[i + 1] +
11444                               (vpd_data[i + 2] << 8)));
11445                         continue;
11446                 }
11447
11448                 if (val != 0x90)
11449                         goto out_not_found;
11450
11451                 block_end = (i + 3 +
11452                              (vpd_data[i + 1] +
11453                               (vpd_data[i + 2] << 8)));
11454                 i += 3;
11455
11456                 if (block_end > 256)
11457                         goto out_not_found;
11458
11459                 while (i < (block_end - 2)) {
11460                         if (vpd_data[i + 0] == 'P' &&
11461                             vpd_data[i + 1] == 'N') {
11462                                 int partno_len = vpd_data[i + 2];
11463
11464                                 i += 3;
11465                                 if (partno_len > 24 || (partno_len + i) > 256)
11466                                         goto out_not_found;
11467
11468                                 memcpy(tp->board_part_number,
11469                                        &vpd_data[i], partno_len);
11470
11471                                 /* Success. */
11472                                 return;
11473                         }
11474                         i += 3 + vpd_data[i + 2];
11475                 }
11476
11477                 /* Part number not found. */
11478                 goto out_not_found;
11479         }
11480
11481 out_not_found:
11482         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11483                 strcpy(tp->board_part_number, "BCM95906");
11484         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11485                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11486                 strcpy(tp->board_part_number, "BCM57780");
11487         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11488                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11489                 strcpy(tp->board_part_number, "BCM57760");
11490         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11491                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11492                 strcpy(tp->board_part_number, "BCM57790");
11493         else
11494                 strcpy(tp->board_part_number, "none");
11495 }
11496
11497 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11498 {
11499         u32 val;
11500
11501         if (tg3_nvram_read(tp, offset, &val) ||
11502             (val & 0xfc000000) != 0x0c000000 ||
11503             tg3_nvram_read(tp, offset + 4, &val) ||
11504             val != 0)
11505                 return 0;
11506
11507         return 1;
11508 }
11509
11510 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11511 {
11512         u32 val, offset, start, ver_offset;
11513         int i;
11514         bool newver = false;
11515
11516         if (tg3_nvram_read(tp, 0xc, &offset) ||
11517             tg3_nvram_read(tp, 0x4, &start))
11518                 return;
11519
11520         offset = tg3_nvram_logical_addr(tp, offset);
11521
11522         if (tg3_nvram_read(tp, offset, &val))
11523                 return;
11524
11525         if ((val & 0xfc000000) == 0x0c000000) {
11526                 if (tg3_nvram_read(tp, offset + 4, &val))
11527                         return;
11528
11529                 if (val == 0)
11530                         newver = true;
11531         }
11532
11533         if (newver) {
11534                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11535                         return;
11536
11537                 offset = offset + ver_offset - start;
11538                 for (i = 0; i < 16; i += 4) {
11539                         __be32 v;
11540                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11541                                 return;
11542
11543                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11544                 }
11545         } else {
11546                 u32 major, minor;
11547
11548                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11549                         return;
11550
11551                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11552                         TG3_NVM_BCVER_MAJSFT;
11553                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11554                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11555         }
11556 }
11557
11558 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11559 {
11560         u32 val, major, minor;
11561
11562         /* Use native endian representation */
11563         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11564                 return;
11565
11566         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11567                 TG3_NVM_HWSB_CFG1_MAJSFT;
11568         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11569                 TG3_NVM_HWSB_CFG1_MINSFT;
11570
11571         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11572 }
11573
11574 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11575 {
11576         u32 offset, major, minor, build;
11577
11578         tp->fw_ver[0] = 's';
11579         tp->fw_ver[1] = 'b';
11580         tp->fw_ver[2] = '\0';
11581
11582         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11583                 return;
11584
11585         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11586         case TG3_EEPROM_SB_REVISION_0:
11587                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11588                 break;
11589         case TG3_EEPROM_SB_REVISION_2:
11590                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11591                 break;
11592         case TG3_EEPROM_SB_REVISION_3:
11593                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11594                 break;
11595         default:
11596                 return;
11597         }
11598
11599         if (tg3_nvram_read(tp, offset, &val))
11600                 return;
11601
11602         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11603                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11604         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11605                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11606         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11607
11608         if (minor > 99 || build > 26)
11609                 return;
11610
11611         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11612
11613         if (build > 0) {
11614                 tp->fw_ver[8] = 'a' + build - 1;
11615                 tp->fw_ver[9] = '\0';
11616         }
11617 }
11618
11619 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11620 {
11621         u32 val, offset, start;
11622         int i, vlen;
11623
11624         for (offset = TG3_NVM_DIR_START;
11625              offset < TG3_NVM_DIR_END;
11626              offset += TG3_NVM_DIRENT_SIZE) {
11627                 if (tg3_nvram_read(tp, offset, &val))
11628                         return;
11629
11630                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11631                         break;
11632         }
11633
11634         if (offset == TG3_NVM_DIR_END)
11635                 return;
11636
11637         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11638                 start = 0x08000000;
11639         else if (tg3_nvram_read(tp, offset - 4, &start))
11640                 return;
11641
11642         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11643             !tg3_fw_img_is_valid(tp, offset) ||
11644             tg3_nvram_read(tp, offset + 8, &val))
11645                 return;
11646
11647         offset += val - start;
11648
11649         vlen = strlen(tp->fw_ver);
11650
11651         tp->fw_ver[vlen++] = ',';
11652         tp->fw_ver[vlen++] = ' ';
11653
11654         for (i = 0; i < 4; i++) {
11655                 __be32 v;
11656                 if (tg3_nvram_read_be32(tp, offset, &v))
11657                         return;
11658
11659                 offset += sizeof(v);
11660
11661                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11662                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11663                         break;
11664                 }
11665
11666                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11667                 vlen += sizeof(v);
11668         }
11669 }
11670
11671 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11672 {
11673         int vlen;
11674         u32 apedata;
11675
11676         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11677             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11678                 return;
11679
11680         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11681         if (apedata != APE_SEG_SIG_MAGIC)
11682                 return;
11683
11684         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11685         if (!(apedata & APE_FW_STATUS_READY))
11686                 return;
11687
11688         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11689
11690         vlen = strlen(tp->fw_ver);
11691
11692         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11693                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11694                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11695                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11696                  (apedata & APE_FW_VERSION_BLDMSK));
11697 }
11698
11699 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11700 {
11701         u32 val;
11702
11703         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11704                 tp->fw_ver[0] = 's';
11705                 tp->fw_ver[1] = 'b';
11706                 tp->fw_ver[2] = '\0';
11707
11708                 return;
11709         }
11710
11711         if (tg3_nvram_read(tp, 0, &val))
11712                 return;
11713
11714         if (val == TG3_EEPROM_MAGIC)
11715                 tg3_read_bc_ver(tp);
11716         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11717                 tg3_read_sb_ver(tp, val);
11718         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11719                 tg3_read_hwsb_ver(tp);
11720         else
11721                 return;
11722
11723         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11724              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11725                 return;
11726
11727         tg3_read_mgmtfw_ver(tp);
11728
11729         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11730 }
11731
11732 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11733
11734 static int __devinit tg3_get_invariants(struct tg3 *tp)
11735 {
11736         static struct pci_device_id write_reorder_chipsets[] = {
11737                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11738                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11739                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11740                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11741                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11742                              PCI_DEVICE_ID_VIA_8385_0) },
11743                 { },
11744         };
11745         u32 misc_ctrl_reg;
11746         u32 pci_state_reg, grc_misc_cfg;
11747         u32 val;
11748         u16 pci_cmd;
11749         int err;
11750
11751         /* Force memory write invalidate off.  If we leave it on,
11752          * then on 5700_BX chips we have to enable a workaround.
11753          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11754          * to match the cacheline size.  The Broadcom driver have this
11755          * workaround but turns MWI off all the times so never uses
11756          * it.  This seems to suggest that the workaround is insufficient.
11757          */
11758         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11759         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11760         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11761
11762         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11763          * has the register indirect write enable bit set before
11764          * we try to access any of the MMIO registers.  It is also
11765          * critical that the PCI-X hw workaround situation is decided
11766          * before that as well.
11767          */
11768         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11769                               &misc_ctrl_reg);
11770
11771         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11772                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11773         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11774                 u32 prod_id_asic_rev;
11775
11776                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11777                                       &prod_id_asic_rev);
11778                 tp->pci_chip_rev_id = prod_id_asic_rev;
11779         }
11780
11781         /* Wrong chip ID in 5752 A0. This code can be removed later
11782          * as A0 is not in production.
11783          */
11784         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11785                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11786
11787         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11788          * we need to disable memory and use config. cycles
11789          * only to access all registers. The 5702/03 chips
11790          * can mistakenly decode the special cycles from the
11791          * ICH chipsets as memory write cycles, causing corruption
11792          * of register and memory space. Only certain ICH bridges
11793          * will drive special cycles with non-zero data during the
11794          * address phase which can fall within the 5703's address
11795          * range. This is not an ICH bug as the PCI spec allows
11796          * non-zero address during special cycles. However, only
11797          * these ICH bridges are known to drive non-zero addresses
11798          * during special cycles.
11799          *
11800          * Since special cycles do not cross PCI bridges, we only
11801          * enable this workaround if the 5703 is on the secondary
11802          * bus of these ICH bridges.
11803          */
11804         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11805             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11806                 static struct tg3_dev_id {
11807                         u32     vendor;
11808                         u32     device;
11809                         u32     rev;
11810                 } ich_chipsets[] = {
11811                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11812                           PCI_ANY_ID },
11813                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11814                           PCI_ANY_ID },
11815                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11816                           0xa },
11817                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11818                           PCI_ANY_ID },
11819                         { },
11820                 };
11821                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11822                 struct pci_dev *bridge = NULL;
11823
11824                 while (pci_id->vendor != 0) {
11825                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11826                                                 bridge);
11827                         if (!bridge) {
11828                                 pci_id++;
11829                                 continue;
11830                         }
11831                         if (pci_id->rev != PCI_ANY_ID) {
11832                                 if (bridge->revision > pci_id->rev)
11833                                         continue;
11834                         }
11835                         if (bridge->subordinate &&
11836                             (bridge->subordinate->number ==
11837                              tp->pdev->bus->number)) {
11838
11839                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11840                                 pci_dev_put(bridge);
11841                                 break;
11842                         }
11843                 }
11844         }
11845
11846         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11847                 static struct tg3_dev_id {
11848                         u32     vendor;
11849                         u32     device;
11850                 } bridge_chipsets[] = {
11851                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11852                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11853                         { },
11854                 };
11855                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11856                 struct pci_dev *bridge = NULL;
11857
11858                 while (pci_id->vendor != 0) {
11859                         bridge = pci_get_device(pci_id->vendor,
11860                                                 pci_id->device,
11861                                                 bridge);
11862                         if (!bridge) {
11863                                 pci_id++;
11864                                 continue;
11865                         }
11866                         if (bridge->subordinate &&
11867                             (bridge->subordinate->number <=
11868                              tp->pdev->bus->number) &&
11869                             (bridge->subordinate->subordinate >=
11870                              tp->pdev->bus->number)) {
11871                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11872                                 pci_dev_put(bridge);
11873                                 break;
11874                         }
11875                 }
11876         }
11877
11878         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11879          * DMA addresses > 40-bit. This bridge may have other additional
11880          * 57xx devices behind it in some 4-port NIC designs for example.
11881          * Any tg3 device found behind the bridge will also need the 40-bit
11882          * DMA workaround.
11883          */
11884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11886                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11887                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11888                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11889         }
11890         else {
11891                 struct pci_dev *bridge = NULL;
11892
11893                 do {
11894                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11895                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11896                                                 bridge);
11897                         if (bridge && bridge->subordinate &&
11898                             (bridge->subordinate->number <=
11899                              tp->pdev->bus->number) &&
11900                             (bridge->subordinate->subordinate >=
11901                              tp->pdev->bus->number)) {
11902                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11903                                 pci_dev_put(bridge);
11904                                 break;
11905                         }
11906                 } while (bridge);
11907         }
11908
11909         /* Initialize misc host control in PCI block. */
11910         tp->misc_host_ctrl |= (misc_ctrl_reg &
11911                                MISC_HOST_CTRL_CHIPREV);
11912         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11913                                tp->misc_host_ctrl);
11914
11915         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11916             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11917                 tp->pdev_peer = tg3_find_peer(tp);
11918
11919         /* Intentionally exclude ASIC_REV_5906 */
11920         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11921             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11922             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11923             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11924             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11925             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11926                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11927
11928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11930             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11931             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11932             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11933                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11934
11935         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11936             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11937                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11938
11939         /* 5700 B0 chips do not support checksumming correctly due
11940          * to hardware bugs.
11941          */
11942         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11943                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11944         else {
11945                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11946                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11947                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11948                         tp->dev->features |= NETIF_F_IPV6_CSUM;
11949         }
11950
11951         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11952                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11953                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11954                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11955                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11956                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11957                      tp->pdev_peer == tp->pdev))
11958                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11959
11960                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11961                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11962                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11963                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11964                 } else {
11965                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11966                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11967                                 ASIC_REV_5750 &&
11968                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11969                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11970                 }
11971         }
11972
11973         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11974              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11975                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11976
11977         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11978                               &pci_state_reg);
11979
11980         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11981         if (tp->pcie_cap != 0) {
11982                 u16 lnkctl;
11983
11984                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11985
11986                 pcie_set_readrq(tp->pdev, 4096);
11987
11988                 pci_read_config_word(tp->pdev,
11989                                      tp->pcie_cap + PCI_EXP_LNKCTL,
11990                                      &lnkctl);
11991                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11992                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11993                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11994                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11995                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11996                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
11997                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
11998                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
11999                 }
12000         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12001                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12002         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12003                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12004                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12005                 if (!tp->pcix_cap) {
12006                         printk(KERN_ERR PFX "Cannot find PCI-X "
12007                                             "capability, aborting.\n");
12008                         return -EIO;
12009                 }
12010
12011                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12012                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12013         }
12014
12015         /* If we have an AMD 762 or VIA K8T800 chipset, write
12016          * reordering to the mailbox registers done by the host
12017          * controller can cause major troubles.  We read back from
12018          * every mailbox register write to force the writes to be
12019          * posted to the chip in order.
12020          */
12021         if (pci_dev_present(write_reorder_chipsets) &&
12022             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12023                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12024
12025         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12026                              &tp->pci_cacheline_sz);
12027         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12028                              &tp->pci_lat_timer);
12029         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12030             tp->pci_lat_timer < 64) {
12031                 tp->pci_lat_timer = 64;
12032                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12033                                       tp->pci_lat_timer);
12034         }
12035
12036         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12037                 /* 5700 BX chips need to have their TX producer index
12038                  * mailboxes written twice to workaround a bug.
12039                  */
12040                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12041
12042                 /* If we are in PCI-X mode, enable register write workaround.
12043                  *
12044                  * The workaround is to use indirect register accesses
12045                  * for all chip writes not to mailbox registers.
12046                  */
12047                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12048                         u32 pm_reg;
12049
12050                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12051
12052                         /* The chip can have it's power management PCI config
12053                          * space registers clobbered due to this bug.
12054                          * So explicitly force the chip into D0 here.
12055                          */
12056                         pci_read_config_dword(tp->pdev,
12057                                               tp->pm_cap + PCI_PM_CTRL,
12058                                               &pm_reg);
12059                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12060                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12061                         pci_write_config_dword(tp->pdev,
12062                                                tp->pm_cap + PCI_PM_CTRL,
12063                                                pm_reg);
12064
12065                         /* Also, force SERR#/PERR# in PCI command. */
12066                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12067                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12068                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12069                 }
12070         }
12071
12072         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12073                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12074         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12075                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12076
12077         /* Chip-specific fixup from Broadcom driver */
12078         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12079             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12080                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12081                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12082         }
12083
12084         /* Default fast path register access methods */
12085         tp->read32 = tg3_read32;
12086         tp->write32 = tg3_write32;
12087         tp->read32_mbox = tg3_read32;
12088         tp->write32_mbox = tg3_write32;
12089         tp->write32_tx_mbox = tg3_write32;
12090         tp->write32_rx_mbox = tg3_write32;
12091
12092         /* Various workaround register access methods */
12093         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12094                 tp->write32 = tg3_write_indirect_reg32;
12095         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12096                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12097                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12098                 /*
12099                  * Back to back register writes can cause problems on these
12100                  * chips, the workaround is to read back all reg writes
12101                  * except those to mailbox regs.
12102                  *
12103                  * See tg3_write_indirect_reg32().
12104                  */
12105                 tp->write32 = tg3_write_flush_reg32;
12106         }
12107
12108
12109         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12110             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12111                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12112                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12113                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12114         }
12115
12116         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12117                 tp->read32 = tg3_read_indirect_reg32;
12118                 tp->write32 = tg3_write_indirect_reg32;
12119                 tp->read32_mbox = tg3_read_indirect_mbox;
12120                 tp->write32_mbox = tg3_write_indirect_mbox;
12121                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12122                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12123
12124                 iounmap(tp->regs);
12125                 tp->regs = NULL;
12126
12127                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12128                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12129                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12130         }
12131         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12132                 tp->read32_mbox = tg3_read32_mbox_5906;
12133                 tp->write32_mbox = tg3_write32_mbox_5906;
12134                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12135                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12136         }
12137
12138         if (tp->write32 == tg3_write_indirect_reg32 ||
12139             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12140              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12141               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12142                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12143
12144         /* Get eeprom hw config before calling tg3_set_power_state().
12145          * In particular, the TG3_FLG2_IS_NIC flag must be
12146          * determined before calling tg3_set_power_state() so that
12147          * we know whether or not to switch out of Vaux power.
12148          * When the flag is set, it means that GPIO1 is used for eeprom
12149          * write protect and also implies that it is a LOM where GPIOs
12150          * are not used to switch power.
12151          */
12152         tg3_get_eeprom_hw_cfg(tp);
12153
12154         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12155                 /* Allow reads and writes to the
12156                  * APE register and memory space.
12157                  */
12158                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12159                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12160                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12161                                        pci_state_reg);
12162         }
12163
12164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12165             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12166             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12167             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12168                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12169
12170         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12171          * GPIO1 driven high will bring 5700's external PHY out of reset.
12172          * It is also used as eeprom write protect on LOMs.
12173          */
12174         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12175         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12176             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12177                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12178                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12179         /* Unused GPIO3 must be driven as output on 5752 because there
12180          * are no pull-up resistors on unused GPIO pins.
12181          */
12182         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12183                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12184
12185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12186             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12187                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12188
12189         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12190             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12191                 /* Turn off the debug UART. */
12192                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12193                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12194                         /* Keep VMain power. */
12195                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12196                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12197         }
12198
12199         /* Force the chip into D0. */
12200         err = tg3_set_power_state(tp, PCI_D0);
12201         if (err) {
12202                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12203                        pci_name(tp->pdev));
12204                 return err;
12205         }
12206
12207         /* Derive initial jumbo mode from MTU assigned in
12208          * ether_setup() via the alloc_etherdev() call
12209          */
12210         if (tp->dev->mtu > ETH_DATA_LEN &&
12211             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12212                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12213
12214         /* Determine WakeOnLan speed to use. */
12215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12216             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12217             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12218             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12219                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12220         } else {
12221                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12222         }
12223
12224         /* A few boards don't want Ethernet@WireSpeed phy feature */
12225         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12226             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12227              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12228              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12229             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12230             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12231                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12232
12233         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12234             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12235                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12236         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12237                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12238
12239         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12240             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12241             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12242             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12243                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12244                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12245                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12246                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12247                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12248                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12249                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12250                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12251                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12252                 } else
12253                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12254         }
12255
12256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12257             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12258                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12259                 if (tp->phy_otp == 0)
12260                         tp->phy_otp = TG3_OTP_DEFAULT;
12261         }
12262
12263         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12264                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12265         else
12266                 tp->mi_mode = MAC_MI_MODE_BASE;
12267
12268         tp->coalesce_mode = 0;
12269         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12270             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12271                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12272
12273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12274             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12275                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12276
12277         err = tg3_mdio_init(tp);
12278         if (err)
12279                 return err;
12280
12281         /* Initialize data/descriptor byte/word swapping. */
12282         val = tr32(GRC_MODE);
12283         val &= GRC_MODE_HOST_STACKUP;
12284         tw32(GRC_MODE, val | tp->grc_mode);
12285
12286         tg3_switch_clocks(tp);
12287
12288         /* Clear this out for sanity. */
12289         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12290
12291         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12292                               &pci_state_reg);
12293         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12294             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12295                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12296
12297                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12298                     chiprevid == CHIPREV_ID_5701_B0 ||
12299                     chiprevid == CHIPREV_ID_5701_B2 ||
12300                     chiprevid == CHIPREV_ID_5701_B5) {
12301                         void __iomem *sram_base;
12302
12303                         /* Write some dummy words into the SRAM status block
12304                          * area, see if it reads back correctly.  If the return
12305                          * value is bad, force enable the PCIX workaround.
12306                          */
12307                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12308
12309                         writel(0x00000000, sram_base);
12310                         writel(0x00000000, sram_base + 4);
12311                         writel(0xffffffff, sram_base + 4);
12312                         if (readl(sram_base) != 0x00000000)
12313                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12314                 }
12315         }
12316
12317         udelay(50);
12318         tg3_nvram_init(tp);
12319
12320         grc_misc_cfg = tr32(GRC_MISC_CFG);
12321         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12322
12323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12324             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12325              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12326                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12327
12328         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12329             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12330                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12331         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12332                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12333                                       HOSTCC_MODE_CLRTICK_TXBD);
12334
12335                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12336                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12337                                        tp->misc_host_ctrl);
12338         }
12339
12340         /* Preserve the APE MAC_MODE bits */
12341         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12342                 tp->mac_mode = tr32(MAC_MODE) |
12343                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12344         else
12345                 tp->mac_mode = TG3_DEF_MAC_MODE;
12346
12347         /* these are limited to 10/100 only */
12348         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12349              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12350             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12351              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12352              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12353               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12354               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12355             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12356              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12357               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12358               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12359             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12360             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12361                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12362
12363         err = tg3_phy_probe(tp);
12364         if (err) {
12365                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12366                        pci_name(tp->pdev), err);
12367                 /* ... but do not return immediately ... */
12368                 tg3_mdio_fini(tp);
12369         }
12370
12371         tg3_read_partno(tp);
12372         tg3_read_fw_ver(tp);
12373
12374         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12375                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12376         } else {
12377                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12378                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12379                 else
12380                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12381         }
12382
12383         /* 5700 {AX,BX} chips have a broken status block link
12384          * change bit implementation, so we must use the
12385          * status register in those cases.
12386          */
12387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12388                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12389         else
12390                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12391
12392         /* The led_ctrl is set during tg3_phy_probe, here we might
12393          * have to force the link status polling mechanism based
12394          * upon subsystem IDs.
12395          */
12396         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12397             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12398             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12399                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12400                                   TG3_FLAG_USE_LINKCHG_REG);
12401         }
12402
12403         /* For all SERDES we poll the MAC status register. */
12404         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12405                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12406         else
12407                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12408
12409         tp->rx_offset = NET_IP_ALIGN;
12410         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12411             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12412                 tp->rx_offset = 0;
12413
12414         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12415
12416         /* Increment the rx prod index on the rx std ring by at most
12417          * 8 for these chips to workaround hw errata.
12418          */
12419         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12420             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12421             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12422                 tp->rx_std_max_post = 8;
12423
12424         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12425                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12426                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12427
12428         return err;
12429 }
12430
12431 #ifdef CONFIG_SPARC
12432 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12433 {
12434         struct net_device *dev = tp->dev;
12435         struct pci_dev *pdev = tp->pdev;
12436         struct device_node *dp = pci_device_to_OF_node(pdev);
12437         const unsigned char *addr;
12438         int len;
12439
12440         addr = of_get_property(dp, "local-mac-address", &len);
12441         if (addr && len == 6) {
12442                 memcpy(dev->dev_addr, addr, 6);
12443                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12444                 return 0;
12445         }
12446         return -ENODEV;
12447 }
12448
12449 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12450 {
12451         struct net_device *dev = tp->dev;
12452
12453         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12454         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12455         return 0;
12456 }
12457 #endif
12458
12459 static int __devinit tg3_get_device_address(struct tg3 *tp)
12460 {
12461         struct net_device *dev = tp->dev;
12462         u32 hi, lo, mac_offset;
12463         int addr_ok = 0;
12464
12465 #ifdef CONFIG_SPARC
12466         if (!tg3_get_macaddr_sparc(tp))
12467                 return 0;
12468 #endif
12469
12470         mac_offset = 0x7c;
12471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12472             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12473                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12474                         mac_offset = 0xcc;
12475                 if (tg3_nvram_lock(tp))
12476                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12477                 else
12478                         tg3_nvram_unlock(tp);
12479         }
12480         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12481                 mac_offset = 0x10;
12482
12483         /* First try to get it from MAC address mailbox. */
12484         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12485         if ((hi >> 16) == 0x484b) {
12486                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12487                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12488
12489                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12490                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12491                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12492                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12493                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12494
12495                 /* Some old bootcode may report a 0 MAC address in SRAM */
12496                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12497         }
12498         if (!addr_ok) {
12499                 /* Next, try NVRAM. */
12500                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12501                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12502                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12503                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12504                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12505                 }
12506                 /* Finally just fetch it out of the MAC control regs. */
12507                 else {
12508                         hi = tr32(MAC_ADDR_0_HIGH);
12509                         lo = tr32(MAC_ADDR_0_LOW);
12510
12511                         dev->dev_addr[5] = lo & 0xff;
12512                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12513                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12514                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12515                         dev->dev_addr[1] = hi & 0xff;
12516                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12517                 }
12518         }
12519
12520         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12521 #ifdef CONFIG_SPARC
12522                 if (!tg3_get_default_macaddr_sparc(tp))
12523                         return 0;
12524 #endif
12525                 return -EINVAL;
12526         }
12527         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12528         return 0;
12529 }
12530
12531 #define BOUNDARY_SINGLE_CACHELINE       1
12532 #define BOUNDARY_MULTI_CACHELINE        2
12533
12534 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12535 {
12536         int cacheline_size;
12537         u8 byte;
12538         int goal;
12539
12540         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12541         if (byte == 0)
12542                 cacheline_size = 1024;
12543         else
12544                 cacheline_size = (int) byte * 4;
12545
12546         /* On 5703 and later chips, the boundary bits have no
12547          * effect.
12548          */
12549         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12550             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12551             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12552                 goto out;
12553
12554 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12555         goal = BOUNDARY_MULTI_CACHELINE;
12556 #else
12557 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12558         goal = BOUNDARY_SINGLE_CACHELINE;
12559 #else
12560         goal = 0;
12561 #endif
12562 #endif
12563
12564         if (!goal)
12565                 goto out;
12566
12567         /* PCI controllers on most RISC systems tend to disconnect
12568          * when a device tries to burst across a cache-line boundary.
12569          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12570          *
12571          * Unfortunately, for PCI-E there are only limited
12572          * write-side controls for this, and thus for reads
12573          * we will still get the disconnects.  We'll also waste
12574          * these PCI cycles for both read and write for chips
12575          * other than 5700 and 5701 which do not implement the
12576          * boundary bits.
12577          */
12578         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12579             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12580                 switch (cacheline_size) {
12581                 case 16:
12582                 case 32:
12583                 case 64:
12584                 case 128:
12585                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12586                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12587                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12588                         } else {
12589                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12590                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12591                         }
12592                         break;
12593
12594                 case 256:
12595                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12596                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12597                         break;
12598
12599                 default:
12600                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12601                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12602                         break;
12603                 }
12604         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12605                 switch (cacheline_size) {
12606                 case 16:
12607                 case 32:
12608                 case 64:
12609                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12610                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12611                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12612                                 break;
12613                         }
12614                         /* fallthrough */
12615                 case 128:
12616                 default:
12617                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12618                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12619                         break;
12620                 }
12621         } else {
12622                 switch (cacheline_size) {
12623                 case 16:
12624                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12625                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12626                                         DMA_RWCTRL_WRITE_BNDRY_16);
12627                                 break;
12628                         }
12629                         /* fallthrough */
12630                 case 32:
12631                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12632                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12633                                         DMA_RWCTRL_WRITE_BNDRY_32);
12634                                 break;
12635                         }
12636                         /* fallthrough */
12637                 case 64:
12638                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12639                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12640                                         DMA_RWCTRL_WRITE_BNDRY_64);
12641                                 break;
12642                         }
12643                         /* fallthrough */
12644                 case 128:
12645                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12646                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12647                                         DMA_RWCTRL_WRITE_BNDRY_128);
12648                                 break;
12649                         }
12650                         /* fallthrough */
12651                 case 256:
12652                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12653                                 DMA_RWCTRL_WRITE_BNDRY_256);
12654                         break;
12655                 case 512:
12656                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12657                                 DMA_RWCTRL_WRITE_BNDRY_512);
12658                         break;
12659                 case 1024:
12660                 default:
12661                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12662                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12663                         break;
12664                 }
12665         }
12666
12667 out:
12668         return val;
12669 }
12670
12671 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12672 {
12673         struct tg3_internal_buffer_desc test_desc;
12674         u32 sram_dma_descs;
12675         int i, ret;
12676
12677         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12678
12679         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12680         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12681         tw32(RDMAC_STATUS, 0);
12682         tw32(WDMAC_STATUS, 0);
12683
12684         tw32(BUFMGR_MODE, 0);
12685         tw32(FTQ_RESET, 0);
12686
12687         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12688         test_desc.addr_lo = buf_dma & 0xffffffff;
12689         test_desc.nic_mbuf = 0x00002100;
12690         test_desc.len = size;
12691
12692         /*
12693          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12694          * the *second* time the tg3 driver was getting loaded after an
12695          * initial scan.
12696          *
12697          * Broadcom tells me:
12698          *   ...the DMA engine is connected to the GRC block and a DMA
12699          *   reset may affect the GRC block in some unpredictable way...
12700          *   The behavior of resets to individual blocks has not been tested.
12701          *
12702          * Broadcom noted the GRC reset will also reset all sub-components.
12703          */
12704         if (to_device) {
12705                 test_desc.cqid_sqid = (13 << 8) | 2;
12706
12707                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12708                 udelay(40);
12709         } else {
12710                 test_desc.cqid_sqid = (16 << 8) | 7;
12711
12712                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12713                 udelay(40);
12714         }
12715         test_desc.flags = 0x00000005;
12716
12717         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12718                 u32 val;
12719
12720                 val = *(((u32 *)&test_desc) + i);
12721                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12722                                        sram_dma_descs + (i * sizeof(u32)));
12723                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12724         }
12725         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12726
12727         if (to_device) {
12728                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12729         } else {
12730                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12731         }
12732
12733         ret = -ENODEV;
12734         for (i = 0; i < 40; i++) {
12735                 u32 val;
12736
12737                 if (to_device)
12738                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12739                 else
12740                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12741                 if ((val & 0xffff) == sram_dma_descs) {
12742                         ret = 0;
12743                         break;
12744                 }
12745
12746                 udelay(100);
12747         }
12748
12749         return ret;
12750 }
12751
12752 #define TEST_BUFFER_SIZE        0x2000
12753
12754 static int __devinit tg3_test_dma(struct tg3 *tp)
12755 {
12756         dma_addr_t buf_dma;
12757         u32 *buf, saved_dma_rwctrl;
12758         int ret;
12759
12760         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12761         if (!buf) {
12762                 ret = -ENOMEM;
12763                 goto out_nofree;
12764         }
12765
12766         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12767                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12768
12769         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12770
12771         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12772                 /* DMA read watermark not used on PCIE */
12773                 tp->dma_rwctrl |= 0x00180000;
12774         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12775                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12776                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12777                         tp->dma_rwctrl |= 0x003f0000;
12778                 else
12779                         tp->dma_rwctrl |= 0x003f000f;
12780         } else {
12781                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12782                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12783                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12784                         u32 read_water = 0x7;
12785
12786                         /* If the 5704 is behind the EPB bridge, we can
12787                          * do the less restrictive ONE_DMA workaround for
12788                          * better performance.
12789                          */
12790                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12791                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12792                                 tp->dma_rwctrl |= 0x8000;
12793                         else if (ccval == 0x6 || ccval == 0x7)
12794                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12795
12796                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12797                                 read_water = 4;
12798                         /* Set bit 23 to enable PCIX hw bug fix */
12799                         tp->dma_rwctrl |=
12800                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12801                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12802                                 (1 << 23);
12803                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12804                         /* 5780 always in PCIX mode */
12805                         tp->dma_rwctrl |= 0x00144000;
12806                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12807                         /* 5714 always in PCIX mode */
12808                         tp->dma_rwctrl |= 0x00148000;
12809                 } else {
12810                         tp->dma_rwctrl |= 0x001b000f;
12811                 }
12812         }
12813
12814         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12815             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12816                 tp->dma_rwctrl &= 0xfffffff0;
12817
12818         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12819             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12820                 /* Remove this if it causes problems for some boards. */
12821                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12822
12823                 /* On 5700/5701 chips, we need to set this bit.
12824                  * Otherwise the chip will issue cacheline transactions
12825                  * to streamable DMA memory with not all the byte
12826                  * enables turned on.  This is an error on several
12827                  * RISC PCI controllers, in particular sparc64.
12828                  *
12829                  * On 5703/5704 chips, this bit has been reassigned
12830                  * a different meaning.  In particular, it is used
12831                  * on those chips to enable a PCI-X workaround.
12832                  */
12833                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12834         }
12835
12836         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12837
12838 #if 0
12839         /* Unneeded, already done by tg3_get_invariants.  */
12840         tg3_switch_clocks(tp);
12841 #endif
12842
12843         ret = 0;
12844         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12845             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12846                 goto out;
12847
12848         /* It is best to perform DMA test with maximum write burst size
12849          * to expose the 5700/5701 write DMA bug.
12850          */
12851         saved_dma_rwctrl = tp->dma_rwctrl;
12852         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12853         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12854
12855         while (1) {
12856                 u32 *p = buf, i;
12857
12858                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12859                         p[i] = i;
12860
12861                 /* Send the buffer to the chip. */
12862                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12863                 if (ret) {
12864                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12865                         break;
12866                 }
12867
12868 #if 0
12869                 /* validate data reached card RAM correctly. */
12870                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12871                         u32 val;
12872                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12873                         if (le32_to_cpu(val) != p[i]) {
12874                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12875                                 /* ret = -ENODEV here? */
12876                         }
12877                         p[i] = 0;
12878                 }
12879 #endif
12880                 /* Now read it back. */
12881                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12882                 if (ret) {
12883                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12884
12885                         break;
12886                 }
12887
12888                 /* Verify it. */
12889                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12890                         if (p[i] == i)
12891                                 continue;
12892
12893                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12894                             DMA_RWCTRL_WRITE_BNDRY_16) {
12895                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12896                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12897                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12898                                 break;
12899                         } else {
12900                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12901                                 ret = -ENODEV;
12902                                 goto out;
12903                         }
12904                 }
12905
12906                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12907                         /* Success. */
12908                         ret = 0;
12909                         break;
12910                 }
12911         }
12912         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12913             DMA_RWCTRL_WRITE_BNDRY_16) {
12914                 static struct pci_device_id dma_wait_state_chipsets[] = {
12915                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12916                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12917                         { },
12918                 };
12919
12920                 /* DMA test passed without adjusting DMA boundary,
12921                  * now look for chipsets that are known to expose the
12922                  * DMA bug without failing the test.
12923                  */
12924                 if (pci_dev_present(dma_wait_state_chipsets)) {
12925                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12926                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12927                 }
12928                 else
12929                         /* Safe to use the calculated DMA boundary. */
12930                         tp->dma_rwctrl = saved_dma_rwctrl;
12931
12932                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12933         }
12934
12935 out:
12936         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12937 out_nofree:
12938         return ret;
12939 }
12940
12941 static void __devinit tg3_init_link_config(struct tg3 *tp)
12942 {
12943         tp->link_config.advertising =
12944                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12945                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12946                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12947                  ADVERTISED_Autoneg | ADVERTISED_MII);
12948         tp->link_config.speed = SPEED_INVALID;
12949         tp->link_config.duplex = DUPLEX_INVALID;
12950         tp->link_config.autoneg = AUTONEG_ENABLE;
12951         tp->link_config.active_speed = SPEED_INVALID;
12952         tp->link_config.active_duplex = DUPLEX_INVALID;
12953         tp->link_config.phy_is_low_power = 0;
12954         tp->link_config.orig_speed = SPEED_INVALID;
12955         tp->link_config.orig_duplex = DUPLEX_INVALID;
12956         tp->link_config.orig_autoneg = AUTONEG_INVALID;
12957 }
12958
12959 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12960 {
12961         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12962                 tp->bufmgr_config.mbuf_read_dma_low_water =
12963                         DEFAULT_MB_RDMA_LOW_WATER_5705;
12964                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12965                         DEFAULT_MB_MACRX_LOW_WATER_5705;
12966                 tp->bufmgr_config.mbuf_high_water =
12967                         DEFAULT_MB_HIGH_WATER_5705;
12968                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12969                         tp->bufmgr_config.mbuf_mac_rx_low_water =
12970                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
12971                         tp->bufmgr_config.mbuf_high_water =
12972                                 DEFAULT_MB_HIGH_WATER_5906;
12973                 }
12974
12975                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12976                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12977                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12978                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12979                 tp->bufmgr_config.mbuf_high_water_jumbo =
12980                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12981         } else {
12982                 tp->bufmgr_config.mbuf_read_dma_low_water =
12983                         DEFAULT_MB_RDMA_LOW_WATER;
12984                 tp->bufmgr_config.mbuf_mac_rx_low_water =
12985                         DEFAULT_MB_MACRX_LOW_WATER;
12986                 tp->bufmgr_config.mbuf_high_water =
12987                         DEFAULT_MB_HIGH_WATER;
12988
12989                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12990                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12991                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12992                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12993                 tp->bufmgr_config.mbuf_high_water_jumbo =
12994                         DEFAULT_MB_HIGH_WATER_JUMBO;
12995         }
12996
12997         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12998         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12999 }
13000
13001 static char * __devinit tg3_phy_string(struct tg3 *tp)
13002 {
13003         switch (tp->phy_id & PHY_ID_MASK) {
13004         case PHY_ID_BCM5400:    return "5400";
13005         case PHY_ID_BCM5401:    return "5401";
13006         case PHY_ID_BCM5411:    return "5411";
13007         case PHY_ID_BCM5701:    return "5701";
13008         case PHY_ID_BCM5703:    return "5703";
13009         case PHY_ID_BCM5704:    return "5704";
13010         case PHY_ID_BCM5705:    return "5705";
13011         case PHY_ID_BCM5750:    return "5750";
13012         case PHY_ID_BCM5752:    return "5752";
13013         case PHY_ID_BCM5714:    return "5714";
13014         case PHY_ID_BCM5780:    return "5780";
13015         case PHY_ID_BCM5755:    return "5755";
13016         case PHY_ID_BCM5787:    return "5787";
13017         case PHY_ID_BCM5784:    return "5784";
13018         case PHY_ID_BCM5756:    return "5722/5756";
13019         case PHY_ID_BCM5906:    return "5906";
13020         case PHY_ID_BCM5761:    return "5761";
13021         case PHY_ID_BCM8002:    return "8002/serdes";
13022         case 0:                 return "serdes";
13023         default:                return "unknown";
13024         }
13025 }
13026
13027 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13028 {
13029         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13030                 strcpy(str, "PCI Express");
13031                 return str;
13032         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13033                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13034
13035                 strcpy(str, "PCIX:");
13036
13037                 if ((clock_ctrl == 7) ||
13038                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13039                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13040                         strcat(str, "133MHz");
13041                 else if (clock_ctrl == 0)
13042                         strcat(str, "33MHz");
13043                 else if (clock_ctrl == 2)
13044                         strcat(str, "50MHz");
13045                 else if (clock_ctrl == 4)
13046                         strcat(str, "66MHz");
13047                 else if (clock_ctrl == 6)
13048                         strcat(str, "100MHz");
13049         } else {
13050                 strcpy(str, "PCI:");
13051                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13052                         strcat(str, "66MHz");
13053                 else
13054                         strcat(str, "33MHz");
13055         }
13056         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13057                 strcat(str, ":32-bit");
13058         else
13059                 strcat(str, ":64-bit");
13060         return str;
13061 }
13062
13063 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13064 {
13065         struct pci_dev *peer;
13066         unsigned int func, devnr = tp->pdev->devfn & ~7;
13067
13068         for (func = 0; func < 8; func++) {
13069                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13070                 if (peer && peer != tp->pdev)
13071                         break;
13072                 pci_dev_put(peer);
13073         }
13074         /* 5704 can be configured in single-port mode, set peer to
13075          * tp->pdev in that case.
13076          */
13077         if (!peer) {
13078                 peer = tp->pdev;
13079                 return peer;
13080         }
13081
13082         /*
13083          * We don't need to keep the refcount elevated; there's no way
13084          * to remove one half of this device without removing the other
13085          */
13086         pci_dev_put(peer);
13087
13088         return peer;
13089 }
13090
13091 static void __devinit tg3_init_coal(struct tg3 *tp)
13092 {
13093         struct ethtool_coalesce *ec = &tp->coal;
13094
13095         memset(ec, 0, sizeof(*ec));
13096         ec->cmd = ETHTOOL_GCOALESCE;
13097         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13098         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13099         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13100         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13101         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13102         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13103         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13104         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13105         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13106
13107         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13108                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13109                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13110                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13111                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13112                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13113         }
13114
13115         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13116                 ec->rx_coalesce_usecs_irq = 0;
13117                 ec->tx_coalesce_usecs_irq = 0;
13118                 ec->stats_block_coalesce_usecs = 0;
13119         }
13120 }
13121
13122 static const struct net_device_ops tg3_netdev_ops = {
13123         .ndo_open               = tg3_open,
13124         .ndo_stop               = tg3_close,
13125         .ndo_start_xmit         = tg3_start_xmit,
13126         .ndo_get_stats          = tg3_get_stats,
13127         .ndo_validate_addr      = eth_validate_addr,
13128         .ndo_set_multicast_list = tg3_set_rx_mode,
13129         .ndo_set_mac_address    = tg3_set_mac_addr,
13130         .ndo_do_ioctl           = tg3_ioctl,
13131         .ndo_tx_timeout         = tg3_tx_timeout,
13132         .ndo_change_mtu         = tg3_change_mtu,
13133 #if TG3_VLAN_TAG_USED
13134         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13135 #endif
13136 #ifdef CONFIG_NET_POLL_CONTROLLER
13137         .ndo_poll_controller    = tg3_poll_controller,
13138 #endif
13139 };
13140
13141 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13142         .ndo_open               = tg3_open,
13143         .ndo_stop               = tg3_close,
13144         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13145         .ndo_get_stats          = tg3_get_stats,
13146         .ndo_validate_addr      = eth_validate_addr,
13147         .ndo_set_multicast_list = tg3_set_rx_mode,
13148         .ndo_set_mac_address    = tg3_set_mac_addr,
13149         .ndo_do_ioctl           = tg3_ioctl,
13150         .ndo_tx_timeout         = tg3_tx_timeout,
13151         .ndo_change_mtu         = tg3_change_mtu,
13152 #if TG3_VLAN_TAG_USED
13153         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13154 #endif
13155 #ifdef CONFIG_NET_POLL_CONTROLLER
13156         .ndo_poll_controller    = tg3_poll_controller,
13157 #endif
13158 };
13159
13160 static int __devinit tg3_init_one(struct pci_dev *pdev,
13161                                   const struct pci_device_id *ent)
13162 {
13163         static int tg3_version_printed = 0;
13164         struct net_device *dev;
13165         struct tg3 *tp;
13166         int err, pm_cap;
13167         char str[40];
13168         u64 dma_mask, persist_dma_mask;
13169
13170         if (tg3_version_printed++ == 0)
13171                 printk(KERN_INFO "%s", version);
13172
13173         err = pci_enable_device(pdev);
13174         if (err) {
13175                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13176                        "aborting.\n");
13177                 return err;
13178         }
13179
13180         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13181         if (err) {
13182                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13183                        "aborting.\n");
13184                 goto err_out_disable_pdev;
13185         }
13186
13187         pci_set_master(pdev);
13188
13189         /* Find power-management capability. */
13190         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13191         if (pm_cap == 0) {
13192                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13193                        "aborting.\n");
13194                 err = -EIO;
13195                 goto err_out_free_res;
13196         }
13197
13198         dev = alloc_etherdev(sizeof(*tp));
13199         if (!dev) {
13200                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13201                 err = -ENOMEM;
13202                 goto err_out_free_res;
13203         }
13204
13205         SET_NETDEV_DEV(dev, &pdev->dev);
13206
13207 #if TG3_VLAN_TAG_USED
13208         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13209 #endif
13210
13211         tp = netdev_priv(dev);
13212         tp->pdev = pdev;
13213         tp->dev = dev;
13214         tp->pm_cap = pm_cap;
13215         tp->rx_mode = TG3_DEF_RX_MODE;
13216         tp->tx_mode = TG3_DEF_TX_MODE;
13217
13218         if (tg3_debug > 0)
13219                 tp->msg_enable = tg3_debug;
13220         else
13221                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13222
13223         /* The word/byte swap controls here control register access byte
13224          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13225          * setting below.
13226          */
13227         tp->misc_host_ctrl =
13228                 MISC_HOST_CTRL_MASK_PCI_INT |
13229                 MISC_HOST_CTRL_WORD_SWAP |
13230                 MISC_HOST_CTRL_INDIR_ACCESS |
13231                 MISC_HOST_CTRL_PCISTATE_RW;
13232
13233         /* The NONFRM (non-frame) byte/word swap controls take effect
13234          * on descriptor entries, anything which isn't packet data.
13235          *
13236          * The StrongARM chips on the board (one for tx, one for rx)
13237          * are running in big-endian mode.
13238          */
13239         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13240                         GRC_MODE_WSWAP_NONFRM_DATA);
13241 #ifdef __BIG_ENDIAN
13242         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13243 #endif
13244         spin_lock_init(&tp->lock);
13245         spin_lock_init(&tp->indirect_lock);
13246         INIT_WORK(&tp->reset_task, tg3_reset_task);
13247
13248         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13249         if (!tp->regs) {
13250                 printk(KERN_ERR PFX "Cannot map device registers, "
13251                        "aborting.\n");
13252                 err = -ENOMEM;
13253                 goto err_out_free_dev;
13254         }
13255
13256         tg3_init_link_config(tp);
13257
13258         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13259         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13260         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13261
13262         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13263         dev->ethtool_ops = &tg3_ethtool_ops;
13264         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13265         dev->irq = pdev->irq;
13266
13267         err = tg3_get_invariants(tp);
13268         if (err) {
13269                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13270                        "aborting.\n");
13271                 goto err_out_iounmap;
13272         }
13273
13274         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13275             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13276                 dev->netdev_ops = &tg3_netdev_ops;
13277         else
13278                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13279
13280
13281         /* The EPB bridge inside 5714, 5715, and 5780 and any
13282          * device behind the EPB cannot support DMA addresses > 40-bit.
13283          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13284          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13285          * do DMA address check in tg3_start_xmit().
13286          */
13287         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13288                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13289         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13290                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13291 #ifdef CONFIG_HIGHMEM
13292                 dma_mask = DMA_BIT_MASK(64);
13293 #endif
13294         } else
13295                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13296
13297         /* Configure DMA attributes. */
13298         if (dma_mask > DMA_BIT_MASK(32)) {
13299                 err = pci_set_dma_mask(pdev, dma_mask);
13300                 if (!err) {
13301                         dev->features |= NETIF_F_HIGHDMA;
13302                         err = pci_set_consistent_dma_mask(pdev,
13303                                                           persist_dma_mask);
13304                         if (err < 0) {
13305                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13306                                        "DMA for consistent allocations\n");
13307                                 goto err_out_iounmap;
13308                         }
13309                 }
13310         }
13311         if (err || dma_mask == DMA_BIT_MASK(32)) {
13312                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13313                 if (err) {
13314                         printk(KERN_ERR PFX "No usable DMA configuration, "
13315                                "aborting.\n");
13316                         goto err_out_iounmap;
13317                 }
13318         }
13319
13320         tg3_init_bufmgr_config(tp);
13321
13322         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13323                 tp->fw_needed = FIRMWARE_TG3;
13324
13325         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13326                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13327         }
13328         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13329             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13330             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13331             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13332             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13333                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13334         } else {
13335                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13336                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13337                         tp->fw_needed = FIRMWARE_TG3TSO5;
13338                 else
13339                         tp->fw_needed = FIRMWARE_TG3TSO;
13340         }
13341
13342         /* TSO is on by default on chips that support hardware TSO.
13343          * Firmware TSO on older chips gives lower performance, so it
13344          * is off by default, but can be enabled using ethtool.
13345          */
13346         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13347                 if (dev->features & NETIF_F_IP_CSUM)
13348                         dev->features |= NETIF_F_TSO;
13349                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13350                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13351                         dev->features |= NETIF_F_TSO6;
13352                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13353                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13354                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13355                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13356                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13357                         dev->features |= NETIF_F_TSO_ECN;
13358         }
13359
13360
13361         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13362             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13363             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13364                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13365                 tp->rx_pending = 63;
13366         }
13367
13368         err = tg3_get_device_address(tp);
13369         if (err) {
13370                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13371                        "aborting.\n");
13372                 goto err_out_fw;
13373         }
13374
13375         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13376                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13377                 if (!tp->aperegs) {
13378                         printk(KERN_ERR PFX "Cannot map APE registers, "
13379                                "aborting.\n");
13380                         err = -ENOMEM;
13381                         goto err_out_fw;
13382                 }
13383
13384                 tg3_ape_lock_init(tp);
13385
13386                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13387                         tg3_read_dash_ver(tp);
13388         }
13389
13390         /*
13391          * Reset chip in case UNDI or EFI driver did not shutdown
13392          * DMA self test will enable WDMAC and we'll see (spurious)
13393          * pending DMA on the PCI bus at that point.
13394          */
13395         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13396             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13397                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13398                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13399         }
13400
13401         err = tg3_test_dma(tp);
13402         if (err) {
13403                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13404                 goto err_out_apeunmap;
13405         }
13406
13407         /* flow control autonegotiation is default behavior */
13408         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13409         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13410
13411         tg3_init_coal(tp);
13412
13413         pci_set_drvdata(pdev, dev);
13414
13415         err = register_netdev(dev);
13416         if (err) {
13417                 printk(KERN_ERR PFX "Cannot register net device, "
13418                        "aborting.\n");
13419                 goto err_out_apeunmap;
13420         }
13421
13422         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13423                dev->name,
13424                tp->board_part_number,
13425                tp->pci_chip_rev_id,
13426                tg3_bus_string(tp, str),
13427                dev->dev_addr);
13428
13429         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13430                 printk(KERN_INFO
13431                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13432                        tp->dev->name,
13433                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13434                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13435         else
13436                 printk(KERN_INFO
13437                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13438                        tp->dev->name, tg3_phy_string(tp),
13439                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13440                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13441                          "10/100/1000Base-T")),
13442                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13443
13444         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13445                dev->name,
13446                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13447                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13448                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13449                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13450                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13451         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13452                dev->name, tp->dma_rwctrl,
13453                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13454                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13455
13456         return 0;
13457
13458 err_out_apeunmap:
13459         if (tp->aperegs) {
13460                 iounmap(tp->aperegs);
13461                 tp->aperegs = NULL;
13462         }
13463
13464 err_out_fw:
13465         if (tp->fw)
13466                 release_firmware(tp->fw);
13467
13468 err_out_iounmap:
13469         if (tp->regs) {
13470                 iounmap(tp->regs);
13471                 tp->regs = NULL;
13472         }
13473
13474 err_out_free_dev:
13475         free_netdev(dev);
13476
13477 err_out_free_res:
13478         pci_release_regions(pdev);
13479
13480 err_out_disable_pdev:
13481         pci_disable_device(pdev);
13482         pci_set_drvdata(pdev, NULL);
13483         return err;
13484 }
13485
13486 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13487 {
13488         struct net_device *dev = pci_get_drvdata(pdev);
13489
13490         if (dev) {
13491                 struct tg3 *tp = netdev_priv(dev);
13492
13493                 if (tp->fw)
13494                         release_firmware(tp->fw);
13495
13496                 flush_scheduled_work();
13497
13498                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13499                         tg3_phy_fini(tp);
13500                         tg3_mdio_fini(tp);
13501                 }
13502
13503                 unregister_netdev(dev);
13504                 if (tp->aperegs) {
13505                         iounmap(tp->aperegs);
13506                         tp->aperegs = NULL;
13507                 }
13508                 if (tp->regs) {
13509                         iounmap(tp->regs);
13510                         tp->regs = NULL;
13511                 }
13512                 free_netdev(dev);
13513                 pci_release_regions(pdev);
13514                 pci_disable_device(pdev);
13515                 pci_set_drvdata(pdev, NULL);
13516         }
13517 }
13518
13519 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13520 {
13521         struct net_device *dev = pci_get_drvdata(pdev);
13522         struct tg3 *tp = netdev_priv(dev);
13523         pci_power_t target_state;
13524         int err;
13525
13526         /* PCI register 4 needs to be saved whether netif_running() or not.
13527          * MSI address and data need to be saved if using MSI and
13528          * netif_running().
13529          */
13530         pci_save_state(pdev);
13531
13532         if (!netif_running(dev))
13533                 return 0;
13534
13535         flush_scheduled_work();
13536         tg3_phy_stop(tp);
13537         tg3_netif_stop(tp);
13538
13539         del_timer_sync(&tp->timer);
13540
13541         tg3_full_lock(tp, 1);
13542         tg3_disable_ints(tp);
13543         tg3_full_unlock(tp);
13544
13545         netif_device_detach(dev);
13546
13547         tg3_full_lock(tp, 0);
13548         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13549         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13550         tg3_full_unlock(tp);
13551
13552         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13553
13554         err = tg3_set_power_state(tp, target_state);
13555         if (err) {
13556                 int err2;
13557
13558                 tg3_full_lock(tp, 0);
13559
13560                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13561                 err2 = tg3_restart_hw(tp, 1);
13562                 if (err2)
13563                         goto out;
13564
13565                 tp->timer.expires = jiffies + tp->timer_offset;
13566                 add_timer(&tp->timer);
13567
13568                 netif_device_attach(dev);
13569                 tg3_netif_start(tp);
13570
13571 out:
13572                 tg3_full_unlock(tp);
13573
13574                 if (!err2)
13575                         tg3_phy_start(tp);
13576         }
13577
13578         return err;
13579 }
13580
13581 static int tg3_resume(struct pci_dev *pdev)
13582 {
13583         struct net_device *dev = pci_get_drvdata(pdev);
13584         struct tg3 *tp = netdev_priv(dev);
13585         int err;
13586
13587         pci_restore_state(tp->pdev);
13588
13589         if (!netif_running(dev))
13590                 return 0;
13591
13592         err = tg3_set_power_state(tp, PCI_D0);
13593         if (err)
13594                 return err;
13595
13596         netif_device_attach(dev);
13597
13598         tg3_full_lock(tp, 0);
13599
13600         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13601         err = tg3_restart_hw(tp, 1);
13602         if (err)
13603                 goto out;
13604
13605         tp->timer.expires = jiffies + tp->timer_offset;
13606         add_timer(&tp->timer);
13607
13608         tg3_netif_start(tp);
13609
13610 out:
13611         tg3_full_unlock(tp);
13612
13613         if (!err)
13614                 tg3_phy_start(tp);
13615
13616         return err;
13617 }
13618
13619 static struct pci_driver tg3_driver = {
13620         .name           = DRV_MODULE_NAME,
13621         .id_table       = tg3_pci_tbl,
13622         .probe          = tg3_init_one,
13623         .remove         = __devexit_p(tg3_remove_one),
13624         .suspend        = tg3_suspend,
13625         .resume         = tg3_resume
13626 };
13627
13628 static int __init tg3_init(void)
13629 {
13630         return pci_register_driver(&tg3_driver);
13631 }
13632
13633 static void __exit tg3_cleanup(void)
13634 {
13635         pci_unregister_driver(&tg3_driver);
13636 }
13637
13638 module_init(tg3_init);
13639 module_exit(tg3_cleanup);