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   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.100"
  72 #define DRV_MODULE_RELDATE      "August 25, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                  TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define TG3_DMA_BYTE_ENAB               64
 129
 130 #define TG3_RX_STD_DMA_SZ               1536
 131 #define TG3_RX_JMB_DMA_SZ               9046
 132
 133 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 134
 135 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 136 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 137
 138 /* minimum number of free TX descriptors required to wake up TX process */
 139 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 140
 141 #define TG3_RAW_IP_ALIGN 2
 142
 143 /* number of ETHTOOL_GSTATS u64's */
 144 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 145
 146 #define TG3_NUM_TEST            6
 147
 148 #define FIRMWARE_TG3            "tigon/tg3.bin"
 149 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 150 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 151
 152 static char version[] __devinitdata =
 153         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 154
 155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 157 MODULE_LICENSE("GPL");
 158 MODULE_VERSION(DRV_MODULE_VERSION);
 159 MODULE_FIRMWARE(FIRMWARE_TG3);
 160 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 162
 163
 164 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 165 module_param(tg3_debug, int, 0);
 166 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 167
 168 static struct pci_device_id tg3_pci_tbl[] = {
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 242         {}
 243 };
 244
 245 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 246
 247 static const struct {
 248         const char string[ETH_GSTRING_LEN];
 249 } ethtool_stats_keys[TG3_NUM_STATS] = {
 250         { "rx_octets" },
 251         { "rx_fragments" },
 252         { "rx_ucast_packets" },
 253         { "rx_mcast_packets" },
 254         { "rx_bcast_packets" },
 255         { "rx_fcs_errors" },
 256         { "rx_align_errors" },
 257         { "rx_xon_pause_rcvd" },
 258         { "rx_xoff_pause_rcvd" },
 259         { "rx_mac_ctrl_rcvd" },
 260         { "rx_xoff_entered" },
 261         { "rx_frame_too_long_errors" },
 262         { "rx_jabbers" },
 263         { "rx_undersize_packets" },
 264         { "rx_in_length_errors" },
 265         { "rx_out_length_errors" },
 266         { "rx_64_or_less_octet_packets" },
 267         { "rx_65_to_127_octet_packets" },
 268         { "rx_128_to_255_octet_packets" },
 269         { "rx_256_to_511_octet_packets" },
 270         { "rx_512_to_1023_octet_packets" },
 271         { "rx_1024_to_1522_octet_packets" },
 272         { "rx_1523_to_2047_octet_packets" },
 273         { "rx_2048_to_4095_octet_packets" },
 274         { "rx_4096_to_8191_octet_packets" },
 275         { "rx_8192_to_9022_octet_packets" },
 276
 277         { "tx_octets" },
 278         { "tx_collisions" },
 279
 280         { "tx_xon_sent" },
 281         { "tx_xoff_sent" },
 282         { "tx_flow_control" },
 283         { "tx_mac_errors" },
 284         { "tx_single_collisions" },
 285         { "tx_mult_collisions" },
 286         { "tx_deferred" },
 287         { "tx_excessive_collisions" },
 288         { "tx_late_collisions" },
 289         { "tx_collide_2times" },
 290         { "tx_collide_3times" },
 291         { "tx_collide_4times" },
 292         { "tx_collide_5times" },
 293         { "tx_collide_6times" },
 294         { "tx_collide_7times" },
 295         { "tx_collide_8times" },
 296         { "tx_collide_9times" },
 297         { "tx_collide_10times" },
 298         { "tx_collide_11times" },
 299         { "tx_collide_12times" },
 300         { "tx_collide_13times" },
 301         { "tx_collide_14times" },
 302         { "tx_collide_15times" },
 303         { "tx_ucast_packets" },
 304         { "tx_mcast_packets" },
 305         { "tx_bcast_packets" },
 306         { "tx_carrier_sense_errors" },
 307         { "tx_discards" },
 308         { "tx_errors" },
 309
 310         { "dma_writeq_full" },
 311         { "dma_write_prioq_full" },
 312         { "rxbds_empty" },
 313         { "rx_discards" },
 314         { "rx_errors" },
 315         { "rx_threshold_hit" },
 316
 317         { "dma_readq_full" },
 318         { "dma_read_prioq_full" },
 319         { "tx_comp_queue_full" },
 320
 321         { "ring_set_send_prod_index" },
 322         { "ring_status_update" },
 323         { "nic_irqs" },
 324         { "nic_avoided_irqs" },
 325         { "nic_tx_threshold_hit" }
 326 };
 327
 328 static const struct {
 329         const char string[ETH_GSTRING_LEN];
 330 } ethtool_test_keys[TG3_NUM_TEST] = {
 331         { "nvram test     (online) " },
 332         { "link test      (online) " },
 333         { "register test  (offline)" },
 334         { "memory test    (offline)" },
 335         { "loopback test  (offline)" },
 336         { "interrupt test (offline)" },
 337 };
 338
 339 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 340 {
 341         writel(val, tp->regs + off);
 342 }
 343
 344 static u32 tg3_read32(struct tg3 *tp, u32 off)
 345 {
 346         return (readl(tp->regs + off));
 347 }
 348
 349 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 350 {
 351         writel(val, tp->aperegs + off);
 352 }
 353
 354 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 355 {
 356         return (readl(tp->aperegs + off));
 357 }
 358
 359 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 360 {
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&tp->indirect_lock, flags);
 364         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 365         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 366         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 367 }
 368
 369 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 370 {
 371         writel(val, tp->regs + off);
 372         readl(tp->regs + off);
 373 }
 374
 375 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 376 {
 377         unsigned long flags;
 378         u32 val;
 379
 380         spin_lock_irqsave(&tp->indirect_lock, flags);
 381         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 382         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 383         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 384         return val;
 385 }
 386
 387 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         unsigned long flags;
 390
 391         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 392                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 393                                        TG3_64BIT_REG_LOW, val);
 394                 return;
 395         }
 396         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 397                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 398                                        TG3_64BIT_REG_LOW, val);
 399                 return;
 400         }
 401
 402         spin_lock_irqsave(&tp->indirect_lock, flags);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 406
 407         /* In indirect mode when disabling interrupts, we also need
 408          * to clear the interrupt bit in the GRC local ctrl register.
 409          */
 410         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 411             (val == 0x1)) {
 412                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 413                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 414         }
 415 }
 416
 417 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 /* usec_wait specifies the wait time in usec when writing to certain registers
 430  * where it is unsafe to read back the register without some delay.
 431  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 432  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 433  */
 434 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 435 {
 436         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 437             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 438                 /* Non-posted methods */
 439                 tp->write32(tp, off, val);
 440         else {
 441                 /* Posted method */
 442                 tg3_write32(tp, off, val);
 443                 if (usec_wait)
 444                         udelay(usec_wait);
 445                 tp->read32(tp, off);
 446         }
 447         /* Wait again after the read for the posted method to guarantee that
 448          * the wait time is met.
 449          */
 450         if (usec_wait)
 451                 udelay(usec_wait);
 452 }
 453
 454 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         tp->write32_mbox(tp, off, val);
 457         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 458             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 459                 tp->read32_mbox(tp, off);
 460 }
 461
 462 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 463 {
 464         void __iomem *mbox = tp->regs + off;
 465         writel(val, mbox);
 466         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 467                 writel(val, mbox);
 468         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 469                 readl(mbox);
 470 }
 471
 472 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 473 {
 474         return (readl(tp->regs + off + GRCMBOX_BASE));
 475 }
 476
 477 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 478 {
 479         writel(val, tp->regs + off + GRCMBOX_BASE);
 480 }
 481
 482 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 483 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 484 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 485 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 486 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 487
 488 #define tw32(reg,val)           tp->write32(tp, reg, val)
 489 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 490 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 491 #define tr32(reg)               tp->read32(tp, reg)
 492
 493 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 494 {
 495         unsigned long flags;
 496
 497         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 498             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 499                 return;
 500
 501         spin_lock_irqsave(&tp->indirect_lock, flags);
 502         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 503                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 505
 506                 /* Always leave this as zero. */
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 508         } else {
 509                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 510                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 511
 512                 /* Always leave this as zero. */
 513                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 514         }
 515         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 516 }
 517
 518 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 519 {
 520         unsigned long flags;
 521
 522         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 523             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 524                 *val = 0;
 525                 return;
 526         }
 527
 528         spin_lock_irqsave(&tp->indirect_lock, flags);
 529         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 530                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 531                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 532
 533                 /* Always leave this as zero. */
 534                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 535         } else {
 536                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 537                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 538
 539                 /* Always leave this as zero. */
 540                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 541         }
 542         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 543 }
 544
 545 static void tg3_ape_lock_init(struct tg3 *tp)
 546 {
 547         int i;
 548
 549         /* Make sure the driver hasn't any stale locks. */
 550         for (i = 0; i < 8; i++)
 551                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 552                                 APE_LOCK_GRANT_DRIVER);
 553 }
 554
 555 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 556 {
 557         int i, off;
 558         int ret = 0;
 559         u32 status;
 560
 561         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 562                 return 0;
 563
 564         switch (locknum) {
 565                 case TG3_APE_LOCK_GRC:
 566                 case TG3_APE_LOCK_MEM:
 567                         break;
 568                 default:
 569                         return -EINVAL;
 570         }
 571
 572         off = 4 * locknum;
 573
 574         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 575
 576         /* Wait for up to 1 millisecond to acquire lock. */
 577         for (i = 0; i < 100; i++) {
 578                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 579                 if (status == APE_LOCK_GRANT_DRIVER)
 580                         break;
 581                 udelay(10);
 582         }
 583
 584         if (status != APE_LOCK_GRANT_DRIVER) {
 585                 /* Revoke the lock request. */
 586                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 587                                 APE_LOCK_GRANT_DRIVER);
 588
 589                 ret = -EBUSY;
 590         }
 591
 592         return ret;
 593 }
 594
 595 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 596 {
 597         int off;
 598
 599         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 600                 return;
 601
 602         switch (locknum) {
 603                 case TG3_APE_LOCK_GRC:
 604                 case TG3_APE_LOCK_MEM:
 605                         break;
 606                 default:
 607                         return;
 608         }
 609
 610         off = 4 * locknum;
 611         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 612 }
 613
 614 static void tg3_disable_ints(struct tg3 *tp)
 615 {
 616         tw32(TG3PCI_MISC_HOST_CTRL,
 617              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 618         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 619 }
 620
 621 static inline void tg3_cond_int(struct tg3 *tp)
 622 {
 623         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 624             (tp->hw_status->status & SD_STATUS_UPDATED))
 625                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 626         else
 627                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 628                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 629 }
 630
 631 static void tg3_enable_ints(struct tg3 *tp)
 632 {
 633         tp->irq_sync = 0;
 634         wmb();
 635
 636         tw32(TG3PCI_MISC_HOST_CTRL,
 637              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 638         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 639                        (tp->last_tag << 24));
 640         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 641                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 642                                (tp->last_tag << 24));
 643         tg3_cond_int(tp);
 644 }
 645
 646 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 647 {
 648         struct tg3 *tp = tnapi->tp;
 649         struct tg3_hw_status *sblk = tp->hw_status;
 650         unsigned int work_exists = 0;
 651
 652         /* check for phy events */
 653         if (!(tp->tg3_flags &
 654               (TG3_FLAG_USE_LINKCHG_REG |
 655                TG3_FLAG_POLL_SERDES))) {
 656                 if (sblk->status & SD_STATUS_LINK_CHG)
 657                         work_exists = 1;
 658         }
 659         /* check for RX/TX work to do */
 660         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 661             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 662                 work_exists = 1;
 663
 664         return work_exists;
 665 }
 666
 667 /* tg3_int_reenable
 668  *  similar to tg3_enable_ints, but it accurately determines whether there
 669  *  is new work pending and can return without flushing the PIO write
 670  *  which reenables interrupts
 671  */
 672 static void tg3_int_reenable(struct tg3_napi *tnapi)
 673 {
 674         struct tg3 *tp = tnapi->tp;
 675
 676         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 677                      tp->last_tag << 24);
 678         mmiowb();
 679
 680         /* When doing tagged status, this work check is unnecessary.
 681          * The last_tag we write above tells the chip which piece of
 682          * work we've completed.
 683          */
 684         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 685             tg3_has_work(tnapi))
 686                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 687                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 688 }
 689
 690 static inline void tg3_netif_stop(struct tg3 *tp)
 691 {
 692         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 693         napi_disable(&tp->napi[0].napi);
 694         netif_tx_disable(tp->dev);
 695 }
 696
 697 static inline void tg3_netif_start(struct tg3 *tp)
 698 {
 699         netif_wake_queue(tp->dev);
 700         /* NOTE: unconditional netif_wake_queue is only appropriate
 701          * so long as all callers are assured to have free tx slots
 702          * (such as after tg3_init_hw)
 703          */
 704         napi_enable(&tp->napi[0].napi);
 705         tp->hw_status->status |= SD_STATUS_UPDATED;
 706         tg3_enable_ints(tp);
 707 }
 708
 709 static void tg3_switch_clocks(struct tg3 *tp)
 710 {
 711         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 712         u32 orig_clock_ctrl;
 713
 714         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 715             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 716                 return;
 717
 718         orig_clock_ctrl = clock_ctrl;
 719         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 720                        CLOCK_CTRL_CLKRUN_OENABLE |
 721                        0x1f);
 722         tp->pci_clock_ctrl = clock_ctrl;
 723
 724         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 725                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 726                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 727                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 728                 }
 729         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 730                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 731                             clock_ctrl |
 732                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 733                             40);
 734                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 735                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 736                             40);
 737         }
 738         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 739 }
 740
 741 #define PHY_BUSY_LOOPS  5000
 742
 743 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 744 {
 745         u32 frame_val;
 746         unsigned int loops;
 747         int ret;
 748
 749         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 750                 tw32_f(MAC_MI_MODE,
 751                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 752                 udelay(80);
 753         }
 754
 755         *val = 0x0;
 756
 757         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 758                       MI_COM_PHY_ADDR_MASK);
 759         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 760                       MI_COM_REG_ADDR_MASK);
 761         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 762
 763         tw32_f(MAC_MI_COM, frame_val);
 764
 765         loops = PHY_BUSY_LOOPS;
 766         while (loops != 0) {
 767                 udelay(10);
 768                 frame_val = tr32(MAC_MI_COM);
 769
 770                 if ((frame_val & MI_COM_BUSY) == 0) {
 771                         udelay(5);
 772                         frame_val = tr32(MAC_MI_COM);
 773                         break;
 774                 }
 775                 loops -= 1;
 776         }
 777
 778         ret = -EBUSY;
 779         if (loops != 0) {
 780                 *val = frame_val & MI_COM_DATA_MASK;
 781                 ret = 0;
 782         }
 783
 784         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 785                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 786                 udelay(80);
 787         }
 788
 789         return ret;
 790 }
 791
 792 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 793 {
 794         u32 frame_val;
 795         unsigned int loops;
 796         int ret;
 797
 798         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 799             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 800                 return 0;
 801
 802         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 803                 tw32_f(MAC_MI_MODE,
 804                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 805                 udelay(80);
 806         }
 807
 808         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 809                       MI_COM_PHY_ADDR_MASK);
 810         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 811                       MI_COM_REG_ADDR_MASK);
 812         frame_val |= (val & MI_COM_DATA_MASK);
 813         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 814
 815         tw32_f(MAC_MI_COM, frame_val);
 816
 817         loops = PHY_BUSY_LOOPS;
 818         while (loops != 0) {
 819                 udelay(10);
 820                 frame_val = tr32(MAC_MI_COM);
 821                 if ((frame_val & MI_COM_BUSY) == 0) {
 822                         udelay(5);
 823                         frame_val = tr32(MAC_MI_COM);
 824                         break;
 825                 }
 826                 loops -= 1;
 827         }
 828
 829         ret = -EBUSY;
 830         if (loops != 0)
 831                 ret = 0;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 835                 udelay(80);
 836         }
 837
 838         return ret;
 839 }
 840
 841 static int tg3_bmcr_reset(struct tg3 *tp)
 842 {
 843         u32 phy_control;
 844         int limit, err;
 845
 846         /* OK, reset it, and poll the BMCR_RESET bit until it
 847          * clears or we time out.
 848          */
 849         phy_control = BMCR_RESET;
 850         err = tg3_writephy(tp, MII_BMCR, phy_control);
 851         if (err != 0)
 852                 return -EBUSY;
 853
 854         limit = 5000;
 855         while (limit--) {
 856                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 857                 if (err != 0)
 858                         return -EBUSY;
 859
 860                 if ((phy_control & BMCR_RESET) == 0) {
 861                         udelay(40);
 862                         break;
 863                 }
 864                 udelay(10);
 865         }
 866         if (limit < 0)
 867                 return -EBUSY;
 868
 869         return 0;
 870 }
 871
 872 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 873 {
 874         struct tg3 *tp = bp->priv;
 875         u32 val;
 876
 877         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 878                 return -EAGAIN;
 879
 880         if (tg3_readphy(tp, reg, &val))
 881                 return -EIO;
 882
 883         return val;
 884 }
 885
 886 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 887 {
 888         struct tg3 *tp = bp->priv;
 889
 890         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 891                 return -EAGAIN;
 892
 893         if (tg3_writephy(tp, reg, val))
 894                 return -EIO;
 895
 896         return 0;
 897 }
 898
 899 static int tg3_mdio_reset(struct mii_bus *bp)
 900 {
 901         return 0;
 902 }
 903
 904 static void tg3_mdio_config_5785(struct tg3 *tp)
 905 {
 906         u32 val;
 907         struct phy_device *phydev;
 908
 909         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 910         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 911         case TG3_PHY_ID_BCM50610:
 912                 val = MAC_PHYCFG2_50610_LED_MODES;
 913                 break;
 914         case TG3_PHY_ID_BCMAC131:
 915                 val = MAC_PHYCFG2_AC131_LED_MODES;
 916                 break;
 917         case TG3_PHY_ID_RTL8211C:
 918                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 919                 break;
 920         case TG3_PHY_ID_RTL8201E:
 921                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 922                 break;
 923         default:
 924                 return;
 925         }
 926
 927         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 928                 tw32(MAC_PHYCFG2, val);
 929
 930                 val = tr32(MAC_PHYCFG1);
 931                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 932                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 933                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 934                 tw32(MAC_PHYCFG1, val);
 935
 936                 return;
 937         }
 938
 939         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 940                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 941                        MAC_PHYCFG2_FMODE_MASK_MASK |
 942                        MAC_PHYCFG2_GMODE_MASK_MASK |
 943                        MAC_PHYCFG2_ACT_MASK_MASK   |
 944                        MAC_PHYCFG2_QUAL_MASK_MASK |
 945                        MAC_PHYCFG2_INBAND_ENABLE;
 946
 947         tw32(MAC_PHYCFG2, val);
 948
 949         val = tr32(MAC_PHYCFG1);
 950         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 951                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 952         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 953                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 954                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 955                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 956                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 957         }
 958         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 959                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 960         tw32(MAC_PHYCFG1, val);
 961
 962         val = tr32(MAC_EXT_RGMII_MODE);
 963         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 964                  MAC_RGMII_MODE_RX_QUALITY |
 965                  MAC_RGMII_MODE_RX_ACTIVITY |
 966                  MAC_RGMII_MODE_RX_ENG_DET |
 967                  MAC_RGMII_MODE_TX_ENABLE |
 968                  MAC_RGMII_MODE_TX_LOWPWR |
 969                  MAC_RGMII_MODE_TX_RESET);
 970         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 971                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 972                         val |= MAC_RGMII_MODE_RX_INT_B |
 973                                MAC_RGMII_MODE_RX_QUALITY |
 974                                MAC_RGMII_MODE_RX_ACTIVITY |
 975                                MAC_RGMII_MODE_RX_ENG_DET;
 976                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 977                         val |= MAC_RGMII_MODE_TX_ENABLE |
 978                                MAC_RGMII_MODE_TX_LOWPWR |
 979                                MAC_RGMII_MODE_TX_RESET;
 980         }
 981         tw32(MAC_EXT_RGMII_MODE, val);
 982 }
 983
 984 static void tg3_mdio_start(struct tg3 *tp)
 985 {
 986         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 987                 mutex_lock(&tp->mdio_bus->mdio_lock);
 988                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 989                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 990         }
 991
 992         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 993         tw32_f(MAC_MI_MODE, tp->mi_mode);
 994         udelay(80);
 995
 996         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 998                 tg3_mdio_config_5785(tp);
 999 }
1000
1001 static void tg3_mdio_stop(struct tg3 *tp)
1002 {
1003         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1004                 mutex_lock(&tp->mdio_bus->mdio_lock);
1005                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1006                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1007         }
1008 }
1009
1010 static int tg3_mdio_init(struct tg3 *tp)
1011 {
1012         int i;
1013         u32 reg;
1014         struct phy_device *phydev;
1015
1016         tg3_mdio_start(tp);
1017
1018         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1019             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1020                 return 0;
1021
1022         tp->mdio_bus = mdiobus_alloc();
1023         if (tp->mdio_bus == NULL)
1024                 return -ENOMEM;
1025
1026         tp->mdio_bus->name     = "tg3 mdio bus";
1027         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1028                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1029         tp->mdio_bus->priv     = tp;
1030         tp->mdio_bus->parent   = &tp->pdev->dev;
1031         tp->mdio_bus->read     = &tg3_mdio_read;
1032         tp->mdio_bus->write    = &tg3_mdio_write;
1033         tp->mdio_bus->reset    = &tg3_mdio_reset;
1034         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1035         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1036
1037         for (i = 0; i < PHY_MAX_ADDR; i++)
1038                 tp->mdio_bus->irq[i] = PHY_POLL;
1039
1040         /* The bus registration will look for all the PHYs on the mdio bus.
1041          * Unfortunately, it does not ensure the PHY is powered up before
1042          * accessing the PHY ID registers.  A chip reset is the
1043          * quickest way to bring the device back to an operational state..
1044          */
1045         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1046                 tg3_bmcr_reset(tp);
1047
1048         i = mdiobus_register(tp->mdio_bus);
1049         if (i) {
1050                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1051                         tp->dev->name, i);
1052                 mdiobus_free(tp->mdio_bus);
1053                 return i;
1054         }
1055
1056         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1057
1058         if (!phydev || !phydev->drv) {
1059                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1060                 mdiobus_unregister(tp->mdio_bus);
1061                 mdiobus_free(tp->mdio_bus);
1062                 return -ENODEV;
1063         }
1064
1065         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1066         case TG3_PHY_ID_BCM57780:
1067                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1068                 break;
1069         case TG3_PHY_ID_BCM50610:
1070                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1071                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1072                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1073                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1074                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1075                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1076                 /* fallthru */
1077         case TG3_PHY_ID_RTL8211C:
1078                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1079                 break;
1080         case TG3_PHY_ID_RTL8201E:
1081         case TG3_PHY_ID_BCMAC131:
1082                 phydev->interface = PHY_INTERFACE_MODE_MII;
1083                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1084                 break;
1085         }
1086
1087         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1090                 tg3_mdio_config_5785(tp);
1091
1092         return 0;
1093 }
1094
1095 static void tg3_mdio_fini(struct tg3 *tp)
1096 {
1097         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1098                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1099                 mdiobus_unregister(tp->mdio_bus);
1100                 mdiobus_free(tp->mdio_bus);
1101                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1102         }
1103 }
1104
1105 /* tp->lock is held. */
1106 static inline void tg3_generate_fw_event(struct tg3 *tp)
1107 {
1108         u32 val;
1109
1110         val = tr32(GRC_RX_CPU_EVENT);
1111         val |= GRC_RX_CPU_DRIVER_EVENT;
1112         tw32_f(GRC_RX_CPU_EVENT, val);
1113
1114         tp->last_event_jiffies = jiffies;
1115 }
1116
1117 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1118
1119 /* tp->lock is held. */
1120 static void tg3_wait_for_event_ack(struct tg3 *tp)
1121 {
1122         int i;
1123         unsigned int delay_cnt;
1124         long time_remain;
1125
1126         /* If enough time has passed, no wait is necessary. */
1127         time_remain = (long)(tp->last_event_jiffies + 1 +
1128                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1129                       (long)jiffies;
1130         if (time_remain < 0)
1131                 return;
1132
1133         /* Check if we can shorten the wait time. */
1134         delay_cnt = jiffies_to_usecs(time_remain);
1135         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1136                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1137         delay_cnt = (delay_cnt >> 3) + 1;
1138
1139         for (i = 0; i < delay_cnt; i++) {
1140                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1141                         break;
1142                 udelay(8);
1143         }
1144 }
1145
1146 /* tp->lock is held. */
1147 static void tg3_ump_link_report(struct tg3 *tp)
1148 {
1149         u32 reg;
1150         u32 val;
1151
1152         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1153             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1154                 return;
1155
1156         tg3_wait_for_event_ack(tp);
1157
1158         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1159
1160         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1161
1162         val = 0;
1163         if (!tg3_readphy(tp, MII_BMCR, &reg))
1164                 val = reg << 16;
1165         if (!tg3_readphy(tp, MII_BMSR, &reg))
1166                 val |= (reg & 0xffff);
1167         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1168
1169         val = 0;
1170         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1171                 val = reg << 16;
1172         if (!tg3_readphy(tp, MII_LPA, &reg))
1173                 val |= (reg & 0xffff);
1174         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1175
1176         val = 0;
1177         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1178                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1179                         val = reg << 16;
1180                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1181                         val |= (reg & 0xffff);
1182         }
1183         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1184
1185         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1186                 val = reg << 16;
1187         else
1188                 val = 0;
1189         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1190
1191         tg3_generate_fw_event(tp);
1192 }
1193
1194 static void tg3_link_report(struct tg3 *tp)
1195 {
1196         if (!netif_carrier_ok(tp->dev)) {
1197                 if (netif_msg_link(tp))
1198                         printk(KERN_INFO PFX "%s: Link is down.\n",
1199                                tp->dev->name);
1200                 tg3_ump_link_report(tp);
1201         } else if (netif_msg_link(tp)) {
1202                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1203                        tp->dev->name,
1204                        (tp->link_config.active_speed == SPEED_1000 ?
1205                         1000 :
1206                         (tp->link_config.active_speed == SPEED_100 ?
1207                          100 : 10)),
1208                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1209                         "full" : "half"));
1210
1211                 printk(KERN_INFO PFX
1212                        "%s: Flow control is %s for TX and %s for RX.\n",
1213                        tp->dev->name,
1214                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1215                        "on" : "off",
1216                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1217                        "on" : "off");
1218                 tg3_ump_link_report(tp);
1219         }
1220 }
1221
1222 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1223 {
1224         u16 miireg;
1225
1226         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1227                 miireg = ADVERTISE_PAUSE_CAP;
1228         else if (flow_ctrl & FLOW_CTRL_TX)
1229                 miireg = ADVERTISE_PAUSE_ASYM;
1230         else if (flow_ctrl & FLOW_CTRL_RX)
1231                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1232         else
1233                 miireg = 0;
1234
1235         return miireg;
1236 }
1237
1238 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1239 {
1240         u16 miireg;
1241
1242         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1243                 miireg = ADVERTISE_1000XPAUSE;
1244         else if (flow_ctrl & FLOW_CTRL_TX)
1245                 miireg = ADVERTISE_1000XPSE_ASYM;
1246         else if (flow_ctrl & FLOW_CTRL_RX)
1247                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1248         else
1249                 miireg = 0;
1250
1251         return miireg;
1252 }
1253
1254 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1255 {
1256         u8 cap = 0;
1257
1258         if (lcladv & ADVERTISE_1000XPAUSE) {
1259                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1260                         if (rmtadv & LPA_1000XPAUSE)
1261                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1262                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1263                                 cap = FLOW_CTRL_RX;
1264                 } else {
1265                         if (rmtadv & LPA_1000XPAUSE)
1266                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1267                 }
1268         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1269                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1270                         cap = FLOW_CTRL_TX;
1271         }
1272
1273         return cap;
1274 }
1275
1276 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1277 {
1278         u8 autoneg;
1279         u8 flowctrl = 0;
1280         u32 old_rx_mode = tp->rx_mode;
1281         u32 old_tx_mode = tp->tx_mode;
1282
1283         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1284                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1285         else
1286                 autoneg = tp->link_config.autoneg;
1287
1288         if (autoneg == AUTONEG_ENABLE &&
1289             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1290                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1291                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1292                 else
1293                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1294         } else
1295                 flowctrl = tp->link_config.flowctrl;
1296
1297         tp->link_config.active_flowctrl = flowctrl;
1298
1299         if (flowctrl & FLOW_CTRL_RX)
1300                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1301         else
1302                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1303
1304         if (old_rx_mode != tp->rx_mode)
1305                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1306
1307         if (flowctrl & FLOW_CTRL_TX)
1308                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1309         else
1310                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1311
1312         if (old_tx_mode != tp->tx_mode)
1313                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1314 }
1315
1316 static void tg3_adjust_link(struct net_device *dev)
1317 {
1318         u8 oldflowctrl, linkmesg = 0;
1319         u32 mac_mode, lcl_adv, rmt_adv;
1320         struct tg3 *tp = netdev_priv(dev);
1321         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1322
1323         spin_lock(&tp->lock);
1324
1325         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1326                                     MAC_MODE_HALF_DUPLEX);
1327
1328         oldflowctrl = tp->link_config.active_flowctrl;
1329
1330         if (phydev->link) {
1331                 lcl_adv = 0;
1332                 rmt_adv = 0;
1333
1334                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1335                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1336                 else
1337                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1338
1339                 if (phydev->duplex == DUPLEX_HALF)
1340                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1341                 else {
1342                         lcl_adv = tg3_advert_flowctrl_1000T(
1343                                   tp->link_config.flowctrl);
1344
1345                         if (phydev->pause)
1346                                 rmt_adv = LPA_PAUSE_CAP;
1347                         if (phydev->asym_pause)
1348                                 rmt_adv |= LPA_PAUSE_ASYM;
1349                 }
1350
1351                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1352         } else
1353                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1354
1355         if (mac_mode != tp->mac_mode) {
1356                 tp->mac_mode = mac_mode;
1357                 tw32_f(MAC_MODE, tp->mac_mode);
1358                 udelay(40);
1359         }
1360
1361         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1362                 if (phydev->speed == SPEED_10)
1363                         tw32(MAC_MI_STAT,
1364                              MAC_MI_STAT_10MBPS_MODE |
1365                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1366                 else
1367                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1368         }
1369
1370         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1371                 tw32(MAC_TX_LENGTHS,
1372                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1373                       (6 << TX_LENGTHS_IPG_SHIFT) |
1374                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1375         else
1376                 tw32(MAC_TX_LENGTHS,
1377                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1378                       (6 << TX_LENGTHS_IPG_SHIFT) |
1379                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1380
1381         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1382             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1383             phydev->speed != tp->link_config.active_speed ||
1384             phydev->duplex != tp->link_config.active_duplex ||
1385             oldflowctrl != tp->link_config.active_flowctrl)
1386             linkmesg = 1;
1387
1388         tp->link_config.active_speed = phydev->speed;
1389         tp->link_config.active_duplex = phydev->duplex;
1390
1391         spin_unlock(&tp->lock);
1392
1393         if (linkmesg)
1394                 tg3_link_report(tp);
1395 }
1396
1397 static int tg3_phy_init(struct tg3 *tp)
1398 {
1399         struct phy_device *phydev;
1400
1401         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1402                 return 0;
1403
1404         /* Bring the PHY back to a known state. */
1405         tg3_bmcr_reset(tp);
1406
1407         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1408
1409         /* Attach the MAC to the PHY. */
1410         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1411                              phydev->dev_flags, phydev->interface);
1412         if (IS_ERR(phydev)) {
1413                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1414                 return PTR_ERR(phydev);
1415         }
1416
1417         /* Mask with MAC supported features. */
1418         switch (phydev->interface) {
1419         case PHY_INTERFACE_MODE_GMII:
1420         case PHY_INTERFACE_MODE_RGMII:
1421                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1422                         phydev->supported &= (PHY_GBIT_FEATURES |
1423                                               SUPPORTED_Pause |
1424                                               SUPPORTED_Asym_Pause);
1425                         break;
1426                 }
1427                 /* fallthru */
1428         case PHY_INTERFACE_MODE_MII:
1429                 phydev->supported &= (PHY_BASIC_FEATURES |
1430                                       SUPPORTED_Pause |
1431                                       SUPPORTED_Asym_Pause);
1432                 break;
1433         default:
1434                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1435                 return -EINVAL;
1436         }
1437
1438         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1439
1440         phydev->advertising = phydev->supported;
1441
1442         return 0;
1443 }
1444
1445 static void tg3_phy_start(struct tg3 *tp)
1446 {
1447         struct phy_device *phydev;
1448
1449         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1450                 return;
1451
1452         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1453
1454         if (tp->link_config.phy_is_low_power) {
1455                 tp->link_config.phy_is_low_power = 0;
1456                 phydev->speed = tp->link_config.orig_speed;
1457                 phydev->duplex = tp->link_config.orig_duplex;
1458                 phydev->autoneg = tp->link_config.orig_autoneg;
1459                 phydev->advertising = tp->link_config.orig_advertising;
1460         }
1461
1462         phy_start(phydev);
1463
1464         phy_start_aneg(phydev);
1465 }
1466
1467 static void tg3_phy_stop(struct tg3 *tp)
1468 {
1469         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1470                 return;
1471
1472         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1473 }
1474
1475 static void tg3_phy_fini(struct tg3 *tp)
1476 {
1477         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1478                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1479                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1480         }
1481 }
1482
1483 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1484 {
1485         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1486         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1487 }
1488
1489 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1490 {
1491         u32 phytest;
1492
1493         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1494                 u32 phy;
1495
1496                 tg3_writephy(tp, MII_TG3_FET_TEST,
1497                              phytest | MII_TG3_FET_SHADOW_EN);
1498                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1499                         if (enable)
1500                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1501                         else
1502                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1503                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1504                 }
1505                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1506         }
1507 }
1508
1509 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1510 {
1511         u32 reg;
1512
1513         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1514                 return;
1515
1516         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1517                 tg3_phy_fet_toggle_apd(tp, enable);
1518                 return;
1519         }
1520
1521         reg = MII_TG3_MISC_SHDW_WREN |
1522               MII_TG3_MISC_SHDW_SCR5_SEL |
1523               MII_TG3_MISC_SHDW_SCR5_LPED |
1524               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1525               MII_TG3_MISC_SHDW_SCR5_SDTL |
1526               MII_TG3_MISC_SHDW_SCR5_C125OE;
1527         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1528                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1529
1530         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1531
1532
1533         reg = MII_TG3_MISC_SHDW_WREN |
1534               MII_TG3_MISC_SHDW_APD_SEL |
1535               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1536         if (enable)
1537                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1538
1539         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1540 }
1541
1542 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1543 {
1544         u32 phy;
1545
1546         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1547             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1548                 return;
1549
1550         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1551                 u32 ephy;
1552
1553                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1554                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1555
1556                         tg3_writephy(tp, MII_TG3_FET_TEST,
1557                                      ephy | MII_TG3_FET_SHADOW_EN);
1558                         if (!tg3_readphy(tp, reg, &phy)) {
1559                                 if (enable)
1560                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1561                                 else
1562                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1563                                 tg3_writephy(tp, reg, phy);
1564                         }
1565                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1566                 }
1567         } else {
1568                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1569                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1570                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1571                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1572                         if (enable)
1573                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1574                         else
1575                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1576                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1577                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1578                 }
1579         }
1580 }
1581
1582 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1583 {
1584         u32 val;
1585
1586         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1587                 return;
1588
1589         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1590             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1591                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1592                              (val | (1 << 15) | (1 << 4)));
1593 }
1594
1595 static void tg3_phy_apply_otp(struct tg3 *tp)
1596 {
1597         u32 otp, phy;
1598
1599         if (!tp->phy_otp)
1600                 return;
1601
1602         otp = tp->phy_otp;
1603
1604         /* Enable SM_DSP clock and tx 6dB coding. */
1605         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1606               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1607               MII_TG3_AUXCTL_ACTL_TX_6DB;
1608         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1609
1610         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1611         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1612         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1613
1614         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1615               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1616         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1617
1618         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1619         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1620         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1621
1622         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1623         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1624
1625         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1626         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1627
1628         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1629               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1630         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1631
1632         /* Turn off SM_DSP clock. */
1633         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1634               MII_TG3_AUXCTL_ACTL_TX_6DB;
1635         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1636 }
1637
1638 static int tg3_wait_macro_done(struct tg3 *tp)
1639 {
1640         int limit = 100;
1641
1642         while (limit--) {
1643                 u32 tmp32;
1644
1645                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1646                         if ((tmp32 & 0x1000) == 0)
1647                                 break;
1648                 }
1649         }
1650         if (limit < 0)
1651                 return -EBUSY;
1652
1653         return 0;
1654 }
1655
1656 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1657 {
1658         static const u32 test_pat[4][6] = {
1659         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1660         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1661         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1662         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1663         };
1664         int chan;
1665
1666         for (chan = 0; chan < 4; chan++) {
1667                 int i;
1668
1669                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1670                              (chan * 0x2000) | 0x0200);
1671                 tg3_writephy(tp, 0x16, 0x0002);
1672
1673                 for (i = 0; i < 6; i++)
1674                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1675                                      test_pat[chan][i]);
1676
1677                 tg3_writephy(tp, 0x16, 0x0202);
1678                 if (tg3_wait_macro_done(tp)) {
1679                         *resetp = 1;
1680                         return -EBUSY;
1681                 }
1682
1683                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1684                              (chan * 0x2000) | 0x0200);
1685                 tg3_writephy(tp, 0x16, 0x0082);
1686                 if (tg3_wait_macro_done(tp)) {
1687                         *resetp = 1;
1688                         return -EBUSY;
1689                 }
1690
1691                 tg3_writephy(tp, 0x16, 0x0802);
1692                 if (tg3_wait_macro_done(tp)) {
1693                         *resetp = 1;
1694                         return -EBUSY;
1695                 }
1696
1697                 for (i = 0; i < 6; i += 2) {
1698                         u32 low, high;
1699
1700                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1701                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1702                             tg3_wait_macro_done(tp)) {
1703                                 *resetp = 1;
1704                                 return -EBUSY;
1705                         }
1706                         low &= 0x7fff;
1707                         high &= 0x000f;
1708                         if (low != test_pat[chan][i] ||
1709                             high != test_pat[chan][i+1]) {
1710                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1711                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1712                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1713
1714                                 return -EBUSY;
1715                         }
1716                 }
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1723 {
1724         int chan;
1725
1726         for (chan = 0; chan < 4; chan++) {
1727                 int i;
1728
1729                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1730                              (chan * 0x2000) | 0x0200);
1731                 tg3_writephy(tp, 0x16, 0x0002);
1732                 for (i = 0; i < 6; i++)
1733                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1734                 tg3_writephy(tp, 0x16, 0x0202);
1735                 if (tg3_wait_macro_done(tp))
1736                         return -EBUSY;
1737         }
1738
1739         return 0;
1740 }
1741
1742 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1743 {
1744         u32 reg32, phy9_orig;
1745         int retries, do_phy_reset, err;
1746
1747         retries = 10;
1748         do_phy_reset = 1;
1749         do {
1750                 if (do_phy_reset) {
1751                         err = tg3_bmcr_reset(tp);
1752                         if (err)
1753                                 return err;
1754                         do_phy_reset = 0;
1755                 }
1756
1757                 /* Disable transmitter and interrupt.  */
1758                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1759                         continue;
1760
1761                 reg32 |= 0x3000;
1762                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1763
1764                 /* Set full-duplex, 1000 mbps.  */
1765                 tg3_writephy(tp, MII_BMCR,
1766                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1767
1768                 /* Set to master mode.  */
1769                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1770                         continue;
1771
1772                 tg3_writephy(tp, MII_TG3_CTRL,
1773                              (MII_TG3_CTRL_AS_MASTER |
1774                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1775
1776                 /* Enable SM_DSP_CLOCK and 6dB.  */
1777                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1778
1779                 /* Block the PHY control access.  */
1780                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1781                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1782
1783                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1784                 if (!err)
1785                         break;
1786         } while (--retries);
1787
1788         err = tg3_phy_reset_chanpat(tp);
1789         if (err)
1790                 return err;
1791
1792         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1793         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1794
1795         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1796         tg3_writephy(tp, 0x16, 0x0000);
1797
1798         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1799             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1800                 /* Set Extended packet length bit for jumbo frames */
1801                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1802         }
1803         else {
1804                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1805         }
1806
1807         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1808
1809         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1810                 reg32 &= ~0x3000;
1811                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1812         } else if (!err)
1813                 err = -EBUSY;
1814
1815         return err;
1816 }
1817
1818 /* This will reset the tigon3 PHY if there is no valid
1819  * link unless the FORCE argument is non-zero.
1820  */
1821 static int tg3_phy_reset(struct tg3 *tp)
1822 {
1823         u32 cpmuctrl;
1824         u32 phy_status;
1825         int err;
1826
1827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1828                 u32 val;
1829
1830                 val = tr32(GRC_MISC_CFG);
1831                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1832                 udelay(40);
1833         }
1834         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1835         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1836         if (err != 0)
1837                 return -EBUSY;
1838
1839         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1840                 netif_carrier_off(tp->dev);
1841                 tg3_link_report(tp);
1842         }
1843
1844         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1847                 err = tg3_phy_reset_5703_4_5(tp);
1848                 if (err)
1849                         return err;
1850                 goto out;
1851         }
1852
1853         cpmuctrl = 0;
1854         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1855             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1856                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1857                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1858                         tw32(TG3_CPMU_CTRL,
1859                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1860         }
1861
1862         err = tg3_bmcr_reset(tp);
1863         if (err)
1864                 return err;
1865
1866         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1867                 u32 phy;
1868
1869                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1870                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1871
1872                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1873         }
1874
1875         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1876             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1877                 u32 val;
1878
1879                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1880                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1881                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1882                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1883                         udelay(40);
1884                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1885                 }
1886         }
1887
1888         tg3_phy_apply_otp(tp);
1889
1890         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1891                 tg3_phy_toggle_apd(tp, true);
1892         else
1893                 tg3_phy_toggle_apd(tp, false);
1894
1895 out:
1896         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1897                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1898                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1899                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1900                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1901                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1902                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1903         }
1904         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1905                 tg3_writephy(tp, 0x1c, 0x8d68);
1906                 tg3_writephy(tp, 0x1c, 0x8d68);
1907         }
1908         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1909                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1912                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1913                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1914                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1915                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1916                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1917         }
1918         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1919                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1920                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1921                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1922                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1923                         tg3_writephy(tp, MII_TG3_TEST1,
1924                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1925                 } else
1926                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1927                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1928         }
1929         /* Set Extended packet length bit (bit 14) on all chips that */
1930         /* support jumbo frames */
1931         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1932                 /* Cannot do read-modify-write on 5401 */
1933                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1934         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1935                 u32 phy_reg;
1936
1937                 /* Set bit 14 with read-modify-write to preserve other bits */
1938                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1939                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1940                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1941         }
1942
1943         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1944          * jumbo frames transmission.
1945          */
1946         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1947                 u32 phy_reg;
1948
1949                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1950                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1951                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1952         }
1953
1954         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1955                 /* adjust output voltage */
1956                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1957         }
1958
1959         tg3_phy_toggle_automdix(tp, 1);
1960         tg3_phy_set_wirespeed(tp);
1961         return 0;
1962 }
1963
1964 static void tg3_frob_aux_power(struct tg3 *tp)
1965 {
1966         struct tg3 *tp_peer = tp;
1967
1968         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1969                 return;
1970
1971         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1972             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1973                 struct net_device *dev_peer;
1974
1975                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1976                 /* remove_one() may have been run on the peer. */
1977                 if (!dev_peer)
1978                         tp_peer = tp;
1979                 else
1980                         tp_peer = netdev_priv(dev_peer);
1981         }
1982
1983         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1984             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1985             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1986             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1987                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1988                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1989                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1990                                     (GRC_LCLCTRL_GPIO_OE0 |
1991                                      GRC_LCLCTRL_GPIO_OE1 |
1992                                      GRC_LCLCTRL_GPIO_OE2 |
1993                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1994                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1995                                     100);
1996                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1997                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1998                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1999                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2000                                              GRC_LCLCTRL_GPIO_OE1 |
2001                                              GRC_LCLCTRL_GPIO_OE2 |
2002                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2003                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2004                                              tp->grc_local_ctrl;
2005                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006
2007                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2008                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2009
2010                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2011                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2012                 } else {
2013                         u32 no_gpio2;
2014                         u32 grc_local_ctrl = 0;
2015
2016                         if (tp_peer != tp &&
2017                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2018                                 return;
2019
2020                         /* Workaround to prevent overdrawing Amps. */
2021                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2022                             ASIC_REV_5714) {
2023                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2024                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2025                                             grc_local_ctrl, 100);
2026                         }
2027
2028                         /* On 5753 and variants, GPIO2 cannot be used. */
2029                         no_gpio2 = tp->nic_sram_data_cfg &
2030                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2031
2032                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2033                                          GRC_LCLCTRL_GPIO_OE1 |
2034                                          GRC_LCLCTRL_GPIO_OE2 |
2035                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2036                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2037                         if (no_gpio2) {
2038                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2039                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2040                         }
2041                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042                                                     grc_local_ctrl, 100);
2043
2044                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2045
2046                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2047                                                     grc_local_ctrl, 100);
2048
2049                         if (!no_gpio2) {
2050                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2051                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2052                                             grc_local_ctrl, 100);
2053                         }
2054                 }
2055         } else {
2056                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2057                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2058                         if (tp_peer != tp &&
2059                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2060                                 return;
2061
2062                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2063                                     (GRC_LCLCTRL_GPIO_OE1 |
2064                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2065
2066                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                     GRC_LCLCTRL_GPIO_OE1, 100);
2068
2069                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2070                                     (GRC_LCLCTRL_GPIO_OE1 |
2071                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2072                 }
2073         }
2074 }
2075
2076 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2077 {
2078         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2079                 return 1;
2080         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2081                 if (speed != SPEED_10)
2082                         return 1;
2083         } else if (speed == SPEED_10)
2084                 return 1;
2085
2086         return 0;
2087 }
2088
2089 static int tg3_setup_phy(struct tg3 *, int);
2090
2091 #define RESET_KIND_SHUTDOWN     0
2092 #define RESET_KIND_INIT         1
2093 #define RESET_KIND_SUSPEND      2
2094
2095 static void tg3_write_sig_post_reset(struct tg3 *, int);
2096 static int tg3_halt_cpu(struct tg3 *, u32);
2097
2098 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2099 {
2100         u32 val;
2101
2102         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2103                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2104                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2105                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2106
2107                         sg_dig_ctrl |=
2108                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2109                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2110                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2111                 }
2112                 return;
2113         }
2114
2115         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2116                 tg3_bmcr_reset(tp);
2117                 val = tr32(GRC_MISC_CFG);
2118                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2119                 udelay(40);
2120                 return;
2121         } else if (do_low_power) {
2122                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2123                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2124
2125                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2126                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2127                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2128                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2129                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2130         }
2131
2132         /* The PHY should not be powered down on some chips because
2133          * of bugs.
2134          */
2135         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2137             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2138              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2139                 return;
2140
2141         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2142             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2143                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2144                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2145                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2146                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2147         }
2148
2149         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2150 }
2151
2152 /* tp->lock is held. */
2153 static int tg3_nvram_lock(struct tg3 *tp)
2154 {
2155         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2156                 int i;
2157
2158                 if (tp->nvram_lock_cnt == 0) {
2159                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2160                         for (i = 0; i < 8000; i++) {
2161                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2162                                         break;
2163                                 udelay(20);
2164                         }
2165                         if (i == 8000) {
2166                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2167                                 return -ENODEV;
2168                         }
2169                 }
2170                 tp->nvram_lock_cnt++;
2171         }
2172         return 0;
2173 }
2174
2175 /* tp->lock is held. */
2176 static void tg3_nvram_unlock(struct tg3 *tp)
2177 {
2178         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2179                 if (tp->nvram_lock_cnt > 0)
2180                         tp->nvram_lock_cnt--;
2181                 if (tp->nvram_lock_cnt == 0)
2182                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2183         }
2184 }
2185
2186 /* tp->lock is held. */
2187 static void tg3_enable_nvram_access(struct tg3 *tp)
2188 {
2189         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2190             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2191                 u32 nvaccess = tr32(NVRAM_ACCESS);
2192
2193                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2194         }
2195 }
2196
2197 /* tp->lock is held. */
2198 static void tg3_disable_nvram_access(struct tg3 *tp)
2199 {
2200         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2201             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2202                 u32 nvaccess = tr32(NVRAM_ACCESS);
2203
2204                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2205         }
2206 }
2207
2208 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2209                                         u32 offset, u32 *val)
2210 {
2211         u32 tmp;
2212         int i;
2213
2214         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2215                 return -EINVAL;
2216
2217         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2218                                         EEPROM_ADDR_DEVID_MASK |
2219                                         EEPROM_ADDR_READ);
2220         tw32(GRC_EEPROM_ADDR,
2221              tmp |
2222              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2223              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2224               EEPROM_ADDR_ADDR_MASK) |
2225              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2226
2227         for (i = 0; i < 1000; i++) {
2228                 tmp = tr32(GRC_EEPROM_ADDR);
2229
2230                 if (tmp & EEPROM_ADDR_COMPLETE)
2231                         break;
2232                 msleep(1);
2233         }
2234         if (!(tmp & EEPROM_ADDR_COMPLETE))
2235                 return -EBUSY;
2236
2237         tmp = tr32(GRC_EEPROM_DATA);
2238
2239         /*
2240          * The data will always be opposite the native endian
2241          * format.  Perform a blind byteswap to compensate.
2242          */
2243         *val = swab32(tmp);
2244
2245         return 0;
2246 }
2247
2248 #define NVRAM_CMD_TIMEOUT 10000
2249
2250 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2251 {
2252         int i;
2253
2254         tw32(NVRAM_CMD, nvram_cmd);
2255         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2256                 udelay(10);
2257                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2258                         udelay(10);
2259                         break;
2260                 }
2261         }
2262
2263         if (i == NVRAM_CMD_TIMEOUT)
2264                 return -EBUSY;
2265
2266         return 0;
2267 }
2268
2269 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2270 {
2271         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2272             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2273             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2274            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2275             (tp->nvram_jedecnum == JEDEC_ATMEL))
2276
2277                 addr = ((addr / tp->nvram_pagesize) <<
2278                         ATMEL_AT45DB0X1B_PAGE_POS) +
2279                        (addr % tp->nvram_pagesize);
2280
2281         return addr;
2282 }
2283
2284 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2285 {
2286         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2287             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2288             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2289            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2290             (tp->nvram_jedecnum == JEDEC_ATMEL))
2291
2292                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2293                         tp->nvram_pagesize) +
2294                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2295
2296         return addr;
2297 }
2298
2299 /* NOTE: Data read in from NVRAM is byteswapped according to
2300  * the byteswapping settings for all other register accesses.
2301  * tg3 devices are BE devices, so on a BE machine, the data
2302  * returned will be exactly as it is seen in NVRAM.  On a LE
2303  * machine, the 32-bit value will be byteswapped.
2304  */
2305 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2306 {
2307         int ret;
2308
2309         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2310                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2311
2312         offset = tg3_nvram_phys_addr(tp, offset);
2313
2314         if (offset > NVRAM_ADDR_MSK)
2315                 return -EINVAL;
2316
2317         ret = tg3_nvram_lock(tp);
2318         if (ret)
2319                 return ret;
2320
2321         tg3_enable_nvram_access(tp);
2322
2323         tw32(NVRAM_ADDR, offset);
2324         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2325                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2326
2327         if (ret == 0)
2328                 *val = tr32(NVRAM_RDDATA);
2329
2330         tg3_disable_nvram_access(tp);
2331
2332         tg3_nvram_unlock(tp);
2333
2334         return ret;
2335 }
2336
2337 /* Ensures NVRAM data is in bytestream format. */
2338 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2339 {
2340         u32 v;
2341         int res = tg3_nvram_read(tp, offset, &v);
2342         if (!res)
2343                 *val = cpu_to_be32(v);
2344         return res;
2345 }
2346
2347 /* tp->lock is held. */
2348 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2349 {
2350         u32 addr_high, addr_low;
2351         int i;
2352
2353         addr_high = ((tp->dev->dev_addr[0] << 8) |
2354                      tp->dev->dev_addr[1]);
2355         addr_low = ((tp->dev->dev_addr[2] << 24) |
2356                     (tp->dev->dev_addr[3] << 16) |
2357                     (tp->dev->dev_addr[4] <<  8) |
2358                     (tp->dev->dev_addr[5] <<  0));
2359         for (i = 0; i < 4; i++) {
2360                 if (i == 1 && skip_mac_1)
2361                         continue;
2362                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2363                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2364         }
2365
2366         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2367             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2368                 for (i = 0; i < 12; i++) {
2369                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2370                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2371                 }
2372         }
2373
2374         addr_high = (tp->dev->dev_addr[0] +
2375                      tp->dev->dev_addr[1] +
2376                      tp->dev->dev_addr[2] +
2377                      tp->dev->dev_addr[3] +
2378                      tp->dev->dev_addr[4] +
2379                      tp->dev->dev_addr[5]) &
2380                 TX_BACKOFF_SEED_MASK;
2381         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2382 }
2383
2384 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2385 {
2386         u32 misc_host_ctrl;
2387         bool device_should_wake, do_low_power;
2388
2389         /* Make sure register accesses (indirect or otherwise)
2390          * will function correctly.
2391          */
2392         pci_write_config_dword(tp->pdev,
2393                                TG3PCI_MISC_HOST_CTRL,
2394                                tp->misc_host_ctrl);
2395
2396         switch (state) {
2397         case PCI_D0:
2398                 pci_enable_wake(tp->pdev, state, false);
2399                 pci_set_power_state(tp->pdev, PCI_D0);
2400
2401                 /* Switch out of Vaux if it is a NIC */
2402                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2403                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2404
2405                 return 0;
2406
2407         case PCI_D1:
2408         case PCI_D2:
2409         case PCI_D3hot:
2410                 break;
2411
2412         default:
2413                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2414                         tp->dev->name, state);
2415                 return -EINVAL;
2416         }
2417
2418         /* Restore the CLKREQ setting. */
2419         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2420                 u16 lnkctl;
2421
2422                 pci_read_config_word(tp->pdev,
2423                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2424                                      &lnkctl);
2425                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2426                 pci_write_config_word(tp->pdev,
2427                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2428                                       lnkctl);
2429         }
2430
2431         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2432         tw32(TG3PCI_MISC_HOST_CTRL,
2433              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2434
2435         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2436                              device_may_wakeup(&tp->pdev->dev) &&
2437                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2438
2439         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2440                 do_low_power = false;
2441                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2442                     !tp->link_config.phy_is_low_power) {
2443                         struct phy_device *phydev;
2444                         u32 phyid, advertising;
2445
2446                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2447
2448                         tp->link_config.phy_is_low_power = 1;
2449
2450                         tp->link_config.orig_speed = phydev->speed;
2451                         tp->link_config.orig_duplex = phydev->duplex;
2452                         tp->link_config.orig_autoneg = phydev->autoneg;
2453                         tp->link_config.orig_advertising = phydev->advertising;
2454
2455                         advertising = ADVERTISED_TP |
2456                                       ADVERTISED_Pause |
2457                                       ADVERTISED_Autoneg |
2458                                       ADVERTISED_10baseT_Half;
2459
2460                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2461                             device_should_wake) {
2462                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2463                                         advertising |=
2464                                                 ADVERTISED_100baseT_Half |
2465                                                 ADVERTISED_100baseT_Full |
2466                                                 ADVERTISED_10baseT_Full;
2467                                 else
2468                                         advertising |= ADVERTISED_10baseT_Full;
2469                         }
2470
2471                         phydev->advertising = advertising;
2472
2473                         phy_start_aneg(phydev);
2474
2475                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2476                         if (phyid != TG3_PHY_ID_BCMAC131) {
2477                                 phyid &= TG3_PHY_OUI_MASK;
2478                                 if (phyid == TG3_PHY_OUI_1 ||
2479                                     phyid == TG3_PHY_OUI_2 ||
2480                                     phyid == TG3_PHY_OUI_3)
2481                                         do_low_power = true;
2482                         }
2483                 }
2484         } else {
2485                 do_low_power = true;
2486
2487                 if (tp->link_config.phy_is_low_power == 0) {
2488                         tp->link_config.phy_is_low_power = 1;
2489                         tp->link_config.orig_speed = tp->link_config.speed;
2490                         tp->link_config.orig_duplex = tp->link_config.duplex;
2491                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2492                 }
2493
2494                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2495                         tp->link_config.speed = SPEED_10;
2496                         tp->link_config.duplex = DUPLEX_HALF;
2497                         tp->link_config.autoneg = AUTONEG_ENABLE;
2498                         tg3_setup_phy(tp, 0);
2499                 }
2500         }
2501
2502         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2503                 u32 val;
2504
2505                 val = tr32(GRC_VCPU_EXT_CTRL);
2506                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2507         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2508                 int i;
2509                 u32 val;
2510
2511                 for (i = 0; i < 200; i++) {
2512                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2513                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2514                                 break;
2515                         msleep(1);
2516                 }
2517         }
2518         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2519                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2520                                                      WOL_DRV_STATE_SHUTDOWN |
2521                                                      WOL_DRV_WOL |
2522                                                      WOL_SET_MAGIC_PKT);
2523
2524         if (device_should_wake) {
2525                 u32 mac_mode;
2526
2527                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2528                         if (do_low_power) {
2529                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2530                                 udelay(40);
2531                         }
2532
2533                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2534                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2535                         else
2536                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2537
2538                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2539                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2540                             ASIC_REV_5700) {
2541                                 u32 speed = (tp->tg3_flags &
2542                                              TG3_FLAG_WOL_SPEED_100MB) ?
2543                                              SPEED_100 : SPEED_10;
2544                                 if (tg3_5700_link_polarity(tp, speed))
2545                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2546                                 else
2547                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2548                         }
2549                 } else {
2550                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2551                 }
2552
2553                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2554                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2555
2556                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2557                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2558                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2559                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2560                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2561                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2562
2563                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2564                         mac_mode |= tp->mac_mode &
2565                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2566                         if (mac_mode & MAC_MODE_APE_TX_EN)
2567                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2568                 }
2569
2570                 tw32_f(MAC_MODE, mac_mode);
2571                 udelay(100);
2572
2573                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2574                 udelay(10);
2575         }
2576
2577         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2578             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2579              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2580                 u32 base_val;
2581
2582                 base_val = tp->pci_clock_ctrl;
2583                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2584                              CLOCK_CTRL_TXCLK_DISABLE);
2585
2586                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2587                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2588         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2589                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2590                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2591                 /* do nothing */
2592         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2593                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2594                 u32 newbits1, newbits2;
2595
2596                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2597                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2598                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2599                                     CLOCK_CTRL_TXCLK_DISABLE |
2600                                     CLOCK_CTRL_ALTCLK);
2601                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2602                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2603                         newbits1 = CLOCK_CTRL_625_CORE;
2604                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2605                 } else {
2606                         newbits1 = CLOCK_CTRL_ALTCLK;
2607                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2608                 }
2609
2610                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2611                             40);
2612
2613                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2614                             40);
2615
2616                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2617                         u32 newbits3;
2618
2619                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2620                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2621                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2622                                             CLOCK_CTRL_TXCLK_DISABLE |
2623                                             CLOCK_CTRL_44MHZ_CORE);
2624                         } else {
2625                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2626                         }
2627
2628                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2629                                     tp->pci_clock_ctrl | newbits3, 40);
2630                 }
2631         }
2632
2633         if (!(device_should_wake) &&
2634             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2635                 tg3_power_down_phy(tp, do_low_power);
2636
2637         tg3_frob_aux_power(tp);
2638
2639         /* Workaround for unstable PLL clock */
2640         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2641             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2642                 u32 val = tr32(0x7d00);
2643
2644                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2645                 tw32(0x7d00, val);
2646                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2647                         int err;
2648
2649                         err = tg3_nvram_lock(tp);
2650                         tg3_halt_cpu(tp, RX_CPU_BASE);
2651                         if (!err)
2652                                 tg3_nvram_unlock(tp);
2653                 }
2654         }
2655
2656         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2657
2658         if (device_should_wake)
2659                 pci_enable_wake(tp->pdev, state, true);
2660
2661         /* Finally, set the new power state. */
2662         pci_set_power_state(tp->pdev, state);
2663
2664         return 0;
2665 }
2666
2667 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2668 {
2669         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2670         case MII_TG3_AUX_STAT_10HALF:
2671                 *speed = SPEED_10;
2672                 *duplex = DUPLEX_HALF;
2673                 break;
2674
2675         case MII_TG3_AUX_STAT_10FULL:
2676                 *speed = SPEED_10;
2677                 *duplex = DUPLEX_FULL;
2678                 break;
2679
2680         case MII_TG3_AUX_STAT_100HALF:
2681                 *speed = SPEED_100;
2682                 *duplex = DUPLEX_HALF;
2683                 break;
2684
2685         case MII_TG3_AUX_STAT_100FULL:
2686                 *speed = SPEED_100;
2687                 *duplex = DUPLEX_FULL;
2688                 break;
2689
2690         case MII_TG3_AUX_STAT_1000HALF:
2691                 *speed = SPEED_1000;
2692                 *duplex = DUPLEX_HALF;
2693                 break;
2694
2695         case MII_TG3_AUX_STAT_1000FULL:
2696                 *speed = SPEED_1000;
2697                 *duplex = DUPLEX_FULL;
2698                 break;
2699
2700         default:
2701                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2702                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2703                                  SPEED_10;
2704                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2705                                   DUPLEX_HALF;
2706                         break;
2707                 }
2708                 *speed = SPEED_INVALID;
2709                 *duplex = DUPLEX_INVALID;
2710                 break;
2711         }
2712 }
2713
2714 static void tg3_phy_copper_begin(struct tg3 *tp)
2715 {
2716         u32 new_adv;
2717         int i;
2718
2719         if (tp->link_config.phy_is_low_power) {
2720                 /* Entering low power mode.  Disable gigabit and
2721                  * 100baseT advertisements.
2722                  */
2723                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2724
2725                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2726                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2727                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2728                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2729
2730                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2731         } else if (tp->link_config.speed == SPEED_INVALID) {
2732                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2733                         tp->link_config.advertising &=
2734                                 ~(ADVERTISED_1000baseT_Half |
2735                                   ADVERTISED_1000baseT_Full);
2736
2737                 new_adv = ADVERTISE_CSMA;
2738                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2739                         new_adv |= ADVERTISE_10HALF;
2740                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2741                         new_adv |= ADVERTISE_10FULL;
2742                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2743                         new_adv |= ADVERTISE_100HALF;
2744                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2745                         new_adv |= ADVERTISE_100FULL;
2746
2747                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2748
2749                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2750
2751                 if (tp->link_config.advertising &
2752                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2753                         new_adv = 0;
2754                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2755                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2756                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2757                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2758                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2759                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2760                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2761                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2762                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2763                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2764                 } else {
2765                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2766                 }
2767         } else {
2768                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2769                 new_adv |= ADVERTISE_CSMA;
2770
2771                 /* Asking for a specific link mode. */
2772                 if (tp->link_config.speed == SPEED_1000) {
2773                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2774
2775                         if (tp->link_config.duplex == DUPLEX_FULL)
2776                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2777                         else
2778                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2779                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2780                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2781                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2782                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2783                 } else {
2784                         if (tp->link_config.speed == SPEED_100) {
2785                                 if (tp->link_config.duplex == DUPLEX_FULL)
2786                                         new_adv |= ADVERTISE_100FULL;
2787                                 else
2788                                         new_adv |= ADVERTISE_100HALF;
2789                         } else {
2790                                 if (tp->link_config.duplex == DUPLEX_FULL)
2791                                         new_adv |= ADVERTISE_10FULL;
2792                                 else
2793                                         new_adv |= ADVERTISE_10HALF;
2794                         }
2795                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2796
2797                         new_adv = 0;
2798                 }
2799
2800                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2801         }
2802
2803         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2804             tp->link_config.speed != SPEED_INVALID) {
2805                 u32 bmcr, orig_bmcr;
2806
2807                 tp->link_config.active_speed = tp->link_config.speed;
2808                 tp->link_config.active_duplex = tp->link_config.duplex;
2809
2810                 bmcr = 0;
2811                 switch (tp->link_config.speed) {
2812                 default:
2813                 case SPEED_10:
2814                         break;
2815
2816                 case SPEED_100:
2817                         bmcr |= BMCR_SPEED100;
2818                         break;
2819
2820                 case SPEED_1000:
2821                         bmcr |= TG3_BMCR_SPEED1000;
2822                         break;
2823                 }
2824
2825                 if (tp->link_config.duplex == DUPLEX_FULL)
2826                         bmcr |= BMCR_FULLDPLX;
2827
2828                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2829                     (bmcr != orig_bmcr)) {
2830                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2831                         for (i = 0; i < 1500; i++) {
2832                                 u32 tmp;
2833
2834                                 udelay(10);
2835                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2836                                     tg3_readphy(tp, MII_BMSR, &tmp))
2837                                         continue;
2838                                 if (!(tmp & BMSR_LSTATUS)) {
2839                                         udelay(40);
2840                                         break;
2841                                 }
2842                         }
2843                         tg3_writephy(tp, MII_BMCR, bmcr);
2844                         udelay(40);
2845                 }
2846         } else {
2847                 tg3_writephy(tp, MII_BMCR,
2848                              BMCR_ANENABLE | BMCR_ANRESTART);
2849         }
2850 }
2851
2852 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2853 {
2854         int err;
2855
2856         /* Turn off tap power management. */
2857         /* Set Extended packet length bit */
2858         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2859
2860         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2861         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2862
2863         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2864         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2865
2866         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2867         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2868
2869         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2870         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2871
2872         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2873         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2874
2875         udelay(40);
2876
2877         return err;
2878 }
2879
2880 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2881 {
2882         u32 adv_reg, all_mask = 0;
2883
2884         if (mask & ADVERTISED_10baseT_Half)
2885                 all_mask |= ADVERTISE_10HALF;
2886         if (mask & ADVERTISED_10baseT_Full)
2887                 all_mask |= ADVERTISE_10FULL;
2888         if (mask & ADVERTISED_100baseT_Half)
2889                 all_mask |= ADVERTISE_100HALF;
2890         if (mask & ADVERTISED_100baseT_Full)
2891                 all_mask |= ADVERTISE_100FULL;
2892
2893         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2894                 return 0;
2895
2896         if ((adv_reg & all_mask) != all_mask)
2897                 return 0;
2898         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2899                 u32 tg3_ctrl;
2900
2901                 all_mask = 0;
2902                 if (mask & ADVERTISED_1000baseT_Half)
2903                         all_mask |= ADVERTISE_1000HALF;
2904                 if (mask & ADVERTISED_1000baseT_Full)
2905                         all_mask |= ADVERTISE_1000FULL;
2906
2907                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2908                         return 0;
2909
2910                 if ((tg3_ctrl & all_mask) != all_mask)
2911                         return 0;
2912         }
2913         return 1;
2914 }
2915
2916 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2917 {
2918         u32 curadv, reqadv;
2919
2920         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2921                 return 1;
2922
2923         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2924         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2925
2926         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2927                 if (curadv != reqadv)
2928                         return 0;
2929
2930                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2931                         tg3_readphy(tp, MII_LPA, rmtadv);
2932         } else {
2933                 /* Reprogram the advertisement register, even if it
2934                  * does not affect the current link.  If the link
2935                  * gets renegotiated in the future, we can save an
2936                  * additional renegotiation cycle by advertising
2937                  * it correctly in the first place.
2938                  */
2939                 if (curadv != reqadv) {
2940                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2941                                      ADVERTISE_PAUSE_ASYM);
2942                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2943                 }
2944         }
2945
2946         return 1;
2947 }
2948
2949 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2950 {
2951         int current_link_up;
2952         u32 bmsr, dummy;
2953         u32 lcl_adv, rmt_adv;
2954         u16 current_speed;
2955         u8 current_duplex;
2956         int i, err;
2957
2958         tw32(MAC_EVENT, 0);
2959
2960         tw32_f(MAC_STATUS,
2961              (MAC_STATUS_SYNC_CHANGED |
2962               MAC_STATUS_CFG_CHANGED |
2963               MAC_STATUS_MI_COMPLETION |
2964               MAC_STATUS_LNKSTATE_CHANGED));
2965         udelay(40);
2966
2967         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2968                 tw32_f(MAC_MI_MODE,
2969                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2970                 udelay(80);
2971         }
2972
2973         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2974
2975         /* Some third-party PHYs need to be reset on link going
2976          * down.
2977          */
2978         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2979              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2980              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2981             netif_carrier_ok(tp->dev)) {
2982                 tg3_readphy(tp, MII_BMSR, &bmsr);
2983                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2984                     !(bmsr & BMSR_LSTATUS))
2985                         force_reset = 1;
2986         }
2987         if (force_reset)
2988                 tg3_phy_reset(tp);
2989
2990         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2991                 tg3_readphy(tp, MII_BMSR, &bmsr);
2992                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2993                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2994                         bmsr = 0;
2995
2996                 if (!(bmsr & BMSR_LSTATUS)) {
2997                         err = tg3_init_5401phy_dsp(tp);
2998                         if (err)
2999                                 return err;
3000
3001                         tg3_readphy(tp, MII_BMSR, &bmsr);
3002                         for (i = 0; i < 1000; i++) {
3003                                 udelay(10);
3004                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3005                                     (bmsr & BMSR_LSTATUS)) {
3006                                         udelay(40);
3007                                         break;
3008                                 }
3009                         }
3010
3011                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3012                             !(bmsr & BMSR_LSTATUS) &&
3013                             tp->link_config.active_speed == SPEED_1000) {
3014                                 err = tg3_phy_reset(tp);
3015                                 if (!err)
3016                                         err = tg3_init_5401phy_dsp(tp);
3017                                 if (err)
3018                                         return err;
3019                         }
3020                 }
3021         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3022                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3023                 /* 5701 {A0,B0} CRC bug workaround */
3024                 tg3_writephy(tp, 0x15, 0x0a75);
3025                 tg3_writephy(tp, 0x1c, 0x8c68);
3026                 tg3_writephy(tp, 0x1c, 0x8d68);
3027                 tg3_writephy(tp, 0x1c, 0x8c68);
3028         }
3029
3030         /* Clear pending interrupts... */
3031         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3032         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3033
3034         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3035                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3036         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3037                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3038
3039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3041                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3042                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3043                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3044                 else
3045                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3046         }
3047
3048         current_link_up = 0;
3049         current_speed = SPEED_INVALID;
3050         current_duplex = DUPLEX_INVALID;
3051
3052         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3053                 u32 val;
3054
3055                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3056                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3057                 if (!(val & (1 << 10))) {
3058                         val |= (1 << 10);
3059                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3060                         goto relink;
3061                 }
3062         }
3063
3064         bmsr = 0;
3065         for (i = 0; i < 100; i++) {
3066                 tg3_readphy(tp, MII_BMSR, &bmsr);
3067                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068                     (bmsr & BMSR_LSTATUS))
3069                         break;
3070                 udelay(40);
3071         }
3072
3073         if (bmsr & BMSR_LSTATUS) {
3074                 u32 aux_stat, bmcr;
3075
3076                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3077                 for (i = 0; i < 2000; i++) {
3078                         udelay(10);
3079                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3080                             aux_stat)
3081                                 break;
3082                 }
3083
3084                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3085                                              &current_speed,
3086                                              &current_duplex);
3087
3088                 bmcr = 0;
3089                 for (i = 0; i < 200; i++) {
3090                         tg3_readphy(tp, MII_BMCR, &bmcr);
3091                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3092                                 continue;
3093                         if (bmcr && bmcr != 0x7fff)
3094                                 break;
3095                         udelay(10);
3096                 }
3097
3098                 lcl_adv = 0;
3099                 rmt_adv = 0;
3100
3101                 tp->link_config.active_speed = current_speed;
3102                 tp->link_config.active_duplex = current_duplex;
3103
3104                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3105                         if ((bmcr & BMCR_ANENABLE) &&
3106                             tg3_copper_is_advertising_all(tp,
3107                                                 tp->link_config.advertising)) {
3108                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3109                                                                   &rmt_adv))
3110                                         current_link_up = 1;
3111                         }
3112                 } else {
3113                         if (!(bmcr & BMCR_ANENABLE) &&
3114                             tp->link_config.speed == current_speed &&
3115                             tp->link_config.duplex == current_duplex &&
3116                             tp->link_config.flowctrl ==
3117                             tp->link_config.active_flowctrl) {
3118                                 current_link_up = 1;
3119                         }
3120                 }
3121
3122                 if (current_link_up == 1 &&
3123                     tp->link_config.active_duplex == DUPLEX_FULL)
3124                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3125         }
3126
3127 relink:
3128         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3129                 u32 tmp;
3130
3131                 tg3_phy_copper_begin(tp);
3132
3133                 tg3_readphy(tp, MII_BMSR, &tmp);
3134                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3135                     (tmp & BMSR_LSTATUS))
3136                         current_link_up = 1;
3137         }
3138
3139         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3140         if (current_link_up == 1) {
3141                 if (tp->link_config.active_speed == SPEED_100 ||
3142                     tp->link_config.active_speed == SPEED_10)
3143                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3144                 else
3145                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3146         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3147                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3148         else
3149                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3150
3151         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3152         if (tp->link_config.active_duplex == DUPLEX_HALF)
3153                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3154
3155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3156                 if (current_link_up == 1 &&
3157                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3158                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3159                 else
3160                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3161         }
3162
3163         /* ??? Without this setting Netgear GA302T PHY does not
3164          * ??? send/receive packets...
3165          */
3166         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3167             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3168                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3169                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3170                 udelay(80);
3171         }
3172
3173         tw32_f(MAC_MODE, tp->mac_mode);
3174         udelay(40);
3175
3176         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3177                 /* Polled via timer. */
3178                 tw32_f(MAC_EVENT, 0);
3179         } else {
3180                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3181         }
3182         udelay(40);
3183
3184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3185             current_link_up == 1 &&
3186             tp->link_config.active_speed == SPEED_1000 &&
3187             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3188              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3189                 udelay(120);
3190                 tw32_f(MAC_STATUS,
3191                      (MAC_STATUS_SYNC_CHANGED |
3192                       MAC_STATUS_CFG_CHANGED));
3193                 udelay(40);
3194                 tg3_write_mem(tp,
3195                               NIC_SRAM_FIRMWARE_MBOX,
3196                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3197         }
3198
3199         /* Prevent send BD corruption. */
3200         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3201                 u16 oldlnkctl, newlnkctl;
3202
3203                 pci_read_config_word(tp->pdev,
3204                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3205                                      &oldlnkctl);
3206                 if (tp->link_config.active_speed == SPEED_100 ||
3207                     tp->link_config.active_speed == SPEED_10)
3208                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3209                 else
3210                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3211                 if (newlnkctl != oldlnkctl)
3212                         pci_write_config_word(tp->pdev,
3213                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3214                                               newlnkctl);
3215         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3216                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3217                 if (tp->link_config.active_speed == SPEED_100 ||
3218                     tp->link_config.active_speed == SPEED_10)
3219                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3220                 else
3221                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3222                 if (newreg != oldreg)
3223                         tw32(TG3_PCIE_LNKCTL, newreg);
3224         }
3225
3226         if (current_link_up != netif_carrier_ok(tp->dev)) {
3227                 if (current_link_up)
3228                         netif_carrier_on(tp->dev);
3229                 else
3230                         netif_carrier_off(tp->dev);
3231                 tg3_link_report(tp);
3232         }
3233
3234         return 0;
3235 }
3236
3237 struct tg3_fiber_aneginfo {
3238         int state;
3239 #define ANEG_STATE_UNKNOWN              0
3240 #define ANEG_STATE_AN_ENABLE            1
3241 #define ANEG_STATE_RESTART_INIT         2
3242 #define ANEG_STATE_RESTART              3
3243 #define ANEG_STATE_DISABLE_LINK_OK      4
3244 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3245 #define ANEG_STATE_ABILITY_DETECT       6
3246 #define ANEG_STATE_ACK_DETECT_INIT      7
3247 #define ANEG_STATE_ACK_DETECT           8
3248 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3249 #define ANEG_STATE_COMPLETE_ACK         10
3250 #define ANEG_STATE_IDLE_DETECT_INIT     11
3251 #define ANEG_STATE_IDLE_DETECT          12
3252 #define ANEG_STATE_LINK_OK              13
3253 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3254 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3255
3256         u32 flags;
3257 #define MR_AN_ENABLE            0x00000001
3258 #define MR_RESTART_AN           0x00000002
3259 #define MR_AN_COMPLETE          0x00000004
3260 #define MR_PAGE_RX              0x00000008
3261 #define MR_NP_LOADED            0x00000010
3262 #define MR_TOGGLE_TX            0x00000020
3263 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3264 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3265 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3266 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3267 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3268 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3269 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3270 #define MR_TOGGLE_RX            0x00002000
3271 #define MR_NP_RX                0x00004000
3272
3273 #define MR_LINK_OK              0x80000000
3274
3275         unsigned long link_time, cur_time;
3276
3277         u32 ability_match_cfg;
3278         int ability_match_count;
3279
3280         char ability_match, idle_match, ack_match;
3281
3282         u32 txconfig, rxconfig;
3283 #define ANEG_CFG_NP             0x00000080
3284 #define ANEG_CFG_ACK            0x00000040
3285 #define ANEG_CFG_RF2            0x00000020
3286 #define ANEG_CFG_RF1            0x00000010
3287 #define ANEG_CFG_PS2            0x00000001
3288 #define ANEG_CFG_PS1            0x00008000
3289 #define ANEG_CFG_HD             0x00004000
3290 #define ANEG_CFG_FD             0x00002000
3291 #define ANEG_CFG_INVAL          0x00001f06
3292
3293 };
3294 #define ANEG_OK         0
3295 #define ANEG_DONE       1
3296 #define ANEG_TIMER_ENAB 2
3297 #define ANEG_FAILED     -1
3298
3299 #define ANEG_STATE_SETTLE_TIME  10000
3300
3301 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3302                                    struct tg3_fiber_aneginfo *ap)
3303 {
3304         u16 flowctrl;
3305         unsigned long delta;
3306         u32 rx_cfg_reg;
3307         int ret;
3308
3309         if (ap->state == ANEG_STATE_UNKNOWN) {
3310                 ap->rxconfig = 0;
3311                 ap->link_time = 0;
3312                 ap->cur_time = 0;
3313                 ap->ability_match_cfg = 0;
3314                 ap->ability_match_count = 0;
3315                 ap->ability_match = 0;
3316                 ap->idle_match = 0;
3317                 ap->ack_match = 0;
3318         }
3319         ap->cur_time++;
3320
3321         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3322                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3323
3324                 if (rx_cfg_reg != ap->ability_match_cfg) {
3325                         ap->ability_match_cfg = rx_cfg_reg;
3326                         ap->ability_match = 0;
3327                         ap->ability_match_count = 0;
3328                 } else {
3329                         if (++ap->ability_match_count > 1) {
3330                                 ap->ability_match = 1;
3331                                 ap->ability_match_cfg = rx_cfg_reg;
3332                         }
3333                 }
3334                 if (rx_cfg_reg & ANEG_CFG_ACK)
3335                         ap->ack_match = 1;
3336                 else
3337                         ap->ack_match = 0;
3338
3339                 ap->idle_match = 0;
3340         } else {
3341                 ap->idle_match = 1;
3342                 ap->ability_match_cfg = 0;
3343                 ap->ability_match_count = 0;
3344                 ap->ability_match = 0;
3345                 ap->ack_match = 0;
3346
3347                 rx_cfg_reg = 0;
3348         }
3349
3350         ap->rxconfig = rx_cfg_reg;
3351         ret = ANEG_OK;
3352
3353         switch(ap->state) {
3354         case ANEG_STATE_UNKNOWN:
3355                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3356                         ap->state = ANEG_STATE_AN_ENABLE;
3357
3358                 /* fallthru */
3359         case ANEG_STATE_AN_ENABLE:
3360                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3361                 if (ap->flags & MR_AN_ENABLE) {
3362                         ap->link_time = 0;
3363                         ap->cur_time = 0;
3364                         ap->ability_match_cfg = 0;
3365                         ap->ability_match_count = 0;
3366                         ap->ability_match = 0;
3367                         ap->idle_match = 0;
3368                         ap->ack_match = 0;
3369
3370                         ap->state = ANEG_STATE_RESTART_INIT;
3371                 } else {
3372                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3373                 }
3374                 break;
3375
3376         case ANEG_STATE_RESTART_INIT:
3377                 ap->link_time = ap->cur_time;
3378                 ap->flags &= ~(MR_NP_LOADED);
3379                 ap->txconfig = 0;
3380                 tw32(MAC_TX_AUTO_NEG, 0);
3381                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3382                 tw32_f(MAC_MODE, tp->mac_mode);
3383                 udelay(40);
3384
3385                 ret = ANEG_TIMER_ENAB;
3386                 ap->state = ANEG_STATE_RESTART;
3387
3388                 /* fallthru */
3389         case ANEG_STATE_RESTART:
3390                 delta = ap->cur_time - ap->link_time;
3391                 if (delta > ANEG_STATE_SETTLE_TIME) {
3392                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3393                 } else {
3394                         ret = ANEG_TIMER_ENAB;
3395                 }
3396                 break;
3397
3398         case ANEG_STATE_DISABLE_LINK_OK:
3399                 ret = ANEG_DONE;
3400                 break;
3401
3402         case ANEG_STATE_ABILITY_DETECT_INIT:
3403                 ap->flags &= ~(MR_TOGGLE_TX);
3404                 ap->txconfig = ANEG_CFG_FD;
3405                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3406                 if (flowctrl & ADVERTISE_1000XPAUSE)
3407                         ap->txconfig |= ANEG_CFG_PS1;
3408                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3409                         ap->txconfig |= ANEG_CFG_PS2;
3410                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3411                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3412                 tw32_f(MAC_MODE, tp->mac_mode);
3413                 udelay(40);
3414
3415                 ap->state = ANEG_STATE_ABILITY_DETECT;
3416                 break;
3417
3418         case ANEG_STATE_ABILITY_DETECT:
3419                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3420                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3421                 }
3422                 break;
3423
3424         case ANEG_STATE_ACK_DETECT_INIT:
3425                 ap->txconfig |= ANEG_CFG_ACK;
3426                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3427                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3428                 tw32_f(MAC_MODE, tp->mac_mode);
3429                 udelay(40);
3430
3431                 ap->state = ANEG_STATE_ACK_DETECT;
3432
3433                 /* fallthru */
3434         case ANEG_STATE_ACK_DETECT:
3435                 if (ap->ack_match != 0) {
3436                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3437                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3438                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3439                         } else {
3440                                 ap->state = ANEG_STATE_AN_ENABLE;
3441                         }
3442                 } else if (ap->ability_match != 0 &&
3443                            ap->rxconfig == 0) {
3444                         ap->state = ANEG_STATE_AN_ENABLE;
3445                 }
3446                 break;
3447
3448         case ANEG_STATE_COMPLETE_ACK_INIT:
3449                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3450                         ret = ANEG_FAILED;
3451                         break;
3452                 }
3453                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3454                                MR_LP_ADV_HALF_DUPLEX |
3455                                MR_LP_ADV_SYM_PAUSE |
3456                                MR_LP_ADV_ASYM_PAUSE |
3457                                MR_LP_ADV_REMOTE_FAULT1 |
3458                                MR_LP_ADV_REMOTE_FAULT2 |
3459                                MR_LP_ADV_NEXT_PAGE |
3460                                MR_TOGGLE_RX |
3461                                MR_NP_RX);
3462                 if (ap->rxconfig & ANEG_CFG_FD)
3463                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3464                 if (ap->rxconfig & ANEG_CFG_HD)
3465                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3466                 if (ap->rxconfig & ANEG_CFG_PS1)
3467                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3468                 if (ap->rxconfig & ANEG_CFG_PS2)
3469                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3470                 if (ap->rxconfig & ANEG_CFG_RF1)
3471                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3472                 if (ap->rxconfig & ANEG_CFG_RF2)
3473                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3474                 if (ap->rxconfig & ANEG_CFG_NP)
3475                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3476
3477                 ap->link_time = ap->cur_time;
3478
3479                 ap->flags ^= (MR_TOGGLE_TX);
3480                 if (ap->rxconfig & 0x0008)
3481                         ap->flags |= MR_TOGGLE_RX;
3482                 if (ap->rxconfig & ANEG_CFG_NP)
3483                         ap->flags |= MR_NP_RX;
3484                 ap->flags |= MR_PAGE_RX;
3485
3486                 ap->state = ANEG_STATE_COMPLETE_ACK;
3487                 ret = ANEG_TIMER_ENAB;
3488                 break;
3489
3490         case ANEG_STATE_COMPLETE_ACK:
3491                 if (ap->ability_match != 0 &&
3492                     ap->rxconfig == 0) {
3493                         ap->state = ANEG_STATE_AN_ENABLE;
3494                         break;
3495                 }
3496                 delta = ap->cur_time - ap->link_time;
3497                 if (delta > ANEG_STATE_SETTLE_TIME) {
3498                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3499                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3500                         } else {
3501                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3502                                     !(ap->flags & MR_NP_RX)) {
3503                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3504                                 } else {
3505                                         ret = ANEG_FAILED;
3506                                 }
3507                         }
3508                 }
3509                 break;
3510
3511         case ANEG_STATE_IDLE_DETECT_INIT:
3512                 ap->link_time = ap->cur_time;
3513                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_IDLE_DETECT;
3518                 ret = ANEG_TIMER_ENAB;
3519                 break;
3520
3521         case ANEG_STATE_IDLE_DETECT:
3522                 if (ap->ability_match != 0 &&
3523                     ap->rxconfig == 0) {
3524                         ap->state = ANEG_STATE_AN_ENABLE;
3525                         break;
3526                 }
3527                 delta = ap->cur_time - ap->link_time;
3528                 if (delta > ANEG_STATE_SETTLE_TIME) {
3529                         /* XXX another gem from the Broadcom driver :( */
3530                         ap->state = ANEG_STATE_LINK_OK;
3531                 }
3532                 break;
3533
3534         case ANEG_STATE_LINK_OK:
3535                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3536                 ret = ANEG_DONE;
3537                 break;
3538
3539         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3540                 /* ??? unimplemented */
3541                 break;
3542
3543         case ANEG_STATE_NEXT_PAGE_WAIT:
3544                 /* ??? unimplemented */
3545                 break;
3546
3547         default:
3548                 ret = ANEG_FAILED;
3549                 break;
3550         }
3551
3552         return ret;
3553 }
3554
3555 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3556 {
3557         int res = 0;
3558         struct tg3_fiber_aneginfo aninfo;
3559         int status = ANEG_FAILED;
3560         unsigned int tick;
3561         u32 tmp;
3562
3563         tw32_f(MAC_TX_AUTO_NEG, 0);
3564
3565         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3566         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3567         udelay(40);
3568
3569         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3570         udelay(40);
3571
3572         memset(&aninfo, 0, sizeof(aninfo));
3573         aninfo.flags |= MR_AN_ENABLE;
3574         aninfo.state = ANEG_STATE_UNKNOWN;
3575         aninfo.cur_time = 0;
3576         tick = 0;
3577         while (++tick < 195000) {
3578                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3579                 if (status == ANEG_DONE || status == ANEG_FAILED)
3580                         break;
3581
3582                 udelay(1);
3583         }
3584
3585         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3586         tw32_f(MAC_MODE, tp->mac_mode);
3587         udelay(40);
3588
3589         *txflags = aninfo.txconfig;
3590         *rxflags = aninfo.flags;
3591
3592         if (status == ANEG_DONE &&
3593             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3594                              MR_LP_ADV_FULL_DUPLEX)))
3595                 res = 1;
3596
3597         return res;
3598 }
3599
3600 static void tg3_init_bcm8002(struct tg3 *tp)
3601 {
3602         u32 mac_status = tr32(MAC_STATUS);
3603         int i;
3604
3605         /* Reset when initting first time or we have a link. */
3606         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3607             !(mac_status & MAC_STATUS_PCS_SYNCED))
3608                 return;
3609
3610         /* Set PLL lock range. */
3611         tg3_writephy(tp, 0x16, 0x8007);
3612
3613         /* SW reset */
3614         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3615
3616         /* Wait for reset to complete. */
3617         /* XXX schedule_timeout() ... */
3618         for (i = 0; i < 500; i++)
3619                 udelay(10);
3620
3621         /* Config mode; select PMA/Ch 1 regs. */
3622         tg3_writephy(tp, 0x10, 0x8411);
3623
3624         /* Enable auto-lock and comdet, select txclk for tx. */
3625         tg3_writephy(tp, 0x11, 0x0a10);
3626
3627         tg3_writephy(tp, 0x18, 0x00a0);
3628         tg3_writephy(tp, 0x16, 0x41ff);
3629
3630         /* Assert and deassert POR. */
3631         tg3_writephy(tp, 0x13, 0x0400);
3632         udelay(40);
3633         tg3_writephy(tp, 0x13, 0x0000);
3634
3635         tg3_writephy(tp, 0x11, 0x0a50);
3636         udelay(40);
3637         tg3_writephy(tp, 0x11, 0x0a10);
3638
3639         /* Wait for signal to stabilize */
3640         /* XXX schedule_timeout() ... */
3641         for (i = 0; i < 15000; i++)
3642                 udelay(10);
3643
3644         /* Deselect the channel register so we can read the PHYID
3645          * later.
3646          */
3647         tg3_writephy(tp, 0x10, 0x8011);
3648 }
3649
3650 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3651 {
3652         u16 flowctrl;
3653         u32 sg_dig_ctrl, sg_dig_status;
3654         u32 serdes_cfg, expected_sg_dig_ctrl;
3655         int workaround, port_a;
3656         int current_link_up;
3657
3658         serdes_cfg = 0;
3659         expected_sg_dig_ctrl = 0;
3660         workaround = 0;
3661         port_a = 1;
3662         current_link_up = 0;
3663
3664         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3665             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3666                 workaround = 1;
3667                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3668                         port_a = 0;
3669
3670                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3671                 /* preserve bits 20-23 for voltage regulator */
3672                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3673         }
3674
3675         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3676
3677         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3678                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3679                         if (workaround) {
3680                                 u32 val = serdes_cfg;
3681
3682                                 if (port_a)
3683                                         val |= 0xc010000;
3684                                 else
3685                                         val |= 0x4010000;
3686                                 tw32_f(MAC_SERDES_CFG, val);
3687                         }
3688
3689                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3690                 }
3691                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3692                         tg3_setup_flow_control(tp, 0, 0);
3693                         current_link_up = 1;
3694                 }
3695                 goto out;
3696         }
3697
3698         /* Want auto-negotiation.  */
3699         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3700
3701         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3702         if (flowctrl & ADVERTISE_1000XPAUSE)
3703                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3704         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3705                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3706
3707         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3708                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3709                     tp->serdes_counter &&
3710                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3711                                     MAC_STATUS_RCVD_CFG)) ==
3712                      MAC_STATUS_PCS_SYNCED)) {
3713                         tp->serdes_counter--;
3714                         current_link_up = 1;
3715                         goto out;
3716                 }
3717 restart_autoneg:
3718                 if (workaround)
3719                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3720                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3721                 udelay(5);
3722                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3723
3724                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3725                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3726         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3727                                  MAC_STATUS_SIGNAL_DET)) {
3728                 sg_dig_status = tr32(SG_DIG_STATUS);
3729                 mac_status = tr32(MAC_STATUS);
3730
3731                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3732                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3733                         u32 local_adv = 0, remote_adv = 0;
3734
3735                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3736                                 local_adv |= ADVERTISE_1000XPAUSE;
3737                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3738                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3739
3740                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3741                                 remote_adv |= LPA_1000XPAUSE;
3742                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3743                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3744
3745                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3746                         current_link_up = 1;
3747                         tp->serdes_counter = 0;
3748                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3749                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3750                         if (tp->serdes_counter)
3751                                 tp->serdes_counter--;
3752                         else {
3753                                 if (workaround) {
3754                                         u32 val = serdes_cfg;
3755
3756                                         if (port_a)
3757                                                 val |= 0xc010000;
3758                                         else
3759                                                 val |= 0x4010000;
3760
3761                                         tw32_f(MAC_SERDES_CFG, val);
3762                                 }
3763
3764                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3765                                 udelay(40);
3766
3767                                 /* Link parallel detection - link is up */
3768                                 /* only if we have PCS_SYNC and not */
3769                                 /* receiving config code words */
3770                                 mac_status = tr32(MAC_STATUS);
3771                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3772                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3773                                         tg3_setup_flow_control(tp, 0, 0);
3774                                         current_link_up = 1;
3775                                         tp->tg3_flags2 |=
3776                                                 TG3_FLG2_PARALLEL_DETECT;
3777                                         tp->serdes_counter =
3778                                                 SERDES_PARALLEL_DET_TIMEOUT;
3779                                 } else
3780                                         goto restart_autoneg;
3781                         }
3782                 }
3783         } else {
3784                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3785                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3786         }
3787
3788 out:
3789         return current_link_up;
3790 }
3791
3792 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3793 {
3794         int current_link_up = 0;
3795
3796         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3797                 goto out;
3798
3799         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3800                 u32 txflags, rxflags;
3801                 int i;
3802
3803                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3804                         u32 local_adv = 0, remote_adv = 0;
3805
3806                         if (txflags & ANEG_CFG_PS1)
3807                                 local_adv |= ADVERTISE_1000XPAUSE;
3808                         if (txflags & ANEG_CFG_PS2)
3809                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3810
3811                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3812                                 remote_adv |= LPA_1000XPAUSE;
3813                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3814                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3815
3816                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3817
3818                         current_link_up = 1;
3819                 }
3820                 for (i = 0; i < 30; i++) {
3821                         udelay(20);
3822                         tw32_f(MAC_STATUS,
3823                                (MAC_STATUS_SYNC_CHANGED |
3824                                 MAC_STATUS_CFG_CHANGED));
3825                         udelay(40);
3826                         if ((tr32(MAC_STATUS) &
3827                              (MAC_STATUS_SYNC_CHANGED |
3828                               MAC_STATUS_CFG_CHANGED)) == 0)
3829                                 break;
3830                 }
3831
3832                 mac_status = tr32(MAC_STATUS);
3833                 if (current_link_up == 0 &&
3834                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3835                     !(mac_status & MAC_STATUS_RCVD_CFG))
3836                         current_link_up = 1;
3837         } else {
3838                 tg3_setup_flow_control(tp, 0, 0);
3839
3840                 /* Forcing 1000FD link up. */
3841                 current_link_up = 1;
3842
3843                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3844                 udelay(40);
3845
3846                 tw32_f(MAC_MODE, tp->mac_mode);
3847                 udelay(40);
3848         }
3849
3850 out:
3851         return current_link_up;
3852 }
3853
3854 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3855 {
3856         u32 orig_pause_cfg;
3857         u16 orig_active_speed;
3858         u8 orig_active_duplex;
3859         u32 mac_status;
3860         int current_link_up;
3861         int i;
3862
3863         orig_pause_cfg = tp->link_config.active_flowctrl;
3864         orig_active_speed = tp->link_config.active_speed;
3865         orig_active_duplex = tp->link_config.active_duplex;
3866
3867         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3868             netif_carrier_ok(tp->dev) &&
3869             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3870                 mac_status = tr32(MAC_STATUS);
3871                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3872                                MAC_STATUS_SIGNAL_DET |
3873                                MAC_STATUS_CFG_CHANGED |
3874                                MAC_STATUS_RCVD_CFG);
3875                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3876                                    MAC_STATUS_SIGNAL_DET)) {
3877                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3878                                             MAC_STATUS_CFG_CHANGED));
3879                         return 0;
3880                 }
3881         }
3882
3883         tw32_f(MAC_TX_AUTO_NEG, 0);
3884
3885         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3886         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3887         tw32_f(MAC_MODE, tp->mac_mode);
3888         udelay(40);
3889
3890         if (tp->phy_id == PHY_ID_BCM8002)
3891                 tg3_init_bcm8002(tp);
3892
3893         /* Enable link change event even when serdes polling.  */
3894         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3895         udelay(40);
3896
3897         current_link_up = 0;
3898         mac_status = tr32(MAC_STATUS);
3899
3900         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3901                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3902         else
3903                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3904
3905         tp->hw_status->status =
3906                 (SD_STATUS_UPDATED |
3907                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3908
3909         for (i = 0; i < 100; i++) {
3910                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3911                                     MAC_STATUS_CFG_CHANGED));
3912                 udelay(5);
3913                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3914                                          MAC_STATUS_CFG_CHANGED |
3915                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3916                         break;
3917         }
3918
3919         mac_status = tr32(MAC_STATUS);
3920         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3921                 current_link_up = 0;
3922                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3923                     tp->serdes_counter == 0) {
3924                         tw32_f(MAC_MODE, (tp->mac_mode |
3925                                           MAC_MODE_SEND_CONFIGS));
3926                         udelay(1);
3927                         tw32_f(MAC_MODE, tp->mac_mode);
3928                 }
3929         }
3930
3931         if (current_link_up == 1) {
3932                 tp->link_config.active_speed = SPEED_1000;
3933                 tp->link_config.active_duplex = DUPLEX_FULL;
3934                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3935                                     LED_CTRL_LNKLED_OVERRIDE |
3936                                     LED_CTRL_1000MBPS_ON));
3937         } else {
3938                 tp->link_config.active_speed = SPEED_INVALID;
3939                 tp->link_config.active_duplex = DUPLEX_INVALID;
3940                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3941                                     LED_CTRL_LNKLED_OVERRIDE |
3942                                     LED_CTRL_TRAFFIC_OVERRIDE));
3943         }
3944
3945         if (current_link_up != netif_carrier_ok(tp->dev)) {
3946                 if (current_link_up)
3947                         netif_carrier_on(tp->dev);
3948                 else
3949                         netif_carrier_off(tp->dev);
3950                 tg3_link_report(tp);
3951         } else {
3952                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3953                 if (orig_pause_cfg != now_pause_cfg ||
3954                     orig_active_speed != tp->link_config.active_speed ||
3955                     orig_active_duplex != tp->link_config.active_duplex)
3956                         tg3_link_report(tp);
3957         }
3958
3959         return 0;
3960 }
3961
3962 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3963 {
3964         int current_link_up, err = 0;
3965         u32 bmsr, bmcr;
3966         u16 current_speed;
3967         u8 current_duplex;
3968         u32 local_adv, remote_adv;
3969
3970         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3971         tw32_f(MAC_MODE, tp->mac_mode);
3972         udelay(40);
3973
3974         tw32(MAC_EVENT, 0);
3975
3976         tw32_f(MAC_STATUS,
3977              (MAC_STATUS_SYNC_CHANGED |
3978               MAC_STATUS_CFG_CHANGED |
3979               MAC_STATUS_MI_COMPLETION |
3980               MAC_STATUS_LNKSTATE_CHANGED));
3981         udelay(40);
3982
3983         if (force_reset)
3984                 tg3_phy_reset(tp);
3985
3986         current_link_up = 0;
3987         current_speed = SPEED_INVALID;
3988         current_duplex = DUPLEX_INVALID;
3989
3990         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3991         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3993                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3994                         bmsr |= BMSR_LSTATUS;
3995                 else
3996                         bmsr &= ~BMSR_LSTATUS;
3997         }
3998
3999         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4000
4001         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4002             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4003                 /* do nothing, just check for link up at the end */
4004         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4005                 u32 adv, new_adv;
4006
4007                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4008                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4009                                   ADVERTISE_1000XPAUSE |
4010                                   ADVERTISE_1000XPSE_ASYM |
4011                                   ADVERTISE_SLCT);
4012
4013                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4014
4015                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4016                         new_adv |= ADVERTISE_1000XHALF;
4017                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4018                         new_adv |= ADVERTISE_1000XFULL;
4019
4020                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4021                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4022                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4023                         tg3_writephy(tp, MII_BMCR, bmcr);
4024
4025                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4026                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4027                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4028
4029                         return err;
4030                 }
4031         } else {
4032                 u32 new_bmcr;
4033
4034                 bmcr &= ~BMCR_SPEED1000;
4035                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4036
4037                 if (tp->link_config.duplex == DUPLEX_FULL)
4038                         new_bmcr |= BMCR_FULLDPLX;
4039
4040                 if (new_bmcr != bmcr) {
4041                         /* BMCR_SPEED1000 is a reserved bit that needs
4042                          * to be set on write.
4043                          */
4044                         new_bmcr |= BMCR_SPEED1000;
4045
4046                         /* Force a linkdown */
4047                         if (netif_carrier_ok(tp->dev)) {
4048                                 u32 adv;
4049
4050                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4051                                 adv &= ~(ADVERTISE_1000XFULL |
4052                                          ADVERTISE_1000XHALF |
4053                                          ADVERTISE_SLCT);
4054                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4055                                 tg3_writephy(tp, MII_BMCR, bmcr |
4056                                                            BMCR_ANRESTART |
4057                                                            BMCR_ANENABLE);
4058                                 udelay(10);
4059                                 netif_carrier_off(tp->dev);
4060                         }
4061                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4062                         bmcr = new_bmcr;
4063                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4064                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4065                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4066                             ASIC_REV_5714) {
4067                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4068                                         bmsr |= BMSR_LSTATUS;
4069                                 else
4070                                         bmsr &= ~BMSR_LSTATUS;
4071                         }
4072                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4073                 }
4074         }
4075
4076         if (bmsr & BMSR_LSTATUS) {
4077                 current_speed = SPEED_1000;
4078                 current_link_up = 1;
4079                 if (bmcr & BMCR_FULLDPLX)
4080                         current_duplex = DUPLEX_FULL;
4081                 else
4082                         current_duplex = DUPLEX_HALF;
4083
4084                 local_adv = 0;
4085                 remote_adv = 0;
4086
4087                 if (bmcr & BMCR_ANENABLE) {
4088                         u32 common;
4089
4090                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4091                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4092                         common = local_adv & remote_adv;
4093                         if (common & (ADVERTISE_1000XHALF |
4094                                       ADVERTISE_1000XFULL)) {
4095                                 if (common & ADVERTISE_1000XFULL)
4096                                         current_duplex = DUPLEX_FULL;
4097                                 else
4098                                         current_duplex = DUPLEX_HALF;
4099                         }
4100                         else
4101                                 current_link_up = 0;
4102                 }
4103         }
4104
4105         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4106                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4107
4108         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4109         if (tp->link_config.active_duplex == DUPLEX_HALF)
4110                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4111
4112         tw32_f(MAC_MODE, tp->mac_mode);
4113         udelay(40);
4114
4115         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4116
4117         tp->link_config.active_speed = current_speed;
4118         tp->link_config.active_duplex = current_duplex;
4119
4120         if (current_link_up != netif_carrier_ok(tp->dev)) {
4121                 if (current_link_up)
4122                         netif_carrier_on(tp->dev);
4123                 else {
4124                         netif_carrier_off(tp->dev);
4125                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126                 }
4127                 tg3_link_report(tp);
4128         }
4129         return err;
4130 }
4131
4132 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4133 {
4134         if (tp->serdes_counter) {
4135                 /* Give autoneg time to complete. */
4136                 tp->serdes_counter--;
4137                 return;
4138         }
4139         if (!netif_carrier_ok(tp->dev) &&
4140             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4141                 u32 bmcr;
4142
4143                 tg3_readphy(tp, MII_BMCR, &bmcr);
4144                 if (bmcr & BMCR_ANENABLE) {
4145                         u32 phy1, phy2;
4146
4147                         /* Select shadow register 0x1f */
4148                         tg3_writephy(tp, 0x1c, 0x7c00);
4149                         tg3_readphy(tp, 0x1c, &phy1);
4150
4151                         /* Select expansion interrupt status register */
4152                         tg3_writephy(tp, 0x17, 0x0f01);
4153                         tg3_readphy(tp, 0x15, &phy2);
4154                         tg3_readphy(tp, 0x15, &phy2);
4155
4156                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4157                                 /* We have signal detect and not receiving
4158                                  * config code words, link is up by parallel
4159                                  * detection.
4160                                  */
4161
4162                                 bmcr &= ~BMCR_ANENABLE;
4163                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4164                                 tg3_writephy(tp, MII_BMCR, bmcr);
4165                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4166                         }
4167                 }
4168         }
4169         else if (netif_carrier_ok(tp->dev) &&
4170                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4171                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4172                 u32 phy2;
4173
4174                 /* Select expansion interrupt status register */
4175                 tg3_writephy(tp, 0x17, 0x0f01);
4176                 tg3_readphy(tp, 0x15, &phy2);
4177                 if (phy2 & 0x20) {
4178                         u32 bmcr;
4179
4180                         /* Config code words received, turn on autoneg. */
4181                         tg3_readphy(tp, MII_BMCR, &bmcr);
4182                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4183
4184                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4185
4186                 }
4187         }
4188 }
4189
4190 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4191 {
4192         int err;
4193
4194         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4195                 err = tg3_setup_fiber_phy(tp, force_reset);
4196         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4197                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4198         } else {
4199                 err = tg3_setup_copper_phy(tp, force_reset);
4200         }
4201
4202         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4203                 u32 val, scale;
4204
4205                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4206                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4207                         scale = 65;
4208                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4209                         scale = 6;
4210                 else
4211                         scale = 12;
4212
4213                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4214                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4215                 tw32(GRC_MISC_CFG, val);
4216         }
4217
4218         if (tp->link_config.active_speed == SPEED_1000 &&
4219             tp->link_config.active_duplex == DUPLEX_HALF)
4220                 tw32(MAC_TX_LENGTHS,
4221                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4222                       (6 << TX_LENGTHS_IPG_SHIFT) |
4223                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4224         else
4225                 tw32(MAC_TX_LENGTHS,
4226                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4227                       (6 << TX_LENGTHS_IPG_SHIFT) |
4228                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4229
4230         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4231                 if (netif_carrier_ok(tp->dev)) {
4232                         tw32(HOSTCC_STAT_COAL_TICKS,
4233                              tp->coal.stats_block_coalesce_usecs);
4234                 } else {
4235                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4236                 }
4237         }
4238
4239         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4240                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4241                 if (!netif_carrier_ok(tp->dev))
4242                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4243                               tp->pwrmgmt_thresh;
4244                 else
4245                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4246                 tw32(PCIE_PWR_MGMT_THRESH, val);
4247         }
4248
4249         return err;
4250 }
4251
4252 /* This is called whenever we suspect that the system chipset is re-
4253  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4254  * is bogus tx completions. We try to recover by setting the
4255  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4256  * in the workqueue.
4257  */
4258 static void tg3_tx_recover(struct tg3 *tp)
4259 {
4260         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4261                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4262
4263         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4264                "mapped I/O cycles to the network device, attempting to "
4265                "recover. Please report the problem to the driver maintainer "
4266                "and include system chipset information.\n", tp->dev->name);
4267
4268         spin_lock(&tp->lock);
4269         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4270         spin_unlock(&tp->lock);
4271 }
4272
4273 static inline u32 tg3_tx_avail(struct tg3 *tp)
4274 {
4275         smp_mb();
4276         return (tp->tx_pending -
4277                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4278 }
4279
4280 /* Tigon3 never reports partial packet sends.  So we do not
4281  * need special logic to handle SKBs that have not had all
4282  * of their frags sent yet, like SunGEM does.
4283  */
4284 static void tg3_tx(struct tg3_napi *tnapi)
4285 {
4286         struct tg3 *tp = tnapi->tp;
4287         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4288         u32 sw_idx = tp->tx_cons;
4289
4290         while (sw_idx != hw_idx) {
4291                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4292                 struct sk_buff *skb = ri->skb;
4293                 int i, tx_bug = 0;
4294
4295                 if (unlikely(skb == NULL)) {
4296                         tg3_tx_recover(tp);
4297                         return;
4298                 }
4299
4300                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4301
4302                 ri->skb = NULL;
4303
4304                 sw_idx = NEXT_TX(sw_idx);
4305
4306                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4307                         ri = &tp->tx_buffers[sw_idx];
4308                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4309                                 tx_bug = 1;
4310                         sw_idx = NEXT_TX(sw_idx);
4311                 }
4312
4313                 dev_kfree_skb(skb);
4314
4315                 if (unlikely(tx_bug)) {
4316                         tg3_tx_recover(tp);
4317                         return;
4318                 }
4319         }
4320
4321         tp->tx_cons = sw_idx;
4322
4323         /* Need to make the tx_cons update visible to tg3_start_xmit()
4324          * before checking for netif_queue_stopped().  Without the
4325          * memory barrier, there is a small possibility that tg3_start_xmit()
4326          * will miss it and cause the queue to be stopped forever.
4327          */
4328         smp_mb();
4329
4330         if (unlikely(netif_queue_stopped(tp->dev) &&
4331                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4332                 netif_tx_lock(tp->dev);
4333                 if (netif_queue_stopped(tp->dev) &&
4334                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4335                         netif_wake_queue(tp->dev);
4336                 netif_tx_unlock(tp->dev);
4337         }
4338 }
4339
4340 /* Returns size of skb allocated or < 0 on error.
4341  *
4342  * We only need to fill in the address because the other members
4343  * of the RX descriptor are invariant, see tg3_init_rings.
4344  *
4345  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4346  * posting buffers we only dirty the first cache line of the RX
4347  * descriptor (containing the address).  Whereas for the RX status
4348  * buffers the cpu only reads the last cacheline of the RX descriptor
4349  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4350  */
4351 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4352                             int src_idx, u32 dest_idx_unmasked)
4353 {
4354         struct tg3 *tp = tnapi->tp;
4355         struct tg3_rx_buffer_desc *desc;
4356         struct ring_info *map, *src_map;
4357         struct sk_buff *skb;
4358         dma_addr_t mapping;
4359         int skb_size, dest_idx;
4360         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4361
4362         src_map = NULL;
4363         switch (opaque_key) {
4364         case RXD_OPAQUE_RING_STD:
4365                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4366                 desc = &tpr->rx_std[dest_idx];
4367                 map = &tpr->rx_std_buffers[dest_idx];
4368                 if (src_idx >= 0)
4369                         src_map = &tpr->rx_std_buffers[src_idx];
4370                 skb_size = tp->rx_pkt_map_sz;
4371                 break;
4372
4373         case RXD_OPAQUE_RING_JUMBO:
4374                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4375                 desc = &tpr->rx_jmb[dest_idx].std;
4376                 map = &tpr->rx_jmb_buffers[dest_idx];
4377                 if (src_idx >= 0)
4378                         src_map = &tpr->rx_jmb_buffers[src_idx];
4379                 skb_size = TG3_RX_JMB_MAP_SZ;
4380                 break;
4381
4382         default:
4383                 return -EINVAL;
4384         }
4385
4386         /* Do not overwrite any of the map or rp information
4387          * until we are sure we can commit to a new buffer.
4388          *
4389          * Callers depend upon this behavior and assume that
4390          * we leave everything unchanged if we fail.
4391          */
4392         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4393         if (skb == NULL)
4394                 return -ENOMEM;
4395
4396         skb_reserve(skb, tp->rx_offset);
4397
4398         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4399                                  PCI_DMA_FROMDEVICE);
4400
4401         map->skb = skb;
4402         pci_unmap_addr_set(map, mapping, mapping);
4403
4404         if (src_map != NULL)
4405                 src_map->skb = NULL;
4406
4407         desc->addr_hi = ((u64)mapping >> 32);
4408         desc->addr_lo = ((u64)mapping & 0xffffffff);
4409
4410         return skb_size;
4411 }
4412
4413 /* We only need to move over in the address because the other
4414  * members of the RX descriptor are invariant.  See notes above
4415  * tg3_alloc_rx_skb for full details.
4416  */
4417 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4418                            int src_idx, u32 dest_idx_unmasked)
4419 {
4420         struct tg3 *tp = tnapi->tp;
4421         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4422         struct ring_info *src_map, *dest_map;
4423         int dest_idx;
4424         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4425
4426         switch (opaque_key) {
4427         case RXD_OPAQUE_RING_STD:
4428                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4429                 dest_desc = &tpr->rx_std[dest_idx];
4430                 dest_map = &tpr->rx_std_buffers[dest_idx];
4431                 src_desc = &tpr->rx_std[src_idx];
4432                 src_map = &tpr->rx_std_buffers[src_idx];
4433                 break;
4434
4435         case RXD_OPAQUE_RING_JUMBO:
4436                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4437                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4438                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4439                 src_desc = &tpr->rx_jmb[src_idx].std;
4440                 src_map = &tpr->rx_jmb_buffers[src_idx];
4441                 break;
4442
4443         default:
4444                 return;
4445         }
4446
4447         dest_map->skb = src_map->skb;
4448         pci_unmap_addr_set(dest_map, mapping,
4449                            pci_unmap_addr(src_map, mapping));
4450         dest_desc->addr_hi = src_desc->addr_hi;
4451         dest_desc->addr_lo = src_desc->addr_lo;
4452
4453         src_map->skb = NULL;
4454 }
4455
4456 /* The RX ring scheme is composed of multiple rings which post fresh
4457  * buffers to the chip, and one special ring the chip uses to report
4458  * status back to the host.
4459  *
4460  * The special ring reports the status of received packets to the
4461  * host.  The chip does not write into the original descriptor the
4462  * RX buffer was obtained from.  The chip simply takes the original
4463  * descriptor as provided by the host, updates the status and length
4464  * field, then writes this into the next status ring entry.
4465  *
4466  * Each ring the host uses to post buffers to the chip is described
4467  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4468  * it is first placed into the on-chip ram.  When the packet's length
4469  * is known, it walks down the TG3_BDINFO entries to select the ring.
4470  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4471  * which is within the range of the new packet's length is chosen.
4472  *
4473  * The "separate ring for rx status" scheme may sound queer, but it makes
4474  * sense from a cache coherency perspective.  If only the host writes
4475  * to the buffer post rings, and only the chip writes to the rx status
4476  * rings, then cache lines never move beyond shared-modified state.
4477  * If both the host and chip were to write into the same ring, cache line
4478  * eviction could occur since both entities want it in an exclusive state.
4479  */
4480 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4481 {
4482         struct tg3 *tp = tnapi->tp;
4483         u32 work_mask, rx_std_posted = 0;
4484         u32 sw_idx = tp->rx_rcb_ptr;
4485         u16 hw_idx;
4486         int received;
4487         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4488
4489         hw_idx = tp->hw_status->idx[0].rx_producer;
4490         /*
4491          * We need to order the read of hw_idx and the read of
4492          * the opaque cookie.
4493          */
4494         rmb();
4495         work_mask = 0;
4496         received = 0;
4497         while (sw_idx != hw_idx && budget > 0) {
4498                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4499                 unsigned int len;
4500                 struct sk_buff *skb;
4501                 dma_addr_t dma_addr;
4502                 u32 opaque_key, desc_idx, *post_ptr;
4503
4504                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4505                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4506                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4507                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4508                         dma_addr = pci_unmap_addr(ri, mapping);
4509                         skb = ri->skb;
4510                         post_ptr = &tpr->rx_std_ptr;
4511                         rx_std_posted++;
4512                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4513                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4514                         dma_addr = pci_unmap_addr(ri, mapping);
4515                         skb = ri->skb;
4516                         post_ptr = &tpr->rx_jmb_ptr;
4517                 } else
4518                         goto next_pkt_nopost;
4519
4520                 work_mask |= opaque_key;
4521
4522                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4523                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4524                 drop_it:
4525                         tg3_recycle_rx(tnapi, opaque_key,
4526                                        desc_idx, *post_ptr);
4527                 drop_it_no_recycle:
4528                         /* Other statistics kept track of by card. */
4529                         tp->net_stats.rx_dropped++;
4530                         goto next_pkt;
4531                 }
4532
4533                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4534                       ETH_FCS_LEN;
4535
4536                 if (len > RX_COPY_THRESHOLD
4537                         && tp->rx_offset == NET_IP_ALIGN
4538                         /* rx_offset will likely not equal NET_IP_ALIGN
4539                          * if this is a 5701 card running in PCI-X mode
4540                          * [see tg3_get_invariants()]
4541                          */
4542                 ) {
4543                         int skb_size;
4544
4545                         skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4546                                                     desc_idx, *post_ptr);
4547                         if (skb_size < 0)
4548                                 goto drop_it;
4549
4550                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4551                                          PCI_DMA_FROMDEVICE);
4552
4553                         skb_put(skb, len);
4554                 } else {
4555                         struct sk_buff *copy_skb;
4556
4557                         tg3_recycle_rx(tnapi, opaque_key,
4558                                        desc_idx, *post_ptr);
4559
4560                         copy_skb = netdev_alloc_skb(tp->dev,
4561                                                     len + TG3_RAW_IP_ALIGN);
4562                         if (copy_skb == NULL)
4563                                 goto drop_it_no_recycle;
4564
4565                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4566                         skb_put(copy_skb, len);
4567                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4568                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4569                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4570
4571                         /* We'll reuse the original ring buffer. */
4572                         skb = copy_skb;
4573                 }
4574
4575                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4576                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4577                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4578                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4579                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4580                 else
4581                         skb->ip_summed = CHECKSUM_NONE;
4582
4583                 skb->protocol = eth_type_trans(skb, tp->dev);
4584
4585                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4586                     skb->protocol != htons(ETH_P_8021Q)) {
4587                         dev_kfree_skb(skb);
4588                         goto next_pkt;
4589                 }
4590
4591 #if TG3_VLAN_TAG_USED
4592                 if (tp->vlgrp != NULL &&
4593                     desc->type_flags & RXD_FLAG_VLAN) {
4594                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4595                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4596                 } else
4597 #endif
4598                         napi_gro_receive(&tnapi->napi, skb);
4599
4600                 received++;
4601                 budget--;
4602
4603 next_pkt:
4604                 (*post_ptr)++;
4605
4606                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4607                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4608
4609                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4610                                      TG3_64BIT_REG_LOW, idx);
4611                         work_mask &= ~RXD_OPAQUE_RING_STD;
4612                         rx_std_posted = 0;
4613                 }
4614 next_pkt_nopost:
4615                 sw_idx++;
4616                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4617
4618                 /* Refresh hw_idx to see if there is new work */
4619                 if (sw_idx == hw_idx) {
4620                         hw_idx = tp->hw_status->idx[0].rx_producer;
4621                         rmb();
4622                 }
4623         }
4624
4625         /* ACK the status ring. */
4626         tp->rx_rcb_ptr = sw_idx;
4627         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4628
4629         /* Refill RX ring(s). */
4630         if (work_mask & RXD_OPAQUE_RING_STD) {
4631                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4632                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4633                              sw_idx);
4634         }
4635         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4636                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4637                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4638                              sw_idx);
4639         }
4640         mmiowb();
4641
4642         return received;
4643 }
4644
4645 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4646 {
4647         struct tg3 *tp = tnapi->tp;
4648         struct tg3_hw_status *sblk = tp->hw_status;
4649
4650         /* handle link change and other phy events */
4651         if (!(tp->tg3_flags &
4652               (TG3_FLAG_USE_LINKCHG_REG |
4653                TG3_FLAG_POLL_SERDES))) {
4654                 if (sblk->status & SD_STATUS_LINK_CHG) {
4655                         sblk->status = SD_STATUS_UPDATED |
4656                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4657                         spin_lock(&tp->lock);
4658                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4659                                 tw32_f(MAC_STATUS,
4660                                      (MAC_STATUS_SYNC_CHANGED |
4661                                       MAC_STATUS_CFG_CHANGED |
4662                                       MAC_STATUS_MI_COMPLETION |
4663                                       MAC_STATUS_LNKSTATE_CHANGED));
4664                                 udelay(40);
4665                         } else
4666                                 tg3_setup_phy(tp, 0);
4667                         spin_unlock(&tp->lock);
4668                 }
4669         }
4670
4671         /* run TX completion thread */
4672         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4673                 tg3_tx(tnapi);
4674                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4675                         return work_done;
4676         }
4677
4678         /* run RX thread, within the bounds set by NAPI.
4679          * All RX "locking" is done by ensuring outside
4680          * code synchronizes with tg3->napi.poll()
4681          */
4682         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4683                 work_done += tg3_rx(tnapi, budget - work_done);
4684
4685         return work_done;
4686 }
4687
4688 static int tg3_poll(struct napi_struct *napi, int budget)
4689 {
4690         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4691         struct tg3 *tp = tnapi->tp;
4692         int work_done = 0;
4693         struct tg3_hw_status *sblk = tp->hw_status;
4694
4695         while (1) {
4696                 work_done = tg3_poll_work(tnapi, work_done, budget);
4697
4698                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4699                         goto tx_recovery;
4700
4701                 if (unlikely(work_done >= budget))
4702                         break;
4703
4704                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4705                         /* tp->last_tag is used in tg3_int_reenable() below
4706                          * to tell the hw how much work has been processed,
4707                          * so we must read it before checking for more work.
4708                          */
4709                         tp->last_tag = sblk->status_tag;
4710                         tp->last_irq_tag = tp->last_tag;
4711                         rmb();
4712                 } else
4713                         sblk->status &= ~SD_STATUS_UPDATED;
4714
4715                 if (likely(!tg3_has_work(tnapi))) {
4716                         napi_complete(napi);
4717                         tg3_int_reenable(tnapi);
4718                         break;
4719                 }
4720         }
4721
4722         return work_done;
4723
4724 tx_recovery:
4725         /* work_done is guaranteed to be less than budget. */
4726         napi_complete(napi);
4727         schedule_work(&tp->reset_task);
4728         return work_done;
4729 }
4730
4731 static void tg3_irq_quiesce(struct tg3 *tp)
4732 {
4733         BUG_ON(tp->irq_sync);
4734
4735         tp->irq_sync = 1;
4736         smp_mb();
4737
4738         synchronize_irq(tp->pdev->irq);
4739 }
4740
4741 static inline int tg3_irq_sync(struct tg3 *tp)
4742 {
4743         return tp->irq_sync;
4744 }
4745
4746 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4747  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4748  * with as well.  Most of the time, this is not necessary except when
4749  * shutting down the device.
4750  */
4751 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4752 {
4753         spin_lock_bh(&tp->lock);
4754         if (irq_sync)
4755                 tg3_irq_quiesce(tp);
4756 }
4757
4758 static inline void tg3_full_unlock(struct tg3 *tp)
4759 {
4760         spin_unlock_bh(&tp->lock);
4761 }
4762
4763 /* One-shot MSI handler - Chip automatically disables interrupt
4764  * after sending MSI so driver doesn't have to do it.
4765  */
4766 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4767 {
4768         struct tg3_napi *tnapi = dev_id;
4769         struct tg3 *tp = tnapi->tp;
4770
4771         prefetch(tp->hw_status);
4772         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4773
4774         if (likely(!tg3_irq_sync(tp)))
4775                 napi_schedule(&tnapi->napi);
4776
4777         return IRQ_HANDLED;
4778 }
4779
4780 /* MSI ISR - No need to check for interrupt sharing and no need to
4781  * flush status block and interrupt mailbox. PCI ordering rules
4782  * guarantee that MSI will arrive after the status block.
4783  */
4784 static irqreturn_t tg3_msi(int irq, void *dev_id)
4785 {
4786         struct tg3_napi *tnapi = dev_id;
4787         struct tg3 *tp = tnapi->tp;
4788
4789         prefetch(tp->hw_status);
4790         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4791         /*
4792          * Writing any value to intr-mbox-0 clears PCI INTA# and
4793          * chip-internal interrupt pending events.
4794          * Writing non-zero to intr-mbox-0 additional tells the
4795          * NIC to stop sending us irqs, engaging "in-intr-handler"
4796          * event coalescing.
4797          */
4798         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4799         if (likely(!tg3_irq_sync(tp)))
4800                 napi_schedule(&tnapi->napi);
4801
4802         return IRQ_RETVAL(1);
4803 }
4804
4805 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4806 {
4807         struct tg3_napi *tnapi = dev_id;
4808         struct tg3 *tp = tnapi->tp;
4809         struct tg3_hw_status *sblk = tp->hw_status;
4810         unsigned int handled = 1;
4811
4812         /* In INTx mode, it is possible for the interrupt to arrive at
4813          * the CPU before the status block posted prior to the interrupt.
4814          * Reading the PCI State register will confirm whether the
4815          * interrupt is ours and will flush the status block.
4816          */
4817         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4818                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4819                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4820                         handled = 0;
4821                         goto out;
4822                 }
4823         }
4824
4825         /*
4826          * Writing any value to intr-mbox-0 clears PCI INTA# and
4827          * chip-internal interrupt pending events.
4828          * Writing non-zero to intr-mbox-0 additional tells the
4829          * NIC to stop sending us irqs, engaging "in-intr-handler"
4830          * event coalescing.
4831          *
4832          * Flush the mailbox to de-assert the IRQ immediately to prevent
4833          * spurious interrupts.  The flush impacts performance but
4834          * excessive spurious interrupts can be worse in some cases.
4835          */
4836         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4837         if (tg3_irq_sync(tp))
4838                 goto out;
4839         sblk->status &= ~SD_STATUS_UPDATED;
4840         if (likely(tg3_has_work(tnapi))) {
4841                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4842                 napi_schedule(&tnapi->napi);
4843         } else {
4844                 /* No work, shared interrupt perhaps?  re-enable
4845                  * interrupts, and flush that PCI write
4846                  */
4847                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4848                                0x00000000);
4849         }
4850 out:
4851         return IRQ_RETVAL(handled);
4852 }
4853
4854 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4855 {
4856         struct tg3_napi *tnapi = dev_id;
4857         struct tg3 *tp = tnapi->tp;
4858         struct tg3_hw_status *sblk = tp->hw_status;
4859         unsigned int handled = 1;
4860
4861         /* In INTx mode, it is possible for the interrupt to arrive at
4862          * the CPU before the status block posted prior to the interrupt.
4863          * Reading the PCI State register will confirm whether the
4864          * interrupt is ours and will flush the status block.
4865          */
4866         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4867                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4868                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4869                         handled = 0;
4870                         goto out;
4871                 }
4872         }
4873
4874         /*
4875          * writing any value to intr-mbox-0 clears PCI INTA# and
4876          * chip-internal interrupt pending events.
4877          * writing non-zero to intr-mbox-0 additional tells the
4878          * NIC to stop sending us irqs, engaging "in-intr-handler"
4879          * event coalescing.
4880          *
4881          * Flush the mailbox to de-assert the IRQ immediately to prevent
4882          * spurious interrupts.  The flush impacts performance but
4883          * excessive spurious interrupts can be worse in some cases.
4884          */
4885         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4886
4887         /*
4888          * In a shared interrupt configuration, sometimes other devices'
4889          * interrupts will scream.  We record the current status tag here
4890          * so that the above check can report that the screaming interrupts
4891          * are unhandled.  Eventually they will be silenced.
4892          */
4893         tp->last_irq_tag = sblk->status_tag;
4894
4895         if (tg3_irq_sync(tp))
4896                 goto out;
4897
4898         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4899
4900         napi_schedule(&tnapi->napi);
4901
4902 out:
4903         return IRQ_RETVAL(handled);
4904 }
4905
4906 /* ISR for interrupt test */
4907 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4908 {
4909         struct tg3_napi *tnapi = dev_id;
4910         struct tg3 *tp = tnapi->tp;
4911         struct tg3_hw_status *sblk = tp->hw_status;
4912
4913         if ((sblk->status & SD_STATUS_UPDATED) ||
4914             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4915                 tg3_disable_ints(tp);
4916                 return IRQ_RETVAL(1);
4917         }
4918         return IRQ_RETVAL(0);
4919 }
4920
4921 static int tg3_init_hw(struct tg3 *, int);
4922 static int tg3_halt(struct tg3 *, int, int);
4923
4924 /* Restart hardware after configuration changes, self-test, etc.
4925  * Invoked with tp->lock held.
4926  */
4927 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4928         __releases(tp->lock)
4929         __acquires(tp->lock)
4930 {
4931         int err;
4932
4933         err = tg3_init_hw(tp, reset_phy);
4934         if (err) {
4935                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4936                        "aborting.\n", tp->dev->name);
4937                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4938                 tg3_full_unlock(tp);
4939                 del_timer_sync(&tp->timer);
4940                 tp->irq_sync = 0;
4941                 napi_enable(&tp->napi[0].napi);
4942                 dev_close(tp->dev);
4943                 tg3_full_lock(tp, 0);
4944         }
4945         return err;
4946 }
4947
4948 #ifdef CONFIG_NET_POLL_CONTROLLER
4949 static void tg3_poll_controller(struct net_device *dev)
4950 {
4951         struct tg3 *tp = netdev_priv(dev);
4952
4953         tg3_interrupt(tp->pdev->irq, dev);
4954 }
4955 #endif
4956
4957 static void tg3_reset_task(struct work_struct *work)
4958 {
4959         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4960         int err;
4961         unsigned int restart_timer;
4962
4963         tg3_full_lock(tp, 0);
4964
4965         if (!netif_running(tp->dev)) {
4966                 tg3_full_unlock(tp);
4967                 return;
4968         }
4969
4970         tg3_full_unlock(tp);
4971
4972         tg3_phy_stop(tp);
4973
4974         tg3_netif_stop(tp);
4975
4976         tg3_full_lock(tp, 1);
4977
4978         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4979         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4980
4981         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4982                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4983                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4984                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4985                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4986         }
4987
4988         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4989         err = tg3_init_hw(tp, 1);
4990         if (err)
4991                 goto out;
4992
4993         tg3_netif_start(tp);
4994
4995         if (restart_timer)
4996                 mod_timer(&tp->timer, jiffies + 1);
4997
4998 out:
4999         tg3_full_unlock(tp);
5000
5001         if (!err)
5002                 tg3_phy_start(tp);
5003 }
5004
5005 static void tg3_dump_short_state(struct tg3 *tp)
5006 {
5007         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5008                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5009         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5010                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5011 }
5012
5013 static void tg3_tx_timeout(struct net_device *dev)
5014 {
5015         struct tg3 *tp = netdev_priv(dev);
5016
5017         if (netif_msg_tx_err(tp)) {
5018                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5019                        dev->name);
5020                 tg3_dump_short_state(tp);
5021         }
5022
5023         schedule_work(&tp->reset_task);
5024 }
5025
5026 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5027 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5028 {
5029         u32 base = (u32) mapping & 0xffffffff;
5030
5031         return ((base > 0xffffdcc0) &&
5032                 (base + len + 8 < base));
5033 }
5034
5035 /* Test for DMA addresses > 40-bit */
5036 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5037                                           int len)
5038 {
5039 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5040         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5041                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5042         return 0;
5043 #else
5044         return 0;
5045 #endif
5046 }
5047
5048 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5049
5050 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5051 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5052                                        u32 last_plus_one, u32 *start,
5053                                        u32 base_flags, u32 mss)
5054 {
5055         struct sk_buff *new_skb;
5056         dma_addr_t new_addr = 0;
5057         u32 entry = *start;
5058         int i, ret = 0;
5059
5060         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5061                 new_skb = skb_copy(skb, GFP_ATOMIC);
5062         else {
5063                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5064
5065                 new_skb = skb_copy_expand(skb,
5066                                           skb_headroom(skb) + more_headroom,
5067                                           skb_tailroom(skb), GFP_ATOMIC);
5068         }
5069
5070         if (!new_skb) {
5071                 ret = -1;
5072         } else {
5073                 /* New SKB is guaranteed to be linear. */
5074                 entry = *start;
5075                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5076                 new_addr = skb_shinfo(new_skb)->dma_head;
5077
5078                 /* Make sure new skb does not cross any 4G boundaries.
5079                  * Drop the packet if it does.
5080                  */
5081                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5082                         if (!ret)
5083                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5084                                               DMA_TO_DEVICE);
5085                         ret = -1;
5086                         dev_kfree_skb(new_skb);
5087                         new_skb = NULL;
5088                 } else {
5089                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5090                                     base_flags, 1 | (mss << 1));
5091                         *start = NEXT_TX(entry);
5092                 }
5093         }
5094
5095         /* Now clean up the sw ring entries. */
5096         i = 0;
5097         while (entry != last_plus_one) {
5098                 if (i == 0) {
5099                         tp->tx_buffers[entry].skb = new_skb;
5100                 } else {
5101                         tp->tx_buffers[entry].skb = NULL;
5102                 }
5103                 entry = NEXT_TX(entry);
5104                 i++;
5105         }
5106
5107         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5108         dev_kfree_skb(skb);
5109
5110         return ret;
5111 }
5112
5113 static void tg3_set_txd(struct tg3 *tp, int entry,
5114                         dma_addr_t mapping, int len, u32 flags,
5115                         u32 mss_and_is_end)
5116 {
5117         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5118         int is_end = (mss_and_is_end & 0x1);
5119         u32 mss = (mss_and_is_end >> 1);
5120         u32 vlan_tag = 0;
5121
5122         if (is_end)
5123                 flags |= TXD_FLAG_END;
5124         if (flags & TXD_FLAG_VLAN) {
5125                 vlan_tag = flags >> 16;
5126                 flags &= 0xffff;
5127         }
5128         vlan_tag |= (mss << TXD_MSS_SHIFT);
5129
5130         txd->addr_hi = ((u64) mapping >> 32);
5131         txd->addr_lo = ((u64) mapping & 0xffffffff);
5132         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5133         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5134 }
5135
5136 /* hard_start_xmit for devices that don't have any bugs and
5137  * support TG3_FLG2_HW_TSO_2 only.
5138  */
5139 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5140 {
5141         struct tg3 *tp = netdev_priv(dev);
5142         u32 len, entry, base_flags, mss;
5143         struct skb_shared_info *sp;
5144         dma_addr_t mapping;
5145
5146         len = skb_headlen(skb);
5147
5148         /* We are running in BH disabled context with netif_tx_lock
5149          * and TX reclaim runs via tp->napi.poll inside of a software
5150          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5151          * no IRQ context deadlocks to worry about either.  Rejoice!
5152          */
5153         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5154                 if (!netif_queue_stopped(dev)) {
5155                         netif_stop_queue(dev);
5156
5157                         /* This is a hard error, log it. */
5158                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5159                                "queue awake!\n", dev->name);
5160                 }
5161                 return NETDEV_TX_BUSY;
5162         }
5163
5164         entry = tp->tx_prod;
5165         base_flags = 0;
5166         mss = 0;
5167         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5168                 int tcp_opt_len, ip_tcp_len;
5169
5170                 if (skb_header_cloned(skb) &&
5171                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5172                         dev_kfree_skb(skb);
5173                         goto out_unlock;
5174                 }
5175
5176                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5177                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5178                 else {
5179                         struct iphdr *iph = ip_hdr(skb);
5180
5181                         tcp_opt_len = tcp_optlen(skb);
5182                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5183
5184                         iph->check = 0;
5185                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5186                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5187                 }
5188
5189                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5190                                TXD_FLAG_CPU_POST_DMA);
5191
5192                 tcp_hdr(skb)->check = 0;
5193
5194         }
5195         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5196                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5197 #if TG3_VLAN_TAG_USED
5198         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5199                 base_flags |= (TXD_FLAG_VLAN |
5200                                (vlan_tx_tag_get(skb) << 16));
5201 #endif
5202
5203         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5204                 dev_kfree_skb(skb);
5205                 goto out_unlock;
5206         }
5207
5208         sp = skb_shinfo(skb);
5209
5210         mapping = sp->dma_head;
5211
5212         tp->tx_buffers[entry].skb = skb;
5213
5214         tg3_set_txd(tp, entry, mapping, len, base_flags,
5215                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5216
5217         entry = NEXT_TX(entry);
5218
5219         /* Now loop through additional data fragments, and queue them. */
5220         if (skb_shinfo(skb)->nr_frags > 0) {
5221                 unsigned int i, last;
5222
5223                 last = skb_shinfo(skb)->nr_frags - 1;
5224                 for (i = 0; i <= last; i++) {
5225                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5226
5227                         len = frag->size;
5228                         mapping = sp->dma_maps[i];
5229                         tp->tx_buffers[entry].skb = NULL;
5230
5231                         tg3_set_txd(tp, entry, mapping, len,
5232                                     base_flags, (i == last) | (mss << 1));
5233
5234                         entry = NEXT_TX(entry);
5235                 }
5236         }
5237
5238         /* Packets are ready, update Tx producer idx local and on card. */
5239         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5240
5241         tp->tx_prod = entry;
5242         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5243                 netif_stop_queue(dev);
5244                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5245                         netif_wake_queue(tp->dev);
5246         }
5247
5248 out_unlock:
5249         mmiowb();
5250
5251         return NETDEV_TX_OK;
5252 }
5253
5254 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5255
5256 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5257  * TSO header is greater than 80 bytes.
5258  */
5259 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5260 {
5261         struct sk_buff *segs, *nskb;
5262
5263         /* Estimate the number of fragments in the worst case */
5264         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5265                 netif_stop_queue(tp->dev);
5266                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5267                         return NETDEV_TX_BUSY;
5268
5269                 netif_wake_queue(tp->dev);
5270         }
5271
5272         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5273         if (IS_ERR(segs))
5274                 goto tg3_tso_bug_end;
5275
5276         do {
5277                 nskb = segs;
5278                 segs = segs->next;
5279                 nskb->next = NULL;
5280                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5281         } while (segs);
5282
5283 tg3_tso_bug_end:
5284         dev_kfree_skb(skb);
5285
5286         return NETDEV_TX_OK;
5287 }
5288
5289 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5290  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5291  */
5292 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5293 {
5294         struct tg3 *tp = netdev_priv(dev);
5295         u32 len, entry, base_flags, mss;
5296         struct skb_shared_info *sp;
5297         int would_hit_hwbug;
5298         dma_addr_t mapping;
5299
5300         len = skb_headlen(skb);
5301
5302         /* We are running in BH disabled context with netif_tx_lock
5303          * and TX reclaim runs via tp->napi.poll inside of a software
5304          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5305          * no IRQ context deadlocks to worry about either.  Rejoice!
5306          */
5307         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5308                 if (!netif_queue_stopped(dev)) {
5309                         netif_stop_queue(dev);
5310
5311                         /* This is a hard error, log it. */
5312                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5313                                "queue awake!\n", dev->name);
5314                 }
5315                 return NETDEV_TX_BUSY;
5316         }
5317
5318         entry = tp->tx_prod;
5319         base_flags = 0;
5320         if (skb->ip_summed == CHECKSUM_PARTIAL)
5321                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5322         mss = 0;
5323         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5324                 struct iphdr *iph;
5325                 int tcp_opt_len, ip_tcp_len, hdr_len;
5326
5327                 if (skb_header_cloned(skb) &&
5328                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5329                         dev_kfree_skb(skb);
5330                         goto out_unlock;
5331                 }
5332
5333                 tcp_opt_len = tcp_optlen(skb);
5334                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5335
5336                 hdr_len = ip_tcp_len + tcp_opt_len;
5337                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5338                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5339                         return (tg3_tso_bug(tp, skb));
5340
5341                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5342                                TXD_FLAG_CPU_POST_DMA);
5343
5344                 iph = ip_hdr(skb);
5345                 iph->check = 0;
5346                 iph->tot_len = htons(mss + hdr_len);
5347                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5348                         tcp_hdr(skb)->check = 0;
5349                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5350                 } else
5351                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5352                                                                  iph->daddr, 0,
5353                                                                  IPPROTO_TCP,
5354                                                                  0);
5355
5356                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5357                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5358                         if (tcp_opt_len || iph->ihl > 5) {
5359                                 int tsflags;
5360
5361                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5362                                 mss |= (tsflags << 11);
5363                         }
5364                 } else {
5365                         if (tcp_opt_len || iph->ihl > 5) {
5366                                 int tsflags;
5367
5368                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5369                                 base_flags |= tsflags << 12;
5370                         }
5371                 }
5372         }
5373 #if TG3_VLAN_TAG_USED
5374         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5375                 base_flags |= (TXD_FLAG_VLAN |
5376                                (vlan_tx_tag_get(skb) << 16));
5377 #endif
5378
5379         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5380                 dev_kfree_skb(skb);
5381                 goto out_unlock;
5382         }
5383
5384         sp = skb_shinfo(skb);
5385
5386         mapping = sp->dma_head;
5387
5388         tp->tx_buffers[entry].skb = skb;
5389
5390         would_hit_hwbug = 0;
5391
5392         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5393                 would_hit_hwbug = 1;
5394         else if (tg3_4g_overflow_test(mapping, len))
5395                 would_hit_hwbug = 1;
5396
5397         tg3_set_txd(tp, entry, mapping, len, base_flags,
5398                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5399
5400         entry = NEXT_TX(entry);
5401
5402         /* Now loop through additional data fragments, and queue them. */
5403         if (skb_shinfo(skb)->nr_frags > 0) {
5404                 unsigned int i, last;
5405
5406                 last = skb_shinfo(skb)->nr_frags - 1;
5407                 for (i = 0; i <= last; i++) {
5408                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5409
5410                         len = frag->size;
5411                         mapping = sp->dma_maps[i];
5412
5413                         tp->tx_buffers[entry].skb = NULL;
5414
5415                         if (tg3_4g_overflow_test(mapping, len))
5416                                 would_hit_hwbug = 1;
5417
5418                         if (tg3_40bit_overflow_test(tp, mapping, len))
5419                                 would_hit_hwbug = 1;
5420
5421                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5422                                 tg3_set_txd(tp, entry, mapping, len,
5423                                             base_flags, (i == last)|(mss << 1));
5424                         else
5425                                 tg3_set_txd(tp, entry, mapping, len,
5426                                             base_flags, (i == last));
5427
5428                         entry = NEXT_TX(entry);
5429                 }
5430         }
5431
5432         if (would_hit_hwbug) {
5433                 u32 last_plus_one = entry;
5434                 u32 start;
5435
5436                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5437                 start &= (TG3_TX_RING_SIZE - 1);
5438
5439                 /* If the workaround fails due to memory/mapping
5440                  * failure, silently drop this packet.
5441                  */
5442                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5443                                                 &start, base_flags, mss))
5444                         goto out_unlock;
5445
5446                 entry = start;
5447         }
5448
5449         /* Packets are ready, update Tx producer idx local and on card. */
5450         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5451
5452         tp->tx_prod = entry;
5453         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5454                 netif_stop_queue(dev);
5455                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5456                         netif_wake_queue(tp->dev);
5457         }
5458
5459 out_unlock:
5460         mmiowb();
5461
5462         return NETDEV_TX_OK;
5463 }
5464
5465 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5466                                int new_mtu)
5467 {
5468         dev->mtu = new_mtu;
5469
5470         if (new_mtu > ETH_DATA_LEN) {
5471                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5472                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5473                         ethtool_op_set_tso(dev, 0);
5474                 }
5475                 else
5476                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5477         } else {
5478                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5479                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5480                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5481         }
5482 }
5483
5484 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5485 {
5486         struct tg3 *tp = netdev_priv(dev);
5487         int err;
5488
5489         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5490                 return -EINVAL;
5491
5492         if (!netif_running(dev)) {
5493                 /* We'll just catch it later when the
5494                  * device is up'd.
5495                  */
5496                 tg3_set_mtu(dev, tp, new_mtu);
5497                 return 0;
5498         }
5499
5500         tg3_phy_stop(tp);
5501
5502         tg3_netif_stop(tp);
5503
5504         tg3_full_lock(tp, 1);
5505
5506         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5507
5508         tg3_set_mtu(dev, tp, new_mtu);
5509
5510         err = tg3_restart_hw(tp, 0);
5511
5512         if (!err)
5513                 tg3_netif_start(tp);
5514
5515         tg3_full_unlock(tp);
5516
5517         if (!err)
5518                 tg3_phy_start(tp);
5519
5520         return err;
5521 }
5522
5523 static void tg3_rx_prodring_free(struct tg3 *tp,
5524                                  struct tg3_rx_prodring_set *tpr)
5525 {
5526         struct ring_info *rxp;
5527         int i;
5528
5529         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5530                 rxp = &tpr->rx_std_buffers[i];
5531
5532                 if (rxp->skb == NULL)
5533                         continue;
5534
5535                 pci_unmap_single(tp->pdev,
5536                                  pci_unmap_addr(rxp, mapping),
5537                                  tp->rx_pkt_map_sz,
5538                                  PCI_DMA_FROMDEVICE);
5539                 dev_kfree_skb_any(rxp->skb);
5540                 rxp->skb = NULL;
5541         }
5542
5543         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5544                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5545                         rxp = &tpr->rx_jmb_buffers[i];
5546
5547                         if (rxp->skb == NULL)
5548                                 continue;
5549
5550                         pci_unmap_single(tp->pdev,
5551                                          pci_unmap_addr(rxp, mapping),
5552                                          TG3_RX_JMB_MAP_SZ,
5553                                          PCI_DMA_FROMDEVICE);
5554                         dev_kfree_skb_any(rxp->skb);
5555                         rxp->skb = NULL;
5556                 }
5557         }
5558 }
5559
5560 /* Initialize tx/rx rings for packet processing.
5561  *
5562  * The chip has been shut down and the driver detached from
5563  * the networking, so no interrupts or new tx packets will
5564  * end up in the driver.  tp->{tx,}lock are held and thus
5565  * we may not sleep.
5566  */
5567 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5568                                  struct tg3_rx_prodring_set *tpr)
5569 {
5570         u32 i, rx_pkt_dma_sz;
5571         struct tg3_napi *tnapi = &tp->napi[0];
5572
5573         /* Zero out all descriptors. */
5574         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5575
5576         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5577         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5578             tp->dev->mtu > ETH_DATA_LEN)
5579                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5580         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5581
5582         /* Initialize invariants of the rings, we only set this
5583          * stuff once.  This works because the card does not
5584          * write into the rx buffer posting rings.
5585          */
5586         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5587                 struct tg3_rx_buffer_desc *rxd;
5588
5589                 rxd = &tpr->rx_std[i];
5590                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5591                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5592                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5593                                (i << RXD_OPAQUE_INDEX_SHIFT));
5594         }
5595
5596         /* Now allocate fresh SKBs for each rx ring. */
5597         for (i = 0; i < tp->rx_pending; i++) {
5598                 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5599                         printk(KERN_WARNING PFX
5600                                "%s: Using a smaller RX standard ring, "
5601                                "only %d out of %d buffers were allocated "
5602                                "successfully.\n",
5603                                tp->dev->name, i, tp->rx_pending);
5604                         if (i == 0)
5605                                 goto initfail;
5606                         tp->rx_pending = i;
5607                         break;
5608                 }
5609         }
5610
5611         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5612                 goto done;
5613
5614         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5615
5616         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5617                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5618                         struct tg3_rx_buffer_desc *rxd;
5619
5620                         rxd = &tpr->rx_jmb[i].std;
5621                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5622                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5623                                 RXD_FLAG_JUMBO;
5624                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5625                                (i << RXD_OPAQUE_INDEX_SHIFT));
5626                 }
5627
5628                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5629                         if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5630                                              -1, i) < 0) {
5631                                 printk(KERN_WARNING PFX
5632                                        "%s: Using a smaller RX jumbo ring, "
5633                                        "only %d out of %d buffers were "
5634                                        "allocated successfully.\n",
5635                                        tp->dev->name, i, tp->rx_jumbo_pending);
5636                                 if (i == 0)
5637                                         goto initfail;
5638                                 tp->rx_jumbo_pending = i;
5639                                 break;
5640                         }
5641                 }
5642         }
5643
5644 done:
5645         return 0;
5646
5647 initfail:
5648         tg3_rx_prodring_free(tp, tpr);
5649         return -ENOMEM;
5650 }
5651
5652 static void tg3_rx_prodring_fini(struct tg3 *tp,
5653                                  struct tg3_rx_prodring_set *tpr)
5654 {
5655         kfree(tpr->rx_std_buffers);
5656         tpr->rx_std_buffers = NULL;
5657         kfree(tpr->rx_jmb_buffers);
5658         tpr->rx_jmb_buffers = NULL;
5659         if (tpr->rx_std) {
5660                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5661                                     tpr->rx_std, tpr->rx_std_mapping);
5662                 tpr->rx_std = NULL;
5663         }
5664         if (tpr->rx_jmb) {
5665                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5666                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5667                 tpr->rx_jmb = NULL;
5668         }
5669 }
5670
5671 static int tg3_rx_prodring_init(struct tg3 *tp,
5672                                 struct tg3_rx_prodring_set *tpr)
5673 {
5674         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5675                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5676         if (!tpr->rx_std_buffers)
5677                 return -ENOMEM;
5678
5679         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5680                                            &tpr->rx_std_mapping);
5681         if (!tpr->rx_std)
5682                 goto err_out;
5683
5684         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5685                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5686                                               TG3_RX_JUMBO_RING_SIZE,
5687                                               GFP_KERNEL);
5688                 if (!tpr->rx_jmb_buffers)
5689                         goto err_out;
5690
5691                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5692                                                    TG3_RX_JUMBO_RING_BYTES,
5693                                                    &tpr->rx_jmb_mapping);
5694                 if (!tpr->rx_jmb)
5695                         goto err_out;
5696         }
5697
5698         return 0;
5699
5700 err_out:
5701         tg3_rx_prodring_fini(tp, tpr);
5702         return -ENOMEM;
5703 }
5704
5705 /* Free up pending packets in all rx/tx rings.
5706  *
5707  * The chip has been shut down and the driver detached from
5708  * the networking, so no interrupts or new tx packets will
5709  * end up in the driver.  tp->{tx,}lock is not held and we are not
5710  * in an interrupt context and thus may sleep.
5711  */
5712 static void tg3_free_rings(struct tg3 *tp)
5713 {
5714         int i;
5715
5716         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5717                 struct tx_ring_info *txp;
5718                 struct sk_buff *skb;
5719
5720                 txp = &tp->tx_buffers[i];
5721                 skb = txp->skb;
5722
5723                 if (skb == NULL) {
5724                         i++;
5725                         continue;
5726                 }
5727
5728                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5729
5730                 txp->skb = NULL;
5731
5732                 i += skb_shinfo(skb)->nr_frags + 1;
5733
5734                 dev_kfree_skb_any(skb);
5735         }
5736
5737         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5738 }
5739
5740 /* Initialize tx/rx rings for packet processing.
5741  *
5742  * The chip has been shut down and the driver detached from
5743  * the networking, so no interrupts or new tx packets will
5744  * end up in the driver.  tp->{tx,}lock are held and thus
5745  * we may not sleep.
5746  */
5747 static int tg3_init_rings(struct tg3 *tp)
5748 {
5749         /* Free up all the SKBs. */
5750         tg3_free_rings(tp);
5751
5752         /* Zero out all descriptors. */
5753         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5754         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5755
5756         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5757 }
5758
5759 /*
5760  * Must not be invoked with interrupt sources disabled and
5761  * the hardware shutdown down.
5762  */
5763 static void tg3_free_consistent(struct tg3 *tp)
5764 {
5765         kfree(tp->tx_buffers);
5766         tp->tx_buffers = NULL;
5767         if (tp->rx_rcb) {
5768                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5769                                     tp->rx_rcb, tp->rx_rcb_mapping);
5770                 tp->rx_rcb = NULL;
5771         }
5772         if (tp->tx_ring) {
5773                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5774                         tp->tx_ring, tp->tx_desc_mapping);
5775                 tp->tx_ring = NULL;
5776         }
5777         if (tp->hw_status) {
5778                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5779                                     tp->hw_status, tp->status_mapping);
5780                 tp->hw_status = NULL;
5781         }
5782         if (tp->hw_stats) {
5783                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5784                                     tp->hw_stats, tp->stats_mapping);
5785                 tp->hw_stats = NULL;
5786         }
5787         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5788 }
5789
5790 /*
5791  * Must not be invoked with interrupt sources disabled and
5792  * the hardware shutdown down.  Can sleep.
5793  */
5794 static int tg3_alloc_consistent(struct tg3 *tp)
5795 {
5796         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5797                 return -ENOMEM;
5798
5799         tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5800                                  TG3_TX_RING_SIZE, GFP_KERNEL);
5801         if (!tp->tx_buffers)
5802                 goto err_out;
5803
5804         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5805                                           &tp->rx_rcb_mapping);
5806         if (!tp->rx_rcb)
5807                 goto err_out;
5808
5809         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5810                                            &tp->tx_desc_mapping);
5811         if (!tp->tx_ring)
5812                 goto err_out;
5813
5814         tp->hw_status = pci_alloc_consistent(tp->pdev,
5815                                              TG3_HW_STATUS_SIZE,
5816                                              &tp->status_mapping);
5817         if (!tp->hw_status)
5818                 goto err_out;
5819
5820         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5821                                             sizeof(struct tg3_hw_stats),
5822                                             &tp->stats_mapping);
5823         if (!tp->hw_stats)
5824                 goto err_out;
5825
5826         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5827         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5828
5829         return 0;
5830
5831 err_out:
5832         tg3_free_consistent(tp);
5833         return -ENOMEM;
5834 }
5835
5836 #define MAX_WAIT_CNT 1000
5837
5838 /* To stop a block, clear the enable bit and poll till it
5839  * clears.  tp->lock is held.
5840  */
5841 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5842 {
5843         unsigned int i;
5844         u32 val;
5845
5846         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5847                 switch (ofs) {
5848                 case RCVLSC_MODE:
5849                 case DMAC_MODE:
5850                 case MBFREE_MODE:
5851                 case BUFMGR_MODE:
5852                 case MEMARB_MODE:
5853                         /* We can't enable/disable these bits of the
5854                          * 5705/5750, just say success.
5855                          */
5856                         return 0;
5857
5858                 default:
5859                         break;
5860                 }
5861         }
5862
5863         val = tr32(ofs);
5864         val &= ~enable_bit;
5865         tw32_f(ofs, val);
5866
5867         for (i = 0; i < MAX_WAIT_CNT; i++) {
5868                 udelay(100);
5869                 val = tr32(ofs);
5870                 if ((val & enable_bit) == 0)
5871                         break;
5872         }
5873
5874         if (i == MAX_WAIT_CNT && !silent) {
5875                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5876                        "ofs=%lx enable_bit=%x\n",
5877                        ofs, enable_bit);
5878                 return -ENODEV;
5879         }
5880
5881         return 0;
5882 }
5883
5884 /* tp->lock is held. */
5885 static int tg3_abort_hw(struct tg3 *tp, int silent)
5886 {
5887         int i, err;
5888
5889         tg3_disable_ints(tp);
5890
5891         tp->rx_mode &= ~RX_MODE_ENABLE;
5892         tw32_f(MAC_RX_MODE, tp->rx_mode);
5893         udelay(10);
5894
5895         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5896         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5897         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5898         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5899         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5900         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5901
5902         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5903         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5904         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5905         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5906         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5907         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5908         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5909
5910         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5911         tw32_f(MAC_MODE, tp->mac_mode);
5912         udelay(40);
5913
5914         tp->tx_mode &= ~TX_MODE_ENABLE;
5915         tw32_f(MAC_TX_MODE, tp->tx_mode);
5916
5917         for (i = 0; i < MAX_WAIT_CNT; i++) {
5918                 udelay(100);
5919                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5920                         break;
5921         }
5922         if (i >= MAX_WAIT_CNT) {
5923                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5924                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5925                        tp->dev->name, tr32(MAC_TX_MODE));
5926                 err |= -ENODEV;
5927         }
5928
5929         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5930         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5931         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5932
5933         tw32(FTQ_RESET, 0xffffffff);
5934         tw32(FTQ_RESET, 0x00000000);
5935
5936         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5937         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5938
5939         if (tp->hw_status)
5940                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5941         if (tp->hw_stats)
5942                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5943
5944         return err;
5945 }
5946
5947 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5948 {
5949         int i;
5950         u32 apedata;
5951
5952         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5953         if (apedata != APE_SEG_SIG_MAGIC)
5954                 return;
5955
5956         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5957         if (!(apedata & APE_FW_STATUS_READY))
5958                 return;
5959
5960         /* Wait for up to 1 millisecond for APE to service previous event. */
5961         for (i = 0; i < 10; i++) {
5962                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5963                         return;
5964
5965                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5966
5967                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5968                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5969                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5970
5971                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5972
5973                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5974                         break;
5975
5976                 udelay(100);
5977         }
5978
5979         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5980                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5981 }
5982
5983 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5984 {
5985         u32 event;
5986         u32 apedata;
5987
5988         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5989                 return;
5990
5991         switch (kind) {
5992                 case RESET_KIND_INIT:
5993                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5994                                         APE_HOST_SEG_SIG_MAGIC);
5995                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5996                                         APE_HOST_SEG_LEN_MAGIC);
5997                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5998                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5999                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6000                                         APE_HOST_DRIVER_ID_MAGIC);
6001                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6002                                         APE_HOST_BEHAV_NO_PHYLOCK);
6003
6004                         event = APE_EVENT_STATUS_STATE_START;
6005                         break;
6006                 case RESET_KIND_SHUTDOWN:
6007                         /* With the interface we are currently using,
6008                          * APE does not track driver state.  Wiping
6009                          * out the HOST SEGMENT SIGNATURE forces
6010                          * the APE to assume OS absent status.
6011                          */
6012                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6013
6014                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6015                         break;
6016                 case RESET_KIND_SUSPEND:
6017                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6018                         break;
6019                 default:
6020                         return;
6021         }
6022
6023         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6024
6025         tg3_ape_send_event(tp, event);
6026 }
6027
6028 /* tp->lock is held. */
6029 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6030 {
6031         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6032                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6033
6034         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6035                 switch (kind) {
6036                 case RESET_KIND_INIT:
6037                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6038                                       DRV_STATE_START);
6039                         break;
6040
6041                 case RESET_KIND_SHUTDOWN:
6042                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6043                                       DRV_STATE_UNLOAD);
6044                         break;
6045
6046                 case RESET_KIND_SUSPEND:
6047                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6048                                       DRV_STATE_SUSPEND);
6049                         break;
6050
6051                 default:
6052                         break;
6053                 }
6054         }
6055
6056         if (kind == RESET_KIND_INIT ||
6057             kind == RESET_KIND_SUSPEND)
6058                 tg3_ape_driver_state_change(tp, kind);
6059 }
6060
6061 /* tp->lock is held. */
6062 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6063 {
6064         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6065                 switch (kind) {
6066                 case RESET_KIND_INIT:
6067                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6068                                       DRV_STATE_START_DONE);
6069                         break;
6070
6071                 case RESET_KIND_SHUTDOWN:
6072                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6073                                       DRV_STATE_UNLOAD_DONE);
6074                         break;
6075
6076                 default:
6077                         break;
6078                 }
6079         }
6080
6081         if (kind == RESET_KIND_SHUTDOWN)
6082                 tg3_ape_driver_state_change(tp, kind);
6083 }
6084
6085 /* tp->lock is held. */
6086 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6087 {
6088         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6089                 switch (kind) {
6090                 case RESET_KIND_INIT:
6091                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6092                                       DRV_STATE_START);
6093                         break;
6094
6095                 case RESET_KIND_SHUTDOWN:
6096                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6097                                       DRV_STATE_UNLOAD);
6098                         break;
6099
6100                 case RESET_KIND_SUSPEND:
6101                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6102                                       DRV_STATE_SUSPEND);
6103                         break;
6104
6105                 default:
6106                         break;
6107                 }
6108         }
6109 }
6110
6111 static int tg3_poll_fw(struct tg3 *tp)
6112 {
6113         int i;
6114         u32 val;
6115
6116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6117                 /* Wait up to 20ms for init done. */
6118                 for (i = 0; i < 200; i++) {
6119                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6120                                 return 0;
6121                         udelay(100);
6122                 }
6123                 return -ENODEV;
6124         }
6125
6126         /* Wait for firmware initialization to complete. */
6127         for (i = 0; i < 100000; i++) {
6128                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6129                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6130                         break;
6131                 udelay(10);
6132         }
6133
6134         /* Chip might not be fitted with firmware.  Some Sun onboard
6135          * parts are configured like that.  So don't signal the timeout
6136          * of the above loop as an error, but do report the lack of
6137          * running firmware once.
6138          */
6139         if (i >= 100000 &&
6140             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6141                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6142
6143                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6144                        tp->dev->name);
6145         }
6146
6147         return 0;
6148 }
6149
6150 /* Save PCI command register before chip reset */
6151 static void tg3_save_pci_state(struct tg3 *tp)
6152 {
6153         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6154 }
6155
6156 /* Restore PCI state after chip reset */
6157 static void tg3_restore_pci_state(struct tg3 *tp)
6158 {
6159         u32 val;
6160
6161         /* Re-enable indirect register accesses. */
6162         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6163                                tp->misc_host_ctrl);
6164
6165         /* Set MAX PCI retry to zero. */
6166         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6167         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6168             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6169                 val |= PCISTATE_RETRY_SAME_DMA;
6170         /* Allow reads and writes to the APE register and memory space. */
6171         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6172                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6173                        PCISTATE_ALLOW_APE_SHMEM_WR;
6174         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6175
6176         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6177
6178         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6179                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6180                         pcie_set_readrq(tp->pdev, 4096);
6181                 else {
6182                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6183                                               tp->pci_cacheline_sz);
6184                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6185                                               tp->pci_lat_timer);
6186                 }
6187         }
6188
6189         /* Make sure PCI-X relaxed ordering bit is clear. */
6190         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6191                 u16 pcix_cmd;
6192
6193                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6194                                      &pcix_cmd);
6195                 pcix_cmd &= ~PCI_X_CMD_ERO;
6196                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6197                                       pcix_cmd);
6198         }
6199
6200         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6201
6202                 /* Chip reset on 5780 will reset MSI enable bit,
6203                  * so need to restore it.
6204                  */
6205                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6206                         u16 ctrl;
6207
6208                         pci_read_config_word(tp->pdev,
6209                                              tp->msi_cap + PCI_MSI_FLAGS,
6210                                              &ctrl);
6211                         pci_write_config_word(tp->pdev,
6212                                               tp->msi_cap + PCI_MSI_FLAGS,
6213                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6214                         val = tr32(MSGINT_MODE);
6215                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6216                 }
6217         }
6218 }
6219
6220 static void tg3_stop_fw(struct tg3 *);
6221
6222 /* tp->lock is held. */
6223 static int tg3_chip_reset(struct tg3 *tp)
6224 {
6225         u32 val;
6226         void (*write_op)(struct tg3 *, u32, u32);
6227         int err;
6228
6229         tg3_nvram_lock(tp);
6230
6231         tg3_mdio_stop(tp);
6232
6233         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6234
6235         /* No matching tg3_nvram_unlock() after this because
6236          * chip reset below will undo the nvram lock.
6237          */
6238         tp->nvram_lock_cnt = 0;
6239
6240         /* GRC_MISC_CFG core clock reset will clear the memory
6241          * enable bit in PCI register 4 and the MSI enable bit
6242          * on some chips, so we save relevant registers here.
6243          */
6244         tg3_save_pci_state(tp);
6245
6246         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6247             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6248                 tw32(GRC_FASTBOOT_PC, 0);
6249
6250         /*
6251          * We must avoid the readl() that normally takes place.
6252          * It locks machines, causes machine checks, and other
6253          * fun things.  So, temporarily disable the 5701
6254          * hardware workaround, while we do the reset.
6255          */
6256         write_op = tp->write32;
6257         if (write_op == tg3_write_flush_reg32)
6258                 tp->write32 = tg3_write32;
6259
6260         /* Prevent the irq handler from reading or writing PCI registers
6261          * during chip reset when the memory enable bit in the PCI command
6262          * register may be cleared.  The chip does not generate interrupt
6263          * at this time, but the irq handler may still be called due to irq
6264          * sharing or irqpoll.
6265          */
6266         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6267         if (tp->hw_status) {
6268                 tp->hw_status->status = 0;
6269                 tp->hw_status->status_tag = 0;
6270         }
6271         tp->last_tag = 0;
6272         tp->last_irq_tag = 0;
6273         smp_mb();
6274         synchronize_irq(tp->pdev->irq);
6275
6276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6277                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6278                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6279         }
6280
6281         /* do the reset */
6282         val = GRC_MISC_CFG_CORECLK_RESET;
6283
6284         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6285                 if (tr32(0x7e2c) == 0x60) {
6286                         tw32(0x7e2c, 0x20);
6287                 }
6288                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6289                         tw32(GRC_MISC_CFG, (1 << 29));
6290                         val |= (1 << 29);
6291                 }
6292         }
6293
6294         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6295                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6296                 tw32(GRC_VCPU_EXT_CTRL,
6297                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6298         }
6299
6300         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6301                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6302         tw32(GRC_MISC_CFG, val);
6303
6304         /* restore 5701 hardware bug workaround write method */
6305         tp->write32 = write_op;
6306
6307         /* Unfortunately, we have to delay before the PCI read back.
6308          * Some 575X chips even will not respond to a PCI cfg access
6309          * when the reset command is given to the chip.
6310          *
6311          * How do these hardware designers expect things to work
6312          * properly if the PCI write is posted for a long period
6313          * of time?  It is always necessary to have some method by
6314          * which a register read back can occur to push the write
6315          * out which does the reset.
6316          *
6317          * For most tg3 variants the trick below was working.
6318          * Ho hum...
6319          */
6320         udelay(120);
6321
6322         /* Flush PCI posted writes.  The normal MMIO registers
6323          * are inaccessible at this time so this is the only
6324          * way to make this reliably (actually, this is no longer
6325          * the case, see above).  I tried to use indirect
6326          * register read/write but this upset some 5701 variants.
6327          */
6328         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6329
6330         udelay(120);
6331
6332         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6333                 u16 val16;
6334
6335                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6336                         int i;
6337                         u32 cfg_val;
6338
6339                         /* Wait for link training to complete.  */
6340                         for (i = 0; i < 5000; i++)
6341                                 udelay(100);
6342
6343                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6344                         pci_write_config_dword(tp->pdev, 0xc4,
6345                                                cfg_val | (1 << 15));
6346                 }
6347
6348                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6349                 pci_read_config_word(tp->pdev,
6350                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6351                                      &val16);
6352                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6353                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6354                 /*
6355                  * Older PCIe devices only support the 128 byte
6356                  * MPS setting.  Enforce the restriction.
6357                  */
6358                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6359                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6360                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6361                 pci_write_config_word(tp->pdev,
6362                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6363                                       val16);
6364
6365                 pcie_set_readrq(tp->pdev, 4096);
6366
6367                 /* Clear error status */
6368                 pci_write_config_word(tp->pdev,
6369                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6370                                       PCI_EXP_DEVSTA_CED |
6371                                       PCI_EXP_DEVSTA_NFED |
6372                                       PCI_EXP_DEVSTA_FED |
6373                                       PCI_EXP_DEVSTA_URD);
6374         }
6375
6376         tg3_restore_pci_state(tp);
6377
6378         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6379
6380         val = 0;
6381         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6382                 val = tr32(MEMARB_MODE);
6383         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6384
6385         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6386                 tg3_stop_fw(tp);
6387                 tw32(0x5000, 0x400);
6388         }
6389
6390         tw32(GRC_MODE, tp->grc_mode);
6391
6392         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6393                 val = tr32(0xc4);
6394
6395                 tw32(0xc4, val | (1 << 15));
6396         }
6397
6398         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6399             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6400                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6401                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6402                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6403                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6404         }
6405
6406         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6407                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6408                 tw32_f(MAC_MODE, tp->mac_mode);
6409         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6410                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6411                 tw32_f(MAC_MODE, tp->mac_mode);
6412         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6413                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6414                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6415                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6416                 tw32_f(MAC_MODE, tp->mac_mode);
6417         } else
6418                 tw32_f(MAC_MODE, 0);
6419         udelay(40);
6420
6421         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6422
6423         err = tg3_poll_fw(tp);
6424         if (err)
6425                 return err;
6426
6427         tg3_mdio_start(tp);
6428
6429         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6430             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6431                 val = tr32(0x7c00);
6432
6433                 tw32(0x7c00, val | (1 << 25));
6434         }
6435
6436         /* Reprobe ASF enable state.  */
6437         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6438         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6439         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6440         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6441                 u32 nic_cfg;
6442
6443                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6444                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6445                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6446                         tp->last_event_jiffies = jiffies;
6447                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6448                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6449                 }
6450         }
6451
6452         return 0;
6453 }
6454
6455 /* tp->lock is held. */
6456 static void tg3_stop_fw(struct tg3 *tp)
6457 {
6458         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6459            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6460                 /* Wait for RX cpu to ACK the previous event. */
6461                 tg3_wait_for_event_ack(tp);
6462
6463                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6464
6465                 tg3_generate_fw_event(tp);
6466
6467                 /* Wait for RX cpu to ACK this event. */
6468                 tg3_wait_for_event_ack(tp);
6469         }
6470 }
6471
6472 /* tp->lock is held. */
6473 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6474 {
6475         int err;
6476
6477         tg3_stop_fw(tp);
6478
6479         tg3_write_sig_pre_reset(tp, kind);
6480
6481         tg3_abort_hw(tp, silent);
6482         err = tg3_chip_reset(tp);
6483
6484         __tg3_set_mac_addr(tp, 0);
6485
6486         tg3_write_sig_legacy(tp, kind);
6487         tg3_write_sig_post_reset(tp, kind);
6488
6489         if (err)
6490                 return err;
6491
6492         return 0;
6493 }
6494
6495 #define RX_CPU_SCRATCH_BASE     0x30000
6496 #define RX_CPU_SCRATCH_SIZE     0x04000
6497 #define TX_CPU_SCRATCH_BASE     0x34000
6498 #define TX_CPU_SCRATCH_SIZE     0x04000
6499
6500 /* tp->lock is held. */
6501 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6502 {
6503         int i;
6504
6505         BUG_ON(offset == TX_CPU_BASE &&
6506             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6507
6508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6509                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6510
6511                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6512                 return 0;
6513         }
6514         if (offset == RX_CPU_BASE) {
6515                 for (i = 0; i < 10000; i++) {
6516                         tw32(offset + CPU_STATE, 0xffffffff);
6517                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6518                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6519                                 break;
6520                 }
6521
6522                 tw32(offset + CPU_STATE, 0xffffffff);
6523                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6524                 udelay(10);
6525         } else {
6526                 for (i = 0; i < 10000; i++) {
6527                         tw32(offset + CPU_STATE, 0xffffffff);
6528                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6529                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6530                                 break;
6531                 }
6532         }
6533
6534         if (i >= 10000) {
6535                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6536                        "and %s CPU\n",
6537                        tp->dev->name,
6538                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6539                 return -ENODEV;
6540         }
6541
6542         /* Clear firmware's nvram arbitration. */
6543         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6544                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6545         return 0;
6546 }
6547
6548 struct fw_info {
6549         unsigned int fw_base;
6550         unsigned int fw_len;
6551         const __be32 *fw_data;
6552 };
6553
6554 /* tp->lock is held. */
6555 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6556                                  int cpu_scratch_size, struct fw_info *info)
6557 {
6558         int err, lock_err, i;
6559         void (*write_op)(struct tg3 *, u32, u32);
6560
6561         if (cpu_base == TX_CPU_BASE &&
6562             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6563                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6564                        "TX cpu firmware on %s which is 5705.\n",
6565                        tp->dev->name);
6566                 return -EINVAL;
6567         }
6568
6569         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6570                 write_op = tg3_write_mem;
6571         else
6572                 write_op = tg3_write_indirect_reg32;
6573
6574         /* It is possible that bootcode is still loading at this point.
6575          * Get the nvram lock first before halting the cpu.
6576          */
6577         lock_err = tg3_nvram_lock(tp);
6578         err = tg3_halt_cpu(tp, cpu_base);
6579         if (!lock_err)
6580                 tg3_nvram_unlock(tp);
6581         if (err)
6582                 goto out;
6583
6584         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6585                 write_op(tp, cpu_scratch_base + i, 0);
6586         tw32(cpu_base + CPU_STATE, 0xffffffff);
6587         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6588         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6589                 write_op(tp, (cpu_scratch_base +
6590                               (info->fw_base & 0xffff) +
6591                               (i * sizeof(u32))),
6592                               be32_to_cpu(info->fw_data[i]));
6593
6594         err = 0;
6595
6596 out:
6597         return err;
6598 }
6599
6600 /* tp->lock is held. */
6601 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6602 {
6603         struct fw_info info;
6604         const __be32 *fw_data;
6605         int err, i;
6606
6607         fw_data = (void *)tp->fw->data;
6608
6609         /* Firmware blob starts with version numbers, followed by
6610            start address and length. We are setting complete length.
6611            length = end_address_of_bss - start_address_of_text.
6612            Remainder is the blob to be loaded contiguously
6613            from start address. */
6614
6615         info.fw_base = be32_to_cpu(fw_data[1]);
6616         info.fw_len = tp->fw->size - 12;
6617         info.fw_data = &fw_data[3];
6618
6619         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6620                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6621                                     &info);
6622         if (err)
6623                 return err;
6624
6625         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6626                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6627                                     &info);
6628         if (err)
6629                 return err;
6630
6631         /* Now startup only the RX cpu. */
6632         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6633         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6634
6635         for (i = 0; i < 5; i++) {
6636                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6637                         break;
6638                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6639                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6640                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6641                 udelay(1000);
6642         }
6643         if (i >= 5) {
6644                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6645                        "to set RX CPU PC, is %08x should be %08x\n",
6646                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6647                        info.fw_base);
6648                 return -ENODEV;
6649         }
6650         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6651         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6652
6653         return 0;
6654 }
6655
6656 /* 5705 needs a special version of the TSO firmware.  */
6657
6658 /* tp->lock is held. */
6659 static int tg3_load_tso_firmware(struct tg3 *tp)
6660 {
6661         struct fw_info info;
6662         const __be32 *fw_data;
6663         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6664         int err, i;
6665
6666         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6667                 return 0;
6668
6669         fw_data = (void *)tp->fw->data;
6670
6671         /* Firmware blob starts with version numbers, followed by
6672            start address and length. We are setting complete length.
6673            length = end_address_of_bss - start_address_of_text.
6674            Remainder is the blob to be loaded contiguously
6675            from start address. */
6676
6677         info.fw_base = be32_to_cpu(fw_data[1]);
6678         cpu_scratch_size = tp->fw_len;
6679         info.fw_len = tp->fw->size - 12;
6680         info.fw_data = &fw_data[3];
6681
6682         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6683                 cpu_base = RX_CPU_BASE;
6684                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6685         } else {
6686                 cpu_base = TX_CPU_BASE;
6687                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6688                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6689         }
6690
6691         err = tg3_load_firmware_cpu(tp, cpu_base,
6692                                     cpu_scratch_base, cpu_scratch_size,
6693                                     &info);
6694         if (err)
6695                 return err;
6696
6697         /* Now startup the cpu. */
6698         tw32(cpu_base + CPU_STATE, 0xffffffff);
6699         tw32_f(cpu_base + CPU_PC, info.fw_base);
6700
6701         for (i = 0; i < 5; i++) {
6702                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6703                         break;
6704                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6705                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6706                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6707                 udelay(1000);
6708         }
6709         if (i >= 5) {
6710                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6711                        "to set CPU PC, is %08x should be %08x\n",
6712                        tp->dev->name, tr32(cpu_base + CPU_PC),
6713                        info.fw_base);
6714                 return -ENODEV;
6715         }
6716         tw32(cpu_base + CPU_STATE, 0xffffffff);
6717         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6718         return 0;
6719 }
6720
6721
6722 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6723 {
6724         struct tg3 *tp = netdev_priv(dev);
6725         struct sockaddr *addr = p;
6726         int err = 0, skip_mac_1 = 0;
6727
6728         if (!is_valid_ether_addr(addr->sa_data))
6729                 return -EINVAL;
6730
6731         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6732
6733         if (!netif_running(dev))
6734                 return 0;
6735
6736         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6737                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6738
6739                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6740                 addr0_low = tr32(MAC_ADDR_0_LOW);
6741                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6742                 addr1_low = tr32(MAC_ADDR_1_LOW);
6743
6744                 /* Skip MAC addr 1 if ASF is using it. */
6745                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6746                     !(addr1_high == 0 && addr1_low == 0))
6747                         skip_mac_1 = 1;
6748         }
6749         spin_lock_bh(&tp->lock);
6750         __tg3_set_mac_addr(tp, skip_mac_1);
6751         spin_unlock_bh(&tp->lock);
6752
6753         return err;
6754 }
6755
6756 /* tp->lock is held. */
6757 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6758                            dma_addr_t mapping, u32 maxlen_flags,
6759                            u32 nic_addr)
6760 {
6761         tg3_write_mem(tp,
6762                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6763                       ((u64) mapping >> 32));
6764         tg3_write_mem(tp,
6765                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6766                       ((u64) mapping & 0xffffffff));
6767         tg3_write_mem(tp,
6768                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6769                        maxlen_flags);
6770
6771         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6772                 tg3_write_mem(tp,
6773                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6774                               nic_addr);
6775 }
6776
6777 static void __tg3_set_rx_mode(struct net_device *);
6778 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6779 {
6780         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6781         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6782         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6783         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6784         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6785                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6786                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6787         }
6788         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6789         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6790         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6791                 u32 val = ec->stats_block_coalesce_usecs;
6792
6793                 if (!netif_carrier_ok(tp->dev))
6794                         val = 0;
6795
6796                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6797         }
6798 }
6799
6800 /* tp->lock is held. */
6801 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6802 {
6803         u32 val, rdmac_mode;
6804         int i, err, limit;
6805         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
6806
6807         tg3_disable_ints(tp);
6808
6809         tg3_stop_fw(tp);
6810
6811         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6812
6813         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6814                 tg3_abort_hw(tp, 1);
6815         }
6816
6817         if (reset_phy &&
6818             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6819                 tg3_phy_reset(tp);
6820
6821         err = tg3_chip_reset(tp);
6822         if (err)
6823                 return err;
6824
6825         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6826
6827         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6828                 val = tr32(TG3_CPMU_CTRL);
6829                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6830                 tw32(TG3_CPMU_CTRL, val);
6831
6832                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6833                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6834                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6835                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6836
6837                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6838                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6839                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6840                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6841
6842                 val = tr32(TG3_CPMU_HST_ACC);
6843                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6844                 val |= CPMU_HST_ACC_MACCLK_6_25;
6845                 tw32(TG3_CPMU_HST_ACC, val);
6846         }
6847
6848         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6849                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6850                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6851                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6852                 tw32(PCIE_PWR_MGMT_THRESH, val);
6853
6854                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6855                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6856
6857                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6858         }
6859
6860         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6861                 val = tr32(TG3_PCIE_LNKCTL);
6862                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6863                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6864                 else
6865                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6866                 tw32(TG3_PCIE_LNKCTL, val);
6867         }
6868
6869         /* This works around an issue with Athlon chipsets on
6870          * B3 tigon3 silicon.  This bit has no effect on any
6871          * other revision.  But do not set this on PCI Express
6872          * chips and don't even touch the clocks if the CPMU is present.
6873          */
6874         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6875                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6876                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6877                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6878         }
6879
6880         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6881             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6882                 val = tr32(TG3PCI_PCISTATE);
6883                 val |= PCISTATE_RETRY_SAME_DMA;
6884                 tw32(TG3PCI_PCISTATE, val);
6885         }
6886
6887         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6888                 /* Allow reads and writes to the
6889                  * APE register and memory space.
6890                  */
6891                 val = tr32(TG3PCI_PCISTATE);
6892                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6893                        PCISTATE_ALLOW_APE_SHMEM_WR;
6894                 tw32(TG3PCI_PCISTATE, val);
6895         }
6896
6897         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6898                 /* Enable some hw fixes.  */
6899                 val = tr32(TG3PCI_MSI_DATA);
6900                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6901                 tw32(TG3PCI_MSI_DATA, val);
6902         }
6903
6904         /* Descriptor ring init may make accesses to the
6905          * NIC SRAM area to setup the TX descriptors, so we
6906          * can only do this after the hardware has been
6907          * successfully reset.
6908          */
6909         err = tg3_init_rings(tp);
6910         if (err)
6911                 return err;
6912
6913         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6914             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6915                 /* This value is determined during the probe time DMA
6916                  * engine test, tg3_test_dma.
6917                  */
6918                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6919         }
6920
6921         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6922                           GRC_MODE_4X_NIC_SEND_RINGS |
6923                           GRC_MODE_NO_TX_PHDR_CSUM |
6924                           GRC_MODE_NO_RX_PHDR_CSUM);
6925         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6926
6927         /* Pseudo-header checksum is done by hardware logic and not
6928          * the offload processers, so make the chip do the pseudo-
6929          * header checksums on receive.  For transmit it is more
6930          * convenient to do the pseudo-header checksum in software
6931          * as Linux does that on transmit for us in all cases.
6932          */
6933         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6934
6935         tw32(GRC_MODE,
6936              tp->grc_mode |
6937              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6938
6939         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6940         val = tr32(GRC_MISC_CFG);
6941         val &= ~0xff;
6942         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6943         tw32(GRC_MISC_CFG, val);
6944
6945         /* Initialize MBUF/DESC pool. */
6946         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6947                 /* Do nothing.  */
6948         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6949                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6950                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6951                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6952                 else
6953                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6954                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6955                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6956         }
6957         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6958                 int fw_len;
6959
6960                 fw_len = tp->fw_len;
6961                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6962                 tw32(BUFMGR_MB_POOL_ADDR,
6963                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6964                 tw32(BUFMGR_MB_POOL_SIZE,
6965                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6966         }
6967
6968         if (tp->dev->mtu <= ETH_DATA_LEN) {
6969                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6970                      tp->bufmgr_config.mbuf_read_dma_low_water);
6971                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6972                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6973                 tw32(BUFMGR_MB_HIGH_WATER,
6974                      tp->bufmgr_config.mbuf_high_water);
6975         } else {
6976                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6977                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6978                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6979                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6980                 tw32(BUFMGR_MB_HIGH_WATER,
6981                      tp->bufmgr_config.mbuf_high_water_jumbo);
6982         }
6983         tw32(BUFMGR_DMA_LOW_WATER,
6984              tp->bufmgr_config.dma_low_water);
6985         tw32(BUFMGR_DMA_HIGH_WATER,
6986              tp->bufmgr_config.dma_high_water);
6987
6988         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6989         for (i = 0; i < 2000; i++) {
6990                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6991                         break;
6992                 udelay(10);
6993         }
6994         if (i >= 2000) {
6995                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6996                        tp->dev->name);
6997                 return -ENODEV;
6998         }
6999
7000         /* Setup replenish threshold. */
7001         val = tp->rx_pending / 8;
7002         if (val == 0)
7003                 val = 1;
7004         else if (val > tp->rx_std_max_post)
7005                 val = tp->rx_std_max_post;
7006         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7007                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7008                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7009
7010                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7011                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7012         }
7013
7014         tw32(RCVBDI_STD_THRESH, val);
7015
7016         /* Initialize TG3_BDINFO's at:
7017          *  RCVDBDI_STD_BD:     standard eth size rx ring
7018          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7019          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7020          *
7021          * like so:
7022          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7023          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7024          *                              ring attribute flags
7025          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7026          *
7027          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7028          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7029          *
7030          * The size of each ring is fixed in the firmware, but the location is
7031          * configurable.
7032          */
7033         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7034              ((u64) tpr->rx_std_mapping >> 32));
7035         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7036              ((u64) tpr->rx_std_mapping & 0xffffffff));
7037         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7038              NIC_SRAM_RX_BUFFER_DESC);
7039
7040         /* Disable the mini ring */
7041         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7042                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7043                      BDINFO_FLAGS_DISABLED);
7044
7045         /* Program the jumbo buffer descriptor ring control
7046          * blocks on those devices that have them.
7047          */
7048         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7049             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7050                 /* Setup replenish threshold. */
7051                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7052
7053                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7054                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7055                              ((u64) tpr->rx_jmb_mapping >> 32));
7056                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7057                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7058                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7059                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7060                              BDINFO_FLAGS_USE_EXT_RECV);
7061                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7062                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7063                 } else {
7064                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7065                              BDINFO_FLAGS_DISABLED);
7066                 }
7067
7068                 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7069         } else
7070                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7071
7072         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7073
7074         /* There is only one send ring on 5705/5750, no need to explicitly
7075          * disable the others.
7076          */
7077         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7078                 /* Clear out send RCB ring in SRAM. */
7079                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7080                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7081                                       BDINFO_FLAGS_DISABLED);
7082         }
7083
7084         tp->tx_prod = 0;
7085         tp->tx_cons = 0;
7086         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7087         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7088
7089         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7090                        tp->tx_desc_mapping,
7091                        (TG3_TX_RING_SIZE <<
7092                         BDINFO_FLAGS_MAXLEN_SHIFT),
7093                        NIC_SRAM_TX_BUFFER_DESC);
7094
7095         /* There is only one receive return ring on 5705/5750, no need
7096          * to explicitly disable the others.
7097          */
7098         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7099                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7100                      i += TG3_BDINFO_SIZE) {
7101                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7102                                       BDINFO_FLAGS_DISABLED);
7103                 }
7104         }
7105
7106         tp->rx_rcb_ptr = 0;
7107         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7108
7109         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7110                        tp->rx_rcb_mapping,
7111                        (TG3_RX_RCB_RING_SIZE(tp) <<
7112                         BDINFO_FLAGS_MAXLEN_SHIFT),
7113                        0);
7114
7115         tpr->rx_std_ptr = tp->rx_pending;
7116         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7117                      tpr->rx_std_ptr);
7118
7119         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7120                           tp->rx_jumbo_pending : 0;
7121         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7122                      tpr->rx_jmb_ptr);
7123
7124         /* Initialize MAC address and backoff seed. */
7125         __tg3_set_mac_addr(tp, 0);
7126
7127         /* MTU + ethernet header + FCS + optional VLAN tag */
7128         tw32(MAC_RX_MTU_SIZE,
7129              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7130
7131         /* The slot time is changed by tg3_setup_phy if we
7132          * run at gigabit with half duplex.
7133          */
7134         tw32(MAC_TX_LENGTHS,
7135              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7136              (6 << TX_LENGTHS_IPG_SHIFT) |
7137              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7138
7139         /* Receive rules. */
7140         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7141         tw32(RCVLPC_CONFIG, 0x0181);
7142
7143         /* Calculate RDMAC_MODE setting early, we need it to determine
7144          * the RCVLPC_STATE_ENABLE mask.
7145          */
7146         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7147                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7148                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7149                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7150                       RDMAC_MODE_LNGREAD_ENAB);
7151
7152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7153             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7154             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7155                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7156                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7157                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7158
7159         /* If statement applies to 5705 and 5750 PCI devices only */
7160         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7161              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7162             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7163                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7164                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7165                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7166                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7167                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7168                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7169                 }
7170         }
7171
7172         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7173                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7174
7175         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7176                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7177
7178         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7179             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7180                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7181
7182         /* Receive/send statistics. */
7183         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7184                 val = tr32(RCVLPC_STATS_ENABLE);
7185                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7186                 tw32(RCVLPC_STATS_ENABLE, val);
7187         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7188                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7189                 val = tr32(RCVLPC_STATS_ENABLE);
7190                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7191                 tw32(RCVLPC_STATS_ENABLE, val);
7192         } else {
7193                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7194         }
7195         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7196         tw32(SNDDATAI_STATSENAB, 0xffffff);
7197         tw32(SNDDATAI_STATSCTRL,
7198              (SNDDATAI_SCTRL_ENABLE |
7199               SNDDATAI_SCTRL_FASTUPD));
7200
7201         /* Setup host coalescing engine. */
7202         tw32(HOSTCC_MODE, 0);
7203         for (i = 0; i < 2000; i++) {
7204                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7205                         break;
7206                 udelay(10);
7207         }
7208
7209         __tg3_set_coalesce(tp, &tp->coal);
7210
7211         /* set status block DMA address */
7212         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7213              ((u64) tp->status_mapping >> 32));
7214         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7215              ((u64) tp->status_mapping & 0xffffffff));
7216
7217         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7218                 /* Status/statistics block address.  See tg3_timer,
7219                  * the tg3_periodic_fetch_stats call there, and
7220                  * tg3_get_stats to see how this works for 5705/5750 chips.
7221                  */
7222                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7223                      ((u64) tp->stats_mapping >> 32));
7224                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7225                      ((u64) tp->stats_mapping & 0xffffffff));
7226                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7227                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7228         }
7229
7230         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7231
7232         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7233         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7234         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7235                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7236
7237         /* Clear statistics/status block in chip, and status block in ram. */
7238         for (i = NIC_SRAM_STATS_BLK;
7239              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7240              i += sizeof(u32)) {
7241                 tg3_write_mem(tp, i, 0);
7242                 udelay(40);
7243         }
7244         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7245
7246         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7247                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7248                 /* reset to prevent losing 1st rx packet intermittently */
7249                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7250                 udelay(10);
7251         }
7252
7253         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7254                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7255         else
7256                 tp->mac_mode = 0;
7257         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7258                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7259         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7260             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7261             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7262                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7263         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7264         udelay(40);
7265
7266         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7267          * If TG3_FLG2_IS_NIC is zero, we should read the
7268          * register to preserve the GPIO settings for LOMs. The GPIOs,
7269          * whether used as inputs or outputs, are set by boot code after
7270          * reset.
7271          */
7272         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7273                 u32 gpio_mask;
7274
7275                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7276                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7277                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7278
7279                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7280                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7281                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7282
7283                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7284                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7285
7286                 tp->grc_local_ctrl &= ~gpio_mask;
7287                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7288
7289                 /* GPIO1 must be driven high for eeprom write protect */
7290                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7291                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7292                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7293         }
7294         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7295         udelay(100);
7296
7297         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7298
7299         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7300                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7301                 udelay(40);
7302         }
7303
7304         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7305                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7306                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7307                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7308                WDMAC_MODE_LNGREAD_ENAB);
7309
7310         /* If statement applies to 5705 and 5750 PCI devices only */
7311         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7312              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7313             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7314                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7315                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7316                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7317                         /* nothing */
7318                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7319                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7320                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7321                         val |= WDMAC_MODE_RX_ACCEL;
7322                 }
7323         }
7324
7325         /* Enable host coalescing bug fix */
7326         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7327                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7328
7329         tw32_f(WDMAC_MODE, val);
7330         udelay(40);
7331
7332         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7333                 u16 pcix_cmd;
7334
7335                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7336                                      &pcix_cmd);
7337                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7338                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7339                         pcix_cmd |= PCI_X_CMD_READ_2K;
7340                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7341                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7342                         pcix_cmd |= PCI_X_CMD_READ_2K;
7343                 }
7344                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7345                                       pcix_cmd);
7346         }
7347
7348         tw32_f(RDMAC_MODE, rdmac_mode);
7349         udelay(40);
7350
7351         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7352         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7353                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7354
7355         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7356                 tw32(SNDDATAC_MODE,
7357                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7358         else
7359                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7360
7361         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7362         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7363         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7364         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7365         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7366                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7367         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7368         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7369
7370         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7371                 err = tg3_load_5701_a0_firmware_fix(tp);
7372                 if (err)
7373                         return err;
7374         }
7375
7376         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7377                 err = tg3_load_tso_firmware(tp);
7378                 if (err)
7379                         return err;
7380         }
7381
7382         tp->tx_mode = TX_MODE_ENABLE;
7383         tw32_f(MAC_TX_MODE, tp->tx_mode);
7384         udelay(100);
7385
7386         tp->rx_mode = RX_MODE_ENABLE;
7387         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7388                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7389
7390         tw32_f(MAC_RX_MODE, tp->rx_mode);
7391         udelay(10);
7392
7393         tw32(MAC_LED_CTRL, tp->led_ctrl);
7394
7395         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7396         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7397                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7398                 udelay(10);
7399         }
7400         tw32_f(MAC_RX_MODE, tp->rx_mode);
7401         udelay(10);
7402
7403         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7404                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7405                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7406                         /* Set drive transmission level to 1.2V  */
7407                         /* only if the signal pre-emphasis bit is not set  */
7408                         val = tr32(MAC_SERDES_CFG);
7409                         val &= 0xfffff000;
7410                         val |= 0x880;
7411                         tw32(MAC_SERDES_CFG, val);
7412                 }
7413                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7414                         tw32(MAC_SERDES_CFG, 0x616000);
7415         }
7416
7417         /* Prevent chip from dropping frames when flow control
7418          * is enabled.
7419          */
7420         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7421
7422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7423             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7424                 /* Use hardware link auto-negotiation */
7425                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7426         }
7427
7428         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7429             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7430                 u32 tmp;
7431
7432                 tmp = tr32(SERDES_RX_CTRL);
7433                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7434                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7435                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7436                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7437         }
7438
7439         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7440                 if (tp->link_config.phy_is_low_power) {
7441                         tp->link_config.phy_is_low_power = 0;
7442                         tp->link_config.speed = tp->link_config.orig_speed;
7443                         tp->link_config.duplex = tp->link_config.orig_duplex;
7444                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7445                 }
7446
7447                 err = tg3_setup_phy(tp, 0);
7448                 if (err)
7449                         return err;
7450
7451                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7452                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7453                         u32 tmp;
7454
7455                         /* Clear CRC stats. */
7456                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7457                                 tg3_writephy(tp, MII_TG3_TEST1,
7458                                              tmp | MII_TG3_TEST1_CRC_EN);
7459                                 tg3_readphy(tp, 0x14, &tmp);
7460                         }
7461                 }
7462         }
7463
7464         __tg3_set_rx_mode(tp->dev);
7465
7466         /* Initialize receive rules. */
7467         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7468         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7469         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7470         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7471
7472         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7473             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7474                 limit = 8;
7475         else
7476                 limit = 16;
7477         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7478                 limit -= 4;
7479         switch (limit) {
7480         case 16:
7481                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7482         case 15:
7483                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7484         case 14:
7485                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7486         case 13:
7487                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7488         case 12:
7489                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7490         case 11:
7491                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7492         case 10:
7493                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7494         case 9:
7495                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7496         case 8:
7497                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7498         case 7:
7499                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7500         case 6:
7501                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7502         case 5:
7503                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7504         case 4:
7505                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7506         case 3:
7507                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7508         case 2:
7509         case 1:
7510
7511         default:
7512                 break;
7513         }
7514
7515         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7516                 /* Write our heartbeat update interval to APE. */
7517                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7518                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7519
7520         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7521
7522         return 0;
7523 }
7524
7525 /* Called at device open time to get the chip ready for
7526  * packet processing.  Invoked with tp->lock held.
7527  */
7528 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7529 {
7530         tg3_switch_clocks(tp);
7531
7532         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7533
7534         return tg3_reset_hw(tp, reset_phy);
7535 }
7536
7537 #define TG3_STAT_ADD32(PSTAT, REG) \
7538 do {    u32 __val = tr32(REG); \
7539         (PSTAT)->low += __val; \
7540         if ((PSTAT)->low < __val) \
7541                 (PSTAT)->high += 1; \
7542 } while (0)
7543
7544 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7545 {
7546         struct tg3_hw_stats *sp = tp->hw_stats;
7547
7548         if (!netif_carrier_ok(tp->dev))
7549                 return;
7550
7551         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7552         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7553         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7554         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7555         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7556         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7557         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7558         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7559         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7560         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7561         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7562         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7563         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7564
7565         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7566         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7567         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7568         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7569         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7570         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7571         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7572         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7573         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7574         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7575         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7576         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7577         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7578         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7579
7580         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7581         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7582         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7583 }
7584
7585 static void tg3_timer(unsigned long __opaque)
7586 {
7587         struct tg3 *tp = (struct tg3 *) __opaque;
7588
7589         if (tp->irq_sync)
7590                 goto restart_timer;
7591
7592         spin_lock(&tp->lock);
7593
7594         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7595                 /* All of this garbage is because when using non-tagged
7596                  * IRQ status the mailbox/status_block protocol the chip
7597                  * uses with the cpu is race prone.
7598                  */
7599                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7600                         tw32(GRC_LOCAL_CTRL,
7601                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7602                 } else {
7603                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7604                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7605                 }
7606
7607                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7608                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7609                         spin_unlock(&tp->lock);
7610                         schedule_work(&tp->reset_task);
7611                         return;
7612                 }
7613         }
7614
7615         /* This part only runs once per second. */
7616         if (!--tp->timer_counter) {
7617                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7618                         tg3_periodic_fetch_stats(tp);
7619
7620                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7621                         u32 mac_stat;
7622                         int phy_event;
7623
7624                         mac_stat = tr32(MAC_STATUS);
7625
7626                         phy_event = 0;
7627                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7628                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7629                                         phy_event = 1;
7630                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7631                                 phy_event = 1;
7632
7633                         if (phy_event)
7634                                 tg3_setup_phy(tp, 0);
7635                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7636                         u32 mac_stat = tr32(MAC_STATUS);
7637                         int need_setup = 0;
7638
7639                         if (netif_carrier_ok(tp->dev) &&
7640                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7641                                 need_setup = 1;
7642                         }
7643                         if (! netif_carrier_ok(tp->dev) &&
7644                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7645                                          MAC_STATUS_SIGNAL_DET))) {
7646                                 need_setup = 1;
7647                         }
7648                         if (need_setup) {
7649                                 if (!tp->serdes_counter) {
7650                                         tw32_f(MAC_MODE,
7651                                              (tp->mac_mode &
7652                                               ~MAC_MODE_PORT_MODE_MASK));
7653                                         udelay(40);
7654                                         tw32_f(MAC_MODE, tp->mac_mode);
7655                                         udelay(40);
7656                                 }
7657                                 tg3_setup_phy(tp, 0);
7658                         }
7659                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7660                         tg3_serdes_parallel_detect(tp);
7661
7662                 tp->timer_counter = tp->timer_multiplier;
7663         }
7664
7665         /* Heartbeat is only sent once every 2 seconds.
7666          *
7667          * The heartbeat is to tell the ASF firmware that the host
7668          * driver is still alive.  In the event that the OS crashes,
7669          * ASF needs to reset the hardware to free up the FIFO space
7670          * that may be filled with rx packets destined for the host.
7671          * If the FIFO is full, ASF will no longer function properly.
7672          *
7673          * Unintended resets have been reported on real time kernels
7674          * where the timer doesn't run on time.  Netpoll will also have
7675          * same problem.
7676          *
7677          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7678          * to check the ring condition when the heartbeat is expiring
7679          * before doing the reset.  This will prevent most unintended
7680          * resets.
7681          */
7682         if (!--tp->asf_counter) {
7683                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7684                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7685                         tg3_wait_for_event_ack(tp);
7686
7687                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7688                                       FWCMD_NICDRV_ALIVE3);
7689                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7690                         /* 5 seconds timeout */
7691                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7692
7693                         tg3_generate_fw_event(tp);
7694                 }
7695                 tp->asf_counter = tp->asf_multiplier;
7696         }
7697
7698         spin_unlock(&tp->lock);
7699
7700 restart_timer:
7701         tp->timer.expires = jiffies + tp->timer_offset;
7702         add_timer(&tp->timer);
7703 }
7704
7705 static int tg3_request_irq(struct tg3 *tp)
7706 {
7707         irq_handler_t fn;
7708         unsigned long flags;
7709         char *name = tp->dev->name;
7710
7711         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7712                 fn = tg3_msi;
7713                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7714                         fn = tg3_msi_1shot;
7715                 flags = IRQF_SAMPLE_RANDOM;
7716         } else {
7717                 fn = tg3_interrupt;
7718                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7719                         fn = tg3_interrupt_tagged;
7720                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7721         }
7722         return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]);
7723 }
7724
7725 static int tg3_test_interrupt(struct tg3 *tp)
7726 {
7727         struct tg3_napi *tnapi = &tp->napi[0];
7728         struct net_device *dev = tp->dev;
7729         int err, i, intr_ok = 0;
7730
7731         if (!netif_running(dev))
7732                 return -ENODEV;
7733
7734         tg3_disable_ints(tp);
7735
7736         free_irq(tp->pdev->irq, tnapi);
7737
7738         err = request_irq(tp->pdev->irq, tg3_test_isr,
7739                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7740         if (err)
7741                 return err;
7742
7743         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7744         tg3_enable_ints(tp);
7745
7746         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7747                HOSTCC_MODE_NOW);
7748
7749         for (i = 0; i < 5; i++) {
7750                 u32 int_mbox, misc_host_ctrl;
7751
7752                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7753                                         TG3_64BIT_REG_LOW);
7754                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7755
7756                 if ((int_mbox != 0) ||
7757                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7758                         intr_ok = 1;
7759                         break;
7760                 }
7761
7762                 msleep(10);
7763         }
7764
7765         tg3_disable_ints(tp);
7766
7767         free_irq(tp->pdev->irq, tnapi);
7768
7769         err = tg3_request_irq(tp);
7770
7771         if (err)
7772                 return err;
7773
7774         if (intr_ok)
7775                 return 0;
7776
7777         return -EIO;
7778 }
7779
7780 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7781  * successfully restored
7782  */
7783 static int tg3_test_msi(struct tg3 *tp)
7784 {
7785         int err;
7786         u16 pci_cmd;
7787
7788         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7789                 return 0;
7790
7791         /* Turn off SERR reporting in case MSI terminates with Master
7792          * Abort.
7793          */
7794         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7795         pci_write_config_word(tp->pdev, PCI_COMMAND,
7796                               pci_cmd & ~PCI_COMMAND_SERR);
7797
7798         err = tg3_test_interrupt(tp);
7799
7800         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7801
7802         if (!err)
7803                 return 0;
7804
7805         /* other failures */
7806         if (err != -EIO)
7807                 return err;
7808
7809         /* MSI test failed, go back to INTx mode */
7810         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7811                "switching to INTx mode. Please report this failure to "
7812                "the PCI maintainer and include system chipset information.\n",
7813                        tp->dev->name);
7814
7815         free_irq(tp->pdev->irq, &tp->napi[0]);
7816
7817         pci_disable_msi(tp->pdev);
7818
7819         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7820
7821         err = tg3_request_irq(tp);
7822         if (err)
7823                 return err;
7824
7825         /* Need to reset the chip because the MSI cycle may have terminated
7826          * with Master Abort.
7827          */
7828         tg3_full_lock(tp, 1);
7829
7830         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7831         err = tg3_init_hw(tp, 1);
7832
7833         tg3_full_unlock(tp);
7834
7835         if (err)
7836                 free_irq(tp->pdev->irq, &tp->napi[0]);
7837
7838         return err;
7839 }
7840
7841 static int tg3_request_firmware(struct tg3 *tp)
7842 {
7843         const __be32 *fw_data;
7844
7845         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7846                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7847                        tp->dev->name, tp->fw_needed);
7848                 return -ENOENT;
7849         }
7850
7851         fw_data = (void *)tp->fw->data;
7852
7853         /* Firmware blob starts with version numbers, followed by
7854          * start address and _full_ length including BSS sections
7855          * (which must be longer than the actual data, of course
7856          */
7857
7858         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7859         if (tp->fw_len < (tp->fw->size - 12)) {
7860                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7861                        tp->dev->name, tp->fw_len, tp->fw_needed);
7862                 release_firmware(tp->fw);
7863                 tp->fw = NULL;
7864                 return -EINVAL;
7865         }
7866
7867         /* We no longer need firmware; we have it. */
7868         tp->fw_needed = NULL;
7869         return 0;
7870 }
7871
7872 static void tg3_ints_init(struct tg3 *tp)
7873 {
7874         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7875                 /* All MSI supporting chips should support tagged
7876                  * status.  Assert that this is the case.
7877                  */
7878                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7879                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7880                                "Not using MSI.\n", tp->dev->name);
7881                 } else if (pci_enable_msi(tp->pdev) == 0) {
7882                         u32 msi_mode;
7883
7884                         msi_mode = tr32(MSGINT_MODE);
7885                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7886                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7887                 }
7888         }
7889 }
7890
7891 static void tg3_ints_fini(struct tg3 *tp)
7892 {
7893                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7894                         pci_disable_msi(tp->pdev);
7895                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7896                 }
7897 }
7898
7899 static int tg3_open(struct net_device *dev)
7900 {
7901         struct tg3 *tp = netdev_priv(dev);
7902         int err;
7903
7904         if (tp->fw_needed) {
7905                 err = tg3_request_firmware(tp);
7906                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7907                         if (err)
7908                                 return err;
7909                 } else if (err) {
7910                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7911                                tp->dev->name);
7912                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7913                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7914                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7915                                tp->dev->name);
7916                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7917                 }
7918         }
7919
7920         netif_carrier_off(tp->dev);
7921
7922         err = tg3_set_power_state(tp, PCI_D0);
7923         if (err)
7924                 return err;
7925
7926         tg3_full_lock(tp, 0);
7927
7928         tg3_disable_ints(tp);
7929         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7930
7931         tg3_full_unlock(tp);
7932
7933         /* The placement of this call is tied
7934          * to the setup and use of Host TX descriptors.
7935          */
7936         err = tg3_alloc_consistent(tp);
7937         if (err)
7938                 return err;
7939
7940         tg3_ints_init(tp);
7941
7942         napi_enable(&tp->napi[0].napi);
7943
7944         err = tg3_request_irq(tp);
7945
7946         if (err)
7947                 goto err_out1;
7948
7949         tg3_full_lock(tp, 0);
7950
7951         err = tg3_init_hw(tp, 1);
7952         if (err) {
7953                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7954                 tg3_free_rings(tp);
7955         } else {
7956                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7957                         tp->timer_offset = HZ;
7958                 else
7959                         tp->timer_offset = HZ / 10;
7960
7961                 BUG_ON(tp->timer_offset > HZ);
7962                 tp->timer_counter = tp->timer_multiplier =
7963                         (HZ / tp->timer_offset);
7964                 tp->asf_counter = tp->asf_multiplier =
7965                         ((HZ / tp->timer_offset) * 2);
7966
7967                 init_timer(&tp->timer);
7968                 tp->timer.expires = jiffies + tp->timer_offset;
7969                 tp->timer.data = (unsigned long) tp;
7970                 tp->timer.function = tg3_timer;
7971         }
7972
7973         tg3_full_unlock(tp);
7974
7975         if (err)
7976                 goto err_out2;
7977
7978         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7979                 err = tg3_test_msi(tp);
7980
7981                 if (err) {
7982                         tg3_full_lock(tp, 0);
7983                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7984                         tg3_free_rings(tp);
7985                         tg3_full_unlock(tp);
7986
7987                         goto err_out1;
7988                 }
7989
7990                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7991                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7992                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7993
7994                                 tw32(PCIE_TRANSACTION_CFG,
7995                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7996                         }
7997                 }
7998         }
7999
8000         tg3_phy_start(tp);
8001
8002         tg3_full_lock(tp, 0);
8003
8004         add_timer(&tp->timer);
8005         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8006         tg3_enable_ints(tp);
8007
8008         tg3_full_unlock(tp);
8009
8010         netif_start_queue(dev);
8011
8012         return 0;
8013
8014 err_out2:
8015         free_irq(tp->pdev->irq, &tp->napi[0]);
8016
8017 err_out1:
8018         napi_disable(&tp->napi[0].napi);
8019         tg3_ints_fini(tp);
8020         tg3_free_consistent(tp);
8021         return err;
8022 }
8023
8024 #if 0
8025 /*static*/ void tg3_dump_state(struct tg3 *tp)
8026 {
8027         u32 val32, val32_2, val32_3, val32_4, val32_5;
8028         u16 val16;
8029         int i;
8030
8031         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8032         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8033         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8034                val16, val32);
8035
8036         /* MAC block */
8037         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8038                tr32(MAC_MODE), tr32(MAC_STATUS));
8039         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8040                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8041         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8042                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8043         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8044                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8045
8046         /* Send data initiator control block */
8047         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8048                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8049         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8050                tr32(SNDDATAI_STATSCTRL));
8051
8052         /* Send data completion control block */
8053         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8054
8055         /* Send BD ring selector block */
8056         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8057                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8058
8059         /* Send BD initiator control block */
8060         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8061                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8062
8063         /* Send BD completion control block */
8064         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8065
8066         /* Receive list placement control block */
8067         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8068                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8069         printk("       RCVLPC_STATSCTRL[%08x]\n",
8070                tr32(RCVLPC_STATSCTRL));
8071
8072         /* Receive data and receive BD initiator control block */
8073         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8074                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8075
8076         /* Receive data completion control block */
8077         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8078                tr32(RCVDCC_MODE));
8079
8080         /* Receive BD initiator control block */
8081         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8082                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8083
8084         /* Receive BD completion control block */
8085         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8086                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8087
8088         /* Receive list selector control block */
8089         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8090                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8091
8092         /* Mbuf cluster free block */
8093         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8094                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8095
8096         /* Host coalescing control block */
8097         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8098                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8099         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8100                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8101                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8102         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8103                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8104                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8105         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8106                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8107         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8108                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8109
8110         /* Memory arbiter control block */
8111         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8112                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8113
8114         /* Buffer manager control block */
8115         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8116                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8117         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8118                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8119         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8120                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8121                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8122                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8123
8124         /* Read DMA control block */
8125         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8126                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8127
8128         /* Write DMA control block */
8129         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8130                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8131
8132         /* DMA completion block */
8133         printk("DEBUG: DMAC_MODE[%08x]\n",
8134                tr32(DMAC_MODE));
8135
8136         /* GRC block */
8137         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8138                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8139         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8140                tr32(GRC_LOCAL_CTRL));
8141
8142         /* TG3_BDINFOs */
8143         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8144                tr32(RCVDBDI_JUMBO_BD + 0x0),
8145                tr32(RCVDBDI_JUMBO_BD + 0x4),
8146                tr32(RCVDBDI_JUMBO_BD + 0x8),
8147                tr32(RCVDBDI_JUMBO_BD + 0xc));
8148         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8149                tr32(RCVDBDI_STD_BD + 0x0),
8150                tr32(RCVDBDI_STD_BD + 0x4),
8151                tr32(RCVDBDI_STD_BD + 0x8),
8152                tr32(RCVDBDI_STD_BD + 0xc));
8153         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8154                tr32(RCVDBDI_MINI_BD + 0x0),
8155                tr32(RCVDBDI_MINI_BD + 0x4),
8156                tr32(RCVDBDI_MINI_BD + 0x8),
8157                tr32(RCVDBDI_MINI_BD + 0xc));
8158
8159         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8160         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8161         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8162         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8163         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8164                val32, val32_2, val32_3, val32_4);
8165
8166         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8167         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8168         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8169         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8170         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8171                val32, val32_2, val32_3, val32_4);
8172
8173         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8174         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8175         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8176         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8177         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8178         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8179                val32, val32_2, val32_3, val32_4, val32_5);
8180
8181         /* SW status block */
8182         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8183                tp->hw_status->status,
8184                tp->hw_status->status_tag,
8185                tp->hw_status->rx_jumbo_consumer,
8186                tp->hw_status->rx_consumer,
8187                tp->hw_status->rx_mini_consumer,
8188                tp->hw_status->idx[0].rx_producer,
8189                tp->hw_status->idx[0].tx_consumer);
8190
8191         /* SW statistics block */
8192         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8193                ((u32 *)tp->hw_stats)[0],
8194                ((u32 *)tp->hw_stats)[1],
8195                ((u32 *)tp->hw_stats)[2],
8196                ((u32 *)tp->hw_stats)[3]);
8197
8198         /* Mailboxes */
8199         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8200                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8201                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8202                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8203                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8204
8205         /* NIC side send descriptors. */
8206         for (i = 0; i < 6; i++) {
8207                 unsigned long txd;
8208
8209                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8210                         + (i * sizeof(struct tg3_tx_buffer_desc));
8211                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8212                        i,
8213                        readl(txd + 0x0), readl(txd + 0x4),
8214                        readl(txd + 0x8), readl(txd + 0xc));
8215         }
8216
8217         /* NIC side RX descriptors. */
8218         for (i = 0; i < 6; i++) {
8219                 unsigned long rxd;
8220
8221                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8222                         + (i * sizeof(struct tg3_rx_buffer_desc));
8223                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8224                        i,
8225                        readl(rxd + 0x0), readl(rxd + 0x4),
8226                        readl(rxd + 0x8), readl(rxd + 0xc));
8227                 rxd += (4 * sizeof(u32));
8228                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8229                        i,
8230                        readl(rxd + 0x0), readl(rxd + 0x4),
8231                        readl(rxd + 0x8), readl(rxd + 0xc));
8232         }
8233
8234         for (i = 0; i < 6; i++) {
8235                 unsigned long rxd;
8236
8237                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8238                         + (i * sizeof(struct tg3_rx_buffer_desc));
8239                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8240                        i,
8241                        readl(rxd + 0x0), readl(rxd + 0x4),
8242                        readl(rxd + 0x8), readl(rxd + 0xc));
8243                 rxd += (4 * sizeof(u32));
8244                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8245                        i,
8246                        readl(rxd + 0x0), readl(rxd + 0x4),
8247                        readl(rxd + 0x8), readl(rxd + 0xc));
8248         }
8249 }
8250 #endif
8251
8252 static struct net_device_stats *tg3_get_stats(struct net_device *);
8253 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8254
8255 static int tg3_close(struct net_device *dev)
8256 {
8257         struct tg3 *tp = netdev_priv(dev);
8258
8259         napi_disable(&tp->napi[0].napi);
8260         cancel_work_sync(&tp->reset_task);
8261
8262         netif_stop_queue(dev);
8263
8264         del_timer_sync(&tp->timer);
8265
8266         tg3_full_lock(tp, 1);
8267 #if 0
8268         tg3_dump_state(tp);
8269 #endif
8270
8271         tg3_disable_ints(tp);
8272
8273         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8274         tg3_free_rings(tp);
8275         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8276
8277         tg3_full_unlock(tp);
8278
8279         free_irq(tp->pdev->irq, &tp->napi[0]);
8280
8281         tg3_ints_fini(tp);
8282
8283         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8284                sizeof(tp->net_stats_prev));
8285         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8286                sizeof(tp->estats_prev));
8287
8288         tg3_free_consistent(tp);
8289
8290         tg3_set_power_state(tp, PCI_D3hot);
8291
8292         netif_carrier_off(tp->dev);
8293
8294         return 0;
8295 }
8296
8297 static inline unsigned long get_stat64(tg3_stat64_t *val)
8298 {
8299         unsigned long ret;
8300
8301 #if (BITS_PER_LONG == 32)
8302         ret = val->low;
8303 #else
8304         ret = ((u64)val->high << 32) | ((u64)val->low);
8305 #endif
8306         return ret;
8307 }
8308
8309 static inline u64 get_estat64(tg3_stat64_t *val)
8310 {
8311        return ((u64)val->high << 32) | ((u64)val->low);
8312 }
8313
8314 static unsigned long calc_crc_errors(struct tg3 *tp)
8315 {
8316         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8317
8318         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8319             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8320              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8321                 u32 val;
8322
8323                 spin_lock_bh(&tp->lock);
8324                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8325                         tg3_writephy(tp, MII_TG3_TEST1,
8326                                      val | MII_TG3_TEST1_CRC_EN);
8327                         tg3_readphy(tp, 0x14, &val);
8328                 } else
8329                         val = 0;
8330                 spin_unlock_bh(&tp->lock);
8331
8332                 tp->phy_crc_errors += val;
8333
8334                 return tp->phy_crc_errors;
8335         }
8336
8337         return get_stat64(&hw_stats->rx_fcs_errors);
8338 }
8339
8340 #define ESTAT_ADD(member) \
8341         estats->member =        old_estats->member + \
8342                                 get_estat64(&hw_stats->member)
8343
8344 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8345 {
8346         struct tg3_ethtool_stats *estats = &tp->estats;
8347         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8348         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8349
8350         if (!hw_stats)
8351                 return old_estats;
8352
8353         ESTAT_ADD(rx_octets);
8354         ESTAT_ADD(rx_fragments);
8355         ESTAT_ADD(rx_ucast_packets);
8356         ESTAT_ADD(rx_mcast_packets);
8357         ESTAT_ADD(rx_bcast_packets);
8358         ESTAT_ADD(rx_fcs_errors);
8359         ESTAT_ADD(rx_align_errors);
8360         ESTAT_ADD(rx_xon_pause_rcvd);
8361         ESTAT_ADD(rx_xoff_pause_rcvd);
8362         ESTAT_ADD(rx_mac_ctrl_rcvd);
8363         ESTAT_ADD(rx_xoff_entered);
8364         ESTAT_ADD(rx_frame_too_long_errors);
8365         ESTAT_ADD(rx_jabbers);
8366         ESTAT_ADD(rx_undersize_packets);
8367         ESTAT_ADD(rx_in_length_errors);
8368         ESTAT_ADD(rx_out_length_errors);
8369         ESTAT_ADD(rx_64_or_less_octet_packets);
8370         ESTAT_ADD(rx_65_to_127_octet_packets);
8371         ESTAT_ADD(rx_128_to_255_octet_packets);
8372         ESTAT_ADD(rx_256_to_511_octet_packets);
8373         ESTAT_ADD(rx_512_to_1023_octet_packets);
8374         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8375         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8376         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8377         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8378         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8379
8380         ESTAT_ADD(tx_octets);
8381         ESTAT_ADD(tx_collisions);
8382         ESTAT_ADD(tx_xon_sent);
8383         ESTAT_ADD(tx_xoff_sent);
8384         ESTAT_ADD(tx_flow_control);
8385         ESTAT_ADD(tx_mac_errors);
8386         ESTAT_ADD(tx_single_collisions);
8387         ESTAT_ADD(tx_mult_collisions);
8388         ESTAT_ADD(tx_deferred);
8389         ESTAT_ADD(tx_excessive_collisions);
8390         ESTAT_ADD(tx_late_collisions);
8391         ESTAT_ADD(tx_collide_2times);
8392         ESTAT_ADD(tx_collide_3times);
8393         ESTAT_ADD(tx_collide_4times);
8394         ESTAT_ADD(tx_collide_5times);
8395         ESTAT_ADD(tx_collide_6times);
8396         ESTAT_ADD(tx_collide_7times);
8397         ESTAT_ADD(tx_collide_8times);
8398         ESTAT_ADD(tx_collide_9times);
8399         ESTAT_ADD(tx_collide_10times);
8400         ESTAT_ADD(tx_collide_11times);
8401         ESTAT_ADD(tx_collide_12times);
8402         ESTAT_ADD(tx_collide_13times);
8403         ESTAT_ADD(tx_collide_14times);
8404         ESTAT_ADD(tx_collide_15times);
8405         ESTAT_ADD(tx_ucast_packets);
8406         ESTAT_ADD(tx_mcast_packets);
8407         ESTAT_ADD(tx_bcast_packets);
8408         ESTAT_ADD(tx_carrier_sense_errors);
8409         ESTAT_ADD(tx_discards);
8410         ESTAT_ADD(tx_errors);
8411
8412         ESTAT_ADD(dma_writeq_full);
8413         ESTAT_ADD(dma_write_prioq_full);
8414         ESTAT_ADD(rxbds_empty);
8415         ESTAT_ADD(rx_discards);
8416         ESTAT_ADD(rx_errors);
8417         ESTAT_ADD(rx_threshold_hit);
8418
8419         ESTAT_ADD(dma_readq_full);
8420         ESTAT_ADD(dma_read_prioq_full);
8421         ESTAT_ADD(tx_comp_queue_full);
8422
8423         ESTAT_ADD(ring_set_send_prod_index);
8424         ESTAT_ADD(ring_status_update);
8425         ESTAT_ADD(nic_irqs);
8426         ESTAT_ADD(nic_avoided_irqs);
8427         ESTAT_ADD(nic_tx_threshold_hit);
8428
8429         return estats;
8430 }
8431
8432 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8433 {
8434         struct tg3 *tp = netdev_priv(dev);
8435         struct net_device_stats *stats = &tp->net_stats;
8436         struct net_device_stats *old_stats = &tp->net_stats_prev;
8437         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8438
8439         if (!hw_stats)
8440                 return old_stats;
8441
8442         stats->rx_packets = old_stats->rx_packets +
8443                 get_stat64(&hw_stats->rx_ucast_packets) +
8444                 get_stat64(&hw_stats->rx_mcast_packets) +
8445                 get_stat64(&hw_stats->rx_bcast_packets);
8446
8447         stats->tx_packets = old_stats->tx_packets +
8448                 get_stat64(&hw_stats->tx_ucast_packets) +
8449                 get_stat64(&hw_stats->tx_mcast_packets) +
8450                 get_stat64(&hw_stats->tx_bcast_packets);
8451
8452         stats->rx_bytes = old_stats->rx_bytes +
8453                 get_stat64(&hw_stats->rx_octets);
8454         stats->tx_bytes = old_stats->tx_bytes +
8455                 get_stat64(&hw_stats->tx_octets);
8456
8457         stats->rx_errors = old_stats->rx_errors +
8458                 get_stat64(&hw_stats->rx_errors);
8459         stats->tx_errors = old_stats->tx_errors +
8460                 get_stat64(&hw_stats->tx_errors) +
8461                 get_stat64(&hw_stats->tx_mac_errors) +
8462                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8463                 get_stat64(&hw_stats->tx_discards);
8464
8465         stats->multicast = old_stats->multicast +
8466                 get_stat64(&hw_stats->rx_mcast_packets);
8467         stats->collisions = old_stats->collisions +
8468                 get_stat64(&hw_stats->tx_collisions);
8469
8470         stats->rx_length_errors = old_stats->rx_length_errors +
8471                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8472                 get_stat64(&hw_stats->rx_undersize_packets);
8473
8474         stats->rx_over_errors = old_stats->rx_over_errors +
8475                 get_stat64(&hw_stats->rxbds_empty);
8476         stats->rx_frame_errors = old_stats->rx_frame_errors +
8477                 get_stat64(&hw_stats->rx_align_errors);
8478         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8479                 get_stat64(&hw_stats->tx_discards);
8480         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8481                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8482
8483         stats->rx_crc_errors = old_stats->rx_crc_errors +
8484                 calc_crc_errors(tp);
8485
8486         stats->rx_missed_errors = old_stats->rx_missed_errors +
8487                 get_stat64(&hw_stats->rx_discards);
8488
8489         return stats;
8490 }
8491
8492 static inline u32 calc_crc(unsigned char *buf, int len)
8493 {
8494         u32 reg;
8495         u32 tmp;
8496         int j, k;
8497
8498         reg = 0xffffffff;
8499
8500         for (j = 0; j < len; j++) {
8501                 reg ^= buf[j];
8502
8503                 for (k = 0; k < 8; k++) {
8504                         tmp = reg & 0x01;
8505
8506                         reg >>= 1;
8507
8508                         if (tmp) {
8509                                 reg ^= 0xedb88320;
8510                         }
8511                 }
8512         }
8513
8514         return ~reg;
8515 }
8516
8517 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8518 {
8519         /* accept or reject all multicast frames */
8520         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8521         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8522         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8523         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8524 }
8525
8526 static void __tg3_set_rx_mode(struct net_device *dev)
8527 {
8528         struct tg3 *tp = netdev_priv(dev);
8529         u32 rx_mode;
8530
8531         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8532                                   RX_MODE_KEEP_VLAN_TAG);
8533
8534         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8535          * flag clear.
8536          */
8537 #if TG3_VLAN_TAG_USED
8538         if (!tp->vlgrp &&
8539             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8540                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8541 #else
8542         /* By definition, VLAN is disabled always in this
8543          * case.
8544          */
8545         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8546                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8547 #endif
8548
8549         if (dev->flags & IFF_PROMISC) {
8550                 /* Promiscuous mode. */
8551                 rx_mode |= RX_MODE_PROMISC;
8552         } else if (dev->flags & IFF_ALLMULTI) {
8553                 /* Accept all multicast. */
8554                 tg3_set_multi (tp, 1);
8555         } else if (dev->mc_count < 1) {
8556                 /* Reject all multicast. */
8557                 tg3_set_multi (tp, 0);
8558         } else {
8559                 /* Accept one or more multicast(s). */
8560                 struct dev_mc_list *mclist;
8561                 unsigned int i;
8562                 u32 mc_filter[4] = { 0, };
8563                 u32 regidx;
8564                 u32 bit;
8565                 u32 crc;
8566
8567                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8568                      i++, mclist = mclist->next) {
8569
8570                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8571                         bit = ~crc & 0x7f;
8572                         regidx = (bit & 0x60) >> 5;
8573                         bit &= 0x1f;
8574                         mc_filter[regidx] |= (1 << bit);
8575                 }
8576
8577                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8578                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8579                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8580                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8581         }
8582
8583         if (rx_mode != tp->rx_mode) {
8584                 tp->rx_mode = rx_mode;
8585                 tw32_f(MAC_RX_MODE, rx_mode);
8586                 udelay(10);
8587         }
8588 }
8589
8590 static void tg3_set_rx_mode(struct net_device *dev)
8591 {
8592         struct tg3 *tp = netdev_priv(dev);
8593
8594         if (!netif_running(dev))
8595                 return;
8596
8597         tg3_full_lock(tp, 0);
8598         __tg3_set_rx_mode(dev);
8599         tg3_full_unlock(tp);
8600 }
8601
8602 #define TG3_REGDUMP_LEN         (32 * 1024)
8603
8604 static int tg3_get_regs_len(struct net_device *dev)
8605 {
8606         return TG3_REGDUMP_LEN;
8607 }
8608
8609 static void tg3_get_regs(struct net_device *dev,
8610                 struct ethtool_regs *regs, void *_p)
8611 {
8612         u32 *p = _p;
8613         struct tg3 *tp = netdev_priv(dev);
8614         u8 *orig_p = _p;
8615         int i;
8616
8617         regs->version = 0;
8618
8619         memset(p, 0, TG3_REGDUMP_LEN);
8620
8621         if (tp->link_config.phy_is_low_power)
8622                 return;
8623
8624         tg3_full_lock(tp, 0);
8625
8626 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8627 #define GET_REG32_LOOP(base,len)                \
8628 do {    p = (u32 *)(orig_p + (base));           \
8629         for (i = 0; i < len; i += 4)            \
8630                 __GET_REG32((base) + i);        \
8631 } while (0)
8632 #define GET_REG32_1(reg)                        \
8633 do {    p = (u32 *)(orig_p + (reg));            \
8634         __GET_REG32((reg));                     \
8635 } while (0)
8636
8637         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8638         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8639         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8640         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8641         GET_REG32_1(SNDDATAC_MODE);
8642         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8643         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8644         GET_REG32_1(SNDBDC_MODE);
8645         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8646         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8647         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8648         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8649         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8650         GET_REG32_1(RCVDCC_MODE);
8651         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8652         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8653         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8654         GET_REG32_1(MBFREE_MODE);
8655         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8656         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8657         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8658         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8659         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8660         GET_REG32_1(RX_CPU_MODE);
8661         GET_REG32_1(RX_CPU_STATE);
8662         GET_REG32_1(RX_CPU_PGMCTR);
8663         GET_REG32_1(RX_CPU_HWBKPT);
8664         GET_REG32_1(TX_CPU_MODE);
8665         GET_REG32_1(TX_CPU_STATE);
8666         GET_REG32_1(TX_CPU_PGMCTR);
8667         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8668         GET_REG32_LOOP(FTQ_RESET, 0x120);
8669         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8670         GET_REG32_1(DMAC_MODE);
8671         GET_REG32_LOOP(GRC_MODE, 0x4c);
8672         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8673                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8674
8675 #undef __GET_REG32
8676 #undef GET_REG32_LOOP
8677 #undef GET_REG32_1
8678
8679         tg3_full_unlock(tp);
8680 }
8681
8682 static int tg3_get_eeprom_len(struct net_device *dev)
8683 {
8684         struct tg3 *tp = netdev_priv(dev);
8685
8686         return tp->nvram_size;
8687 }
8688
8689 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8690 {
8691         struct tg3 *tp = netdev_priv(dev);
8692         int ret;
8693         u8  *pd;
8694         u32 i, offset, len, b_offset, b_count;
8695         __be32 val;
8696
8697         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8698                 return -EINVAL;
8699
8700         if (tp->link_config.phy_is_low_power)
8701                 return -EAGAIN;
8702
8703         offset = eeprom->offset;
8704         len = eeprom->len;
8705         eeprom->len = 0;
8706
8707         eeprom->magic = TG3_EEPROM_MAGIC;
8708
8709         if (offset & 3) {
8710                 /* adjustments to start on required 4 byte boundary */
8711                 b_offset = offset & 3;
8712                 b_count = 4 - b_offset;
8713                 if (b_count > len) {
8714                         /* i.e. offset=1 len=2 */
8715                         b_count = len;
8716                 }
8717                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8718                 if (ret)
8719                         return ret;
8720                 memcpy(data, ((char*)&val) + b_offset, b_count);
8721                 len -= b_count;
8722                 offset += b_count;
8723                 eeprom->len += b_count;
8724         }
8725
8726         /* read bytes upto the last 4 byte boundary */
8727         pd = &data[eeprom->len];
8728         for (i = 0; i < (len - (len & 3)); i += 4) {
8729                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8730                 if (ret) {
8731                         eeprom->len += i;
8732                         return ret;
8733                 }
8734                 memcpy(pd + i, &val, 4);
8735         }
8736         eeprom->len += i;
8737
8738         if (len & 3) {
8739                 /* read last bytes not ending on 4 byte boundary */
8740                 pd = &data[eeprom->len];
8741                 b_count = len & 3;
8742                 b_offset = offset + len - b_count;
8743                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8744                 if (ret)
8745                         return ret;
8746                 memcpy(pd, &val, b_count);
8747                 eeprom->len += b_count;
8748         }
8749         return 0;
8750 }
8751
8752 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8753
8754 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8755 {
8756         struct tg3 *tp = netdev_priv(dev);
8757         int ret;
8758         u32 offset, len, b_offset, odd_len;
8759         u8 *buf;
8760         __be32 start, end;
8761
8762         if (tp->link_config.phy_is_low_power)
8763                 return -EAGAIN;
8764
8765         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8766             eeprom->magic != TG3_EEPROM_MAGIC)
8767                 return -EINVAL;
8768
8769         offset = eeprom->offset;
8770         len = eeprom->len;
8771
8772         if ((b_offset = (offset & 3))) {
8773                 /* adjustments to start on required 4 byte boundary */
8774                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8775                 if (ret)
8776                         return ret;
8777                 len += b_offset;
8778                 offset &= ~3;
8779                 if (len < 4)
8780                         len = 4;
8781         }
8782
8783         odd_len = 0;
8784         if (len & 3) {
8785                 /* adjustments to end on required 4 byte boundary */
8786                 odd_len = 1;
8787                 len = (len + 3) & ~3;
8788                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8789                 if (ret)
8790                         return ret;
8791         }
8792
8793         buf = data;
8794         if (b_offset || odd_len) {
8795                 buf = kmalloc(len, GFP_KERNEL);
8796                 if (!buf)
8797                         return -ENOMEM;
8798                 if (b_offset)
8799                         memcpy(buf, &start, 4);
8800                 if (odd_len)
8801                         memcpy(buf+len-4, &end, 4);
8802                 memcpy(buf + b_offset, data, eeprom->len);
8803         }
8804
8805         ret = tg3_nvram_write_block(tp, offset, len, buf);
8806
8807         if (buf != data)
8808                 kfree(buf);
8809
8810         return ret;
8811 }
8812
8813 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8814 {
8815         struct tg3 *tp = netdev_priv(dev);
8816
8817         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8818                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8819                         return -EAGAIN;
8820                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8821         }
8822
8823         cmd->supported = (SUPPORTED_Autoneg);
8824
8825         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8826                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8827                                    SUPPORTED_1000baseT_Full);
8828
8829         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8830                 cmd->supported |= (SUPPORTED_100baseT_Half |
8831                                   SUPPORTED_100baseT_Full |
8832                                   SUPPORTED_10baseT_Half |
8833                                   SUPPORTED_10baseT_Full |
8834                                   SUPPORTED_TP);
8835                 cmd->port = PORT_TP;
8836         } else {
8837                 cmd->supported |= SUPPORTED_FIBRE;
8838                 cmd->port = PORT_FIBRE;
8839         }
8840
8841         cmd->advertising = tp->link_config.advertising;
8842         if (netif_running(dev)) {
8843                 cmd->speed = tp->link_config.active_speed;
8844                 cmd->duplex = tp->link_config.active_duplex;
8845         }
8846         cmd->phy_address = PHY_ADDR;
8847         cmd->transceiver = XCVR_INTERNAL;
8848         cmd->autoneg = tp->link_config.autoneg;
8849         cmd->maxtxpkt = 0;
8850         cmd->maxrxpkt = 0;
8851         return 0;
8852 }
8853
8854 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8855 {
8856         struct tg3 *tp = netdev_priv(dev);
8857
8858         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8859                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8860                         return -EAGAIN;
8861                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8862         }
8863
8864         if (cmd->autoneg != AUTONEG_ENABLE &&
8865             cmd->autoneg != AUTONEG_DISABLE)
8866                 return -EINVAL;
8867
8868         if (cmd->autoneg == AUTONEG_DISABLE &&
8869             cmd->duplex != DUPLEX_FULL &&
8870             cmd->duplex != DUPLEX_HALF)
8871                 return -EINVAL;
8872
8873         if (cmd->autoneg == AUTONEG_ENABLE) {
8874                 u32 mask = ADVERTISED_Autoneg |
8875                            ADVERTISED_Pause |
8876                            ADVERTISED_Asym_Pause;
8877
8878                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8879                         mask |= ADVERTISED_1000baseT_Half |
8880                                 ADVERTISED_1000baseT_Full;
8881
8882                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8883                         mask |= ADVERTISED_100baseT_Half |
8884                                 ADVERTISED_100baseT_Full |
8885                                 ADVERTISED_10baseT_Half |
8886                                 ADVERTISED_10baseT_Full |
8887                                 ADVERTISED_TP;
8888                 else
8889                         mask |= ADVERTISED_FIBRE;
8890
8891                 if (cmd->advertising & ~mask)
8892                         return -EINVAL;
8893
8894                 mask &= (ADVERTISED_1000baseT_Half |
8895                          ADVERTISED_1000baseT_Full |
8896                          ADVERTISED_100baseT_Half |
8897                          ADVERTISED_100baseT_Full |
8898                          ADVERTISED_10baseT_Half |
8899                          ADVERTISED_10baseT_Full);
8900
8901                 cmd->advertising &= mask;
8902         } else {
8903                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8904                         if (cmd->speed != SPEED_1000)
8905                                 return -EINVAL;
8906
8907                         if (cmd->duplex != DUPLEX_FULL)
8908                                 return -EINVAL;
8909                 } else {
8910                         if (cmd->speed != SPEED_100 &&
8911                             cmd->speed != SPEED_10)
8912                                 return -EINVAL;
8913                 }
8914         }
8915
8916         tg3_full_lock(tp, 0);
8917
8918         tp->link_config.autoneg = cmd->autoneg;
8919         if (cmd->autoneg == AUTONEG_ENABLE) {
8920                 tp->link_config.advertising = (cmd->advertising |
8921                                               ADVERTISED_Autoneg);
8922                 tp->link_config.speed = SPEED_INVALID;
8923                 tp->link_config.duplex = DUPLEX_INVALID;
8924         } else {
8925                 tp->link_config.advertising = 0;
8926                 tp->link_config.speed = cmd->speed;
8927                 tp->link_config.duplex = cmd->duplex;
8928         }
8929
8930         tp->link_config.orig_speed = tp->link_config.speed;
8931         tp->link_config.orig_duplex = tp->link_config.duplex;
8932         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8933
8934         if (netif_running(dev))
8935                 tg3_setup_phy(tp, 1);
8936
8937         tg3_full_unlock(tp);
8938
8939         return 0;
8940 }
8941
8942 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8943 {
8944         struct tg3 *tp = netdev_priv(dev);
8945
8946         strcpy(info->driver, DRV_MODULE_NAME);
8947         strcpy(info->version, DRV_MODULE_VERSION);
8948         strcpy(info->fw_version, tp->fw_ver);
8949         strcpy(info->bus_info, pci_name(tp->pdev));
8950 }
8951
8952 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8953 {
8954         struct tg3 *tp = netdev_priv(dev);
8955
8956         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8957             device_can_wakeup(&tp->pdev->dev))
8958                 wol->supported = WAKE_MAGIC;
8959         else
8960                 wol->supported = 0;
8961         wol->wolopts = 0;
8962         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8963             device_can_wakeup(&tp->pdev->dev))
8964                 wol->wolopts = WAKE_MAGIC;
8965         memset(&wol->sopass, 0, sizeof(wol->sopass));
8966 }
8967
8968 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8969 {
8970         struct tg3 *tp = netdev_priv(dev);
8971         struct device *dp = &tp->pdev->dev;
8972
8973         if (wol->wolopts & ~WAKE_MAGIC)
8974                 return -EINVAL;
8975         if ((wol->wolopts & WAKE_MAGIC) &&
8976             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8977                 return -EINVAL;
8978
8979         spin_lock_bh(&tp->lock);
8980         if (wol->wolopts & WAKE_MAGIC) {
8981                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8982                 device_set_wakeup_enable(dp, true);
8983         } else {
8984                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8985                 device_set_wakeup_enable(dp, false);
8986         }
8987         spin_unlock_bh(&tp->lock);
8988
8989         return 0;
8990 }
8991
8992 static u32 tg3_get_msglevel(struct net_device *dev)
8993 {
8994         struct tg3 *tp = netdev_priv(dev);
8995         return tp->msg_enable;
8996 }
8997
8998 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8999 {
9000         struct tg3 *tp = netdev_priv(dev);
9001         tp->msg_enable = value;
9002 }
9003
9004 static int tg3_set_tso(struct net_device *dev, u32 value)
9005 {
9006         struct tg3 *tp = netdev_priv(dev);
9007
9008         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9009                 if (value)
9010                         return -EINVAL;
9011                 return 0;
9012         }
9013         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9014             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9015                 if (value) {
9016                         dev->features |= NETIF_F_TSO6;
9017                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9018                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9019                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9020                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9021                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9022                                 dev->features |= NETIF_F_TSO_ECN;
9023                 } else
9024                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9025         }
9026         return ethtool_op_set_tso(dev, value);
9027 }
9028
9029 static int tg3_nway_reset(struct net_device *dev)
9030 {
9031         struct tg3 *tp = netdev_priv(dev);
9032         int r;
9033
9034         if (!netif_running(dev))
9035                 return -EAGAIN;
9036
9037         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9038                 return -EINVAL;
9039
9040         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9041                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9042                         return -EAGAIN;
9043                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9044         } else {
9045                 u32 bmcr;
9046
9047                 spin_lock_bh(&tp->lock);
9048                 r = -EINVAL;
9049                 tg3_readphy(tp, MII_BMCR, &bmcr);
9050                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9051                     ((bmcr & BMCR_ANENABLE) ||
9052                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9053                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9054                                                    BMCR_ANENABLE);
9055                         r = 0;
9056                 }
9057                 spin_unlock_bh(&tp->lock);
9058         }
9059
9060         return r;
9061 }
9062
9063 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9064 {
9065         struct tg3 *tp = netdev_priv(dev);
9066
9067         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9068         ering->rx_mini_max_pending = 0;
9069         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9070                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9071         else
9072                 ering->rx_jumbo_max_pending = 0;
9073
9074         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9075
9076         ering->rx_pending = tp->rx_pending;
9077         ering->rx_mini_pending = 0;
9078         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9079                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9080         else
9081                 ering->rx_jumbo_pending = 0;
9082
9083         ering->tx_pending = tp->tx_pending;
9084 }
9085
9086 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9087 {
9088         struct tg3 *tp = netdev_priv(dev);
9089         int irq_sync = 0, err = 0;
9090
9091         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9092             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9093             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9094             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9095             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9096              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9097                 return -EINVAL;
9098
9099         if (netif_running(dev)) {
9100                 tg3_phy_stop(tp);
9101                 tg3_netif_stop(tp);
9102                 irq_sync = 1;
9103         }
9104
9105         tg3_full_lock(tp, irq_sync);
9106
9107         tp->rx_pending = ering->rx_pending;
9108
9109         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9110             tp->rx_pending > 63)
9111                 tp->rx_pending = 63;
9112         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9113         tp->tx_pending = ering->tx_pending;
9114
9115         if (netif_running(dev)) {
9116                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9117                 err = tg3_restart_hw(tp, 1);
9118                 if (!err)
9119                         tg3_netif_start(tp);
9120         }
9121
9122         tg3_full_unlock(tp);
9123
9124         if (irq_sync && !err)
9125                 tg3_phy_start(tp);
9126
9127         return err;
9128 }
9129
9130 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9131 {
9132         struct tg3 *tp = netdev_priv(dev);
9133
9134         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9135
9136         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9137                 epause->rx_pause = 1;
9138         else
9139                 epause->rx_pause = 0;
9140
9141         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9142                 epause->tx_pause = 1;
9143         else
9144                 epause->tx_pause = 0;
9145 }
9146
9147 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9148 {
9149         struct tg3 *tp = netdev_priv(dev);
9150         int err = 0;
9151
9152         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9153                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9154                         return -EAGAIN;
9155
9156                 if (epause->autoneg) {
9157                         u32 newadv;
9158                         struct phy_device *phydev;
9159
9160                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9161
9162                         if (epause->rx_pause) {
9163                                 if (epause->tx_pause)
9164                                         newadv = ADVERTISED_Pause;
9165                                 else
9166                                         newadv = ADVERTISED_Pause |
9167                                                  ADVERTISED_Asym_Pause;
9168                         } else if (epause->tx_pause) {
9169                                 newadv = ADVERTISED_Asym_Pause;
9170                         } else
9171                                 newadv = 0;
9172
9173                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9174                                 u32 oldadv = phydev->advertising &
9175                                              (ADVERTISED_Pause |
9176                                               ADVERTISED_Asym_Pause);
9177                                 if (oldadv != newadv) {
9178                                         phydev->advertising &=
9179                                                 ~(ADVERTISED_Pause |
9180                                                   ADVERTISED_Asym_Pause);
9181                                         phydev->advertising |= newadv;
9182                                         err = phy_start_aneg(phydev);
9183                                 }
9184                         } else {
9185                                 tp->link_config.advertising &=
9186                                                 ~(ADVERTISED_Pause |
9187                                                   ADVERTISED_Asym_Pause);
9188                                 tp->link_config.advertising |= newadv;
9189                         }
9190                 } else {
9191                         if (epause->rx_pause)
9192                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9193                         else
9194                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9195
9196                         if (epause->tx_pause)
9197                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9198                         else
9199                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9200
9201                         if (netif_running(dev))
9202                                 tg3_setup_flow_control(tp, 0, 0);
9203                 }
9204         } else {
9205                 int irq_sync = 0;
9206
9207                 if (netif_running(dev)) {
9208                         tg3_netif_stop(tp);
9209                         irq_sync = 1;
9210                 }
9211
9212                 tg3_full_lock(tp, irq_sync);
9213
9214                 if (epause->autoneg)
9215                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9216                 else
9217                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9218                 if (epause->rx_pause)
9219                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9220                 else
9221                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9222                 if (epause->tx_pause)
9223                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9224                 else
9225                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9226
9227                 if (netif_running(dev)) {
9228                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9229                         err = tg3_restart_hw(tp, 1);
9230                         if (!err)
9231                                 tg3_netif_start(tp);
9232                 }
9233
9234                 tg3_full_unlock(tp);
9235         }
9236
9237         return err;
9238 }
9239
9240 static u32 tg3_get_rx_csum(struct net_device *dev)
9241 {
9242         struct tg3 *tp = netdev_priv(dev);
9243         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9244 }
9245
9246 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9247 {
9248         struct tg3 *tp = netdev_priv(dev);
9249
9250         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9251                 if (data != 0)
9252                         return -EINVAL;
9253                 return 0;
9254         }
9255
9256         spin_lock_bh(&tp->lock);
9257         if (data)
9258                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9259         else
9260                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9261         spin_unlock_bh(&tp->lock);
9262
9263         return 0;
9264 }
9265
9266 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9267 {
9268         struct tg3 *tp = netdev_priv(dev);
9269
9270         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9271                 if (data != 0)
9272                         return -EINVAL;
9273                 return 0;
9274         }
9275
9276         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9277                 ethtool_op_set_tx_ipv6_csum(dev, data);
9278         else
9279                 ethtool_op_set_tx_csum(dev, data);
9280
9281         return 0;
9282 }
9283
9284 static int tg3_get_sset_count (struct net_device *dev, int sset)
9285 {
9286         switch (sset) {
9287         case ETH_SS_TEST:
9288                 return TG3_NUM_TEST;
9289         case ETH_SS_STATS:
9290                 return TG3_NUM_STATS;
9291         default:
9292                 return -EOPNOTSUPP;
9293         }
9294 }
9295
9296 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9297 {
9298         switch (stringset) {
9299         case ETH_SS_STATS:
9300                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9301                 break;
9302         case ETH_SS_TEST:
9303                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9304                 break;
9305         default:
9306                 WARN_ON(1);     /* we need a WARN() */
9307                 break;
9308         }
9309 }
9310
9311 static int tg3_phys_id(struct net_device *dev, u32 data)
9312 {
9313         struct tg3 *tp = netdev_priv(dev);
9314         int i;
9315
9316         if (!netif_running(tp->dev))
9317                 return -EAGAIN;
9318
9319         if (data == 0)
9320                 data = UINT_MAX / 2;
9321
9322         for (i = 0; i < (data * 2); i++) {
9323                 if ((i % 2) == 0)
9324                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9325                                            LED_CTRL_1000MBPS_ON |
9326                                            LED_CTRL_100MBPS_ON |
9327                                            LED_CTRL_10MBPS_ON |
9328                                            LED_CTRL_TRAFFIC_OVERRIDE |
9329                                            LED_CTRL_TRAFFIC_BLINK |
9330                                            LED_CTRL_TRAFFIC_LED);
9331
9332                 else
9333                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9334                                            LED_CTRL_TRAFFIC_OVERRIDE);
9335
9336                 if (msleep_interruptible(500))
9337                         break;
9338         }
9339         tw32(MAC_LED_CTRL, tp->led_ctrl);
9340         return 0;
9341 }
9342
9343 static void tg3_get_ethtool_stats (struct net_device *dev,
9344                                    struct ethtool_stats *estats, u64 *tmp_stats)
9345 {
9346         struct tg3 *tp = netdev_priv(dev);
9347         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9348 }
9349
9350 #define NVRAM_TEST_SIZE 0x100
9351 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9352 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9353 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9354 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9355 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9356
9357 static int tg3_test_nvram(struct tg3 *tp)
9358 {
9359         u32 csum, magic;
9360         __be32 *buf;
9361         int i, j, k, err = 0, size;
9362
9363         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9364                 return 0;
9365
9366         if (tg3_nvram_read(tp, 0, &magic) != 0)
9367                 return -EIO;
9368
9369         if (magic == TG3_EEPROM_MAGIC)
9370                 size = NVRAM_TEST_SIZE;
9371         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9372                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9373                     TG3_EEPROM_SB_FORMAT_1) {
9374                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9375                         case TG3_EEPROM_SB_REVISION_0:
9376                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9377                                 break;
9378                         case TG3_EEPROM_SB_REVISION_2:
9379                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9380                                 break;
9381                         case TG3_EEPROM_SB_REVISION_3:
9382                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9383                                 break;
9384                         default:
9385                                 return 0;
9386                         }
9387                 } else
9388                         return 0;
9389         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9390                 size = NVRAM_SELFBOOT_HW_SIZE;
9391         else
9392                 return -EIO;
9393
9394         buf = kmalloc(size, GFP_KERNEL);
9395         if (buf == NULL)
9396                 return -ENOMEM;
9397
9398         err = -EIO;
9399         for (i = 0, j = 0; i < size; i += 4, j++) {
9400                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9401                 if (err)
9402                         break;
9403         }
9404         if (i < size)
9405                 goto out;
9406
9407         /* Selfboot format */
9408         magic = be32_to_cpu(buf[0]);
9409         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9410             TG3_EEPROM_MAGIC_FW) {
9411                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9412
9413                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9414                     TG3_EEPROM_SB_REVISION_2) {
9415                         /* For rev 2, the csum doesn't include the MBA. */
9416                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9417                                 csum8 += buf8[i];
9418                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9419                                 csum8 += buf8[i];
9420                 } else {
9421                         for (i = 0; i < size; i++)
9422                                 csum8 += buf8[i];
9423                 }
9424
9425                 if (csum8 == 0) {
9426                         err = 0;
9427                         goto out;
9428                 }
9429
9430                 err = -EIO;
9431                 goto out;
9432         }
9433
9434         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9435             TG3_EEPROM_MAGIC_HW) {
9436                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9437                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9438                 u8 *buf8 = (u8 *) buf;
9439
9440                 /* Separate the parity bits and the data bytes.  */
9441                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9442                         if ((i == 0) || (i == 8)) {
9443                                 int l;
9444                                 u8 msk;
9445
9446                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9447                                         parity[k++] = buf8[i] & msk;
9448                                 i++;
9449                         }
9450                         else if (i == 16) {
9451                                 int l;
9452                                 u8 msk;
9453
9454                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9455                                         parity[k++] = buf8[i] & msk;
9456                                 i++;
9457
9458                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9459                                         parity[k++] = buf8[i] & msk;
9460                                 i++;
9461                         }
9462                         data[j++] = buf8[i];
9463                 }
9464
9465                 err = -EIO;
9466                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9467                         u8 hw8 = hweight8(data[i]);
9468
9469                         if ((hw8 & 0x1) && parity[i])
9470                                 goto out;
9471                         else if (!(hw8 & 0x1) && !parity[i])
9472                                 goto out;
9473                 }
9474                 err = 0;
9475                 goto out;
9476         }
9477
9478         /* Bootstrap checksum at offset 0x10 */
9479         csum = calc_crc((unsigned char *) buf, 0x10);
9480         if (csum != be32_to_cpu(buf[0x10/4]))
9481                 goto out;
9482
9483         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9484         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9485         if (csum != be32_to_cpu(buf[0xfc/4]))
9486                 goto out;
9487
9488         err = 0;
9489
9490 out:
9491         kfree(buf);
9492         return err;
9493 }
9494
9495 #define TG3_SERDES_TIMEOUT_SEC  2
9496 #define TG3_COPPER_TIMEOUT_SEC  6
9497
9498 static int tg3_test_link(struct tg3 *tp)
9499 {
9500         int i, max;
9501
9502         if (!netif_running(tp->dev))
9503                 return -ENODEV;
9504
9505         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9506                 max = TG3_SERDES_TIMEOUT_SEC;
9507         else
9508                 max = TG3_COPPER_TIMEOUT_SEC;
9509
9510         for (i = 0; i < max; i++) {
9511                 if (netif_carrier_ok(tp->dev))
9512                         return 0;
9513
9514                 if (msleep_interruptible(1000))
9515                         break;
9516         }
9517
9518         return -EIO;
9519 }
9520
9521 /* Only test the commonly used registers */
9522 static int tg3_test_registers(struct tg3 *tp)
9523 {
9524         int i, is_5705, is_5750;
9525         u32 offset, read_mask, write_mask, val, save_val, read_val;
9526         static struct {
9527                 u16 offset;
9528                 u16 flags;
9529 #define TG3_FL_5705     0x1
9530 #define TG3_FL_NOT_5705 0x2
9531 #define TG3_FL_NOT_5788 0x4
9532 #define TG3_FL_NOT_5750 0x8
9533                 u32 read_mask;
9534                 u32 write_mask;
9535         } reg_tbl[] = {
9536                 /* MAC Control Registers */
9537                 { MAC_MODE, TG3_FL_NOT_5705,
9538                         0x00000000, 0x00ef6f8c },
9539                 { MAC_MODE, TG3_FL_5705,
9540                         0x00000000, 0x01ef6b8c },
9541                 { MAC_STATUS, TG3_FL_NOT_5705,
9542                         0x03800107, 0x00000000 },
9543                 { MAC_STATUS, TG3_FL_5705,
9544                         0x03800100, 0x00000000 },
9545                 { MAC_ADDR_0_HIGH, 0x0000,
9546                         0x00000000, 0x0000ffff },
9547                 { MAC_ADDR_0_LOW, 0x0000,
9548                         0x00000000, 0xffffffff },
9549                 { MAC_RX_MTU_SIZE, 0x0000,
9550                         0x00000000, 0x0000ffff },
9551                 { MAC_TX_MODE, 0x0000,
9552                         0x00000000, 0x00000070 },
9553                 { MAC_TX_LENGTHS, 0x0000,
9554                         0x00000000, 0x00003fff },
9555                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9556                         0x00000000, 0x000007fc },
9557                 { MAC_RX_MODE, TG3_FL_5705,
9558                         0x00000000, 0x000007dc },
9559                 { MAC_HASH_REG_0, 0x0000,
9560                         0x00000000, 0xffffffff },
9561                 { MAC_HASH_REG_1, 0x0000,
9562                         0x00000000, 0xffffffff },
9563                 { MAC_HASH_REG_2, 0x0000,
9564                         0x00000000, 0xffffffff },
9565                 { MAC_HASH_REG_3, 0x0000,
9566                         0x00000000, 0xffffffff },
9567
9568                 /* Receive Data and Receive BD Initiator Control Registers. */
9569                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9570                         0x00000000, 0xffffffff },
9571                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9572                         0x00000000, 0xffffffff },
9573                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9574                         0x00000000, 0x00000003 },
9575                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9576                         0x00000000, 0xffffffff },
9577                 { RCVDBDI_STD_BD+0, 0x0000,
9578                         0x00000000, 0xffffffff },
9579                 { RCVDBDI_STD_BD+4, 0x0000,
9580                         0x00000000, 0xffffffff },
9581                 { RCVDBDI_STD_BD+8, 0x0000,
9582                         0x00000000, 0xffff0002 },
9583                 { RCVDBDI_STD_BD+0xc, 0x0000,
9584                         0x00000000, 0xffffffff },
9585
9586                 /* Receive BD Initiator Control Registers. */
9587                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9588                         0x00000000, 0xffffffff },
9589                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9590                         0x00000000, 0x000003ff },
9591                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9592                         0x00000000, 0xffffffff },
9593
9594                 /* Host Coalescing Control Registers. */
9595                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9596                         0x00000000, 0x00000004 },
9597                 { HOSTCC_MODE, TG3_FL_5705,
9598                         0x00000000, 0x000000f6 },
9599                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9600                         0x00000000, 0xffffffff },
9601                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9602                         0x00000000, 0x000003ff },
9603                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9604                         0x00000000, 0xffffffff },
9605                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9606                         0x00000000, 0x000003ff },
9607                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9608                         0x00000000, 0xffffffff },
9609                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9610                         0x00000000, 0x000000ff },
9611                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9612                         0x00000000, 0xffffffff },
9613                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9614                         0x00000000, 0x000000ff },
9615                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9616                         0x00000000, 0xffffffff },
9617                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9618                         0x00000000, 0xffffffff },
9619                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9620                         0x00000000, 0xffffffff },
9621                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9622                         0x00000000, 0x000000ff },
9623                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9624                         0x00000000, 0xffffffff },
9625                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9626                         0x00000000, 0x000000ff },
9627                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9628                         0x00000000, 0xffffffff },
9629                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9630                         0x00000000, 0xffffffff },
9631                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9632                         0x00000000, 0xffffffff },
9633                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9634                         0x00000000, 0xffffffff },
9635                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9636                         0x00000000, 0xffffffff },
9637                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9638                         0xffffffff, 0x00000000 },
9639                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9640                         0xffffffff, 0x00000000 },
9641
9642                 /* Buffer Manager Control Registers. */
9643                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9644                         0x00000000, 0x007fff80 },
9645                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9646                         0x00000000, 0x007fffff },
9647                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9648                         0x00000000, 0x0000003f },
9649                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9650                         0x00000000, 0x000001ff },
9651                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9652                         0x00000000, 0x000001ff },
9653                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9654                         0xffffffff, 0x00000000 },
9655                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9656                         0xffffffff, 0x00000000 },
9657
9658                 /* Mailbox Registers */
9659                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9660                         0x00000000, 0x000001ff },
9661                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9662                         0x00000000, 0x000001ff },
9663                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9664                         0x00000000, 0x000007ff },
9665                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9666                         0x00000000, 0x000001ff },
9667
9668                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9669         };
9670
9671         is_5705 = is_5750 = 0;
9672         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9673                 is_5705 = 1;
9674                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9675                         is_5750 = 1;
9676         }
9677
9678         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9679                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9680                         continue;
9681
9682                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9683                         continue;
9684
9685                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9686                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9687                         continue;
9688
9689                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9690                         continue;
9691
9692                 offset = (u32) reg_tbl[i].offset;
9693                 read_mask = reg_tbl[i].read_mask;
9694                 write_mask = reg_tbl[i].write_mask;
9695
9696                 /* Save the original register content */
9697                 save_val = tr32(offset);
9698
9699                 /* Determine the read-only value. */
9700                 read_val = save_val & read_mask;
9701
9702                 /* Write zero to the register, then make sure the read-only bits
9703                  * are not changed and the read/write bits are all zeros.
9704                  */
9705                 tw32(offset, 0);
9706
9707                 val = tr32(offset);
9708
9709                 /* Test the read-only and read/write bits. */
9710                 if (((val & read_mask) != read_val) || (val & write_mask))
9711                         goto out;
9712
9713                 /* Write ones to all the bits defined by RdMask and WrMask, then
9714                  * make sure the read-only bits are not changed and the
9715                  * read/write bits are all ones.
9716                  */
9717                 tw32(offset, read_mask | write_mask);
9718
9719                 val = tr32(offset);
9720
9721                 /* Test the read-only bits. */
9722                 if ((val & read_mask) != read_val)
9723                         goto out;
9724
9725                 /* Test the read/write bits. */
9726                 if ((val & write_mask) != write_mask)
9727                         goto out;
9728
9729                 tw32(offset, save_val);
9730         }
9731
9732         return 0;
9733
9734 out:
9735         if (netif_msg_hw(tp))
9736                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9737                        offset);
9738         tw32(offset, save_val);
9739         return -EIO;
9740 }
9741
9742 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9743 {
9744         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9745         int i;
9746         u32 j;
9747
9748         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9749                 for (j = 0; j < len; j += 4) {
9750                         u32 val;
9751
9752                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9753                         tg3_read_mem(tp, offset + j, &val);
9754                         if (val != test_pattern[i])
9755                                 return -EIO;
9756                 }
9757         }
9758         return 0;
9759 }
9760
9761 static int tg3_test_memory(struct tg3 *tp)
9762 {
9763         static struct mem_entry {
9764                 u32 offset;
9765                 u32 len;
9766         } mem_tbl_570x[] = {
9767                 { 0x00000000, 0x00b50},
9768                 { 0x00002000, 0x1c000},
9769                 { 0xffffffff, 0x00000}
9770         }, mem_tbl_5705[] = {
9771                 { 0x00000100, 0x0000c},
9772                 { 0x00000200, 0x00008},
9773                 { 0x00004000, 0x00800},
9774                 { 0x00006000, 0x01000},
9775                 { 0x00008000, 0x02000},
9776                 { 0x00010000, 0x0e000},
9777                 { 0xffffffff, 0x00000}
9778         }, mem_tbl_5755[] = {
9779                 { 0x00000200, 0x00008},
9780                 { 0x00004000, 0x00800},
9781                 { 0x00006000, 0x00800},
9782                 { 0x00008000, 0x02000},
9783                 { 0x00010000, 0x0c000},
9784                 { 0xffffffff, 0x00000}
9785         }, mem_tbl_5906[] = {
9786                 { 0x00000200, 0x00008},
9787                 { 0x00004000, 0x00400},
9788                 { 0x00006000, 0x00400},
9789                 { 0x00008000, 0x01000},
9790                 { 0x00010000, 0x01000},
9791                 { 0xffffffff, 0x00000}
9792         };
9793         struct mem_entry *mem_tbl;
9794         int err = 0;
9795         int i;
9796
9797         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9798                 mem_tbl = mem_tbl_5755;
9799         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9800                 mem_tbl = mem_tbl_5906;
9801         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9802                 mem_tbl = mem_tbl_5705;
9803         else
9804                 mem_tbl = mem_tbl_570x;
9805
9806         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9807                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9808                     mem_tbl[i].len)) != 0)
9809                         break;
9810         }
9811
9812         return err;
9813 }
9814
9815 #define TG3_MAC_LOOPBACK        0
9816 #define TG3_PHY_LOOPBACK        1
9817
9818 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9819 {
9820         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9821         u32 desc_idx;
9822         struct sk_buff *skb, *rx_skb;
9823         u8 *tx_data;
9824         dma_addr_t map;
9825         int num_pkts, tx_len, rx_len, i, err;
9826         struct tg3_rx_buffer_desc *desc;
9827         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
9828
9829         if (loopback_mode == TG3_MAC_LOOPBACK) {
9830                 /* HW errata - mac loopback fails in some cases on 5780.
9831                  * Normal traffic and PHY loopback are not affected by
9832                  * errata.
9833                  */
9834                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9835                         return 0;
9836
9837                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9838                            MAC_MODE_PORT_INT_LPBACK;
9839                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9840                         mac_mode |= MAC_MODE_LINK_POLARITY;
9841                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9842                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9843                 else
9844                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9845                 tw32(MAC_MODE, mac_mode);
9846         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9847                 u32 val;
9848
9849                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9850                         tg3_phy_fet_toggle_apd(tp, false);
9851                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9852                 } else
9853                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9854
9855                 tg3_phy_toggle_automdix(tp, 0);
9856
9857                 tg3_writephy(tp, MII_BMCR, val);
9858                 udelay(40);
9859
9860                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9861                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9862                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9863                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9864                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9865                 } else
9866                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9867
9868                 /* reset to prevent losing 1st rx packet intermittently */
9869                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9870                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9871                         udelay(10);
9872                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9873                 }
9874                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9875                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9876                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9877                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9878                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9879                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9880                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9881                 }
9882                 tw32(MAC_MODE, mac_mode);
9883         }
9884         else
9885                 return -EINVAL;
9886
9887         err = -EIO;
9888
9889         tx_len = 1514;
9890         skb = netdev_alloc_skb(tp->dev, tx_len);
9891         if (!skb)
9892                 return -ENOMEM;
9893
9894         tx_data = skb_put(skb, tx_len);
9895         memcpy(tx_data, tp->dev->dev_addr, 6);
9896         memset(tx_data + 6, 0x0, 8);
9897
9898         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9899
9900         for (i = 14; i < tx_len; i++)
9901                 tx_data[i] = (u8) (i & 0xff);
9902
9903         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9904
9905         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9906              HOSTCC_MODE_NOW);
9907
9908         udelay(10);
9909
9910         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9911
9912         num_pkts = 0;
9913
9914         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9915
9916         tp->tx_prod++;
9917         num_pkts++;
9918
9919         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9920                      tp->tx_prod);
9921         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9922
9923         udelay(10);
9924
9925         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9926         for (i = 0; i < 25; i++) {
9927                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9928                        HOSTCC_MODE_NOW);
9929
9930                 udelay(10);
9931
9932                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9933                 rx_idx = tp->hw_status->idx[0].rx_producer;
9934                 if ((tx_idx == tp->tx_prod) &&
9935                     (rx_idx == (rx_start_idx + num_pkts)))
9936                         break;
9937         }
9938
9939         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9940         dev_kfree_skb(skb);
9941
9942         if (tx_idx != tp->tx_prod)
9943                 goto out;
9944
9945         if (rx_idx != rx_start_idx + num_pkts)
9946                 goto out;
9947
9948         desc = &tp->rx_rcb[rx_start_idx];
9949         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9950         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9951         if (opaque_key != RXD_OPAQUE_RING_STD)
9952                 goto out;
9953
9954         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9955             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9956                 goto out;
9957
9958         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9959         if (rx_len != tx_len)
9960                 goto out;
9961
9962         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
9963
9964         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
9965         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9966
9967         for (i = 14; i < tx_len; i++) {
9968                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9969                         goto out;
9970         }
9971         err = 0;
9972
9973         /* tg3_free_rings will unmap and free the rx_skb */
9974 out:
9975         return err;
9976 }
9977
9978 #define TG3_MAC_LOOPBACK_FAILED         1
9979 #define TG3_PHY_LOOPBACK_FAILED         2
9980 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9981                                          TG3_PHY_LOOPBACK_FAILED)
9982
9983 static int tg3_test_loopback(struct tg3 *tp)
9984 {
9985         int err = 0;
9986         u32 cpmuctrl = 0;
9987
9988         if (!netif_running(tp->dev))
9989                 return TG3_LOOPBACK_FAILED;
9990
9991         err = tg3_reset_hw(tp, 1);
9992         if (err)
9993                 return TG3_LOOPBACK_FAILED;
9994
9995         /* Turn off gphy autopowerdown. */
9996         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9997                 tg3_phy_toggle_apd(tp, false);
9998
9999         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10000                 int i;
10001                 u32 status;
10002
10003                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10004
10005                 /* Wait for up to 40 microseconds to acquire lock. */
10006                 for (i = 0; i < 4; i++) {
10007                         status = tr32(TG3_CPMU_MUTEX_GNT);
10008                         if (status == CPMU_MUTEX_GNT_DRIVER)
10009                                 break;
10010                         udelay(10);
10011                 }
10012
10013                 if (status != CPMU_MUTEX_GNT_DRIVER)
10014                         return TG3_LOOPBACK_FAILED;
10015
10016                 /* Turn off link-based power management. */
10017                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10018                 tw32(TG3_CPMU_CTRL,
10019                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10020                                   CPMU_CTRL_LINK_AWARE_MODE));
10021         }
10022
10023         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10024                 err |= TG3_MAC_LOOPBACK_FAILED;
10025
10026         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10027                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10028
10029                 /* Release the mutex */
10030                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10031         }
10032
10033         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10034             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10035                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10036                         err |= TG3_PHY_LOOPBACK_FAILED;
10037         }
10038
10039         /* Re-enable gphy autopowerdown. */
10040         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10041                 tg3_phy_toggle_apd(tp, true);
10042
10043         return err;
10044 }
10045
10046 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10047                           u64 *data)
10048 {
10049         struct tg3 *tp = netdev_priv(dev);
10050
10051         if (tp->link_config.phy_is_low_power)
10052                 tg3_set_power_state(tp, PCI_D0);
10053
10054         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10055
10056         if (tg3_test_nvram(tp) != 0) {
10057                 etest->flags |= ETH_TEST_FL_FAILED;
10058                 data[0] = 1;
10059         }
10060         if (tg3_test_link(tp) != 0) {
10061                 etest->flags |= ETH_TEST_FL_FAILED;
10062                 data[1] = 1;
10063         }
10064         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10065                 int err, err2 = 0, irq_sync = 0;
10066
10067                 if (netif_running(dev)) {
10068                         tg3_phy_stop(tp);
10069                         tg3_netif_stop(tp);
10070                         irq_sync = 1;
10071                 }
10072
10073                 tg3_full_lock(tp, irq_sync);
10074
10075                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10076                 err = tg3_nvram_lock(tp);
10077                 tg3_halt_cpu(tp, RX_CPU_BASE);
10078                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10079                         tg3_halt_cpu(tp, TX_CPU_BASE);
10080                 if (!err)
10081                         tg3_nvram_unlock(tp);
10082
10083                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10084                         tg3_phy_reset(tp);
10085
10086                 if (tg3_test_registers(tp) != 0) {
10087                         etest->flags |= ETH_TEST_FL_FAILED;
10088                         data[2] = 1;
10089                 }
10090                 if (tg3_test_memory(tp) != 0) {
10091                         etest->flags |= ETH_TEST_FL_FAILED;
10092                         data[3] = 1;
10093                 }
10094                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10095                         etest->flags |= ETH_TEST_FL_FAILED;
10096
10097                 tg3_full_unlock(tp);
10098
10099                 if (tg3_test_interrupt(tp) != 0) {
10100                         etest->flags |= ETH_TEST_FL_FAILED;
10101                         data[5] = 1;
10102                 }
10103
10104                 tg3_full_lock(tp, 0);
10105
10106                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10107                 if (netif_running(dev)) {
10108                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10109                         err2 = tg3_restart_hw(tp, 1);
10110                         if (!err2)
10111                                 tg3_netif_start(tp);
10112                 }
10113
10114                 tg3_full_unlock(tp);
10115
10116                 if (irq_sync && !err2)
10117                         tg3_phy_start(tp);
10118         }
10119         if (tp->link_config.phy_is_low_power)
10120                 tg3_set_power_state(tp, PCI_D3hot);
10121
10122 }
10123
10124 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10125 {
10126         struct mii_ioctl_data *data = if_mii(ifr);
10127         struct tg3 *tp = netdev_priv(dev);
10128         int err;
10129
10130         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10131                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10132                         return -EAGAIN;
10133                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10134         }
10135
10136         switch(cmd) {
10137         case SIOCGMIIPHY:
10138                 data->phy_id = PHY_ADDR;
10139
10140                 /* fallthru */
10141         case SIOCGMIIREG: {
10142                 u32 mii_regval;
10143
10144                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10145                         break;                  /* We have no PHY */
10146
10147                 if (tp->link_config.phy_is_low_power)
10148                         return -EAGAIN;
10149
10150                 spin_lock_bh(&tp->lock);
10151                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10152                 spin_unlock_bh(&tp->lock);
10153
10154                 data->val_out = mii_regval;
10155
10156                 return err;
10157         }
10158
10159         case SIOCSMIIREG:
10160                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10161                         break;                  /* We have no PHY */
10162
10163                 if (!capable(CAP_NET_ADMIN))
10164                         return -EPERM;
10165
10166                 if (tp->link_config.phy_is_low_power)
10167                         return -EAGAIN;
10168
10169                 spin_lock_bh(&tp->lock);
10170                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10171                 spin_unlock_bh(&tp->lock);
10172
10173                 return err;
10174
10175         default:
10176                 /* do nothing */
10177                 break;
10178         }
10179         return -EOPNOTSUPP;
10180 }
10181
10182 #if TG3_VLAN_TAG_USED
10183 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10184 {
10185         struct tg3 *tp = netdev_priv(dev);
10186
10187         if (!netif_running(dev)) {
10188                 tp->vlgrp = grp;
10189                 return;
10190         }
10191
10192         tg3_netif_stop(tp);
10193
10194         tg3_full_lock(tp, 0);
10195
10196         tp->vlgrp = grp;
10197
10198         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10199         __tg3_set_rx_mode(dev);
10200
10201         tg3_netif_start(tp);
10202
10203         tg3_full_unlock(tp);
10204 }
10205 #endif
10206
10207 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10208 {
10209         struct tg3 *tp = netdev_priv(dev);
10210
10211         memcpy(ec, &tp->coal, sizeof(*ec));
10212         return 0;
10213 }
10214
10215 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10216 {
10217         struct tg3 *tp = netdev_priv(dev);
10218         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10219         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10220
10221         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10222                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10223                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10224                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10225                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10226         }
10227
10228         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10229             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10230             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10231             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10232             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10233             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10234             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10235             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10236             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10237             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10238                 return -EINVAL;
10239
10240         /* No rx interrupts will be generated if both are zero */
10241         if ((ec->rx_coalesce_usecs == 0) &&
10242             (ec->rx_max_coalesced_frames == 0))
10243                 return -EINVAL;
10244
10245         /* No tx interrupts will be generated if both are zero */
10246         if ((ec->tx_coalesce_usecs == 0) &&
10247             (ec->tx_max_coalesced_frames == 0))
10248                 return -EINVAL;
10249
10250         /* Only copy relevant parameters, ignore all others. */
10251         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10252         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10253         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10254         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10255         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10256         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10257         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10258         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10259         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10260
10261         if (netif_running(dev)) {
10262                 tg3_full_lock(tp, 0);
10263                 __tg3_set_coalesce(tp, &tp->coal);
10264                 tg3_full_unlock(tp);
10265         }
10266         return 0;
10267 }
10268
10269 static const struct ethtool_ops tg3_ethtool_ops = {
10270         .get_settings           = tg3_get_settings,
10271         .set_settings           = tg3_set_settings,
10272         .get_drvinfo            = tg3_get_drvinfo,
10273         .get_regs_len           = tg3_get_regs_len,
10274         .get_regs               = tg3_get_regs,
10275         .get_wol                = tg3_get_wol,
10276         .set_wol                = tg3_set_wol,
10277         .get_msglevel           = tg3_get_msglevel,
10278         .set_msglevel           = tg3_set_msglevel,
10279         .nway_reset             = tg3_nway_reset,
10280         .get_link               = ethtool_op_get_link,
10281         .get_eeprom_len         = tg3_get_eeprom_len,
10282         .get_eeprom             = tg3_get_eeprom,
10283         .set_eeprom             = tg3_set_eeprom,
10284         .get_ringparam          = tg3_get_ringparam,
10285         .set_ringparam          = tg3_set_ringparam,
10286         .get_pauseparam         = tg3_get_pauseparam,
10287         .set_pauseparam         = tg3_set_pauseparam,
10288         .get_rx_csum            = tg3_get_rx_csum,
10289         .set_rx_csum            = tg3_set_rx_csum,
10290         .set_tx_csum            = tg3_set_tx_csum,
10291         .set_sg                 = ethtool_op_set_sg,
10292         .set_tso                = tg3_set_tso,
10293         .self_test              = tg3_self_test,
10294         .get_strings            = tg3_get_strings,
10295         .phys_id                = tg3_phys_id,
10296         .get_ethtool_stats      = tg3_get_ethtool_stats,
10297         .get_coalesce           = tg3_get_coalesce,
10298         .set_coalesce           = tg3_set_coalesce,
10299         .get_sset_count         = tg3_get_sset_count,
10300 };
10301
10302 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10303 {
10304         u32 cursize, val, magic;
10305
10306         tp->nvram_size = EEPROM_CHIP_SIZE;
10307
10308         if (tg3_nvram_read(tp, 0, &magic) != 0)
10309                 return;
10310
10311         if ((magic != TG3_EEPROM_MAGIC) &&
10312             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10313             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10314                 return;
10315
10316         /*
10317          * Size the chip by reading offsets at increasing powers of two.
10318          * When we encounter our validation signature, we know the addressing
10319          * has wrapped around, and thus have our chip size.
10320          */
10321         cursize = 0x10;
10322
10323         while (cursize < tp->nvram_size) {
10324                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10325                         return;
10326
10327                 if (val == magic)
10328                         break;
10329
10330                 cursize <<= 1;
10331         }
10332
10333         tp->nvram_size = cursize;
10334 }
10335
10336 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10337 {
10338         u32 val;
10339
10340         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10341             tg3_nvram_read(tp, 0, &val) != 0)
10342                 return;
10343
10344         /* Selfboot format */
10345         if (val != TG3_EEPROM_MAGIC) {
10346                 tg3_get_eeprom_size(tp);
10347                 return;
10348         }
10349
10350         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10351                 if (val != 0) {
10352                         /* This is confusing.  We want to operate on the
10353                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10354                          * call will read from NVRAM and byteswap the data
10355                          * according to the byteswapping settings for all
10356                          * other register accesses.  This ensures the data we
10357                          * want will always reside in the lower 16-bits.
10358                          * However, the data in NVRAM is in LE format, which
10359                          * means the data from the NVRAM read will always be
10360                          * opposite the endianness of the CPU.  The 16-bit
10361                          * byteswap then brings the data to CPU endianness.
10362                          */
10363                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10364                         return;
10365                 }
10366         }
10367         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10368 }
10369
10370 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10371 {
10372         u32 nvcfg1;
10373
10374         nvcfg1 = tr32(NVRAM_CFG1);
10375         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10377         } else {
10378                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10379                 tw32(NVRAM_CFG1, nvcfg1);
10380         }
10381
10382         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10383             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10384                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10385                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10386                         tp->nvram_jedecnum = JEDEC_ATMEL;
10387                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10388                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10389                         break;
10390                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10391                         tp->nvram_jedecnum = JEDEC_ATMEL;
10392                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10393                         break;
10394                 case FLASH_VENDOR_ATMEL_EEPROM:
10395                         tp->nvram_jedecnum = JEDEC_ATMEL;
10396                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10397                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10398                         break;
10399                 case FLASH_VENDOR_ST:
10400                         tp->nvram_jedecnum = JEDEC_ST;
10401                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10402                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10403                         break;
10404                 case FLASH_VENDOR_SAIFUN:
10405                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10406                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10407                         break;
10408                 case FLASH_VENDOR_SST_SMALL:
10409                 case FLASH_VENDOR_SST_LARGE:
10410                         tp->nvram_jedecnum = JEDEC_SST;
10411                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10412                         break;
10413                 }
10414         } else {
10415                 tp->nvram_jedecnum = JEDEC_ATMEL;
10416                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10417                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10418         }
10419 }
10420
10421 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10422 {
10423         u32 nvcfg1;
10424
10425         nvcfg1 = tr32(NVRAM_CFG1);
10426
10427         /* NVRAM protection for TPM */
10428         if (nvcfg1 & (1 << 27))
10429                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10430
10431         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10432         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10433         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10434                 tp->nvram_jedecnum = JEDEC_ATMEL;
10435                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10436                 break;
10437         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10438                 tp->nvram_jedecnum = JEDEC_ATMEL;
10439                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10440                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10441                 break;
10442         case FLASH_5752VENDOR_ST_M45PE10:
10443         case FLASH_5752VENDOR_ST_M45PE20:
10444         case FLASH_5752VENDOR_ST_M45PE40:
10445                 tp->nvram_jedecnum = JEDEC_ST;
10446                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10447                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10448                 break;
10449         }
10450
10451         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10452                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10453                 case FLASH_5752PAGE_SIZE_256:
10454                         tp->nvram_pagesize = 256;
10455                         break;
10456                 case FLASH_5752PAGE_SIZE_512:
10457                         tp->nvram_pagesize = 512;
10458                         break;
10459                 case FLASH_5752PAGE_SIZE_1K:
10460                         tp->nvram_pagesize = 1024;
10461                         break;
10462                 case FLASH_5752PAGE_SIZE_2K:
10463                         tp->nvram_pagesize = 2048;
10464                         break;
10465                 case FLASH_5752PAGE_SIZE_4K:
10466                         tp->nvram_pagesize = 4096;
10467                         break;
10468                 case FLASH_5752PAGE_SIZE_264:
10469                         tp->nvram_pagesize = 264;
10470                         break;
10471                 }
10472         } else {
10473                 /* For eeprom, set pagesize to maximum eeprom size */
10474                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10475
10476                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10477                 tw32(NVRAM_CFG1, nvcfg1);
10478         }
10479 }
10480
10481 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10482 {
10483         u32 nvcfg1, protect = 0;
10484
10485         nvcfg1 = tr32(NVRAM_CFG1);
10486
10487         /* NVRAM protection for TPM */
10488         if (nvcfg1 & (1 << 27)) {
10489                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10490                 protect = 1;
10491         }
10492
10493         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10494         switch (nvcfg1) {
10495         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10496         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10497         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10498         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10499                 tp->nvram_jedecnum = JEDEC_ATMEL;
10500                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10501                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10502                 tp->nvram_pagesize = 264;
10503                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10504                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10505                         tp->nvram_size = (protect ? 0x3e200 :
10506                                           TG3_NVRAM_SIZE_512KB);
10507                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10508                         tp->nvram_size = (protect ? 0x1f200 :
10509                                           TG3_NVRAM_SIZE_256KB);
10510                 else
10511                         tp->nvram_size = (protect ? 0x1f200 :
10512                                           TG3_NVRAM_SIZE_128KB);
10513                 break;
10514         case FLASH_5752VENDOR_ST_M45PE10:
10515         case FLASH_5752VENDOR_ST_M45PE20:
10516         case FLASH_5752VENDOR_ST_M45PE40:
10517                 tp->nvram_jedecnum = JEDEC_ST;
10518                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10520                 tp->nvram_pagesize = 256;
10521                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10522                         tp->nvram_size = (protect ?
10523                                           TG3_NVRAM_SIZE_64KB :
10524                                           TG3_NVRAM_SIZE_128KB);
10525                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10526                         tp->nvram_size = (protect ?
10527                                           TG3_NVRAM_SIZE_64KB :
10528                                           TG3_NVRAM_SIZE_256KB);
10529                 else
10530                         tp->nvram_size = (protect ?
10531                                           TG3_NVRAM_SIZE_128KB :
10532                                           TG3_NVRAM_SIZE_512KB);
10533                 break;
10534         }
10535 }
10536
10537 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10538 {
10539         u32 nvcfg1;
10540
10541         nvcfg1 = tr32(NVRAM_CFG1);
10542
10543         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10544         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10545         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10546         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10547         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10548                 tp->nvram_jedecnum = JEDEC_ATMEL;
10549                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10550                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10551
10552                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10553                 tw32(NVRAM_CFG1, nvcfg1);
10554                 break;
10555         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10556         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10557         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10558         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10559                 tp->nvram_jedecnum = JEDEC_ATMEL;
10560                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10561                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10562                 tp->nvram_pagesize = 264;
10563                 break;
10564         case FLASH_5752VENDOR_ST_M45PE10:
10565         case FLASH_5752VENDOR_ST_M45PE20:
10566         case FLASH_5752VENDOR_ST_M45PE40:
10567                 tp->nvram_jedecnum = JEDEC_ST;
10568                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10569                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10570                 tp->nvram_pagesize = 256;
10571                 break;
10572         }
10573 }
10574
10575 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10576 {
10577         u32 nvcfg1, protect = 0;
10578
10579         nvcfg1 = tr32(NVRAM_CFG1);
10580
10581         /* NVRAM protection for TPM */
10582         if (nvcfg1 & (1 << 27)) {
10583                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10584                 protect = 1;
10585         }
10586
10587         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10588         switch (nvcfg1) {
10589         case FLASH_5761VENDOR_ATMEL_ADB021D:
10590         case FLASH_5761VENDOR_ATMEL_ADB041D:
10591         case FLASH_5761VENDOR_ATMEL_ADB081D:
10592         case FLASH_5761VENDOR_ATMEL_ADB161D:
10593         case FLASH_5761VENDOR_ATMEL_MDB021D:
10594         case FLASH_5761VENDOR_ATMEL_MDB041D:
10595         case FLASH_5761VENDOR_ATMEL_MDB081D:
10596         case FLASH_5761VENDOR_ATMEL_MDB161D:
10597                 tp->nvram_jedecnum = JEDEC_ATMEL;
10598                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10599                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10600                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10601                 tp->nvram_pagesize = 256;
10602                 break;
10603         case FLASH_5761VENDOR_ST_A_M45PE20:
10604         case FLASH_5761VENDOR_ST_A_M45PE40:
10605         case FLASH_5761VENDOR_ST_A_M45PE80:
10606         case FLASH_5761VENDOR_ST_A_M45PE16:
10607         case FLASH_5761VENDOR_ST_M_M45PE20:
10608         case FLASH_5761VENDOR_ST_M_M45PE40:
10609         case FLASH_5761VENDOR_ST_M_M45PE80:
10610         case FLASH_5761VENDOR_ST_M_M45PE16:
10611                 tp->nvram_jedecnum = JEDEC_ST;
10612                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10613                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10614                 tp->nvram_pagesize = 256;
10615                 break;
10616         }
10617
10618         if (protect) {
10619                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10620         } else {
10621                 switch (nvcfg1) {
10622                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10623                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10624                 case FLASH_5761VENDOR_ST_A_M45PE16:
10625                 case FLASH_5761VENDOR_ST_M_M45PE16:
10626                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10627                         break;
10628                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10629                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10630                 case FLASH_5761VENDOR_ST_A_M45PE80:
10631                 case FLASH_5761VENDOR_ST_M_M45PE80:
10632                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10633                         break;
10634                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10635                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10636                 case FLASH_5761VENDOR_ST_A_M45PE40:
10637                 case FLASH_5761VENDOR_ST_M_M45PE40:
10638                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10639                         break;
10640                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10641                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10642                 case FLASH_5761VENDOR_ST_A_M45PE20:
10643                 case FLASH_5761VENDOR_ST_M_M45PE20:
10644                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10645                         break;
10646                 }
10647         }
10648 }
10649
10650 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10651 {
10652         tp->nvram_jedecnum = JEDEC_ATMEL;
10653         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10654         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10655 }
10656
10657 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10658 {
10659         u32 nvcfg1;
10660
10661         nvcfg1 = tr32(NVRAM_CFG1);
10662
10663         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10664         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10665         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10666                 tp->nvram_jedecnum = JEDEC_ATMEL;
10667                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10668                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10669
10670                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10671                 tw32(NVRAM_CFG1, nvcfg1);
10672                 return;
10673         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10674         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10675         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10676         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10677         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10678         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10679         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10680                 tp->nvram_jedecnum = JEDEC_ATMEL;
10681                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10682                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10683
10684                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10685                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10686                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10687                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10688                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10689                         break;
10690                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10691                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10692                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10693                         break;
10694                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10695                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10696                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10697                         break;
10698                 }
10699                 break;
10700         case FLASH_5752VENDOR_ST_M45PE10:
10701         case FLASH_5752VENDOR_ST_M45PE20:
10702         case FLASH_5752VENDOR_ST_M45PE40:
10703                 tp->nvram_jedecnum = JEDEC_ST;
10704                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10705                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10706
10707                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10708                 case FLASH_5752VENDOR_ST_M45PE10:
10709                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10710                         break;
10711                 case FLASH_5752VENDOR_ST_M45PE20:
10712                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10713                         break;
10714                 case FLASH_5752VENDOR_ST_M45PE40:
10715                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10716                         break;
10717                 }
10718                 break;
10719         default:
10720                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10721                 return;
10722         }
10723
10724         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10725         case FLASH_5752PAGE_SIZE_256:
10726                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10727                 tp->nvram_pagesize = 256;
10728                 break;
10729         case FLASH_5752PAGE_SIZE_512:
10730                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10731                 tp->nvram_pagesize = 512;
10732                 break;
10733         case FLASH_5752PAGE_SIZE_1K:
10734                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10735                 tp->nvram_pagesize = 1024;
10736                 break;
10737         case FLASH_5752PAGE_SIZE_2K:
10738                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10739                 tp->nvram_pagesize = 2048;
10740                 break;
10741         case FLASH_5752PAGE_SIZE_4K:
10742                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10743                 tp->nvram_pagesize = 4096;
10744                 break;
10745         case FLASH_5752PAGE_SIZE_264:
10746                 tp->nvram_pagesize = 264;
10747                 break;
10748         case FLASH_5752PAGE_SIZE_528:
10749                 tp->nvram_pagesize = 528;
10750                 break;
10751         }
10752 }
10753
10754 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10755 static void __devinit tg3_nvram_init(struct tg3 *tp)
10756 {
10757         tw32_f(GRC_EEPROM_ADDR,
10758              (EEPROM_ADDR_FSM_RESET |
10759               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10760                EEPROM_ADDR_CLKPERD_SHIFT)));
10761
10762         msleep(1);
10763
10764         /* Enable seeprom accesses. */
10765         tw32_f(GRC_LOCAL_CTRL,
10766              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10767         udelay(100);
10768
10769         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10770             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10771                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10772
10773                 if (tg3_nvram_lock(tp)) {
10774                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10775                                "tg3_nvram_init failed.\n", tp->dev->name);
10776                         return;
10777                 }
10778                 tg3_enable_nvram_access(tp);
10779
10780                 tp->nvram_size = 0;
10781
10782                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10783                         tg3_get_5752_nvram_info(tp);
10784                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10785                         tg3_get_5755_nvram_info(tp);
10786                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10787                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10788                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10789                         tg3_get_5787_nvram_info(tp);
10790                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10791                         tg3_get_5761_nvram_info(tp);
10792                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10793                         tg3_get_5906_nvram_info(tp);
10794                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10795                         tg3_get_57780_nvram_info(tp);
10796                 else
10797                         tg3_get_nvram_info(tp);
10798
10799                 if (tp->nvram_size == 0)
10800                         tg3_get_nvram_size(tp);
10801
10802                 tg3_disable_nvram_access(tp);
10803                 tg3_nvram_unlock(tp);
10804
10805         } else {
10806                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10807
10808                 tg3_get_eeprom_size(tp);
10809         }
10810 }
10811
10812 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10813                                     u32 offset, u32 len, u8 *buf)
10814 {
10815         int i, j, rc = 0;
10816         u32 val;
10817
10818         for (i = 0; i < len; i += 4) {
10819                 u32 addr;
10820                 __be32 data;
10821
10822                 addr = offset + i;
10823
10824                 memcpy(&data, buf + i, 4);
10825
10826                 /*
10827                  * The SEEPROM interface expects the data to always be opposite
10828                  * the native endian format.  We accomplish this by reversing
10829                  * all the operations that would have been performed on the
10830                  * data from a call to tg3_nvram_read_be32().
10831                  */
10832                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10833
10834                 val = tr32(GRC_EEPROM_ADDR);
10835                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10836
10837                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10838                         EEPROM_ADDR_READ);
10839                 tw32(GRC_EEPROM_ADDR, val |
10840                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10841                         (addr & EEPROM_ADDR_ADDR_MASK) |
10842                         EEPROM_ADDR_START |
10843                         EEPROM_ADDR_WRITE);
10844
10845                 for (j = 0; j < 1000; j++) {
10846                         val = tr32(GRC_EEPROM_ADDR);
10847
10848                         if (val & EEPROM_ADDR_COMPLETE)
10849                                 break;
10850                         msleep(1);
10851                 }
10852                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10853                         rc = -EBUSY;
10854                         break;
10855                 }
10856         }
10857
10858         return rc;
10859 }
10860
10861 /* offset and length are dword aligned */
10862 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10863                 u8 *buf)
10864 {
10865         int ret = 0;
10866         u32 pagesize = tp->nvram_pagesize;
10867         u32 pagemask = pagesize - 1;
10868         u32 nvram_cmd;
10869         u8 *tmp;
10870
10871         tmp = kmalloc(pagesize, GFP_KERNEL);
10872         if (tmp == NULL)
10873                 return -ENOMEM;
10874
10875         while (len) {
10876                 int j;
10877                 u32 phy_addr, page_off, size;
10878
10879                 phy_addr = offset & ~pagemask;
10880
10881                 for (j = 0; j < pagesize; j += 4) {
10882                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10883                                                   (__be32 *) (tmp + j));
10884                         if (ret)
10885                                 break;
10886                 }
10887                 if (ret)
10888                         break;
10889
10890                 page_off = offset & pagemask;
10891                 size = pagesize;
10892                 if (len < size)
10893                         size = len;
10894
10895                 len -= size;
10896
10897                 memcpy(tmp + page_off, buf, size);
10898
10899                 offset = offset + (pagesize - page_off);
10900
10901                 tg3_enable_nvram_access(tp);
10902
10903                 /*
10904                  * Before we can erase the flash page, we need
10905                  * to issue a special "write enable" command.
10906                  */
10907                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10908
10909                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10910                         break;
10911
10912                 /* Erase the target page */
10913                 tw32(NVRAM_ADDR, phy_addr);
10914
10915                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10916                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10917
10918                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10919                         break;
10920
10921                 /* Issue another write enable to start the write. */
10922                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10923
10924                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10925                         break;
10926
10927                 for (j = 0; j < pagesize; j += 4) {
10928                         __be32 data;
10929
10930                         data = *((__be32 *) (tmp + j));
10931
10932                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10933
10934                         tw32(NVRAM_ADDR, phy_addr + j);
10935
10936                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10937                                 NVRAM_CMD_WR;
10938
10939                         if (j == 0)
10940                                 nvram_cmd |= NVRAM_CMD_FIRST;
10941                         else if (j == (pagesize - 4))
10942                                 nvram_cmd |= NVRAM_CMD_LAST;
10943
10944                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10945                                 break;
10946                 }
10947                 if (ret)
10948                         break;
10949         }
10950
10951         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10952         tg3_nvram_exec_cmd(tp, nvram_cmd);
10953
10954         kfree(tmp);
10955
10956         return ret;
10957 }
10958
10959 /* offset and length are dword aligned */
10960 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10961                 u8 *buf)
10962 {
10963         int i, ret = 0;
10964
10965         for (i = 0; i < len; i += 4, offset += 4) {
10966                 u32 page_off, phy_addr, nvram_cmd;
10967                 __be32 data;
10968
10969                 memcpy(&data, buf + i, 4);
10970                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10971
10972                 page_off = offset % tp->nvram_pagesize;
10973
10974                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10975
10976                 tw32(NVRAM_ADDR, phy_addr);
10977
10978                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10979
10980                 if ((page_off == 0) || (i == 0))
10981                         nvram_cmd |= NVRAM_CMD_FIRST;
10982                 if (page_off == (tp->nvram_pagesize - 4))
10983                         nvram_cmd |= NVRAM_CMD_LAST;
10984
10985                 if (i == (len - 4))
10986                         nvram_cmd |= NVRAM_CMD_LAST;
10987
10988                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10989                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10990                     (tp->nvram_jedecnum == JEDEC_ST) &&
10991                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10992
10993                         if ((ret = tg3_nvram_exec_cmd(tp,
10994                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10995                                 NVRAM_CMD_DONE)))
10996
10997                                 break;
10998                 }
10999                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11000                         /* We always do complete word writes to eeprom. */
11001                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11002                 }
11003
11004                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11005                         break;
11006         }
11007         return ret;
11008 }
11009
11010 /* offset and length are dword aligned */
11011 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11012 {
11013         int ret;
11014
11015         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11016                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11017                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11018                 udelay(40);
11019         }
11020
11021         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11022                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11023         }
11024         else {
11025                 u32 grc_mode;
11026
11027                 ret = tg3_nvram_lock(tp);
11028                 if (ret)
11029                         return ret;
11030
11031                 tg3_enable_nvram_access(tp);
11032                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11033                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11034                         tw32(NVRAM_WRITE1, 0x406);
11035
11036                 grc_mode = tr32(GRC_MODE);
11037                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11038
11039                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11040                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11041
11042                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11043                                 buf);
11044                 }
11045                 else {
11046                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11047                                 buf);
11048                 }
11049
11050                 grc_mode = tr32(GRC_MODE);
11051                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11052
11053                 tg3_disable_nvram_access(tp);
11054                 tg3_nvram_unlock(tp);
11055         }
11056
11057         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11058                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11059                 udelay(40);
11060         }
11061
11062         return ret;
11063 }
11064
11065 struct subsys_tbl_ent {
11066         u16 subsys_vendor, subsys_devid;
11067         u32 phy_id;
11068 };
11069
11070 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11071         /* Broadcom boards. */
11072         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11073         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11074         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11075         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11076         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11077         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11078         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11079         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11080         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11081         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11082         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11083
11084         /* 3com boards. */
11085         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11086         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11087         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11088         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11089         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11090
11091         /* DELL boards. */
11092         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11093         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11094         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11095         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11096
11097         /* Compaq boards. */
11098         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11099         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11100         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11101         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11102         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11103
11104         /* IBM boards. */
11105         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11106 };
11107
11108 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11109 {
11110         int i;
11111
11112         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11113                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11114                      tp->pdev->subsystem_vendor) &&
11115                     (subsys_id_to_phy_id[i].subsys_devid ==
11116                      tp->pdev->subsystem_device))
11117                         return &subsys_id_to_phy_id[i];
11118         }
11119         return NULL;
11120 }
11121
11122 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11123 {
11124         u32 val;
11125         u16 pmcsr;
11126
11127         /* On some early chips the SRAM cannot be accessed in D3hot state,
11128          * so need make sure we're in D0.
11129          */
11130         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11131         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11132         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11133         msleep(1);
11134
11135         /* Make sure register accesses (indirect or otherwise)
11136          * will function correctly.
11137          */
11138         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11139                                tp->misc_host_ctrl);
11140
11141         /* The memory arbiter has to be enabled in order for SRAM accesses
11142          * to succeed.  Normally on powerup the tg3 chip firmware will make
11143          * sure it is enabled, but other entities such as system netboot
11144          * code might disable it.
11145          */
11146         val = tr32(MEMARB_MODE);
11147         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11148
11149         tp->phy_id = PHY_ID_INVALID;
11150         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11151
11152         /* Assume an onboard device and WOL capable by default.  */
11153         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11154
11155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11156                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11157                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11158                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11159                 }
11160                 val = tr32(VCPU_CFGSHDW);
11161                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11162                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11163                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11164                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11165                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11166                 goto done;
11167         }
11168
11169         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11170         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11171                 u32 nic_cfg, led_cfg;
11172                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11173                 int eeprom_phy_serdes = 0;
11174
11175                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11176                 tp->nic_sram_data_cfg = nic_cfg;
11177
11178                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11179                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11180                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11181                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11182                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11183                     (ver > 0) && (ver < 0x100))
11184                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11185
11186                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11187                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11188
11189                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11190                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11191                         eeprom_phy_serdes = 1;
11192
11193                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11194                 if (nic_phy_id != 0) {
11195                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11196                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11197
11198                         eeprom_phy_id  = (id1 >> 16) << 10;
11199                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11200                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11201                 } else
11202                         eeprom_phy_id = 0;
11203
11204                 tp->phy_id = eeprom_phy_id;
11205                 if (eeprom_phy_serdes) {
11206                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11207                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11208                         else
11209                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11210                 }
11211
11212                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11213                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11214                                     SHASTA_EXT_LED_MODE_MASK);
11215                 else
11216                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11217
11218                 switch (led_cfg) {
11219                 default:
11220                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11221                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11222                         break;
11223
11224                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11225                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11226                         break;
11227
11228                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11229                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11230
11231                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11232                          * read on some older 5700/5701 bootcode.
11233                          */
11234                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11235                             ASIC_REV_5700 ||
11236                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11237                             ASIC_REV_5701)
11238                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11239
11240                         break;
11241
11242                 case SHASTA_EXT_LED_SHARED:
11243                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11244                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11245                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11246                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11247                                                  LED_CTRL_MODE_PHY_2);
11248                         break;
11249
11250                 case SHASTA_EXT_LED_MAC:
11251                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11252                         break;
11253
11254                 case SHASTA_EXT_LED_COMBO:
11255                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11256                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11257                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11258                                                  LED_CTRL_MODE_PHY_2);
11259                         break;
11260
11261                 }
11262
11263                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11264                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11265                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11266                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11267
11268                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11269                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11270
11271                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11272                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11273                         if ((tp->pdev->subsystem_vendor ==
11274                              PCI_VENDOR_ID_ARIMA) &&
11275                             (tp->pdev->subsystem_device == 0x205a ||
11276                              tp->pdev->subsystem_device == 0x2063))
11277                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11278                 } else {
11279                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11280                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11281                 }
11282
11283                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11284                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11285                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11286                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11287                 }
11288
11289                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11290                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11291                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11292
11293                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11294                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11295                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11296
11297                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11298                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11299                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11300
11301                 if (cfg2 & (1 << 17))
11302                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11303
11304                 /* serdes signal pre-emphasis in register 0x590 set by */
11305                 /* bootcode if bit 18 is set */
11306                 if (cfg2 & (1 << 18))
11307                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11308
11309                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11310                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11311                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11312                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11313
11314                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11315                         u32 cfg3;
11316
11317                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11318                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11319                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11320                 }
11321
11322                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11323                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11324                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11325                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11326                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11327                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11328         }
11329 done:
11330         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11331         device_set_wakeup_enable(&tp->pdev->dev,
11332                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11333 }
11334
11335 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11336 {
11337         int i;
11338         u32 val;
11339
11340         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11341         tw32(OTP_CTRL, cmd);
11342
11343         /* Wait for up to 1 ms for command to execute. */
11344         for (i = 0; i < 100; i++) {
11345                 val = tr32(OTP_STATUS);
11346                 if (val & OTP_STATUS_CMD_DONE)
11347                         break;
11348                 udelay(10);
11349         }
11350
11351         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11352 }
11353
11354 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11355  * configuration is a 32-bit value that straddles the alignment boundary.
11356  * We do two 32-bit reads and then shift and merge the results.
11357  */
11358 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11359 {
11360         u32 bhalf_otp, thalf_otp;
11361
11362         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11363
11364         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11365                 return 0;
11366
11367         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11368
11369         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11370                 return 0;
11371
11372         thalf_otp = tr32(OTP_READ_DATA);
11373
11374         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11375
11376         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11377                 return 0;
11378
11379         bhalf_otp = tr32(OTP_READ_DATA);
11380
11381         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11382 }
11383
11384 static int __devinit tg3_phy_probe(struct tg3 *tp)
11385 {
11386         u32 hw_phy_id_1, hw_phy_id_2;
11387         u32 hw_phy_id, hw_phy_id_masked;
11388         int err;
11389
11390         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11391                 return tg3_phy_init(tp);
11392
11393         /* Reading the PHY ID register can conflict with ASF
11394          * firmware access to the PHY hardware.
11395          */
11396         err = 0;
11397         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11398             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11399                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11400         } else {
11401                 /* Now read the physical PHY_ID from the chip and verify
11402                  * that it is sane.  If it doesn't look good, we fall back
11403                  * to either the hard-coded table based PHY_ID and failing
11404                  * that the value found in the eeprom area.
11405                  */
11406                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11407                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11408
11409                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11410                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11411                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11412
11413                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11414         }
11415
11416         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11417                 tp->phy_id = hw_phy_id;
11418                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11419                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11420                 else
11421                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11422         } else {
11423                 if (tp->phy_id != PHY_ID_INVALID) {
11424                         /* Do nothing, phy ID already set up in
11425                          * tg3_get_eeprom_hw_cfg().
11426                          */
11427                 } else {
11428                         struct subsys_tbl_ent *p;
11429
11430                         /* No eeprom signature?  Try the hardcoded
11431                          * subsys device table.
11432                          */
11433                         p = lookup_by_subsys(tp);
11434                         if (!p)
11435                                 return -ENODEV;
11436
11437                         tp->phy_id = p->phy_id;
11438                         if (!tp->phy_id ||
11439                             tp->phy_id == PHY_ID_BCM8002)
11440                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11441                 }
11442         }
11443
11444         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11445             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11446             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11447                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11448
11449                 tg3_readphy(tp, MII_BMSR, &bmsr);
11450                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11451                     (bmsr & BMSR_LSTATUS))
11452                         goto skip_phy_reset;
11453
11454                 err = tg3_phy_reset(tp);
11455                 if (err)
11456                         return err;
11457
11458                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11459                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11460                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11461                 tg3_ctrl = 0;
11462                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11463                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11464                                     MII_TG3_CTRL_ADV_1000_FULL);
11465                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11466                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11467                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11468                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11469                 }
11470
11471                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11472                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11473                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11474                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11475                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11476
11477                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11478                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11479
11480                         tg3_writephy(tp, MII_BMCR,
11481                                      BMCR_ANENABLE | BMCR_ANRESTART);
11482                 }
11483                 tg3_phy_set_wirespeed(tp);
11484
11485                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11486                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11487                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11488         }
11489
11490 skip_phy_reset:
11491         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11492                 err = tg3_init_5401phy_dsp(tp);
11493                 if (err)
11494                         return err;
11495         }
11496
11497         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11498                 err = tg3_init_5401phy_dsp(tp);
11499         }
11500
11501         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11502                 tp->link_config.advertising =
11503                         (ADVERTISED_1000baseT_Half |
11504                          ADVERTISED_1000baseT_Full |
11505                          ADVERTISED_Autoneg |
11506                          ADVERTISED_FIBRE);
11507         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11508                 tp->link_config.advertising &=
11509                         ~(ADVERTISED_1000baseT_Half |
11510                           ADVERTISED_1000baseT_Full);
11511
11512         return err;
11513 }
11514
11515 static void __devinit tg3_read_partno(struct tg3 *tp)
11516 {
11517         unsigned char vpd_data[256];   /* in little-endian format */
11518         unsigned int i;
11519         u32 magic;
11520
11521         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11522             tg3_nvram_read(tp, 0x0, &magic))
11523                 goto out_not_found;
11524
11525         if (magic == TG3_EEPROM_MAGIC) {
11526                 for (i = 0; i < 256; i += 4) {
11527                         u32 tmp;
11528
11529                         /* The data is in little-endian format in NVRAM.
11530                          * Use the big-endian read routines to preserve
11531                          * the byte order as it exists in NVRAM.
11532                          */
11533                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11534                                 goto out_not_found;
11535
11536                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11537                 }
11538         } else {
11539                 int vpd_cap;
11540
11541                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11542                 for (i = 0; i < 256; i += 4) {
11543                         u32 tmp, j = 0;
11544                         __le32 v;
11545                         u16 tmp16;
11546
11547                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11548                                               i);
11549                         while (j++ < 100) {
11550                                 pci_read_config_word(tp->pdev, vpd_cap +
11551                                                      PCI_VPD_ADDR, &tmp16);
11552                                 if (tmp16 & 0x8000)
11553                                         break;
11554                                 msleep(1);
11555                         }
11556                         if (!(tmp16 & 0x8000))
11557                                 goto out_not_found;
11558
11559                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11560                                               &tmp);
11561                         v = cpu_to_le32(tmp);
11562                         memcpy(&vpd_data[i], &v, sizeof(v));
11563                 }
11564         }
11565
11566         /* Now parse and find the part number. */
11567         for (i = 0; i < 254; ) {
11568                 unsigned char val = vpd_data[i];
11569                 unsigned int block_end;
11570
11571                 if (val == 0x82 || val == 0x91) {
11572                         i = (i + 3 +
11573                              (vpd_data[i + 1] +
11574                               (vpd_data[i + 2] << 8)));
11575                         continue;
11576                 }
11577
11578                 if (val != 0x90)
11579                         goto out_not_found;
11580
11581                 block_end = (i + 3 +
11582                              (vpd_data[i + 1] +
11583                               (vpd_data[i + 2] << 8)));
11584                 i += 3;
11585
11586                 if (block_end > 256)
11587                         goto out_not_found;
11588
11589                 while (i < (block_end - 2)) {
11590                         if (vpd_data[i + 0] == 'P' &&
11591                             vpd_data[i + 1] == 'N') {
11592                                 int partno_len = vpd_data[i + 2];
11593
11594                                 i += 3;
11595                                 if (partno_len > 24 || (partno_len + i) > 256)
11596                                         goto out_not_found;
11597
11598                                 memcpy(tp->board_part_number,
11599                                        &vpd_data[i], partno_len);
11600
11601                                 /* Success. */
11602                                 return;
11603                         }
11604                         i += 3 + vpd_data[i + 2];
11605                 }
11606
11607                 /* Part number not found. */
11608                 goto out_not_found;
11609         }
11610
11611 out_not_found:
11612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11613                 strcpy(tp->board_part_number, "BCM95906");
11614         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11615                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11616                 strcpy(tp->board_part_number, "BCM57780");
11617         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11618                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11619                 strcpy(tp->board_part_number, "BCM57760");
11620         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11621                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11622                 strcpy(tp->board_part_number, "BCM57790");
11623         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11624                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11625                 strcpy(tp->board_part_number, "BCM57788");
11626         else
11627                 strcpy(tp->board_part_number, "none");
11628 }
11629
11630 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11631 {
11632         u32 val;
11633
11634         if (tg3_nvram_read(tp, offset, &val) ||
11635             (val & 0xfc000000) != 0x0c000000 ||
11636             tg3_nvram_read(tp, offset + 4, &val) ||
11637             val != 0)
11638                 return 0;
11639
11640         return 1;
11641 }
11642
11643 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11644 {
11645         u32 val, offset, start, ver_offset;
11646         int i;
11647         bool newver = false;
11648
11649         if (tg3_nvram_read(tp, 0xc, &offset) ||
11650             tg3_nvram_read(tp, 0x4, &start))
11651                 return;
11652
11653         offset = tg3_nvram_logical_addr(tp, offset);
11654
11655         if (tg3_nvram_read(tp, offset, &val))
11656                 return;
11657
11658         if ((val & 0xfc000000) == 0x0c000000) {
11659                 if (tg3_nvram_read(tp, offset + 4, &val))
11660                         return;
11661
11662                 if (val == 0)
11663                         newver = true;
11664         }
11665
11666         if (newver) {
11667                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11668                         return;
11669
11670                 offset = offset + ver_offset - start;
11671                 for (i = 0; i < 16; i += 4) {
11672                         __be32 v;
11673                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11674                                 return;
11675
11676                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11677                 }
11678         } else {
11679                 u32 major, minor;
11680
11681                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11682                         return;
11683
11684                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11685                         TG3_NVM_BCVER_MAJSFT;
11686                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11687                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11688         }
11689 }
11690
11691 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11692 {
11693         u32 val, major, minor;
11694
11695         /* Use native endian representation */
11696         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11697                 return;
11698
11699         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11700                 TG3_NVM_HWSB_CFG1_MAJSFT;
11701         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11702                 TG3_NVM_HWSB_CFG1_MINSFT;
11703
11704         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11705 }
11706
11707 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11708 {
11709         u32 offset, major, minor, build;
11710
11711         tp->fw_ver[0] = 's';
11712         tp->fw_ver[1] = 'b';
11713         tp->fw_ver[2] = '\0';
11714
11715         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11716                 return;
11717
11718         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11719         case TG3_EEPROM_SB_REVISION_0:
11720                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11721                 break;
11722         case TG3_EEPROM_SB_REVISION_2:
11723                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11724                 break;
11725         case TG3_EEPROM_SB_REVISION_3:
11726                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11727                 break;
11728         default:
11729                 return;
11730         }
11731
11732         if (tg3_nvram_read(tp, offset, &val))
11733                 return;
11734
11735         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11736                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11737         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11738                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11739         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11740
11741         if (minor > 99 || build > 26)
11742                 return;
11743
11744         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11745
11746         if (build > 0) {
11747                 tp->fw_ver[8] = 'a' + build - 1;
11748                 tp->fw_ver[9] = '\0';
11749         }
11750 }
11751
11752 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11753 {
11754         u32 val, offset, start;
11755         int i, vlen;
11756
11757         for (offset = TG3_NVM_DIR_START;
11758              offset < TG3_NVM_DIR_END;
11759              offset += TG3_NVM_DIRENT_SIZE) {
11760                 if (tg3_nvram_read(tp, offset, &val))
11761                         return;
11762
11763                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11764                         break;
11765         }
11766
11767         if (offset == TG3_NVM_DIR_END)
11768                 return;
11769
11770         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11771                 start = 0x08000000;
11772         else if (tg3_nvram_read(tp, offset - 4, &start))
11773                 return;
11774
11775         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11776             !tg3_fw_img_is_valid(tp, offset) ||
11777             tg3_nvram_read(tp, offset + 8, &val))
11778                 return;
11779
11780         offset += val - start;
11781
11782         vlen = strlen(tp->fw_ver);
11783
11784         tp->fw_ver[vlen++] = ',';
11785         tp->fw_ver[vlen++] = ' ';
11786
11787         for (i = 0; i < 4; i++) {
11788                 __be32 v;
11789                 if (tg3_nvram_read_be32(tp, offset, &v))
11790                         return;
11791
11792                 offset += sizeof(v);
11793
11794                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11795                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11796                         break;
11797                 }
11798
11799                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11800                 vlen += sizeof(v);
11801         }
11802 }
11803
11804 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11805 {
11806         int vlen;
11807         u32 apedata;
11808
11809         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11810             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11811                 return;
11812
11813         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11814         if (apedata != APE_SEG_SIG_MAGIC)
11815                 return;
11816
11817         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11818         if (!(apedata & APE_FW_STATUS_READY))
11819                 return;
11820
11821         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11822
11823         vlen = strlen(tp->fw_ver);
11824
11825         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11826                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11827                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11828                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11829                  (apedata & APE_FW_VERSION_BLDMSK));
11830 }
11831
11832 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11833 {
11834         u32 val;
11835
11836         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11837                 tp->fw_ver[0] = 's';
11838                 tp->fw_ver[1] = 'b';
11839                 tp->fw_ver[2] = '\0';
11840
11841                 return;
11842         }
11843
11844         if (tg3_nvram_read(tp, 0, &val))
11845                 return;
11846
11847         if (val == TG3_EEPROM_MAGIC)
11848                 tg3_read_bc_ver(tp);
11849         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11850                 tg3_read_sb_ver(tp, val);
11851         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11852                 tg3_read_hwsb_ver(tp);
11853         else
11854                 return;
11855
11856         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11857              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11858                 return;
11859
11860         tg3_read_mgmtfw_ver(tp);
11861
11862         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11863 }
11864
11865 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11866
11867 static int __devinit tg3_get_invariants(struct tg3 *tp)
11868 {
11869         static struct pci_device_id write_reorder_chipsets[] = {
11870                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11871                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11872                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11873                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11874                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11875                              PCI_DEVICE_ID_VIA_8385_0) },
11876                 { },
11877         };
11878         u32 misc_ctrl_reg;
11879         u32 pci_state_reg, grc_misc_cfg;
11880         u32 val;
11881         u16 pci_cmd;
11882         int err;
11883
11884         /* Force memory write invalidate off.  If we leave it on,
11885          * then on 5700_BX chips we have to enable a workaround.
11886          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11887          * to match the cacheline size.  The Broadcom driver have this
11888          * workaround but turns MWI off all the times so never uses
11889          * it.  This seems to suggest that the workaround is insufficient.
11890          */
11891         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11892         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11893         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11894
11895         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11896          * has the register indirect write enable bit set before
11897          * we try to access any of the MMIO registers.  It is also
11898          * critical that the PCI-X hw workaround situation is decided
11899          * before that as well.
11900          */
11901         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11902                               &misc_ctrl_reg);
11903
11904         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11905                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11906         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11907                 u32 prod_id_asic_rev;
11908
11909                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11910                                       &prod_id_asic_rev);
11911                 tp->pci_chip_rev_id = prod_id_asic_rev;
11912         }
11913
11914         /* Wrong chip ID in 5752 A0. This code can be removed later
11915          * as A0 is not in production.
11916          */
11917         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11918                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11919
11920         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11921          * we need to disable memory and use config. cycles
11922          * only to access all registers. The 5702/03 chips
11923          * can mistakenly decode the special cycles from the
11924          * ICH chipsets as memory write cycles, causing corruption
11925          * of register and memory space. Only certain ICH bridges
11926          * will drive special cycles with non-zero data during the
11927          * address phase which can fall within the 5703's address
11928          * range. This is not an ICH bug as the PCI spec allows
11929          * non-zero address during special cycles. However, only
11930          * these ICH bridges are known to drive non-zero addresses
11931          * during special cycles.
11932          *
11933          * Since special cycles do not cross PCI bridges, we only
11934          * enable this workaround if the 5703 is on the secondary
11935          * bus of these ICH bridges.
11936          */
11937         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11938             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11939                 static struct tg3_dev_id {
11940                         u32     vendor;
11941                         u32     device;
11942                         u32     rev;
11943                 } ich_chipsets[] = {
11944                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11945                           PCI_ANY_ID },
11946                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11947                           PCI_ANY_ID },
11948                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11949                           0xa },
11950                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11951                           PCI_ANY_ID },
11952                         { },
11953                 };
11954                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11955                 struct pci_dev *bridge = NULL;
11956
11957                 while (pci_id->vendor != 0) {
11958                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11959                                                 bridge);
11960                         if (!bridge) {
11961                                 pci_id++;
11962                                 continue;
11963                         }
11964                         if (pci_id->rev != PCI_ANY_ID) {
11965                                 if (bridge->revision > pci_id->rev)
11966                                         continue;
11967                         }
11968                         if (bridge->subordinate &&
11969                             (bridge->subordinate->number ==
11970                              tp->pdev->bus->number)) {
11971
11972                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11973                                 pci_dev_put(bridge);
11974                                 break;
11975                         }
11976                 }
11977         }
11978
11979         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11980                 static struct tg3_dev_id {
11981                         u32     vendor;
11982                         u32     device;
11983                 } bridge_chipsets[] = {
11984                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11985                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11986                         { },
11987                 };
11988                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11989                 struct pci_dev *bridge = NULL;
11990
11991                 while (pci_id->vendor != 0) {
11992                         bridge = pci_get_device(pci_id->vendor,
11993                                                 pci_id->device,
11994                                                 bridge);
11995                         if (!bridge) {
11996                                 pci_id++;
11997                                 continue;
11998                         }
11999                         if (bridge->subordinate &&
12000                             (bridge->subordinate->number <=
12001                              tp->pdev->bus->number) &&
12002                             (bridge->subordinate->subordinate >=
12003                              tp->pdev->bus->number)) {
12004                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12005                                 pci_dev_put(bridge);
12006                                 break;
12007                         }
12008                 }
12009         }
12010
12011         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12012          * DMA addresses > 40-bit. This bridge may have other additional
12013          * 57xx devices behind it in some 4-port NIC designs for example.
12014          * Any tg3 device found behind the bridge will also need the 40-bit
12015          * DMA workaround.
12016          */
12017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12019                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12020                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12021                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12022         }
12023         else {
12024                 struct pci_dev *bridge = NULL;
12025
12026                 do {
12027                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12028                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12029                                                 bridge);
12030                         if (bridge && bridge->subordinate &&
12031                             (bridge->subordinate->number <=
12032                              tp->pdev->bus->number) &&
12033                             (bridge->subordinate->subordinate >=
12034                              tp->pdev->bus->number)) {
12035                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12036                                 pci_dev_put(bridge);
12037                                 break;
12038                         }
12039                 } while (bridge);
12040         }
12041
12042         /* Initialize misc host control in PCI block. */
12043         tp->misc_host_ctrl |= (misc_ctrl_reg &
12044                                MISC_HOST_CTRL_CHIPREV);
12045         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12046                                tp->misc_host_ctrl);
12047
12048         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12049             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12050                 tp->pdev_peer = tg3_find_peer(tp);
12051
12052         /* Intentionally exclude ASIC_REV_5906 */
12053         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12058             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12059                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12060
12061         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12062             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12063             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12064             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12065             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12066                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12067
12068         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12069             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12070                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12071
12072         /* 5700 B0 chips do not support checksumming correctly due
12073          * to hardware bugs.
12074          */
12075         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12076                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12077         else {
12078                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12079                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12080                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12081                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12082         }
12083
12084         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12085                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12086                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12087                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12088                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12089                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12090                      tp->pdev_peer == tp->pdev))
12091                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12092
12093                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12094                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12095                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12096                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12097                 } else {
12098                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12099                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12100                                 ASIC_REV_5750 &&
12101                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12102                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12103                 }
12104         }
12105
12106         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12107              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12108                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12109
12110         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12111                               &pci_state_reg);
12112
12113         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12114         if (tp->pcie_cap != 0) {
12115                 u16 lnkctl;
12116
12117                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12118
12119                 pcie_set_readrq(tp->pdev, 4096);
12120
12121                 pci_read_config_word(tp->pdev,
12122                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12123                                      &lnkctl);
12124                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12125                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12126                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12127                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12128                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12129                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12130                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12131                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12132                 }
12133         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12134                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12135         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12136                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12137                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12138                 if (!tp->pcix_cap) {
12139                         printk(KERN_ERR PFX "Cannot find PCI-X "
12140                                             "capability, aborting.\n");
12141                         return -EIO;
12142                 }
12143
12144                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12145                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12146         }
12147
12148         /* If we have an AMD 762 or VIA K8T800 chipset, write
12149          * reordering to the mailbox registers done by the host
12150          * controller can cause major troubles.  We read back from
12151          * every mailbox register write to force the writes to be
12152          * posted to the chip in order.
12153          */
12154         if (pci_dev_present(write_reorder_chipsets) &&
12155             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12156                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12157
12158         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12159                              &tp->pci_cacheline_sz);
12160         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12161                              &tp->pci_lat_timer);
12162         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12163             tp->pci_lat_timer < 64) {
12164                 tp->pci_lat_timer = 64;
12165                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12166                                       tp->pci_lat_timer);
12167         }
12168
12169         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12170                 /* 5700 BX chips need to have their TX producer index
12171                  * mailboxes written twice to workaround a bug.
12172                  */
12173                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12174
12175                 /* If we are in PCI-X mode, enable register write workaround.
12176                  *
12177                  * The workaround is to use indirect register accesses
12178                  * for all chip writes not to mailbox registers.
12179                  */
12180                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12181                         u32 pm_reg;
12182
12183                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12184
12185                         /* The chip can have it's power management PCI config
12186                          * space registers clobbered due to this bug.
12187                          * So explicitly force the chip into D0 here.
12188                          */
12189                         pci_read_config_dword(tp->pdev,
12190                                               tp->pm_cap + PCI_PM_CTRL,
12191                                               &pm_reg);
12192                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12193                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12194                         pci_write_config_dword(tp->pdev,
12195                                                tp->pm_cap + PCI_PM_CTRL,
12196                                                pm_reg);
12197
12198                         /* Also, force SERR#/PERR# in PCI command. */
12199                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12200                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12201                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12202                 }
12203         }
12204
12205         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12206                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12207         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12208                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12209
12210         /* Chip-specific fixup from Broadcom driver */
12211         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12212             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12213                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12214                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12215         }
12216
12217         /* Default fast path register access methods */
12218         tp->read32 = tg3_read32;
12219         tp->write32 = tg3_write32;
12220         tp->read32_mbox = tg3_read32;
12221         tp->write32_mbox = tg3_write32;
12222         tp->write32_tx_mbox = tg3_write32;
12223         tp->write32_rx_mbox = tg3_write32;
12224
12225         /* Various workaround register access methods */
12226         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12227                 tp->write32 = tg3_write_indirect_reg32;
12228         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12229                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12230                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12231                 /*
12232                  * Back to back register writes can cause problems on these
12233                  * chips, the workaround is to read back all reg writes
12234                  * except those to mailbox regs.
12235                  *
12236                  * See tg3_write_indirect_reg32().
12237                  */
12238                 tp->write32 = tg3_write_flush_reg32;
12239         }
12240
12241
12242         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12243             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12244                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12245                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12246                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12247         }
12248
12249         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12250                 tp->read32 = tg3_read_indirect_reg32;
12251                 tp->write32 = tg3_write_indirect_reg32;
12252                 tp->read32_mbox = tg3_read_indirect_mbox;
12253                 tp->write32_mbox = tg3_write_indirect_mbox;
12254                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12255                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12256
12257                 iounmap(tp->regs);
12258                 tp->regs = NULL;
12259
12260                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12261                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12262                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12263         }
12264         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12265                 tp->read32_mbox = tg3_read32_mbox_5906;
12266                 tp->write32_mbox = tg3_write32_mbox_5906;
12267                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12268                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12269         }
12270
12271         if (tp->write32 == tg3_write_indirect_reg32 ||
12272             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12273              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12274               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12275                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12276
12277         /* Get eeprom hw config before calling tg3_set_power_state().
12278          * In particular, the TG3_FLG2_IS_NIC flag must be
12279          * determined before calling tg3_set_power_state() so that
12280          * we know whether or not to switch out of Vaux power.
12281          * When the flag is set, it means that GPIO1 is used for eeprom
12282          * write protect and also implies that it is a LOM where GPIOs
12283          * are not used to switch power.
12284          */
12285         tg3_get_eeprom_hw_cfg(tp);
12286
12287         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12288                 /* Allow reads and writes to the
12289                  * APE register and memory space.
12290                  */
12291                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12292                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12293                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12294                                        pci_state_reg);
12295         }
12296
12297         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12298             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12299             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12300             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12301                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12302
12303         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12304          * GPIO1 driven high will bring 5700's external PHY out of reset.
12305          * It is also used as eeprom write protect on LOMs.
12306          */
12307         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12308         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12309             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12310                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12311                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12312         /* Unused GPIO3 must be driven as output on 5752 because there
12313          * are no pull-up resistors on unused GPIO pins.
12314          */
12315         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12316                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12317
12318         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12319             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12320                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12321
12322         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12323             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12324                 /* Turn off the debug UART. */
12325                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12326                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12327                         /* Keep VMain power. */
12328                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12329                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12330         }
12331
12332         /* Force the chip into D0. */
12333         err = tg3_set_power_state(tp, PCI_D0);
12334         if (err) {
12335                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12336                        pci_name(tp->pdev));
12337                 return err;
12338         }
12339
12340         /* Derive initial jumbo mode from MTU assigned in
12341          * ether_setup() via the alloc_etherdev() call
12342          */
12343         if (tp->dev->mtu > ETH_DATA_LEN &&
12344             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12345                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12346
12347         /* Determine WakeOnLan speed to use. */
12348         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12349             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12350             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12351             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12352                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12353         } else {
12354                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12355         }
12356
12357         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12358                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12359
12360         /* A few boards don't want Ethernet@WireSpeed phy feature */
12361         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12362             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12363              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12364              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12365             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12366             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12367                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12368
12369         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12370             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12371                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12372         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12373                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12374
12375         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12376             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12377             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12378             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12379                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12380                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12381                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12382                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12383                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12384                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12385                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12386                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12387                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12388                 } else
12389                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12390         }
12391
12392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12393             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12394                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12395                 if (tp->phy_otp == 0)
12396                         tp->phy_otp = TG3_OTP_DEFAULT;
12397         }
12398
12399         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12400                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12401         else
12402                 tp->mi_mode = MAC_MI_MODE_BASE;
12403
12404         tp->coalesce_mode = 0;
12405         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12406             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12407                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12408
12409         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12410             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12411                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12412
12413         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12414              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12415             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12416                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12417
12418         err = tg3_mdio_init(tp);
12419         if (err)
12420                 return err;
12421
12422         /* Initialize data/descriptor byte/word swapping. */
12423         val = tr32(GRC_MODE);
12424         val &= GRC_MODE_HOST_STACKUP;
12425         tw32(GRC_MODE, val | tp->grc_mode);
12426
12427         tg3_switch_clocks(tp);
12428
12429         /* Clear this out for sanity. */
12430         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12431
12432         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12433                               &pci_state_reg);
12434         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12435             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12436                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12437
12438                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12439                     chiprevid == CHIPREV_ID_5701_B0 ||
12440                     chiprevid == CHIPREV_ID_5701_B2 ||
12441                     chiprevid == CHIPREV_ID_5701_B5) {
12442                         void __iomem *sram_base;
12443
12444                         /* Write some dummy words into the SRAM status block
12445                          * area, see if it reads back correctly.  If the return
12446                          * value is bad, force enable the PCIX workaround.
12447                          */
12448                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12449
12450                         writel(0x00000000, sram_base);
12451                         writel(0x00000000, sram_base + 4);
12452                         writel(0xffffffff, sram_base + 4);
12453                         if (readl(sram_base) != 0x00000000)
12454                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12455                 }
12456         }
12457
12458         udelay(50);
12459         tg3_nvram_init(tp);
12460
12461         grc_misc_cfg = tr32(GRC_MISC_CFG);
12462         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12463
12464         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12465             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12466              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12467                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12468
12469         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12470             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12471                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12472         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12473                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12474                                       HOSTCC_MODE_CLRTICK_TXBD);
12475
12476                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12477                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12478                                        tp->misc_host_ctrl);
12479         }
12480
12481         /* Preserve the APE MAC_MODE bits */
12482         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12483                 tp->mac_mode = tr32(MAC_MODE) |
12484                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12485         else
12486                 tp->mac_mode = TG3_DEF_MAC_MODE;
12487
12488         /* these are limited to 10/100 only */
12489         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12490              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12491             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12492              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12493              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12494               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12495               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12496             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12497              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12498               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12499               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12500             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12501             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12502                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12503
12504         err = tg3_phy_probe(tp);
12505         if (err) {
12506                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12507                        pci_name(tp->pdev), err);
12508                 /* ... but do not return immediately ... */
12509                 tg3_mdio_fini(tp);
12510         }
12511
12512         tg3_read_partno(tp);
12513         tg3_read_fw_ver(tp);
12514
12515         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12516                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12517         } else {
12518                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12519                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12520                 else
12521                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12522         }
12523
12524         /* 5700 {AX,BX} chips have a broken status block link
12525          * change bit implementation, so we must use the
12526          * status register in those cases.
12527          */
12528         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12529                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12530         else
12531                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12532
12533         /* The led_ctrl is set during tg3_phy_probe, here we might
12534          * have to force the link status polling mechanism based
12535          * upon subsystem IDs.
12536          */
12537         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12538             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12539             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12540                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12541                                   TG3_FLAG_USE_LINKCHG_REG);
12542         }
12543
12544         /* For all SERDES we poll the MAC status register. */
12545         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12546                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12547         else
12548                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12549
12550         tp->rx_offset = NET_IP_ALIGN;
12551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12552             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12553                 tp->rx_offset = 0;
12554
12555         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12556
12557         /* Increment the rx prod index on the rx std ring by at most
12558          * 8 for these chips to workaround hw errata.
12559          */
12560         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12562             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12563                 tp->rx_std_max_post = 8;
12564
12565         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12566                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12567                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12568
12569         return err;
12570 }
12571
12572 #ifdef CONFIG_SPARC
12573 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12574 {
12575         struct net_device *dev = tp->dev;
12576         struct pci_dev *pdev = tp->pdev;
12577         struct device_node *dp = pci_device_to_OF_node(pdev);
12578         const unsigned char *addr;
12579         int len;
12580
12581         addr = of_get_property(dp, "local-mac-address", &len);
12582         if (addr && len == 6) {
12583                 memcpy(dev->dev_addr, addr, 6);
12584                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12585                 return 0;
12586         }
12587         return -ENODEV;
12588 }
12589
12590 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12591 {
12592         struct net_device *dev = tp->dev;
12593
12594         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12595         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12596         return 0;
12597 }
12598 #endif
12599
12600 static int __devinit tg3_get_device_address(struct tg3 *tp)
12601 {
12602         struct net_device *dev = tp->dev;
12603         u32 hi, lo, mac_offset;
12604         int addr_ok = 0;
12605
12606 #ifdef CONFIG_SPARC
12607         if (!tg3_get_macaddr_sparc(tp))
12608                 return 0;
12609 #endif
12610
12611         mac_offset = 0x7c;
12612         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12613             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12614                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12615                         mac_offset = 0xcc;
12616                 if (tg3_nvram_lock(tp))
12617                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12618                 else
12619                         tg3_nvram_unlock(tp);
12620         }
12621         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12622                 mac_offset = 0x10;
12623
12624         /* First try to get it from MAC address mailbox. */
12625         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12626         if ((hi >> 16) == 0x484b) {
12627                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12628                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12629
12630                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12631                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12632                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12633                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12634                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12635
12636                 /* Some old bootcode may report a 0 MAC address in SRAM */
12637                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12638         }
12639         if (!addr_ok) {
12640                 /* Next, try NVRAM. */
12641                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12642                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12643                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12644                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12645                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12646                 }
12647                 /* Finally just fetch it out of the MAC control regs. */
12648                 else {
12649                         hi = tr32(MAC_ADDR_0_HIGH);
12650                         lo = tr32(MAC_ADDR_0_LOW);
12651
12652                         dev->dev_addr[5] = lo & 0xff;
12653                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12654                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12655                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12656                         dev->dev_addr[1] = hi & 0xff;
12657                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12658                 }
12659         }
12660
12661         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12662 #ifdef CONFIG_SPARC
12663                 if (!tg3_get_default_macaddr_sparc(tp))
12664                         return 0;
12665 #endif
12666                 return -EINVAL;
12667         }
12668         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12669         return 0;
12670 }
12671
12672 #define BOUNDARY_SINGLE_CACHELINE       1
12673 #define BOUNDARY_MULTI_CACHELINE        2
12674
12675 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12676 {
12677         int cacheline_size;
12678         u8 byte;
12679         int goal;
12680
12681         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12682         if (byte == 0)
12683                 cacheline_size = 1024;
12684         else
12685                 cacheline_size = (int) byte * 4;
12686
12687         /* On 5703 and later chips, the boundary bits have no
12688          * effect.
12689          */
12690         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12691             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12692             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12693                 goto out;
12694
12695 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12696         goal = BOUNDARY_MULTI_CACHELINE;
12697 #else
12698 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12699         goal = BOUNDARY_SINGLE_CACHELINE;
12700 #else
12701         goal = 0;
12702 #endif
12703 #endif
12704
12705         if (!goal)
12706                 goto out;
12707
12708         /* PCI controllers on most RISC systems tend to disconnect
12709          * when a device tries to burst across a cache-line boundary.
12710          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12711          *
12712          * Unfortunately, for PCI-E there are only limited
12713          * write-side controls for this, and thus for reads
12714          * we will still get the disconnects.  We'll also waste
12715          * these PCI cycles for both read and write for chips
12716          * other than 5700 and 5701 which do not implement the
12717          * boundary bits.
12718          */
12719         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12720             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12721                 switch (cacheline_size) {
12722                 case 16:
12723                 case 32:
12724                 case 64:
12725                 case 128:
12726                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12727                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12728                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12729                         } else {
12730                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12731                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12732                         }
12733                         break;
12734
12735                 case 256:
12736                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12737                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12738                         break;
12739
12740                 default:
12741                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12742                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12743                         break;
12744                 }
12745         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12746                 switch (cacheline_size) {
12747                 case 16:
12748                 case 32:
12749                 case 64:
12750                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12751                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12752                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12753                                 break;
12754                         }
12755                         /* fallthrough */
12756                 case 128:
12757                 default:
12758                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12759                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12760                         break;
12761                 }
12762         } else {
12763                 switch (cacheline_size) {
12764                 case 16:
12765                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12766                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12767                                         DMA_RWCTRL_WRITE_BNDRY_16);
12768                                 break;
12769                         }
12770                         /* fallthrough */
12771                 case 32:
12772                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12773                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12774                                         DMA_RWCTRL_WRITE_BNDRY_32);
12775                                 break;
12776                         }
12777                         /* fallthrough */
12778                 case 64:
12779                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12780                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12781                                         DMA_RWCTRL_WRITE_BNDRY_64);
12782                                 break;
12783                         }
12784                         /* fallthrough */
12785                 case 128:
12786                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12787                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12788                                         DMA_RWCTRL_WRITE_BNDRY_128);
12789                                 break;
12790                         }
12791                         /* fallthrough */
12792                 case 256:
12793                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12794                                 DMA_RWCTRL_WRITE_BNDRY_256);
12795                         break;
12796                 case 512:
12797                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12798                                 DMA_RWCTRL_WRITE_BNDRY_512);
12799                         break;
12800                 case 1024:
12801                 default:
12802                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12803                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12804                         break;
12805                 }
12806         }
12807
12808 out:
12809         return val;
12810 }
12811
12812 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12813 {
12814         struct tg3_internal_buffer_desc test_desc;
12815         u32 sram_dma_descs;
12816         int i, ret;
12817
12818         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12819
12820         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12821         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12822         tw32(RDMAC_STATUS, 0);
12823         tw32(WDMAC_STATUS, 0);
12824
12825         tw32(BUFMGR_MODE, 0);
12826         tw32(FTQ_RESET, 0);
12827
12828         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12829         test_desc.addr_lo = buf_dma & 0xffffffff;
12830         test_desc.nic_mbuf = 0x00002100;
12831         test_desc.len = size;
12832
12833         /*
12834          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12835          * the *second* time the tg3 driver was getting loaded after an
12836          * initial scan.
12837          *
12838          * Broadcom tells me:
12839          *   ...the DMA engine is connected to the GRC block and a DMA
12840          *   reset may affect the GRC block in some unpredictable way...
12841          *   The behavior of resets to individual blocks has not been tested.
12842          *
12843          * Broadcom noted the GRC reset will also reset all sub-components.
12844          */
12845         if (to_device) {
12846                 test_desc.cqid_sqid = (13 << 8) | 2;
12847
12848                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12849                 udelay(40);
12850         } else {
12851                 test_desc.cqid_sqid = (16 << 8) | 7;
12852
12853                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12854                 udelay(40);
12855         }
12856         test_desc.flags = 0x00000005;
12857
12858         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12859                 u32 val;
12860
12861                 val = *(((u32 *)&test_desc) + i);
12862                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12863                                        sram_dma_descs + (i * sizeof(u32)));
12864                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12865         }
12866         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12867
12868         if (to_device) {
12869                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12870         } else {
12871                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12872         }
12873
12874         ret = -ENODEV;
12875         for (i = 0; i < 40; i++) {
12876                 u32 val;
12877
12878                 if (to_device)
12879                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12880                 else
12881                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12882                 if ((val & 0xffff) == sram_dma_descs) {
12883                         ret = 0;
12884                         break;
12885                 }
12886
12887                 udelay(100);
12888         }
12889
12890         return ret;
12891 }
12892
12893 #define TEST_BUFFER_SIZE        0x2000
12894
12895 static int __devinit tg3_test_dma(struct tg3 *tp)
12896 {
12897         dma_addr_t buf_dma;
12898         u32 *buf, saved_dma_rwctrl;
12899         int ret;
12900
12901         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12902         if (!buf) {
12903                 ret = -ENOMEM;
12904                 goto out_nofree;
12905         }
12906
12907         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12908                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12909
12910         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12911
12912         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12913                 /* DMA read watermark not used on PCIE */
12914                 tp->dma_rwctrl |= 0x00180000;
12915         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12916                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12917                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12918                         tp->dma_rwctrl |= 0x003f0000;
12919                 else
12920                         tp->dma_rwctrl |= 0x003f000f;
12921         } else {
12922                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12923                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12924                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12925                         u32 read_water = 0x7;
12926
12927                         /* If the 5704 is behind the EPB bridge, we can
12928                          * do the less restrictive ONE_DMA workaround for
12929                          * better performance.
12930                          */
12931                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12932                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12933                                 tp->dma_rwctrl |= 0x8000;
12934                         else if (ccval == 0x6 || ccval == 0x7)
12935                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12936
12937                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12938                                 read_water = 4;
12939                         /* Set bit 23 to enable PCIX hw bug fix */
12940                         tp->dma_rwctrl |=
12941                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12942                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12943                                 (1 << 23);
12944                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12945                         /* 5780 always in PCIX mode */
12946                         tp->dma_rwctrl |= 0x00144000;
12947                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12948                         /* 5714 always in PCIX mode */
12949                         tp->dma_rwctrl |= 0x00148000;
12950                 } else {
12951                         tp->dma_rwctrl |= 0x001b000f;
12952                 }
12953         }
12954
12955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12957                 tp->dma_rwctrl &= 0xfffffff0;
12958
12959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12960             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12961                 /* Remove this if it causes problems for some boards. */
12962                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12963
12964                 /* On 5700/5701 chips, we need to set this bit.
12965                  * Otherwise the chip will issue cacheline transactions
12966                  * to streamable DMA memory with not all the byte
12967                  * enables turned on.  This is an error on several
12968                  * RISC PCI controllers, in particular sparc64.
12969                  *
12970                  * On 5703/5704 chips, this bit has been reassigned
12971                  * a different meaning.  In particular, it is used
12972                  * on those chips to enable a PCI-X workaround.
12973                  */
12974                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12975         }
12976
12977         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12978
12979 #if 0
12980         /* Unneeded, already done by tg3_get_invariants.  */
12981         tg3_switch_clocks(tp);
12982 #endif
12983
12984         ret = 0;
12985         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12986             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12987                 goto out;
12988
12989         /* It is best to perform DMA test with maximum write burst size
12990          * to expose the 5700/5701 write DMA bug.
12991          */
12992         saved_dma_rwctrl = tp->dma_rwctrl;
12993         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12994         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12995
12996         while (1) {
12997                 u32 *p = buf, i;
12998
12999                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13000                         p[i] = i;
13001
13002                 /* Send the buffer to the chip. */
13003                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13004                 if (ret) {
13005                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13006                         break;
13007                 }
13008
13009 #if 0
13010                 /* validate data reached card RAM correctly. */
13011                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13012                         u32 val;
13013                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13014                         if (le32_to_cpu(val) != p[i]) {
13015                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13016                                 /* ret = -ENODEV here? */
13017                         }
13018                         p[i] = 0;
13019                 }
13020 #endif
13021                 /* Now read it back. */
13022                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13023                 if (ret) {
13024                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13025
13026                         break;
13027                 }
13028
13029                 /* Verify it. */
13030                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13031                         if (p[i] == i)
13032                                 continue;
13033
13034                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13035                             DMA_RWCTRL_WRITE_BNDRY_16) {
13036                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13037                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13038                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13039                                 break;
13040                         } else {
13041                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13042                                 ret = -ENODEV;
13043                                 goto out;
13044                         }
13045                 }
13046
13047                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13048                         /* Success. */
13049                         ret = 0;
13050                         break;
13051                 }
13052         }
13053         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13054             DMA_RWCTRL_WRITE_BNDRY_16) {
13055                 static struct pci_device_id dma_wait_state_chipsets[] = {
13056                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13057                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13058                         { },
13059                 };
13060
13061                 /* DMA test passed without adjusting DMA boundary,
13062                  * now look for chipsets that are known to expose the
13063                  * DMA bug without failing the test.
13064                  */
13065                 if (pci_dev_present(dma_wait_state_chipsets)) {
13066                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13067                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13068                 }
13069                 else
13070                         /* Safe to use the calculated DMA boundary. */
13071                         tp->dma_rwctrl = saved_dma_rwctrl;
13072
13073                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13074         }
13075
13076 out:
13077         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13078 out_nofree:
13079         return ret;
13080 }
13081
13082 static void __devinit tg3_init_link_config(struct tg3 *tp)
13083 {
13084         tp->link_config.advertising =
13085                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13086                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13087                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13088                  ADVERTISED_Autoneg | ADVERTISED_MII);
13089         tp->link_config.speed = SPEED_INVALID;
13090         tp->link_config.duplex = DUPLEX_INVALID;
13091         tp->link_config.autoneg = AUTONEG_ENABLE;
13092         tp->link_config.active_speed = SPEED_INVALID;
13093         tp->link_config.active_duplex = DUPLEX_INVALID;
13094         tp->link_config.phy_is_low_power = 0;
13095         tp->link_config.orig_speed = SPEED_INVALID;
13096         tp->link_config.orig_duplex = DUPLEX_INVALID;
13097         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13098 }
13099
13100 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13101 {
13102         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13103                 tp->bufmgr_config.mbuf_read_dma_low_water =
13104                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13105                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13106                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13107                 tp->bufmgr_config.mbuf_high_water =
13108                         DEFAULT_MB_HIGH_WATER_5705;
13109                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13110                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13111                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13112                         tp->bufmgr_config.mbuf_high_water =
13113                                 DEFAULT_MB_HIGH_WATER_5906;
13114                 }
13115
13116                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13117                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13118                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13119                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13120                 tp->bufmgr_config.mbuf_high_water_jumbo =
13121                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13122         } else {
13123                 tp->bufmgr_config.mbuf_read_dma_low_water =
13124                         DEFAULT_MB_RDMA_LOW_WATER;
13125                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13126                         DEFAULT_MB_MACRX_LOW_WATER;
13127                 tp->bufmgr_config.mbuf_high_water =
13128                         DEFAULT_MB_HIGH_WATER;
13129
13130                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13131                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13132                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13133                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13134                 tp->bufmgr_config.mbuf_high_water_jumbo =
13135                         DEFAULT_MB_HIGH_WATER_JUMBO;
13136         }
13137
13138         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13139         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13140 }
13141
13142 static char * __devinit tg3_phy_string(struct tg3 *tp)
13143 {
13144         switch (tp->phy_id & PHY_ID_MASK) {
13145         case PHY_ID_BCM5400:    return "5400";
13146         case PHY_ID_BCM5401:    return "5401";
13147         case PHY_ID_BCM5411:    return "5411";
13148         case PHY_ID_BCM5701:    return "5701";
13149         case PHY_ID_BCM5703:    return "5703";
13150         case PHY_ID_BCM5704:    return "5704";
13151         case PHY_ID_BCM5705:    return "5705";
13152         case PHY_ID_BCM5750:    return "5750";
13153         case PHY_ID_BCM5752:    return "5752";
13154         case PHY_ID_BCM5714:    return "5714";
13155         case PHY_ID_BCM5780:    return "5780";
13156         case PHY_ID_BCM5755:    return "5755";
13157         case PHY_ID_BCM5787:    return "5787";
13158         case PHY_ID_BCM5784:    return "5784";
13159         case PHY_ID_BCM5756:    return "5722/5756";
13160         case PHY_ID_BCM5906:    return "5906";
13161         case PHY_ID_BCM5761:    return "5761";
13162         case PHY_ID_BCM8002:    return "8002/serdes";
13163         case 0:                 return "serdes";
13164         default:                return "unknown";
13165         }
13166 }
13167
13168 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13169 {
13170         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13171                 strcpy(str, "PCI Express");
13172                 return str;
13173         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13174                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13175
13176                 strcpy(str, "PCIX:");
13177
13178                 if ((clock_ctrl == 7) ||
13179                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13180                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13181                         strcat(str, "133MHz");
13182                 else if (clock_ctrl == 0)
13183                         strcat(str, "33MHz");
13184                 else if (clock_ctrl == 2)
13185                         strcat(str, "50MHz");
13186                 else if (clock_ctrl == 4)
13187                         strcat(str, "66MHz");
13188                 else if (clock_ctrl == 6)
13189                         strcat(str, "100MHz");
13190         } else {
13191                 strcpy(str, "PCI:");
13192                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13193                         strcat(str, "66MHz");
13194                 else
13195                         strcat(str, "33MHz");
13196         }
13197         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13198                 strcat(str, ":32-bit");
13199         else
13200                 strcat(str, ":64-bit");
13201         return str;
13202 }
13203
13204 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13205 {
13206         struct pci_dev *peer;
13207         unsigned int func, devnr = tp->pdev->devfn & ~7;
13208
13209         for (func = 0; func < 8; func++) {
13210                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13211                 if (peer && peer != tp->pdev)
13212                         break;
13213                 pci_dev_put(peer);
13214         }
13215         /* 5704 can be configured in single-port mode, set peer to
13216          * tp->pdev in that case.
13217          */
13218         if (!peer) {
13219                 peer = tp->pdev;
13220                 return peer;
13221         }
13222
13223         /*
13224          * We don't need to keep the refcount elevated; there's no way
13225          * to remove one half of this device without removing the other
13226          */
13227         pci_dev_put(peer);
13228
13229         return peer;
13230 }
13231
13232 static void __devinit tg3_init_coal(struct tg3 *tp)
13233 {
13234         struct ethtool_coalesce *ec = &tp->coal;
13235
13236         memset(ec, 0, sizeof(*ec));
13237         ec->cmd = ETHTOOL_GCOALESCE;
13238         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13239         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13240         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13241         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13242         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13243         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13244         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13245         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13246         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13247
13248         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13249                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13250                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13251                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13252                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13253                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13254         }
13255
13256         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13257                 ec->rx_coalesce_usecs_irq = 0;
13258                 ec->tx_coalesce_usecs_irq = 0;
13259                 ec->stats_block_coalesce_usecs = 0;
13260         }
13261 }
13262
13263 static const struct net_device_ops tg3_netdev_ops = {
13264         .ndo_open               = tg3_open,
13265         .ndo_stop               = tg3_close,
13266         .ndo_start_xmit         = tg3_start_xmit,
13267         .ndo_get_stats          = tg3_get_stats,
13268         .ndo_validate_addr      = eth_validate_addr,
13269         .ndo_set_multicast_list = tg3_set_rx_mode,
13270         .ndo_set_mac_address    = tg3_set_mac_addr,
13271         .ndo_do_ioctl           = tg3_ioctl,
13272         .ndo_tx_timeout         = tg3_tx_timeout,
13273         .ndo_change_mtu         = tg3_change_mtu,
13274 #if TG3_VLAN_TAG_USED
13275         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13276 #endif
13277 #ifdef CONFIG_NET_POLL_CONTROLLER
13278         .ndo_poll_controller    = tg3_poll_controller,
13279 #endif
13280 };
13281
13282 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13283         .ndo_open               = tg3_open,
13284         .ndo_stop               = tg3_close,
13285         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13286         .ndo_get_stats          = tg3_get_stats,
13287         .ndo_validate_addr      = eth_validate_addr,
13288         .ndo_set_multicast_list = tg3_set_rx_mode,
13289         .ndo_set_mac_address    = tg3_set_mac_addr,
13290         .ndo_do_ioctl           = tg3_ioctl,
13291         .ndo_tx_timeout         = tg3_tx_timeout,
13292         .ndo_change_mtu         = tg3_change_mtu,
13293 #if TG3_VLAN_TAG_USED
13294         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13295 #endif
13296 #ifdef CONFIG_NET_POLL_CONTROLLER
13297         .ndo_poll_controller    = tg3_poll_controller,
13298 #endif
13299 };
13300
13301 static int __devinit tg3_init_one(struct pci_dev *pdev,
13302                                   const struct pci_device_id *ent)
13303 {
13304         static int tg3_version_printed = 0;
13305         struct net_device *dev;
13306         struct tg3 *tp;
13307         int err, pm_cap;
13308         char str[40];
13309         u64 dma_mask, persist_dma_mask;
13310
13311         if (tg3_version_printed++ == 0)
13312                 printk(KERN_INFO "%s", version);
13313
13314         err = pci_enable_device(pdev);
13315         if (err) {
13316                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13317                        "aborting.\n");
13318                 return err;
13319         }
13320
13321         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13322         if (err) {
13323                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13324                        "aborting.\n");
13325                 goto err_out_disable_pdev;
13326         }
13327
13328         pci_set_master(pdev);
13329
13330         /* Find power-management capability. */
13331         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13332         if (pm_cap == 0) {
13333                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13334                        "aborting.\n");
13335                 err = -EIO;
13336                 goto err_out_free_res;
13337         }
13338
13339         dev = alloc_etherdev(sizeof(*tp));
13340         if (!dev) {
13341                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13342                 err = -ENOMEM;
13343                 goto err_out_free_res;
13344         }
13345
13346         SET_NETDEV_DEV(dev, &pdev->dev);
13347
13348 #if TG3_VLAN_TAG_USED
13349         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13350 #endif
13351
13352         tp = netdev_priv(dev);
13353         tp->pdev = pdev;
13354         tp->dev = dev;
13355         tp->pm_cap = pm_cap;
13356         tp->rx_mode = TG3_DEF_RX_MODE;
13357         tp->tx_mode = TG3_DEF_TX_MODE;
13358
13359         if (tg3_debug > 0)
13360                 tp->msg_enable = tg3_debug;
13361         else
13362                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13363
13364         /* The word/byte swap controls here control register access byte
13365          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13366          * setting below.
13367          */
13368         tp->misc_host_ctrl =
13369                 MISC_HOST_CTRL_MASK_PCI_INT |
13370                 MISC_HOST_CTRL_WORD_SWAP |
13371                 MISC_HOST_CTRL_INDIR_ACCESS |
13372                 MISC_HOST_CTRL_PCISTATE_RW;
13373
13374         /* The NONFRM (non-frame) byte/word swap controls take effect
13375          * on descriptor entries, anything which isn't packet data.
13376          *
13377          * The StrongARM chips on the board (one for tx, one for rx)
13378          * are running in big-endian mode.
13379          */
13380         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13381                         GRC_MODE_WSWAP_NONFRM_DATA);
13382 #ifdef __BIG_ENDIAN
13383         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13384 #endif
13385         spin_lock_init(&tp->lock);
13386         spin_lock_init(&tp->indirect_lock);
13387         INIT_WORK(&tp->reset_task, tg3_reset_task);
13388
13389         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13390         if (!tp->regs) {
13391                 printk(KERN_ERR PFX "Cannot map device registers, "
13392                        "aborting.\n");
13393                 err = -ENOMEM;
13394                 goto err_out_free_dev;
13395         }
13396
13397         tg3_init_link_config(tp);
13398
13399         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13400         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13401         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13402
13403         tp->napi[0].tp = tp;
13404         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13405         dev->ethtool_ops = &tg3_ethtool_ops;
13406         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13407         dev->irq = pdev->irq;
13408
13409         err = tg3_get_invariants(tp);
13410         if (err) {
13411                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13412                        "aborting.\n");
13413                 goto err_out_iounmap;
13414         }
13415
13416         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13417             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13418                 dev->netdev_ops = &tg3_netdev_ops;
13419         else
13420                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13421
13422
13423         /* The EPB bridge inside 5714, 5715, and 5780 and any
13424          * device behind the EPB cannot support DMA addresses > 40-bit.
13425          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13426          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13427          * do DMA address check in tg3_start_xmit().
13428          */
13429         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13430                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13431         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13432                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13433 #ifdef CONFIG_HIGHMEM
13434                 dma_mask = DMA_BIT_MASK(64);
13435 #endif
13436         } else
13437                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13438
13439         /* Configure DMA attributes. */
13440         if (dma_mask > DMA_BIT_MASK(32)) {
13441                 err = pci_set_dma_mask(pdev, dma_mask);
13442                 if (!err) {
13443                         dev->features |= NETIF_F_HIGHDMA;
13444                         err = pci_set_consistent_dma_mask(pdev,
13445                                                           persist_dma_mask);
13446                         if (err < 0) {
13447                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13448                                        "DMA for consistent allocations\n");
13449                                 goto err_out_iounmap;
13450                         }
13451                 }
13452         }
13453         if (err || dma_mask == DMA_BIT_MASK(32)) {
13454                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13455                 if (err) {
13456                         printk(KERN_ERR PFX "No usable DMA configuration, "
13457                                "aborting.\n");
13458                         goto err_out_iounmap;
13459                 }
13460         }
13461
13462         tg3_init_bufmgr_config(tp);
13463
13464         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13465                 tp->fw_needed = FIRMWARE_TG3;
13466
13467         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13468                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13469         }
13470         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13471             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13472             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13473             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13474             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13475                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13476         } else {
13477                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13478                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13479                         tp->fw_needed = FIRMWARE_TG3TSO5;
13480                 else
13481                         tp->fw_needed = FIRMWARE_TG3TSO;
13482         }
13483
13484         /* TSO is on by default on chips that support hardware TSO.
13485          * Firmware TSO on older chips gives lower performance, so it
13486          * is off by default, but can be enabled using ethtool.
13487          */
13488         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13489                 if (dev->features & NETIF_F_IP_CSUM)
13490                         dev->features |= NETIF_F_TSO;
13491                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13492                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13493                         dev->features |= NETIF_F_TSO6;
13494                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13495                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13496                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13497                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13498                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13499                         dev->features |= NETIF_F_TSO_ECN;
13500         }
13501
13502
13503         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13504             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13505             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13506                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13507                 tp->rx_pending = 63;
13508         }
13509
13510         err = tg3_get_device_address(tp);
13511         if (err) {
13512                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13513                        "aborting.\n");
13514                 goto err_out_fw;
13515         }
13516
13517         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13518                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13519                 if (!tp->aperegs) {
13520                         printk(KERN_ERR PFX "Cannot map APE registers, "
13521                                "aborting.\n");
13522                         err = -ENOMEM;
13523                         goto err_out_fw;
13524                 }
13525
13526                 tg3_ape_lock_init(tp);
13527
13528                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13529                         tg3_read_dash_ver(tp);
13530         }
13531
13532         /*
13533          * Reset chip in case UNDI or EFI driver did not shutdown
13534          * DMA self test will enable WDMAC and we'll see (spurious)
13535          * pending DMA on the PCI bus at that point.
13536          */
13537         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13538             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13539                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13540                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13541         }
13542
13543         err = tg3_test_dma(tp);
13544         if (err) {
13545                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13546                 goto err_out_apeunmap;
13547         }
13548
13549         /* flow control autonegotiation is default behavior */
13550         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13551         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13552
13553         tg3_init_coal(tp);
13554
13555         pci_set_drvdata(pdev, dev);
13556
13557         err = register_netdev(dev);
13558         if (err) {
13559                 printk(KERN_ERR PFX "Cannot register net device, "
13560                        "aborting.\n");
13561                 goto err_out_apeunmap;
13562         }
13563
13564         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13565                dev->name,
13566                tp->board_part_number,
13567                tp->pci_chip_rev_id,
13568                tg3_bus_string(tp, str),
13569                dev->dev_addr);
13570
13571         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13572                 printk(KERN_INFO
13573                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13574                        tp->dev->name,
13575                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13576                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13577         else
13578                 printk(KERN_INFO
13579                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13580                        tp->dev->name, tg3_phy_string(tp),
13581                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13582                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13583                          "10/100/1000Base-T")),
13584                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13585
13586         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13587                dev->name,
13588                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13589                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13590                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13591                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13592                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13593         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13594                dev->name, tp->dma_rwctrl,
13595                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13596                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13597
13598         return 0;
13599
13600 err_out_apeunmap:
13601         if (tp->aperegs) {
13602                 iounmap(tp->aperegs);
13603                 tp->aperegs = NULL;
13604         }
13605
13606 err_out_fw:
13607         if (tp->fw)
13608                 release_firmware(tp->fw);
13609
13610 err_out_iounmap:
13611         if (tp->regs) {
13612                 iounmap(tp->regs);
13613                 tp->regs = NULL;
13614         }
13615
13616 err_out_free_dev:
13617         free_netdev(dev);
13618
13619 err_out_free_res:
13620         pci_release_regions(pdev);
13621
13622 err_out_disable_pdev:
13623         pci_disable_device(pdev);
13624         pci_set_drvdata(pdev, NULL);
13625         return err;
13626 }
13627
13628 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13629 {
13630         struct net_device *dev = pci_get_drvdata(pdev);
13631
13632         if (dev) {
13633                 struct tg3 *tp = netdev_priv(dev);
13634
13635                 if (tp->fw)
13636                         release_firmware(tp->fw);
13637
13638                 flush_scheduled_work();
13639
13640                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13641                         tg3_phy_fini(tp);
13642                         tg3_mdio_fini(tp);
13643                 }
13644
13645                 unregister_netdev(dev);
13646                 if (tp->aperegs) {
13647                         iounmap(tp->aperegs);
13648                         tp->aperegs = NULL;
13649                 }
13650                 if (tp->regs) {
13651                         iounmap(tp->regs);
13652                         tp->regs = NULL;
13653                 }
13654                 free_netdev(dev);
13655                 pci_release_regions(pdev);
13656                 pci_disable_device(pdev);
13657                 pci_set_drvdata(pdev, NULL);
13658         }
13659 }
13660
13661 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13662 {
13663         struct net_device *dev = pci_get_drvdata(pdev);
13664         struct tg3 *tp = netdev_priv(dev);
13665         pci_power_t target_state;
13666         int err;
13667
13668         /* PCI register 4 needs to be saved whether netif_running() or not.
13669          * MSI address and data need to be saved if using MSI and
13670          * netif_running().
13671          */
13672         pci_save_state(pdev);
13673
13674         if (!netif_running(dev))
13675                 return 0;
13676
13677         flush_scheduled_work();
13678         tg3_phy_stop(tp);
13679         tg3_netif_stop(tp);
13680
13681         del_timer_sync(&tp->timer);
13682
13683         tg3_full_lock(tp, 1);
13684         tg3_disable_ints(tp);
13685         tg3_full_unlock(tp);
13686
13687         netif_device_detach(dev);
13688
13689         tg3_full_lock(tp, 0);
13690         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13691         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13692         tg3_full_unlock(tp);
13693
13694         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13695
13696         err = tg3_set_power_state(tp, target_state);
13697         if (err) {
13698                 int err2;
13699
13700                 tg3_full_lock(tp, 0);
13701
13702                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13703                 err2 = tg3_restart_hw(tp, 1);
13704                 if (err2)
13705                         goto out;
13706
13707                 tp->timer.expires = jiffies + tp->timer_offset;
13708                 add_timer(&tp->timer);
13709
13710                 netif_device_attach(dev);
13711                 tg3_netif_start(tp);
13712
13713 out:
13714                 tg3_full_unlock(tp);
13715
13716                 if (!err2)
13717                         tg3_phy_start(tp);
13718         }
13719
13720         return err;
13721 }
13722
13723 static int tg3_resume(struct pci_dev *pdev)
13724 {
13725         struct net_device *dev = pci_get_drvdata(pdev);
13726         struct tg3 *tp = netdev_priv(dev);
13727         int err;
13728
13729         pci_restore_state(tp->pdev);
13730
13731         if (!netif_running(dev))
13732                 return 0;
13733
13734         err = tg3_set_power_state(tp, PCI_D0);
13735         if (err)
13736                 return err;
13737
13738         netif_device_attach(dev);
13739
13740         tg3_full_lock(tp, 0);
13741
13742         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13743         err = tg3_restart_hw(tp, 1);
13744         if (err)
13745                 goto out;
13746
13747         tp->timer.expires = jiffies + tp->timer_offset;
13748         add_timer(&tp->timer);
13749
13750         tg3_netif_start(tp);
13751
13752 out:
13753         tg3_full_unlock(tp);
13754
13755         if (!err)
13756                 tg3_phy_start(tp);
13757
13758         return err;
13759 }
13760
13761 static struct pci_driver tg3_driver = {
13762         .name           = DRV_MODULE_NAME,
13763         .id_table       = tg3_pci_tbl,
13764         .probe          = tg3_init_one,
13765         .remove         = __devexit_p(tg3_remove_one),
13766         .suspend        = tg3_suspend,
13767         .resume         = tg3_resume
13768 };
13769
13770 static int __init tg3_init(void)
13771 {
13772         return pci_register_driver(&tg3_driver);
13773 }
13774
13775 static void __exit tg3_cleanup(void)
13776 {
13777         pci_unregister_driver(&tg3_driver);
13778 }
13779
13780 module_init(tg3_init);
13781 module_exit(tg3_cleanup);