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   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2009 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.100"
  72 #define DRV_MODULE_RELDATE      "August 25, 2009"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                  TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define TG3_DMA_BYTE_ENAB               64
 129
 130 #define TG3_RX_STD_DMA_SZ               1536
 131 #define TG3_RX_JMB_DMA_SZ               9046
 132
 133 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 134
 135 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 136 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 137
 138 /* minimum number of free TX descriptors required to wake up TX process */
 139 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 140
 141 #define TG3_RAW_IP_ALIGN 2
 142
 143 /* number of ETHTOOL_GSTATS u64's */
 144 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 145
 146 #define TG3_NUM_TEST            6
 147
 148 #define FIRMWARE_TG3            "tigon/tg3.bin"
 149 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 150 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 151
 152 static char version[] __devinitdata =
 153         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 154
 155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 157 MODULE_LICENSE("GPL");
 158 MODULE_VERSION(DRV_MODULE_VERSION);
 159 MODULE_FIRMWARE(FIRMWARE_TG3);
 160 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 162
 163
 164 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 165 module_param(tg3_debug, int, 0);
 166 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 167
 168 static struct pci_device_id tg3_pci_tbl[] = {
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 242         {}
 243 };
 244
 245 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 246
 247 static const struct {
 248         const char string[ETH_GSTRING_LEN];
 249 } ethtool_stats_keys[TG3_NUM_STATS] = {
 250         { "rx_octets" },
 251         { "rx_fragments" },
 252         { "rx_ucast_packets" },
 253         { "rx_mcast_packets" },
 254         { "rx_bcast_packets" },
 255         { "rx_fcs_errors" },
 256         { "rx_align_errors" },
 257         { "rx_xon_pause_rcvd" },
 258         { "rx_xoff_pause_rcvd" },
 259         { "rx_mac_ctrl_rcvd" },
 260         { "rx_xoff_entered" },
 261         { "rx_frame_too_long_errors" },
 262         { "rx_jabbers" },
 263         { "rx_undersize_packets" },
 264         { "rx_in_length_errors" },
 265         { "rx_out_length_errors" },
 266         { "rx_64_or_less_octet_packets" },
 267         { "rx_65_to_127_octet_packets" },
 268         { "rx_128_to_255_octet_packets" },
 269         { "rx_256_to_511_octet_packets" },
 270         { "rx_512_to_1023_octet_packets" },
 271         { "rx_1024_to_1522_octet_packets" },
 272         { "rx_1523_to_2047_octet_packets" },
 273         { "rx_2048_to_4095_octet_packets" },
 274         { "rx_4096_to_8191_octet_packets" },
 275         { "rx_8192_to_9022_octet_packets" },
 276
 277         { "tx_octets" },
 278         { "tx_collisions" },
 279
 280         { "tx_xon_sent" },
 281         { "tx_xoff_sent" },
 282         { "tx_flow_control" },
 283         { "tx_mac_errors" },
 284         { "tx_single_collisions" },
 285         { "tx_mult_collisions" },
 286         { "tx_deferred" },
 287         { "tx_excessive_collisions" },
 288         { "tx_late_collisions" },
 289         { "tx_collide_2times" },
 290         { "tx_collide_3times" },
 291         { "tx_collide_4times" },
 292         { "tx_collide_5times" },
 293         { "tx_collide_6times" },
 294         { "tx_collide_7times" },
 295         { "tx_collide_8times" },
 296         { "tx_collide_9times" },
 297         { "tx_collide_10times" },
 298         { "tx_collide_11times" },
 299         { "tx_collide_12times" },
 300         { "tx_collide_13times" },
 301         { "tx_collide_14times" },
 302         { "tx_collide_15times" },
 303         { "tx_ucast_packets" },
 304         { "tx_mcast_packets" },
 305         { "tx_bcast_packets" },
 306         { "tx_carrier_sense_errors" },
 307         { "tx_discards" },
 308         { "tx_errors" },
 309
 310         { "dma_writeq_full" },
 311         { "dma_write_prioq_full" },
 312         { "rxbds_empty" },
 313         { "rx_discards" },
 314         { "rx_errors" },
 315         { "rx_threshold_hit" },
 316
 317         { "dma_readq_full" },
 318         { "dma_read_prioq_full" },
 319         { "tx_comp_queue_full" },
 320
 321         { "ring_set_send_prod_index" },
 322         { "ring_status_update" },
 323         { "nic_irqs" },
 324         { "nic_avoided_irqs" },
 325         { "nic_tx_threshold_hit" }
 326 };
 327
 328 static const struct {
 329         const char string[ETH_GSTRING_LEN];
 330 } ethtool_test_keys[TG3_NUM_TEST] = {
 331         { "nvram test     (online) " },
 332         { "link test      (online) " },
 333         { "register test  (offline)" },
 334         { "memory test    (offline)" },
 335         { "loopback test  (offline)" },
 336         { "interrupt test (offline)" },
 337 };
 338
 339 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 340 {
 341         writel(val, tp->regs + off);
 342 }
 343
 344 static u32 tg3_read32(struct tg3 *tp, u32 off)
 345 {
 346         return (readl(tp->regs + off));
 347 }
 348
 349 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 350 {
 351         writel(val, tp->aperegs + off);
 352 }
 353
 354 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 355 {
 356         return (readl(tp->aperegs + off));
 357 }
 358
 359 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 360 {
 361         unsigned long flags;
 362
 363         spin_lock_irqsave(&tp->indirect_lock, flags);
 364         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 365         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 366         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 367 }
 368
 369 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 370 {
 371         writel(val, tp->regs + off);
 372         readl(tp->regs + off);
 373 }
 374
 375 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 376 {
 377         unsigned long flags;
 378         u32 val;
 379
 380         spin_lock_irqsave(&tp->indirect_lock, flags);
 381         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 382         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 383         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 384         return val;
 385 }
 386
 387 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         unsigned long flags;
 390
 391         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 392                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 393                                        TG3_64BIT_REG_LOW, val);
 394                 return;
 395         }
 396         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 397                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 398                                        TG3_64BIT_REG_LOW, val);
 399                 return;
 400         }
 401
 402         spin_lock_irqsave(&tp->indirect_lock, flags);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 406
 407         /* In indirect mode when disabling interrupts, we also need
 408          * to clear the interrupt bit in the GRC local ctrl register.
 409          */
 410         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 411             (val == 0x1)) {
 412                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 413                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 414         }
 415 }
 416
 417 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 /* usec_wait specifies the wait time in usec when writing to certain registers
 430  * where it is unsafe to read back the register without some delay.
 431  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 432  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 433  */
 434 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 435 {
 436         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 437             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 438                 /* Non-posted methods */
 439                 tp->write32(tp, off, val);
 440         else {
 441                 /* Posted method */
 442                 tg3_write32(tp, off, val);
 443                 if (usec_wait)
 444                         udelay(usec_wait);
 445                 tp->read32(tp, off);
 446         }
 447         /* Wait again after the read for the posted method to guarantee that
 448          * the wait time is met.
 449          */
 450         if (usec_wait)
 451                 udelay(usec_wait);
 452 }
 453
 454 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 455 {
 456         tp->write32_mbox(tp, off, val);
 457         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 458             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 459                 tp->read32_mbox(tp, off);
 460 }
 461
 462 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 463 {
 464         void __iomem *mbox = tp->regs + off;
 465         writel(val, mbox);
 466         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 467                 writel(val, mbox);
 468         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 469                 readl(mbox);
 470 }
 471
 472 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 473 {
 474         return (readl(tp->regs + off + GRCMBOX_BASE));
 475 }
 476
 477 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 478 {
 479         writel(val, tp->regs + off + GRCMBOX_BASE);
 480 }
 481
 482 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 483 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 484 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 485 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 486 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 487
 488 #define tw32(reg,val)           tp->write32(tp, reg, val)
 489 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 490 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 491 #define tr32(reg)               tp->read32(tp, reg)
 492
 493 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 494 {
 495         unsigned long flags;
 496
 497         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 498             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 499                 return;
 500
 501         spin_lock_irqsave(&tp->indirect_lock, flags);
 502         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 503                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 505
 506                 /* Always leave this as zero. */
 507                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 508         } else {
 509                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 510                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 511
 512                 /* Always leave this as zero. */
 513                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 514         }
 515         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 516 }
 517
 518 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 519 {
 520         unsigned long flags;
 521
 522         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 523             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 524                 *val = 0;
 525                 return;
 526         }
 527
 528         spin_lock_irqsave(&tp->indirect_lock, flags);
 529         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 530                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 531                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 532
 533                 /* Always leave this as zero. */
 534                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 535         } else {
 536                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 537                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 538
 539                 /* Always leave this as zero. */
 540                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 541         }
 542         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 543 }
 544
 545 static void tg3_ape_lock_init(struct tg3 *tp)
 546 {
 547         int i;
 548
 549         /* Make sure the driver hasn't any stale locks. */
 550         for (i = 0; i < 8; i++)
 551                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 552                                 APE_LOCK_GRANT_DRIVER);
 553 }
 554
 555 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 556 {
 557         int i, off;
 558         int ret = 0;
 559         u32 status;
 560
 561         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 562                 return 0;
 563
 564         switch (locknum) {
 565                 case TG3_APE_LOCK_GRC:
 566                 case TG3_APE_LOCK_MEM:
 567                         break;
 568                 default:
 569                         return -EINVAL;
 570         }
 571
 572         off = 4 * locknum;
 573
 574         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 575
 576         /* Wait for up to 1 millisecond to acquire lock. */
 577         for (i = 0; i < 100; i++) {
 578                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 579                 if (status == APE_LOCK_GRANT_DRIVER)
 580                         break;
 581                 udelay(10);
 582         }
 583
 584         if (status != APE_LOCK_GRANT_DRIVER) {
 585                 /* Revoke the lock request. */
 586                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 587                                 APE_LOCK_GRANT_DRIVER);
 588
 589                 ret = -EBUSY;
 590         }
 591
 592         return ret;
 593 }
 594
 595 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 596 {
 597         int off;
 598
 599         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 600                 return;
 601
 602         switch (locknum) {
 603                 case TG3_APE_LOCK_GRC:
 604                 case TG3_APE_LOCK_MEM:
 605                         break;
 606                 default:
 607                         return;
 608         }
 609
 610         off = 4 * locknum;
 611         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 612 }
 613
 614 static void tg3_disable_ints(struct tg3 *tp)
 615 {
 616         tw32(TG3PCI_MISC_HOST_CTRL,
 617              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 618         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 619 }
 620
 621 static inline void tg3_cond_int(struct tg3 *tp)
 622 {
 623         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 624             (tp->hw_status->status & SD_STATUS_UPDATED))
 625                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 626         else
 627                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 628                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 629 }
 630
 631 static void tg3_enable_ints(struct tg3 *tp)
 632 {
 633         tp->irq_sync = 0;
 634         wmb();
 635
 636         tw32(TG3PCI_MISC_HOST_CTRL,
 637              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 638         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 639                        (tp->last_tag << 24));
 640         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 641                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 642                                (tp->last_tag << 24));
 643         tg3_cond_int(tp);
 644 }
 645
 646 static inline unsigned int tg3_has_work(struct tg3 *tp)
 647 {
 648         struct tg3_hw_status *sblk = tp->hw_status;
 649         unsigned int work_exists = 0;
 650
 651         /* check for phy events */
 652         if (!(tp->tg3_flags &
 653               (TG3_FLAG_USE_LINKCHG_REG |
 654                TG3_FLAG_POLL_SERDES))) {
 655                 if (sblk->status & SD_STATUS_LINK_CHG)
 656                         work_exists = 1;
 657         }
 658         /* check for RX/TX work to do */
 659         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 660             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 661                 work_exists = 1;
 662
 663         return work_exists;
 664 }
 665
 666 /* tg3_restart_ints
 667  *  similar to tg3_enable_ints, but it accurately determines whether there
 668  *  is new work pending and can return without flushing the PIO write
 669  *  which reenables interrupts
 670  */
 671 static void tg3_restart_ints(struct tg3 *tp)
 672 {
 673         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 674                      tp->last_tag << 24);
 675         mmiowb();
 676
 677         /* When doing tagged status, this work check is unnecessary.
 678          * The last_tag we write above tells the chip which piece of
 679          * work we've completed.
 680          */
 681         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 682             tg3_has_work(tp))
 683                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 684                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 685 }
 686
 687 static inline void tg3_netif_stop(struct tg3 *tp)
 688 {
 689         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 690         napi_disable(&tp->napi[0].napi);
 691         netif_tx_disable(tp->dev);
 692 }
 693
 694 static inline void tg3_netif_start(struct tg3 *tp)
 695 {
 696         netif_wake_queue(tp->dev);
 697         /* NOTE: unconditional netif_wake_queue is only appropriate
 698          * so long as all callers are assured to have free tx slots
 699          * (such as after tg3_init_hw)
 700          */
 701         napi_enable(&tp->napi[0].napi);
 702         tp->hw_status->status |= SD_STATUS_UPDATED;
 703         tg3_enable_ints(tp);
 704 }
 705
 706 static void tg3_switch_clocks(struct tg3 *tp)
 707 {
 708         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 709         u32 orig_clock_ctrl;
 710
 711         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 712             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 713                 return;
 714
 715         orig_clock_ctrl = clock_ctrl;
 716         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 717                        CLOCK_CTRL_CLKRUN_OENABLE |
 718                        0x1f);
 719         tp->pci_clock_ctrl = clock_ctrl;
 720
 721         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 722                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 723                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 724                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 725                 }
 726         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 727                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 728                             clock_ctrl |
 729                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 730                             40);
 731                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 732                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 733                             40);
 734         }
 735         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 736 }
 737
 738 #define PHY_BUSY_LOOPS  5000
 739
 740 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 741 {
 742         u32 frame_val;
 743         unsigned int loops;
 744         int ret;
 745
 746         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 747                 tw32_f(MAC_MI_MODE,
 748                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 749                 udelay(80);
 750         }
 751
 752         *val = 0x0;
 753
 754         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 755                       MI_COM_PHY_ADDR_MASK);
 756         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 757                       MI_COM_REG_ADDR_MASK);
 758         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 759
 760         tw32_f(MAC_MI_COM, frame_val);
 761
 762         loops = PHY_BUSY_LOOPS;
 763         while (loops != 0) {
 764                 udelay(10);
 765                 frame_val = tr32(MAC_MI_COM);
 766
 767                 if ((frame_val & MI_COM_BUSY) == 0) {
 768                         udelay(5);
 769                         frame_val = tr32(MAC_MI_COM);
 770                         break;
 771                 }
 772                 loops -= 1;
 773         }
 774
 775         ret = -EBUSY;
 776         if (loops != 0) {
 777                 *val = frame_val & MI_COM_DATA_MASK;
 778                 ret = 0;
 779         }
 780
 781         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 782                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 783                 udelay(80);
 784         }
 785
 786         return ret;
 787 }
 788
 789 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 790 {
 791         u32 frame_val;
 792         unsigned int loops;
 793         int ret;
 794
 795         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 796             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 797                 return 0;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE,
 801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 802                 udelay(80);
 803         }
 804
 805         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 806                       MI_COM_PHY_ADDR_MASK);
 807         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 808                       MI_COM_REG_ADDR_MASK);
 809         frame_val |= (val & MI_COM_DATA_MASK);
 810         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 811
 812         tw32_f(MAC_MI_COM, frame_val);
 813
 814         loops = PHY_BUSY_LOOPS;
 815         while (loops != 0) {
 816                 udelay(10);
 817                 frame_val = tr32(MAC_MI_COM);
 818                 if ((frame_val & MI_COM_BUSY) == 0) {
 819                         udelay(5);
 820                         frame_val = tr32(MAC_MI_COM);
 821                         break;
 822                 }
 823                 loops -= 1;
 824         }
 825
 826         ret = -EBUSY;
 827         if (loops != 0)
 828                 ret = 0;
 829
 830         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 831                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 832                 udelay(80);
 833         }
 834
 835         return ret;
 836 }
 837
 838 static int tg3_bmcr_reset(struct tg3 *tp)
 839 {
 840         u32 phy_control;
 841         int limit, err;
 842
 843         /* OK, reset it, and poll the BMCR_RESET bit until it
 844          * clears or we time out.
 845          */
 846         phy_control = BMCR_RESET;
 847         err = tg3_writephy(tp, MII_BMCR, phy_control);
 848         if (err != 0)
 849                 return -EBUSY;
 850
 851         limit = 5000;
 852         while (limit--) {
 853                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 854                 if (err != 0)
 855                         return -EBUSY;
 856
 857                 if ((phy_control & BMCR_RESET) == 0) {
 858                         udelay(40);
 859                         break;
 860                 }
 861                 udelay(10);
 862         }
 863         if (limit < 0)
 864                 return -EBUSY;
 865
 866         return 0;
 867 }
 868
 869 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 870 {
 871         struct tg3 *tp = bp->priv;
 872         u32 val;
 873
 874         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 875                 return -EAGAIN;
 876
 877         if (tg3_readphy(tp, reg, &val))
 878                 return -EIO;
 879
 880         return val;
 881 }
 882
 883 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 884 {
 885         struct tg3 *tp = bp->priv;
 886
 887         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 888                 return -EAGAIN;
 889
 890         if (tg3_writephy(tp, reg, val))
 891                 return -EIO;
 892
 893         return 0;
 894 }
 895
 896 static int tg3_mdio_reset(struct mii_bus *bp)
 897 {
 898         return 0;
 899 }
 900
 901 static void tg3_mdio_config_5785(struct tg3 *tp)
 902 {
 903         u32 val;
 904         struct phy_device *phydev;
 905
 906         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 907         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 908         case TG3_PHY_ID_BCM50610:
 909                 val = MAC_PHYCFG2_50610_LED_MODES;
 910                 break;
 911         case TG3_PHY_ID_BCMAC131:
 912                 val = MAC_PHYCFG2_AC131_LED_MODES;
 913                 break;
 914         case TG3_PHY_ID_RTL8211C:
 915                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 916                 break;
 917         case TG3_PHY_ID_RTL8201E:
 918                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 919                 break;
 920         default:
 921                 return;
 922         }
 923
 924         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 925                 tw32(MAC_PHYCFG2, val);
 926
 927                 val = tr32(MAC_PHYCFG1);
 928                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 929                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 930                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 931                 tw32(MAC_PHYCFG1, val);
 932
 933                 return;
 934         }
 935
 936         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 937                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 938                        MAC_PHYCFG2_FMODE_MASK_MASK |
 939                        MAC_PHYCFG2_GMODE_MASK_MASK |
 940                        MAC_PHYCFG2_ACT_MASK_MASK   |
 941                        MAC_PHYCFG2_QUAL_MASK_MASK |
 942                        MAC_PHYCFG2_INBAND_ENABLE;
 943
 944         tw32(MAC_PHYCFG2, val);
 945
 946         val = tr32(MAC_PHYCFG1);
 947         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 948                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 949         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 950                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 951                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 952                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 953                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 954         }
 955         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
 956                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
 957         tw32(MAC_PHYCFG1, val);
 958
 959         val = tr32(MAC_EXT_RGMII_MODE);
 960         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 961                  MAC_RGMII_MODE_RX_QUALITY |
 962                  MAC_RGMII_MODE_RX_ACTIVITY |
 963                  MAC_RGMII_MODE_RX_ENG_DET |
 964                  MAC_RGMII_MODE_TX_ENABLE |
 965                  MAC_RGMII_MODE_TX_LOWPWR |
 966                  MAC_RGMII_MODE_TX_RESET);
 967         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
 968                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 969                         val |= MAC_RGMII_MODE_RX_INT_B |
 970                                MAC_RGMII_MODE_RX_QUALITY |
 971                                MAC_RGMII_MODE_RX_ACTIVITY |
 972                                MAC_RGMII_MODE_RX_ENG_DET;
 973                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 974                         val |= MAC_RGMII_MODE_TX_ENABLE |
 975                                MAC_RGMII_MODE_TX_LOWPWR |
 976                                MAC_RGMII_MODE_TX_RESET;
 977         }
 978         tw32(MAC_EXT_RGMII_MODE, val);
 979 }
 980
 981 static void tg3_mdio_start(struct tg3 *tp)
 982 {
 983         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 984                 mutex_lock(&tp->mdio_bus->mdio_lock);
 985                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 986                 mutex_unlock(&tp->mdio_bus->mdio_lock);
 987         }
 988
 989         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 990         tw32_f(MAC_MI_MODE, tp->mi_mode);
 991         udelay(80);
 992
 993         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
 994             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
 995                 tg3_mdio_config_5785(tp);
 996 }
 997
 998 static void tg3_mdio_stop(struct tg3 *tp)
 999 {
1000         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1001                 mutex_lock(&tp->mdio_bus->mdio_lock);
1002                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
1003                 mutex_unlock(&tp->mdio_bus->mdio_lock);
1004         }
1005 }
1006
1007 static int tg3_mdio_init(struct tg3 *tp)
1008 {
1009         int i;
1010         u32 reg;
1011         struct phy_device *phydev;
1012
1013         tg3_mdio_start(tp);
1014
1015         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1016             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1017                 return 0;
1018
1019         tp->mdio_bus = mdiobus_alloc();
1020         if (tp->mdio_bus == NULL)
1021                 return -ENOMEM;
1022
1023         tp->mdio_bus->name     = "tg3 mdio bus";
1024         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1025                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1026         tp->mdio_bus->priv     = tp;
1027         tp->mdio_bus->parent   = &tp->pdev->dev;
1028         tp->mdio_bus->read     = &tg3_mdio_read;
1029         tp->mdio_bus->write    = &tg3_mdio_write;
1030         tp->mdio_bus->reset    = &tg3_mdio_reset;
1031         tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1032         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1033
1034         for (i = 0; i < PHY_MAX_ADDR; i++)
1035                 tp->mdio_bus->irq[i] = PHY_POLL;
1036
1037         /* The bus registration will look for all the PHYs on the mdio bus.
1038          * Unfortunately, it does not ensure the PHY is powered up before
1039          * accessing the PHY ID registers.  A chip reset is the
1040          * quickest way to bring the device back to an operational state..
1041          */
1042         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1043                 tg3_bmcr_reset(tp);
1044
1045         i = mdiobus_register(tp->mdio_bus);
1046         if (i) {
1047                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1048                         tp->dev->name, i);
1049                 mdiobus_free(tp->mdio_bus);
1050                 return i;
1051         }
1052
1053         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1054
1055         if (!phydev || !phydev->drv) {
1056                 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1057                 mdiobus_unregister(tp->mdio_bus);
1058                 mdiobus_free(tp->mdio_bus);
1059                 return -ENODEV;
1060         }
1061
1062         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1063         case TG3_PHY_ID_BCM57780:
1064                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1065                 break;
1066         case TG3_PHY_ID_BCM50610:
1067                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1068                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1069                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1070                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1071                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1072                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1073                 /* fallthru */
1074         case TG3_PHY_ID_RTL8211C:
1075                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1076                 break;
1077         case TG3_PHY_ID_RTL8201E:
1078         case TG3_PHY_ID_BCMAC131:
1079                 phydev->interface = PHY_INTERFACE_MODE_MII;
1080                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1081                 break;
1082         }
1083
1084         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1085
1086         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1087                 tg3_mdio_config_5785(tp);
1088
1089         return 0;
1090 }
1091
1092 static void tg3_mdio_fini(struct tg3 *tp)
1093 {
1094         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1095                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1096                 mdiobus_unregister(tp->mdio_bus);
1097                 mdiobus_free(tp->mdio_bus);
1098                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1099         }
1100 }
1101
1102 /* tp->lock is held. */
1103 static inline void tg3_generate_fw_event(struct tg3 *tp)
1104 {
1105         u32 val;
1106
1107         val = tr32(GRC_RX_CPU_EVENT);
1108         val |= GRC_RX_CPU_DRIVER_EVENT;
1109         tw32_f(GRC_RX_CPU_EVENT, val);
1110
1111         tp->last_event_jiffies = jiffies;
1112 }
1113
1114 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1115
1116 /* tp->lock is held. */
1117 static void tg3_wait_for_event_ack(struct tg3 *tp)
1118 {
1119         int i;
1120         unsigned int delay_cnt;
1121         long time_remain;
1122
1123         /* If enough time has passed, no wait is necessary. */
1124         time_remain = (long)(tp->last_event_jiffies + 1 +
1125                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1126                       (long)jiffies;
1127         if (time_remain < 0)
1128                 return;
1129
1130         /* Check if we can shorten the wait time. */
1131         delay_cnt = jiffies_to_usecs(time_remain);
1132         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1133                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1134         delay_cnt = (delay_cnt >> 3) + 1;
1135
1136         for (i = 0; i < delay_cnt; i++) {
1137                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1138                         break;
1139                 udelay(8);
1140         }
1141 }
1142
1143 /* tp->lock is held. */
1144 static void tg3_ump_link_report(struct tg3 *tp)
1145 {
1146         u32 reg;
1147         u32 val;
1148
1149         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1150             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1151                 return;
1152
1153         tg3_wait_for_event_ack(tp);
1154
1155         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1156
1157         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1158
1159         val = 0;
1160         if (!tg3_readphy(tp, MII_BMCR, &reg))
1161                 val = reg << 16;
1162         if (!tg3_readphy(tp, MII_BMSR, &reg))
1163                 val |= (reg & 0xffff);
1164         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1165
1166         val = 0;
1167         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1168                 val = reg << 16;
1169         if (!tg3_readphy(tp, MII_LPA, &reg))
1170                 val |= (reg & 0xffff);
1171         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1172
1173         val = 0;
1174         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1175                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1176                         val = reg << 16;
1177                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1178                         val |= (reg & 0xffff);
1179         }
1180         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1181
1182         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1183                 val = reg << 16;
1184         else
1185                 val = 0;
1186         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1187
1188         tg3_generate_fw_event(tp);
1189 }
1190
1191 static void tg3_link_report(struct tg3 *tp)
1192 {
1193         if (!netif_carrier_ok(tp->dev)) {
1194                 if (netif_msg_link(tp))
1195                         printk(KERN_INFO PFX "%s: Link is down.\n",
1196                                tp->dev->name);
1197                 tg3_ump_link_report(tp);
1198         } else if (netif_msg_link(tp)) {
1199                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1200                        tp->dev->name,
1201                        (tp->link_config.active_speed == SPEED_1000 ?
1202                         1000 :
1203                         (tp->link_config.active_speed == SPEED_100 ?
1204                          100 : 10)),
1205                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1206                         "full" : "half"));
1207
1208                 printk(KERN_INFO PFX
1209                        "%s: Flow control is %s for TX and %s for RX.\n",
1210                        tp->dev->name,
1211                        (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1212                        "on" : "off",
1213                        (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1214                        "on" : "off");
1215                 tg3_ump_link_report(tp);
1216         }
1217 }
1218
1219 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1220 {
1221         u16 miireg;
1222
1223         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1224                 miireg = ADVERTISE_PAUSE_CAP;
1225         else if (flow_ctrl & FLOW_CTRL_TX)
1226                 miireg = ADVERTISE_PAUSE_ASYM;
1227         else if (flow_ctrl & FLOW_CTRL_RX)
1228                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1229         else
1230                 miireg = 0;
1231
1232         return miireg;
1233 }
1234
1235 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1236 {
1237         u16 miireg;
1238
1239         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1240                 miireg = ADVERTISE_1000XPAUSE;
1241         else if (flow_ctrl & FLOW_CTRL_TX)
1242                 miireg = ADVERTISE_1000XPSE_ASYM;
1243         else if (flow_ctrl & FLOW_CTRL_RX)
1244                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1245         else
1246                 miireg = 0;
1247
1248         return miireg;
1249 }
1250
1251 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1252 {
1253         u8 cap = 0;
1254
1255         if (lcladv & ADVERTISE_1000XPAUSE) {
1256                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1257                         if (rmtadv & LPA_1000XPAUSE)
1258                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1259                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1260                                 cap = FLOW_CTRL_RX;
1261                 } else {
1262                         if (rmtadv & LPA_1000XPAUSE)
1263                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1264                 }
1265         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1266                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1267                         cap = FLOW_CTRL_TX;
1268         }
1269
1270         return cap;
1271 }
1272
1273 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1274 {
1275         u8 autoneg;
1276         u8 flowctrl = 0;
1277         u32 old_rx_mode = tp->rx_mode;
1278         u32 old_tx_mode = tp->tx_mode;
1279
1280         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1281                 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1282         else
1283                 autoneg = tp->link_config.autoneg;
1284
1285         if (autoneg == AUTONEG_ENABLE &&
1286             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1287                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1288                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1289                 else
1290                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1291         } else
1292                 flowctrl = tp->link_config.flowctrl;
1293
1294         tp->link_config.active_flowctrl = flowctrl;
1295
1296         if (flowctrl & FLOW_CTRL_RX)
1297                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1298         else
1299                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1300
1301         if (old_rx_mode != tp->rx_mode)
1302                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1303
1304         if (flowctrl & FLOW_CTRL_TX)
1305                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1306         else
1307                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1308
1309         if (old_tx_mode != tp->tx_mode)
1310                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1311 }
1312
1313 static void tg3_adjust_link(struct net_device *dev)
1314 {
1315         u8 oldflowctrl, linkmesg = 0;
1316         u32 mac_mode, lcl_adv, rmt_adv;
1317         struct tg3 *tp = netdev_priv(dev);
1318         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1319
1320         spin_lock(&tp->lock);
1321
1322         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1323                                     MAC_MODE_HALF_DUPLEX);
1324
1325         oldflowctrl = tp->link_config.active_flowctrl;
1326
1327         if (phydev->link) {
1328                 lcl_adv = 0;
1329                 rmt_adv = 0;
1330
1331                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1332                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1333                 else
1334                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1335
1336                 if (phydev->duplex == DUPLEX_HALF)
1337                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1338                 else {
1339                         lcl_adv = tg3_advert_flowctrl_1000T(
1340                                   tp->link_config.flowctrl);
1341
1342                         if (phydev->pause)
1343                                 rmt_adv = LPA_PAUSE_CAP;
1344                         if (phydev->asym_pause)
1345                                 rmt_adv |= LPA_PAUSE_ASYM;
1346                 }
1347
1348                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1349         } else
1350                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1351
1352         if (mac_mode != tp->mac_mode) {
1353                 tp->mac_mode = mac_mode;
1354                 tw32_f(MAC_MODE, tp->mac_mode);
1355                 udelay(40);
1356         }
1357
1358         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1359                 if (phydev->speed == SPEED_10)
1360                         tw32(MAC_MI_STAT,
1361                              MAC_MI_STAT_10MBPS_MODE |
1362                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1363                 else
1364                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1365         }
1366
1367         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1368                 tw32(MAC_TX_LENGTHS,
1369                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1370                       (6 << TX_LENGTHS_IPG_SHIFT) |
1371                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1372         else
1373                 tw32(MAC_TX_LENGTHS,
1374                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1375                       (6 << TX_LENGTHS_IPG_SHIFT) |
1376                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1377
1378         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1379             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1380             phydev->speed != tp->link_config.active_speed ||
1381             phydev->duplex != tp->link_config.active_duplex ||
1382             oldflowctrl != tp->link_config.active_flowctrl)
1383             linkmesg = 1;
1384
1385         tp->link_config.active_speed = phydev->speed;
1386         tp->link_config.active_duplex = phydev->duplex;
1387
1388         spin_unlock(&tp->lock);
1389
1390         if (linkmesg)
1391                 tg3_link_report(tp);
1392 }
1393
1394 static int tg3_phy_init(struct tg3 *tp)
1395 {
1396         struct phy_device *phydev;
1397
1398         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1399                 return 0;
1400
1401         /* Bring the PHY back to a known state. */
1402         tg3_bmcr_reset(tp);
1403
1404         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1405
1406         /* Attach the MAC to the PHY. */
1407         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1408                              phydev->dev_flags, phydev->interface);
1409         if (IS_ERR(phydev)) {
1410                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1411                 return PTR_ERR(phydev);
1412         }
1413
1414         /* Mask with MAC supported features. */
1415         switch (phydev->interface) {
1416         case PHY_INTERFACE_MODE_GMII:
1417         case PHY_INTERFACE_MODE_RGMII:
1418                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1419                         phydev->supported &= (PHY_GBIT_FEATURES |
1420                                               SUPPORTED_Pause |
1421                                               SUPPORTED_Asym_Pause);
1422                         break;
1423                 }
1424                 /* fallthru */
1425         case PHY_INTERFACE_MODE_MII:
1426                 phydev->supported &= (PHY_BASIC_FEATURES |
1427                                       SUPPORTED_Pause |
1428                                       SUPPORTED_Asym_Pause);
1429                 break;
1430         default:
1431                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1432                 return -EINVAL;
1433         }
1434
1435         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1436
1437         phydev->advertising = phydev->supported;
1438
1439         return 0;
1440 }
1441
1442 static void tg3_phy_start(struct tg3 *tp)
1443 {
1444         struct phy_device *phydev;
1445
1446         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1447                 return;
1448
1449         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1450
1451         if (tp->link_config.phy_is_low_power) {
1452                 tp->link_config.phy_is_low_power = 0;
1453                 phydev->speed = tp->link_config.orig_speed;
1454                 phydev->duplex = tp->link_config.orig_duplex;
1455                 phydev->autoneg = tp->link_config.orig_autoneg;
1456                 phydev->advertising = tp->link_config.orig_advertising;
1457         }
1458
1459         phy_start(phydev);
1460
1461         phy_start_aneg(phydev);
1462 }
1463
1464 static void tg3_phy_stop(struct tg3 *tp)
1465 {
1466         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1467                 return;
1468
1469         phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1470 }
1471
1472 static void tg3_phy_fini(struct tg3 *tp)
1473 {
1474         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1475                 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1476                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1477         }
1478 }
1479
1480 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1481 {
1482         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1483         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1484 }
1485
1486 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1487 {
1488         u32 phytest;
1489
1490         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1491                 u32 phy;
1492
1493                 tg3_writephy(tp, MII_TG3_FET_TEST,
1494                              phytest | MII_TG3_FET_SHADOW_EN);
1495                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1496                         if (enable)
1497                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1498                         else
1499                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1500                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1501                 }
1502                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1503         }
1504 }
1505
1506 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1507 {
1508         u32 reg;
1509
1510         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1511                 return;
1512
1513         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1514                 tg3_phy_fet_toggle_apd(tp, enable);
1515                 return;
1516         }
1517
1518         reg = MII_TG3_MISC_SHDW_WREN |
1519               MII_TG3_MISC_SHDW_SCR5_SEL |
1520               MII_TG3_MISC_SHDW_SCR5_LPED |
1521               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1522               MII_TG3_MISC_SHDW_SCR5_SDTL |
1523               MII_TG3_MISC_SHDW_SCR5_C125OE;
1524         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1525                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1526
1527         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1528
1529
1530         reg = MII_TG3_MISC_SHDW_WREN |
1531               MII_TG3_MISC_SHDW_APD_SEL |
1532               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1533         if (enable)
1534                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1535
1536         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1537 }
1538
1539 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1540 {
1541         u32 phy;
1542
1543         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1544             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1545                 return;
1546
1547         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1548                 u32 ephy;
1549
1550                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1551                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1552
1553                         tg3_writephy(tp, MII_TG3_FET_TEST,
1554                                      ephy | MII_TG3_FET_SHADOW_EN);
1555                         if (!tg3_readphy(tp, reg, &phy)) {
1556                                 if (enable)
1557                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1558                                 else
1559                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1560                                 tg3_writephy(tp, reg, phy);
1561                         }
1562                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1563                 }
1564         } else {
1565                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1566                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1567                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1568                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1569                         if (enable)
1570                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1571                         else
1572                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1573                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1574                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1575                 }
1576         }
1577 }
1578
1579 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1580 {
1581         u32 val;
1582
1583         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1584                 return;
1585
1586         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1587             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1588                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1589                              (val | (1 << 15) | (1 << 4)));
1590 }
1591
1592 static void tg3_phy_apply_otp(struct tg3 *tp)
1593 {
1594         u32 otp, phy;
1595
1596         if (!tp->phy_otp)
1597                 return;
1598
1599         otp = tp->phy_otp;
1600
1601         /* Enable SM_DSP clock and tx 6dB coding. */
1602         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1603               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1604               MII_TG3_AUXCTL_ACTL_TX_6DB;
1605         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1606
1607         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1608         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1609         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1610
1611         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1612               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1613         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1614
1615         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1616         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1617         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1618
1619         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1620         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1621
1622         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1623         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1624
1625         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1626               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1627         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1628
1629         /* Turn off SM_DSP clock. */
1630         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1631               MII_TG3_AUXCTL_ACTL_TX_6DB;
1632         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1633 }
1634
1635 static int tg3_wait_macro_done(struct tg3 *tp)
1636 {
1637         int limit = 100;
1638
1639         while (limit--) {
1640                 u32 tmp32;
1641
1642                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1643                         if ((tmp32 & 0x1000) == 0)
1644                                 break;
1645                 }
1646         }
1647         if (limit < 0)
1648                 return -EBUSY;
1649
1650         return 0;
1651 }
1652
1653 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1654 {
1655         static const u32 test_pat[4][6] = {
1656         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1657         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1658         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1659         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1660         };
1661         int chan;
1662
1663         for (chan = 0; chan < 4; chan++) {
1664                 int i;
1665
1666                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1667                              (chan * 0x2000) | 0x0200);
1668                 tg3_writephy(tp, 0x16, 0x0002);
1669
1670                 for (i = 0; i < 6; i++)
1671                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1672                                      test_pat[chan][i]);
1673
1674                 tg3_writephy(tp, 0x16, 0x0202);
1675                 if (tg3_wait_macro_done(tp)) {
1676                         *resetp = 1;
1677                         return -EBUSY;
1678                 }
1679
1680                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1681                              (chan * 0x2000) | 0x0200);
1682                 tg3_writephy(tp, 0x16, 0x0082);
1683                 if (tg3_wait_macro_done(tp)) {
1684                         *resetp = 1;
1685                         return -EBUSY;
1686                 }
1687
1688                 tg3_writephy(tp, 0x16, 0x0802);
1689                 if (tg3_wait_macro_done(tp)) {
1690                         *resetp = 1;
1691                         return -EBUSY;
1692                 }
1693
1694                 for (i = 0; i < 6; i += 2) {
1695                         u32 low, high;
1696
1697                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1698                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1699                             tg3_wait_macro_done(tp)) {
1700                                 *resetp = 1;
1701                                 return -EBUSY;
1702                         }
1703                         low &= 0x7fff;
1704                         high &= 0x000f;
1705                         if (low != test_pat[chan][i] ||
1706                             high != test_pat[chan][i+1]) {
1707                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1708                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1709                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1710
1711                                 return -EBUSY;
1712                         }
1713                 }
1714         }
1715
1716         return 0;
1717 }
1718
1719 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1720 {
1721         int chan;
1722
1723         for (chan = 0; chan < 4; chan++) {
1724                 int i;
1725
1726                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1727                              (chan * 0x2000) | 0x0200);
1728                 tg3_writephy(tp, 0x16, 0x0002);
1729                 for (i = 0; i < 6; i++)
1730                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1731                 tg3_writephy(tp, 0x16, 0x0202);
1732                 if (tg3_wait_macro_done(tp))
1733                         return -EBUSY;
1734         }
1735
1736         return 0;
1737 }
1738
1739 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1740 {
1741         u32 reg32, phy9_orig;
1742         int retries, do_phy_reset, err;
1743
1744         retries = 10;
1745         do_phy_reset = 1;
1746         do {
1747                 if (do_phy_reset) {
1748                         err = tg3_bmcr_reset(tp);
1749                         if (err)
1750                                 return err;
1751                         do_phy_reset = 0;
1752                 }
1753
1754                 /* Disable transmitter and interrupt.  */
1755                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1756                         continue;
1757
1758                 reg32 |= 0x3000;
1759                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1760
1761                 /* Set full-duplex, 1000 mbps.  */
1762                 tg3_writephy(tp, MII_BMCR,
1763                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1764
1765                 /* Set to master mode.  */
1766                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1767                         continue;
1768
1769                 tg3_writephy(tp, MII_TG3_CTRL,
1770                              (MII_TG3_CTRL_AS_MASTER |
1771                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1772
1773                 /* Enable SM_DSP_CLOCK and 6dB.  */
1774                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1775
1776                 /* Block the PHY control access.  */
1777                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1778                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1779
1780                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1781                 if (!err)
1782                         break;
1783         } while (--retries);
1784
1785         err = tg3_phy_reset_chanpat(tp);
1786         if (err)
1787                 return err;
1788
1789         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1790         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1791
1792         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1793         tg3_writephy(tp, 0x16, 0x0000);
1794
1795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1797                 /* Set Extended packet length bit for jumbo frames */
1798                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1799         }
1800         else {
1801                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1802         }
1803
1804         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1805
1806         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1807                 reg32 &= ~0x3000;
1808                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1809         } else if (!err)
1810                 err = -EBUSY;
1811
1812         return err;
1813 }
1814
1815 /* This will reset the tigon3 PHY if there is no valid
1816  * link unless the FORCE argument is non-zero.
1817  */
1818 static int tg3_phy_reset(struct tg3 *tp)
1819 {
1820         u32 cpmuctrl;
1821         u32 phy_status;
1822         int err;
1823
1824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1825                 u32 val;
1826
1827                 val = tr32(GRC_MISC_CFG);
1828                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1829                 udelay(40);
1830         }
1831         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1832         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1833         if (err != 0)
1834                 return -EBUSY;
1835
1836         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1837                 netif_carrier_off(tp->dev);
1838                 tg3_link_report(tp);
1839         }
1840
1841         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1842             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1843             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1844                 err = tg3_phy_reset_5703_4_5(tp);
1845                 if (err)
1846                         return err;
1847                 goto out;
1848         }
1849
1850         cpmuctrl = 0;
1851         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1852             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1853                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1854                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1855                         tw32(TG3_CPMU_CTRL,
1856                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1857         }
1858
1859         err = tg3_bmcr_reset(tp);
1860         if (err)
1861                 return err;
1862
1863         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1864                 u32 phy;
1865
1866                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1867                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1868
1869                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1870         }
1871
1872         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1873             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1874                 u32 val;
1875
1876                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1877                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1878                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1879                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1880                         udelay(40);
1881                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1882                 }
1883         }
1884
1885         tg3_phy_apply_otp(tp);
1886
1887         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1888                 tg3_phy_toggle_apd(tp, true);
1889         else
1890                 tg3_phy_toggle_apd(tp, false);
1891
1892 out:
1893         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1894                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1895                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1896                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1898                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1900         }
1901         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1902                 tg3_writephy(tp, 0x1c, 0x8d68);
1903                 tg3_writephy(tp, 0x1c, 0x8d68);
1904         }
1905         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1906                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1907                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1908                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1909                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1910                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1911                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1912                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1913                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1914         }
1915         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1916                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1917                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1918                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1919                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1920                         tg3_writephy(tp, MII_TG3_TEST1,
1921                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1922                 } else
1923                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1924                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1925         }
1926         /* Set Extended packet length bit (bit 14) on all chips that */
1927         /* support jumbo frames */
1928         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1929                 /* Cannot do read-modify-write on 5401 */
1930                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1931         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1932                 u32 phy_reg;
1933
1934                 /* Set bit 14 with read-modify-write to preserve other bits */
1935                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1936                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1937                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1938         }
1939
1940         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1941          * jumbo frames transmission.
1942          */
1943         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1944                 u32 phy_reg;
1945
1946                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1947                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1948                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1949         }
1950
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1952                 /* adjust output voltage */
1953                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1954         }
1955
1956         tg3_phy_toggle_automdix(tp, 1);
1957         tg3_phy_set_wirespeed(tp);
1958         return 0;
1959 }
1960
1961 static void tg3_frob_aux_power(struct tg3 *tp)
1962 {
1963         struct tg3 *tp_peer = tp;
1964
1965         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1966                 return;
1967
1968         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1969             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1970                 struct net_device *dev_peer;
1971
1972                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1973                 /* remove_one() may have been run on the peer. */
1974                 if (!dev_peer)
1975                         tp_peer = tp;
1976                 else
1977                         tp_peer = netdev_priv(dev_peer);
1978         }
1979
1980         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1981             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1982             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1983             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1984                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1985                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1986                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1987                                     (GRC_LCLCTRL_GPIO_OE0 |
1988                                      GRC_LCLCTRL_GPIO_OE1 |
1989                                      GRC_LCLCTRL_GPIO_OE2 |
1990                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1991                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1992                                     100);
1993                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1994                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1995                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1996                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1997                                              GRC_LCLCTRL_GPIO_OE1 |
1998                                              GRC_LCLCTRL_GPIO_OE2 |
1999                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2000                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2001                                              tp->grc_local_ctrl;
2002                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2003
2004                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2005                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2006
2007                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2008                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2009                 } else {
2010                         u32 no_gpio2;
2011                         u32 grc_local_ctrl = 0;
2012
2013                         if (tp_peer != tp &&
2014                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2015                                 return;
2016
2017                         /* Workaround to prevent overdrawing Amps. */
2018                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2019                             ASIC_REV_5714) {
2020                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2021                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022                                             grc_local_ctrl, 100);
2023                         }
2024
2025                         /* On 5753 and variants, GPIO2 cannot be used. */
2026                         no_gpio2 = tp->nic_sram_data_cfg &
2027                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2028
2029                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2030                                          GRC_LCLCTRL_GPIO_OE1 |
2031                                          GRC_LCLCTRL_GPIO_OE2 |
2032                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2033                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2034                         if (no_gpio2) {
2035                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2036                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2037                         }
2038                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2039                                                     grc_local_ctrl, 100);
2040
2041                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2042
2043                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2044                                                     grc_local_ctrl, 100);
2045
2046                         if (!no_gpio2) {
2047                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2048                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2049                                             grc_local_ctrl, 100);
2050                         }
2051                 }
2052         } else {
2053                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2054                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2055                         if (tp_peer != tp &&
2056                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2057                                 return;
2058
2059                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2060                                     (GRC_LCLCTRL_GPIO_OE1 |
2061                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2062
2063                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2064                                     GRC_LCLCTRL_GPIO_OE1, 100);
2065
2066                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2067                                     (GRC_LCLCTRL_GPIO_OE1 |
2068                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2069                 }
2070         }
2071 }
2072
2073 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2074 {
2075         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2076                 return 1;
2077         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2078                 if (speed != SPEED_10)
2079                         return 1;
2080         } else if (speed == SPEED_10)
2081                 return 1;
2082
2083         return 0;
2084 }
2085
2086 static int tg3_setup_phy(struct tg3 *, int);
2087
2088 #define RESET_KIND_SHUTDOWN     0
2089 #define RESET_KIND_INIT         1
2090 #define RESET_KIND_SUSPEND      2
2091
2092 static void tg3_write_sig_post_reset(struct tg3 *, int);
2093 static int tg3_halt_cpu(struct tg3 *, u32);
2094
2095 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2096 {
2097         u32 val;
2098
2099         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2100                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2101                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2102                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2103
2104                         sg_dig_ctrl |=
2105                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2106                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2107                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2108                 }
2109                 return;
2110         }
2111
2112         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2113                 tg3_bmcr_reset(tp);
2114                 val = tr32(GRC_MISC_CFG);
2115                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2116                 udelay(40);
2117                 return;
2118         } else if (do_low_power) {
2119                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2120                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2121
2122                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2123                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2124                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2125                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2126                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2127         }
2128
2129         /* The PHY should not be powered down on some chips because
2130          * of bugs.
2131          */
2132         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2133             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2134             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2135              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2136                 return;
2137
2138         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2139             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2140                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2141                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2142                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2143                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2144         }
2145
2146         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2147 }
2148
2149 /* tp->lock is held. */
2150 static int tg3_nvram_lock(struct tg3 *tp)
2151 {
2152         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2153                 int i;
2154
2155                 if (tp->nvram_lock_cnt == 0) {
2156                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2157                         for (i = 0; i < 8000; i++) {
2158                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2159                                         break;
2160                                 udelay(20);
2161                         }
2162                         if (i == 8000) {
2163                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2164                                 return -ENODEV;
2165                         }
2166                 }
2167                 tp->nvram_lock_cnt++;
2168         }
2169         return 0;
2170 }
2171
2172 /* tp->lock is held. */
2173 static void tg3_nvram_unlock(struct tg3 *tp)
2174 {
2175         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2176                 if (tp->nvram_lock_cnt > 0)
2177                         tp->nvram_lock_cnt--;
2178                 if (tp->nvram_lock_cnt == 0)
2179                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2180         }
2181 }
2182
2183 /* tp->lock is held. */
2184 static void tg3_enable_nvram_access(struct tg3 *tp)
2185 {
2186         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2187             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2188                 u32 nvaccess = tr32(NVRAM_ACCESS);
2189
2190                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2191         }
2192 }
2193
2194 /* tp->lock is held. */
2195 static void tg3_disable_nvram_access(struct tg3 *tp)
2196 {
2197         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2198             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2199                 u32 nvaccess = tr32(NVRAM_ACCESS);
2200
2201                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2202         }
2203 }
2204
2205 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2206                                         u32 offset, u32 *val)
2207 {
2208         u32 tmp;
2209         int i;
2210
2211         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2212                 return -EINVAL;
2213
2214         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2215                                         EEPROM_ADDR_DEVID_MASK |
2216                                         EEPROM_ADDR_READ);
2217         tw32(GRC_EEPROM_ADDR,
2218              tmp |
2219              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2220              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2221               EEPROM_ADDR_ADDR_MASK) |
2222              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2223
2224         for (i = 0; i < 1000; i++) {
2225                 tmp = tr32(GRC_EEPROM_ADDR);
2226
2227                 if (tmp & EEPROM_ADDR_COMPLETE)
2228                         break;
2229                 msleep(1);
2230         }
2231         if (!(tmp & EEPROM_ADDR_COMPLETE))
2232                 return -EBUSY;
2233
2234         tmp = tr32(GRC_EEPROM_DATA);
2235
2236         /*
2237          * The data will always be opposite the native endian
2238          * format.  Perform a blind byteswap to compensate.
2239          */
2240         *val = swab32(tmp);
2241
2242         return 0;
2243 }
2244
2245 #define NVRAM_CMD_TIMEOUT 10000
2246
2247 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2248 {
2249         int i;
2250
2251         tw32(NVRAM_CMD, nvram_cmd);
2252         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2253                 udelay(10);
2254                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2255                         udelay(10);
2256                         break;
2257                 }
2258         }
2259
2260         if (i == NVRAM_CMD_TIMEOUT)
2261                 return -EBUSY;
2262
2263         return 0;
2264 }
2265
2266 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2267 {
2268         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2269             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2270             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2271            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2272             (tp->nvram_jedecnum == JEDEC_ATMEL))
2273
2274                 addr = ((addr / tp->nvram_pagesize) <<
2275                         ATMEL_AT45DB0X1B_PAGE_POS) +
2276                        (addr % tp->nvram_pagesize);
2277
2278         return addr;
2279 }
2280
2281 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2282 {
2283         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2284             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2285             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2286            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2287             (tp->nvram_jedecnum == JEDEC_ATMEL))
2288
2289                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2290                         tp->nvram_pagesize) +
2291                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2292
2293         return addr;
2294 }
2295
2296 /* NOTE: Data read in from NVRAM is byteswapped according to
2297  * the byteswapping settings for all other register accesses.
2298  * tg3 devices are BE devices, so on a BE machine, the data
2299  * returned will be exactly as it is seen in NVRAM.  On a LE
2300  * machine, the 32-bit value will be byteswapped.
2301  */
2302 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2303 {
2304         int ret;
2305
2306         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2307                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2308
2309         offset = tg3_nvram_phys_addr(tp, offset);
2310
2311         if (offset > NVRAM_ADDR_MSK)
2312                 return -EINVAL;
2313
2314         ret = tg3_nvram_lock(tp);
2315         if (ret)
2316                 return ret;
2317
2318         tg3_enable_nvram_access(tp);
2319
2320         tw32(NVRAM_ADDR, offset);
2321         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2322                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2323
2324         if (ret == 0)
2325                 *val = tr32(NVRAM_RDDATA);
2326
2327         tg3_disable_nvram_access(tp);
2328
2329         tg3_nvram_unlock(tp);
2330
2331         return ret;
2332 }
2333
2334 /* Ensures NVRAM data is in bytestream format. */
2335 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2336 {
2337         u32 v;
2338         int res = tg3_nvram_read(tp, offset, &v);
2339         if (!res)
2340                 *val = cpu_to_be32(v);
2341         return res;
2342 }
2343
2344 /* tp->lock is held. */
2345 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2346 {
2347         u32 addr_high, addr_low;
2348         int i;
2349
2350         addr_high = ((tp->dev->dev_addr[0] << 8) |
2351                      tp->dev->dev_addr[1]);
2352         addr_low = ((tp->dev->dev_addr[2] << 24) |
2353                     (tp->dev->dev_addr[3] << 16) |
2354                     (tp->dev->dev_addr[4] <<  8) |
2355                     (tp->dev->dev_addr[5] <<  0));
2356         for (i = 0; i < 4; i++) {
2357                 if (i == 1 && skip_mac_1)
2358                         continue;
2359                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2360                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2361         }
2362
2363         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2364             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2365                 for (i = 0; i < 12; i++) {
2366                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2367                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2368                 }
2369         }
2370
2371         addr_high = (tp->dev->dev_addr[0] +
2372                      tp->dev->dev_addr[1] +
2373                      tp->dev->dev_addr[2] +
2374                      tp->dev->dev_addr[3] +
2375                      tp->dev->dev_addr[4] +
2376                      tp->dev->dev_addr[5]) &
2377                 TX_BACKOFF_SEED_MASK;
2378         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2379 }
2380
2381 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2382 {
2383         u32 misc_host_ctrl;
2384         bool device_should_wake, do_low_power;
2385
2386         /* Make sure register accesses (indirect or otherwise)
2387          * will function correctly.
2388          */
2389         pci_write_config_dword(tp->pdev,
2390                                TG3PCI_MISC_HOST_CTRL,
2391                                tp->misc_host_ctrl);
2392
2393         switch (state) {
2394         case PCI_D0:
2395                 pci_enable_wake(tp->pdev, state, false);
2396                 pci_set_power_state(tp->pdev, PCI_D0);
2397
2398                 /* Switch out of Vaux if it is a NIC */
2399                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2400                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2401
2402                 return 0;
2403
2404         case PCI_D1:
2405         case PCI_D2:
2406         case PCI_D3hot:
2407                 break;
2408
2409         default:
2410                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2411                         tp->dev->name, state);
2412                 return -EINVAL;
2413         }
2414
2415         /* Restore the CLKREQ setting. */
2416         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2417                 u16 lnkctl;
2418
2419                 pci_read_config_word(tp->pdev,
2420                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2421                                      &lnkctl);
2422                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2423                 pci_write_config_word(tp->pdev,
2424                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2425                                       lnkctl);
2426         }
2427
2428         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2429         tw32(TG3PCI_MISC_HOST_CTRL,
2430              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2431
2432         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2433                              device_may_wakeup(&tp->pdev->dev) &&
2434                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2435
2436         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2437                 do_low_power = false;
2438                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2439                     !tp->link_config.phy_is_low_power) {
2440                         struct phy_device *phydev;
2441                         u32 phyid, advertising;
2442
2443                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2444
2445                         tp->link_config.phy_is_low_power = 1;
2446
2447                         tp->link_config.orig_speed = phydev->speed;
2448                         tp->link_config.orig_duplex = phydev->duplex;
2449                         tp->link_config.orig_autoneg = phydev->autoneg;
2450                         tp->link_config.orig_advertising = phydev->advertising;
2451
2452                         advertising = ADVERTISED_TP |
2453                                       ADVERTISED_Pause |
2454                                       ADVERTISED_Autoneg |
2455                                       ADVERTISED_10baseT_Half;
2456
2457                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2458                             device_should_wake) {
2459                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2460                                         advertising |=
2461                                                 ADVERTISED_100baseT_Half |
2462                                                 ADVERTISED_100baseT_Full |
2463                                                 ADVERTISED_10baseT_Full;
2464                                 else
2465                                         advertising |= ADVERTISED_10baseT_Full;
2466                         }
2467
2468                         phydev->advertising = advertising;
2469
2470                         phy_start_aneg(phydev);
2471
2472                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2473                         if (phyid != TG3_PHY_ID_BCMAC131) {
2474                                 phyid &= TG3_PHY_OUI_MASK;
2475                                 if (phyid == TG3_PHY_OUI_1 ||
2476                                     phyid == TG3_PHY_OUI_2 ||
2477                                     phyid == TG3_PHY_OUI_3)
2478                                         do_low_power = true;
2479                         }
2480                 }
2481         } else {
2482                 do_low_power = true;
2483
2484                 if (tp->link_config.phy_is_low_power == 0) {
2485                         tp->link_config.phy_is_low_power = 1;
2486                         tp->link_config.orig_speed = tp->link_config.speed;
2487                         tp->link_config.orig_duplex = tp->link_config.duplex;
2488                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2489                 }
2490
2491                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2492                         tp->link_config.speed = SPEED_10;
2493                         tp->link_config.duplex = DUPLEX_HALF;
2494                         tp->link_config.autoneg = AUTONEG_ENABLE;
2495                         tg3_setup_phy(tp, 0);
2496                 }
2497         }
2498
2499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2500                 u32 val;
2501
2502                 val = tr32(GRC_VCPU_EXT_CTRL);
2503                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2504         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2505                 int i;
2506                 u32 val;
2507
2508                 for (i = 0; i < 200; i++) {
2509                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2510                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2511                                 break;
2512                         msleep(1);
2513                 }
2514         }
2515         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2516                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2517                                                      WOL_DRV_STATE_SHUTDOWN |
2518                                                      WOL_DRV_WOL |
2519                                                      WOL_SET_MAGIC_PKT);
2520
2521         if (device_should_wake) {
2522                 u32 mac_mode;
2523
2524                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2525                         if (do_low_power) {
2526                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2527                                 udelay(40);
2528                         }
2529
2530                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2531                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2532                         else
2533                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2534
2535                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2536                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2537                             ASIC_REV_5700) {
2538                                 u32 speed = (tp->tg3_flags &
2539                                              TG3_FLAG_WOL_SPEED_100MB) ?
2540                                              SPEED_100 : SPEED_10;
2541                                 if (tg3_5700_link_polarity(tp, speed))
2542                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2543                                 else
2544                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2545                         }
2546                 } else {
2547                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2548                 }
2549
2550                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2551                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2552
2553                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2554                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2555                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2556                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2557                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2558                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2559
2560                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2561                         mac_mode |= tp->mac_mode &
2562                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2563                         if (mac_mode & MAC_MODE_APE_TX_EN)
2564                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2565                 }
2566
2567                 tw32_f(MAC_MODE, mac_mode);
2568                 udelay(100);
2569
2570                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2571                 udelay(10);
2572         }
2573
2574         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2575             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2576              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2577                 u32 base_val;
2578
2579                 base_val = tp->pci_clock_ctrl;
2580                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2581                              CLOCK_CTRL_TXCLK_DISABLE);
2582
2583                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2584                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2585         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2586                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2587                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2588                 /* do nothing */
2589         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2590                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2591                 u32 newbits1, newbits2;
2592
2593                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2594                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2595                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2596                                     CLOCK_CTRL_TXCLK_DISABLE |
2597                                     CLOCK_CTRL_ALTCLK);
2598                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2599                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2600                         newbits1 = CLOCK_CTRL_625_CORE;
2601                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2602                 } else {
2603                         newbits1 = CLOCK_CTRL_ALTCLK;
2604                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2605                 }
2606
2607                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2608                             40);
2609
2610                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2611                             40);
2612
2613                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2614                         u32 newbits3;
2615
2616                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2617                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2618                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2619                                             CLOCK_CTRL_TXCLK_DISABLE |
2620                                             CLOCK_CTRL_44MHZ_CORE);
2621                         } else {
2622                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2623                         }
2624
2625                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2626                                     tp->pci_clock_ctrl | newbits3, 40);
2627                 }
2628         }
2629
2630         if (!(device_should_wake) &&
2631             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2632                 tg3_power_down_phy(tp, do_low_power);
2633
2634         tg3_frob_aux_power(tp);
2635
2636         /* Workaround for unstable PLL clock */
2637         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2638             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2639                 u32 val = tr32(0x7d00);
2640
2641                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2642                 tw32(0x7d00, val);
2643                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2644                         int err;
2645
2646                         err = tg3_nvram_lock(tp);
2647                         tg3_halt_cpu(tp, RX_CPU_BASE);
2648                         if (!err)
2649                                 tg3_nvram_unlock(tp);
2650                 }
2651         }
2652
2653         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2654
2655         if (device_should_wake)
2656                 pci_enable_wake(tp->pdev, state, true);
2657
2658         /* Finally, set the new power state. */
2659         pci_set_power_state(tp->pdev, state);
2660
2661         return 0;
2662 }
2663
2664 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2665 {
2666         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2667         case MII_TG3_AUX_STAT_10HALF:
2668                 *speed = SPEED_10;
2669                 *duplex = DUPLEX_HALF;
2670                 break;
2671
2672         case MII_TG3_AUX_STAT_10FULL:
2673                 *speed = SPEED_10;
2674                 *duplex = DUPLEX_FULL;
2675                 break;
2676
2677         case MII_TG3_AUX_STAT_100HALF:
2678                 *speed = SPEED_100;
2679                 *duplex = DUPLEX_HALF;
2680                 break;
2681
2682         case MII_TG3_AUX_STAT_100FULL:
2683                 *speed = SPEED_100;
2684                 *duplex = DUPLEX_FULL;
2685                 break;
2686
2687         case MII_TG3_AUX_STAT_1000HALF:
2688                 *speed = SPEED_1000;
2689                 *duplex = DUPLEX_HALF;
2690                 break;
2691
2692         case MII_TG3_AUX_STAT_1000FULL:
2693                 *speed = SPEED_1000;
2694                 *duplex = DUPLEX_FULL;
2695                 break;
2696
2697         default:
2698                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2699                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2700                                  SPEED_10;
2701                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2702                                   DUPLEX_HALF;
2703                         break;
2704                 }
2705                 *speed = SPEED_INVALID;
2706                 *duplex = DUPLEX_INVALID;
2707                 break;
2708         }
2709 }
2710
2711 static void tg3_phy_copper_begin(struct tg3 *tp)
2712 {
2713         u32 new_adv;
2714         int i;
2715
2716         if (tp->link_config.phy_is_low_power) {
2717                 /* Entering low power mode.  Disable gigabit and
2718                  * 100baseT advertisements.
2719                  */
2720                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2721
2722                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2723                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2724                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2725                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2726
2727                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2728         } else if (tp->link_config.speed == SPEED_INVALID) {
2729                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2730                         tp->link_config.advertising &=
2731                                 ~(ADVERTISED_1000baseT_Half |
2732                                   ADVERTISED_1000baseT_Full);
2733
2734                 new_adv = ADVERTISE_CSMA;
2735                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2736                         new_adv |= ADVERTISE_10HALF;
2737                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2738                         new_adv |= ADVERTISE_10FULL;
2739                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2740                         new_adv |= ADVERTISE_100HALF;
2741                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2742                         new_adv |= ADVERTISE_100FULL;
2743
2744                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2745
2746                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2747
2748                 if (tp->link_config.advertising &
2749                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2750                         new_adv = 0;
2751                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2752                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2753                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2754                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2755                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2756                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2757                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2758                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2759                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2760                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2761                 } else {
2762                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2763                 }
2764         } else {
2765                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2766                 new_adv |= ADVERTISE_CSMA;
2767
2768                 /* Asking for a specific link mode. */
2769                 if (tp->link_config.speed == SPEED_1000) {
2770                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2771
2772                         if (tp->link_config.duplex == DUPLEX_FULL)
2773                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2774                         else
2775                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2776                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2777                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2778                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2779                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2780                 } else {
2781                         if (tp->link_config.speed == SPEED_100) {
2782                                 if (tp->link_config.duplex == DUPLEX_FULL)
2783                                         new_adv |= ADVERTISE_100FULL;
2784                                 else
2785                                         new_adv |= ADVERTISE_100HALF;
2786                         } else {
2787                                 if (tp->link_config.duplex == DUPLEX_FULL)
2788                                         new_adv |= ADVERTISE_10FULL;
2789                                 else
2790                                         new_adv |= ADVERTISE_10HALF;
2791                         }
2792                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2793
2794                         new_adv = 0;
2795                 }
2796
2797                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2798         }
2799
2800         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2801             tp->link_config.speed != SPEED_INVALID) {
2802                 u32 bmcr, orig_bmcr;
2803
2804                 tp->link_config.active_speed = tp->link_config.speed;
2805                 tp->link_config.active_duplex = tp->link_config.duplex;
2806
2807                 bmcr = 0;
2808                 switch (tp->link_config.speed) {
2809                 default:
2810                 case SPEED_10:
2811                         break;
2812
2813                 case SPEED_100:
2814                         bmcr |= BMCR_SPEED100;
2815                         break;
2816
2817                 case SPEED_1000:
2818                         bmcr |= TG3_BMCR_SPEED1000;
2819                         break;
2820                 }
2821
2822                 if (tp->link_config.duplex == DUPLEX_FULL)
2823                         bmcr |= BMCR_FULLDPLX;
2824
2825                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2826                     (bmcr != orig_bmcr)) {
2827                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2828                         for (i = 0; i < 1500; i++) {
2829                                 u32 tmp;
2830
2831                                 udelay(10);
2832                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2833                                     tg3_readphy(tp, MII_BMSR, &tmp))
2834                                         continue;
2835                                 if (!(tmp & BMSR_LSTATUS)) {
2836                                         udelay(40);
2837                                         break;
2838                                 }
2839                         }
2840                         tg3_writephy(tp, MII_BMCR, bmcr);
2841                         udelay(40);
2842                 }
2843         } else {
2844                 tg3_writephy(tp, MII_BMCR,
2845                              BMCR_ANENABLE | BMCR_ANRESTART);
2846         }
2847 }
2848
2849 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2850 {
2851         int err;
2852
2853         /* Turn off tap power management. */
2854         /* Set Extended packet length bit */
2855         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2856
2857         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2858         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2859
2860         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2861         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2862
2863         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2864         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2865
2866         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2867         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2868
2869         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2870         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2871
2872         udelay(40);
2873
2874         return err;
2875 }
2876
2877 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2878 {
2879         u32 adv_reg, all_mask = 0;
2880
2881         if (mask & ADVERTISED_10baseT_Half)
2882                 all_mask |= ADVERTISE_10HALF;
2883         if (mask & ADVERTISED_10baseT_Full)
2884                 all_mask |= ADVERTISE_10FULL;
2885         if (mask & ADVERTISED_100baseT_Half)
2886                 all_mask |= ADVERTISE_100HALF;
2887         if (mask & ADVERTISED_100baseT_Full)
2888                 all_mask |= ADVERTISE_100FULL;
2889
2890         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2891                 return 0;
2892
2893         if ((adv_reg & all_mask) != all_mask)
2894                 return 0;
2895         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2896                 u32 tg3_ctrl;
2897
2898                 all_mask = 0;
2899                 if (mask & ADVERTISED_1000baseT_Half)
2900                         all_mask |= ADVERTISE_1000HALF;
2901                 if (mask & ADVERTISED_1000baseT_Full)
2902                         all_mask |= ADVERTISE_1000FULL;
2903
2904                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2905                         return 0;
2906
2907                 if ((tg3_ctrl & all_mask) != all_mask)
2908                         return 0;
2909         }
2910         return 1;
2911 }
2912
2913 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2914 {
2915         u32 curadv, reqadv;
2916
2917         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2918                 return 1;
2919
2920         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2921         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2922
2923         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2924                 if (curadv != reqadv)
2925                         return 0;
2926
2927                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2928                         tg3_readphy(tp, MII_LPA, rmtadv);
2929         } else {
2930                 /* Reprogram the advertisement register, even if it
2931                  * does not affect the current link.  If the link
2932                  * gets renegotiated in the future, we can save an
2933                  * additional renegotiation cycle by advertising
2934                  * it correctly in the first place.
2935                  */
2936                 if (curadv != reqadv) {
2937                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2938                                      ADVERTISE_PAUSE_ASYM);
2939                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2940                 }
2941         }
2942
2943         return 1;
2944 }
2945
2946 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2947 {
2948         int current_link_up;
2949         u32 bmsr, dummy;
2950         u32 lcl_adv, rmt_adv;
2951         u16 current_speed;
2952         u8 current_duplex;
2953         int i, err;
2954
2955         tw32(MAC_EVENT, 0);
2956
2957         tw32_f(MAC_STATUS,
2958              (MAC_STATUS_SYNC_CHANGED |
2959               MAC_STATUS_CFG_CHANGED |
2960               MAC_STATUS_MI_COMPLETION |
2961               MAC_STATUS_LNKSTATE_CHANGED));
2962         udelay(40);
2963
2964         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2965                 tw32_f(MAC_MI_MODE,
2966                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2967                 udelay(80);
2968         }
2969
2970         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2971
2972         /* Some third-party PHYs need to be reset on link going
2973          * down.
2974          */
2975         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2976              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2977              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2978             netif_carrier_ok(tp->dev)) {
2979                 tg3_readphy(tp, MII_BMSR, &bmsr);
2980                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2981                     !(bmsr & BMSR_LSTATUS))
2982                         force_reset = 1;
2983         }
2984         if (force_reset)
2985                 tg3_phy_reset(tp);
2986
2987         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2988                 tg3_readphy(tp, MII_BMSR, &bmsr);
2989                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2990                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2991                         bmsr = 0;
2992
2993                 if (!(bmsr & BMSR_LSTATUS)) {
2994                         err = tg3_init_5401phy_dsp(tp);
2995                         if (err)
2996                                 return err;
2997
2998                         tg3_readphy(tp, MII_BMSR, &bmsr);
2999                         for (i = 0; i < 1000; i++) {
3000                                 udelay(10);
3001                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3002                                     (bmsr & BMSR_LSTATUS)) {
3003                                         udelay(40);
3004                                         break;
3005                                 }
3006                         }
3007
3008                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3009                             !(bmsr & BMSR_LSTATUS) &&
3010                             tp->link_config.active_speed == SPEED_1000) {
3011                                 err = tg3_phy_reset(tp);
3012                                 if (!err)
3013                                         err = tg3_init_5401phy_dsp(tp);
3014                                 if (err)
3015                                         return err;
3016                         }
3017                 }
3018         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3019                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3020                 /* 5701 {A0,B0} CRC bug workaround */
3021                 tg3_writephy(tp, 0x15, 0x0a75);
3022                 tg3_writephy(tp, 0x1c, 0x8c68);
3023                 tg3_writephy(tp, 0x1c, 0x8d68);
3024                 tg3_writephy(tp, 0x1c, 0x8c68);
3025         }
3026
3027         /* Clear pending interrupts... */
3028         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3029         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3030
3031         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3032                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3033         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3034                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3035
3036         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3038                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3039                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3040                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3041                 else
3042                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3043         }
3044
3045         current_link_up = 0;
3046         current_speed = SPEED_INVALID;
3047         current_duplex = DUPLEX_INVALID;
3048
3049         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3050                 u32 val;
3051
3052                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3053                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3054                 if (!(val & (1 << 10))) {
3055                         val |= (1 << 10);
3056                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3057                         goto relink;
3058                 }
3059         }
3060
3061         bmsr = 0;
3062         for (i = 0; i < 100; i++) {
3063                 tg3_readphy(tp, MII_BMSR, &bmsr);
3064                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3065                     (bmsr & BMSR_LSTATUS))
3066                         break;
3067                 udelay(40);
3068         }
3069
3070         if (bmsr & BMSR_LSTATUS) {
3071                 u32 aux_stat, bmcr;
3072
3073                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3074                 for (i = 0; i < 2000; i++) {
3075                         udelay(10);
3076                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3077                             aux_stat)
3078                                 break;
3079                 }
3080
3081                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3082                                              &current_speed,
3083                                              &current_duplex);
3084
3085                 bmcr = 0;
3086                 for (i = 0; i < 200; i++) {
3087                         tg3_readphy(tp, MII_BMCR, &bmcr);
3088                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3089                                 continue;
3090                         if (bmcr && bmcr != 0x7fff)
3091                                 break;
3092                         udelay(10);
3093                 }
3094
3095                 lcl_adv = 0;
3096                 rmt_adv = 0;
3097
3098                 tp->link_config.active_speed = current_speed;
3099                 tp->link_config.active_duplex = current_duplex;
3100
3101                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3102                         if ((bmcr & BMCR_ANENABLE) &&
3103                             tg3_copper_is_advertising_all(tp,
3104                                                 tp->link_config.advertising)) {
3105                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3106                                                                   &rmt_adv))
3107                                         current_link_up = 1;
3108                         }
3109                 } else {
3110                         if (!(bmcr & BMCR_ANENABLE) &&
3111                             tp->link_config.speed == current_speed &&
3112                             tp->link_config.duplex == current_duplex &&
3113                             tp->link_config.flowctrl ==
3114                             tp->link_config.active_flowctrl) {
3115                                 current_link_up = 1;
3116                         }
3117                 }
3118
3119                 if (current_link_up == 1 &&
3120                     tp->link_config.active_duplex == DUPLEX_FULL)
3121                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3122         }
3123
3124 relink:
3125         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3126                 u32 tmp;
3127
3128                 tg3_phy_copper_begin(tp);
3129
3130                 tg3_readphy(tp, MII_BMSR, &tmp);
3131                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3132                     (tmp & BMSR_LSTATUS))
3133                         current_link_up = 1;
3134         }
3135
3136         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3137         if (current_link_up == 1) {
3138                 if (tp->link_config.active_speed == SPEED_100 ||
3139                     tp->link_config.active_speed == SPEED_10)
3140                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3141                 else
3142                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3143         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3144                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3145         else
3146                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3147
3148         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3149         if (tp->link_config.active_duplex == DUPLEX_HALF)
3150                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3151
3152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3153                 if (current_link_up == 1 &&
3154                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3155                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3156                 else
3157                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3158         }
3159
3160         /* ??? Without this setting Netgear GA302T PHY does not
3161          * ??? send/receive packets...
3162          */
3163         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3164             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3165                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3166                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3167                 udelay(80);
3168         }
3169
3170         tw32_f(MAC_MODE, tp->mac_mode);
3171         udelay(40);
3172
3173         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3174                 /* Polled via timer. */
3175                 tw32_f(MAC_EVENT, 0);
3176         } else {
3177                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3178         }
3179         udelay(40);
3180
3181         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3182             current_link_up == 1 &&
3183             tp->link_config.active_speed == SPEED_1000 &&
3184             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3185              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3186                 udelay(120);
3187                 tw32_f(MAC_STATUS,
3188                      (MAC_STATUS_SYNC_CHANGED |
3189                       MAC_STATUS_CFG_CHANGED));
3190                 udelay(40);
3191                 tg3_write_mem(tp,
3192                               NIC_SRAM_FIRMWARE_MBOX,
3193                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3194         }
3195
3196         /* Prevent send BD corruption. */
3197         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3198                 u16 oldlnkctl, newlnkctl;
3199
3200                 pci_read_config_word(tp->pdev,
3201                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3202                                      &oldlnkctl);
3203                 if (tp->link_config.active_speed == SPEED_100 ||
3204                     tp->link_config.active_speed == SPEED_10)
3205                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3206                 else
3207                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3208                 if (newlnkctl != oldlnkctl)
3209                         pci_write_config_word(tp->pdev,
3210                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3211                                               newlnkctl);
3212         } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3213                 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3214                 if (tp->link_config.active_speed == SPEED_100 ||
3215                     tp->link_config.active_speed == SPEED_10)
3216                         newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3217                 else
3218                         newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3219                 if (newreg != oldreg)
3220                         tw32(TG3_PCIE_LNKCTL, newreg);
3221         }
3222
3223         if (current_link_up != netif_carrier_ok(tp->dev)) {
3224                 if (current_link_up)
3225                         netif_carrier_on(tp->dev);
3226                 else
3227                         netif_carrier_off(tp->dev);
3228                 tg3_link_report(tp);
3229         }
3230
3231         return 0;
3232 }
3233
3234 struct tg3_fiber_aneginfo {
3235         int state;
3236 #define ANEG_STATE_UNKNOWN              0
3237 #define ANEG_STATE_AN_ENABLE            1
3238 #define ANEG_STATE_RESTART_INIT         2
3239 #define ANEG_STATE_RESTART              3
3240 #define ANEG_STATE_DISABLE_LINK_OK      4
3241 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3242 #define ANEG_STATE_ABILITY_DETECT       6
3243 #define ANEG_STATE_ACK_DETECT_INIT      7
3244 #define ANEG_STATE_ACK_DETECT           8
3245 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3246 #define ANEG_STATE_COMPLETE_ACK         10
3247 #define ANEG_STATE_IDLE_DETECT_INIT     11
3248 #define ANEG_STATE_IDLE_DETECT          12
3249 #define ANEG_STATE_LINK_OK              13
3250 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3251 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3252
3253         u32 flags;
3254 #define MR_AN_ENABLE            0x00000001
3255 #define MR_RESTART_AN           0x00000002
3256 #define MR_AN_COMPLETE          0x00000004
3257 #define MR_PAGE_RX              0x00000008
3258 #define MR_NP_LOADED            0x00000010
3259 #define MR_TOGGLE_TX            0x00000020
3260 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3261 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3262 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3263 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3264 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3265 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3266 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3267 #define MR_TOGGLE_RX            0x00002000
3268 #define MR_NP_RX                0x00004000
3269
3270 #define MR_LINK_OK              0x80000000
3271
3272         unsigned long link_time, cur_time;
3273
3274         u32 ability_match_cfg;
3275         int ability_match_count;
3276
3277         char ability_match, idle_match, ack_match;
3278
3279         u32 txconfig, rxconfig;
3280 #define ANEG_CFG_NP             0x00000080
3281 #define ANEG_CFG_ACK            0x00000040
3282 #define ANEG_CFG_RF2            0x00000020
3283 #define ANEG_CFG_RF1            0x00000010
3284 #define ANEG_CFG_PS2            0x00000001
3285 #define ANEG_CFG_PS1            0x00008000
3286 #define ANEG_CFG_HD             0x00004000
3287 #define ANEG_CFG_FD             0x00002000
3288 #define ANEG_CFG_INVAL          0x00001f06
3289
3290 };
3291 #define ANEG_OK         0
3292 #define ANEG_DONE       1
3293 #define ANEG_TIMER_ENAB 2
3294 #define ANEG_FAILED     -1
3295
3296 #define ANEG_STATE_SETTLE_TIME  10000
3297
3298 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3299                                    struct tg3_fiber_aneginfo *ap)
3300 {
3301         u16 flowctrl;
3302         unsigned long delta;
3303         u32 rx_cfg_reg;
3304         int ret;
3305
3306         if (ap->state == ANEG_STATE_UNKNOWN) {
3307                 ap->rxconfig = 0;
3308                 ap->link_time = 0;
3309                 ap->cur_time = 0;
3310                 ap->ability_match_cfg = 0;
3311                 ap->ability_match_count = 0;
3312                 ap->ability_match = 0;
3313                 ap->idle_match = 0;
3314                 ap->ack_match = 0;
3315         }
3316         ap->cur_time++;
3317
3318         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3319                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3320
3321                 if (rx_cfg_reg != ap->ability_match_cfg) {
3322                         ap->ability_match_cfg = rx_cfg_reg;
3323                         ap->ability_match = 0;
3324                         ap->ability_match_count = 0;
3325                 } else {
3326                         if (++ap->ability_match_count > 1) {
3327                                 ap->ability_match = 1;
3328                                 ap->ability_match_cfg = rx_cfg_reg;
3329                         }
3330                 }
3331                 if (rx_cfg_reg & ANEG_CFG_ACK)
3332                         ap->ack_match = 1;
3333                 else
3334                         ap->ack_match = 0;
3335
3336                 ap->idle_match = 0;
3337         } else {
3338                 ap->idle_match = 1;
3339                 ap->ability_match_cfg = 0;
3340                 ap->ability_match_count = 0;
3341                 ap->ability_match = 0;
3342                 ap->ack_match = 0;
3343
3344                 rx_cfg_reg = 0;
3345         }
3346
3347         ap->rxconfig = rx_cfg_reg;
3348         ret = ANEG_OK;
3349
3350         switch(ap->state) {
3351         case ANEG_STATE_UNKNOWN:
3352                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3353                         ap->state = ANEG_STATE_AN_ENABLE;
3354
3355                 /* fallthru */
3356         case ANEG_STATE_AN_ENABLE:
3357                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3358                 if (ap->flags & MR_AN_ENABLE) {
3359                         ap->link_time = 0;
3360                         ap->cur_time = 0;
3361                         ap->ability_match_cfg = 0;
3362                         ap->ability_match_count = 0;
3363                         ap->ability_match = 0;
3364                         ap->idle_match = 0;
3365                         ap->ack_match = 0;
3366
3367                         ap->state = ANEG_STATE_RESTART_INIT;
3368                 } else {
3369                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3370                 }
3371                 break;
3372
3373         case ANEG_STATE_RESTART_INIT:
3374                 ap->link_time = ap->cur_time;
3375                 ap->flags &= ~(MR_NP_LOADED);
3376                 ap->txconfig = 0;
3377                 tw32(MAC_TX_AUTO_NEG, 0);
3378                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3379                 tw32_f(MAC_MODE, tp->mac_mode);
3380                 udelay(40);
3381
3382                 ret = ANEG_TIMER_ENAB;
3383                 ap->state = ANEG_STATE_RESTART;
3384
3385                 /* fallthru */
3386         case ANEG_STATE_RESTART:
3387                 delta = ap->cur_time - ap->link_time;
3388                 if (delta > ANEG_STATE_SETTLE_TIME) {
3389                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3390                 } else {
3391                         ret = ANEG_TIMER_ENAB;
3392                 }
3393                 break;
3394
3395         case ANEG_STATE_DISABLE_LINK_OK:
3396                 ret = ANEG_DONE;
3397                 break;
3398
3399         case ANEG_STATE_ABILITY_DETECT_INIT:
3400                 ap->flags &= ~(MR_TOGGLE_TX);
3401                 ap->txconfig = ANEG_CFG_FD;
3402                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3403                 if (flowctrl & ADVERTISE_1000XPAUSE)
3404                         ap->txconfig |= ANEG_CFG_PS1;
3405                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3406                         ap->txconfig |= ANEG_CFG_PS2;
3407                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3408                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3409                 tw32_f(MAC_MODE, tp->mac_mode);
3410                 udelay(40);
3411
3412                 ap->state = ANEG_STATE_ABILITY_DETECT;
3413                 break;
3414
3415         case ANEG_STATE_ABILITY_DETECT:
3416                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3417                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3418                 }
3419                 break;
3420
3421         case ANEG_STATE_ACK_DETECT_INIT:
3422                 ap->txconfig |= ANEG_CFG_ACK;
3423                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3424                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3425                 tw32_f(MAC_MODE, tp->mac_mode);
3426                 udelay(40);
3427
3428                 ap->state = ANEG_STATE_ACK_DETECT;
3429
3430                 /* fallthru */
3431         case ANEG_STATE_ACK_DETECT:
3432                 if (ap->ack_match != 0) {
3433                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3434                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3435                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3436                         } else {
3437                                 ap->state = ANEG_STATE_AN_ENABLE;
3438                         }
3439                 } else if (ap->ability_match != 0 &&
3440                            ap->rxconfig == 0) {
3441                         ap->state = ANEG_STATE_AN_ENABLE;
3442                 }
3443                 break;
3444
3445         case ANEG_STATE_COMPLETE_ACK_INIT:
3446                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3447                         ret = ANEG_FAILED;
3448                         break;
3449                 }
3450                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3451                                MR_LP_ADV_HALF_DUPLEX |
3452                                MR_LP_ADV_SYM_PAUSE |
3453                                MR_LP_ADV_ASYM_PAUSE |
3454                                MR_LP_ADV_REMOTE_FAULT1 |
3455                                MR_LP_ADV_REMOTE_FAULT2 |
3456                                MR_LP_ADV_NEXT_PAGE |
3457                                MR_TOGGLE_RX |
3458                                MR_NP_RX);
3459                 if (ap->rxconfig & ANEG_CFG_FD)
3460                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3461                 if (ap->rxconfig & ANEG_CFG_HD)
3462                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3463                 if (ap->rxconfig & ANEG_CFG_PS1)
3464                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3465                 if (ap->rxconfig & ANEG_CFG_PS2)
3466                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3467                 if (ap->rxconfig & ANEG_CFG_RF1)
3468                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3469                 if (ap->rxconfig & ANEG_CFG_RF2)
3470                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3471                 if (ap->rxconfig & ANEG_CFG_NP)
3472                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3473
3474                 ap->link_time = ap->cur_time;
3475
3476                 ap->flags ^= (MR_TOGGLE_TX);
3477                 if (ap->rxconfig & 0x0008)
3478                         ap->flags |= MR_TOGGLE_RX;
3479                 if (ap->rxconfig & ANEG_CFG_NP)
3480                         ap->flags |= MR_NP_RX;
3481                 ap->flags |= MR_PAGE_RX;
3482
3483                 ap->state = ANEG_STATE_COMPLETE_ACK;
3484                 ret = ANEG_TIMER_ENAB;
3485                 break;
3486
3487         case ANEG_STATE_COMPLETE_ACK:
3488                 if (ap->ability_match != 0 &&
3489                     ap->rxconfig == 0) {
3490                         ap->state = ANEG_STATE_AN_ENABLE;
3491                         break;
3492                 }
3493                 delta = ap->cur_time - ap->link_time;
3494                 if (delta > ANEG_STATE_SETTLE_TIME) {
3495                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3496                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3497                         } else {
3498                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3499                                     !(ap->flags & MR_NP_RX)) {
3500                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3501                                 } else {
3502                                         ret = ANEG_FAILED;
3503                                 }
3504                         }
3505                 }
3506                 break;
3507
3508         case ANEG_STATE_IDLE_DETECT_INIT:
3509                 ap->link_time = ap->cur_time;
3510                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3511                 tw32_f(MAC_MODE, tp->mac_mode);
3512                 udelay(40);
3513
3514                 ap->state = ANEG_STATE_IDLE_DETECT;
3515                 ret = ANEG_TIMER_ENAB;
3516                 break;
3517
3518         case ANEG_STATE_IDLE_DETECT:
3519                 if (ap->ability_match != 0 &&
3520                     ap->rxconfig == 0) {
3521                         ap->state = ANEG_STATE_AN_ENABLE;
3522                         break;
3523                 }
3524                 delta = ap->cur_time - ap->link_time;
3525                 if (delta > ANEG_STATE_SETTLE_TIME) {
3526                         /* XXX another gem from the Broadcom driver :( */
3527                         ap->state = ANEG_STATE_LINK_OK;
3528                 }
3529                 break;
3530
3531         case ANEG_STATE_LINK_OK:
3532                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3533                 ret = ANEG_DONE;
3534                 break;
3535
3536         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3537                 /* ??? unimplemented */
3538                 break;
3539
3540         case ANEG_STATE_NEXT_PAGE_WAIT:
3541                 /* ??? unimplemented */
3542                 break;
3543
3544         default:
3545                 ret = ANEG_FAILED;
3546                 break;
3547         }
3548
3549         return ret;
3550 }
3551
3552 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3553 {
3554         int res = 0;
3555         struct tg3_fiber_aneginfo aninfo;
3556         int status = ANEG_FAILED;
3557         unsigned int tick;
3558         u32 tmp;
3559
3560         tw32_f(MAC_TX_AUTO_NEG, 0);
3561
3562         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3563         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3564         udelay(40);
3565
3566         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3567         udelay(40);
3568
3569         memset(&aninfo, 0, sizeof(aninfo));
3570         aninfo.flags |= MR_AN_ENABLE;
3571         aninfo.state = ANEG_STATE_UNKNOWN;
3572         aninfo.cur_time = 0;
3573         tick = 0;
3574         while (++tick < 195000) {
3575                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3576                 if (status == ANEG_DONE || status == ANEG_FAILED)
3577                         break;
3578
3579                 udelay(1);
3580         }
3581
3582         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3583         tw32_f(MAC_MODE, tp->mac_mode);
3584         udelay(40);
3585
3586         *txflags = aninfo.txconfig;
3587         *rxflags = aninfo.flags;
3588
3589         if (status == ANEG_DONE &&
3590             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3591                              MR_LP_ADV_FULL_DUPLEX)))
3592                 res = 1;
3593
3594         return res;
3595 }
3596
3597 static void tg3_init_bcm8002(struct tg3 *tp)
3598 {
3599         u32 mac_status = tr32(MAC_STATUS);
3600         int i;
3601
3602         /* Reset when initting first time or we have a link. */
3603         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3604             !(mac_status & MAC_STATUS_PCS_SYNCED))
3605                 return;
3606
3607         /* Set PLL lock range. */
3608         tg3_writephy(tp, 0x16, 0x8007);
3609
3610         /* SW reset */
3611         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3612
3613         /* Wait for reset to complete. */
3614         /* XXX schedule_timeout() ... */
3615         for (i = 0; i < 500; i++)
3616                 udelay(10);
3617
3618         /* Config mode; select PMA/Ch 1 regs. */
3619         tg3_writephy(tp, 0x10, 0x8411);
3620
3621         /* Enable auto-lock and comdet, select txclk for tx. */
3622         tg3_writephy(tp, 0x11, 0x0a10);
3623
3624         tg3_writephy(tp, 0x18, 0x00a0);
3625         tg3_writephy(tp, 0x16, 0x41ff);
3626
3627         /* Assert and deassert POR. */
3628         tg3_writephy(tp, 0x13, 0x0400);
3629         udelay(40);
3630         tg3_writephy(tp, 0x13, 0x0000);
3631
3632         tg3_writephy(tp, 0x11, 0x0a50);
3633         udelay(40);
3634         tg3_writephy(tp, 0x11, 0x0a10);
3635
3636         /* Wait for signal to stabilize */
3637         /* XXX schedule_timeout() ... */
3638         for (i = 0; i < 15000; i++)
3639                 udelay(10);
3640
3641         /* Deselect the channel register so we can read the PHYID
3642          * later.
3643          */
3644         tg3_writephy(tp, 0x10, 0x8011);
3645 }
3646
3647 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3648 {
3649         u16 flowctrl;
3650         u32 sg_dig_ctrl, sg_dig_status;
3651         u32 serdes_cfg, expected_sg_dig_ctrl;
3652         int workaround, port_a;
3653         int current_link_up;
3654
3655         serdes_cfg = 0;
3656         expected_sg_dig_ctrl = 0;
3657         workaround = 0;
3658         port_a = 1;
3659         current_link_up = 0;
3660
3661         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3662             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3663                 workaround = 1;
3664                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3665                         port_a = 0;
3666
3667                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3668                 /* preserve bits 20-23 for voltage regulator */
3669                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3670         }
3671
3672         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3673
3674         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3675                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3676                         if (workaround) {
3677                                 u32 val = serdes_cfg;
3678
3679                                 if (port_a)
3680                                         val |= 0xc010000;
3681                                 else
3682                                         val |= 0x4010000;
3683                                 tw32_f(MAC_SERDES_CFG, val);
3684                         }
3685
3686                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3687                 }
3688                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3689                         tg3_setup_flow_control(tp, 0, 0);
3690                         current_link_up = 1;
3691                 }
3692                 goto out;
3693         }
3694
3695         /* Want auto-negotiation.  */
3696         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3697
3698         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3699         if (flowctrl & ADVERTISE_1000XPAUSE)
3700                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3701         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3702                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3703
3704         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3705                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3706                     tp->serdes_counter &&
3707                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3708                                     MAC_STATUS_RCVD_CFG)) ==
3709                      MAC_STATUS_PCS_SYNCED)) {
3710                         tp->serdes_counter--;
3711                         current_link_up = 1;
3712                         goto out;
3713                 }
3714 restart_autoneg:
3715                 if (workaround)
3716                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3717                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3718                 udelay(5);
3719                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3720
3721                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3722                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3723         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3724                                  MAC_STATUS_SIGNAL_DET)) {
3725                 sg_dig_status = tr32(SG_DIG_STATUS);
3726                 mac_status = tr32(MAC_STATUS);
3727
3728                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3729                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3730                         u32 local_adv = 0, remote_adv = 0;
3731
3732                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3733                                 local_adv |= ADVERTISE_1000XPAUSE;
3734                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3735                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3736
3737                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3738                                 remote_adv |= LPA_1000XPAUSE;
3739                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3740                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3741
3742                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3743                         current_link_up = 1;
3744                         tp->serdes_counter = 0;
3745                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3746                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3747                         if (tp->serdes_counter)
3748                                 tp->serdes_counter--;
3749                         else {
3750                                 if (workaround) {
3751                                         u32 val = serdes_cfg;
3752
3753                                         if (port_a)
3754                                                 val |= 0xc010000;
3755                                         else
3756                                                 val |= 0x4010000;
3757
3758                                         tw32_f(MAC_SERDES_CFG, val);
3759                                 }
3760
3761                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3762                                 udelay(40);
3763
3764                                 /* Link parallel detection - link is up */
3765                                 /* only if we have PCS_SYNC and not */
3766                                 /* receiving config code words */
3767                                 mac_status = tr32(MAC_STATUS);
3768                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3769                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3770                                         tg3_setup_flow_control(tp, 0, 0);
3771                                         current_link_up = 1;
3772                                         tp->tg3_flags2 |=
3773                                                 TG3_FLG2_PARALLEL_DETECT;
3774                                         tp->serdes_counter =
3775                                                 SERDES_PARALLEL_DET_TIMEOUT;
3776                                 } else
3777                                         goto restart_autoneg;
3778                         }
3779                 }
3780         } else {
3781                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3782                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3783         }
3784
3785 out:
3786         return current_link_up;
3787 }
3788
3789 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3790 {
3791         int current_link_up = 0;
3792
3793         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3794                 goto out;
3795
3796         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3797                 u32 txflags, rxflags;
3798                 int i;
3799
3800                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3801                         u32 local_adv = 0, remote_adv = 0;
3802
3803                         if (txflags & ANEG_CFG_PS1)
3804                                 local_adv |= ADVERTISE_1000XPAUSE;
3805                         if (txflags & ANEG_CFG_PS2)
3806                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3807
3808                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3809                                 remote_adv |= LPA_1000XPAUSE;
3810                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3811                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3812
3813                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3814
3815                         current_link_up = 1;
3816                 }
3817                 for (i = 0; i < 30; i++) {
3818                         udelay(20);
3819                         tw32_f(MAC_STATUS,
3820                                (MAC_STATUS_SYNC_CHANGED |
3821                                 MAC_STATUS_CFG_CHANGED));
3822                         udelay(40);
3823                         if ((tr32(MAC_STATUS) &
3824                              (MAC_STATUS_SYNC_CHANGED |
3825                               MAC_STATUS_CFG_CHANGED)) == 0)
3826                                 break;
3827                 }
3828
3829                 mac_status = tr32(MAC_STATUS);
3830                 if (current_link_up == 0 &&
3831                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3832                     !(mac_status & MAC_STATUS_RCVD_CFG))
3833                         current_link_up = 1;
3834         } else {
3835                 tg3_setup_flow_control(tp, 0, 0);
3836
3837                 /* Forcing 1000FD link up. */
3838                 current_link_up = 1;
3839
3840                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3841                 udelay(40);
3842
3843                 tw32_f(MAC_MODE, tp->mac_mode);
3844                 udelay(40);
3845         }
3846
3847 out:
3848         return current_link_up;
3849 }
3850
3851 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3852 {
3853         u32 orig_pause_cfg;
3854         u16 orig_active_speed;
3855         u8 orig_active_duplex;
3856         u32 mac_status;
3857         int current_link_up;
3858         int i;
3859
3860         orig_pause_cfg = tp->link_config.active_flowctrl;
3861         orig_active_speed = tp->link_config.active_speed;
3862         orig_active_duplex = tp->link_config.active_duplex;
3863
3864         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3865             netif_carrier_ok(tp->dev) &&
3866             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3867                 mac_status = tr32(MAC_STATUS);
3868                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3869                                MAC_STATUS_SIGNAL_DET |
3870                                MAC_STATUS_CFG_CHANGED |
3871                                MAC_STATUS_RCVD_CFG);
3872                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3873                                    MAC_STATUS_SIGNAL_DET)) {
3874                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3875                                             MAC_STATUS_CFG_CHANGED));
3876                         return 0;
3877                 }
3878         }
3879
3880         tw32_f(MAC_TX_AUTO_NEG, 0);
3881
3882         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3883         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3884         tw32_f(MAC_MODE, tp->mac_mode);
3885         udelay(40);
3886
3887         if (tp->phy_id == PHY_ID_BCM8002)
3888                 tg3_init_bcm8002(tp);
3889
3890         /* Enable link change event even when serdes polling.  */
3891         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3892         udelay(40);
3893
3894         current_link_up = 0;
3895         mac_status = tr32(MAC_STATUS);
3896
3897         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3898                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3899         else
3900                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3901
3902         tp->hw_status->status =
3903                 (SD_STATUS_UPDATED |
3904                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3905
3906         for (i = 0; i < 100; i++) {
3907                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3908                                     MAC_STATUS_CFG_CHANGED));
3909                 udelay(5);
3910                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3911                                          MAC_STATUS_CFG_CHANGED |
3912                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3913                         break;
3914         }
3915
3916         mac_status = tr32(MAC_STATUS);
3917         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3918                 current_link_up = 0;
3919                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3920                     tp->serdes_counter == 0) {
3921                         tw32_f(MAC_MODE, (tp->mac_mode |
3922                                           MAC_MODE_SEND_CONFIGS));
3923                         udelay(1);
3924                         tw32_f(MAC_MODE, tp->mac_mode);
3925                 }
3926         }
3927
3928         if (current_link_up == 1) {
3929                 tp->link_config.active_speed = SPEED_1000;
3930                 tp->link_config.active_duplex = DUPLEX_FULL;
3931                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3932                                     LED_CTRL_LNKLED_OVERRIDE |
3933                                     LED_CTRL_1000MBPS_ON));
3934         } else {
3935                 tp->link_config.active_speed = SPEED_INVALID;
3936                 tp->link_config.active_duplex = DUPLEX_INVALID;
3937                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3938                                     LED_CTRL_LNKLED_OVERRIDE |
3939                                     LED_CTRL_TRAFFIC_OVERRIDE));
3940         }
3941
3942         if (current_link_up != netif_carrier_ok(tp->dev)) {
3943                 if (current_link_up)
3944                         netif_carrier_on(tp->dev);
3945                 else
3946                         netif_carrier_off(tp->dev);
3947                 tg3_link_report(tp);
3948         } else {
3949                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3950                 if (orig_pause_cfg != now_pause_cfg ||
3951                     orig_active_speed != tp->link_config.active_speed ||
3952                     orig_active_duplex != tp->link_config.active_duplex)
3953                         tg3_link_report(tp);
3954         }
3955
3956         return 0;
3957 }
3958
3959 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3960 {
3961         int current_link_up, err = 0;
3962         u32 bmsr, bmcr;
3963         u16 current_speed;
3964         u8 current_duplex;
3965         u32 local_adv, remote_adv;
3966
3967         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3968         tw32_f(MAC_MODE, tp->mac_mode);
3969         udelay(40);
3970
3971         tw32(MAC_EVENT, 0);
3972
3973         tw32_f(MAC_STATUS,
3974              (MAC_STATUS_SYNC_CHANGED |
3975               MAC_STATUS_CFG_CHANGED |
3976               MAC_STATUS_MI_COMPLETION |
3977               MAC_STATUS_LNKSTATE_CHANGED));
3978         udelay(40);
3979
3980         if (force_reset)
3981                 tg3_phy_reset(tp);
3982
3983         current_link_up = 0;
3984         current_speed = SPEED_INVALID;
3985         current_duplex = DUPLEX_INVALID;
3986
3987         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3988         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3990                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3991                         bmsr |= BMSR_LSTATUS;
3992                 else
3993                         bmsr &= ~BMSR_LSTATUS;
3994         }
3995
3996         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3997
3998         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3999             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4000                 /* do nothing, just check for link up at the end */
4001         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4002                 u32 adv, new_adv;
4003
4004                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4005                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4006                                   ADVERTISE_1000XPAUSE |
4007                                   ADVERTISE_1000XPSE_ASYM |
4008                                   ADVERTISE_SLCT);
4009
4010                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4011
4012                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4013                         new_adv |= ADVERTISE_1000XHALF;
4014                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4015                         new_adv |= ADVERTISE_1000XFULL;
4016
4017                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4018                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4019                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4020                         tg3_writephy(tp, MII_BMCR, bmcr);
4021
4022                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4023                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4024                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4025
4026                         return err;
4027                 }
4028         } else {
4029                 u32 new_bmcr;
4030
4031                 bmcr &= ~BMCR_SPEED1000;
4032                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4033
4034                 if (tp->link_config.duplex == DUPLEX_FULL)
4035                         new_bmcr |= BMCR_FULLDPLX;
4036
4037                 if (new_bmcr != bmcr) {
4038                         /* BMCR_SPEED1000 is a reserved bit that needs
4039                          * to be set on write.
4040                          */
4041                         new_bmcr |= BMCR_SPEED1000;
4042
4043                         /* Force a linkdown */
4044                         if (netif_carrier_ok(tp->dev)) {
4045                                 u32 adv;
4046
4047                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4048                                 adv &= ~(ADVERTISE_1000XFULL |
4049                                          ADVERTISE_1000XHALF |
4050                                          ADVERTISE_SLCT);
4051                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4052                                 tg3_writephy(tp, MII_BMCR, bmcr |
4053                                                            BMCR_ANRESTART |
4054                                                            BMCR_ANENABLE);
4055                                 udelay(10);
4056                                 netif_carrier_off(tp->dev);
4057                         }
4058                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4059                         bmcr = new_bmcr;
4060                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4061                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4062                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4063                             ASIC_REV_5714) {
4064                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4065                                         bmsr |= BMSR_LSTATUS;
4066                                 else
4067                                         bmsr &= ~BMSR_LSTATUS;
4068                         }
4069                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4070                 }
4071         }
4072
4073         if (bmsr & BMSR_LSTATUS) {
4074                 current_speed = SPEED_1000;
4075                 current_link_up = 1;
4076                 if (bmcr & BMCR_FULLDPLX)
4077                         current_duplex = DUPLEX_FULL;
4078                 else
4079                         current_duplex = DUPLEX_HALF;
4080
4081                 local_adv = 0;
4082                 remote_adv = 0;
4083
4084                 if (bmcr & BMCR_ANENABLE) {
4085                         u32 common;
4086
4087                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4088                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4089                         common = local_adv & remote_adv;
4090                         if (common & (ADVERTISE_1000XHALF |
4091                                       ADVERTISE_1000XFULL)) {
4092                                 if (common & ADVERTISE_1000XFULL)
4093                                         current_duplex = DUPLEX_FULL;
4094                                 else
4095                                         current_duplex = DUPLEX_HALF;
4096                         }
4097                         else
4098                                 current_link_up = 0;
4099                 }
4100         }
4101
4102         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4103                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4104
4105         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4106         if (tp->link_config.active_duplex == DUPLEX_HALF)
4107                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4108
4109         tw32_f(MAC_MODE, tp->mac_mode);
4110         udelay(40);
4111
4112         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4113
4114         tp->link_config.active_speed = current_speed;
4115         tp->link_config.active_duplex = current_duplex;
4116
4117         if (current_link_up != netif_carrier_ok(tp->dev)) {
4118                 if (current_link_up)
4119                         netif_carrier_on(tp->dev);
4120                 else {
4121                         netif_carrier_off(tp->dev);
4122                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4123                 }
4124                 tg3_link_report(tp);
4125         }
4126         return err;
4127 }
4128
4129 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4130 {
4131         if (tp->serdes_counter) {
4132                 /* Give autoneg time to complete. */
4133                 tp->serdes_counter--;
4134                 return;
4135         }
4136         if (!netif_carrier_ok(tp->dev) &&
4137             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4138                 u32 bmcr;
4139
4140                 tg3_readphy(tp, MII_BMCR, &bmcr);
4141                 if (bmcr & BMCR_ANENABLE) {
4142                         u32 phy1, phy2;
4143
4144                         /* Select shadow register 0x1f */
4145                         tg3_writephy(tp, 0x1c, 0x7c00);
4146                         tg3_readphy(tp, 0x1c, &phy1);
4147
4148                         /* Select expansion interrupt status register */
4149                         tg3_writephy(tp, 0x17, 0x0f01);
4150                         tg3_readphy(tp, 0x15, &phy2);
4151                         tg3_readphy(tp, 0x15, &phy2);
4152
4153                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4154                                 /* We have signal detect and not receiving
4155                                  * config code words, link is up by parallel
4156                                  * detection.
4157                                  */
4158
4159                                 bmcr &= ~BMCR_ANENABLE;
4160                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4161                                 tg3_writephy(tp, MII_BMCR, bmcr);
4162                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4163                         }
4164                 }
4165         }
4166         else if (netif_carrier_ok(tp->dev) &&
4167                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4168                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4169                 u32 phy2;
4170
4171                 /* Select expansion interrupt status register */
4172                 tg3_writephy(tp, 0x17, 0x0f01);
4173                 tg3_readphy(tp, 0x15, &phy2);
4174                 if (phy2 & 0x20) {
4175                         u32 bmcr;
4176
4177                         /* Config code words received, turn on autoneg. */
4178                         tg3_readphy(tp, MII_BMCR, &bmcr);
4179                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4180
4181                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4182
4183                 }
4184         }
4185 }
4186
4187 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4188 {
4189         int err;
4190
4191         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4192                 err = tg3_setup_fiber_phy(tp, force_reset);
4193         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4194                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4195         } else {
4196                 err = tg3_setup_copper_phy(tp, force_reset);
4197         }
4198
4199         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4200                 u32 val, scale;
4201
4202                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4203                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4204                         scale = 65;
4205                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4206                         scale = 6;
4207                 else
4208                         scale = 12;
4209
4210                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4211                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4212                 tw32(GRC_MISC_CFG, val);
4213         }
4214
4215         if (tp->link_config.active_speed == SPEED_1000 &&
4216             tp->link_config.active_duplex == DUPLEX_HALF)
4217                 tw32(MAC_TX_LENGTHS,
4218                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4219                       (6 << TX_LENGTHS_IPG_SHIFT) |
4220                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4221         else
4222                 tw32(MAC_TX_LENGTHS,
4223                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4224                       (6 << TX_LENGTHS_IPG_SHIFT) |
4225                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4226
4227         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4228                 if (netif_carrier_ok(tp->dev)) {
4229                         tw32(HOSTCC_STAT_COAL_TICKS,
4230                              tp->coal.stats_block_coalesce_usecs);
4231                 } else {
4232                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4233                 }
4234         }
4235
4236         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4237                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4238                 if (!netif_carrier_ok(tp->dev))
4239                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4240                               tp->pwrmgmt_thresh;
4241                 else
4242                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4243                 tw32(PCIE_PWR_MGMT_THRESH, val);
4244         }
4245
4246         return err;
4247 }
4248
4249 /* This is called whenever we suspect that the system chipset is re-
4250  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4251  * is bogus tx completions. We try to recover by setting the
4252  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4253  * in the workqueue.
4254  */
4255 static void tg3_tx_recover(struct tg3 *tp)
4256 {
4257         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4258                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4259
4260         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4261                "mapped I/O cycles to the network device, attempting to "
4262                "recover. Please report the problem to the driver maintainer "
4263                "and include system chipset information.\n", tp->dev->name);
4264
4265         spin_lock(&tp->lock);
4266         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4267         spin_unlock(&tp->lock);
4268 }
4269
4270 static inline u32 tg3_tx_avail(struct tg3 *tp)
4271 {
4272         smp_mb();
4273         return (tp->tx_pending -
4274                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4275 }
4276
4277 /* Tigon3 never reports partial packet sends.  So we do not
4278  * need special logic to handle SKBs that have not had all
4279  * of their frags sent yet, like SunGEM does.
4280  */
4281 static void tg3_tx(struct tg3 *tp)
4282 {
4283         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4284         u32 sw_idx = tp->tx_cons;
4285
4286         while (sw_idx != hw_idx) {
4287                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4288                 struct sk_buff *skb = ri->skb;
4289                 int i, tx_bug = 0;
4290
4291                 if (unlikely(skb == NULL)) {
4292                         tg3_tx_recover(tp);
4293                         return;
4294                 }
4295
4296                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4297
4298                 ri->skb = NULL;
4299
4300                 sw_idx = NEXT_TX(sw_idx);
4301
4302                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4303                         ri = &tp->tx_buffers[sw_idx];
4304                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4305                                 tx_bug = 1;
4306                         sw_idx = NEXT_TX(sw_idx);
4307                 }
4308
4309                 dev_kfree_skb(skb);
4310
4311                 if (unlikely(tx_bug)) {
4312                         tg3_tx_recover(tp);
4313                         return;
4314                 }
4315         }
4316
4317         tp->tx_cons = sw_idx;
4318
4319         /* Need to make the tx_cons update visible to tg3_start_xmit()
4320          * before checking for netif_queue_stopped().  Without the
4321          * memory barrier, there is a small possibility that tg3_start_xmit()
4322          * will miss it and cause the queue to be stopped forever.
4323          */
4324         smp_mb();
4325
4326         if (unlikely(netif_queue_stopped(tp->dev) &&
4327                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4328                 netif_tx_lock(tp->dev);
4329                 if (netif_queue_stopped(tp->dev) &&
4330                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4331                         netif_wake_queue(tp->dev);
4332                 netif_tx_unlock(tp->dev);
4333         }
4334 }
4335
4336 /* Returns size of skb allocated or < 0 on error.
4337  *
4338  * We only need to fill in the address because the other members
4339  * of the RX descriptor are invariant, see tg3_init_rings.
4340  *
4341  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4342  * posting buffers we only dirty the first cache line of the RX
4343  * descriptor (containing the address).  Whereas for the RX status
4344  * buffers the cpu only reads the last cacheline of the RX descriptor
4345  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4346  */
4347 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4348                             int src_idx, u32 dest_idx_unmasked)
4349 {
4350         struct tg3_rx_buffer_desc *desc;
4351         struct ring_info *map, *src_map;
4352         struct sk_buff *skb;
4353         dma_addr_t mapping;
4354         int skb_size, dest_idx;
4355         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4356
4357         src_map = NULL;
4358         switch (opaque_key) {
4359         case RXD_OPAQUE_RING_STD:
4360                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4361                 desc = &tpr->rx_std[dest_idx];
4362                 map = &tpr->rx_std_buffers[dest_idx];
4363                 if (src_idx >= 0)
4364                         src_map = &tpr->rx_std_buffers[src_idx];
4365                 skb_size = tp->rx_pkt_map_sz;
4366                 break;
4367
4368         case RXD_OPAQUE_RING_JUMBO:
4369                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4370                 desc = &tpr->rx_jmb[dest_idx].std;
4371                 map = &tpr->rx_jmb_buffers[dest_idx];
4372                 if (src_idx >= 0)
4373                         src_map = &tpr->rx_jmb_buffers[src_idx];
4374                 skb_size = TG3_RX_JMB_MAP_SZ;
4375                 break;
4376
4377         default:
4378                 return -EINVAL;
4379         }
4380
4381         /* Do not overwrite any of the map or rp information
4382          * until we are sure we can commit to a new buffer.
4383          *
4384          * Callers depend upon this behavior and assume that
4385          * we leave everything unchanged if we fail.
4386          */
4387         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4388         if (skb == NULL)
4389                 return -ENOMEM;
4390
4391         skb_reserve(skb, tp->rx_offset);
4392
4393         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4394                                  PCI_DMA_FROMDEVICE);
4395
4396         map->skb = skb;
4397         pci_unmap_addr_set(map, mapping, mapping);
4398
4399         if (src_map != NULL)
4400                 src_map->skb = NULL;
4401
4402         desc->addr_hi = ((u64)mapping >> 32);
4403         desc->addr_lo = ((u64)mapping & 0xffffffff);
4404
4405         return skb_size;
4406 }
4407
4408 /* We only need to move over in the address because the other
4409  * members of the RX descriptor are invariant.  See notes above
4410  * tg3_alloc_rx_skb for full details.
4411  */
4412 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4413                            int src_idx, u32 dest_idx_unmasked)
4414 {
4415         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4416         struct ring_info *src_map, *dest_map;
4417         int dest_idx;
4418         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4419
4420         switch (opaque_key) {
4421         case RXD_OPAQUE_RING_STD:
4422                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4423                 dest_desc = &tpr->rx_std[dest_idx];
4424                 dest_map = &tpr->rx_std_buffers[dest_idx];
4425                 src_desc = &tpr->rx_std[src_idx];
4426                 src_map = &tpr->rx_std_buffers[src_idx];
4427                 break;
4428
4429         case RXD_OPAQUE_RING_JUMBO:
4430                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4431                 dest_desc = &tpr->rx_jmb[dest_idx].std;
4432                 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4433                 src_desc = &tpr->rx_jmb[src_idx].std;
4434                 src_map = &tpr->rx_jmb_buffers[src_idx];
4435                 break;
4436
4437         default:
4438                 return;
4439         }
4440
4441         dest_map->skb = src_map->skb;
4442         pci_unmap_addr_set(dest_map, mapping,
4443                            pci_unmap_addr(src_map, mapping));
4444         dest_desc->addr_hi = src_desc->addr_hi;
4445         dest_desc->addr_lo = src_desc->addr_lo;
4446
4447         src_map->skb = NULL;
4448 }
4449
4450 /* The RX ring scheme is composed of multiple rings which post fresh
4451  * buffers to the chip, and one special ring the chip uses to report
4452  * status back to the host.
4453  *
4454  * The special ring reports the status of received packets to the
4455  * host.  The chip does not write into the original descriptor the
4456  * RX buffer was obtained from.  The chip simply takes the original
4457  * descriptor as provided by the host, updates the status and length
4458  * field, then writes this into the next status ring entry.
4459  *
4460  * Each ring the host uses to post buffers to the chip is described
4461  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4462  * it is first placed into the on-chip ram.  When the packet's length
4463  * is known, it walks down the TG3_BDINFO entries to select the ring.
4464  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4465  * which is within the range of the new packet's length is chosen.
4466  *
4467  * The "separate ring for rx status" scheme may sound queer, but it makes
4468  * sense from a cache coherency perspective.  If only the host writes
4469  * to the buffer post rings, and only the chip writes to the rx status
4470  * rings, then cache lines never move beyond shared-modified state.
4471  * If both the host and chip were to write into the same ring, cache line
4472  * eviction could occur since both entities want it in an exclusive state.
4473  */
4474 static int tg3_rx(struct tg3 *tp, int budget)
4475 {
4476         u32 work_mask, rx_std_posted = 0;
4477         u32 sw_idx = tp->rx_rcb_ptr;
4478         u16 hw_idx;
4479         int received;
4480         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4481
4482         hw_idx = tp->hw_status->idx[0].rx_producer;
4483         /*
4484          * We need to order the read of hw_idx and the read of
4485          * the opaque cookie.
4486          */
4487         rmb();
4488         work_mask = 0;
4489         received = 0;
4490         while (sw_idx != hw_idx && budget > 0) {
4491                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4492                 unsigned int len;
4493                 struct sk_buff *skb;
4494                 dma_addr_t dma_addr;
4495                 u32 opaque_key, desc_idx, *post_ptr;
4496
4497                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4498                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4499                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4500                         struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4501                         dma_addr = pci_unmap_addr(ri, mapping);
4502                         skb = ri->skb;
4503                         post_ptr = &tpr->rx_std_ptr;
4504                         rx_std_posted++;
4505                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4506                         struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4507                         dma_addr = pci_unmap_addr(ri, mapping);
4508                         skb = ri->skb;
4509                         post_ptr = &tpr->rx_jmb_ptr;
4510                 } else
4511                         goto next_pkt_nopost;
4512
4513                 work_mask |= opaque_key;
4514
4515                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4516                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4517                 drop_it:
4518                         tg3_recycle_rx(tp, opaque_key,
4519                                        desc_idx, *post_ptr);
4520                 drop_it_no_recycle:
4521                         /* Other statistics kept track of by card. */
4522                         tp->net_stats.rx_dropped++;
4523                         goto next_pkt;
4524                 }
4525
4526                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4527                       ETH_FCS_LEN;
4528
4529                 if (len > RX_COPY_THRESHOLD
4530                         && tp->rx_offset == NET_IP_ALIGN
4531                         /* rx_offset will likely not equal NET_IP_ALIGN
4532                          * if this is a 5701 card running in PCI-X mode
4533                          * [see tg3_get_invariants()]
4534                          */
4535                 ) {
4536                         int skb_size;
4537
4538                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4539                                                     desc_idx, *post_ptr);
4540                         if (skb_size < 0)
4541                                 goto drop_it;
4542
4543                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4544                                          PCI_DMA_FROMDEVICE);
4545
4546                         skb_put(skb, len);
4547                 } else {
4548                         struct sk_buff *copy_skb;
4549
4550                         tg3_recycle_rx(tp, opaque_key,
4551                                        desc_idx, *post_ptr);
4552
4553                         copy_skb = netdev_alloc_skb(tp->dev,
4554                                                     len + TG3_RAW_IP_ALIGN);
4555                         if (copy_skb == NULL)
4556                                 goto drop_it_no_recycle;
4557
4558                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4559                         skb_put(copy_skb, len);
4560                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4561                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4562                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4563
4564                         /* We'll reuse the original ring buffer. */
4565                         skb = copy_skb;
4566                 }
4567
4568                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4569                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4570                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4571                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4572                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4573                 else
4574                         skb->ip_summed = CHECKSUM_NONE;
4575
4576                 skb->protocol = eth_type_trans(skb, tp->dev);
4577
4578                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4579                     skb->protocol != htons(ETH_P_8021Q)) {
4580                         dev_kfree_skb(skb);
4581                         goto next_pkt;
4582                 }
4583
4584 #if TG3_VLAN_TAG_USED
4585                 if (tp->vlgrp != NULL &&
4586                     desc->type_flags & RXD_FLAG_VLAN) {
4587                         vlan_gro_receive(&tp->napi[0].napi, tp->vlgrp,
4588                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4589                 } else
4590 #endif
4591                         napi_gro_receive(&tp->napi[0].napi, skb);
4592
4593                 received++;
4594                 budget--;
4595
4596 next_pkt:
4597                 (*post_ptr)++;
4598
4599                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4600                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4601
4602                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4603                                      TG3_64BIT_REG_LOW, idx);
4604                         work_mask &= ~RXD_OPAQUE_RING_STD;
4605                         rx_std_posted = 0;
4606                 }
4607 next_pkt_nopost:
4608                 sw_idx++;
4609                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4610
4611                 /* Refresh hw_idx to see if there is new work */
4612                 if (sw_idx == hw_idx) {
4613                         hw_idx = tp->hw_status->idx[0].rx_producer;
4614                         rmb();
4615                 }
4616         }
4617
4618         /* ACK the status ring. */
4619         tp->rx_rcb_ptr = sw_idx;
4620         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4621
4622         /* Refill RX ring(s). */
4623         if (work_mask & RXD_OPAQUE_RING_STD) {
4624                 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4625                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4626                              sw_idx);
4627         }
4628         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4629                 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4630                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4631                              sw_idx);
4632         }
4633         mmiowb();
4634
4635         return received;
4636 }
4637
4638 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4639 {
4640         struct tg3_hw_status *sblk = tp->hw_status;
4641
4642         /* handle link change and other phy events */
4643         if (!(tp->tg3_flags &
4644               (TG3_FLAG_USE_LINKCHG_REG |
4645                TG3_FLAG_POLL_SERDES))) {
4646                 if (sblk->status & SD_STATUS_LINK_CHG) {
4647                         sblk->status = SD_STATUS_UPDATED |
4648                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4649                         spin_lock(&tp->lock);
4650                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4651                                 tw32_f(MAC_STATUS,
4652                                      (MAC_STATUS_SYNC_CHANGED |
4653                                       MAC_STATUS_CFG_CHANGED |
4654                                       MAC_STATUS_MI_COMPLETION |
4655                                       MAC_STATUS_LNKSTATE_CHANGED));
4656                                 udelay(40);
4657                         } else
4658                                 tg3_setup_phy(tp, 0);
4659                         spin_unlock(&tp->lock);
4660                 }
4661         }
4662
4663         /* run TX completion thread */
4664         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4665                 tg3_tx(tp);
4666                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4667                         return work_done;
4668         }
4669
4670         /* run RX thread, within the bounds set by NAPI.
4671          * All RX "locking" is done by ensuring outside
4672          * code synchronizes with tg3->napi.poll()
4673          */
4674         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4675                 work_done += tg3_rx(tp, budget - work_done);
4676
4677         return work_done;
4678 }
4679
4680 static int tg3_poll(struct napi_struct *napi, int budget)
4681 {
4682         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4683         struct tg3 *tp = tnapi->tp;
4684         int work_done = 0;
4685         struct tg3_hw_status *sblk = tp->hw_status;
4686
4687         while (1) {
4688                 work_done = tg3_poll_work(tp, work_done, budget);
4689
4690                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4691                         goto tx_recovery;
4692
4693                 if (unlikely(work_done >= budget))
4694                         break;
4695
4696                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4697                         /* tp->last_tag is used in tg3_restart_ints() below
4698                          * to tell the hw how much work has been processed,
4699                          * so we must read it before checking for more work.
4700                          */
4701                         tp->last_tag = sblk->status_tag;
4702                         tp->last_irq_tag = tp->last_tag;
4703                         rmb();
4704                 } else
4705                         sblk->status &= ~SD_STATUS_UPDATED;
4706
4707                 if (likely(!tg3_has_work(tp))) {
4708                         napi_complete(napi);
4709                         tg3_restart_ints(tp);
4710                         break;
4711                 }
4712         }
4713
4714         return work_done;
4715
4716 tx_recovery:
4717         /* work_done is guaranteed to be less than budget. */
4718         napi_complete(napi);
4719         schedule_work(&tp->reset_task);
4720         return work_done;
4721 }
4722
4723 static void tg3_irq_quiesce(struct tg3 *tp)
4724 {
4725         BUG_ON(tp->irq_sync);
4726
4727         tp->irq_sync = 1;
4728         smp_mb();
4729
4730         synchronize_irq(tp->pdev->irq);
4731 }
4732
4733 static inline int tg3_irq_sync(struct tg3 *tp)
4734 {
4735         return tp->irq_sync;
4736 }
4737
4738 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4739  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4740  * with as well.  Most of the time, this is not necessary except when
4741  * shutting down the device.
4742  */
4743 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4744 {
4745         spin_lock_bh(&tp->lock);
4746         if (irq_sync)
4747                 tg3_irq_quiesce(tp);
4748 }
4749
4750 static inline void tg3_full_unlock(struct tg3 *tp)
4751 {
4752         spin_unlock_bh(&tp->lock);
4753 }
4754
4755 /* One-shot MSI handler - Chip automatically disables interrupt
4756  * after sending MSI so driver doesn't have to do it.
4757  */
4758 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4759 {
4760         struct tg3_napi *tnapi = dev_id;
4761         struct tg3 *tp = tnapi->tp;
4762
4763         prefetch(tp->hw_status);
4764         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4765
4766         if (likely(!tg3_irq_sync(tp)))
4767                 napi_schedule(&tnapi->napi);
4768
4769         return IRQ_HANDLED;
4770 }
4771
4772 /* MSI ISR - No need to check for interrupt sharing and no need to
4773  * flush status block and interrupt mailbox. PCI ordering rules
4774  * guarantee that MSI will arrive after the status block.
4775  */
4776 static irqreturn_t tg3_msi(int irq, void *dev_id)
4777 {
4778         struct tg3_napi *tnapi = dev_id;
4779         struct tg3 *tp = tnapi->tp;
4780
4781         prefetch(tp->hw_status);
4782         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4783         /*
4784          * Writing any value to intr-mbox-0 clears PCI INTA# and
4785          * chip-internal interrupt pending events.
4786          * Writing non-zero to intr-mbox-0 additional tells the
4787          * NIC to stop sending us irqs, engaging "in-intr-handler"
4788          * event coalescing.
4789          */
4790         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4791         if (likely(!tg3_irq_sync(tp)))
4792                 napi_schedule(&tnapi->napi);
4793
4794         return IRQ_RETVAL(1);
4795 }
4796
4797 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4798 {
4799         struct tg3_napi *tnapi = dev_id;
4800         struct tg3 *tp = tnapi->tp;
4801         struct tg3_hw_status *sblk = tp->hw_status;
4802         unsigned int handled = 1;
4803
4804         /* In INTx mode, it is possible for the interrupt to arrive at
4805          * the CPU before the status block posted prior to the interrupt.
4806          * Reading the PCI State register will confirm whether the
4807          * interrupt is ours and will flush the status block.
4808          */
4809         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4810                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4811                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4812                         handled = 0;
4813                         goto out;
4814                 }
4815         }
4816
4817         /*
4818          * Writing any value to intr-mbox-0 clears PCI INTA# and
4819          * chip-internal interrupt pending events.
4820          * Writing non-zero to intr-mbox-0 additional tells the
4821          * NIC to stop sending us irqs, engaging "in-intr-handler"
4822          * event coalescing.
4823          *
4824          * Flush the mailbox to de-assert the IRQ immediately to prevent
4825          * spurious interrupts.  The flush impacts performance but
4826          * excessive spurious interrupts can be worse in some cases.
4827          */
4828         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4829         if (tg3_irq_sync(tp))
4830                 goto out;
4831         sblk->status &= ~SD_STATUS_UPDATED;
4832         if (likely(tg3_has_work(tp))) {
4833                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4834                 napi_schedule(&tnapi->napi);
4835         } else {
4836                 /* No work, shared interrupt perhaps?  re-enable
4837                  * interrupts, and flush that PCI write
4838                  */
4839                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4840                                0x00000000);
4841         }
4842 out:
4843         return IRQ_RETVAL(handled);
4844 }
4845
4846 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4847 {
4848         struct tg3_napi *tnapi = dev_id;
4849         struct tg3 *tp = tnapi->tp;
4850         struct tg3_hw_status *sblk = tp->hw_status;
4851         unsigned int handled = 1;
4852
4853         /* In INTx mode, it is possible for the interrupt to arrive at
4854          * the CPU before the status block posted prior to the interrupt.
4855          * Reading the PCI State register will confirm whether the
4856          * interrupt is ours and will flush the status block.
4857          */
4858         if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4859                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4860                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4861                         handled = 0;
4862                         goto out;
4863                 }
4864         }
4865
4866         /*
4867          * writing any value to intr-mbox-0 clears PCI INTA# and
4868          * chip-internal interrupt pending events.
4869          * writing non-zero to intr-mbox-0 additional tells the
4870          * NIC to stop sending us irqs, engaging "in-intr-handler"
4871          * event coalescing.
4872          *
4873          * Flush the mailbox to de-assert the IRQ immediately to prevent
4874          * spurious interrupts.  The flush impacts performance but
4875          * excessive spurious interrupts can be worse in some cases.
4876          */
4877         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4878
4879         /*
4880          * In a shared interrupt configuration, sometimes other devices'
4881          * interrupts will scream.  We record the current status tag here
4882          * so that the above check can report that the screaming interrupts
4883          * are unhandled.  Eventually they will be silenced.
4884          */
4885         tp->last_irq_tag = sblk->status_tag;
4886
4887         if (tg3_irq_sync(tp))
4888                 goto out;
4889
4890         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4891
4892         napi_schedule(&tnapi->napi);
4893
4894 out:
4895         return IRQ_RETVAL(handled);
4896 }
4897
4898 /* ISR for interrupt test */
4899 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4900 {
4901         struct tg3_napi *tnapi = dev_id;
4902         struct tg3 *tp = tnapi->tp;
4903         struct tg3_hw_status *sblk = tp->hw_status;
4904
4905         if ((sblk->status & SD_STATUS_UPDATED) ||
4906             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4907                 tg3_disable_ints(tp);
4908                 return IRQ_RETVAL(1);
4909         }
4910         return IRQ_RETVAL(0);
4911 }
4912
4913 static int tg3_init_hw(struct tg3 *, int);
4914 static int tg3_halt(struct tg3 *, int, int);
4915
4916 /* Restart hardware after configuration changes, self-test, etc.
4917  * Invoked with tp->lock held.
4918  */
4919 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4920         __releases(tp->lock)
4921         __acquires(tp->lock)
4922 {
4923         int err;
4924
4925         err = tg3_init_hw(tp, reset_phy);
4926         if (err) {
4927                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4928                        "aborting.\n", tp->dev->name);
4929                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4930                 tg3_full_unlock(tp);
4931                 del_timer_sync(&tp->timer);
4932                 tp->irq_sync = 0;
4933                 napi_enable(&tp->napi[0].napi);
4934                 dev_close(tp->dev);
4935                 tg3_full_lock(tp, 0);
4936         }
4937         return err;
4938 }
4939
4940 #ifdef CONFIG_NET_POLL_CONTROLLER
4941 static void tg3_poll_controller(struct net_device *dev)
4942 {
4943         struct tg3 *tp = netdev_priv(dev);
4944
4945         tg3_interrupt(tp->pdev->irq, dev);
4946 }
4947 #endif
4948
4949 static void tg3_reset_task(struct work_struct *work)
4950 {
4951         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4952         int err;
4953         unsigned int restart_timer;
4954
4955         tg3_full_lock(tp, 0);
4956
4957         if (!netif_running(tp->dev)) {
4958                 tg3_full_unlock(tp);
4959                 return;
4960         }
4961
4962         tg3_full_unlock(tp);
4963
4964         tg3_phy_stop(tp);
4965
4966         tg3_netif_stop(tp);
4967
4968         tg3_full_lock(tp, 1);
4969
4970         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4971         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4972
4973         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4974                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4975                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4976                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4977                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4978         }
4979
4980         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4981         err = tg3_init_hw(tp, 1);
4982         if (err)
4983                 goto out;
4984
4985         tg3_netif_start(tp);
4986
4987         if (restart_timer)
4988                 mod_timer(&tp->timer, jiffies + 1);
4989
4990 out:
4991         tg3_full_unlock(tp);
4992
4993         if (!err)
4994                 tg3_phy_start(tp);
4995 }
4996
4997 static void tg3_dump_short_state(struct tg3 *tp)
4998 {
4999         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5000                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5001         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5002                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5003 }
5004
5005 static void tg3_tx_timeout(struct net_device *dev)
5006 {
5007         struct tg3 *tp = netdev_priv(dev);
5008
5009         if (netif_msg_tx_err(tp)) {
5010                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5011                        dev->name);
5012                 tg3_dump_short_state(tp);
5013         }
5014
5015         schedule_work(&tp->reset_task);
5016 }
5017
5018 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5019 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5020 {
5021         u32 base = (u32) mapping & 0xffffffff;
5022
5023         return ((base > 0xffffdcc0) &&
5024                 (base + len + 8 < base));
5025 }
5026
5027 /* Test for DMA addresses > 40-bit */
5028 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5029                                           int len)
5030 {
5031 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5032         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5033                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5034         return 0;
5035 #else
5036         return 0;
5037 #endif
5038 }
5039
5040 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
5041
5042 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5043 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5044                                        u32 last_plus_one, u32 *start,
5045                                        u32 base_flags, u32 mss)
5046 {
5047         struct sk_buff *new_skb;
5048         dma_addr_t new_addr = 0;
5049         u32 entry = *start;
5050         int i, ret = 0;
5051
5052         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5053                 new_skb = skb_copy(skb, GFP_ATOMIC);
5054         else {
5055                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5056
5057                 new_skb = skb_copy_expand(skb,
5058                                           skb_headroom(skb) + more_headroom,
5059                                           skb_tailroom(skb), GFP_ATOMIC);
5060         }
5061
5062         if (!new_skb) {
5063                 ret = -1;
5064         } else {
5065                 /* New SKB is guaranteed to be linear. */
5066                 entry = *start;
5067                 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5068                 new_addr = skb_shinfo(new_skb)->dma_head;
5069
5070                 /* Make sure new skb does not cross any 4G boundaries.
5071                  * Drop the packet if it does.
5072                  */
5073                 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5074                         if (!ret)
5075                                 skb_dma_unmap(&tp->pdev->dev, new_skb,
5076                                               DMA_TO_DEVICE);
5077                         ret = -1;
5078                         dev_kfree_skb(new_skb);
5079                         new_skb = NULL;
5080                 } else {
5081                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
5082                                     base_flags, 1 | (mss << 1));
5083                         *start = NEXT_TX(entry);
5084                 }
5085         }
5086
5087         /* Now clean up the sw ring entries. */
5088         i = 0;
5089         while (entry != last_plus_one) {
5090                 if (i == 0) {
5091                         tp->tx_buffers[entry].skb = new_skb;
5092                 } else {
5093                         tp->tx_buffers[entry].skb = NULL;
5094                 }
5095                 entry = NEXT_TX(entry);
5096                 i++;
5097         }
5098
5099         skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5100         dev_kfree_skb(skb);
5101
5102         return ret;
5103 }
5104
5105 static void tg3_set_txd(struct tg3 *tp, int entry,
5106                         dma_addr_t mapping, int len, u32 flags,
5107                         u32 mss_and_is_end)
5108 {
5109         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5110         int is_end = (mss_and_is_end & 0x1);
5111         u32 mss = (mss_and_is_end >> 1);
5112         u32 vlan_tag = 0;
5113
5114         if (is_end)
5115                 flags |= TXD_FLAG_END;
5116         if (flags & TXD_FLAG_VLAN) {
5117                 vlan_tag = flags >> 16;
5118                 flags &= 0xffff;
5119         }
5120         vlan_tag |= (mss << TXD_MSS_SHIFT);
5121
5122         txd->addr_hi = ((u64) mapping >> 32);
5123         txd->addr_lo = ((u64) mapping & 0xffffffff);
5124         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5125         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5126 }
5127
5128 /* hard_start_xmit for devices that don't have any bugs and
5129  * support TG3_FLG2_HW_TSO_2 only.
5130  */
5131 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5132 {
5133         struct tg3 *tp = netdev_priv(dev);
5134         u32 len, entry, base_flags, mss;
5135         struct skb_shared_info *sp;
5136         dma_addr_t mapping;
5137
5138         len = skb_headlen(skb);
5139
5140         /* We are running in BH disabled context with netif_tx_lock
5141          * and TX reclaim runs via tp->napi.poll inside of a software
5142          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5143          * no IRQ context deadlocks to worry about either.  Rejoice!
5144          */
5145         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5146                 if (!netif_queue_stopped(dev)) {
5147                         netif_stop_queue(dev);
5148
5149                         /* This is a hard error, log it. */
5150                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5151                                "queue awake!\n", dev->name);
5152                 }
5153                 return NETDEV_TX_BUSY;
5154         }
5155
5156         entry = tp->tx_prod;
5157         base_flags = 0;
5158         mss = 0;
5159         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5160                 int tcp_opt_len, ip_tcp_len;
5161
5162                 if (skb_header_cloned(skb) &&
5163                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5164                         dev_kfree_skb(skb);
5165                         goto out_unlock;
5166                 }
5167
5168                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5169                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5170                 else {
5171                         struct iphdr *iph = ip_hdr(skb);
5172
5173                         tcp_opt_len = tcp_optlen(skb);
5174                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5175
5176                         iph->check = 0;
5177                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5178                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
5179                 }
5180
5181                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5182                                TXD_FLAG_CPU_POST_DMA);
5183
5184                 tcp_hdr(skb)->check = 0;
5185
5186         }
5187         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5188                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5189 #if TG3_VLAN_TAG_USED
5190         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5191                 base_flags |= (TXD_FLAG_VLAN |
5192                                (vlan_tx_tag_get(skb) << 16));
5193 #endif
5194
5195         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5196                 dev_kfree_skb(skb);
5197                 goto out_unlock;
5198         }
5199
5200         sp = skb_shinfo(skb);
5201
5202         mapping = sp->dma_head;
5203
5204         tp->tx_buffers[entry].skb = skb;
5205
5206         tg3_set_txd(tp, entry, mapping, len, base_flags,
5207                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5208
5209         entry = NEXT_TX(entry);
5210
5211         /* Now loop through additional data fragments, and queue them. */
5212         if (skb_shinfo(skb)->nr_frags > 0) {
5213                 unsigned int i, last;
5214
5215                 last = skb_shinfo(skb)->nr_frags - 1;
5216                 for (i = 0; i <= last; i++) {
5217                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5218
5219                         len = frag->size;
5220                         mapping = sp->dma_maps[i];
5221                         tp->tx_buffers[entry].skb = NULL;
5222
5223                         tg3_set_txd(tp, entry, mapping, len,
5224                                     base_flags, (i == last) | (mss << 1));
5225
5226                         entry = NEXT_TX(entry);
5227                 }
5228         }
5229
5230         /* Packets are ready, update Tx producer idx local and on card. */
5231         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5232
5233         tp->tx_prod = entry;
5234         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5235                 netif_stop_queue(dev);
5236                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5237                         netif_wake_queue(tp->dev);
5238         }
5239
5240 out_unlock:
5241         mmiowb();
5242
5243         return NETDEV_TX_OK;
5244 }
5245
5246 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5247
5248 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5249  * TSO header is greater than 80 bytes.
5250  */
5251 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5252 {
5253         struct sk_buff *segs, *nskb;
5254
5255         /* Estimate the number of fragments in the worst case */
5256         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5257                 netif_stop_queue(tp->dev);
5258                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5259                         return NETDEV_TX_BUSY;
5260
5261                 netif_wake_queue(tp->dev);
5262         }
5263
5264         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5265         if (IS_ERR(segs))
5266                 goto tg3_tso_bug_end;
5267
5268         do {
5269                 nskb = segs;
5270                 segs = segs->next;
5271                 nskb->next = NULL;
5272                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5273         } while (segs);
5274
5275 tg3_tso_bug_end:
5276         dev_kfree_skb(skb);
5277
5278         return NETDEV_TX_OK;
5279 }
5280
5281 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5282  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5283  */
5284 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5285 {
5286         struct tg3 *tp = netdev_priv(dev);
5287         u32 len, entry, base_flags, mss;
5288         struct skb_shared_info *sp;
5289         int would_hit_hwbug;
5290         dma_addr_t mapping;
5291
5292         len = skb_headlen(skb);
5293
5294         /* We are running in BH disabled context with netif_tx_lock
5295          * and TX reclaim runs via tp->napi.poll inside of a software
5296          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5297          * no IRQ context deadlocks to worry about either.  Rejoice!
5298          */
5299         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5300                 if (!netif_queue_stopped(dev)) {
5301                         netif_stop_queue(dev);
5302
5303                         /* This is a hard error, log it. */
5304                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5305                                "queue awake!\n", dev->name);
5306                 }
5307                 return NETDEV_TX_BUSY;
5308         }
5309
5310         entry = tp->tx_prod;
5311         base_flags = 0;
5312         if (skb->ip_summed == CHECKSUM_PARTIAL)
5313                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5314         mss = 0;
5315         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5316                 struct iphdr *iph;
5317                 int tcp_opt_len, ip_tcp_len, hdr_len;
5318
5319                 if (skb_header_cloned(skb) &&
5320                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5321                         dev_kfree_skb(skb);
5322                         goto out_unlock;
5323                 }
5324
5325                 tcp_opt_len = tcp_optlen(skb);
5326                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5327
5328                 hdr_len = ip_tcp_len + tcp_opt_len;
5329                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5330                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5331                         return (tg3_tso_bug(tp, skb));
5332
5333                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5334                                TXD_FLAG_CPU_POST_DMA);
5335
5336                 iph = ip_hdr(skb);
5337                 iph->check = 0;
5338                 iph->tot_len = htons(mss + hdr_len);
5339                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5340                         tcp_hdr(skb)->check = 0;
5341                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5342                 } else
5343                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5344                                                                  iph->daddr, 0,
5345                                                                  IPPROTO_TCP,
5346                                                                  0);
5347
5348                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5349                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5350                         if (tcp_opt_len || iph->ihl > 5) {
5351                                 int tsflags;
5352
5353                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5354                                 mss |= (tsflags << 11);
5355                         }
5356                 } else {
5357                         if (tcp_opt_len || iph->ihl > 5) {
5358                                 int tsflags;
5359
5360                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5361                                 base_flags |= tsflags << 12;
5362                         }
5363                 }
5364         }
5365 #if TG3_VLAN_TAG_USED
5366         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5367                 base_flags |= (TXD_FLAG_VLAN |
5368                                (vlan_tx_tag_get(skb) << 16));
5369 #endif
5370
5371         if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5372                 dev_kfree_skb(skb);
5373                 goto out_unlock;
5374         }
5375
5376         sp = skb_shinfo(skb);
5377
5378         mapping = sp->dma_head;
5379
5380         tp->tx_buffers[entry].skb = skb;
5381
5382         would_hit_hwbug = 0;
5383
5384         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5385                 would_hit_hwbug = 1;
5386         else if (tg3_4g_overflow_test(mapping, len))
5387                 would_hit_hwbug = 1;
5388
5389         tg3_set_txd(tp, entry, mapping, len, base_flags,
5390                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5391
5392         entry = NEXT_TX(entry);
5393
5394         /* Now loop through additional data fragments, and queue them. */
5395         if (skb_shinfo(skb)->nr_frags > 0) {
5396                 unsigned int i, last;
5397
5398                 last = skb_shinfo(skb)->nr_frags - 1;
5399                 for (i = 0; i <= last; i++) {
5400                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5401
5402                         len = frag->size;
5403                         mapping = sp->dma_maps[i];
5404
5405                         tp->tx_buffers[entry].skb = NULL;
5406
5407                         if (tg3_4g_overflow_test(mapping, len))
5408                                 would_hit_hwbug = 1;
5409
5410                         if (tg3_40bit_overflow_test(tp, mapping, len))
5411                                 would_hit_hwbug = 1;
5412
5413                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5414                                 tg3_set_txd(tp, entry, mapping, len,
5415                                             base_flags, (i == last)|(mss << 1));
5416                         else
5417                                 tg3_set_txd(tp, entry, mapping, len,
5418                                             base_flags, (i == last));
5419
5420                         entry = NEXT_TX(entry);
5421                 }
5422         }
5423
5424         if (would_hit_hwbug) {
5425                 u32 last_plus_one = entry;
5426                 u32 start;
5427
5428                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5429                 start &= (TG3_TX_RING_SIZE - 1);
5430
5431                 /* If the workaround fails due to memory/mapping
5432                  * failure, silently drop this packet.
5433                  */
5434                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5435                                                 &start, base_flags, mss))
5436                         goto out_unlock;
5437
5438                 entry = start;
5439         }
5440
5441         /* Packets are ready, update Tx producer idx local and on card. */
5442         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5443
5444         tp->tx_prod = entry;
5445         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5446                 netif_stop_queue(dev);
5447                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5448                         netif_wake_queue(tp->dev);
5449         }
5450
5451 out_unlock:
5452         mmiowb();
5453
5454         return NETDEV_TX_OK;
5455 }
5456
5457 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5458                                int new_mtu)
5459 {
5460         dev->mtu = new_mtu;
5461
5462         if (new_mtu > ETH_DATA_LEN) {
5463                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5464                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5465                         ethtool_op_set_tso(dev, 0);
5466                 }
5467                 else
5468                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5469         } else {
5470                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5471                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5472                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5473         }
5474 }
5475
5476 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5477 {
5478         struct tg3 *tp = netdev_priv(dev);
5479         int err;
5480
5481         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5482                 return -EINVAL;
5483
5484         if (!netif_running(dev)) {
5485                 /* We'll just catch it later when the
5486                  * device is up'd.
5487                  */
5488                 tg3_set_mtu(dev, tp, new_mtu);
5489                 return 0;
5490         }
5491
5492         tg3_phy_stop(tp);
5493
5494         tg3_netif_stop(tp);
5495
5496         tg3_full_lock(tp, 1);
5497
5498         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5499
5500         tg3_set_mtu(dev, tp, new_mtu);
5501
5502         err = tg3_restart_hw(tp, 0);
5503
5504         if (!err)
5505                 tg3_netif_start(tp);
5506
5507         tg3_full_unlock(tp);
5508
5509         if (!err)
5510                 tg3_phy_start(tp);
5511
5512         return err;
5513 }
5514
5515 static void tg3_rx_prodring_free(struct tg3 *tp,
5516                                  struct tg3_rx_prodring_set *tpr)
5517 {
5518         struct ring_info *rxp;
5519         int i;
5520
5521         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5522                 rxp = &tpr->rx_std_buffers[i];
5523
5524                 if (rxp->skb == NULL)
5525                         continue;
5526
5527                 pci_unmap_single(tp->pdev,
5528                                  pci_unmap_addr(rxp, mapping),
5529                                  tp->rx_pkt_map_sz,
5530                                  PCI_DMA_FROMDEVICE);
5531                 dev_kfree_skb_any(rxp->skb);
5532                 rxp->skb = NULL;
5533         }
5534
5535         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5536                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5537                         rxp = &tpr->rx_jmb_buffers[i];
5538
5539                         if (rxp->skb == NULL)
5540                                 continue;
5541
5542                         pci_unmap_single(tp->pdev,
5543                                          pci_unmap_addr(rxp, mapping),
5544                                          TG3_RX_JMB_MAP_SZ,
5545                                          PCI_DMA_FROMDEVICE);
5546                         dev_kfree_skb_any(rxp->skb);
5547                         rxp->skb = NULL;
5548                 }
5549         }
5550 }
5551
5552 /* Initialize tx/rx rings for packet processing.
5553  *
5554  * The chip has been shut down and the driver detached from
5555  * the networking, so no interrupts or new tx packets will
5556  * end up in the driver.  tp->{tx,}lock are held and thus
5557  * we may not sleep.
5558  */
5559 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5560                                  struct tg3_rx_prodring_set *tpr)
5561 {
5562         u32 i, rx_pkt_dma_sz;
5563
5564         /* Zero out all descriptors. */
5565         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5566
5567         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5568         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5569             tp->dev->mtu > ETH_DATA_LEN)
5570                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5571         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5572
5573         /* Initialize invariants of the rings, we only set this
5574          * stuff once.  This works because the card does not
5575          * write into the rx buffer posting rings.
5576          */
5577         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5578                 struct tg3_rx_buffer_desc *rxd;
5579
5580                 rxd = &tpr->rx_std[i];
5581                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5582                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5583                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5584                                (i << RXD_OPAQUE_INDEX_SHIFT));
5585         }
5586
5587         /* Now allocate fresh SKBs for each rx ring. */
5588         for (i = 0; i < tp->rx_pending; i++) {
5589                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5590                         printk(KERN_WARNING PFX
5591                                "%s: Using a smaller RX standard ring, "
5592                                "only %d out of %d buffers were allocated "
5593                                "successfully.\n",
5594                                tp->dev->name, i, tp->rx_pending);
5595                         if (i == 0)
5596                                 goto initfail;
5597                         tp->rx_pending = i;
5598                         break;
5599                 }
5600         }
5601
5602         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5603                 goto done;
5604
5605         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5606
5607         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5608                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5609                         struct tg3_rx_buffer_desc *rxd;
5610
5611                         rxd = &tpr->rx_jmb[i].std;
5612                         rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5613                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5614                                 RXD_FLAG_JUMBO;
5615                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5616                                (i << RXD_OPAQUE_INDEX_SHIFT));
5617                 }
5618
5619                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5620                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5621                                              -1, i) < 0) {
5622                                 printk(KERN_WARNING PFX
5623                                        "%s: Using a smaller RX jumbo ring, "
5624                                        "only %d out of %d buffers were "
5625                                        "allocated successfully.\n",
5626                                        tp->dev->name, i, tp->rx_jumbo_pending);
5627                                 if (i == 0)
5628                                         goto initfail;
5629                                 tp->rx_jumbo_pending = i;
5630                                 break;
5631                         }
5632                 }
5633         }
5634
5635 done:
5636         return 0;
5637
5638 initfail:
5639         tg3_rx_prodring_free(tp, tpr);
5640         return -ENOMEM;
5641 }
5642
5643 static void tg3_rx_prodring_fini(struct tg3 *tp,
5644                                  struct tg3_rx_prodring_set *tpr)
5645 {
5646         kfree(tpr->rx_std_buffers);
5647         tpr->rx_std_buffers = NULL;
5648         kfree(tpr->rx_jmb_buffers);
5649         tpr->rx_jmb_buffers = NULL;
5650         if (tpr->rx_std) {
5651                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5652                                     tpr->rx_std, tpr->rx_std_mapping);
5653                 tpr->rx_std = NULL;
5654         }
5655         if (tpr->rx_jmb) {
5656                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5657                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
5658                 tpr->rx_jmb = NULL;
5659         }
5660 }
5661
5662 static int tg3_rx_prodring_init(struct tg3 *tp,
5663                                 struct tg3_rx_prodring_set *tpr)
5664 {
5665         tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5666                                       TG3_RX_RING_SIZE, GFP_KERNEL);
5667         if (!tpr->rx_std_buffers)
5668                 return -ENOMEM;
5669
5670         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5671                                            &tpr->rx_std_mapping);
5672         if (!tpr->rx_std)
5673                 goto err_out;
5674
5675         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5676                 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5677                                               TG3_RX_JUMBO_RING_SIZE,
5678                                               GFP_KERNEL);
5679                 if (!tpr->rx_jmb_buffers)
5680                         goto err_out;
5681
5682                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5683                                                    TG3_RX_JUMBO_RING_BYTES,
5684                                                    &tpr->rx_jmb_mapping);
5685                 if (!tpr->rx_jmb)
5686                         goto err_out;
5687         }
5688
5689         return 0;
5690
5691 err_out:
5692         tg3_rx_prodring_fini(tp, tpr);
5693         return -ENOMEM;
5694 }
5695
5696 /* Free up pending packets in all rx/tx rings.
5697  *
5698  * The chip has been shut down and the driver detached from
5699  * the networking, so no interrupts or new tx packets will
5700  * end up in the driver.  tp->{tx,}lock is not held and we are not
5701  * in an interrupt context and thus may sleep.
5702  */
5703 static void tg3_free_rings(struct tg3 *tp)
5704 {
5705         int i;
5706
5707         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5708                 struct tx_ring_info *txp;
5709                 struct sk_buff *skb;
5710
5711                 txp = &tp->tx_buffers[i];
5712                 skb = txp->skb;
5713
5714                 if (skb == NULL) {
5715                         i++;
5716                         continue;
5717                 }
5718
5719                 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5720
5721                 txp->skb = NULL;
5722
5723                 i += skb_shinfo(skb)->nr_frags + 1;
5724
5725                 dev_kfree_skb_any(skb);
5726         }
5727
5728         tg3_rx_prodring_free(tp, &tp->prodring[0]);
5729 }
5730
5731 /* Initialize tx/rx rings for packet processing.
5732  *
5733  * The chip has been shut down and the driver detached from
5734  * the networking, so no interrupts or new tx packets will
5735  * end up in the driver.  tp->{tx,}lock are held and thus
5736  * we may not sleep.
5737  */
5738 static int tg3_init_rings(struct tg3 *tp)
5739 {
5740         /* Free up all the SKBs. */
5741         tg3_free_rings(tp);
5742
5743         /* Zero out all descriptors. */
5744         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5745         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5746
5747         return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5748 }
5749
5750 /*
5751  * Must not be invoked with interrupt sources disabled and
5752  * the hardware shutdown down.
5753  */
5754 static void tg3_free_consistent(struct tg3 *tp)
5755 {
5756         kfree(tp->tx_buffers);
5757         tp->tx_buffers = NULL;
5758         if (tp->rx_rcb) {
5759                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5760                                     tp->rx_rcb, tp->rx_rcb_mapping);
5761                 tp->rx_rcb = NULL;
5762         }
5763         if (tp->tx_ring) {
5764                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5765                         tp->tx_ring, tp->tx_desc_mapping);
5766                 tp->tx_ring = NULL;
5767         }
5768         if (tp->hw_status) {
5769                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5770                                     tp->hw_status, tp->status_mapping);
5771                 tp->hw_status = NULL;
5772         }
5773         if (tp->hw_stats) {
5774                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5775                                     tp->hw_stats, tp->stats_mapping);
5776                 tp->hw_stats = NULL;
5777         }
5778         tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5779 }
5780
5781 /*
5782  * Must not be invoked with interrupt sources disabled and
5783  * the hardware shutdown down.  Can sleep.
5784  */
5785 static int tg3_alloc_consistent(struct tg3 *tp)
5786 {
5787         if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5788                 return -ENOMEM;
5789
5790         tp->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5791                                  TG3_TX_RING_SIZE, GFP_KERNEL);
5792         if (!tp->tx_buffers)
5793                 goto err_out;
5794
5795         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5796                                           &tp->rx_rcb_mapping);
5797         if (!tp->rx_rcb)
5798                 goto err_out;
5799
5800         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5801                                            &tp->tx_desc_mapping);
5802         if (!tp->tx_ring)
5803                 goto err_out;
5804
5805         tp->hw_status = pci_alloc_consistent(tp->pdev,
5806                                              TG3_HW_STATUS_SIZE,
5807                                              &tp->status_mapping);
5808         if (!tp->hw_status)
5809                 goto err_out;
5810
5811         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5812                                             sizeof(struct tg3_hw_stats),
5813                                             &tp->stats_mapping);
5814         if (!tp->hw_stats)
5815                 goto err_out;
5816
5817         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5818         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5819
5820         return 0;
5821
5822 err_out:
5823         tg3_free_consistent(tp);
5824         return -ENOMEM;
5825 }
5826
5827 #define MAX_WAIT_CNT 1000
5828
5829 /* To stop a block, clear the enable bit and poll till it
5830  * clears.  tp->lock is held.
5831  */
5832 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5833 {
5834         unsigned int i;
5835         u32 val;
5836
5837         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5838                 switch (ofs) {
5839                 case RCVLSC_MODE:
5840                 case DMAC_MODE:
5841                 case MBFREE_MODE:
5842                 case BUFMGR_MODE:
5843                 case MEMARB_MODE:
5844                         /* We can't enable/disable these bits of the
5845                          * 5705/5750, just say success.
5846                          */
5847                         return 0;
5848
5849                 default:
5850                         break;
5851                 }
5852         }
5853
5854         val = tr32(ofs);
5855         val &= ~enable_bit;
5856         tw32_f(ofs, val);
5857
5858         for (i = 0; i < MAX_WAIT_CNT; i++) {
5859                 udelay(100);
5860                 val = tr32(ofs);
5861                 if ((val & enable_bit) == 0)
5862                         break;
5863         }
5864
5865         if (i == MAX_WAIT_CNT && !silent) {
5866                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5867                        "ofs=%lx enable_bit=%x\n",
5868                        ofs, enable_bit);
5869                 return -ENODEV;
5870         }
5871
5872         return 0;
5873 }
5874
5875 /* tp->lock is held. */
5876 static int tg3_abort_hw(struct tg3 *tp, int silent)
5877 {
5878         int i, err;
5879
5880         tg3_disable_ints(tp);
5881
5882         tp->rx_mode &= ~RX_MODE_ENABLE;
5883         tw32_f(MAC_RX_MODE, tp->rx_mode);
5884         udelay(10);
5885
5886         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5887         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5888         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5889         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5890         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5891         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5892
5893         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5894         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5895         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5896         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5897         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5898         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5899         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5900
5901         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5902         tw32_f(MAC_MODE, tp->mac_mode);
5903         udelay(40);
5904
5905         tp->tx_mode &= ~TX_MODE_ENABLE;
5906         tw32_f(MAC_TX_MODE, tp->tx_mode);
5907
5908         for (i = 0; i < MAX_WAIT_CNT; i++) {
5909                 udelay(100);
5910                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5911                         break;
5912         }
5913         if (i >= MAX_WAIT_CNT) {
5914                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5915                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5916                        tp->dev->name, tr32(MAC_TX_MODE));
5917                 err |= -ENODEV;
5918         }
5919
5920         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5921         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5922         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5923
5924         tw32(FTQ_RESET, 0xffffffff);
5925         tw32(FTQ_RESET, 0x00000000);
5926
5927         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5928         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5929
5930         if (tp->hw_status)
5931                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5932         if (tp->hw_stats)
5933                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5934
5935         return err;
5936 }
5937
5938 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5939 {
5940         int i;
5941         u32 apedata;
5942
5943         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5944         if (apedata != APE_SEG_SIG_MAGIC)
5945                 return;
5946
5947         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5948         if (!(apedata & APE_FW_STATUS_READY))
5949                 return;
5950
5951         /* Wait for up to 1 millisecond for APE to service previous event. */
5952         for (i = 0; i < 10; i++) {
5953                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5954                         return;
5955
5956                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5957
5958                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5959                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5960                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5961
5962                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5963
5964                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5965                         break;
5966
5967                 udelay(100);
5968         }
5969
5970         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5971                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5972 }
5973
5974 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5975 {
5976         u32 event;
5977         u32 apedata;
5978
5979         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5980                 return;
5981
5982         switch (kind) {
5983                 case RESET_KIND_INIT:
5984                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5985                                         APE_HOST_SEG_SIG_MAGIC);
5986                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5987                                         APE_HOST_SEG_LEN_MAGIC);
5988                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5989                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5990                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5991                                         APE_HOST_DRIVER_ID_MAGIC);
5992                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5993                                         APE_HOST_BEHAV_NO_PHYLOCK);
5994
5995                         event = APE_EVENT_STATUS_STATE_START;
5996                         break;
5997                 case RESET_KIND_SHUTDOWN:
5998                         /* With the interface we are currently using,
5999                          * APE does not track driver state.  Wiping
6000                          * out the HOST SEGMENT SIGNATURE forces
6001                          * the APE to assume OS absent status.
6002                          */
6003                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6004
6005                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6006                         break;
6007                 case RESET_KIND_SUSPEND:
6008                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6009                         break;
6010                 default:
6011                         return;
6012         }
6013
6014         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6015
6016         tg3_ape_send_event(tp, event);
6017 }
6018
6019 /* tp->lock is held. */
6020 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6021 {
6022         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6023                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6024
6025         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6026                 switch (kind) {
6027                 case RESET_KIND_INIT:
6028                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6029                                       DRV_STATE_START);
6030                         break;
6031
6032                 case RESET_KIND_SHUTDOWN:
6033                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6034                                       DRV_STATE_UNLOAD);
6035                         break;
6036
6037                 case RESET_KIND_SUSPEND:
6038                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6039                                       DRV_STATE_SUSPEND);
6040                         break;
6041
6042                 default:
6043                         break;
6044                 }
6045         }
6046
6047         if (kind == RESET_KIND_INIT ||
6048             kind == RESET_KIND_SUSPEND)
6049                 tg3_ape_driver_state_change(tp, kind);
6050 }
6051
6052 /* tp->lock is held. */
6053 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6054 {
6055         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6056                 switch (kind) {
6057                 case RESET_KIND_INIT:
6058                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6059                                       DRV_STATE_START_DONE);
6060                         break;
6061
6062                 case RESET_KIND_SHUTDOWN:
6063                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6064                                       DRV_STATE_UNLOAD_DONE);
6065                         break;
6066
6067                 default:
6068                         break;
6069                 }
6070         }
6071
6072         if (kind == RESET_KIND_SHUTDOWN)
6073                 tg3_ape_driver_state_change(tp, kind);
6074 }
6075
6076 /* tp->lock is held. */
6077 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6078 {
6079         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6080                 switch (kind) {
6081                 case RESET_KIND_INIT:
6082                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6083                                       DRV_STATE_START);
6084                         break;
6085
6086                 case RESET_KIND_SHUTDOWN:
6087                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6088                                       DRV_STATE_UNLOAD);
6089                         break;
6090
6091                 case RESET_KIND_SUSPEND:
6092                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6093                                       DRV_STATE_SUSPEND);
6094                         break;
6095
6096                 default:
6097                         break;
6098                 }
6099         }
6100 }
6101
6102 static int tg3_poll_fw(struct tg3 *tp)
6103 {
6104         int i;
6105         u32 val;
6106
6107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6108                 /* Wait up to 20ms for init done. */
6109                 for (i = 0; i < 200; i++) {
6110                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6111                                 return 0;
6112                         udelay(100);
6113                 }
6114                 return -ENODEV;
6115         }
6116
6117         /* Wait for firmware initialization to complete. */
6118         for (i = 0; i < 100000; i++) {
6119                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6120                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6121                         break;
6122                 udelay(10);
6123         }
6124
6125         /* Chip might not be fitted with firmware.  Some Sun onboard
6126          * parts are configured like that.  So don't signal the timeout
6127          * of the above loop as an error, but do report the lack of
6128          * running firmware once.
6129          */
6130         if (i >= 100000 &&
6131             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6132                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6133
6134                 printk(KERN_INFO PFX "%s: No firmware running.\n",
6135                        tp->dev->name);
6136         }
6137
6138         return 0;
6139 }
6140
6141 /* Save PCI command register before chip reset */
6142 static void tg3_save_pci_state(struct tg3 *tp)
6143 {
6144         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6145 }
6146
6147 /* Restore PCI state after chip reset */
6148 static void tg3_restore_pci_state(struct tg3 *tp)
6149 {
6150         u32 val;
6151
6152         /* Re-enable indirect register accesses. */
6153         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6154                                tp->misc_host_ctrl);
6155
6156         /* Set MAX PCI retry to zero. */
6157         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6158         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6159             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6160                 val |= PCISTATE_RETRY_SAME_DMA;
6161         /* Allow reads and writes to the APE register and memory space. */
6162         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6163                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6164                        PCISTATE_ALLOW_APE_SHMEM_WR;
6165         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6166
6167         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6168
6169         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6170                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6171                         pcie_set_readrq(tp->pdev, 4096);
6172                 else {
6173                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6174                                               tp->pci_cacheline_sz);
6175                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6176                                               tp->pci_lat_timer);
6177                 }
6178         }
6179
6180         /* Make sure PCI-X relaxed ordering bit is clear. */
6181         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6182                 u16 pcix_cmd;
6183
6184                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6185                                      &pcix_cmd);
6186                 pcix_cmd &= ~PCI_X_CMD_ERO;
6187                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6188                                       pcix_cmd);
6189         }
6190
6191         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6192
6193                 /* Chip reset on 5780 will reset MSI enable bit,
6194                  * so need to restore it.
6195                  */
6196                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6197                         u16 ctrl;
6198
6199                         pci_read_config_word(tp->pdev,
6200                                              tp->msi_cap + PCI_MSI_FLAGS,
6201                                              &ctrl);
6202                         pci_write_config_word(tp->pdev,
6203                                               tp->msi_cap + PCI_MSI_FLAGS,
6204                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6205                         val = tr32(MSGINT_MODE);
6206                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6207                 }
6208         }
6209 }
6210
6211 static void tg3_stop_fw(struct tg3 *);
6212
6213 /* tp->lock is held. */
6214 static int tg3_chip_reset(struct tg3 *tp)
6215 {
6216         u32 val;
6217         void (*write_op)(struct tg3 *, u32, u32);
6218         int err;
6219
6220         tg3_nvram_lock(tp);
6221
6222         tg3_mdio_stop(tp);
6223
6224         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6225
6226         /* No matching tg3_nvram_unlock() after this because
6227          * chip reset below will undo the nvram lock.
6228          */
6229         tp->nvram_lock_cnt = 0;
6230
6231         /* GRC_MISC_CFG core clock reset will clear the memory
6232          * enable bit in PCI register 4 and the MSI enable bit
6233          * on some chips, so we save relevant registers here.
6234          */
6235         tg3_save_pci_state(tp);
6236
6237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6238             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6239                 tw32(GRC_FASTBOOT_PC, 0);
6240
6241         /*
6242          * We must avoid the readl() that normally takes place.
6243          * It locks machines, causes machine checks, and other
6244          * fun things.  So, temporarily disable the 5701
6245          * hardware workaround, while we do the reset.
6246          */
6247         write_op = tp->write32;
6248         if (write_op == tg3_write_flush_reg32)
6249                 tp->write32 = tg3_write32;
6250
6251         /* Prevent the irq handler from reading or writing PCI registers
6252          * during chip reset when the memory enable bit in the PCI command
6253          * register may be cleared.  The chip does not generate interrupt
6254          * at this time, but the irq handler may still be called due to irq
6255          * sharing or irqpoll.
6256          */
6257         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6258         if (tp->hw_status) {
6259                 tp->hw_status->status = 0;
6260                 tp->hw_status->status_tag = 0;
6261         }
6262         tp->last_tag = 0;
6263         tp->last_irq_tag = 0;
6264         smp_mb();
6265         synchronize_irq(tp->pdev->irq);
6266
6267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6268                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6269                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6270         }
6271
6272         /* do the reset */
6273         val = GRC_MISC_CFG_CORECLK_RESET;
6274
6275         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6276                 if (tr32(0x7e2c) == 0x60) {
6277                         tw32(0x7e2c, 0x20);
6278                 }
6279                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6280                         tw32(GRC_MISC_CFG, (1 << 29));
6281                         val |= (1 << 29);
6282                 }
6283         }
6284
6285         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6286                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6287                 tw32(GRC_VCPU_EXT_CTRL,
6288                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6289         }
6290
6291         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6292                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6293         tw32(GRC_MISC_CFG, val);
6294
6295         /* restore 5701 hardware bug workaround write method */
6296         tp->write32 = write_op;
6297
6298         /* Unfortunately, we have to delay before the PCI read back.
6299          * Some 575X chips even will not respond to a PCI cfg access
6300          * when the reset command is given to the chip.
6301          *
6302          * How do these hardware designers expect things to work
6303          * properly if the PCI write is posted for a long period
6304          * of time?  It is always necessary to have some method by
6305          * which a register read back can occur to push the write
6306          * out which does the reset.
6307          *
6308          * For most tg3 variants the trick below was working.
6309          * Ho hum...
6310          */
6311         udelay(120);
6312
6313         /* Flush PCI posted writes.  The normal MMIO registers
6314          * are inaccessible at this time so this is the only
6315          * way to make this reliably (actually, this is no longer
6316          * the case, see above).  I tried to use indirect
6317          * register read/write but this upset some 5701 variants.
6318          */
6319         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6320
6321         udelay(120);
6322
6323         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6324                 u16 val16;
6325
6326                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6327                         int i;
6328                         u32 cfg_val;
6329
6330                         /* Wait for link training to complete.  */
6331                         for (i = 0; i < 5000; i++)
6332                                 udelay(100);
6333
6334                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6335                         pci_write_config_dword(tp->pdev, 0xc4,
6336                                                cfg_val | (1 << 15));
6337                 }
6338
6339                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6340                 pci_read_config_word(tp->pdev,
6341                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6342                                      &val16);
6343                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6344                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6345                 /*
6346                  * Older PCIe devices only support the 128 byte
6347                  * MPS setting.  Enforce the restriction.
6348                  */
6349                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6350                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6351                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6352                 pci_write_config_word(tp->pdev,
6353                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6354                                       val16);
6355
6356                 pcie_set_readrq(tp->pdev, 4096);
6357
6358                 /* Clear error status */
6359                 pci_write_config_word(tp->pdev,
6360                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6361                                       PCI_EXP_DEVSTA_CED |
6362                                       PCI_EXP_DEVSTA_NFED |
6363                                       PCI_EXP_DEVSTA_FED |
6364                                       PCI_EXP_DEVSTA_URD);
6365         }
6366
6367         tg3_restore_pci_state(tp);
6368
6369         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6370
6371         val = 0;
6372         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6373                 val = tr32(MEMARB_MODE);
6374         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6375
6376         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6377                 tg3_stop_fw(tp);
6378                 tw32(0x5000, 0x400);
6379         }
6380
6381         tw32(GRC_MODE, tp->grc_mode);
6382
6383         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6384                 val = tr32(0xc4);
6385
6386                 tw32(0xc4, val | (1 << 15));
6387         }
6388
6389         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6390             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6391                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6392                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6393                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6394                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6395         }
6396
6397         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6398                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6399                 tw32_f(MAC_MODE, tp->mac_mode);
6400         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6401                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6402                 tw32_f(MAC_MODE, tp->mac_mode);
6403         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6404                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6405                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6406                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6407                 tw32_f(MAC_MODE, tp->mac_mode);
6408         } else
6409                 tw32_f(MAC_MODE, 0);
6410         udelay(40);
6411
6412         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6413
6414         err = tg3_poll_fw(tp);
6415         if (err)
6416                 return err;
6417
6418         tg3_mdio_start(tp);
6419
6420         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6421             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6422                 val = tr32(0x7c00);
6423
6424                 tw32(0x7c00, val | (1 << 25));
6425         }
6426
6427         /* Reprobe ASF enable state.  */
6428         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6429         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6430         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6431         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6432                 u32 nic_cfg;
6433
6434                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6435                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6436                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6437                         tp->last_event_jiffies = jiffies;
6438                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6439                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6440                 }
6441         }
6442
6443         return 0;
6444 }
6445
6446 /* tp->lock is held. */
6447 static void tg3_stop_fw(struct tg3 *tp)
6448 {
6449         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6450            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6451                 /* Wait for RX cpu to ACK the previous event. */
6452                 tg3_wait_for_event_ack(tp);
6453
6454                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6455
6456                 tg3_generate_fw_event(tp);
6457
6458                 /* Wait for RX cpu to ACK this event. */
6459                 tg3_wait_for_event_ack(tp);
6460         }
6461 }
6462
6463 /* tp->lock is held. */
6464 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6465 {
6466         int err;
6467
6468         tg3_stop_fw(tp);
6469
6470         tg3_write_sig_pre_reset(tp, kind);
6471
6472         tg3_abort_hw(tp, silent);
6473         err = tg3_chip_reset(tp);
6474
6475         __tg3_set_mac_addr(tp, 0);
6476
6477         tg3_write_sig_legacy(tp, kind);
6478         tg3_write_sig_post_reset(tp, kind);
6479
6480         if (err)
6481                 return err;
6482
6483         return 0;
6484 }
6485
6486 #define RX_CPU_SCRATCH_BASE     0x30000
6487 #define RX_CPU_SCRATCH_SIZE     0x04000
6488 #define TX_CPU_SCRATCH_BASE     0x34000
6489 #define TX_CPU_SCRATCH_SIZE     0x04000
6490
6491 /* tp->lock is held. */
6492 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6493 {
6494         int i;
6495
6496         BUG_ON(offset == TX_CPU_BASE &&
6497             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6498
6499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6500                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6501
6502                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6503                 return 0;
6504         }
6505         if (offset == RX_CPU_BASE) {
6506                 for (i = 0; i < 10000; i++) {
6507                         tw32(offset + CPU_STATE, 0xffffffff);
6508                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6509                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6510                                 break;
6511                 }
6512
6513                 tw32(offset + CPU_STATE, 0xffffffff);
6514                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6515                 udelay(10);
6516         } else {
6517                 for (i = 0; i < 10000; i++) {
6518                         tw32(offset + CPU_STATE, 0xffffffff);
6519                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6520                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6521                                 break;
6522                 }
6523         }
6524
6525         if (i >= 10000) {
6526                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6527                        "and %s CPU\n",
6528                        tp->dev->name,
6529                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6530                 return -ENODEV;
6531         }
6532
6533         /* Clear firmware's nvram arbitration. */
6534         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6535                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6536         return 0;
6537 }
6538
6539 struct fw_info {
6540         unsigned int fw_base;
6541         unsigned int fw_len;
6542         const __be32 *fw_data;
6543 };
6544
6545 /* tp->lock is held. */
6546 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6547                                  int cpu_scratch_size, struct fw_info *info)
6548 {
6549         int err, lock_err, i;
6550         void (*write_op)(struct tg3 *, u32, u32);
6551
6552         if (cpu_base == TX_CPU_BASE &&
6553             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6554                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6555                        "TX cpu firmware on %s which is 5705.\n",
6556                        tp->dev->name);
6557                 return -EINVAL;
6558         }
6559
6560         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6561                 write_op = tg3_write_mem;
6562         else
6563                 write_op = tg3_write_indirect_reg32;
6564
6565         /* It is possible that bootcode is still loading at this point.
6566          * Get the nvram lock first before halting the cpu.
6567          */
6568         lock_err = tg3_nvram_lock(tp);
6569         err = tg3_halt_cpu(tp, cpu_base);
6570         if (!lock_err)
6571                 tg3_nvram_unlock(tp);
6572         if (err)
6573                 goto out;
6574
6575         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6576                 write_op(tp, cpu_scratch_base + i, 0);
6577         tw32(cpu_base + CPU_STATE, 0xffffffff);
6578         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6579         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6580                 write_op(tp, (cpu_scratch_base +
6581                               (info->fw_base & 0xffff) +
6582                               (i * sizeof(u32))),
6583                               be32_to_cpu(info->fw_data[i]));
6584
6585         err = 0;
6586
6587 out:
6588         return err;
6589 }
6590
6591 /* tp->lock is held. */
6592 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6593 {
6594         struct fw_info info;
6595         const __be32 *fw_data;
6596         int err, i;
6597
6598         fw_data = (void *)tp->fw->data;
6599
6600         /* Firmware blob starts with version numbers, followed by
6601            start address and length. We are setting complete length.
6602            length = end_address_of_bss - start_address_of_text.
6603            Remainder is the blob to be loaded contiguously
6604            from start address. */
6605
6606         info.fw_base = be32_to_cpu(fw_data[1]);
6607         info.fw_len = tp->fw->size - 12;
6608         info.fw_data = &fw_data[3];
6609
6610         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6611                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6612                                     &info);
6613         if (err)
6614                 return err;
6615
6616         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6617                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6618                                     &info);
6619         if (err)
6620                 return err;
6621
6622         /* Now startup only the RX cpu. */
6623         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6624         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6625
6626         for (i = 0; i < 5; i++) {
6627                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6628                         break;
6629                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6630                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6631                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6632                 udelay(1000);
6633         }
6634         if (i >= 5) {
6635                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6636                        "to set RX CPU PC, is %08x should be %08x\n",
6637                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6638                        info.fw_base);
6639                 return -ENODEV;
6640         }
6641         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6642         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6643
6644         return 0;
6645 }
6646
6647 /* 5705 needs a special version of the TSO firmware.  */
6648
6649 /* tp->lock is held. */
6650 static int tg3_load_tso_firmware(struct tg3 *tp)
6651 {
6652         struct fw_info info;
6653         const __be32 *fw_data;
6654         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6655         int err, i;
6656
6657         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6658                 return 0;
6659
6660         fw_data = (void *)tp->fw->data;
6661
6662         /* Firmware blob starts with version numbers, followed by
6663            start address and length. We are setting complete length.
6664            length = end_address_of_bss - start_address_of_text.
6665            Remainder is the blob to be loaded contiguously
6666            from start address. */
6667
6668         info.fw_base = be32_to_cpu(fw_data[1]);
6669         cpu_scratch_size = tp->fw_len;
6670         info.fw_len = tp->fw->size - 12;
6671         info.fw_data = &fw_data[3];
6672
6673         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6674                 cpu_base = RX_CPU_BASE;
6675                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6676         } else {
6677                 cpu_base = TX_CPU_BASE;
6678                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6679                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6680         }
6681
6682         err = tg3_load_firmware_cpu(tp, cpu_base,
6683                                     cpu_scratch_base, cpu_scratch_size,
6684                                     &info);
6685         if (err)
6686                 return err;
6687
6688         /* Now startup the cpu. */
6689         tw32(cpu_base + CPU_STATE, 0xffffffff);
6690         tw32_f(cpu_base + CPU_PC, info.fw_base);
6691
6692         for (i = 0; i < 5; i++) {
6693                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6694                         break;
6695                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6696                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6697                 tw32_f(cpu_base + CPU_PC, info.fw_base);
6698                 udelay(1000);
6699         }
6700         if (i >= 5) {
6701                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6702                        "to set CPU PC, is %08x should be %08x\n",
6703                        tp->dev->name, tr32(cpu_base + CPU_PC),
6704                        info.fw_base);
6705                 return -ENODEV;
6706         }
6707         tw32(cpu_base + CPU_STATE, 0xffffffff);
6708         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6709         return 0;
6710 }
6711
6712
6713 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6714 {
6715         struct tg3 *tp = netdev_priv(dev);
6716         struct sockaddr *addr = p;
6717         int err = 0, skip_mac_1 = 0;
6718
6719         if (!is_valid_ether_addr(addr->sa_data))
6720                 return -EINVAL;
6721
6722         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6723
6724         if (!netif_running(dev))
6725                 return 0;
6726
6727         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6728                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6729
6730                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6731                 addr0_low = tr32(MAC_ADDR_0_LOW);
6732                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6733                 addr1_low = tr32(MAC_ADDR_1_LOW);
6734
6735                 /* Skip MAC addr 1 if ASF is using it. */
6736                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6737                     !(addr1_high == 0 && addr1_low == 0))
6738                         skip_mac_1 = 1;
6739         }
6740         spin_lock_bh(&tp->lock);
6741         __tg3_set_mac_addr(tp, skip_mac_1);
6742         spin_unlock_bh(&tp->lock);
6743
6744         return err;
6745 }
6746
6747 /* tp->lock is held. */
6748 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6749                            dma_addr_t mapping, u32 maxlen_flags,
6750                            u32 nic_addr)
6751 {
6752         tg3_write_mem(tp,
6753                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6754                       ((u64) mapping >> 32));
6755         tg3_write_mem(tp,
6756                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6757                       ((u64) mapping & 0xffffffff));
6758         tg3_write_mem(tp,
6759                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6760                        maxlen_flags);
6761
6762         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6763                 tg3_write_mem(tp,
6764                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6765                               nic_addr);
6766 }
6767
6768 static void __tg3_set_rx_mode(struct net_device *);
6769 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6770 {
6771         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6772         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6773         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6774         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6775         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6776                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6777                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6778         }
6779         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6780         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6781         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6782                 u32 val = ec->stats_block_coalesce_usecs;
6783
6784                 if (!netif_carrier_ok(tp->dev))
6785                         val = 0;
6786
6787                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6788         }
6789 }
6790
6791 /* tp->lock is held. */
6792 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6793 {
6794         u32 val, rdmac_mode;
6795         int i, err, limit;
6796         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
6797
6798         tg3_disable_ints(tp);
6799
6800         tg3_stop_fw(tp);
6801
6802         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6803
6804         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6805                 tg3_abort_hw(tp, 1);
6806         }
6807
6808         if (reset_phy &&
6809             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6810                 tg3_phy_reset(tp);
6811
6812         err = tg3_chip_reset(tp);
6813         if (err)
6814                 return err;
6815
6816         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6817
6818         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6819                 val = tr32(TG3_CPMU_CTRL);
6820                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6821                 tw32(TG3_CPMU_CTRL, val);
6822
6823                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6824                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6825                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6826                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6827
6828                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6829                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6830                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6831                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6832
6833                 val = tr32(TG3_CPMU_HST_ACC);
6834                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6835                 val |= CPMU_HST_ACC_MACCLK_6_25;
6836                 tw32(TG3_CPMU_HST_ACC, val);
6837         }
6838
6839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6840                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6841                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6842                        PCIE_PWR_MGMT_L1_THRESH_4MS;
6843                 tw32(PCIE_PWR_MGMT_THRESH, val);
6844
6845                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
6846                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
6847
6848                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
6849         }
6850
6851         if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
6852                 val = tr32(TG3_PCIE_LNKCTL);
6853                 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
6854                         val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6855                 else
6856                         val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
6857                 tw32(TG3_PCIE_LNKCTL, val);
6858         }
6859
6860         /* This works around an issue with Athlon chipsets on
6861          * B3 tigon3 silicon.  This bit has no effect on any
6862          * other revision.  But do not set this on PCI Express
6863          * chips and don't even touch the clocks if the CPMU is present.
6864          */
6865         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6866                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6867                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6868                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6869         }
6870
6871         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6872             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6873                 val = tr32(TG3PCI_PCISTATE);
6874                 val |= PCISTATE_RETRY_SAME_DMA;
6875                 tw32(TG3PCI_PCISTATE, val);
6876         }
6877
6878         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6879                 /* Allow reads and writes to the
6880                  * APE register and memory space.
6881                  */
6882                 val = tr32(TG3PCI_PCISTATE);
6883                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6884                        PCISTATE_ALLOW_APE_SHMEM_WR;
6885                 tw32(TG3PCI_PCISTATE, val);
6886         }
6887
6888         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6889                 /* Enable some hw fixes.  */
6890                 val = tr32(TG3PCI_MSI_DATA);
6891                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6892                 tw32(TG3PCI_MSI_DATA, val);
6893         }
6894
6895         /* Descriptor ring init may make accesses to the
6896          * NIC SRAM area to setup the TX descriptors, so we
6897          * can only do this after the hardware has been
6898          * successfully reset.
6899          */
6900         err = tg3_init_rings(tp);
6901         if (err)
6902                 return err;
6903
6904         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6905             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6906                 /* This value is determined during the probe time DMA
6907                  * engine test, tg3_test_dma.
6908                  */
6909                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6910         }
6911
6912         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6913                           GRC_MODE_4X_NIC_SEND_RINGS |
6914                           GRC_MODE_NO_TX_PHDR_CSUM |
6915                           GRC_MODE_NO_RX_PHDR_CSUM);
6916         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6917
6918         /* Pseudo-header checksum is done by hardware logic and not
6919          * the offload processers, so make the chip do the pseudo-
6920          * header checksums on receive.  For transmit it is more
6921          * convenient to do the pseudo-header checksum in software
6922          * as Linux does that on transmit for us in all cases.
6923          */
6924         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6925
6926         tw32(GRC_MODE,
6927              tp->grc_mode |
6928              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6929
6930         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6931         val = tr32(GRC_MISC_CFG);
6932         val &= ~0xff;
6933         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6934         tw32(GRC_MISC_CFG, val);
6935
6936         /* Initialize MBUF/DESC pool. */
6937         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6938                 /* Do nothing.  */
6939         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6940                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6941                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6942                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6943                 else
6944                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6945                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6946                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6947         }
6948         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6949                 int fw_len;
6950
6951                 fw_len = tp->fw_len;
6952                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6953                 tw32(BUFMGR_MB_POOL_ADDR,
6954                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6955                 tw32(BUFMGR_MB_POOL_SIZE,
6956                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6957         }
6958
6959         if (tp->dev->mtu <= ETH_DATA_LEN) {
6960                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6961                      tp->bufmgr_config.mbuf_read_dma_low_water);
6962                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6963                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6964                 tw32(BUFMGR_MB_HIGH_WATER,
6965                      tp->bufmgr_config.mbuf_high_water);
6966         } else {
6967                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6968                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6969                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6970                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6971                 tw32(BUFMGR_MB_HIGH_WATER,
6972                      tp->bufmgr_config.mbuf_high_water_jumbo);
6973         }
6974         tw32(BUFMGR_DMA_LOW_WATER,
6975              tp->bufmgr_config.dma_low_water);
6976         tw32(BUFMGR_DMA_HIGH_WATER,
6977              tp->bufmgr_config.dma_high_water);
6978
6979         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6980         for (i = 0; i < 2000; i++) {
6981                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6982                         break;
6983                 udelay(10);
6984         }
6985         if (i >= 2000) {
6986                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6987                        tp->dev->name);
6988                 return -ENODEV;
6989         }
6990
6991         /* Setup replenish threshold. */
6992         val = tp->rx_pending / 8;
6993         if (val == 0)
6994                 val = 1;
6995         else if (val > tp->rx_std_max_post)
6996                 val = tp->rx_std_max_post;
6997         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6998                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6999                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7000
7001                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7002                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7003         }
7004
7005         tw32(RCVBDI_STD_THRESH, val);
7006
7007         /* Initialize TG3_BDINFO's at:
7008          *  RCVDBDI_STD_BD:     standard eth size rx ring
7009          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7010          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7011          *
7012          * like so:
7013          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7014          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7015          *                              ring attribute flags
7016          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7017          *
7018          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7019          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7020          *
7021          * The size of each ring is fixed in the firmware, but the location is
7022          * configurable.
7023          */
7024         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7025              ((u64) tpr->rx_std_mapping >> 32));
7026         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7027              ((u64) tpr->rx_std_mapping & 0xffffffff));
7028         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7029              NIC_SRAM_RX_BUFFER_DESC);
7030
7031         /* Disable the mini ring */
7032         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7033                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7034                      BDINFO_FLAGS_DISABLED);
7035
7036         /* Program the jumbo buffer descriptor ring control
7037          * blocks on those devices that have them.
7038          */
7039         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7040             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7041                 /* Setup replenish threshold. */
7042                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7043
7044                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7045                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7046                              ((u64) tpr->rx_jmb_mapping >> 32));
7047                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7048                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7049                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7050                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7051                              BDINFO_FLAGS_USE_EXT_RECV);
7052                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7053                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7054                 } else {
7055                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7056                              BDINFO_FLAGS_DISABLED);
7057                 }
7058
7059                 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7060         } else
7061                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7062
7063         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7064
7065         /* There is only one send ring on 5705/5750, no need to explicitly
7066          * disable the others.
7067          */
7068         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7069                 /* Clear out send RCB ring in SRAM. */
7070                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7071                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7072                                       BDINFO_FLAGS_DISABLED);
7073         }
7074
7075         tp->tx_prod = 0;
7076         tp->tx_cons = 0;
7077         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7078         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7079
7080         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7081                        tp->tx_desc_mapping,
7082                        (TG3_TX_RING_SIZE <<
7083                         BDINFO_FLAGS_MAXLEN_SHIFT),
7084                        NIC_SRAM_TX_BUFFER_DESC);
7085
7086         /* There is only one receive return ring on 5705/5750, no need
7087          * to explicitly disable the others.
7088          */
7089         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7090                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7091                      i += TG3_BDINFO_SIZE) {
7092                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7093                                       BDINFO_FLAGS_DISABLED);
7094                 }
7095         }
7096
7097         tp->rx_rcb_ptr = 0;
7098         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7099
7100         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7101                        tp->rx_rcb_mapping,
7102                        (TG3_RX_RCB_RING_SIZE(tp) <<
7103                         BDINFO_FLAGS_MAXLEN_SHIFT),
7104                        0);
7105
7106         tpr->rx_std_ptr = tp->rx_pending;
7107         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7108                      tpr->rx_std_ptr);
7109
7110         tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7111                           tp->rx_jumbo_pending : 0;
7112         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7113                      tpr->rx_jmb_ptr);
7114
7115         /* Initialize MAC address and backoff seed. */
7116         __tg3_set_mac_addr(tp, 0);
7117
7118         /* MTU + ethernet header + FCS + optional VLAN tag */
7119         tw32(MAC_RX_MTU_SIZE,
7120              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7121
7122         /* The slot time is changed by tg3_setup_phy if we
7123          * run at gigabit with half duplex.
7124          */
7125         tw32(MAC_TX_LENGTHS,
7126              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7127              (6 << TX_LENGTHS_IPG_SHIFT) |
7128              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7129
7130         /* Receive rules. */
7131         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7132         tw32(RCVLPC_CONFIG, 0x0181);
7133
7134         /* Calculate RDMAC_MODE setting early, we need it to determine
7135          * the RCVLPC_STATE_ENABLE mask.
7136          */
7137         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7138                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7139                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7140                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7141                       RDMAC_MODE_LNGREAD_ENAB);
7142
7143         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7144             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7145             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7146                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7147                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7148                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7149
7150         /* If statement applies to 5705 and 5750 PCI devices only */
7151         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7152              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7153             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7154                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7155                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7156                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7157                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7158                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7159                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7160                 }
7161         }
7162
7163         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7164                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7165
7166         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7167                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7168
7169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7170             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7171                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7172
7173         /* Receive/send statistics. */
7174         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7175                 val = tr32(RCVLPC_STATS_ENABLE);
7176                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7177                 tw32(RCVLPC_STATS_ENABLE, val);
7178         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7179                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7180                 val = tr32(RCVLPC_STATS_ENABLE);
7181                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7182                 tw32(RCVLPC_STATS_ENABLE, val);
7183         } else {
7184                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7185         }
7186         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7187         tw32(SNDDATAI_STATSENAB, 0xffffff);
7188         tw32(SNDDATAI_STATSCTRL,
7189              (SNDDATAI_SCTRL_ENABLE |
7190               SNDDATAI_SCTRL_FASTUPD));
7191
7192         /* Setup host coalescing engine. */
7193         tw32(HOSTCC_MODE, 0);
7194         for (i = 0; i < 2000; i++) {
7195                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7196                         break;
7197                 udelay(10);
7198         }
7199
7200         __tg3_set_coalesce(tp, &tp->coal);
7201
7202         /* set status block DMA address */
7203         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7204              ((u64) tp->status_mapping >> 32));
7205         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7206              ((u64) tp->status_mapping & 0xffffffff));
7207
7208         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7209                 /* Status/statistics block address.  See tg3_timer,
7210                  * the tg3_periodic_fetch_stats call there, and
7211                  * tg3_get_stats to see how this works for 5705/5750 chips.
7212                  */
7213                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7214                      ((u64) tp->stats_mapping >> 32));
7215                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7216                      ((u64) tp->stats_mapping & 0xffffffff));
7217                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7218                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7219         }
7220
7221         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7222
7223         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7224         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7225         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7226                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7227
7228         /* Clear statistics/status block in chip, and status block in ram. */
7229         for (i = NIC_SRAM_STATS_BLK;
7230              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7231              i += sizeof(u32)) {
7232                 tg3_write_mem(tp, i, 0);
7233                 udelay(40);
7234         }
7235         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7236
7237         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7238                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7239                 /* reset to prevent losing 1st rx packet intermittently */
7240                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7241                 udelay(10);
7242         }
7243
7244         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7245                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7246         else
7247                 tp->mac_mode = 0;
7248         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7249                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7250         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7251             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7252             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7253                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7254         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7255         udelay(40);
7256
7257         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7258          * If TG3_FLG2_IS_NIC is zero, we should read the
7259          * register to preserve the GPIO settings for LOMs. The GPIOs,
7260          * whether used as inputs or outputs, are set by boot code after
7261          * reset.
7262          */
7263         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7264                 u32 gpio_mask;
7265
7266                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7267                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7268                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7269
7270                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7271                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7272                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7273
7274                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7275                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7276
7277                 tp->grc_local_ctrl &= ~gpio_mask;
7278                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7279
7280                 /* GPIO1 must be driven high for eeprom write protect */
7281                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7282                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7283                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7284         }
7285         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7286         udelay(100);
7287
7288         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7289
7290         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7291                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7292                 udelay(40);
7293         }
7294
7295         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7296                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7297                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7298                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7299                WDMAC_MODE_LNGREAD_ENAB);
7300
7301         /* If statement applies to 5705 and 5750 PCI devices only */
7302         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7303              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7305                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7306                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7307                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7308                         /* nothing */
7309                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7310                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7311                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7312                         val |= WDMAC_MODE_RX_ACCEL;
7313                 }
7314         }
7315
7316         /* Enable host coalescing bug fix */
7317         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7318                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7319
7320         tw32_f(WDMAC_MODE, val);
7321         udelay(40);
7322
7323         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7324                 u16 pcix_cmd;
7325
7326                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7327                                      &pcix_cmd);
7328                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7329                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7330                         pcix_cmd |= PCI_X_CMD_READ_2K;
7331                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7332                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7333                         pcix_cmd |= PCI_X_CMD_READ_2K;
7334                 }
7335                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7336                                       pcix_cmd);
7337         }
7338
7339         tw32_f(RDMAC_MODE, rdmac_mode);
7340         udelay(40);
7341
7342         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7343         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7344                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7345
7346         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7347                 tw32(SNDDATAC_MODE,
7348                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7349         else
7350                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7351
7352         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7353         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7354         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7355         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7356         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7357                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7358         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7359         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7360
7361         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7362                 err = tg3_load_5701_a0_firmware_fix(tp);
7363                 if (err)
7364                         return err;
7365         }
7366
7367         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7368                 err = tg3_load_tso_firmware(tp);
7369                 if (err)
7370                         return err;
7371         }
7372
7373         tp->tx_mode = TX_MODE_ENABLE;
7374         tw32_f(MAC_TX_MODE, tp->tx_mode);
7375         udelay(100);
7376
7377         tp->rx_mode = RX_MODE_ENABLE;
7378         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7379                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7380
7381         tw32_f(MAC_RX_MODE, tp->rx_mode);
7382         udelay(10);
7383
7384         tw32(MAC_LED_CTRL, tp->led_ctrl);
7385
7386         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7387         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7388                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7389                 udelay(10);
7390         }
7391         tw32_f(MAC_RX_MODE, tp->rx_mode);
7392         udelay(10);
7393
7394         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7395                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7396                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7397                         /* Set drive transmission level to 1.2V  */
7398                         /* only if the signal pre-emphasis bit is not set  */
7399                         val = tr32(MAC_SERDES_CFG);
7400                         val &= 0xfffff000;
7401                         val |= 0x880;
7402                         tw32(MAC_SERDES_CFG, val);
7403                 }
7404                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7405                         tw32(MAC_SERDES_CFG, 0x616000);
7406         }
7407
7408         /* Prevent chip from dropping frames when flow control
7409          * is enabled.
7410          */
7411         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7412
7413         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7414             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7415                 /* Use hardware link auto-negotiation */
7416                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7417         }
7418
7419         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7420             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7421                 u32 tmp;
7422
7423                 tmp = tr32(SERDES_RX_CTRL);
7424                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7425                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7426                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7427                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7428         }
7429
7430         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7431                 if (tp->link_config.phy_is_low_power) {
7432                         tp->link_config.phy_is_low_power = 0;
7433                         tp->link_config.speed = tp->link_config.orig_speed;
7434                         tp->link_config.duplex = tp->link_config.orig_duplex;
7435                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7436                 }
7437
7438                 err = tg3_setup_phy(tp, 0);
7439                 if (err)
7440                         return err;
7441
7442                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7443                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7444                         u32 tmp;
7445
7446                         /* Clear CRC stats. */
7447                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7448                                 tg3_writephy(tp, MII_TG3_TEST1,
7449                                              tmp | MII_TG3_TEST1_CRC_EN);
7450                                 tg3_readphy(tp, 0x14, &tmp);
7451                         }
7452                 }
7453         }
7454
7455         __tg3_set_rx_mode(tp->dev);
7456
7457         /* Initialize receive rules. */
7458         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7459         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7460         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7461         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7462
7463         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7464             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7465                 limit = 8;
7466         else
7467                 limit = 16;
7468         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7469                 limit -= 4;
7470         switch (limit) {
7471         case 16:
7472                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7473         case 15:
7474                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7475         case 14:
7476                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7477         case 13:
7478                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7479         case 12:
7480                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7481         case 11:
7482                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7483         case 10:
7484                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7485         case 9:
7486                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7487         case 8:
7488                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7489         case 7:
7490                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7491         case 6:
7492                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7493         case 5:
7494                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7495         case 4:
7496                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7497         case 3:
7498                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7499         case 2:
7500         case 1:
7501
7502         default:
7503                 break;
7504         }
7505
7506         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7507                 /* Write our heartbeat update interval to APE. */
7508                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7509                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7510
7511         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7512
7513         return 0;
7514 }
7515
7516 /* Called at device open time to get the chip ready for
7517  * packet processing.  Invoked with tp->lock held.
7518  */
7519 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7520 {
7521         tg3_switch_clocks(tp);
7522
7523         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7524
7525         return tg3_reset_hw(tp, reset_phy);
7526 }
7527
7528 #define TG3_STAT_ADD32(PSTAT, REG) \
7529 do {    u32 __val = tr32(REG); \
7530         (PSTAT)->low += __val; \
7531         if ((PSTAT)->low < __val) \
7532                 (PSTAT)->high += 1; \
7533 } while (0)
7534
7535 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7536 {
7537         struct tg3_hw_stats *sp = tp->hw_stats;
7538
7539         if (!netif_carrier_ok(tp->dev))
7540                 return;
7541
7542         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7543         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7544         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7545         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7546         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7547         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7548         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7549         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7550         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7551         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7552         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7553         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7554         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7555
7556         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7557         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7558         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7559         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7560         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7561         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7562         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7563         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7564         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7565         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7566         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7567         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7568         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7569         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7570
7571         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7572         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7573         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7574 }
7575
7576 static void tg3_timer(unsigned long __opaque)
7577 {
7578         struct tg3 *tp = (struct tg3 *) __opaque;
7579
7580         if (tp->irq_sync)
7581                 goto restart_timer;
7582
7583         spin_lock(&tp->lock);
7584
7585         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7586                 /* All of this garbage is because when using non-tagged
7587                  * IRQ status the mailbox/status_block protocol the chip
7588                  * uses with the cpu is race prone.
7589                  */
7590                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7591                         tw32(GRC_LOCAL_CTRL,
7592                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7593                 } else {
7594                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7595                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7596                 }
7597
7598                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7599                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7600                         spin_unlock(&tp->lock);
7601                         schedule_work(&tp->reset_task);
7602                         return;
7603                 }
7604         }
7605
7606         /* This part only runs once per second. */
7607         if (!--tp->timer_counter) {
7608                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7609                         tg3_periodic_fetch_stats(tp);
7610
7611                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7612                         u32 mac_stat;
7613                         int phy_event;
7614
7615                         mac_stat = tr32(MAC_STATUS);
7616
7617                         phy_event = 0;
7618                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7619                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7620                                         phy_event = 1;
7621                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7622                                 phy_event = 1;
7623
7624                         if (phy_event)
7625                                 tg3_setup_phy(tp, 0);
7626                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7627                         u32 mac_stat = tr32(MAC_STATUS);
7628                         int need_setup = 0;
7629
7630                         if (netif_carrier_ok(tp->dev) &&
7631                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7632                                 need_setup = 1;
7633                         }
7634                         if (! netif_carrier_ok(tp->dev) &&
7635                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7636                                          MAC_STATUS_SIGNAL_DET))) {
7637                                 need_setup = 1;
7638                         }
7639                         if (need_setup) {
7640                                 if (!tp->serdes_counter) {
7641                                         tw32_f(MAC_MODE,
7642                                              (tp->mac_mode &
7643                                               ~MAC_MODE_PORT_MODE_MASK));
7644                                         udelay(40);
7645                                         tw32_f(MAC_MODE, tp->mac_mode);
7646                                         udelay(40);
7647                                 }
7648                                 tg3_setup_phy(tp, 0);
7649                         }
7650                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7651                         tg3_serdes_parallel_detect(tp);
7652
7653                 tp->timer_counter = tp->timer_multiplier;
7654         }
7655
7656         /* Heartbeat is only sent once every 2 seconds.
7657          *
7658          * The heartbeat is to tell the ASF firmware that the host
7659          * driver is still alive.  In the event that the OS crashes,
7660          * ASF needs to reset the hardware to free up the FIFO space
7661          * that may be filled with rx packets destined for the host.
7662          * If the FIFO is full, ASF will no longer function properly.
7663          *
7664          * Unintended resets have been reported on real time kernels
7665          * where the timer doesn't run on time.  Netpoll will also have
7666          * same problem.
7667          *
7668          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7669          * to check the ring condition when the heartbeat is expiring
7670          * before doing the reset.  This will prevent most unintended
7671          * resets.
7672          */
7673         if (!--tp->asf_counter) {
7674                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7675                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7676                         tg3_wait_for_event_ack(tp);
7677
7678                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7679                                       FWCMD_NICDRV_ALIVE3);
7680                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7681                         /* 5 seconds timeout */
7682                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7683
7684                         tg3_generate_fw_event(tp);
7685                 }
7686                 tp->asf_counter = tp->asf_multiplier;
7687         }
7688
7689         spin_unlock(&tp->lock);
7690
7691 restart_timer:
7692         tp->timer.expires = jiffies + tp->timer_offset;
7693         add_timer(&tp->timer);
7694 }
7695
7696 static int tg3_request_irq(struct tg3 *tp)
7697 {
7698         irq_handler_t fn;
7699         unsigned long flags;
7700         char *name = tp->dev->name;
7701
7702         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7703                 fn = tg3_msi;
7704                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7705                         fn = tg3_msi_1shot;
7706                 flags = IRQF_SAMPLE_RANDOM;
7707         } else {
7708                 fn = tg3_interrupt;
7709                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7710                         fn = tg3_interrupt_tagged;
7711                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7712         }
7713         return request_irq(tp->pdev->irq, fn, flags, name, &tp->napi[0]);
7714 }
7715
7716 static int tg3_test_interrupt(struct tg3 *tp)
7717 {
7718         struct tg3_napi *tnapi = &tp->napi[0];
7719         struct net_device *dev = tp->dev;
7720         int err, i, intr_ok = 0;
7721
7722         if (!netif_running(dev))
7723                 return -ENODEV;
7724
7725         tg3_disable_ints(tp);
7726
7727         free_irq(tp->pdev->irq, tnapi);
7728
7729         err = request_irq(tp->pdev->irq, tg3_test_isr,
7730                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
7731         if (err)
7732                 return err;
7733
7734         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7735         tg3_enable_ints(tp);
7736
7737         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7738                HOSTCC_MODE_NOW);
7739
7740         for (i = 0; i < 5; i++) {
7741                 u32 int_mbox, misc_host_ctrl;
7742
7743                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7744                                         TG3_64BIT_REG_LOW);
7745                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7746
7747                 if ((int_mbox != 0) ||
7748                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7749                         intr_ok = 1;
7750                         break;
7751                 }
7752
7753                 msleep(10);
7754         }
7755
7756         tg3_disable_ints(tp);
7757
7758         free_irq(tp->pdev->irq, tnapi);
7759
7760         err = tg3_request_irq(tp);
7761
7762         if (err)
7763                 return err;
7764
7765         if (intr_ok)
7766                 return 0;
7767
7768         return -EIO;
7769 }
7770
7771 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7772  * successfully restored
7773  */
7774 static int tg3_test_msi(struct tg3 *tp)
7775 {
7776         int err;
7777         u16 pci_cmd;
7778
7779         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7780                 return 0;
7781
7782         /* Turn off SERR reporting in case MSI terminates with Master
7783          * Abort.
7784          */
7785         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7786         pci_write_config_word(tp->pdev, PCI_COMMAND,
7787                               pci_cmd & ~PCI_COMMAND_SERR);
7788
7789         err = tg3_test_interrupt(tp);
7790
7791         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7792
7793         if (!err)
7794                 return 0;
7795
7796         /* other failures */
7797         if (err != -EIO)
7798                 return err;
7799
7800         /* MSI test failed, go back to INTx mode */
7801         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7802                "switching to INTx mode. Please report this failure to "
7803                "the PCI maintainer and include system chipset information.\n",
7804                        tp->dev->name);
7805
7806         free_irq(tp->pdev->irq, &tp->napi[0]);
7807
7808         pci_disable_msi(tp->pdev);
7809
7810         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7811
7812         err = tg3_request_irq(tp);
7813         if (err)
7814                 return err;
7815
7816         /* Need to reset the chip because the MSI cycle may have terminated
7817          * with Master Abort.
7818          */
7819         tg3_full_lock(tp, 1);
7820
7821         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7822         err = tg3_init_hw(tp, 1);
7823
7824         tg3_full_unlock(tp);
7825
7826         if (err)
7827                 free_irq(tp->pdev->irq, &tp->napi[0]);
7828
7829         return err;
7830 }
7831
7832 static int tg3_request_firmware(struct tg3 *tp)
7833 {
7834         const __be32 *fw_data;
7835
7836         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7837                 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7838                        tp->dev->name, tp->fw_needed);
7839                 return -ENOENT;
7840         }
7841
7842         fw_data = (void *)tp->fw->data;
7843
7844         /* Firmware blob starts with version numbers, followed by
7845          * start address and _full_ length including BSS sections
7846          * (which must be longer than the actual data, of course
7847          */
7848
7849         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
7850         if (tp->fw_len < (tp->fw->size - 12)) {
7851                 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7852                        tp->dev->name, tp->fw_len, tp->fw_needed);
7853                 release_firmware(tp->fw);
7854                 tp->fw = NULL;
7855                 return -EINVAL;
7856         }
7857
7858         /* We no longer need firmware; we have it. */
7859         tp->fw_needed = NULL;
7860         return 0;
7861 }
7862
7863 static void tg3_ints_init(struct tg3 *tp)
7864 {
7865         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7866                 /* All MSI supporting chips should support tagged
7867                  * status.  Assert that this is the case.
7868                  */
7869                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7870                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7871                                "Not using MSI.\n", tp->dev->name);
7872                 } else if (pci_enable_msi(tp->pdev) == 0) {
7873                         u32 msi_mode;
7874
7875                         msi_mode = tr32(MSGINT_MODE);
7876                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7877                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7878                 }
7879         }
7880 }
7881
7882 static void tg3_ints_fini(struct tg3 *tp)
7883 {
7884                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7885                         pci_disable_msi(tp->pdev);
7886                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7887                 }
7888 }
7889
7890 static int tg3_open(struct net_device *dev)
7891 {
7892         struct tg3 *tp = netdev_priv(dev);
7893         int err;
7894
7895         if (tp->fw_needed) {
7896                 err = tg3_request_firmware(tp);
7897                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7898                         if (err)
7899                                 return err;
7900                 } else if (err) {
7901                         printk(KERN_WARNING "%s: TSO capability disabled.\n",
7902                                tp->dev->name);
7903                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7904                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7905                         printk(KERN_NOTICE "%s: TSO capability restored.\n",
7906                                tp->dev->name);
7907                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7908                 }
7909         }
7910
7911         netif_carrier_off(tp->dev);
7912
7913         err = tg3_set_power_state(tp, PCI_D0);
7914         if (err)
7915                 return err;
7916
7917         tg3_full_lock(tp, 0);
7918
7919         tg3_disable_ints(tp);
7920         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7921
7922         tg3_full_unlock(tp);
7923
7924         /* The placement of this call is tied
7925          * to the setup and use of Host TX descriptors.
7926          */
7927         err = tg3_alloc_consistent(tp);
7928         if (err)
7929                 return err;
7930
7931         tg3_ints_init(tp);
7932
7933         napi_enable(&tp->napi[0].napi);
7934
7935         err = tg3_request_irq(tp);
7936
7937         if (err)
7938                 goto err_out1;
7939
7940         tg3_full_lock(tp, 0);
7941
7942         err = tg3_init_hw(tp, 1);
7943         if (err) {
7944                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7945                 tg3_free_rings(tp);
7946         } else {
7947                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7948                         tp->timer_offset = HZ;
7949                 else
7950                         tp->timer_offset = HZ / 10;
7951
7952                 BUG_ON(tp->timer_offset > HZ);
7953                 tp->timer_counter = tp->timer_multiplier =
7954                         (HZ / tp->timer_offset);
7955                 tp->asf_counter = tp->asf_multiplier =
7956                         ((HZ / tp->timer_offset) * 2);
7957
7958                 init_timer(&tp->timer);
7959                 tp->timer.expires = jiffies + tp->timer_offset;
7960                 tp->timer.data = (unsigned long) tp;
7961                 tp->timer.function = tg3_timer;
7962         }
7963
7964         tg3_full_unlock(tp);
7965
7966         if (err)
7967                 goto err_out2;
7968
7969         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7970                 err = tg3_test_msi(tp);
7971
7972                 if (err) {
7973                         tg3_full_lock(tp, 0);
7974                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7975                         tg3_free_rings(tp);
7976                         tg3_full_unlock(tp);
7977
7978                         goto err_out1;
7979                 }
7980
7981                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7982                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7983                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7984
7985                                 tw32(PCIE_TRANSACTION_CFG,
7986                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7987                         }
7988                 }
7989         }
7990
7991         tg3_phy_start(tp);
7992
7993         tg3_full_lock(tp, 0);
7994
7995         add_timer(&tp->timer);
7996         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7997         tg3_enable_ints(tp);
7998
7999         tg3_full_unlock(tp);
8000
8001         netif_start_queue(dev);
8002
8003         return 0;
8004
8005 err_out2:
8006         free_irq(tp->pdev->irq, &tp->napi[0]);
8007
8008 err_out1:
8009         napi_disable(&tp->napi[0].napi);
8010         tg3_ints_fini(tp);
8011         tg3_free_consistent(tp);
8012         return err;
8013 }
8014
8015 #if 0
8016 /*static*/ void tg3_dump_state(struct tg3 *tp)
8017 {
8018         u32 val32, val32_2, val32_3, val32_4, val32_5;
8019         u16 val16;
8020         int i;
8021
8022         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8023         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8024         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8025                val16, val32);
8026
8027         /* MAC block */
8028         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8029                tr32(MAC_MODE), tr32(MAC_STATUS));
8030         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8031                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8032         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8033                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8034         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8035                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8036
8037         /* Send data initiator control block */
8038         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8039                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8040         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8041                tr32(SNDDATAI_STATSCTRL));
8042
8043         /* Send data completion control block */
8044         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8045
8046         /* Send BD ring selector block */
8047         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8048                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8049
8050         /* Send BD initiator control block */
8051         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8052                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8053
8054         /* Send BD completion control block */
8055         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8056
8057         /* Receive list placement control block */
8058         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8059                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8060         printk("       RCVLPC_STATSCTRL[%08x]\n",
8061                tr32(RCVLPC_STATSCTRL));
8062
8063         /* Receive data and receive BD initiator control block */
8064         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8065                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8066
8067         /* Receive data completion control block */
8068         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8069                tr32(RCVDCC_MODE));
8070
8071         /* Receive BD initiator control block */
8072         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8073                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8074
8075         /* Receive BD completion control block */
8076         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8077                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8078
8079         /* Receive list selector control block */
8080         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8081                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8082
8083         /* Mbuf cluster free block */
8084         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8085                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8086
8087         /* Host coalescing control block */
8088         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8089                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8090         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8091                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8092                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8093         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8094                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8095                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8096         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8097                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8098         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8099                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8100
8101         /* Memory arbiter control block */
8102         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8103                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8104
8105         /* Buffer manager control block */
8106         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8107                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8108         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8109                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8110         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8111                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8112                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8113                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8114
8115         /* Read DMA control block */
8116         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8117                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8118
8119         /* Write DMA control block */
8120         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8121                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8122
8123         /* DMA completion block */
8124         printk("DEBUG: DMAC_MODE[%08x]\n",
8125                tr32(DMAC_MODE));
8126
8127         /* GRC block */
8128         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8129                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8130         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8131                tr32(GRC_LOCAL_CTRL));
8132
8133         /* TG3_BDINFOs */
8134         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8135                tr32(RCVDBDI_JUMBO_BD + 0x0),
8136                tr32(RCVDBDI_JUMBO_BD + 0x4),
8137                tr32(RCVDBDI_JUMBO_BD + 0x8),
8138                tr32(RCVDBDI_JUMBO_BD + 0xc));
8139         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8140                tr32(RCVDBDI_STD_BD + 0x0),
8141                tr32(RCVDBDI_STD_BD + 0x4),
8142                tr32(RCVDBDI_STD_BD + 0x8),
8143                tr32(RCVDBDI_STD_BD + 0xc));
8144         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8145                tr32(RCVDBDI_MINI_BD + 0x0),
8146                tr32(RCVDBDI_MINI_BD + 0x4),
8147                tr32(RCVDBDI_MINI_BD + 0x8),
8148                tr32(RCVDBDI_MINI_BD + 0xc));
8149
8150         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8151         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8152         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8153         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8154         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8155                val32, val32_2, val32_3, val32_4);
8156
8157         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8158         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8159         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8160         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8161         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8162                val32, val32_2, val32_3, val32_4);
8163
8164         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8165         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8166         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8167         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8168         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8169         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8170                val32, val32_2, val32_3, val32_4, val32_5);
8171
8172         /* SW status block */
8173         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8174                tp->hw_status->status,
8175                tp->hw_status->status_tag,
8176                tp->hw_status->rx_jumbo_consumer,
8177                tp->hw_status->rx_consumer,
8178                tp->hw_status->rx_mini_consumer,
8179                tp->hw_status->idx[0].rx_producer,
8180                tp->hw_status->idx[0].tx_consumer);
8181
8182         /* SW statistics block */
8183         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8184                ((u32 *)tp->hw_stats)[0],
8185                ((u32 *)tp->hw_stats)[1],
8186                ((u32 *)tp->hw_stats)[2],
8187                ((u32 *)tp->hw_stats)[3]);
8188
8189         /* Mailboxes */
8190         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8191                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8192                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8193                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8194                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8195
8196         /* NIC side send descriptors. */
8197         for (i = 0; i < 6; i++) {
8198                 unsigned long txd;
8199
8200                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8201                         + (i * sizeof(struct tg3_tx_buffer_desc));
8202                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8203                        i,
8204                        readl(txd + 0x0), readl(txd + 0x4),
8205                        readl(txd + 0x8), readl(txd + 0xc));
8206         }
8207
8208         /* NIC side RX descriptors. */
8209         for (i = 0; i < 6; i++) {
8210                 unsigned long rxd;
8211
8212                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8213                         + (i * sizeof(struct tg3_rx_buffer_desc));
8214                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8215                        i,
8216                        readl(rxd + 0x0), readl(rxd + 0x4),
8217                        readl(rxd + 0x8), readl(rxd + 0xc));
8218                 rxd += (4 * sizeof(u32));
8219                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8220                        i,
8221                        readl(rxd + 0x0), readl(rxd + 0x4),
8222                        readl(rxd + 0x8), readl(rxd + 0xc));
8223         }
8224
8225         for (i = 0; i < 6; i++) {
8226                 unsigned long rxd;
8227
8228                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8229                         + (i * sizeof(struct tg3_rx_buffer_desc));
8230                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8231                        i,
8232                        readl(rxd + 0x0), readl(rxd + 0x4),
8233                        readl(rxd + 0x8), readl(rxd + 0xc));
8234                 rxd += (4 * sizeof(u32));
8235                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8236                        i,
8237                        readl(rxd + 0x0), readl(rxd + 0x4),
8238                        readl(rxd + 0x8), readl(rxd + 0xc));
8239         }
8240 }
8241 #endif
8242
8243 static struct net_device_stats *tg3_get_stats(struct net_device *);
8244 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8245
8246 static int tg3_close(struct net_device *dev)
8247 {
8248         struct tg3 *tp = netdev_priv(dev);
8249
8250         napi_disable(&tp->napi[0].napi);
8251         cancel_work_sync(&tp->reset_task);
8252
8253         netif_stop_queue(dev);
8254
8255         del_timer_sync(&tp->timer);
8256
8257         tg3_full_lock(tp, 1);
8258 #if 0
8259         tg3_dump_state(tp);
8260 #endif
8261
8262         tg3_disable_ints(tp);
8263
8264         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8265         tg3_free_rings(tp);
8266         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8267
8268         tg3_full_unlock(tp);
8269
8270         free_irq(tp->pdev->irq, &tp->napi[0]);
8271
8272         tg3_ints_fini(tp);
8273
8274         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8275                sizeof(tp->net_stats_prev));
8276         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8277                sizeof(tp->estats_prev));
8278
8279         tg3_free_consistent(tp);
8280
8281         tg3_set_power_state(tp, PCI_D3hot);
8282
8283         netif_carrier_off(tp->dev);
8284
8285         return 0;
8286 }
8287
8288 static inline unsigned long get_stat64(tg3_stat64_t *val)
8289 {
8290         unsigned long ret;
8291
8292 #if (BITS_PER_LONG == 32)
8293         ret = val->low;
8294 #else
8295         ret = ((u64)val->high << 32) | ((u64)val->low);
8296 #endif
8297         return ret;
8298 }
8299
8300 static inline u64 get_estat64(tg3_stat64_t *val)
8301 {
8302        return ((u64)val->high << 32) | ((u64)val->low);
8303 }
8304
8305 static unsigned long calc_crc_errors(struct tg3 *tp)
8306 {
8307         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8308
8309         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8310             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8311              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8312                 u32 val;
8313
8314                 spin_lock_bh(&tp->lock);
8315                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8316                         tg3_writephy(tp, MII_TG3_TEST1,
8317                                      val | MII_TG3_TEST1_CRC_EN);
8318                         tg3_readphy(tp, 0x14, &val);
8319                 } else
8320                         val = 0;
8321                 spin_unlock_bh(&tp->lock);
8322
8323                 tp->phy_crc_errors += val;
8324
8325                 return tp->phy_crc_errors;
8326         }
8327
8328         return get_stat64(&hw_stats->rx_fcs_errors);
8329 }
8330
8331 #define ESTAT_ADD(member) \
8332         estats->member =        old_estats->member + \
8333                                 get_estat64(&hw_stats->member)
8334
8335 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8336 {
8337         struct tg3_ethtool_stats *estats = &tp->estats;
8338         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8339         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8340
8341         if (!hw_stats)
8342                 return old_estats;
8343
8344         ESTAT_ADD(rx_octets);
8345         ESTAT_ADD(rx_fragments);
8346         ESTAT_ADD(rx_ucast_packets);
8347         ESTAT_ADD(rx_mcast_packets);
8348         ESTAT_ADD(rx_bcast_packets);
8349         ESTAT_ADD(rx_fcs_errors);
8350         ESTAT_ADD(rx_align_errors);
8351         ESTAT_ADD(rx_xon_pause_rcvd);
8352         ESTAT_ADD(rx_xoff_pause_rcvd);
8353         ESTAT_ADD(rx_mac_ctrl_rcvd);
8354         ESTAT_ADD(rx_xoff_entered);
8355         ESTAT_ADD(rx_frame_too_long_errors);
8356         ESTAT_ADD(rx_jabbers);
8357         ESTAT_ADD(rx_undersize_packets);
8358         ESTAT_ADD(rx_in_length_errors);
8359         ESTAT_ADD(rx_out_length_errors);
8360         ESTAT_ADD(rx_64_or_less_octet_packets);
8361         ESTAT_ADD(rx_65_to_127_octet_packets);
8362         ESTAT_ADD(rx_128_to_255_octet_packets);
8363         ESTAT_ADD(rx_256_to_511_octet_packets);
8364         ESTAT_ADD(rx_512_to_1023_octet_packets);
8365         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8366         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8367         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8368         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8369         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8370
8371         ESTAT_ADD(tx_octets);
8372         ESTAT_ADD(tx_collisions);
8373         ESTAT_ADD(tx_xon_sent);
8374         ESTAT_ADD(tx_xoff_sent);
8375         ESTAT_ADD(tx_flow_control);
8376         ESTAT_ADD(tx_mac_errors);
8377         ESTAT_ADD(tx_single_collisions);
8378         ESTAT_ADD(tx_mult_collisions);
8379         ESTAT_ADD(tx_deferred);
8380         ESTAT_ADD(tx_excessive_collisions);
8381         ESTAT_ADD(tx_late_collisions);
8382         ESTAT_ADD(tx_collide_2times);
8383         ESTAT_ADD(tx_collide_3times);
8384         ESTAT_ADD(tx_collide_4times);
8385         ESTAT_ADD(tx_collide_5times);
8386         ESTAT_ADD(tx_collide_6times);
8387         ESTAT_ADD(tx_collide_7times);
8388         ESTAT_ADD(tx_collide_8times);
8389         ESTAT_ADD(tx_collide_9times);
8390         ESTAT_ADD(tx_collide_10times);
8391         ESTAT_ADD(tx_collide_11times);
8392         ESTAT_ADD(tx_collide_12times);
8393         ESTAT_ADD(tx_collide_13times);
8394         ESTAT_ADD(tx_collide_14times);
8395         ESTAT_ADD(tx_collide_15times);
8396         ESTAT_ADD(tx_ucast_packets);
8397         ESTAT_ADD(tx_mcast_packets);
8398         ESTAT_ADD(tx_bcast_packets);
8399         ESTAT_ADD(tx_carrier_sense_errors);
8400         ESTAT_ADD(tx_discards);
8401         ESTAT_ADD(tx_errors);
8402
8403         ESTAT_ADD(dma_writeq_full);
8404         ESTAT_ADD(dma_write_prioq_full);
8405         ESTAT_ADD(rxbds_empty);
8406         ESTAT_ADD(rx_discards);
8407         ESTAT_ADD(rx_errors);
8408         ESTAT_ADD(rx_threshold_hit);
8409
8410         ESTAT_ADD(dma_readq_full);
8411         ESTAT_ADD(dma_read_prioq_full);
8412         ESTAT_ADD(tx_comp_queue_full);
8413
8414         ESTAT_ADD(ring_set_send_prod_index);
8415         ESTAT_ADD(ring_status_update);
8416         ESTAT_ADD(nic_irqs);
8417         ESTAT_ADD(nic_avoided_irqs);
8418         ESTAT_ADD(nic_tx_threshold_hit);
8419
8420         return estats;
8421 }
8422
8423 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8424 {
8425         struct tg3 *tp = netdev_priv(dev);
8426         struct net_device_stats *stats = &tp->net_stats;
8427         struct net_device_stats *old_stats = &tp->net_stats_prev;
8428         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8429
8430         if (!hw_stats)
8431                 return old_stats;
8432
8433         stats->rx_packets = old_stats->rx_packets +
8434                 get_stat64(&hw_stats->rx_ucast_packets) +
8435                 get_stat64(&hw_stats->rx_mcast_packets) +
8436                 get_stat64(&hw_stats->rx_bcast_packets);
8437
8438         stats->tx_packets = old_stats->tx_packets +
8439                 get_stat64(&hw_stats->tx_ucast_packets) +
8440                 get_stat64(&hw_stats->tx_mcast_packets) +
8441                 get_stat64(&hw_stats->tx_bcast_packets);
8442
8443         stats->rx_bytes = old_stats->rx_bytes +
8444                 get_stat64(&hw_stats->rx_octets);
8445         stats->tx_bytes = old_stats->tx_bytes +
8446                 get_stat64(&hw_stats->tx_octets);
8447
8448         stats->rx_errors = old_stats->rx_errors +
8449                 get_stat64(&hw_stats->rx_errors);
8450         stats->tx_errors = old_stats->tx_errors +
8451                 get_stat64(&hw_stats->tx_errors) +
8452                 get_stat64(&hw_stats->tx_mac_errors) +
8453                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8454                 get_stat64(&hw_stats->tx_discards);
8455
8456         stats->multicast = old_stats->multicast +
8457                 get_stat64(&hw_stats->rx_mcast_packets);
8458         stats->collisions = old_stats->collisions +
8459                 get_stat64(&hw_stats->tx_collisions);
8460
8461         stats->rx_length_errors = old_stats->rx_length_errors +
8462                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8463                 get_stat64(&hw_stats->rx_undersize_packets);
8464
8465         stats->rx_over_errors = old_stats->rx_over_errors +
8466                 get_stat64(&hw_stats->rxbds_empty);
8467         stats->rx_frame_errors = old_stats->rx_frame_errors +
8468                 get_stat64(&hw_stats->rx_align_errors);
8469         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8470                 get_stat64(&hw_stats->tx_discards);
8471         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8472                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8473
8474         stats->rx_crc_errors = old_stats->rx_crc_errors +
8475                 calc_crc_errors(tp);
8476
8477         stats->rx_missed_errors = old_stats->rx_missed_errors +
8478                 get_stat64(&hw_stats->rx_discards);
8479
8480         return stats;
8481 }
8482
8483 static inline u32 calc_crc(unsigned char *buf, int len)
8484 {
8485         u32 reg;
8486         u32 tmp;
8487         int j, k;
8488
8489         reg = 0xffffffff;
8490
8491         for (j = 0; j < len; j++) {
8492                 reg ^= buf[j];
8493
8494                 for (k = 0; k < 8; k++) {
8495                         tmp = reg & 0x01;
8496
8497                         reg >>= 1;
8498
8499                         if (tmp) {
8500                                 reg ^= 0xedb88320;
8501                         }
8502                 }
8503         }
8504
8505         return ~reg;
8506 }
8507
8508 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8509 {
8510         /* accept or reject all multicast frames */
8511         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8512         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8513         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8514         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8515 }
8516
8517 static void __tg3_set_rx_mode(struct net_device *dev)
8518 {
8519         struct tg3 *tp = netdev_priv(dev);
8520         u32 rx_mode;
8521
8522         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8523                                   RX_MODE_KEEP_VLAN_TAG);
8524
8525         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8526          * flag clear.
8527          */
8528 #if TG3_VLAN_TAG_USED
8529         if (!tp->vlgrp &&
8530             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8531                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8532 #else
8533         /* By definition, VLAN is disabled always in this
8534          * case.
8535          */
8536         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8537                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8538 #endif
8539
8540         if (dev->flags & IFF_PROMISC) {
8541                 /* Promiscuous mode. */
8542                 rx_mode |= RX_MODE_PROMISC;
8543         } else if (dev->flags & IFF_ALLMULTI) {
8544                 /* Accept all multicast. */
8545                 tg3_set_multi (tp, 1);
8546         } else if (dev->mc_count < 1) {
8547                 /* Reject all multicast. */
8548                 tg3_set_multi (tp, 0);
8549         } else {
8550                 /* Accept one or more multicast(s). */
8551                 struct dev_mc_list *mclist;
8552                 unsigned int i;
8553                 u32 mc_filter[4] = { 0, };
8554                 u32 regidx;
8555                 u32 bit;
8556                 u32 crc;
8557
8558                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8559                      i++, mclist = mclist->next) {
8560
8561                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8562                         bit = ~crc & 0x7f;
8563                         regidx = (bit & 0x60) >> 5;
8564                         bit &= 0x1f;
8565                         mc_filter[regidx] |= (1 << bit);
8566                 }
8567
8568                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8569                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8570                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8571                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8572         }
8573
8574         if (rx_mode != tp->rx_mode) {
8575                 tp->rx_mode = rx_mode;
8576                 tw32_f(MAC_RX_MODE, rx_mode);
8577                 udelay(10);
8578         }
8579 }
8580
8581 static void tg3_set_rx_mode(struct net_device *dev)
8582 {
8583         struct tg3 *tp = netdev_priv(dev);
8584
8585         if (!netif_running(dev))
8586                 return;
8587
8588         tg3_full_lock(tp, 0);
8589         __tg3_set_rx_mode(dev);
8590         tg3_full_unlock(tp);
8591 }
8592
8593 #define TG3_REGDUMP_LEN         (32 * 1024)
8594
8595 static int tg3_get_regs_len(struct net_device *dev)
8596 {
8597         return TG3_REGDUMP_LEN;
8598 }
8599
8600 static void tg3_get_regs(struct net_device *dev,
8601                 struct ethtool_regs *regs, void *_p)
8602 {
8603         u32 *p = _p;
8604         struct tg3 *tp = netdev_priv(dev);
8605         u8 *orig_p = _p;
8606         int i;
8607
8608         regs->version = 0;
8609
8610         memset(p, 0, TG3_REGDUMP_LEN);
8611
8612         if (tp->link_config.phy_is_low_power)
8613                 return;
8614
8615         tg3_full_lock(tp, 0);
8616
8617 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8618 #define GET_REG32_LOOP(base,len)                \
8619 do {    p = (u32 *)(orig_p + (base));           \
8620         for (i = 0; i < len; i += 4)            \
8621                 __GET_REG32((base) + i);        \
8622 } while (0)
8623 #define GET_REG32_1(reg)                        \
8624 do {    p = (u32 *)(orig_p + (reg));            \
8625         __GET_REG32((reg));                     \
8626 } while (0)
8627
8628         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8629         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8630         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8631         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8632         GET_REG32_1(SNDDATAC_MODE);
8633         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8634         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8635         GET_REG32_1(SNDBDC_MODE);
8636         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8637         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8638         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8639         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8640         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8641         GET_REG32_1(RCVDCC_MODE);
8642         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8643         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8644         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8645         GET_REG32_1(MBFREE_MODE);
8646         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8647         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8648         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8649         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8650         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8651         GET_REG32_1(RX_CPU_MODE);
8652         GET_REG32_1(RX_CPU_STATE);
8653         GET_REG32_1(RX_CPU_PGMCTR);
8654         GET_REG32_1(RX_CPU_HWBKPT);
8655         GET_REG32_1(TX_CPU_MODE);
8656         GET_REG32_1(TX_CPU_STATE);
8657         GET_REG32_1(TX_CPU_PGMCTR);
8658         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8659         GET_REG32_LOOP(FTQ_RESET, 0x120);
8660         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8661         GET_REG32_1(DMAC_MODE);
8662         GET_REG32_LOOP(GRC_MODE, 0x4c);
8663         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8664                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8665
8666 #undef __GET_REG32
8667 #undef GET_REG32_LOOP
8668 #undef GET_REG32_1
8669
8670         tg3_full_unlock(tp);
8671 }
8672
8673 static int tg3_get_eeprom_len(struct net_device *dev)
8674 {
8675         struct tg3 *tp = netdev_priv(dev);
8676
8677         return tp->nvram_size;
8678 }
8679
8680 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8681 {
8682         struct tg3 *tp = netdev_priv(dev);
8683         int ret;
8684         u8  *pd;
8685         u32 i, offset, len, b_offset, b_count;
8686         __be32 val;
8687
8688         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8689                 return -EINVAL;
8690
8691         if (tp->link_config.phy_is_low_power)
8692                 return -EAGAIN;
8693
8694         offset = eeprom->offset;
8695         len = eeprom->len;
8696         eeprom->len = 0;
8697
8698         eeprom->magic = TG3_EEPROM_MAGIC;
8699
8700         if (offset & 3) {
8701                 /* adjustments to start on required 4 byte boundary */
8702                 b_offset = offset & 3;
8703                 b_count = 4 - b_offset;
8704                 if (b_count > len) {
8705                         /* i.e. offset=1 len=2 */
8706                         b_count = len;
8707                 }
8708                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8709                 if (ret)
8710                         return ret;
8711                 memcpy(data, ((char*)&val) + b_offset, b_count);
8712                 len -= b_count;
8713                 offset += b_count;
8714                 eeprom->len += b_count;
8715         }
8716
8717         /* read bytes upto the last 4 byte boundary */
8718         pd = &data[eeprom->len];
8719         for (i = 0; i < (len - (len & 3)); i += 4) {
8720                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8721                 if (ret) {
8722                         eeprom->len += i;
8723                         return ret;
8724                 }
8725                 memcpy(pd + i, &val, 4);
8726         }
8727         eeprom->len += i;
8728
8729         if (len & 3) {
8730                 /* read last bytes not ending on 4 byte boundary */
8731                 pd = &data[eeprom->len];
8732                 b_count = len & 3;
8733                 b_offset = offset + len - b_count;
8734                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8735                 if (ret)
8736                         return ret;
8737                 memcpy(pd, &val, b_count);
8738                 eeprom->len += b_count;
8739         }
8740         return 0;
8741 }
8742
8743 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8744
8745 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8746 {
8747         struct tg3 *tp = netdev_priv(dev);
8748         int ret;
8749         u32 offset, len, b_offset, odd_len;
8750         u8 *buf;
8751         __be32 start, end;
8752
8753         if (tp->link_config.phy_is_low_power)
8754                 return -EAGAIN;
8755
8756         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8757             eeprom->magic != TG3_EEPROM_MAGIC)
8758                 return -EINVAL;
8759
8760         offset = eeprom->offset;
8761         len = eeprom->len;
8762
8763         if ((b_offset = (offset & 3))) {
8764                 /* adjustments to start on required 4 byte boundary */
8765                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8766                 if (ret)
8767                         return ret;
8768                 len += b_offset;
8769                 offset &= ~3;
8770                 if (len < 4)
8771                         len = 4;
8772         }
8773
8774         odd_len = 0;
8775         if (len & 3) {
8776                 /* adjustments to end on required 4 byte boundary */
8777                 odd_len = 1;
8778                 len = (len + 3) & ~3;
8779                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8780                 if (ret)
8781                         return ret;
8782         }
8783
8784         buf = data;
8785         if (b_offset || odd_len) {
8786                 buf = kmalloc(len, GFP_KERNEL);
8787                 if (!buf)
8788                         return -ENOMEM;
8789                 if (b_offset)
8790                         memcpy(buf, &start, 4);
8791                 if (odd_len)
8792                         memcpy(buf+len-4, &end, 4);
8793                 memcpy(buf + b_offset, data, eeprom->len);
8794         }
8795
8796         ret = tg3_nvram_write_block(tp, offset, len, buf);
8797
8798         if (buf != data)
8799                 kfree(buf);
8800
8801         return ret;
8802 }
8803
8804 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8805 {
8806         struct tg3 *tp = netdev_priv(dev);
8807
8808         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8809                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8810                         return -EAGAIN;
8811                 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8812         }
8813
8814         cmd->supported = (SUPPORTED_Autoneg);
8815
8816         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8817                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8818                                    SUPPORTED_1000baseT_Full);
8819
8820         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8821                 cmd->supported |= (SUPPORTED_100baseT_Half |
8822                                   SUPPORTED_100baseT_Full |
8823                                   SUPPORTED_10baseT_Half |
8824                                   SUPPORTED_10baseT_Full |
8825                                   SUPPORTED_TP);
8826                 cmd->port = PORT_TP;
8827         } else {
8828                 cmd->supported |= SUPPORTED_FIBRE;
8829                 cmd->port = PORT_FIBRE;
8830         }
8831
8832         cmd->advertising = tp->link_config.advertising;
8833         if (netif_running(dev)) {
8834                 cmd->speed = tp->link_config.active_speed;
8835                 cmd->duplex = tp->link_config.active_duplex;
8836         }
8837         cmd->phy_address = PHY_ADDR;
8838         cmd->transceiver = XCVR_INTERNAL;
8839         cmd->autoneg = tp->link_config.autoneg;
8840         cmd->maxtxpkt = 0;
8841         cmd->maxrxpkt = 0;
8842         return 0;
8843 }
8844
8845 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8846 {
8847         struct tg3 *tp = netdev_priv(dev);
8848
8849         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8850                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8851                         return -EAGAIN;
8852                 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8853         }
8854
8855         if (cmd->autoneg != AUTONEG_ENABLE &&
8856             cmd->autoneg != AUTONEG_DISABLE)
8857                 return -EINVAL;
8858
8859         if (cmd->autoneg == AUTONEG_DISABLE &&
8860             cmd->duplex != DUPLEX_FULL &&
8861             cmd->duplex != DUPLEX_HALF)
8862                 return -EINVAL;
8863
8864         if (cmd->autoneg == AUTONEG_ENABLE) {
8865                 u32 mask = ADVERTISED_Autoneg |
8866                            ADVERTISED_Pause |
8867                            ADVERTISED_Asym_Pause;
8868
8869                 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8870                         mask |= ADVERTISED_1000baseT_Half |
8871                                 ADVERTISED_1000baseT_Full;
8872
8873                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8874                         mask |= ADVERTISED_100baseT_Half |
8875                                 ADVERTISED_100baseT_Full |
8876                                 ADVERTISED_10baseT_Half |
8877                                 ADVERTISED_10baseT_Full |
8878                                 ADVERTISED_TP;
8879                 else
8880                         mask |= ADVERTISED_FIBRE;
8881
8882                 if (cmd->advertising & ~mask)
8883                         return -EINVAL;
8884
8885                 mask &= (ADVERTISED_1000baseT_Half |
8886                          ADVERTISED_1000baseT_Full |
8887                          ADVERTISED_100baseT_Half |
8888                          ADVERTISED_100baseT_Full |
8889                          ADVERTISED_10baseT_Half |
8890                          ADVERTISED_10baseT_Full);
8891
8892                 cmd->advertising &= mask;
8893         } else {
8894                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8895                         if (cmd->speed != SPEED_1000)
8896                                 return -EINVAL;
8897
8898                         if (cmd->duplex != DUPLEX_FULL)
8899                                 return -EINVAL;
8900                 } else {
8901                         if (cmd->speed != SPEED_100 &&
8902                             cmd->speed != SPEED_10)
8903                                 return -EINVAL;
8904                 }
8905         }
8906
8907         tg3_full_lock(tp, 0);
8908
8909         tp->link_config.autoneg = cmd->autoneg;
8910         if (cmd->autoneg == AUTONEG_ENABLE) {
8911                 tp->link_config.advertising = (cmd->advertising |
8912                                               ADVERTISED_Autoneg);
8913                 tp->link_config.speed = SPEED_INVALID;
8914                 tp->link_config.duplex = DUPLEX_INVALID;
8915         } else {
8916                 tp->link_config.advertising = 0;
8917                 tp->link_config.speed = cmd->speed;
8918                 tp->link_config.duplex = cmd->duplex;
8919         }
8920
8921         tp->link_config.orig_speed = tp->link_config.speed;
8922         tp->link_config.orig_duplex = tp->link_config.duplex;
8923         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8924
8925         if (netif_running(dev))
8926                 tg3_setup_phy(tp, 1);
8927
8928         tg3_full_unlock(tp);
8929
8930         return 0;
8931 }
8932
8933 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8934 {
8935         struct tg3 *tp = netdev_priv(dev);
8936
8937         strcpy(info->driver, DRV_MODULE_NAME);
8938         strcpy(info->version, DRV_MODULE_VERSION);
8939         strcpy(info->fw_version, tp->fw_ver);
8940         strcpy(info->bus_info, pci_name(tp->pdev));
8941 }
8942
8943 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8944 {
8945         struct tg3 *tp = netdev_priv(dev);
8946
8947         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8948             device_can_wakeup(&tp->pdev->dev))
8949                 wol->supported = WAKE_MAGIC;
8950         else
8951                 wol->supported = 0;
8952         wol->wolopts = 0;
8953         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8954             device_can_wakeup(&tp->pdev->dev))
8955                 wol->wolopts = WAKE_MAGIC;
8956         memset(&wol->sopass, 0, sizeof(wol->sopass));
8957 }
8958
8959 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8960 {
8961         struct tg3 *tp = netdev_priv(dev);
8962         struct device *dp = &tp->pdev->dev;
8963
8964         if (wol->wolopts & ~WAKE_MAGIC)
8965                 return -EINVAL;
8966         if ((wol->wolopts & WAKE_MAGIC) &&
8967             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8968                 return -EINVAL;
8969
8970         spin_lock_bh(&tp->lock);
8971         if (wol->wolopts & WAKE_MAGIC) {
8972                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8973                 device_set_wakeup_enable(dp, true);
8974         } else {
8975                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8976                 device_set_wakeup_enable(dp, false);
8977         }
8978         spin_unlock_bh(&tp->lock);
8979
8980         return 0;
8981 }
8982
8983 static u32 tg3_get_msglevel(struct net_device *dev)
8984 {
8985         struct tg3 *tp = netdev_priv(dev);
8986         return tp->msg_enable;
8987 }
8988
8989 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8990 {
8991         struct tg3 *tp = netdev_priv(dev);
8992         tp->msg_enable = value;
8993 }
8994
8995 static int tg3_set_tso(struct net_device *dev, u32 value)
8996 {
8997         struct tg3 *tp = netdev_priv(dev);
8998
8999         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9000                 if (value)
9001                         return -EINVAL;
9002                 return 0;
9003         }
9004         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9005             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9006                 if (value) {
9007                         dev->features |= NETIF_F_TSO6;
9008                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9009                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9010                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9011                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9012                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9013                                 dev->features |= NETIF_F_TSO_ECN;
9014                 } else
9015                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9016         }
9017         return ethtool_op_set_tso(dev, value);
9018 }
9019
9020 static int tg3_nway_reset(struct net_device *dev)
9021 {
9022         struct tg3 *tp = netdev_priv(dev);
9023         int r;
9024
9025         if (!netif_running(dev))
9026                 return -EAGAIN;
9027
9028         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9029                 return -EINVAL;
9030
9031         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9032                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9033                         return -EAGAIN;
9034                 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9035         } else {
9036                 u32 bmcr;
9037
9038                 spin_lock_bh(&tp->lock);
9039                 r = -EINVAL;
9040                 tg3_readphy(tp, MII_BMCR, &bmcr);
9041                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9042                     ((bmcr & BMCR_ANENABLE) ||
9043                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9044                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9045                                                    BMCR_ANENABLE);
9046                         r = 0;
9047                 }
9048                 spin_unlock_bh(&tp->lock);
9049         }
9050
9051         return r;
9052 }
9053
9054 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9055 {
9056         struct tg3 *tp = netdev_priv(dev);
9057
9058         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9059         ering->rx_mini_max_pending = 0;
9060         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9061                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9062         else
9063                 ering->rx_jumbo_max_pending = 0;
9064
9065         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9066
9067         ering->rx_pending = tp->rx_pending;
9068         ering->rx_mini_pending = 0;
9069         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9070                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9071         else
9072                 ering->rx_jumbo_pending = 0;
9073
9074         ering->tx_pending = tp->tx_pending;
9075 }
9076
9077 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9078 {
9079         struct tg3 *tp = netdev_priv(dev);
9080         int irq_sync = 0, err = 0;
9081
9082         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9083             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9084             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9085             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9086             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9087              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9088                 return -EINVAL;
9089
9090         if (netif_running(dev)) {
9091                 tg3_phy_stop(tp);
9092                 tg3_netif_stop(tp);
9093                 irq_sync = 1;
9094         }
9095
9096         tg3_full_lock(tp, irq_sync);
9097
9098         tp->rx_pending = ering->rx_pending;
9099
9100         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9101             tp->rx_pending > 63)
9102                 tp->rx_pending = 63;
9103         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9104         tp->tx_pending = ering->tx_pending;
9105
9106         if (netif_running(dev)) {
9107                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9108                 err = tg3_restart_hw(tp, 1);
9109                 if (!err)
9110                         tg3_netif_start(tp);
9111         }
9112
9113         tg3_full_unlock(tp);
9114
9115         if (irq_sync && !err)
9116                 tg3_phy_start(tp);
9117
9118         return err;
9119 }
9120
9121 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9122 {
9123         struct tg3 *tp = netdev_priv(dev);
9124
9125         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9126
9127         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9128                 epause->rx_pause = 1;
9129         else
9130                 epause->rx_pause = 0;
9131
9132         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9133                 epause->tx_pause = 1;
9134         else
9135                 epause->tx_pause = 0;
9136 }
9137
9138 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9139 {
9140         struct tg3 *tp = netdev_priv(dev);
9141         int err = 0;
9142
9143         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9144                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9145                         return -EAGAIN;
9146
9147                 if (epause->autoneg) {
9148                         u32 newadv;
9149                         struct phy_device *phydev;
9150
9151                         phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9152
9153                         if (epause->rx_pause) {
9154                                 if (epause->tx_pause)
9155                                         newadv = ADVERTISED_Pause;
9156                                 else
9157                                         newadv = ADVERTISED_Pause |
9158                                                  ADVERTISED_Asym_Pause;
9159                         } else if (epause->tx_pause) {
9160                                 newadv = ADVERTISED_Asym_Pause;
9161                         } else
9162                                 newadv = 0;
9163
9164                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9165                                 u32 oldadv = phydev->advertising &
9166                                              (ADVERTISED_Pause |
9167                                               ADVERTISED_Asym_Pause);
9168                                 if (oldadv != newadv) {
9169                                         phydev->advertising &=
9170                                                 ~(ADVERTISED_Pause |
9171                                                   ADVERTISED_Asym_Pause);
9172                                         phydev->advertising |= newadv;
9173                                         err = phy_start_aneg(phydev);
9174                                 }
9175                         } else {
9176                                 tp->link_config.advertising &=
9177                                                 ~(ADVERTISED_Pause |
9178                                                   ADVERTISED_Asym_Pause);
9179                                 tp->link_config.advertising |= newadv;
9180                         }
9181                 } else {
9182                         if (epause->rx_pause)
9183                                 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9184                         else
9185                                 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9186
9187                         if (epause->tx_pause)
9188                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9189                         else
9190                                 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9191
9192                         if (netif_running(dev))
9193                                 tg3_setup_flow_control(tp, 0, 0);
9194                 }
9195         } else {
9196                 int irq_sync = 0;
9197
9198                 if (netif_running(dev)) {
9199                         tg3_netif_stop(tp);
9200                         irq_sync = 1;
9201                 }
9202
9203                 tg3_full_lock(tp, irq_sync);
9204
9205                 if (epause->autoneg)
9206                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9207                 else
9208                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9209                 if (epause->rx_pause)
9210                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9211                 else
9212                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9213                 if (epause->tx_pause)
9214                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9215                 else
9216                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9217
9218                 if (netif_running(dev)) {
9219                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9220                         err = tg3_restart_hw(tp, 1);
9221                         if (!err)
9222                                 tg3_netif_start(tp);
9223                 }
9224
9225                 tg3_full_unlock(tp);
9226         }
9227
9228         return err;
9229 }
9230
9231 static u32 tg3_get_rx_csum(struct net_device *dev)
9232 {
9233         struct tg3 *tp = netdev_priv(dev);
9234         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9235 }
9236
9237 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9238 {
9239         struct tg3 *tp = netdev_priv(dev);
9240
9241         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9242                 if (data != 0)
9243                         return -EINVAL;
9244                 return 0;
9245         }
9246
9247         spin_lock_bh(&tp->lock);
9248         if (data)
9249                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9250         else
9251                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9252         spin_unlock_bh(&tp->lock);
9253
9254         return 0;
9255 }
9256
9257 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9258 {
9259         struct tg3 *tp = netdev_priv(dev);
9260
9261         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9262                 if (data != 0)
9263                         return -EINVAL;
9264                 return 0;
9265         }
9266
9267         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9268                 ethtool_op_set_tx_ipv6_csum(dev, data);
9269         else
9270                 ethtool_op_set_tx_csum(dev, data);
9271
9272         return 0;
9273 }
9274
9275 static int tg3_get_sset_count (struct net_device *dev, int sset)
9276 {
9277         switch (sset) {
9278         case ETH_SS_TEST:
9279                 return TG3_NUM_TEST;
9280         case ETH_SS_STATS:
9281                 return TG3_NUM_STATS;
9282         default:
9283                 return -EOPNOTSUPP;
9284         }
9285 }
9286
9287 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9288 {
9289         switch (stringset) {
9290         case ETH_SS_STATS:
9291                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9292                 break;
9293         case ETH_SS_TEST:
9294                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9295                 break;
9296         default:
9297                 WARN_ON(1);     /* we need a WARN() */
9298                 break;
9299         }
9300 }
9301
9302 static int tg3_phys_id(struct net_device *dev, u32 data)
9303 {
9304         struct tg3 *tp = netdev_priv(dev);
9305         int i;
9306
9307         if (!netif_running(tp->dev))
9308                 return -EAGAIN;
9309
9310         if (data == 0)
9311                 data = UINT_MAX / 2;
9312
9313         for (i = 0; i < (data * 2); i++) {
9314                 if ((i % 2) == 0)
9315                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9316                                            LED_CTRL_1000MBPS_ON |
9317                                            LED_CTRL_100MBPS_ON |
9318                                            LED_CTRL_10MBPS_ON |
9319                                            LED_CTRL_TRAFFIC_OVERRIDE |
9320                                            LED_CTRL_TRAFFIC_BLINK |
9321                                            LED_CTRL_TRAFFIC_LED);
9322
9323                 else
9324                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9325                                            LED_CTRL_TRAFFIC_OVERRIDE);
9326
9327                 if (msleep_interruptible(500))
9328                         break;
9329         }
9330         tw32(MAC_LED_CTRL, tp->led_ctrl);
9331         return 0;
9332 }
9333
9334 static void tg3_get_ethtool_stats (struct net_device *dev,
9335                                    struct ethtool_stats *estats, u64 *tmp_stats)
9336 {
9337         struct tg3 *tp = netdev_priv(dev);
9338         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9339 }
9340
9341 #define NVRAM_TEST_SIZE 0x100
9342 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9343 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9344 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9345 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9346 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9347
9348 static int tg3_test_nvram(struct tg3 *tp)
9349 {
9350         u32 csum, magic;
9351         __be32 *buf;
9352         int i, j, k, err = 0, size;
9353
9354         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9355                 return 0;
9356
9357         if (tg3_nvram_read(tp, 0, &magic) != 0)
9358                 return -EIO;
9359
9360         if (magic == TG3_EEPROM_MAGIC)
9361                 size = NVRAM_TEST_SIZE;
9362         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9363                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9364                     TG3_EEPROM_SB_FORMAT_1) {
9365                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9366                         case TG3_EEPROM_SB_REVISION_0:
9367                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9368                                 break;
9369                         case TG3_EEPROM_SB_REVISION_2:
9370                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9371                                 break;
9372                         case TG3_EEPROM_SB_REVISION_3:
9373                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9374                                 break;
9375                         default:
9376                                 return 0;
9377                         }
9378                 } else
9379                         return 0;
9380         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9381                 size = NVRAM_SELFBOOT_HW_SIZE;
9382         else
9383                 return -EIO;
9384
9385         buf = kmalloc(size, GFP_KERNEL);
9386         if (buf == NULL)
9387                 return -ENOMEM;
9388
9389         err = -EIO;
9390         for (i = 0, j = 0; i < size; i += 4, j++) {
9391                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9392                 if (err)
9393                         break;
9394         }
9395         if (i < size)
9396                 goto out;
9397
9398         /* Selfboot format */
9399         magic = be32_to_cpu(buf[0]);
9400         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9401             TG3_EEPROM_MAGIC_FW) {
9402                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9403
9404                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9405                     TG3_EEPROM_SB_REVISION_2) {
9406                         /* For rev 2, the csum doesn't include the MBA. */
9407                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9408                                 csum8 += buf8[i];
9409                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9410                                 csum8 += buf8[i];
9411                 } else {
9412                         for (i = 0; i < size; i++)
9413                                 csum8 += buf8[i];
9414                 }
9415
9416                 if (csum8 == 0) {
9417                         err = 0;
9418                         goto out;
9419                 }
9420
9421                 err = -EIO;
9422                 goto out;
9423         }
9424
9425         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9426             TG3_EEPROM_MAGIC_HW) {
9427                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9428                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9429                 u8 *buf8 = (u8 *) buf;
9430
9431                 /* Separate the parity bits and the data bytes.  */
9432                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9433                         if ((i == 0) || (i == 8)) {
9434                                 int l;
9435                                 u8 msk;
9436
9437                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9438                                         parity[k++] = buf8[i] & msk;
9439                                 i++;
9440                         }
9441                         else if (i == 16) {
9442                                 int l;
9443                                 u8 msk;
9444
9445                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9446                                         parity[k++] = buf8[i] & msk;
9447                                 i++;
9448
9449                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9450                                         parity[k++] = buf8[i] & msk;
9451                                 i++;
9452                         }
9453                         data[j++] = buf8[i];
9454                 }
9455
9456                 err = -EIO;
9457                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9458                         u8 hw8 = hweight8(data[i]);
9459
9460                         if ((hw8 & 0x1) && parity[i])
9461                                 goto out;
9462                         else if (!(hw8 & 0x1) && !parity[i])
9463                                 goto out;
9464                 }
9465                 err = 0;
9466                 goto out;
9467         }
9468
9469         /* Bootstrap checksum at offset 0x10 */
9470         csum = calc_crc((unsigned char *) buf, 0x10);
9471         if (csum != be32_to_cpu(buf[0x10/4]))
9472                 goto out;
9473
9474         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9475         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9476         if (csum != be32_to_cpu(buf[0xfc/4]))
9477                 goto out;
9478
9479         err = 0;
9480
9481 out:
9482         kfree(buf);
9483         return err;
9484 }
9485
9486 #define TG3_SERDES_TIMEOUT_SEC  2
9487 #define TG3_COPPER_TIMEOUT_SEC  6
9488
9489 static int tg3_test_link(struct tg3 *tp)
9490 {
9491         int i, max;
9492
9493         if (!netif_running(tp->dev))
9494                 return -ENODEV;
9495
9496         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9497                 max = TG3_SERDES_TIMEOUT_SEC;
9498         else
9499                 max = TG3_COPPER_TIMEOUT_SEC;
9500
9501         for (i = 0; i < max; i++) {
9502                 if (netif_carrier_ok(tp->dev))
9503                         return 0;
9504
9505                 if (msleep_interruptible(1000))
9506                         break;
9507         }
9508
9509         return -EIO;
9510 }
9511
9512 /* Only test the commonly used registers */
9513 static int tg3_test_registers(struct tg3 *tp)
9514 {
9515         int i, is_5705, is_5750;
9516         u32 offset, read_mask, write_mask, val, save_val, read_val;
9517         static struct {
9518                 u16 offset;
9519                 u16 flags;
9520 #define TG3_FL_5705     0x1
9521 #define TG3_FL_NOT_5705 0x2
9522 #define TG3_FL_NOT_5788 0x4
9523 #define TG3_FL_NOT_5750 0x8
9524                 u32 read_mask;
9525                 u32 write_mask;
9526         } reg_tbl[] = {
9527                 /* MAC Control Registers */
9528                 { MAC_MODE, TG3_FL_NOT_5705,
9529                         0x00000000, 0x00ef6f8c },
9530                 { MAC_MODE, TG3_FL_5705,
9531                         0x00000000, 0x01ef6b8c },
9532                 { MAC_STATUS, TG3_FL_NOT_5705,
9533                         0x03800107, 0x00000000 },
9534                 { MAC_STATUS, TG3_FL_5705,
9535                         0x03800100, 0x00000000 },
9536                 { MAC_ADDR_0_HIGH, 0x0000,
9537                         0x00000000, 0x0000ffff },
9538                 { MAC_ADDR_0_LOW, 0x0000,
9539                         0x00000000, 0xffffffff },
9540                 { MAC_RX_MTU_SIZE, 0x0000,
9541                         0x00000000, 0x0000ffff },
9542                 { MAC_TX_MODE, 0x0000,
9543                         0x00000000, 0x00000070 },
9544                 { MAC_TX_LENGTHS, 0x0000,
9545                         0x00000000, 0x00003fff },
9546                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9547                         0x00000000, 0x000007fc },
9548                 { MAC_RX_MODE, TG3_FL_5705,
9549                         0x00000000, 0x000007dc },
9550                 { MAC_HASH_REG_0, 0x0000,
9551                         0x00000000, 0xffffffff },
9552                 { MAC_HASH_REG_1, 0x0000,
9553                         0x00000000, 0xffffffff },
9554                 { MAC_HASH_REG_2, 0x0000,
9555                         0x00000000, 0xffffffff },
9556                 { MAC_HASH_REG_3, 0x0000,
9557                         0x00000000, 0xffffffff },
9558
9559                 /* Receive Data and Receive BD Initiator Control Registers. */
9560                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9561                         0x00000000, 0xffffffff },
9562                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9563                         0x00000000, 0xffffffff },
9564                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9565                         0x00000000, 0x00000003 },
9566                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9567                         0x00000000, 0xffffffff },
9568                 { RCVDBDI_STD_BD+0, 0x0000,
9569                         0x00000000, 0xffffffff },
9570                 { RCVDBDI_STD_BD+4, 0x0000,
9571                         0x00000000, 0xffffffff },
9572                 { RCVDBDI_STD_BD+8, 0x0000,
9573                         0x00000000, 0xffff0002 },
9574                 { RCVDBDI_STD_BD+0xc, 0x0000,
9575                         0x00000000, 0xffffffff },
9576
9577                 /* Receive BD Initiator Control Registers. */
9578                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9579                         0x00000000, 0xffffffff },
9580                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9581                         0x00000000, 0x000003ff },
9582                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9583                         0x00000000, 0xffffffff },
9584
9585                 /* Host Coalescing Control Registers. */
9586                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9587                         0x00000000, 0x00000004 },
9588                 { HOSTCC_MODE, TG3_FL_5705,
9589                         0x00000000, 0x000000f6 },
9590                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9591                         0x00000000, 0xffffffff },
9592                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9593                         0x00000000, 0x000003ff },
9594                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9595                         0x00000000, 0xffffffff },
9596                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9597                         0x00000000, 0x000003ff },
9598                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9599                         0x00000000, 0xffffffff },
9600                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9601                         0x00000000, 0x000000ff },
9602                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9603                         0x00000000, 0xffffffff },
9604                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9605                         0x00000000, 0x000000ff },
9606                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9607                         0x00000000, 0xffffffff },
9608                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9609                         0x00000000, 0xffffffff },
9610                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9611                         0x00000000, 0xffffffff },
9612                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9613                         0x00000000, 0x000000ff },
9614                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9615                         0x00000000, 0xffffffff },
9616                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9617                         0x00000000, 0x000000ff },
9618                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9619                         0x00000000, 0xffffffff },
9620                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9621                         0x00000000, 0xffffffff },
9622                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9623                         0x00000000, 0xffffffff },
9624                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9625                         0x00000000, 0xffffffff },
9626                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9627                         0x00000000, 0xffffffff },
9628                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9629                         0xffffffff, 0x00000000 },
9630                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9631                         0xffffffff, 0x00000000 },
9632
9633                 /* Buffer Manager Control Registers. */
9634                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9635                         0x00000000, 0x007fff80 },
9636                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9637                         0x00000000, 0x007fffff },
9638                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9639                         0x00000000, 0x0000003f },
9640                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9641                         0x00000000, 0x000001ff },
9642                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9643                         0x00000000, 0x000001ff },
9644                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9645                         0xffffffff, 0x00000000 },
9646                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9647                         0xffffffff, 0x00000000 },
9648
9649                 /* Mailbox Registers */
9650                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9651                         0x00000000, 0x000001ff },
9652                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9653                         0x00000000, 0x000001ff },
9654                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9655                         0x00000000, 0x000007ff },
9656                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9657                         0x00000000, 0x000001ff },
9658
9659                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9660         };
9661
9662         is_5705 = is_5750 = 0;
9663         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9664                 is_5705 = 1;
9665                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9666                         is_5750 = 1;
9667         }
9668
9669         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9670                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9671                         continue;
9672
9673                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9674                         continue;
9675
9676                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9677                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9678                         continue;
9679
9680                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9681                         continue;
9682
9683                 offset = (u32) reg_tbl[i].offset;
9684                 read_mask = reg_tbl[i].read_mask;
9685                 write_mask = reg_tbl[i].write_mask;
9686
9687                 /* Save the original register content */
9688                 save_val = tr32(offset);
9689
9690                 /* Determine the read-only value. */
9691                 read_val = save_val & read_mask;
9692
9693                 /* Write zero to the register, then make sure the read-only bits
9694                  * are not changed and the read/write bits are all zeros.
9695                  */
9696                 tw32(offset, 0);
9697
9698                 val = tr32(offset);
9699
9700                 /* Test the read-only and read/write bits. */
9701                 if (((val & read_mask) != read_val) || (val & write_mask))
9702                         goto out;
9703
9704                 /* Write ones to all the bits defined by RdMask and WrMask, then
9705                  * make sure the read-only bits are not changed and the
9706                  * read/write bits are all ones.
9707                  */
9708                 tw32(offset, read_mask | write_mask);
9709
9710                 val = tr32(offset);
9711
9712                 /* Test the read-only bits. */
9713                 if ((val & read_mask) != read_val)
9714                         goto out;
9715
9716                 /* Test the read/write bits. */
9717                 if ((val & write_mask) != write_mask)
9718                         goto out;
9719
9720                 tw32(offset, save_val);
9721         }
9722
9723         return 0;
9724
9725 out:
9726         if (netif_msg_hw(tp))
9727                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9728                        offset);
9729         tw32(offset, save_val);
9730         return -EIO;
9731 }
9732
9733 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9734 {
9735         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9736         int i;
9737         u32 j;
9738
9739         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9740                 for (j = 0; j < len; j += 4) {
9741                         u32 val;
9742
9743                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9744                         tg3_read_mem(tp, offset + j, &val);
9745                         if (val != test_pattern[i])
9746                                 return -EIO;
9747                 }
9748         }
9749         return 0;
9750 }
9751
9752 static int tg3_test_memory(struct tg3 *tp)
9753 {
9754         static struct mem_entry {
9755                 u32 offset;
9756                 u32 len;
9757         } mem_tbl_570x[] = {
9758                 { 0x00000000, 0x00b50},
9759                 { 0x00002000, 0x1c000},
9760                 { 0xffffffff, 0x00000}
9761         }, mem_tbl_5705[] = {
9762                 { 0x00000100, 0x0000c},
9763                 { 0x00000200, 0x00008},
9764                 { 0x00004000, 0x00800},
9765                 { 0x00006000, 0x01000},
9766                 { 0x00008000, 0x02000},
9767                 { 0x00010000, 0x0e000},
9768                 { 0xffffffff, 0x00000}
9769         }, mem_tbl_5755[] = {
9770                 { 0x00000200, 0x00008},
9771                 { 0x00004000, 0x00800},
9772                 { 0x00006000, 0x00800},
9773                 { 0x00008000, 0x02000},
9774                 { 0x00010000, 0x0c000},
9775                 { 0xffffffff, 0x00000}
9776         }, mem_tbl_5906[] = {
9777                 { 0x00000200, 0x00008},
9778                 { 0x00004000, 0x00400},
9779                 { 0x00006000, 0x00400},
9780                 { 0x00008000, 0x01000},
9781                 { 0x00010000, 0x01000},
9782                 { 0xffffffff, 0x00000}
9783         };
9784         struct mem_entry *mem_tbl;
9785         int err = 0;
9786         int i;
9787
9788         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9789                 mem_tbl = mem_tbl_5755;
9790         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9791                 mem_tbl = mem_tbl_5906;
9792         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9793                 mem_tbl = mem_tbl_5705;
9794         else
9795                 mem_tbl = mem_tbl_570x;
9796
9797         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9798                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9799                     mem_tbl[i].len)) != 0)
9800                         break;
9801         }
9802
9803         return err;
9804 }
9805
9806 #define TG3_MAC_LOOPBACK        0
9807 #define TG3_PHY_LOOPBACK        1
9808
9809 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9810 {
9811         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9812         u32 desc_idx;
9813         struct sk_buff *skb, *rx_skb;
9814         u8 *tx_data;
9815         dma_addr_t map;
9816         int num_pkts, tx_len, rx_len, i, err;
9817         struct tg3_rx_buffer_desc *desc;
9818         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
9819
9820         if (loopback_mode == TG3_MAC_LOOPBACK) {
9821                 /* HW errata - mac loopback fails in some cases on 5780.
9822                  * Normal traffic and PHY loopback are not affected by
9823                  * errata.
9824                  */
9825                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9826                         return 0;
9827
9828                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9829                            MAC_MODE_PORT_INT_LPBACK;
9830                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9831                         mac_mode |= MAC_MODE_LINK_POLARITY;
9832                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9833                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9834                 else
9835                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9836                 tw32(MAC_MODE, mac_mode);
9837         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9838                 u32 val;
9839
9840                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9841                         tg3_phy_fet_toggle_apd(tp, false);
9842                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9843                 } else
9844                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9845
9846                 tg3_phy_toggle_automdix(tp, 0);
9847
9848                 tg3_writephy(tp, MII_BMCR, val);
9849                 udelay(40);
9850
9851                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9852                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
9853                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9854                                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
9855                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9856                 } else
9857                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9858
9859                 /* reset to prevent losing 1st rx packet intermittently */
9860                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9861                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9862                         udelay(10);
9863                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9864                 }
9865                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9866                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9867                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9868                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9869                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9870                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9871                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9872                 }
9873                 tw32(MAC_MODE, mac_mode);
9874         }
9875         else
9876                 return -EINVAL;
9877
9878         err = -EIO;
9879
9880         tx_len = 1514;
9881         skb = netdev_alloc_skb(tp->dev, tx_len);
9882         if (!skb)
9883                 return -ENOMEM;
9884
9885         tx_data = skb_put(skb, tx_len);
9886         memcpy(tx_data, tp->dev->dev_addr, 6);
9887         memset(tx_data + 6, 0x0, 8);
9888
9889         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9890
9891         for (i = 14; i < tx_len; i++)
9892                 tx_data[i] = (u8) (i & 0xff);
9893
9894         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9895
9896         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9897              HOSTCC_MODE_NOW);
9898
9899         udelay(10);
9900
9901         rx_start_idx = tp->hw_status->idx[0].rx_producer;
9902
9903         num_pkts = 0;
9904
9905         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9906
9907         tp->tx_prod++;
9908         num_pkts++;
9909
9910         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9911                      tp->tx_prod);
9912         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9913
9914         udelay(10);
9915
9916         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
9917         for (i = 0; i < 25; i++) {
9918                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9919                        HOSTCC_MODE_NOW);
9920
9921                 udelay(10);
9922
9923                 tx_idx = tp->hw_status->idx[0].tx_consumer;
9924                 rx_idx = tp->hw_status->idx[0].rx_producer;
9925                 if ((tx_idx == tp->tx_prod) &&
9926                     (rx_idx == (rx_start_idx + num_pkts)))
9927                         break;
9928         }
9929
9930         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9931         dev_kfree_skb(skb);
9932
9933         if (tx_idx != tp->tx_prod)
9934                 goto out;
9935
9936         if (rx_idx != rx_start_idx + num_pkts)
9937                 goto out;
9938
9939         desc = &tp->rx_rcb[rx_start_idx];
9940         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9941         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9942         if (opaque_key != RXD_OPAQUE_RING_STD)
9943                 goto out;
9944
9945         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9946             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9947                 goto out;
9948
9949         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9950         if (rx_len != tx_len)
9951                 goto out;
9952
9953         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
9954
9955         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
9956         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9957
9958         for (i = 14; i < tx_len; i++) {
9959                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9960                         goto out;
9961         }
9962         err = 0;
9963
9964         /* tg3_free_rings will unmap and free the rx_skb */
9965 out:
9966         return err;
9967 }
9968
9969 #define TG3_MAC_LOOPBACK_FAILED         1
9970 #define TG3_PHY_LOOPBACK_FAILED         2
9971 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9972                                          TG3_PHY_LOOPBACK_FAILED)
9973
9974 static int tg3_test_loopback(struct tg3 *tp)
9975 {
9976         int err = 0;
9977         u32 cpmuctrl = 0;
9978
9979         if (!netif_running(tp->dev))
9980                 return TG3_LOOPBACK_FAILED;
9981
9982         err = tg3_reset_hw(tp, 1);
9983         if (err)
9984                 return TG3_LOOPBACK_FAILED;
9985
9986         /* Turn off gphy autopowerdown. */
9987         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9988                 tg3_phy_toggle_apd(tp, false);
9989
9990         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9991                 int i;
9992                 u32 status;
9993
9994                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9995
9996                 /* Wait for up to 40 microseconds to acquire lock. */
9997                 for (i = 0; i < 4; i++) {
9998                         status = tr32(TG3_CPMU_MUTEX_GNT);
9999                         if (status == CPMU_MUTEX_GNT_DRIVER)
10000                                 break;
10001                         udelay(10);
10002                 }
10003
10004                 if (status != CPMU_MUTEX_GNT_DRIVER)
10005                         return TG3_LOOPBACK_FAILED;
10006
10007                 /* Turn off link-based power management. */
10008                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10009                 tw32(TG3_CPMU_CTRL,
10010                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10011                                   CPMU_CTRL_LINK_AWARE_MODE));
10012         }
10013
10014         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10015                 err |= TG3_MAC_LOOPBACK_FAILED;
10016
10017         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10018                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10019
10020                 /* Release the mutex */
10021                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10022         }
10023
10024         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10025             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10026                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10027                         err |= TG3_PHY_LOOPBACK_FAILED;
10028         }
10029
10030         /* Re-enable gphy autopowerdown. */
10031         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10032                 tg3_phy_toggle_apd(tp, true);
10033
10034         return err;
10035 }
10036
10037 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10038                           u64 *data)
10039 {
10040         struct tg3 *tp = netdev_priv(dev);
10041
10042         if (tp->link_config.phy_is_low_power)
10043                 tg3_set_power_state(tp, PCI_D0);
10044
10045         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10046
10047         if (tg3_test_nvram(tp) != 0) {
10048                 etest->flags |= ETH_TEST_FL_FAILED;
10049                 data[0] = 1;
10050         }
10051         if (tg3_test_link(tp) != 0) {
10052                 etest->flags |= ETH_TEST_FL_FAILED;
10053                 data[1] = 1;
10054         }
10055         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10056                 int err, err2 = 0, irq_sync = 0;
10057
10058                 if (netif_running(dev)) {
10059                         tg3_phy_stop(tp);
10060                         tg3_netif_stop(tp);
10061                         irq_sync = 1;
10062                 }
10063
10064                 tg3_full_lock(tp, irq_sync);
10065
10066                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10067                 err = tg3_nvram_lock(tp);
10068                 tg3_halt_cpu(tp, RX_CPU_BASE);
10069                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10070                         tg3_halt_cpu(tp, TX_CPU_BASE);
10071                 if (!err)
10072                         tg3_nvram_unlock(tp);
10073
10074                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10075                         tg3_phy_reset(tp);
10076
10077                 if (tg3_test_registers(tp) != 0) {
10078                         etest->flags |= ETH_TEST_FL_FAILED;
10079                         data[2] = 1;
10080                 }
10081                 if (tg3_test_memory(tp) != 0) {
10082                         etest->flags |= ETH_TEST_FL_FAILED;
10083                         data[3] = 1;
10084                 }
10085                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10086                         etest->flags |= ETH_TEST_FL_FAILED;
10087
10088                 tg3_full_unlock(tp);
10089
10090                 if (tg3_test_interrupt(tp) != 0) {
10091                         etest->flags |= ETH_TEST_FL_FAILED;
10092                         data[5] = 1;
10093                 }
10094
10095                 tg3_full_lock(tp, 0);
10096
10097                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10098                 if (netif_running(dev)) {
10099                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10100                         err2 = tg3_restart_hw(tp, 1);
10101                         if (!err2)
10102                                 tg3_netif_start(tp);
10103                 }
10104
10105                 tg3_full_unlock(tp);
10106
10107                 if (irq_sync && !err2)
10108                         tg3_phy_start(tp);
10109         }
10110         if (tp->link_config.phy_is_low_power)
10111                 tg3_set_power_state(tp, PCI_D3hot);
10112
10113 }
10114
10115 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10116 {
10117         struct mii_ioctl_data *data = if_mii(ifr);
10118         struct tg3 *tp = netdev_priv(dev);
10119         int err;
10120
10121         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10122                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10123                         return -EAGAIN;
10124                 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10125         }
10126
10127         switch(cmd) {
10128         case SIOCGMIIPHY:
10129                 data->phy_id = PHY_ADDR;
10130
10131                 /* fallthru */
10132         case SIOCGMIIREG: {
10133                 u32 mii_regval;
10134
10135                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10136                         break;                  /* We have no PHY */
10137
10138                 if (tp->link_config.phy_is_low_power)
10139                         return -EAGAIN;
10140
10141                 spin_lock_bh(&tp->lock);
10142                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10143                 spin_unlock_bh(&tp->lock);
10144
10145                 data->val_out = mii_regval;
10146
10147                 return err;
10148         }
10149
10150         case SIOCSMIIREG:
10151                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10152                         break;                  /* We have no PHY */
10153
10154                 if (!capable(CAP_NET_ADMIN))
10155                         return -EPERM;
10156
10157                 if (tp->link_config.phy_is_low_power)
10158                         return -EAGAIN;
10159
10160                 spin_lock_bh(&tp->lock);
10161                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10162                 spin_unlock_bh(&tp->lock);
10163
10164                 return err;
10165
10166         default:
10167                 /* do nothing */
10168                 break;
10169         }
10170         return -EOPNOTSUPP;
10171 }
10172
10173 #if TG3_VLAN_TAG_USED
10174 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10175 {
10176         struct tg3 *tp = netdev_priv(dev);
10177
10178         if (!netif_running(dev)) {
10179                 tp->vlgrp = grp;
10180                 return;
10181         }
10182
10183         tg3_netif_stop(tp);
10184
10185         tg3_full_lock(tp, 0);
10186
10187         tp->vlgrp = grp;
10188
10189         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10190         __tg3_set_rx_mode(dev);
10191
10192         tg3_netif_start(tp);
10193
10194         tg3_full_unlock(tp);
10195 }
10196 #endif
10197
10198 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10199 {
10200         struct tg3 *tp = netdev_priv(dev);
10201
10202         memcpy(ec, &tp->coal, sizeof(*ec));
10203         return 0;
10204 }
10205
10206 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10207 {
10208         struct tg3 *tp = netdev_priv(dev);
10209         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10210         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10211
10212         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10213                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10214                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10215                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10216                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10217         }
10218
10219         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10220             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10221             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10222             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10223             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10224             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10225             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10226             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10227             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10228             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10229                 return -EINVAL;
10230
10231         /* No rx interrupts will be generated if both are zero */
10232         if ((ec->rx_coalesce_usecs == 0) &&
10233             (ec->rx_max_coalesced_frames == 0))
10234                 return -EINVAL;
10235
10236         /* No tx interrupts will be generated if both are zero */
10237         if ((ec->tx_coalesce_usecs == 0) &&
10238             (ec->tx_max_coalesced_frames == 0))
10239                 return -EINVAL;
10240
10241         /* Only copy relevant parameters, ignore all others. */
10242         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10243         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10244         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10245         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10246         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10247         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10248         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10249         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10250         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10251
10252         if (netif_running(dev)) {
10253                 tg3_full_lock(tp, 0);
10254                 __tg3_set_coalesce(tp, &tp->coal);
10255                 tg3_full_unlock(tp);
10256         }
10257         return 0;
10258 }
10259
10260 static const struct ethtool_ops tg3_ethtool_ops = {
10261         .get_settings           = tg3_get_settings,
10262         .set_settings           = tg3_set_settings,
10263         .get_drvinfo            = tg3_get_drvinfo,
10264         .get_regs_len           = tg3_get_regs_len,
10265         .get_regs               = tg3_get_regs,
10266         .get_wol                = tg3_get_wol,
10267         .set_wol                = tg3_set_wol,
10268         .get_msglevel           = tg3_get_msglevel,
10269         .set_msglevel           = tg3_set_msglevel,
10270         .nway_reset             = tg3_nway_reset,
10271         .get_link               = ethtool_op_get_link,
10272         .get_eeprom_len         = tg3_get_eeprom_len,
10273         .get_eeprom             = tg3_get_eeprom,
10274         .set_eeprom             = tg3_set_eeprom,
10275         .get_ringparam          = tg3_get_ringparam,
10276         .set_ringparam          = tg3_set_ringparam,
10277         .get_pauseparam         = tg3_get_pauseparam,
10278         .set_pauseparam         = tg3_set_pauseparam,
10279         .get_rx_csum            = tg3_get_rx_csum,
10280         .set_rx_csum            = tg3_set_rx_csum,
10281         .set_tx_csum            = tg3_set_tx_csum,
10282         .set_sg                 = ethtool_op_set_sg,
10283         .set_tso                = tg3_set_tso,
10284         .self_test              = tg3_self_test,
10285         .get_strings            = tg3_get_strings,
10286         .phys_id                = tg3_phys_id,
10287         .get_ethtool_stats      = tg3_get_ethtool_stats,
10288         .get_coalesce           = tg3_get_coalesce,
10289         .set_coalesce           = tg3_set_coalesce,
10290         .get_sset_count         = tg3_get_sset_count,
10291 };
10292
10293 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10294 {
10295         u32 cursize, val, magic;
10296
10297         tp->nvram_size = EEPROM_CHIP_SIZE;
10298
10299         if (tg3_nvram_read(tp, 0, &magic) != 0)
10300                 return;
10301
10302         if ((magic != TG3_EEPROM_MAGIC) &&
10303             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10304             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10305                 return;
10306
10307         /*
10308          * Size the chip by reading offsets at increasing powers of two.
10309          * When we encounter our validation signature, we know the addressing
10310          * has wrapped around, and thus have our chip size.
10311          */
10312         cursize = 0x10;
10313
10314         while (cursize < tp->nvram_size) {
10315                 if (tg3_nvram_read(tp, cursize, &val) != 0)
10316                         return;
10317
10318                 if (val == magic)
10319                         break;
10320
10321                 cursize <<= 1;
10322         }
10323
10324         tp->nvram_size = cursize;
10325 }
10326
10327 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10328 {
10329         u32 val;
10330
10331         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10332             tg3_nvram_read(tp, 0, &val) != 0)
10333                 return;
10334
10335         /* Selfboot format */
10336         if (val != TG3_EEPROM_MAGIC) {
10337                 tg3_get_eeprom_size(tp);
10338                 return;
10339         }
10340
10341         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10342                 if (val != 0) {
10343                         /* This is confusing.  We want to operate on the
10344                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
10345                          * call will read from NVRAM and byteswap the data
10346                          * according to the byteswapping settings for all
10347                          * other register accesses.  This ensures the data we
10348                          * want will always reside in the lower 16-bits.
10349                          * However, the data in NVRAM is in LE format, which
10350                          * means the data from the NVRAM read will always be
10351                          * opposite the endianness of the CPU.  The 16-bit
10352                          * byteswap then brings the data to CPU endianness.
10353                          */
10354                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10355                         return;
10356                 }
10357         }
10358         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10359 }
10360
10361 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10362 {
10363         u32 nvcfg1;
10364
10365         nvcfg1 = tr32(NVRAM_CFG1);
10366         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10367                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10368         } else {
10369                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10370                 tw32(NVRAM_CFG1, nvcfg1);
10371         }
10372
10373         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10374             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10375                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10376                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10377                         tp->nvram_jedecnum = JEDEC_ATMEL;
10378                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10379                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10380                         break;
10381                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10382                         tp->nvram_jedecnum = JEDEC_ATMEL;
10383                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10384                         break;
10385                 case FLASH_VENDOR_ATMEL_EEPROM:
10386                         tp->nvram_jedecnum = JEDEC_ATMEL;
10387                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10388                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10389                         break;
10390                 case FLASH_VENDOR_ST:
10391                         tp->nvram_jedecnum = JEDEC_ST;
10392                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10393                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10394                         break;
10395                 case FLASH_VENDOR_SAIFUN:
10396                         tp->nvram_jedecnum = JEDEC_SAIFUN;
10397                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10398                         break;
10399                 case FLASH_VENDOR_SST_SMALL:
10400                 case FLASH_VENDOR_SST_LARGE:
10401                         tp->nvram_jedecnum = JEDEC_SST;
10402                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10403                         break;
10404                 }
10405         } else {
10406                 tp->nvram_jedecnum = JEDEC_ATMEL;
10407                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10408                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10409         }
10410 }
10411
10412 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10413 {
10414         u32 nvcfg1;
10415
10416         nvcfg1 = tr32(NVRAM_CFG1);
10417
10418         /* NVRAM protection for TPM */
10419         if (nvcfg1 & (1 << 27))
10420                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10421
10422         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10423         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10424         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10425                 tp->nvram_jedecnum = JEDEC_ATMEL;
10426                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10427                 break;
10428         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10429                 tp->nvram_jedecnum = JEDEC_ATMEL;
10430                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10431                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10432                 break;
10433         case FLASH_5752VENDOR_ST_M45PE10:
10434         case FLASH_5752VENDOR_ST_M45PE20:
10435         case FLASH_5752VENDOR_ST_M45PE40:
10436                 tp->nvram_jedecnum = JEDEC_ST;
10437                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10438                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10439                 break;
10440         }
10441
10442         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10443                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10444                 case FLASH_5752PAGE_SIZE_256:
10445                         tp->nvram_pagesize = 256;
10446                         break;
10447                 case FLASH_5752PAGE_SIZE_512:
10448                         tp->nvram_pagesize = 512;
10449                         break;
10450                 case FLASH_5752PAGE_SIZE_1K:
10451                         tp->nvram_pagesize = 1024;
10452                         break;
10453                 case FLASH_5752PAGE_SIZE_2K:
10454                         tp->nvram_pagesize = 2048;
10455                         break;
10456                 case FLASH_5752PAGE_SIZE_4K:
10457                         tp->nvram_pagesize = 4096;
10458                         break;
10459                 case FLASH_5752PAGE_SIZE_264:
10460                         tp->nvram_pagesize = 264;
10461                         break;
10462                 }
10463         } else {
10464                 /* For eeprom, set pagesize to maximum eeprom size */
10465                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10466
10467                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10468                 tw32(NVRAM_CFG1, nvcfg1);
10469         }
10470 }
10471
10472 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10473 {
10474         u32 nvcfg1, protect = 0;
10475
10476         nvcfg1 = tr32(NVRAM_CFG1);
10477
10478         /* NVRAM protection for TPM */
10479         if (nvcfg1 & (1 << 27)) {
10480                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10481                 protect = 1;
10482         }
10483
10484         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10485         switch (nvcfg1) {
10486         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10487         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10488         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10489         case FLASH_5755VENDOR_ATMEL_FLASH_5:
10490                 tp->nvram_jedecnum = JEDEC_ATMEL;
10491                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10492                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10493                 tp->nvram_pagesize = 264;
10494                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10495                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10496                         tp->nvram_size = (protect ? 0x3e200 :
10497                                           TG3_NVRAM_SIZE_512KB);
10498                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10499                         tp->nvram_size = (protect ? 0x1f200 :
10500                                           TG3_NVRAM_SIZE_256KB);
10501                 else
10502                         tp->nvram_size = (protect ? 0x1f200 :
10503                                           TG3_NVRAM_SIZE_128KB);
10504                 break;
10505         case FLASH_5752VENDOR_ST_M45PE10:
10506         case FLASH_5752VENDOR_ST_M45PE20:
10507         case FLASH_5752VENDOR_ST_M45PE40:
10508                 tp->nvram_jedecnum = JEDEC_ST;
10509                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10510                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10511                 tp->nvram_pagesize = 256;
10512                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10513                         tp->nvram_size = (protect ?
10514                                           TG3_NVRAM_SIZE_64KB :
10515                                           TG3_NVRAM_SIZE_128KB);
10516                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10517                         tp->nvram_size = (protect ?
10518                                           TG3_NVRAM_SIZE_64KB :
10519                                           TG3_NVRAM_SIZE_256KB);
10520                 else
10521                         tp->nvram_size = (protect ?
10522                                           TG3_NVRAM_SIZE_128KB :
10523                                           TG3_NVRAM_SIZE_512KB);
10524                 break;
10525         }
10526 }
10527
10528 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10529 {
10530         u32 nvcfg1;
10531
10532         nvcfg1 = tr32(NVRAM_CFG1);
10533
10534         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10535         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10536         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10537         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10538         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10539                 tp->nvram_jedecnum = JEDEC_ATMEL;
10540                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10541                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10542
10543                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10544                 tw32(NVRAM_CFG1, nvcfg1);
10545                 break;
10546         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10547         case FLASH_5755VENDOR_ATMEL_FLASH_1:
10548         case FLASH_5755VENDOR_ATMEL_FLASH_2:
10549         case FLASH_5755VENDOR_ATMEL_FLASH_3:
10550                 tp->nvram_jedecnum = JEDEC_ATMEL;
10551                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10552                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10553                 tp->nvram_pagesize = 264;
10554                 break;
10555         case FLASH_5752VENDOR_ST_M45PE10:
10556         case FLASH_5752VENDOR_ST_M45PE20:
10557         case FLASH_5752VENDOR_ST_M45PE40:
10558                 tp->nvram_jedecnum = JEDEC_ST;
10559                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10560                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10561                 tp->nvram_pagesize = 256;
10562                 break;
10563         }
10564 }
10565
10566 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10567 {
10568         u32 nvcfg1, protect = 0;
10569
10570         nvcfg1 = tr32(NVRAM_CFG1);
10571
10572         /* NVRAM protection for TPM */
10573         if (nvcfg1 & (1 << 27)) {
10574                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10575                 protect = 1;
10576         }
10577
10578         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10579         switch (nvcfg1) {
10580         case FLASH_5761VENDOR_ATMEL_ADB021D:
10581         case FLASH_5761VENDOR_ATMEL_ADB041D:
10582         case FLASH_5761VENDOR_ATMEL_ADB081D:
10583         case FLASH_5761VENDOR_ATMEL_ADB161D:
10584         case FLASH_5761VENDOR_ATMEL_MDB021D:
10585         case FLASH_5761VENDOR_ATMEL_MDB041D:
10586         case FLASH_5761VENDOR_ATMEL_MDB081D:
10587         case FLASH_5761VENDOR_ATMEL_MDB161D:
10588                 tp->nvram_jedecnum = JEDEC_ATMEL;
10589                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10590                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10591                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10592                 tp->nvram_pagesize = 256;
10593                 break;
10594         case FLASH_5761VENDOR_ST_A_M45PE20:
10595         case FLASH_5761VENDOR_ST_A_M45PE40:
10596         case FLASH_5761VENDOR_ST_A_M45PE80:
10597         case FLASH_5761VENDOR_ST_A_M45PE16:
10598         case FLASH_5761VENDOR_ST_M_M45PE20:
10599         case FLASH_5761VENDOR_ST_M_M45PE40:
10600         case FLASH_5761VENDOR_ST_M_M45PE80:
10601         case FLASH_5761VENDOR_ST_M_M45PE16:
10602                 tp->nvram_jedecnum = JEDEC_ST;
10603                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10604                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10605                 tp->nvram_pagesize = 256;
10606                 break;
10607         }
10608
10609         if (protect) {
10610                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10611         } else {
10612                 switch (nvcfg1) {
10613                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10614                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10615                 case FLASH_5761VENDOR_ST_A_M45PE16:
10616                 case FLASH_5761VENDOR_ST_M_M45PE16:
10617                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10618                         break;
10619                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10620                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10621                 case FLASH_5761VENDOR_ST_A_M45PE80:
10622                 case FLASH_5761VENDOR_ST_M_M45PE80:
10623                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10624                         break;
10625                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10626                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10627                 case FLASH_5761VENDOR_ST_A_M45PE40:
10628                 case FLASH_5761VENDOR_ST_M_M45PE40:
10629                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10630                         break;
10631                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10632                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10633                 case FLASH_5761VENDOR_ST_A_M45PE20:
10634                 case FLASH_5761VENDOR_ST_M_M45PE20:
10635                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10636                         break;
10637                 }
10638         }
10639 }
10640
10641 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10642 {
10643         tp->nvram_jedecnum = JEDEC_ATMEL;
10644         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10645         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10646 }
10647
10648 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10649 {
10650         u32 nvcfg1;
10651
10652         nvcfg1 = tr32(NVRAM_CFG1);
10653
10654         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10655         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10656         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10657                 tp->nvram_jedecnum = JEDEC_ATMEL;
10658                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10659                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10660
10661                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10662                 tw32(NVRAM_CFG1, nvcfg1);
10663                 return;
10664         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10665         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10666         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10667         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10668         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10669         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10670         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10671                 tp->nvram_jedecnum = JEDEC_ATMEL;
10672                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10673                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10674
10675                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10676                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10677                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10678                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10679                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10680                         break;
10681                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10682                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10683                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10684                         break;
10685                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10686                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10687                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10688                         break;
10689                 }
10690                 break;
10691         case FLASH_5752VENDOR_ST_M45PE10:
10692         case FLASH_5752VENDOR_ST_M45PE20:
10693         case FLASH_5752VENDOR_ST_M45PE40:
10694                 tp->nvram_jedecnum = JEDEC_ST;
10695                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10696                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10697
10698                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10699                 case FLASH_5752VENDOR_ST_M45PE10:
10700                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10701                         break;
10702                 case FLASH_5752VENDOR_ST_M45PE20:
10703                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10704                         break;
10705                 case FLASH_5752VENDOR_ST_M45PE40:
10706                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10707                         break;
10708                 }
10709                 break;
10710         default:
10711                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10712                 return;
10713         }
10714
10715         switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10716         case FLASH_5752PAGE_SIZE_256:
10717                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10718                 tp->nvram_pagesize = 256;
10719                 break;
10720         case FLASH_5752PAGE_SIZE_512:
10721                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10722                 tp->nvram_pagesize = 512;
10723                 break;
10724         case FLASH_5752PAGE_SIZE_1K:
10725                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10726                 tp->nvram_pagesize = 1024;
10727                 break;
10728         case FLASH_5752PAGE_SIZE_2K:
10729                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10730                 tp->nvram_pagesize = 2048;
10731                 break;
10732         case FLASH_5752PAGE_SIZE_4K:
10733                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10734                 tp->nvram_pagesize = 4096;
10735                 break;
10736         case FLASH_5752PAGE_SIZE_264:
10737                 tp->nvram_pagesize = 264;
10738                 break;
10739         case FLASH_5752PAGE_SIZE_528:
10740                 tp->nvram_pagesize = 528;
10741                 break;
10742         }
10743 }
10744
10745 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10746 static void __devinit tg3_nvram_init(struct tg3 *tp)
10747 {
10748         tw32_f(GRC_EEPROM_ADDR,
10749              (EEPROM_ADDR_FSM_RESET |
10750               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10751                EEPROM_ADDR_CLKPERD_SHIFT)));
10752
10753         msleep(1);
10754
10755         /* Enable seeprom accesses. */
10756         tw32_f(GRC_LOCAL_CTRL,
10757              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10758         udelay(100);
10759
10760         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10761             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10762                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10763
10764                 if (tg3_nvram_lock(tp)) {
10765                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10766                                "tg3_nvram_init failed.\n", tp->dev->name);
10767                         return;
10768                 }
10769                 tg3_enable_nvram_access(tp);
10770
10771                 tp->nvram_size = 0;
10772
10773                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10774                         tg3_get_5752_nvram_info(tp);
10775                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10776                         tg3_get_5755_nvram_info(tp);
10777                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10778                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10779                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10780                         tg3_get_5787_nvram_info(tp);
10781                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10782                         tg3_get_5761_nvram_info(tp);
10783                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10784                         tg3_get_5906_nvram_info(tp);
10785                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10786                         tg3_get_57780_nvram_info(tp);
10787                 else
10788                         tg3_get_nvram_info(tp);
10789
10790                 if (tp->nvram_size == 0)
10791                         tg3_get_nvram_size(tp);
10792
10793                 tg3_disable_nvram_access(tp);
10794                 tg3_nvram_unlock(tp);
10795
10796         } else {
10797                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10798
10799                 tg3_get_eeprom_size(tp);
10800         }
10801 }
10802
10803 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10804                                     u32 offset, u32 len, u8 *buf)
10805 {
10806         int i, j, rc = 0;
10807         u32 val;
10808
10809         for (i = 0; i < len; i += 4) {
10810                 u32 addr;
10811                 __be32 data;
10812
10813                 addr = offset + i;
10814
10815                 memcpy(&data, buf + i, 4);
10816
10817                 /*
10818                  * The SEEPROM interface expects the data to always be opposite
10819                  * the native endian format.  We accomplish this by reversing
10820                  * all the operations that would have been performed on the
10821                  * data from a call to tg3_nvram_read_be32().
10822                  */
10823                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10824
10825                 val = tr32(GRC_EEPROM_ADDR);
10826                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10827
10828                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10829                         EEPROM_ADDR_READ);
10830                 tw32(GRC_EEPROM_ADDR, val |
10831                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10832                         (addr & EEPROM_ADDR_ADDR_MASK) |
10833                         EEPROM_ADDR_START |
10834                         EEPROM_ADDR_WRITE);
10835
10836                 for (j = 0; j < 1000; j++) {
10837                         val = tr32(GRC_EEPROM_ADDR);
10838
10839                         if (val & EEPROM_ADDR_COMPLETE)
10840                                 break;
10841                         msleep(1);
10842                 }
10843                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10844                         rc = -EBUSY;
10845                         break;
10846                 }
10847         }
10848
10849         return rc;
10850 }
10851
10852 /* offset and length are dword aligned */
10853 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10854                 u8 *buf)
10855 {
10856         int ret = 0;
10857         u32 pagesize = tp->nvram_pagesize;
10858         u32 pagemask = pagesize - 1;
10859         u32 nvram_cmd;
10860         u8 *tmp;
10861
10862         tmp = kmalloc(pagesize, GFP_KERNEL);
10863         if (tmp == NULL)
10864                 return -ENOMEM;
10865
10866         while (len) {
10867                 int j;
10868                 u32 phy_addr, page_off, size;
10869
10870                 phy_addr = offset & ~pagemask;
10871
10872                 for (j = 0; j < pagesize; j += 4) {
10873                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
10874                                                   (__be32 *) (tmp + j));
10875                         if (ret)
10876                                 break;
10877                 }
10878                 if (ret)
10879                         break;
10880
10881                 page_off = offset & pagemask;
10882                 size = pagesize;
10883                 if (len < size)
10884                         size = len;
10885
10886                 len -= size;
10887
10888                 memcpy(tmp + page_off, buf, size);
10889
10890                 offset = offset + (pagesize - page_off);
10891
10892                 tg3_enable_nvram_access(tp);
10893
10894                 /*
10895                  * Before we can erase the flash page, we need
10896                  * to issue a special "write enable" command.
10897                  */
10898                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10899
10900                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10901                         break;
10902
10903                 /* Erase the target page */
10904                 tw32(NVRAM_ADDR, phy_addr);
10905
10906                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10907                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10908
10909                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10910                         break;
10911
10912                 /* Issue another write enable to start the write. */
10913                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10914
10915                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10916                         break;
10917
10918                 for (j = 0; j < pagesize; j += 4) {
10919                         __be32 data;
10920
10921                         data = *((__be32 *) (tmp + j));
10922
10923                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
10924
10925                         tw32(NVRAM_ADDR, phy_addr + j);
10926
10927                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10928                                 NVRAM_CMD_WR;
10929
10930                         if (j == 0)
10931                                 nvram_cmd |= NVRAM_CMD_FIRST;
10932                         else if (j == (pagesize - 4))
10933                                 nvram_cmd |= NVRAM_CMD_LAST;
10934
10935                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10936                                 break;
10937                 }
10938                 if (ret)
10939                         break;
10940         }
10941
10942         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10943         tg3_nvram_exec_cmd(tp, nvram_cmd);
10944
10945         kfree(tmp);
10946
10947         return ret;
10948 }
10949
10950 /* offset and length are dword aligned */
10951 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10952                 u8 *buf)
10953 {
10954         int i, ret = 0;
10955
10956         for (i = 0; i < len; i += 4, offset += 4) {
10957                 u32 page_off, phy_addr, nvram_cmd;
10958                 __be32 data;
10959
10960                 memcpy(&data, buf + i, 4);
10961                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10962
10963                 page_off = offset % tp->nvram_pagesize;
10964
10965                 phy_addr = tg3_nvram_phys_addr(tp, offset);
10966
10967                 tw32(NVRAM_ADDR, phy_addr);
10968
10969                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10970
10971                 if ((page_off == 0) || (i == 0))
10972                         nvram_cmd |= NVRAM_CMD_FIRST;
10973                 if (page_off == (tp->nvram_pagesize - 4))
10974                         nvram_cmd |= NVRAM_CMD_LAST;
10975
10976                 if (i == (len - 4))
10977                         nvram_cmd |= NVRAM_CMD_LAST;
10978
10979                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10980                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10981                     (tp->nvram_jedecnum == JEDEC_ST) &&
10982                     (nvram_cmd & NVRAM_CMD_FIRST)) {
10983
10984                         if ((ret = tg3_nvram_exec_cmd(tp,
10985                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10986                                 NVRAM_CMD_DONE)))
10987
10988                                 break;
10989                 }
10990                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10991                         /* We always do complete word writes to eeprom. */
10992                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10993                 }
10994
10995                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10996                         break;
10997         }
10998         return ret;
10999 }
11000
11001 /* offset and length are dword aligned */
11002 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11003 {
11004         int ret;
11005
11006         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11007                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11008                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11009                 udelay(40);
11010         }
11011
11012         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11013                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11014         }
11015         else {
11016                 u32 grc_mode;
11017
11018                 ret = tg3_nvram_lock(tp);
11019                 if (ret)
11020                         return ret;
11021
11022                 tg3_enable_nvram_access(tp);
11023                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11024                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11025                         tw32(NVRAM_WRITE1, 0x406);
11026
11027                 grc_mode = tr32(GRC_MODE);
11028                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11029
11030                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11031                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11032
11033                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11034                                 buf);
11035                 }
11036                 else {
11037                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11038                                 buf);
11039                 }
11040
11041                 grc_mode = tr32(GRC_MODE);
11042                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11043
11044                 tg3_disable_nvram_access(tp);
11045                 tg3_nvram_unlock(tp);
11046         }
11047
11048         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11049                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11050                 udelay(40);
11051         }
11052
11053         return ret;
11054 }
11055
11056 struct subsys_tbl_ent {
11057         u16 subsys_vendor, subsys_devid;
11058         u32 phy_id;
11059 };
11060
11061 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11062         /* Broadcom boards. */
11063         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11064         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11065         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11066         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11067         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11068         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11069         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11070         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11071         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11072         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11073         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11074
11075         /* 3com boards. */
11076         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11077         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11078         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11079         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11080         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11081
11082         /* DELL boards. */
11083         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11084         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11085         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11086         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11087
11088         /* Compaq boards. */
11089         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11090         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11091         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11092         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11093         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11094
11095         /* IBM boards. */
11096         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11097 };
11098
11099 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11100 {
11101         int i;
11102
11103         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11104                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11105                      tp->pdev->subsystem_vendor) &&
11106                     (subsys_id_to_phy_id[i].subsys_devid ==
11107                      tp->pdev->subsystem_device))
11108                         return &subsys_id_to_phy_id[i];
11109         }
11110         return NULL;
11111 }
11112
11113 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11114 {
11115         u32 val;
11116         u16 pmcsr;
11117
11118         /* On some early chips the SRAM cannot be accessed in D3hot state,
11119          * so need make sure we're in D0.
11120          */
11121         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11122         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11123         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11124         msleep(1);
11125
11126         /* Make sure register accesses (indirect or otherwise)
11127          * will function correctly.
11128          */
11129         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11130                                tp->misc_host_ctrl);
11131
11132         /* The memory arbiter has to be enabled in order for SRAM accesses
11133          * to succeed.  Normally on powerup the tg3 chip firmware will make
11134          * sure it is enabled, but other entities such as system netboot
11135          * code might disable it.
11136          */
11137         val = tr32(MEMARB_MODE);
11138         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11139
11140         tp->phy_id = PHY_ID_INVALID;
11141         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11142
11143         /* Assume an onboard device and WOL capable by default.  */
11144         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11145
11146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11147                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11148                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11149                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11150                 }
11151                 val = tr32(VCPU_CFGSHDW);
11152                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11153                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11154                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11155                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11156                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11157                 goto done;
11158         }
11159
11160         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11161         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11162                 u32 nic_cfg, led_cfg;
11163                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11164                 int eeprom_phy_serdes = 0;
11165
11166                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11167                 tp->nic_sram_data_cfg = nic_cfg;
11168
11169                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11170                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11171                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11172                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11173                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11174                     (ver > 0) && (ver < 0x100))
11175                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11176
11177                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11178                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11179
11180                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11181                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11182                         eeprom_phy_serdes = 1;
11183
11184                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11185                 if (nic_phy_id != 0) {
11186                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11187                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11188
11189                         eeprom_phy_id  = (id1 >> 16) << 10;
11190                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11191                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11192                 } else
11193                         eeprom_phy_id = 0;
11194
11195                 tp->phy_id = eeprom_phy_id;
11196                 if (eeprom_phy_serdes) {
11197                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11198                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11199                         else
11200                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11201                 }
11202
11203                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11204                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11205                                     SHASTA_EXT_LED_MODE_MASK);
11206                 else
11207                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11208
11209                 switch (led_cfg) {
11210                 default:
11211                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11212                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11213                         break;
11214
11215                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11216                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11217                         break;
11218
11219                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11220                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11221
11222                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11223                          * read on some older 5700/5701 bootcode.
11224                          */
11225                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11226                             ASIC_REV_5700 ||
11227                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11228                             ASIC_REV_5701)
11229                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11230
11231                         break;
11232
11233                 case SHASTA_EXT_LED_SHARED:
11234                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11235                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11236                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11237                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11238                                                  LED_CTRL_MODE_PHY_2);
11239                         break;
11240
11241                 case SHASTA_EXT_LED_MAC:
11242                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11243                         break;
11244
11245                 case SHASTA_EXT_LED_COMBO:
11246                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11247                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11248                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11249                                                  LED_CTRL_MODE_PHY_2);
11250                         break;
11251
11252                 }
11253
11254                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11255                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11256                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11257                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11258
11259                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11260                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11261
11262                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11263                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11264                         if ((tp->pdev->subsystem_vendor ==
11265                              PCI_VENDOR_ID_ARIMA) &&
11266                             (tp->pdev->subsystem_device == 0x205a ||
11267                              tp->pdev->subsystem_device == 0x2063))
11268                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11269                 } else {
11270                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11271                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11272                 }
11273
11274                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11275                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11276                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11277                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11278                 }
11279
11280                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11281                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11282                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11283
11284                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11285                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11286                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11287
11288                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11289                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11290                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11291
11292                 if (cfg2 & (1 << 17))
11293                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11294
11295                 /* serdes signal pre-emphasis in register 0x590 set by */
11296                 /* bootcode if bit 18 is set */
11297                 if (cfg2 & (1 << 18))
11298                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11299
11300                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11301                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11302                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11303                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11304
11305                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11306                         u32 cfg3;
11307
11308                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11309                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11310                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11311                 }
11312
11313                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11314                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11315                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11316                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11317                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11318                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11319         }
11320 done:
11321         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11322         device_set_wakeup_enable(&tp->pdev->dev,
11323                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11324 }
11325
11326 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11327 {
11328         int i;
11329         u32 val;
11330
11331         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11332         tw32(OTP_CTRL, cmd);
11333
11334         /* Wait for up to 1 ms for command to execute. */
11335         for (i = 0; i < 100; i++) {
11336                 val = tr32(OTP_STATUS);
11337                 if (val & OTP_STATUS_CMD_DONE)
11338                         break;
11339                 udelay(10);
11340         }
11341
11342         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11343 }
11344
11345 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11346  * configuration is a 32-bit value that straddles the alignment boundary.
11347  * We do two 32-bit reads and then shift and merge the results.
11348  */
11349 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11350 {
11351         u32 bhalf_otp, thalf_otp;
11352
11353         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11354
11355         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11356                 return 0;
11357
11358         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11359
11360         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11361                 return 0;
11362
11363         thalf_otp = tr32(OTP_READ_DATA);
11364
11365         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11366
11367         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11368                 return 0;
11369
11370         bhalf_otp = tr32(OTP_READ_DATA);
11371
11372         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11373 }
11374
11375 static int __devinit tg3_phy_probe(struct tg3 *tp)
11376 {
11377         u32 hw_phy_id_1, hw_phy_id_2;
11378         u32 hw_phy_id, hw_phy_id_masked;
11379         int err;
11380
11381         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11382                 return tg3_phy_init(tp);
11383
11384         /* Reading the PHY ID register can conflict with ASF
11385          * firmware access to the PHY hardware.
11386          */
11387         err = 0;
11388         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11389             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11390                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11391         } else {
11392                 /* Now read the physical PHY_ID from the chip and verify
11393                  * that it is sane.  If it doesn't look good, we fall back
11394                  * to either the hard-coded table based PHY_ID and failing
11395                  * that the value found in the eeprom area.
11396                  */
11397                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11398                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11399
11400                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11401                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11402                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11403
11404                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11405         }
11406
11407         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11408                 tp->phy_id = hw_phy_id;
11409                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11410                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11411                 else
11412                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11413         } else {
11414                 if (tp->phy_id != PHY_ID_INVALID) {
11415                         /* Do nothing, phy ID already set up in
11416                          * tg3_get_eeprom_hw_cfg().
11417                          */
11418                 } else {
11419                         struct subsys_tbl_ent *p;
11420
11421                         /* No eeprom signature?  Try the hardcoded
11422                          * subsys device table.
11423                          */
11424                         p = lookup_by_subsys(tp);
11425                         if (!p)
11426                                 return -ENODEV;
11427
11428                         tp->phy_id = p->phy_id;
11429                         if (!tp->phy_id ||
11430                             tp->phy_id == PHY_ID_BCM8002)
11431                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11432                 }
11433         }
11434
11435         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11436             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11437             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11438                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11439
11440                 tg3_readphy(tp, MII_BMSR, &bmsr);
11441                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11442                     (bmsr & BMSR_LSTATUS))
11443                         goto skip_phy_reset;
11444
11445                 err = tg3_phy_reset(tp);
11446                 if (err)
11447                         return err;
11448
11449                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11450                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11451                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11452                 tg3_ctrl = 0;
11453                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11454                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11455                                     MII_TG3_CTRL_ADV_1000_FULL);
11456                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11457                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11458                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11459                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11460                 }
11461
11462                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11463                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11464                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11465                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11466                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11467
11468                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11469                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11470
11471                         tg3_writephy(tp, MII_BMCR,
11472                                      BMCR_ANENABLE | BMCR_ANRESTART);
11473                 }
11474                 tg3_phy_set_wirespeed(tp);
11475
11476                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11477                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11478                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11479         }
11480
11481 skip_phy_reset:
11482         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11483                 err = tg3_init_5401phy_dsp(tp);
11484                 if (err)
11485                         return err;
11486         }
11487
11488         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11489                 err = tg3_init_5401phy_dsp(tp);
11490         }
11491
11492         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11493                 tp->link_config.advertising =
11494                         (ADVERTISED_1000baseT_Half |
11495                          ADVERTISED_1000baseT_Full |
11496                          ADVERTISED_Autoneg |
11497                          ADVERTISED_FIBRE);
11498         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11499                 tp->link_config.advertising &=
11500                         ~(ADVERTISED_1000baseT_Half |
11501                           ADVERTISED_1000baseT_Full);
11502
11503         return err;
11504 }
11505
11506 static void __devinit tg3_read_partno(struct tg3 *tp)
11507 {
11508         unsigned char vpd_data[256];   /* in little-endian format */
11509         unsigned int i;
11510         u32 magic;
11511
11512         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11513             tg3_nvram_read(tp, 0x0, &magic))
11514                 goto out_not_found;
11515
11516         if (magic == TG3_EEPROM_MAGIC) {
11517                 for (i = 0; i < 256; i += 4) {
11518                         u32 tmp;
11519
11520                         /* The data is in little-endian format in NVRAM.
11521                          * Use the big-endian read routines to preserve
11522                          * the byte order as it exists in NVRAM.
11523                          */
11524                         if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11525                                 goto out_not_found;
11526
11527                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11528                 }
11529         } else {
11530                 int vpd_cap;
11531
11532                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11533                 for (i = 0; i < 256; i += 4) {
11534                         u32 tmp, j = 0;
11535                         __le32 v;
11536                         u16 tmp16;
11537
11538                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11539                                               i);
11540                         while (j++ < 100) {
11541                                 pci_read_config_word(tp->pdev, vpd_cap +
11542                                                      PCI_VPD_ADDR, &tmp16);
11543                                 if (tmp16 & 0x8000)
11544                                         break;
11545                                 msleep(1);
11546                         }
11547                         if (!(tmp16 & 0x8000))
11548                                 goto out_not_found;
11549
11550                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11551                                               &tmp);
11552                         v = cpu_to_le32(tmp);
11553                         memcpy(&vpd_data[i], &v, sizeof(v));
11554                 }
11555         }
11556
11557         /* Now parse and find the part number. */
11558         for (i = 0; i < 254; ) {
11559                 unsigned char val = vpd_data[i];
11560                 unsigned int block_end;
11561
11562                 if (val == 0x82 || val == 0x91) {
11563                         i = (i + 3 +
11564                              (vpd_data[i + 1] +
11565                               (vpd_data[i + 2] << 8)));
11566                         continue;
11567                 }
11568
11569                 if (val != 0x90)
11570                         goto out_not_found;
11571
11572                 block_end = (i + 3 +
11573                              (vpd_data[i + 1] +
11574                               (vpd_data[i + 2] << 8)));
11575                 i += 3;
11576
11577                 if (block_end > 256)
11578                         goto out_not_found;
11579
11580                 while (i < (block_end - 2)) {
11581                         if (vpd_data[i + 0] == 'P' &&
11582                             vpd_data[i + 1] == 'N') {
11583                                 int partno_len = vpd_data[i + 2];
11584
11585                                 i += 3;
11586                                 if (partno_len > 24 || (partno_len + i) > 256)
11587                                         goto out_not_found;
11588
11589                                 memcpy(tp->board_part_number,
11590                                        &vpd_data[i], partno_len);
11591
11592                                 /* Success. */
11593                                 return;
11594                         }
11595                         i += 3 + vpd_data[i + 2];
11596                 }
11597
11598                 /* Part number not found. */
11599                 goto out_not_found;
11600         }
11601
11602 out_not_found:
11603         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11604                 strcpy(tp->board_part_number, "BCM95906");
11605         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11606                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11607                 strcpy(tp->board_part_number, "BCM57780");
11608         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11609                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11610                 strcpy(tp->board_part_number, "BCM57760");
11611         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11612                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11613                 strcpy(tp->board_part_number, "BCM57790");
11614         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11615                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
11616                 strcpy(tp->board_part_number, "BCM57788");
11617         else
11618                 strcpy(tp->board_part_number, "none");
11619 }
11620
11621 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11622 {
11623         u32 val;
11624
11625         if (tg3_nvram_read(tp, offset, &val) ||
11626             (val & 0xfc000000) != 0x0c000000 ||
11627             tg3_nvram_read(tp, offset + 4, &val) ||
11628             val != 0)
11629                 return 0;
11630
11631         return 1;
11632 }
11633
11634 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11635 {
11636         u32 val, offset, start, ver_offset;
11637         int i;
11638         bool newver = false;
11639
11640         if (tg3_nvram_read(tp, 0xc, &offset) ||
11641             tg3_nvram_read(tp, 0x4, &start))
11642                 return;
11643
11644         offset = tg3_nvram_logical_addr(tp, offset);
11645
11646         if (tg3_nvram_read(tp, offset, &val))
11647                 return;
11648
11649         if ((val & 0xfc000000) == 0x0c000000) {
11650                 if (tg3_nvram_read(tp, offset + 4, &val))
11651                         return;
11652
11653                 if (val == 0)
11654                         newver = true;
11655         }
11656
11657         if (newver) {
11658                 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11659                         return;
11660
11661                 offset = offset + ver_offset - start;
11662                 for (i = 0; i < 16; i += 4) {
11663                         __be32 v;
11664                         if (tg3_nvram_read_be32(tp, offset + i, &v))
11665                                 return;
11666
11667                         memcpy(tp->fw_ver + i, &v, sizeof(v));
11668                 }
11669         } else {
11670                 u32 major, minor;
11671
11672                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11673                         return;
11674
11675                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11676                         TG3_NVM_BCVER_MAJSFT;
11677                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11678                 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11679         }
11680 }
11681
11682 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11683 {
11684         u32 val, major, minor;
11685
11686         /* Use native endian representation */
11687         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11688                 return;
11689
11690         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11691                 TG3_NVM_HWSB_CFG1_MAJSFT;
11692         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11693                 TG3_NVM_HWSB_CFG1_MINSFT;
11694
11695         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11696 }
11697
11698 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11699 {
11700         u32 offset, major, minor, build;
11701
11702         tp->fw_ver[0] = 's';
11703         tp->fw_ver[1] = 'b';
11704         tp->fw_ver[2] = '\0';
11705
11706         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11707                 return;
11708
11709         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11710         case TG3_EEPROM_SB_REVISION_0:
11711                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11712                 break;
11713         case TG3_EEPROM_SB_REVISION_2:
11714                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11715                 break;
11716         case TG3_EEPROM_SB_REVISION_3:
11717                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11718                 break;
11719         default:
11720                 return;
11721         }
11722
11723         if (tg3_nvram_read(tp, offset, &val))
11724                 return;
11725
11726         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11727                 TG3_EEPROM_SB_EDH_BLD_SHFT;
11728         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11729                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11730         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
11731
11732         if (minor > 99 || build > 26)
11733                 return;
11734
11735         snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11736
11737         if (build > 0) {
11738                 tp->fw_ver[8] = 'a' + build - 1;
11739                 tp->fw_ver[9] = '\0';
11740         }
11741 }
11742
11743 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11744 {
11745         u32 val, offset, start;
11746         int i, vlen;
11747
11748         for (offset = TG3_NVM_DIR_START;
11749              offset < TG3_NVM_DIR_END;
11750              offset += TG3_NVM_DIRENT_SIZE) {
11751                 if (tg3_nvram_read(tp, offset, &val))
11752                         return;
11753
11754                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11755                         break;
11756         }
11757
11758         if (offset == TG3_NVM_DIR_END)
11759                 return;
11760
11761         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11762                 start = 0x08000000;
11763         else if (tg3_nvram_read(tp, offset - 4, &start))
11764                 return;
11765
11766         if (tg3_nvram_read(tp, offset + 4, &offset) ||
11767             !tg3_fw_img_is_valid(tp, offset) ||
11768             tg3_nvram_read(tp, offset + 8, &val))
11769                 return;
11770
11771         offset += val - start;
11772
11773         vlen = strlen(tp->fw_ver);
11774
11775         tp->fw_ver[vlen++] = ',';
11776         tp->fw_ver[vlen++] = ' ';
11777
11778         for (i = 0; i < 4; i++) {
11779                 __be32 v;
11780                 if (tg3_nvram_read_be32(tp, offset, &v))
11781                         return;
11782
11783                 offset += sizeof(v);
11784
11785                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11786                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11787                         break;
11788                 }
11789
11790                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11791                 vlen += sizeof(v);
11792         }
11793 }
11794
11795 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11796 {
11797         int vlen;
11798         u32 apedata;
11799
11800         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11801             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
11802                 return;
11803
11804         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11805         if (apedata != APE_SEG_SIG_MAGIC)
11806                 return;
11807
11808         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11809         if (!(apedata & APE_FW_STATUS_READY))
11810                 return;
11811
11812         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11813
11814         vlen = strlen(tp->fw_ver);
11815
11816         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11817                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11818                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11819                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11820                  (apedata & APE_FW_VERSION_BLDMSK));
11821 }
11822
11823 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11824 {
11825         u32 val;
11826
11827         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11828                 tp->fw_ver[0] = 's';
11829                 tp->fw_ver[1] = 'b';
11830                 tp->fw_ver[2] = '\0';
11831
11832                 return;
11833         }
11834
11835         if (tg3_nvram_read(tp, 0, &val))
11836                 return;
11837
11838         if (val == TG3_EEPROM_MAGIC)
11839                 tg3_read_bc_ver(tp);
11840         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11841                 tg3_read_sb_ver(tp, val);
11842         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11843                 tg3_read_hwsb_ver(tp);
11844         else
11845                 return;
11846
11847         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11848              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11849                 return;
11850
11851         tg3_read_mgmtfw_ver(tp);
11852
11853         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11854 }
11855
11856 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11857
11858 static int __devinit tg3_get_invariants(struct tg3 *tp)
11859 {
11860         static struct pci_device_id write_reorder_chipsets[] = {
11861                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11862                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11863                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11864                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11865                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11866                              PCI_DEVICE_ID_VIA_8385_0) },
11867                 { },
11868         };
11869         u32 misc_ctrl_reg;
11870         u32 pci_state_reg, grc_misc_cfg;
11871         u32 val;
11872         u16 pci_cmd;
11873         int err;
11874
11875         /* Force memory write invalidate off.  If we leave it on,
11876          * then on 5700_BX chips we have to enable a workaround.
11877          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11878          * to match the cacheline size.  The Broadcom driver have this
11879          * workaround but turns MWI off all the times so never uses
11880          * it.  This seems to suggest that the workaround is insufficient.
11881          */
11882         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11883         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11884         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11885
11886         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11887          * has the register indirect write enable bit set before
11888          * we try to access any of the MMIO registers.  It is also
11889          * critical that the PCI-X hw workaround situation is decided
11890          * before that as well.
11891          */
11892         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11893                               &misc_ctrl_reg);
11894
11895         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11896                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11897         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11898                 u32 prod_id_asic_rev;
11899
11900                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11901                                       &prod_id_asic_rev);
11902                 tp->pci_chip_rev_id = prod_id_asic_rev;
11903         }
11904
11905         /* Wrong chip ID in 5752 A0. This code can be removed later
11906          * as A0 is not in production.
11907          */
11908         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11909                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11910
11911         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11912          * we need to disable memory and use config. cycles
11913          * only to access all registers. The 5702/03 chips
11914          * can mistakenly decode the special cycles from the
11915          * ICH chipsets as memory write cycles, causing corruption
11916          * of register and memory space. Only certain ICH bridges
11917          * will drive special cycles with non-zero data during the
11918          * address phase which can fall within the 5703's address
11919          * range. This is not an ICH bug as the PCI spec allows
11920          * non-zero address during special cycles. However, only
11921          * these ICH bridges are known to drive non-zero addresses
11922          * during special cycles.
11923          *
11924          * Since special cycles do not cross PCI bridges, we only
11925          * enable this workaround if the 5703 is on the secondary
11926          * bus of these ICH bridges.
11927          */
11928         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11929             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11930                 static struct tg3_dev_id {
11931                         u32     vendor;
11932                         u32     device;
11933                         u32     rev;
11934                 } ich_chipsets[] = {
11935                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11936                           PCI_ANY_ID },
11937                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11938                           PCI_ANY_ID },
11939                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11940                           0xa },
11941                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11942                           PCI_ANY_ID },
11943                         { },
11944                 };
11945                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11946                 struct pci_dev *bridge = NULL;
11947
11948                 while (pci_id->vendor != 0) {
11949                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11950                                                 bridge);
11951                         if (!bridge) {
11952                                 pci_id++;
11953                                 continue;
11954                         }
11955                         if (pci_id->rev != PCI_ANY_ID) {
11956                                 if (bridge->revision > pci_id->rev)
11957                                         continue;
11958                         }
11959                         if (bridge->subordinate &&
11960                             (bridge->subordinate->number ==
11961                              tp->pdev->bus->number)) {
11962
11963                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11964                                 pci_dev_put(bridge);
11965                                 break;
11966                         }
11967                 }
11968         }
11969
11970         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11971                 static struct tg3_dev_id {
11972                         u32     vendor;
11973                         u32     device;
11974                 } bridge_chipsets[] = {
11975                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11976                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11977                         { },
11978                 };
11979                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11980                 struct pci_dev *bridge = NULL;
11981
11982                 while (pci_id->vendor != 0) {
11983                         bridge = pci_get_device(pci_id->vendor,
11984                                                 pci_id->device,
11985                                                 bridge);
11986                         if (!bridge) {
11987                                 pci_id++;
11988                                 continue;
11989                         }
11990                         if (bridge->subordinate &&
11991                             (bridge->subordinate->number <=
11992                              tp->pdev->bus->number) &&
11993                             (bridge->subordinate->subordinate >=
11994                              tp->pdev->bus->number)) {
11995                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11996                                 pci_dev_put(bridge);
11997                                 break;
11998                         }
11999                 }
12000         }
12001
12002         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12003          * DMA addresses > 40-bit. This bridge may have other additional
12004          * 57xx devices behind it in some 4-port NIC designs for example.
12005          * Any tg3 device found behind the bridge will also need the 40-bit
12006          * DMA workaround.
12007          */
12008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12010                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12011                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12012                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12013         }
12014         else {
12015                 struct pci_dev *bridge = NULL;
12016
12017                 do {
12018                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12019                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12020                                                 bridge);
12021                         if (bridge && bridge->subordinate &&
12022                             (bridge->subordinate->number <=
12023                              tp->pdev->bus->number) &&
12024                             (bridge->subordinate->subordinate >=
12025                              tp->pdev->bus->number)) {
12026                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12027                                 pci_dev_put(bridge);
12028                                 break;
12029                         }
12030                 } while (bridge);
12031         }
12032
12033         /* Initialize misc host control in PCI block. */
12034         tp->misc_host_ctrl |= (misc_ctrl_reg &
12035                                MISC_HOST_CTRL_CHIPREV);
12036         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12037                                tp->misc_host_ctrl);
12038
12039         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12040             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12041                 tp->pdev_peer = tg3_find_peer(tp);
12042
12043         /* Intentionally exclude ASIC_REV_5906 */
12044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12048             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12049             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12050                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12051
12052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12055             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12056             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12057                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12058
12059         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12060             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12061                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12062
12063         /* 5700 B0 chips do not support checksumming correctly due
12064          * to hardware bugs.
12065          */
12066         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12067                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12068         else {
12069                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12070                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12071                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12072                         tp->dev->features |= NETIF_F_IPV6_CSUM;
12073         }
12074
12075         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12076                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12077                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12078                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12079                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12080                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12081                      tp->pdev_peer == tp->pdev))
12082                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12083
12084                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12085                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12086                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12087                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12088                 } else {
12089                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12090                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12091                                 ASIC_REV_5750 &&
12092                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12093                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12094                 }
12095         }
12096
12097         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12098              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12099                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12100
12101         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12102                               &pci_state_reg);
12103
12104         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12105         if (tp->pcie_cap != 0) {
12106                 u16 lnkctl;
12107
12108                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12109
12110                 pcie_set_readrq(tp->pdev, 4096);
12111
12112                 pci_read_config_word(tp->pdev,
12113                                      tp->pcie_cap + PCI_EXP_LNKCTL,
12114                                      &lnkctl);
12115                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12116                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12117                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12118                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12119                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12120                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12121                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12122                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12123                 }
12124         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12125                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12126         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12127                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12128                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12129                 if (!tp->pcix_cap) {
12130                         printk(KERN_ERR PFX "Cannot find PCI-X "
12131                                             "capability, aborting.\n");
12132                         return -EIO;
12133                 }
12134
12135                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12136                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12137         }
12138
12139         /* If we have an AMD 762 or VIA K8T800 chipset, write
12140          * reordering to the mailbox registers done by the host
12141          * controller can cause major troubles.  We read back from
12142          * every mailbox register write to force the writes to be
12143          * posted to the chip in order.
12144          */
12145         if (pci_dev_present(write_reorder_chipsets) &&
12146             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12147                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12148
12149         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12150                              &tp->pci_cacheline_sz);
12151         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12152                              &tp->pci_lat_timer);
12153         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12154             tp->pci_lat_timer < 64) {
12155                 tp->pci_lat_timer = 64;
12156                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12157                                       tp->pci_lat_timer);
12158         }
12159
12160         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12161                 /* 5700 BX chips need to have their TX producer index
12162                  * mailboxes written twice to workaround a bug.
12163                  */
12164                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12165
12166                 /* If we are in PCI-X mode, enable register write workaround.
12167                  *
12168                  * The workaround is to use indirect register accesses
12169                  * for all chip writes not to mailbox registers.
12170                  */
12171                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12172                         u32 pm_reg;
12173
12174                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12175
12176                         /* The chip can have it's power management PCI config
12177                          * space registers clobbered due to this bug.
12178                          * So explicitly force the chip into D0 here.
12179                          */
12180                         pci_read_config_dword(tp->pdev,
12181                                               tp->pm_cap + PCI_PM_CTRL,
12182                                               &pm_reg);
12183                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12184                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12185                         pci_write_config_dword(tp->pdev,
12186                                                tp->pm_cap + PCI_PM_CTRL,
12187                                                pm_reg);
12188
12189                         /* Also, force SERR#/PERR# in PCI command. */
12190                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12191                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12192                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12193                 }
12194         }
12195
12196         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12197                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12198         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12199                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12200
12201         /* Chip-specific fixup from Broadcom driver */
12202         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12203             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12204                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12205                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12206         }
12207
12208         /* Default fast path register access methods */
12209         tp->read32 = tg3_read32;
12210         tp->write32 = tg3_write32;
12211         tp->read32_mbox = tg3_read32;
12212         tp->write32_mbox = tg3_write32;
12213         tp->write32_tx_mbox = tg3_write32;
12214         tp->write32_rx_mbox = tg3_write32;
12215
12216         /* Various workaround register access methods */
12217         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12218                 tp->write32 = tg3_write_indirect_reg32;
12219         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12220                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12221                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12222                 /*
12223                  * Back to back register writes can cause problems on these
12224                  * chips, the workaround is to read back all reg writes
12225                  * except those to mailbox regs.
12226                  *
12227                  * See tg3_write_indirect_reg32().
12228                  */
12229                 tp->write32 = tg3_write_flush_reg32;
12230         }
12231
12232
12233         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12234             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12235                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12236                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12237                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12238         }
12239
12240         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12241                 tp->read32 = tg3_read_indirect_reg32;
12242                 tp->write32 = tg3_write_indirect_reg32;
12243                 tp->read32_mbox = tg3_read_indirect_mbox;
12244                 tp->write32_mbox = tg3_write_indirect_mbox;
12245                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12246                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12247
12248                 iounmap(tp->regs);
12249                 tp->regs = NULL;
12250
12251                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12252                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12253                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12254         }
12255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12256                 tp->read32_mbox = tg3_read32_mbox_5906;
12257                 tp->write32_mbox = tg3_write32_mbox_5906;
12258                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12259                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12260         }
12261
12262         if (tp->write32 == tg3_write_indirect_reg32 ||
12263             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12264              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12265               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12266                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12267
12268         /* Get eeprom hw config before calling tg3_set_power_state().
12269          * In particular, the TG3_FLG2_IS_NIC flag must be
12270          * determined before calling tg3_set_power_state() so that
12271          * we know whether or not to switch out of Vaux power.
12272          * When the flag is set, it means that GPIO1 is used for eeprom
12273          * write protect and also implies that it is a LOM where GPIOs
12274          * are not used to switch power.
12275          */
12276         tg3_get_eeprom_hw_cfg(tp);
12277
12278         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12279                 /* Allow reads and writes to the
12280                  * APE register and memory space.
12281                  */
12282                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12283                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12284                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12285                                        pci_state_reg);
12286         }
12287
12288         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12289             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12290             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12291             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12292                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12293
12294         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12295          * GPIO1 driven high will bring 5700's external PHY out of reset.
12296          * It is also used as eeprom write protect on LOMs.
12297          */
12298         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12299         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12300             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12301                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12302                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12303         /* Unused GPIO3 must be driven as output on 5752 because there
12304          * are no pull-up resistors on unused GPIO pins.
12305          */
12306         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12307                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12308
12309         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12310             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12311                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12312
12313         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12314             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12315                 /* Turn off the debug UART. */
12316                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12317                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12318                         /* Keep VMain power. */
12319                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12320                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12321         }
12322
12323         /* Force the chip into D0. */
12324         err = tg3_set_power_state(tp, PCI_D0);
12325         if (err) {
12326                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12327                        pci_name(tp->pdev));
12328                 return err;
12329         }
12330
12331         /* Derive initial jumbo mode from MTU assigned in
12332          * ether_setup() via the alloc_etherdev() call
12333          */
12334         if (tp->dev->mtu > ETH_DATA_LEN &&
12335             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12336                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12337
12338         /* Determine WakeOnLan speed to use. */
12339         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12340             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12341             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12342             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12343                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12344         } else {
12345                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12346         }
12347
12348         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12349                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12350
12351         /* A few boards don't want Ethernet@WireSpeed phy feature */
12352         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12353             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12354              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12355              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12356             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12357             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12358                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12359
12360         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12361             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12362                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12363         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12364                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12365
12366         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12367             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12368             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12369             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12370                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12371                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12372                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12373                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12374                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12375                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12376                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12377                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12378                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12379                 } else
12380                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12381         }
12382
12383         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12384             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12385                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12386                 if (tp->phy_otp == 0)
12387                         tp->phy_otp = TG3_OTP_DEFAULT;
12388         }
12389
12390         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12391                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12392         else
12393                 tp->mi_mode = MAC_MI_MODE_BASE;
12394
12395         tp->coalesce_mode = 0;
12396         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12397             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12398                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12399
12400         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12401             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12402                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12403
12404         if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12405              tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12406             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12407                 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12408
12409         err = tg3_mdio_init(tp);
12410         if (err)
12411                 return err;
12412
12413         /* Initialize data/descriptor byte/word swapping. */
12414         val = tr32(GRC_MODE);
12415         val &= GRC_MODE_HOST_STACKUP;
12416         tw32(GRC_MODE, val | tp->grc_mode);
12417
12418         tg3_switch_clocks(tp);
12419
12420         /* Clear this out for sanity. */
12421         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12422
12423         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12424                               &pci_state_reg);
12425         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12426             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12427                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12428
12429                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12430                     chiprevid == CHIPREV_ID_5701_B0 ||
12431                     chiprevid == CHIPREV_ID_5701_B2 ||
12432                     chiprevid == CHIPREV_ID_5701_B5) {
12433                         void __iomem *sram_base;
12434
12435                         /* Write some dummy words into the SRAM status block
12436                          * area, see if it reads back correctly.  If the return
12437                          * value is bad, force enable the PCIX workaround.
12438                          */
12439                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12440
12441                         writel(0x00000000, sram_base);
12442                         writel(0x00000000, sram_base + 4);
12443                         writel(0xffffffff, sram_base + 4);
12444                         if (readl(sram_base) != 0x00000000)
12445                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12446                 }
12447         }
12448
12449         udelay(50);
12450         tg3_nvram_init(tp);
12451
12452         grc_misc_cfg = tr32(GRC_MISC_CFG);
12453         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12454
12455         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12456             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12457              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12458                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12459
12460         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12461             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12462                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12463         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12464                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12465                                       HOSTCC_MODE_CLRTICK_TXBD);
12466
12467                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12468                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12469                                        tp->misc_host_ctrl);
12470         }
12471
12472         /* Preserve the APE MAC_MODE bits */
12473         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12474                 tp->mac_mode = tr32(MAC_MODE) |
12475                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12476         else
12477                 tp->mac_mode = TG3_DEF_MAC_MODE;
12478
12479         /* these are limited to 10/100 only */
12480         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12481              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12482             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12483              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12484              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12485               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12486               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12487             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12488              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12489               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12490               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12491             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12492             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
12493                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12494
12495         err = tg3_phy_probe(tp);
12496         if (err) {
12497                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12498                        pci_name(tp->pdev), err);
12499                 /* ... but do not return immediately ... */
12500                 tg3_mdio_fini(tp);
12501         }
12502
12503         tg3_read_partno(tp);
12504         tg3_read_fw_ver(tp);
12505
12506         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12507                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12508         } else {
12509                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12510                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12511                 else
12512                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12513         }
12514
12515         /* 5700 {AX,BX} chips have a broken status block link
12516          * change bit implementation, so we must use the
12517          * status register in those cases.
12518          */
12519         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12520                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12521         else
12522                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12523
12524         /* The led_ctrl is set during tg3_phy_probe, here we might
12525          * have to force the link status polling mechanism based
12526          * upon subsystem IDs.
12527          */
12528         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12529             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12530             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12531                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12532                                   TG3_FLAG_USE_LINKCHG_REG);
12533         }
12534
12535         /* For all SERDES we poll the MAC status register. */
12536         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12537                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12538         else
12539                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12540
12541         tp->rx_offset = NET_IP_ALIGN;
12542         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12543             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12544                 tp->rx_offset = 0;
12545
12546         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12547
12548         /* Increment the rx prod index on the rx std ring by at most
12549          * 8 for these chips to workaround hw errata.
12550          */
12551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12552             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12553             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12554                 tp->rx_std_max_post = 8;
12555
12556         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12557                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12558                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12559
12560         return err;
12561 }
12562
12563 #ifdef CONFIG_SPARC
12564 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12565 {
12566         struct net_device *dev = tp->dev;
12567         struct pci_dev *pdev = tp->pdev;
12568         struct device_node *dp = pci_device_to_OF_node(pdev);
12569         const unsigned char *addr;
12570         int len;
12571
12572         addr = of_get_property(dp, "local-mac-address", &len);
12573         if (addr && len == 6) {
12574                 memcpy(dev->dev_addr, addr, 6);
12575                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12576                 return 0;
12577         }
12578         return -ENODEV;
12579 }
12580
12581 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12582 {
12583         struct net_device *dev = tp->dev;
12584
12585         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12586         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12587         return 0;
12588 }
12589 #endif
12590
12591 static int __devinit tg3_get_device_address(struct tg3 *tp)
12592 {
12593         struct net_device *dev = tp->dev;
12594         u32 hi, lo, mac_offset;
12595         int addr_ok = 0;
12596
12597 #ifdef CONFIG_SPARC
12598         if (!tg3_get_macaddr_sparc(tp))
12599                 return 0;
12600 #endif
12601
12602         mac_offset = 0x7c;
12603         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12604             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12605                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12606                         mac_offset = 0xcc;
12607                 if (tg3_nvram_lock(tp))
12608                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12609                 else
12610                         tg3_nvram_unlock(tp);
12611         }
12612         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12613                 mac_offset = 0x10;
12614
12615         /* First try to get it from MAC address mailbox. */
12616         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12617         if ((hi >> 16) == 0x484b) {
12618                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12619                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12620
12621                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12622                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12623                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12624                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12625                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12626
12627                 /* Some old bootcode may report a 0 MAC address in SRAM */
12628                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12629         }
12630         if (!addr_ok) {
12631                 /* Next, try NVRAM. */
12632                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12633                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12634                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12635                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12636                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12637                 }
12638                 /* Finally just fetch it out of the MAC control regs. */
12639                 else {
12640                         hi = tr32(MAC_ADDR_0_HIGH);
12641                         lo = tr32(MAC_ADDR_0_LOW);
12642
12643                         dev->dev_addr[5] = lo & 0xff;
12644                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12645                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12646                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12647                         dev->dev_addr[1] = hi & 0xff;
12648                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12649                 }
12650         }
12651
12652         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12653 #ifdef CONFIG_SPARC
12654                 if (!tg3_get_default_macaddr_sparc(tp))
12655                         return 0;
12656 #endif
12657                 return -EINVAL;
12658         }
12659         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12660         return 0;
12661 }
12662
12663 #define BOUNDARY_SINGLE_CACHELINE       1
12664 #define BOUNDARY_MULTI_CACHELINE        2
12665
12666 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12667 {
12668         int cacheline_size;
12669         u8 byte;
12670         int goal;
12671
12672         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12673         if (byte == 0)
12674                 cacheline_size = 1024;
12675         else
12676                 cacheline_size = (int) byte * 4;
12677
12678         /* On 5703 and later chips, the boundary bits have no
12679          * effect.
12680          */
12681         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12682             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12683             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12684                 goto out;
12685
12686 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12687         goal = BOUNDARY_MULTI_CACHELINE;
12688 #else
12689 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12690         goal = BOUNDARY_SINGLE_CACHELINE;
12691 #else
12692         goal = 0;
12693 #endif
12694 #endif
12695
12696         if (!goal)
12697                 goto out;
12698
12699         /* PCI controllers on most RISC systems tend to disconnect
12700          * when a device tries to burst across a cache-line boundary.
12701          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12702          *
12703          * Unfortunately, for PCI-E there are only limited
12704          * write-side controls for this, and thus for reads
12705          * we will still get the disconnects.  We'll also waste
12706          * these PCI cycles for both read and write for chips
12707          * other than 5700 and 5701 which do not implement the
12708          * boundary bits.
12709          */
12710         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12711             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12712                 switch (cacheline_size) {
12713                 case 16:
12714                 case 32:
12715                 case 64:
12716                 case 128:
12717                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12718                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12719                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12720                         } else {
12721                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12722                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12723                         }
12724                         break;
12725
12726                 case 256:
12727                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12728                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12729                         break;
12730
12731                 default:
12732                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12733                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12734                         break;
12735                 }
12736         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12737                 switch (cacheline_size) {
12738                 case 16:
12739                 case 32:
12740                 case 64:
12741                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12742                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12743                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12744                                 break;
12745                         }
12746                         /* fallthrough */
12747                 case 128:
12748                 default:
12749                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12750                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12751                         break;
12752                 }
12753         } else {
12754                 switch (cacheline_size) {
12755                 case 16:
12756                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12757                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12758                                         DMA_RWCTRL_WRITE_BNDRY_16);
12759                                 break;
12760                         }
12761                         /* fallthrough */
12762                 case 32:
12763                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12764                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12765                                         DMA_RWCTRL_WRITE_BNDRY_32);
12766                                 break;
12767                         }
12768                         /* fallthrough */
12769                 case 64:
12770                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12771                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12772                                         DMA_RWCTRL_WRITE_BNDRY_64);
12773                                 break;
12774                         }
12775                         /* fallthrough */
12776                 case 128:
12777                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12778                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12779                                         DMA_RWCTRL_WRITE_BNDRY_128);
12780                                 break;
12781                         }
12782                         /* fallthrough */
12783                 case 256:
12784                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12785                                 DMA_RWCTRL_WRITE_BNDRY_256);
12786                         break;
12787                 case 512:
12788                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12789                                 DMA_RWCTRL_WRITE_BNDRY_512);
12790                         break;
12791                 case 1024:
12792                 default:
12793                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12794                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12795                         break;
12796                 }
12797         }
12798
12799 out:
12800         return val;
12801 }
12802
12803 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12804 {
12805         struct tg3_internal_buffer_desc test_desc;
12806         u32 sram_dma_descs;
12807         int i, ret;
12808
12809         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12810
12811         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12812         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12813         tw32(RDMAC_STATUS, 0);
12814         tw32(WDMAC_STATUS, 0);
12815
12816         tw32(BUFMGR_MODE, 0);
12817         tw32(FTQ_RESET, 0);
12818
12819         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12820         test_desc.addr_lo = buf_dma & 0xffffffff;
12821         test_desc.nic_mbuf = 0x00002100;
12822         test_desc.len = size;
12823
12824         /*
12825          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12826          * the *second* time the tg3 driver was getting loaded after an
12827          * initial scan.
12828          *
12829          * Broadcom tells me:
12830          *   ...the DMA engine is connected to the GRC block and a DMA
12831          *   reset may affect the GRC block in some unpredictable way...
12832          *   The behavior of resets to individual blocks has not been tested.
12833          *
12834          * Broadcom noted the GRC reset will also reset all sub-components.
12835          */
12836         if (to_device) {
12837                 test_desc.cqid_sqid = (13 << 8) | 2;
12838
12839                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12840                 udelay(40);
12841         } else {
12842                 test_desc.cqid_sqid = (16 << 8) | 7;
12843
12844                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12845                 udelay(40);
12846         }
12847         test_desc.flags = 0x00000005;
12848
12849         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12850                 u32 val;
12851
12852                 val = *(((u32 *)&test_desc) + i);
12853                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12854                                        sram_dma_descs + (i * sizeof(u32)));
12855                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12856         }
12857         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12858
12859         if (to_device) {
12860                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12861         } else {
12862                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12863         }
12864
12865         ret = -ENODEV;
12866         for (i = 0; i < 40; i++) {
12867                 u32 val;
12868
12869                 if (to_device)
12870                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12871                 else
12872                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12873                 if ((val & 0xffff) == sram_dma_descs) {
12874                         ret = 0;
12875                         break;
12876                 }
12877
12878                 udelay(100);
12879         }
12880
12881         return ret;
12882 }
12883
12884 #define TEST_BUFFER_SIZE        0x2000
12885
12886 static int __devinit tg3_test_dma(struct tg3 *tp)
12887 {
12888         dma_addr_t buf_dma;
12889         u32 *buf, saved_dma_rwctrl;
12890         int ret;
12891
12892         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12893         if (!buf) {
12894                 ret = -ENOMEM;
12895                 goto out_nofree;
12896         }
12897
12898         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12899                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12900
12901         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12902
12903         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12904                 /* DMA read watermark not used on PCIE */
12905                 tp->dma_rwctrl |= 0x00180000;
12906         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12907                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12908                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12909                         tp->dma_rwctrl |= 0x003f0000;
12910                 else
12911                         tp->dma_rwctrl |= 0x003f000f;
12912         } else {
12913                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12914                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12915                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12916                         u32 read_water = 0x7;
12917
12918                         /* If the 5704 is behind the EPB bridge, we can
12919                          * do the less restrictive ONE_DMA workaround for
12920                          * better performance.
12921                          */
12922                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12923                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12924                                 tp->dma_rwctrl |= 0x8000;
12925                         else if (ccval == 0x6 || ccval == 0x7)
12926                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12927
12928                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12929                                 read_water = 4;
12930                         /* Set bit 23 to enable PCIX hw bug fix */
12931                         tp->dma_rwctrl |=
12932                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12933                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12934                                 (1 << 23);
12935                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12936                         /* 5780 always in PCIX mode */
12937                         tp->dma_rwctrl |= 0x00144000;
12938                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12939                         /* 5714 always in PCIX mode */
12940                         tp->dma_rwctrl |= 0x00148000;
12941                 } else {
12942                         tp->dma_rwctrl |= 0x001b000f;
12943                 }
12944         }
12945
12946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12947             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12948                 tp->dma_rwctrl &= 0xfffffff0;
12949
12950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12951             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12952                 /* Remove this if it causes problems for some boards. */
12953                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12954
12955                 /* On 5700/5701 chips, we need to set this bit.
12956                  * Otherwise the chip will issue cacheline transactions
12957                  * to streamable DMA memory with not all the byte
12958                  * enables turned on.  This is an error on several
12959                  * RISC PCI controllers, in particular sparc64.
12960                  *
12961                  * On 5703/5704 chips, this bit has been reassigned
12962                  * a different meaning.  In particular, it is used
12963                  * on those chips to enable a PCI-X workaround.
12964                  */
12965                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12966         }
12967
12968         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12969
12970 #if 0
12971         /* Unneeded, already done by tg3_get_invariants.  */
12972         tg3_switch_clocks(tp);
12973 #endif
12974
12975         ret = 0;
12976         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12977             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12978                 goto out;
12979
12980         /* It is best to perform DMA test with maximum write burst size
12981          * to expose the 5700/5701 write DMA bug.
12982          */
12983         saved_dma_rwctrl = tp->dma_rwctrl;
12984         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12985         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12986
12987         while (1) {
12988                 u32 *p = buf, i;
12989
12990                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12991                         p[i] = i;
12992
12993                 /* Send the buffer to the chip. */
12994                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12995                 if (ret) {
12996                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12997                         break;
12998                 }
12999
13000 #if 0
13001                 /* validate data reached card RAM correctly. */
13002                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13003                         u32 val;
13004                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
13005                         if (le32_to_cpu(val) != p[i]) {
13006                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
13007                                 /* ret = -ENODEV here? */
13008                         }
13009                         p[i] = 0;
13010                 }
13011 #endif
13012                 /* Now read it back. */
13013                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13014                 if (ret) {
13015                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13016
13017                         break;
13018                 }
13019
13020                 /* Verify it. */
13021                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13022                         if (p[i] == i)
13023                                 continue;
13024
13025                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13026                             DMA_RWCTRL_WRITE_BNDRY_16) {
13027                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13028                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13029                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13030                                 break;
13031                         } else {
13032                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13033                                 ret = -ENODEV;
13034                                 goto out;
13035                         }
13036                 }
13037
13038                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13039                         /* Success. */
13040                         ret = 0;
13041                         break;
13042                 }
13043         }
13044         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13045             DMA_RWCTRL_WRITE_BNDRY_16) {
13046                 static struct pci_device_id dma_wait_state_chipsets[] = {
13047                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13048                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13049                         { },
13050                 };
13051
13052                 /* DMA test passed without adjusting DMA boundary,
13053                  * now look for chipsets that are known to expose the
13054                  * DMA bug without failing the test.
13055                  */
13056                 if (pci_dev_present(dma_wait_state_chipsets)) {
13057                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13058                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13059                 }
13060                 else
13061                         /* Safe to use the calculated DMA boundary. */
13062                         tp->dma_rwctrl = saved_dma_rwctrl;
13063
13064                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13065         }
13066
13067 out:
13068         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13069 out_nofree:
13070         return ret;
13071 }
13072
13073 static void __devinit tg3_init_link_config(struct tg3 *tp)
13074 {
13075         tp->link_config.advertising =
13076                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13077                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13078                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13079                  ADVERTISED_Autoneg | ADVERTISED_MII);
13080         tp->link_config.speed = SPEED_INVALID;
13081         tp->link_config.duplex = DUPLEX_INVALID;
13082         tp->link_config.autoneg = AUTONEG_ENABLE;
13083         tp->link_config.active_speed = SPEED_INVALID;
13084         tp->link_config.active_duplex = DUPLEX_INVALID;
13085         tp->link_config.phy_is_low_power = 0;
13086         tp->link_config.orig_speed = SPEED_INVALID;
13087         tp->link_config.orig_duplex = DUPLEX_INVALID;
13088         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13089 }
13090
13091 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13092 {
13093         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13094                 tp->bufmgr_config.mbuf_read_dma_low_water =
13095                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13096                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13097                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13098                 tp->bufmgr_config.mbuf_high_water =
13099                         DEFAULT_MB_HIGH_WATER_5705;
13100                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13101                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13102                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13103                         tp->bufmgr_config.mbuf_high_water =
13104                                 DEFAULT_MB_HIGH_WATER_5906;
13105                 }
13106
13107                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13108                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13109                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13110                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13111                 tp->bufmgr_config.mbuf_high_water_jumbo =
13112                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13113         } else {
13114                 tp->bufmgr_config.mbuf_read_dma_low_water =
13115                         DEFAULT_MB_RDMA_LOW_WATER;
13116                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13117                         DEFAULT_MB_MACRX_LOW_WATER;
13118                 tp->bufmgr_config.mbuf_high_water =
13119                         DEFAULT_MB_HIGH_WATER;
13120
13121                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13122                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13123                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13124                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13125                 tp->bufmgr_config.mbuf_high_water_jumbo =
13126                         DEFAULT_MB_HIGH_WATER_JUMBO;
13127         }
13128
13129         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13130         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13131 }
13132
13133 static char * __devinit tg3_phy_string(struct tg3 *tp)
13134 {
13135         switch (tp->phy_id & PHY_ID_MASK) {
13136         case PHY_ID_BCM5400:    return "5400";
13137         case PHY_ID_BCM5401:    return "5401";
13138         case PHY_ID_BCM5411:    return "5411";
13139         case PHY_ID_BCM5701:    return "5701";
13140         case PHY_ID_BCM5703:    return "5703";
13141         case PHY_ID_BCM5704:    return "5704";
13142         case PHY_ID_BCM5705:    return "5705";
13143         case PHY_ID_BCM5750:    return "5750";
13144         case PHY_ID_BCM5752:    return "5752";
13145         case PHY_ID_BCM5714:    return "5714";
13146         case PHY_ID_BCM5780:    return "5780";
13147         case PHY_ID_BCM5755:    return "5755";
13148         case PHY_ID_BCM5787:    return "5787";
13149         case PHY_ID_BCM5784:    return "5784";
13150         case PHY_ID_BCM5756:    return "5722/5756";
13151         case PHY_ID_BCM5906:    return "5906";
13152         case PHY_ID_BCM5761:    return "5761";
13153         case PHY_ID_BCM8002:    return "8002/serdes";
13154         case 0:                 return "serdes";
13155         default:                return "unknown";
13156         }
13157 }
13158
13159 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13160 {
13161         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13162                 strcpy(str, "PCI Express");
13163                 return str;
13164         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13165                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13166
13167                 strcpy(str, "PCIX:");
13168
13169                 if ((clock_ctrl == 7) ||
13170                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13171                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13172                         strcat(str, "133MHz");
13173                 else if (clock_ctrl == 0)
13174                         strcat(str, "33MHz");
13175                 else if (clock_ctrl == 2)
13176                         strcat(str, "50MHz");
13177                 else if (clock_ctrl == 4)
13178                         strcat(str, "66MHz");
13179                 else if (clock_ctrl == 6)
13180                         strcat(str, "100MHz");
13181         } else {
13182                 strcpy(str, "PCI:");
13183                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13184                         strcat(str, "66MHz");
13185                 else
13186                         strcat(str, "33MHz");
13187         }
13188         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13189                 strcat(str, ":32-bit");
13190         else
13191                 strcat(str, ":64-bit");
13192         return str;
13193 }
13194
13195 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13196 {
13197         struct pci_dev *peer;
13198         unsigned int func, devnr = tp->pdev->devfn & ~7;
13199
13200         for (func = 0; func < 8; func++) {
13201                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13202                 if (peer && peer != tp->pdev)
13203                         break;
13204                 pci_dev_put(peer);
13205         }
13206         /* 5704 can be configured in single-port mode, set peer to
13207          * tp->pdev in that case.
13208          */
13209         if (!peer) {
13210                 peer = tp->pdev;
13211                 return peer;
13212         }
13213
13214         /*
13215          * We don't need to keep the refcount elevated; there's no way
13216          * to remove one half of this device without removing the other
13217          */
13218         pci_dev_put(peer);
13219
13220         return peer;
13221 }
13222
13223 static void __devinit tg3_init_coal(struct tg3 *tp)
13224 {
13225         struct ethtool_coalesce *ec = &tp->coal;
13226
13227         memset(ec, 0, sizeof(*ec));
13228         ec->cmd = ETHTOOL_GCOALESCE;
13229         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13230         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13231         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13232         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13233         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13234         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13235         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13236         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13237         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13238
13239         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13240                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13241                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13242                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13243                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13244                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13245         }
13246
13247         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13248                 ec->rx_coalesce_usecs_irq = 0;
13249                 ec->tx_coalesce_usecs_irq = 0;
13250                 ec->stats_block_coalesce_usecs = 0;
13251         }
13252 }
13253
13254 static const struct net_device_ops tg3_netdev_ops = {
13255         .ndo_open               = tg3_open,
13256         .ndo_stop               = tg3_close,
13257         .ndo_start_xmit         = tg3_start_xmit,
13258         .ndo_get_stats          = tg3_get_stats,
13259         .ndo_validate_addr      = eth_validate_addr,
13260         .ndo_set_multicast_list = tg3_set_rx_mode,
13261         .ndo_set_mac_address    = tg3_set_mac_addr,
13262         .ndo_do_ioctl           = tg3_ioctl,
13263         .ndo_tx_timeout         = tg3_tx_timeout,
13264         .ndo_change_mtu         = tg3_change_mtu,
13265 #if TG3_VLAN_TAG_USED
13266         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13267 #endif
13268 #ifdef CONFIG_NET_POLL_CONTROLLER
13269         .ndo_poll_controller    = tg3_poll_controller,
13270 #endif
13271 };
13272
13273 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13274         .ndo_open               = tg3_open,
13275         .ndo_stop               = tg3_close,
13276         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
13277         .ndo_get_stats          = tg3_get_stats,
13278         .ndo_validate_addr      = eth_validate_addr,
13279         .ndo_set_multicast_list = tg3_set_rx_mode,
13280         .ndo_set_mac_address    = tg3_set_mac_addr,
13281         .ndo_do_ioctl           = tg3_ioctl,
13282         .ndo_tx_timeout         = tg3_tx_timeout,
13283         .ndo_change_mtu         = tg3_change_mtu,
13284 #if TG3_VLAN_TAG_USED
13285         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
13286 #endif
13287 #ifdef CONFIG_NET_POLL_CONTROLLER
13288         .ndo_poll_controller    = tg3_poll_controller,
13289 #endif
13290 };
13291
13292 static int __devinit tg3_init_one(struct pci_dev *pdev,
13293                                   const struct pci_device_id *ent)
13294 {
13295         static int tg3_version_printed = 0;
13296         struct net_device *dev;
13297         struct tg3 *tp;
13298         int err, pm_cap;
13299         char str[40];
13300         u64 dma_mask, persist_dma_mask;
13301
13302         if (tg3_version_printed++ == 0)
13303                 printk(KERN_INFO "%s", version);
13304
13305         err = pci_enable_device(pdev);
13306         if (err) {
13307                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13308                        "aborting.\n");
13309                 return err;
13310         }
13311
13312         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13313         if (err) {
13314                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13315                        "aborting.\n");
13316                 goto err_out_disable_pdev;
13317         }
13318
13319         pci_set_master(pdev);
13320
13321         /* Find power-management capability. */
13322         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13323         if (pm_cap == 0) {
13324                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13325                        "aborting.\n");
13326                 err = -EIO;
13327                 goto err_out_free_res;
13328         }
13329
13330         dev = alloc_etherdev(sizeof(*tp));
13331         if (!dev) {
13332                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13333                 err = -ENOMEM;
13334                 goto err_out_free_res;
13335         }
13336
13337         SET_NETDEV_DEV(dev, &pdev->dev);
13338
13339 #if TG3_VLAN_TAG_USED
13340         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13341 #endif
13342
13343         tp = netdev_priv(dev);
13344         tp->pdev = pdev;
13345         tp->dev = dev;
13346         tp->pm_cap = pm_cap;
13347         tp->rx_mode = TG3_DEF_RX_MODE;
13348         tp->tx_mode = TG3_DEF_TX_MODE;
13349
13350         if (tg3_debug > 0)
13351                 tp->msg_enable = tg3_debug;
13352         else
13353                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13354
13355         /* The word/byte swap controls here control register access byte
13356          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13357          * setting below.
13358          */
13359         tp->misc_host_ctrl =
13360                 MISC_HOST_CTRL_MASK_PCI_INT |
13361                 MISC_HOST_CTRL_WORD_SWAP |
13362                 MISC_HOST_CTRL_INDIR_ACCESS |
13363                 MISC_HOST_CTRL_PCISTATE_RW;
13364
13365         /* The NONFRM (non-frame) byte/word swap controls take effect
13366          * on descriptor entries, anything which isn't packet data.
13367          *
13368          * The StrongARM chips on the board (one for tx, one for rx)
13369          * are running in big-endian mode.
13370          */
13371         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13372                         GRC_MODE_WSWAP_NONFRM_DATA);
13373 #ifdef __BIG_ENDIAN
13374         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13375 #endif
13376         spin_lock_init(&tp->lock);
13377         spin_lock_init(&tp->indirect_lock);
13378         INIT_WORK(&tp->reset_task, tg3_reset_task);
13379
13380         tp->regs = pci_ioremap_bar(pdev, BAR_0);
13381         if (!tp->regs) {
13382                 printk(KERN_ERR PFX "Cannot map device registers, "
13383                        "aborting.\n");
13384                 err = -ENOMEM;
13385                 goto err_out_free_dev;
13386         }
13387
13388         tg3_init_link_config(tp);
13389
13390         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13391         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13392         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13393
13394         tp->napi[0].tp = tp;
13395         netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13396         dev->ethtool_ops = &tg3_ethtool_ops;
13397         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13398         dev->irq = pdev->irq;
13399
13400         err = tg3_get_invariants(tp);
13401         if (err) {
13402                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13403                        "aborting.\n");
13404                 goto err_out_iounmap;
13405         }
13406
13407         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13408             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13409                 dev->netdev_ops = &tg3_netdev_ops;
13410         else
13411                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13412
13413
13414         /* The EPB bridge inside 5714, 5715, and 5780 and any
13415          * device behind the EPB cannot support DMA addresses > 40-bit.
13416          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13417          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13418          * do DMA address check in tg3_start_xmit().
13419          */
13420         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13421                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13422         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13423                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13424 #ifdef CONFIG_HIGHMEM
13425                 dma_mask = DMA_BIT_MASK(64);
13426 #endif
13427         } else
13428                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13429
13430         /* Configure DMA attributes. */
13431         if (dma_mask > DMA_BIT_MASK(32)) {
13432                 err = pci_set_dma_mask(pdev, dma_mask);
13433                 if (!err) {
13434                         dev->features |= NETIF_F_HIGHDMA;
13435                         err = pci_set_consistent_dma_mask(pdev,
13436                                                           persist_dma_mask);
13437                         if (err < 0) {
13438                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13439                                        "DMA for consistent allocations\n");
13440                                 goto err_out_iounmap;
13441                         }
13442                 }
13443         }
13444         if (err || dma_mask == DMA_BIT_MASK(32)) {
13445                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13446                 if (err) {
13447                         printk(KERN_ERR PFX "No usable DMA configuration, "
13448                                "aborting.\n");
13449                         goto err_out_iounmap;
13450                 }
13451         }
13452
13453         tg3_init_bufmgr_config(tp);
13454
13455         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13456                 tp->fw_needed = FIRMWARE_TG3;
13457
13458         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13459                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13460         }
13461         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13462             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13463             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13464             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13465             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13466                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13467         } else {
13468                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13469                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13470                         tp->fw_needed = FIRMWARE_TG3TSO5;
13471                 else
13472                         tp->fw_needed = FIRMWARE_TG3TSO;
13473         }
13474
13475         /* TSO is on by default on chips that support hardware TSO.
13476          * Firmware TSO on older chips gives lower performance, so it
13477          * is off by default, but can be enabled using ethtool.
13478          */
13479         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13480                 if (dev->features & NETIF_F_IP_CSUM)
13481                         dev->features |= NETIF_F_TSO;
13482                 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13483                     (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13484                         dev->features |= NETIF_F_TSO6;
13485                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13486                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13487                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13488                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13489                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13490                         dev->features |= NETIF_F_TSO_ECN;
13491         }
13492
13493
13494         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13495             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13496             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13497                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13498                 tp->rx_pending = 63;
13499         }
13500
13501         err = tg3_get_device_address(tp);
13502         if (err) {
13503                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13504                        "aborting.\n");
13505                 goto err_out_fw;
13506         }
13507
13508         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13509                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13510                 if (!tp->aperegs) {
13511                         printk(KERN_ERR PFX "Cannot map APE registers, "
13512                                "aborting.\n");
13513                         err = -ENOMEM;
13514                         goto err_out_fw;
13515                 }
13516
13517                 tg3_ape_lock_init(tp);
13518
13519                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13520                         tg3_read_dash_ver(tp);
13521         }
13522
13523         /*
13524          * Reset chip in case UNDI or EFI driver did not shutdown
13525          * DMA self test will enable WDMAC and we'll see (spurious)
13526          * pending DMA on the PCI bus at that point.
13527          */
13528         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13529             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13530                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13531                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13532         }
13533
13534         err = tg3_test_dma(tp);
13535         if (err) {
13536                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13537                 goto err_out_apeunmap;
13538         }
13539
13540         /* flow control autonegotiation is default behavior */
13541         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13542         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13543
13544         tg3_init_coal(tp);
13545
13546         pci_set_drvdata(pdev, dev);
13547
13548         err = register_netdev(dev);
13549         if (err) {
13550                 printk(KERN_ERR PFX "Cannot register net device, "
13551                        "aborting.\n");
13552                 goto err_out_apeunmap;
13553         }
13554
13555         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13556                dev->name,
13557                tp->board_part_number,
13558                tp->pci_chip_rev_id,
13559                tg3_bus_string(tp, str),
13560                dev->dev_addr);
13561
13562         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13563                 printk(KERN_INFO
13564                        "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13565                        tp->dev->name,
13566                        tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13567                        dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13568         else
13569                 printk(KERN_INFO
13570                        "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13571                        tp->dev->name, tg3_phy_string(tp),
13572                        ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13573                         ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13574                          "10/100/1000Base-T")),
13575                        (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13576
13577         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13578                dev->name,
13579                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13580                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13581                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13582                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13583                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13584         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13585                dev->name, tp->dma_rwctrl,
13586                (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13587                 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13588
13589         return 0;
13590
13591 err_out_apeunmap:
13592         if (tp->aperegs) {
13593                 iounmap(tp->aperegs);
13594                 tp->aperegs = NULL;
13595         }
13596
13597 err_out_fw:
13598         if (tp->fw)
13599                 release_firmware(tp->fw);
13600
13601 err_out_iounmap:
13602         if (tp->regs) {
13603                 iounmap(tp->regs);
13604                 tp->regs = NULL;
13605         }
13606
13607 err_out_free_dev:
13608         free_netdev(dev);
13609
13610 err_out_free_res:
13611         pci_release_regions(pdev);
13612
13613 err_out_disable_pdev:
13614         pci_disable_device(pdev);
13615         pci_set_drvdata(pdev, NULL);
13616         return err;
13617 }
13618
13619 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13620 {
13621         struct net_device *dev = pci_get_drvdata(pdev);
13622
13623         if (dev) {
13624                 struct tg3 *tp = netdev_priv(dev);
13625
13626                 if (tp->fw)
13627                         release_firmware(tp->fw);
13628
13629                 flush_scheduled_work();
13630
13631                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13632                         tg3_phy_fini(tp);
13633                         tg3_mdio_fini(tp);
13634                 }
13635
13636                 unregister_netdev(dev);
13637                 if (tp->aperegs) {
13638                         iounmap(tp->aperegs);
13639                         tp->aperegs = NULL;
13640                 }
13641                 if (tp->regs) {
13642                         iounmap(tp->regs);
13643                         tp->regs = NULL;
13644                 }
13645                 free_netdev(dev);
13646                 pci_release_regions(pdev);
13647                 pci_disable_device(pdev);
13648                 pci_set_drvdata(pdev, NULL);
13649         }
13650 }
13651
13652 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13653 {
13654         struct net_device *dev = pci_get_drvdata(pdev);
13655         struct tg3 *tp = netdev_priv(dev);
13656         pci_power_t target_state;
13657         int err;
13658
13659         /* PCI register 4 needs to be saved whether netif_running() or not.
13660          * MSI address and data need to be saved if using MSI and
13661          * netif_running().
13662          */
13663         pci_save_state(pdev);
13664
13665         if (!netif_running(dev))
13666                 return 0;
13667
13668         flush_scheduled_work();
13669         tg3_phy_stop(tp);
13670         tg3_netif_stop(tp);
13671
13672         del_timer_sync(&tp->timer);
13673
13674         tg3_full_lock(tp, 1);
13675         tg3_disable_ints(tp);
13676         tg3_full_unlock(tp);
13677
13678         netif_device_detach(dev);
13679
13680         tg3_full_lock(tp, 0);
13681         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13682         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13683         tg3_full_unlock(tp);
13684
13685         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13686
13687         err = tg3_set_power_state(tp, target_state);
13688         if (err) {
13689                 int err2;
13690
13691                 tg3_full_lock(tp, 0);
13692
13693                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13694                 err2 = tg3_restart_hw(tp, 1);
13695                 if (err2)
13696                         goto out;
13697
13698                 tp->timer.expires = jiffies + tp->timer_offset;
13699                 add_timer(&tp->timer);
13700
13701                 netif_device_attach(dev);
13702                 tg3_netif_start(tp);
13703
13704 out:
13705                 tg3_full_unlock(tp);
13706
13707                 if (!err2)
13708                         tg3_phy_start(tp);
13709         }
13710
13711         return err;
13712 }
13713
13714 static int tg3_resume(struct pci_dev *pdev)
13715 {
13716         struct net_device *dev = pci_get_drvdata(pdev);
13717         struct tg3 *tp = netdev_priv(dev);
13718         int err;
13719
13720         pci_restore_state(tp->pdev);
13721
13722         if (!netif_running(dev))
13723                 return 0;
13724
13725         err = tg3_set_power_state(tp, PCI_D0);
13726         if (err)
13727                 return err;
13728
13729         netif_device_attach(dev);
13730
13731         tg3_full_lock(tp, 0);
13732
13733         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13734         err = tg3_restart_hw(tp, 1);
13735         if (err)
13736                 goto out;
13737
13738         tp->timer.expires = jiffies + tp->timer_offset;
13739         add_timer(&tp->timer);
13740
13741         tg3_netif_start(tp);
13742
13743 out:
13744         tg3_full_unlock(tp);
13745
13746         if (!err)
13747                 tg3_phy_start(tp);
13748
13749         return err;
13750 }
13751
13752 static struct pci_driver tg3_driver = {
13753         .name           = DRV_MODULE_NAME,
13754         .id_table       = tg3_pci_tbl,
13755         .probe          = tg3_init_one,
13756         .remove         = __devexit_p(tg3_remove_one),
13757         .suspend        = tg3_suspend,
13758         .resume         = tg3_resume
13759 };
13760
13761 static int __init tg3_init(void)
13762 {
13763         return pci_register_driver(&tg3_driver);
13764 }
13765
13766 static void __exit tg3_cleanup(void)
13767 {
13768         pci_unregister_driver(&tg3_driver);
13769 }
13770
13771 module_init(tg3_init);
13772 module_exit(tg3_cleanup);