1 /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
2 * auto carrier detecting ethernet driver. Also known as the
3 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 * Copyright (C) 1996, 1998, 1999, 2002, 2003,
6 2006 David S. Miller (davem@davemloft.net)
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
23 #include <linux/slab.h>
24 #include <linux/string.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/ethtool.h>
28 #include <linux/mii.h>
29 #include <linux/crc32.h>
30 #include <linux/random.h>
31 #include <linux/errno.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
36 #include <linux/bitops.h>
37 #include <linux/dma-mapping.h>
39 #include <asm/system.h>
42 #include <asm/byteorder.h>
45 #include <asm/idprom.h>
47 #include <asm/openprom.h>
48 #include <asm/oplib.h>
50 #include <asm/auxio.h>
52 #include <asm/uaccess.h>
54 #include <asm/pgtable.h>
58 #include <linux/pci.h>
63 #define DRV_NAME "sunhme"
64 #define DRV_VERSION "3.00"
65 #define DRV_RELDATE "June 23, 2006"
66 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
68 static char version[] =
69 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
71 MODULE_VERSION(DRV_VERSION);
72 MODULE_AUTHOR(DRV_AUTHOR);
73 MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
74 MODULE_LICENSE("GPL");
76 static int macaddr[6];
78 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
79 module_param_array(macaddr, int, NULL, 0);
80 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
83 static struct quattro *qfe_sbus_list;
87 static struct quattro *qfe_pci_list;
97 struct hme_tx_logent {
101 #define TXLOG_ACTION_IRQ 0x01
102 #define TXLOG_ACTION_TXMIT 0x02
103 #define TXLOG_ACTION_TBUSY 0x04
104 #define TXLOG_ACTION_NBUFS 0x08
107 #define TX_LOG_LEN 128
108 static struct hme_tx_logent tx_log[TX_LOG_LEN];
109 static int txlog_cur_entry;
110 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
112 struct hme_tx_logent *tlp;
115 local_irq_save(flags);
116 tlp = &tx_log[txlog_cur_entry];
117 tlp->tstamp = (unsigned int)jiffies;
118 tlp->tx_new = hp->tx_new;
119 tlp->tx_old = hp->tx_old;
122 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
123 local_irq_restore(flags);
125 static __inline__ void tx_dump_log(void)
129 this = txlog_cur_entry;
130 for (i = 0; i < TX_LOG_LEN; i++) {
131 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
133 tx_log[this].tx_new, tx_log[this].tx_old,
134 tx_log[this].action, tx_log[this].status);
135 this = (this + 1) & (TX_LOG_LEN - 1);
138 static __inline__ void tx_dump_ring(struct happy_meal *hp)
140 struct hmeal_init_block *hb = hp->happy_block;
141 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
144 for (i = 0; i < TX_RING_SIZE; i+=4) {
145 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
147 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
148 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
149 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
150 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
154 #define tx_add_log(hp, a, s) do { } while(0)
155 #define tx_dump_log() do { } while(0)
156 #define tx_dump_ring(hp) do { } while(0)
160 #define HMD(x) printk x
165 /* #define AUTO_SWITCH_DEBUG */
167 #ifdef AUTO_SWITCH_DEBUG
168 #define ASD(x) printk x
173 #define DEFAULT_IPG0 16 /* For lance-mode only */
174 #define DEFAULT_IPG1 8 /* For all modes */
175 #define DEFAULT_IPG2 4 /* For all modes */
176 #define DEFAULT_JAMSIZE 4 /* Toe jam */
178 /* NOTE: In the descriptor writes one _must_ write the address
179 * member _first_. The card must not be allowed to see
180 * the updated descriptor flags until the address is
181 * correct. I've added a write memory barrier between
182 * the two stores so that I can sleep well at night... -DaveM
185 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
186 static void sbus_hme_write32(void __iomem *reg, u32 val)
188 sbus_writel(val, reg);
191 static u32 sbus_hme_read32(void __iomem *reg)
193 return sbus_readl(reg);
196 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
198 rxd->rx_addr = (__force hme32)addr;
200 rxd->rx_flags = (__force hme32)flags;
203 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
205 txd->tx_addr = (__force hme32)addr;
207 txd->tx_flags = (__force hme32)flags;
210 static u32 sbus_hme_read_desc32(hme32 *p)
212 return (__force u32)*p;
215 static void pci_hme_write32(void __iomem *reg, u32 val)
220 static u32 pci_hme_read32(void __iomem *reg)
225 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
227 rxd->rx_addr = (__force hme32)cpu_to_le32(addr);
229 rxd->rx_flags = (__force hme32)cpu_to_le32(flags);
232 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
234 txd->tx_addr = (__force hme32)cpu_to_le32(addr);
236 txd->tx_flags = (__force hme32)cpu_to_le32(flags);
239 static u32 pci_hme_read_desc32(hme32 *p)
241 return le32_to_cpup((__le32 *)p);
244 #define hme_write32(__hp, __reg, __val) \
245 ((__hp)->write32((__reg), (__val)))
246 #define hme_read32(__hp, __reg) \
247 ((__hp)->read32(__reg))
248 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
249 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
250 #define hme_write_txd(__hp, __txd, __flags, __addr) \
251 ((__hp)->write_txd((__txd), (__flags), (__addr)))
252 #define hme_read_desc32(__hp, __p) \
253 ((__hp)->read_desc32(__p))
254 #define hme_dma_map(__hp, __ptr, __size, __dir) \
255 ((__hp)->dma_map((__hp)->dma_dev, (__ptr), (__size), (__dir)))
256 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
257 ((__hp)->dma_unmap((__hp)->dma_dev, (__addr), (__size), (__dir)))
258 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
259 ((__hp)->dma_sync_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir)))
260 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
261 ((__hp)->dma_sync_for_device((__hp)->dma_dev, (__addr), (__size), (__dir)))
264 /* SBUS only compilation */
265 #define hme_write32(__hp, __reg, __val) \
266 sbus_writel((__val), (__reg))
267 #define hme_read32(__hp, __reg) \
269 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
270 do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \
272 (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \
274 #define hme_write_txd(__hp, __txd, __flags, __addr) \
275 do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \
277 (__txd)->tx_flags = (__force hme32)(u32)(__flags); \
279 #define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p))
280 #define hme_dma_map(__hp, __ptr, __size, __dir) \
281 dma_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
282 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
283 dma_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
284 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
285 dma_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
286 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
287 dma_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
289 /* PCI only compilation */
290 #define hme_write32(__hp, __reg, __val) \
291 writel((__val), (__reg))
292 #define hme_read32(__hp, __reg) \
294 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
295 do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \
297 (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \
299 #define hme_write_txd(__hp, __txd, __flags, __addr) \
300 do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \
302 (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \
304 static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
306 return le32_to_cpup((__le32 *)p);
308 #define hme_dma_map(__hp, __ptr, __size, __dir) \
309 pci_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
310 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
311 pci_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
312 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
313 pci_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
314 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
315 pci_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
320 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
321 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
323 hme_write32(hp, tregs + TCVR_BBDATA, bit);
324 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
325 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
329 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
333 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
334 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
335 ret = hme_read32(hp, tregs + TCVR_CFG);
337 ret &= TCV_CFG_MDIO0;
339 ret &= TCV_CFG_MDIO1;
345 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
349 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
351 retval = hme_read32(hp, tregs + TCVR_CFG);
353 retval &= TCV_CFG_MDIO0;
355 retval &= TCV_CFG_MDIO1;
356 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
361 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
363 static int happy_meal_bb_read(struct happy_meal *hp,
364 void __iomem *tregs, int reg)
370 ASD(("happy_meal_bb_read: reg=%d ", reg));
372 /* Enable the MIF BitBang outputs. */
373 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
375 /* Force BitBang into the idle state. */
376 for (i = 0; i < 32; i++)
377 BB_PUT_BIT(hp, tregs, 1);
379 /* Give it the read sequence. */
380 BB_PUT_BIT(hp, tregs, 0);
381 BB_PUT_BIT(hp, tregs, 1);
382 BB_PUT_BIT(hp, tregs, 1);
383 BB_PUT_BIT(hp, tregs, 0);
385 /* Give it the PHY address. */
386 tmp = hp->paddr & 0xff;
387 for (i = 4; i >= 0; i--)
388 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
390 /* Tell it what register we want to read. */
392 for (i = 4; i >= 0; i--)
393 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
395 /* Close down the MIF BitBang outputs. */
396 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
398 /* Now read in the value. */
399 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
400 for (i = 15; i >= 0; i--)
401 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
402 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
403 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
404 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
405 ASD(("value=%x\n", retval));
409 static void happy_meal_bb_write(struct happy_meal *hp,
410 void __iomem *tregs, int reg,
411 unsigned short value)
416 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
418 /* Enable the MIF BitBang outputs. */
419 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
421 /* Force BitBang into the idle state. */
422 for (i = 0; i < 32; i++)
423 BB_PUT_BIT(hp, tregs, 1);
425 /* Give it write sequence. */
426 BB_PUT_BIT(hp, tregs, 0);
427 BB_PUT_BIT(hp, tregs, 1);
428 BB_PUT_BIT(hp, tregs, 0);
429 BB_PUT_BIT(hp, tregs, 1);
431 /* Give it the PHY address. */
432 tmp = (hp->paddr & 0xff);
433 for (i = 4; i >= 0; i--)
434 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
436 /* Tell it what register we will be writing. */
438 for (i = 4; i >= 0; i--)
439 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
441 /* Tell it to become ready for the bits. */
442 BB_PUT_BIT(hp, tregs, 1);
443 BB_PUT_BIT(hp, tregs, 0);
445 for (i = 15; i >= 0; i--)
446 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
448 /* Close down the MIF BitBang outputs. */
449 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
452 #define TCVR_READ_TRIES 16
454 static int happy_meal_tcvr_read(struct happy_meal *hp,
455 void __iomem *tregs, int reg)
457 int tries = TCVR_READ_TRIES;
460 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
461 if (hp->tcvr_type == none) {
462 ASD(("no transceiver, value=TCVR_FAILURE\n"));
466 if (!(hp->happy_flags & HFLAG_FENABLE)) {
467 ASD(("doing bit bang\n"));
468 return happy_meal_bb_read(hp, tregs, reg);
471 hme_write32(hp, tregs + TCVR_FRAME,
472 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
473 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
476 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
479 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
480 ASD(("value=%04x\n", retval));
484 #define TCVR_WRITE_TRIES 16
486 static void happy_meal_tcvr_write(struct happy_meal *hp,
487 void __iomem *tregs, int reg,
488 unsigned short value)
490 int tries = TCVR_WRITE_TRIES;
492 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
494 /* Welcome to Sun Microsystems, can I take your order please? */
495 if (!(hp->happy_flags & HFLAG_FENABLE)) {
496 happy_meal_bb_write(hp, tregs, reg, value);
500 /* Would you like fries with that? */
501 hme_write32(hp, tregs + TCVR_FRAME,
502 (FRAME_WRITE | (hp->paddr << 23) |
503 ((reg & 0xff) << 18) | (value & 0xffff)));
504 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
509 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
511 /* Fifty-two cents is your change, have a nice day. */
514 /* Auto negotiation. The scheme is very simple. We have a timer routine
515 * that keeps watching the auto negotiation process as it progresses.
516 * The DP83840 is first told to start doing it's thing, we set up the time
517 * and place the timer state machine in it's initial state.
519 * Here the timer peeks at the DP83840 status registers at each click to see
520 * if the auto negotiation has completed, we assume here that the DP83840 PHY
521 * will time out at some point and just tell us what (didn't) happen. For
522 * complete coverage we only allow so many of the ticks at this level to run,
523 * when this has expired we print a warning message and try another strategy.
524 * This "other" strategy is to force the interface into various speed/duplex
525 * configurations and we stop when we see a link-up condition before the
526 * maximum number of "peek" ticks have occurred.
528 * Once a valid link status has been detected we configure the BigMAC and
529 * the rest of the Happy Meal to speak the most efficient protocol we could
530 * get a clean link for. The priority for link configurations, highest first
532 * 100 Base-T Full Duplex
533 * 100 Base-T Half Duplex
534 * 10 Base-T Full Duplex
535 * 10 Base-T Half Duplex
537 * We start a new timer now, after a successful auto negotiation status has
538 * been detected. This timer just waits for the link-up bit to get set in
539 * the BMCR of the DP83840. When this occurs we print a kernel log message
540 * describing the link type in use and the fact that it is up.
542 * If a fatal error of some sort is signalled and detected in the interrupt
543 * service routine, and the chip is reset, or the link is ifconfig'd down
544 * and then back up, this entire process repeats itself all over again.
546 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
548 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
550 /* Downgrade from full to half duplex. Only possible
553 if (hp->sw_bmcr & BMCR_FULLDPLX) {
554 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
555 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
559 /* Downgrade from 100 to 10. */
560 if (hp->sw_bmcr & BMCR_SPEED100) {
561 hp->sw_bmcr &= ~(BMCR_SPEED100);
562 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
566 /* We've tried everything. */
570 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
572 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
573 if (hp->tcvr_type == external)
577 printk("transceiver at ");
578 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
579 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
580 if (hp->sw_lpa & LPA_100FULL)
581 printk("100Mb/s, Full Duplex.\n");
583 printk("100Mb/s, Half Duplex.\n");
585 if (hp->sw_lpa & LPA_10FULL)
586 printk("10Mb/s, Full Duplex.\n");
588 printk("10Mb/s, Half Duplex.\n");
592 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
594 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
595 if (hp->tcvr_type == external)
599 printk("transceiver at ");
600 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
601 if (hp->sw_bmcr & BMCR_SPEED100)
605 if (hp->sw_bmcr & BMCR_FULLDPLX)
606 printk("Full Duplex.\n");
608 printk("Half Duplex.\n");
611 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
615 /* All we care about is making sure the bigmac tx_cfg has a
616 * proper duplex setting.
618 if (hp->timer_state == arbwait) {
619 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
620 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
622 if (hp->sw_lpa & LPA_100FULL)
624 else if (hp->sw_lpa & LPA_100HALF)
626 else if (hp->sw_lpa & LPA_10FULL)
631 /* Forcing a link mode. */
632 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
633 if (hp->sw_bmcr & BMCR_FULLDPLX)
639 /* Before changing other bits in the tx_cfg register, and in
640 * general any of other the TX config registers too, you
643 * 2) Poll with reads until that bit reads back as zero
644 * 3) Make TX configuration changes
645 * 4) Set Enable once more
647 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
648 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
649 ~(BIGMAC_TXCFG_ENABLE));
650 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
653 hp->happy_flags |= HFLAG_FULL;
654 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
655 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
656 BIGMAC_TXCFG_FULLDPLX);
658 hp->happy_flags &= ~(HFLAG_FULL);
659 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
660 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
661 ~(BIGMAC_TXCFG_FULLDPLX));
663 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
664 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
665 BIGMAC_TXCFG_ENABLE);
671 static int happy_meal_init(struct happy_meal *hp);
673 static int is_lucent_phy(struct happy_meal *hp)
675 void __iomem *tregs = hp->tcvregs;
676 unsigned short mr2, mr3;
679 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
680 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
681 if ((mr2 & 0xffff) == 0x0180 &&
682 ((mr3 & 0xffff) >> 10) == 0x1d)
688 static void happy_meal_timer(unsigned long data)
690 struct happy_meal *hp = (struct happy_meal *) data;
691 void __iomem *tregs = hp->tcvregs;
692 int restart_timer = 0;
694 spin_lock_irq(&hp->happy_lock);
697 switch(hp->timer_state) {
699 /* Only allow for 5 ticks, thats 10 seconds and much too
700 * long to wait for arbitration to complete.
702 if (hp->timer_ticks >= 10) {
703 /* Enter force mode. */
705 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
706 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
708 hp->sw_bmcr = BMCR_SPEED100;
709 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
711 if (!is_lucent_phy(hp)) {
712 /* OK, seems we need do disable the transceiver for the first
713 * tick to make sure we get an accurate link state at the
716 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
717 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
718 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
720 hp->timer_state = ltrywait;
724 /* Anything interesting happen? */
725 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
726 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
729 /* Just what we've been waiting for... */
730 ret = set_happy_link_modes(hp, tregs);
732 /* Ooops, something bad happened, go to force
735 * XXX Broken hubs which don't support 802.3u
736 * XXX auto-negotiation make this happen as well.
741 /* Success, at least so far, advance our state engine. */
742 hp->timer_state = lupwait;
751 /* Auto negotiation was successful and we are awaiting a
752 * link up status. I have decided to let this timer run
753 * forever until some sort of error is signalled, reporting
754 * a message to the user at 10 second intervals.
756 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
757 if (hp->sw_bmsr & BMSR_LSTATUS) {
758 /* Wheee, it's up, display the link mode in use and put
759 * the timer to sleep.
761 display_link_mode(hp, tregs);
762 hp->timer_state = asleep;
765 if (hp->timer_ticks >= 10) {
766 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
767 "not completely up.\n", hp->dev->name);
777 /* Making the timeout here too long can make it take
778 * annoyingly long to attempt all of the link mode
779 * permutations, but then again this is essentially
780 * error recovery code for the most part.
782 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
783 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
784 if (hp->timer_ticks == 1) {
785 if (!is_lucent_phy(hp)) {
786 /* Re-enable transceiver, we'll re-enable the transceiver next
787 * tick, then check link state on the following tick.
789 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
790 happy_meal_tcvr_write(hp, tregs,
791 DP83840_CSCONFIG, hp->sw_csconfig);
796 if (hp->timer_ticks == 2) {
797 if (!is_lucent_phy(hp)) {
798 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
799 happy_meal_tcvr_write(hp, tregs,
800 DP83840_CSCONFIG, hp->sw_csconfig);
805 if (hp->sw_bmsr & BMSR_LSTATUS) {
806 /* Force mode selection success. */
807 display_forced_link_mode(hp, tregs);
808 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
809 hp->timer_state = asleep;
812 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
815 ret = try_next_permutation(hp, tregs);
817 /* Aieee, tried them all, reset the
818 * chip and try all over again.
821 /* Let the user know... */
822 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
825 ret = happy_meal_init(hp);
828 printk(KERN_ERR "%s: Error, cannot re-init the "
829 "Happy Meal.\n", hp->dev->name);
833 if (!is_lucent_phy(hp)) {
834 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
836 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
837 happy_meal_tcvr_write(hp, tregs,
838 DP83840_CSCONFIG, hp->sw_csconfig);
850 /* Can't happens.... */
851 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
855 hp->timer_state = asleep; /* foo on you */
860 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
861 add_timer(&hp->happy_timer);
865 spin_unlock_irq(&hp->happy_lock);
868 #define TX_RESET_TRIES 32
869 #define RX_RESET_TRIES 32
871 /* hp->happy_lock must be held */
872 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
874 int tries = TX_RESET_TRIES;
876 HMD(("happy_meal_tx_reset: reset, "));
878 /* Would you like to try our SMCC Delux? */
879 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
880 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
883 /* Lettuce, tomato, buggy hardware (no extra charge)? */
885 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
891 /* hp->happy_lock must be held */
892 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
894 int tries = RX_RESET_TRIES;
896 HMD(("happy_meal_rx_reset: reset, "));
898 /* We have a special on GNU/Viking hardware bugs today. */
899 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
900 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
903 /* Will that be all? */
905 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
907 /* Don't forget your vik_1137125_wa. Have a nice day. */
911 #define STOP_TRIES 16
913 /* hp->happy_lock must be held */
914 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
916 int tries = STOP_TRIES;
918 HMD(("happy_meal_stop: reset, "));
920 /* We're consolidating our STB products, it's your lucky day. */
921 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
922 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
925 /* Come back next week when we are "Sun Microelectronics". */
927 printk(KERN_ERR "happy meal: Fry guys.");
929 /* Remember: "Different name, same old buggy as shit hardware." */
933 /* hp->happy_lock must be held */
934 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
936 struct net_device_stats *stats = &hp->net_stats;
938 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
939 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
941 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
942 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
944 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
945 hme_write32(hp, bregs + BMAC_GLECTR, 0);
947 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
950 (hme_read32(hp, bregs + BMAC_EXCTR) +
951 hme_read32(hp, bregs + BMAC_LTCTR));
952 hme_write32(hp, bregs + BMAC_EXCTR, 0);
953 hme_write32(hp, bregs + BMAC_LTCTR, 0);
956 /* hp->happy_lock must be held */
957 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
959 ASD(("happy_meal_poll_stop: "));
961 /* If polling disabled or not polling already, nothing to do. */
962 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
963 (HFLAG_POLLENABLE | HFLAG_POLL)) {
964 HMD(("not polling, return\n"));
968 /* Shut up the MIF. */
969 ASD(("were polling, mif ints off, "));
970 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
972 /* Turn off polling. */
973 ASD(("polling off, "));
974 hme_write32(hp, tregs + TCVR_CFG,
975 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
977 /* We are no longer polling. */
978 hp->happy_flags &= ~(HFLAG_POLL);
980 /* Let the bits set. */
985 /* Only Sun can take such nice parts and fuck up the programming interface
986 * like this. Good job guys...
988 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
989 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
991 /* hp->happy_lock must be held */
992 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
995 int result, tries = TCVR_RESET_TRIES;
997 tconfig = hme_read32(hp, tregs + TCVR_CFG);
998 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
999 if (hp->tcvr_type == external) {
1001 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1002 hp->tcvr_type = internal;
1003 hp->paddr = TCV_PADDR_ITX;
1005 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1006 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1007 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1008 if (result == TCVR_FAILURE) {
1009 ASD(("phyread_fail>\n"));
1012 ASD(("phyread_ok,PSELECT>"));
1013 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1014 hp->tcvr_type = external;
1015 hp->paddr = TCV_PADDR_ETX;
1017 if (tconfig & TCV_CFG_MDIO1) {
1018 ASD(("internal<PSELECT,"));
1019 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1021 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1022 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1023 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1024 if (result == TCVR_FAILURE) {
1025 ASD(("phyread_fail>\n"));
1028 ASD(("phyread_ok,~PSELECT>"));
1029 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1030 hp->tcvr_type = internal;
1031 hp->paddr = TCV_PADDR_ITX;
1035 ASD(("BMCR_RESET "));
1036 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1039 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1040 if (result == TCVR_FAILURE)
1042 hp->sw_bmcr = result;
1043 if (!(result & BMCR_RESET))
1048 ASD(("BMCR RESET FAILED!\n"));
1051 ASD(("RESET_OK\n"));
1053 /* Get fresh copies of the PHY registers. */
1054 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1055 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1056 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1057 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1060 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1061 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1063 tries = TCVR_UNISOLATE_TRIES;
1065 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1066 if (result == TCVR_FAILURE)
1068 if (!(result & BMCR_ISOLATE))
1073 ASD((" FAILED!\n"));
1076 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1077 if (!is_lucent_phy(hp)) {
1078 result = happy_meal_tcvr_read(hp, tregs,
1080 happy_meal_tcvr_write(hp, tregs,
1081 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1086 /* Figure out whether we have an internal or external transceiver.
1088 * hp->happy_lock must be held
1090 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1092 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1094 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1095 if (hp->happy_flags & HFLAG_POLL) {
1096 /* If we are polling, we must stop to get the transceiver type. */
1097 ASD(("<polling> "));
1098 if (hp->tcvr_type == internal) {
1099 if (tconfig & TCV_CFG_MDIO1) {
1100 ASD(("<internal> <poll stop> "));
1101 happy_meal_poll_stop(hp, tregs);
1102 hp->paddr = TCV_PADDR_ETX;
1103 hp->tcvr_type = external;
1104 ASD(("<external>\n"));
1105 tconfig &= ~(TCV_CFG_PENABLE);
1106 tconfig |= TCV_CFG_PSELECT;
1107 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1110 if (hp->tcvr_type == external) {
1111 ASD(("<external> "));
1112 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1113 ASD(("<poll stop> "));
1114 happy_meal_poll_stop(hp, tregs);
1115 hp->paddr = TCV_PADDR_ITX;
1116 hp->tcvr_type = internal;
1117 ASD(("<internal>\n"));
1118 hme_write32(hp, tregs + TCVR_CFG,
1119 hme_read32(hp, tregs + TCVR_CFG) &
1120 ~(TCV_CFG_PSELECT));
1128 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1130 /* Else we can just work off of the MDIO bits. */
1131 ASD(("<not polling> "));
1132 if (reread & TCV_CFG_MDIO1) {
1133 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1134 hp->paddr = TCV_PADDR_ETX;
1135 hp->tcvr_type = external;
1136 ASD(("<external>\n"));
1138 if (reread & TCV_CFG_MDIO0) {
1139 hme_write32(hp, tregs + TCVR_CFG,
1140 tconfig & ~(TCV_CFG_PSELECT));
1141 hp->paddr = TCV_PADDR_ITX;
1142 hp->tcvr_type = internal;
1143 ASD(("<internal>\n"));
1145 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1146 hp->tcvr_type = none; /* Grrr... */
1153 /* The receive ring buffers are a bit tricky to get right. Here goes...
1155 * The buffers we dma into must be 64 byte aligned. So we use a special
1156 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1159 * We use skb_reserve() to align the data block we get in the skb. We
1160 * also program the etxregs->cfg register to use an offset of 2. This
1161 * imperical constant plus the ethernet header size will always leave
1162 * us with a nicely aligned ip header once we pass things up to the
1165 * The numbers work out to:
1167 * Max ethernet frame size 1518
1168 * Ethernet header size 14
1169 * Happy Meal base offset 2
1171 * Say a skb data area is at 0xf001b010, and its size alloced is
1172 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1174 * First our alloc_skb() routine aligns the data base to a 64 byte
1175 * boundary. We now have 0xf001b040 as our skb data address. We
1176 * plug this into the receive descriptor address.
1178 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1179 * So now the data we will end up looking at starts at 0xf001b042. When
1180 * the packet arrives, we will check out the size received and subtract
1181 * this from the skb->length. Then we just pass the packet up to the
1182 * protocols as is, and allocate a new skb to replace this slot we have
1183 * just received from.
1185 * The ethernet layer will strip the ether header from the front of the
1186 * skb we just sent to it, this leaves us with the ip header sitting
1187 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1188 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1189 * bit checksum is obtained from the low bits of the receive descriptor
1192 * skb->csum = rxd->rx_flags & 0xffff;
1193 * skb->ip_summed = CHECKSUM_COMPLETE;
1195 * before sending off the skb to the protocols, and we are good as gold.
1197 static void happy_meal_clean_rings(struct happy_meal *hp)
1201 for (i = 0; i < RX_RING_SIZE; i++) {
1202 if (hp->rx_skbs[i] != NULL) {
1203 struct sk_buff *skb = hp->rx_skbs[i];
1204 struct happy_meal_rxd *rxd;
1207 rxd = &hp->happy_block->happy_meal_rxd[i];
1208 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1209 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
1210 dev_kfree_skb_any(skb);
1211 hp->rx_skbs[i] = NULL;
1215 for (i = 0; i < TX_RING_SIZE; i++) {
1216 if (hp->tx_skbs[i] != NULL) {
1217 struct sk_buff *skb = hp->tx_skbs[i];
1218 struct happy_meal_txd *txd;
1222 hp->tx_skbs[i] = NULL;
1224 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1225 txd = &hp->happy_block->happy_meal_txd[i];
1226 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1227 hme_dma_unmap(hp, dma_addr,
1228 (hme_read_desc32(hp, &txd->tx_flags)
1232 if (frag != skb_shinfo(skb)->nr_frags)
1236 dev_kfree_skb_any(skb);
1241 /* hp->happy_lock must be held */
1242 static void happy_meal_init_rings(struct happy_meal *hp)
1244 struct hmeal_init_block *hb = hp->happy_block;
1245 struct net_device *dev = hp->dev;
1248 HMD(("happy_meal_init_rings: counters to zero, "));
1249 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1251 /* Free any skippy bufs left around in the rings. */
1253 happy_meal_clean_rings(hp);
1255 /* Now get new skippy bufs for the receive ring. */
1256 HMD(("init rxring, "));
1257 for (i = 0; i < RX_RING_SIZE; i++) {
1258 struct sk_buff *skb;
1260 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1262 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1265 hp->rx_skbs[i] = skb;
1268 /* Because we reserve afterwards. */
1269 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
1270 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1271 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1272 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE));
1273 skb_reserve(skb, RX_OFFSET);
1276 HMD(("init txring, "));
1277 for (i = 0; i < TX_RING_SIZE; i++)
1278 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1283 /* hp->happy_lock must be held */
1284 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1285 void __iomem *tregs,
1286 struct ethtool_cmd *ep)
1290 /* Read all of the registers we are interested in now. */
1291 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1292 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1293 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1294 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1296 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1298 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1299 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1300 /* Advertise everything we can support. */
1301 if (hp->sw_bmsr & BMSR_10HALF)
1302 hp->sw_advertise |= (ADVERTISE_10HALF);
1304 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1306 if (hp->sw_bmsr & BMSR_10FULL)
1307 hp->sw_advertise |= (ADVERTISE_10FULL);
1309 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1310 if (hp->sw_bmsr & BMSR_100HALF)
1311 hp->sw_advertise |= (ADVERTISE_100HALF);
1313 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1314 if (hp->sw_bmsr & BMSR_100FULL)
1315 hp->sw_advertise |= (ADVERTISE_100FULL);
1317 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1318 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1320 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1321 * XXX and this is because the DP83840 does not support it, changes
1322 * XXX would need to be made to the tx/rx logic in the driver as well
1323 * XXX so I completely skip checking for it in the BMSR for now.
1326 #ifdef AUTO_SWITCH_DEBUG
1327 ASD(("%s: Advertising [ ", hp->dev->name));
1328 if (hp->sw_advertise & ADVERTISE_10HALF)
1330 if (hp->sw_advertise & ADVERTISE_10FULL)
1332 if (hp->sw_advertise & ADVERTISE_100HALF)
1334 if (hp->sw_advertise & ADVERTISE_100FULL)
1338 /* Enable Auto-Negotiation, this is usually on already... */
1339 hp->sw_bmcr |= BMCR_ANENABLE;
1340 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1342 /* Restart it to make sure it is going. */
1343 hp->sw_bmcr |= BMCR_ANRESTART;
1344 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1346 /* BMCR_ANRESTART self clears when the process has begun. */
1348 timeout = 64; /* More than enough. */
1350 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1351 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1352 break; /* got it. */
1356 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1357 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1358 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1362 hp->timer_state = arbwait;
1366 /* Force the link up, trying first a particular mode.
1367 * Either we are here at the request of ethtool or
1368 * because the Happy Meal would not start to autoneg.
1371 /* Disable auto-negotiation in BMCR, enable the duplex and
1372 * speed setting, init the timer state machine, and fire it off.
1374 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1375 hp->sw_bmcr = BMCR_SPEED100;
1377 if (ep->speed == SPEED_100)
1378 hp->sw_bmcr = BMCR_SPEED100;
1381 if (ep->duplex == DUPLEX_FULL)
1382 hp->sw_bmcr |= BMCR_FULLDPLX;
1384 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1386 if (!is_lucent_phy(hp)) {
1387 /* OK, seems we need do disable the transceiver for the first
1388 * tick to make sure we get an accurate link state at the
1391 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1393 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1394 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1397 hp->timer_state = ltrywait;
1400 hp->timer_ticks = 0;
1401 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1402 hp->happy_timer.data = (unsigned long) hp;
1403 hp->happy_timer.function = &happy_meal_timer;
1404 add_timer(&hp->happy_timer);
1407 /* hp->happy_lock must be held */
1408 static int happy_meal_init(struct happy_meal *hp)
1410 void __iomem *gregs = hp->gregs;
1411 void __iomem *etxregs = hp->etxregs;
1412 void __iomem *erxregs = hp->erxregs;
1413 void __iomem *bregs = hp->bigmacregs;
1414 void __iomem *tregs = hp->tcvregs;
1416 unsigned char *e = &hp->dev->dev_addr[0];
1418 /* If auto-negotiation timer is running, kill it. */
1419 del_timer(&hp->happy_timer);
1421 HMD(("happy_meal_init: happy_flags[%08x] ",
1423 if (!(hp->happy_flags & HFLAG_INIT)) {
1424 HMD(("set HFLAG_INIT, "));
1425 hp->happy_flags |= HFLAG_INIT;
1426 happy_meal_get_counters(hp, bregs);
1430 HMD(("to happy_meal_poll_stop\n"));
1431 happy_meal_poll_stop(hp, tregs);
1433 /* Stop transmitter and receiver. */
1434 HMD(("happy_meal_init: to happy_meal_stop\n"));
1435 happy_meal_stop(hp, gregs);
1437 /* Alloc and reset the tx/rx descriptor chains. */
1438 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1439 happy_meal_init_rings(hp);
1441 /* Shut up the MIF. */
1442 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1443 hme_read32(hp, tregs + TCVR_IMASK)));
1444 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1446 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1447 if (hp->happy_flags & HFLAG_FENABLE) {
1448 HMD(("use frame old[%08x], ",
1449 hme_read32(hp, tregs + TCVR_CFG)));
1450 hme_write32(hp, tregs + TCVR_CFG,
1451 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1453 HMD(("use bitbang old[%08x], ",
1454 hme_read32(hp, tregs + TCVR_CFG)));
1455 hme_write32(hp, tregs + TCVR_CFG,
1456 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1459 /* Check the state of the transceiver. */
1460 HMD(("to happy_meal_transceiver_check\n"));
1461 happy_meal_transceiver_check(hp, tregs);
1463 /* Put the Big Mac into a sane state. */
1464 HMD(("happy_meal_init: "));
1465 switch(hp->tcvr_type) {
1467 /* Cannot operate if we don't know the transceiver type! */
1468 HMD(("AAIEEE no transceiver type, EAGAIN"));
1472 /* Using the MII buffers. */
1473 HMD(("internal, using MII, "));
1474 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1478 /* Not using the MII, disable it. */
1479 HMD(("external, disable MII, "));
1480 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1484 if (happy_meal_tcvr_reset(hp, tregs))
1487 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1488 HMD(("tx/rx reset, "));
1489 happy_meal_tx_reset(hp, bregs);
1490 happy_meal_rx_reset(hp, bregs);
1492 /* Set jam size and inter-packet gaps to reasonable defaults. */
1493 HMD(("jsize/ipg1/ipg2, "));
1494 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1495 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1496 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1498 /* Load up the MAC address and random seed. */
1499 HMD(("rseed/macaddr, "));
1501 /* The docs recommend to use the 10LSB of our MAC here. */
1502 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1504 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1505 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1506 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1509 if ((hp->dev->flags & IFF_ALLMULTI) ||
1510 (hp->dev->mc_count > 64)) {
1511 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1512 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1513 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1514 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1515 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1517 struct dev_mc_list *dmi = hp->dev->mc_list;
1522 for (i = 0; i < 4; i++)
1525 for (i = 0; i < hp->dev->mc_count; i++) {
1526 addrs = dmi->dmi_addr;
1532 crc = ether_crc_le(6, addrs);
1534 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1536 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1537 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1538 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1539 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1541 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1542 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1543 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1544 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1547 /* Set the RX and TX ring ptrs. */
1548 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1549 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1550 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1551 hme_write32(hp, erxregs + ERX_RING,
1552 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1553 hme_write32(hp, etxregs + ETX_RING,
1554 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1556 /* Parity issues in the ERX unit of some HME revisions can cause some
1557 * registers to not be written unless their parity is even. Detect such
1558 * lost writes and simply rewrite with a low bit set (which will be ignored
1559 * since the rxring needs to be 2K aligned).
1561 if (hme_read32(hp, erxregs + ERX_RING) !=
1562 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1563 hme_write32(hp, erxregs + ERX_RING,
1564 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1567 /* Set the supported burst sizes. */
1568 HMD(("happy_meal_init: old[%08x] bursts<",
1569 hme_read32(hp, gregs + GREG_CFG)));
1571 #ifndef CONFIG_SPARC
1572 /* It is always PCI and can handle 64byte bursts. */
1573 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1575 if ((hp->happy_bursts & DMA_BURST64) &&
1576 ((hp->happy_flags & HFLAG_PCI) != 0
1578 || sbus_can_burst64()
1581 u32 gcfg = GREG_CFG_BURST64;
1583 /* I have no idea if I should set the extended
1584 * transfer mode bit for Cheerio, so for now I
1588 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1589 struct sbus_dev *sdev = hp->happy_dev;
1590 if (sbus_can_dma_64bit()) {
1591 sbus_set_sbus64(&sdev->ofdev.dev,
1593 gcfg |= GREG_CFG_64BIT;
1599 hme_write32(hp, gregs + GREG_CFG, gcfg);
1600 } else if (hp->happy_bursts & DMA_BURST32) {
1602 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1603 } else if (hp->happy_bursts & DMA_BURST16) {
1605 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1608 hme_write32(hp, gregs + GREG_CFG, 0);
1610 #endif /* CONFIG_SPARC */
1612 /* Turn off interrupts we do not want to hear. */
1613 HMD((", enable global interrupts, "));
1614 hme_write32(hp, gregs + GREG_IMASK,
1615 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1616 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1618 /* Set the transmit ring buffer size. */
1619 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1620 hme_read32(hp, etxregs + ETX_RSIZE)));
1621 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1623 /* Enable transmitter DVMA. */
1624 HMD(("tx dma enable old[%08x], ",
1625 hme_read32(hp, etxregs + ETX_CFG)));
1626 hme_write32(hp, etxregs + ETX_CFG,
1627 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1629 /* This chip really rots, for the receiver sometimes when you
1630 * write to its control registers not all the bits get there
1631 * properly. I cannot think of a sane way to provide complete
1632 * coverage for this hardware bug yet.
1634 HMD(("erx regs bug old[%08x]\n",
1635 hme_read32(hp, erxregs + ERX_CFG)));
1636 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1637 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1638 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1639 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1640 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1641 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1642 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1643 /* XXX Should return failure here... */
1646 /* Enable Big Mac hash table filter. */
1647 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1648 hme_read32(hp, bregs + BMAC_RXCFG)));
1649 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1650 if (hp->dev->flags & IFF_PROMISC)
1651 rxcfg |= BIGMAC_RXCFG_PMISC;
1652 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1654 /* Let the bits settle in the chip. */
1657 /* Ok, configure the Big Mac transmitter. */
1658 HMD(("BIGMAC init, "));
1660 if (hp->happy_flags & HFLAG_FULL)
1661 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1663 /* Don't turn on the "don't give up" bit for now. It could cause hme
1664 * to deadlock with the PHY if a Jabber occurs.
1666 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1668 /* Give up after 16 TX attempts. */
1669 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1671 /* Enable the output drivers no matter what. */
1672 regtmp = BIGMAC_XCFG_ODENABLE;
1674 /* If card can do lance mode, enable it. */
1675 if (hp->happy_flags & HFLAG_LANCE)
1676 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1678 /* Disable the MII buffers if using external transceiver. */
1679 if (hp->tcvr_type == external)
1680 regtmp |= BIGMAC_XCFG_MIIDISAB;
1682 HMD(("XIF config old[%08x], ",
1683 hme_read32(hp, bregs + BMAC_XIFCFG)));
1684 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1686 /* Start things up. */
1687 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1688 hme_read32(hp, bregs + BMAC_TXCFG),
1689 hme_read32(hp, bregs + BMAC_RXCFG)));
1691 /* Set larger TX/RX size to allow for 802.1q */
1692 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1693 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1695 hme_write32(hp, bregs + BMAC_TXCFG,
1696 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1697 hme_write32(hp, bregs + BMAC_RXCFG,
1698 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1700 /* Get the autonegotiation started, and the watch timer ticking. */
1701 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1707 /* hp->happy_lock must be held */
1708 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1710 void __iomem *tregs = hp->tcvregs;
1711 void __iomem *bregs = hp->bigmacregs;
1712 void __iomem *gregs = hp->gregs;
1714 happy_meal_stop(hp, gregs);
1715 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1716 if (hp->happy_flags & HFLAG_FENABLE)
1717 hme_write32(hp, tregs + TCVR_CFG,
1718 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1720 hme_write32(hp, tregs + TCVR_CFG,
1721 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1722 happy_meal_transceiver_check(hp, tregs);
1723 switch(hp->tcvr_type) {
1727 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1730 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1733 if (happy_meal_tcvr_reset(hp, tregs))
1736 /* Latch PHY registers as of now. */
1737 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1738 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1740 /* Advertise everything we can support. */
1741 if (hp->sw_bmsr & BMSR_10HALF)
1742 hp->sw_advertise |= (ADVERTISE_10HALF);
1744 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1746 if (hp->sw_bmsr & BMSR_10FULL)
1747 hp->sw_advertise |= (ADVERTISE_10FULL);
1749 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1750 if (hp->sw_bmsr & BMSR_100HALF)
1751 hp->sw_advertise |= (ADVERTISE_100HALF);
1753 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1754 if (hp->sw_bmsr & BMSR_100FULL)
1755 hp->sw_advertise |= (ADVERTISE_100FULL);
1757 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1759 /* Update the PHY advertisement register. */
1760 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1763 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1764 * the hardware, so we cannot re-read it and get a correct value.
1766 * hp->happy_lock must be held
1768 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1772 /* Only print messages for non-counter related interrupts. */
1773 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1774 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1775 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1776 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1777 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1779 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1780 hp->dev->name, status);
1782 if (status & GREG_STAT_RFIFOVF) {
1783 /* Receive FIFO overflow is harmless and the hardware will take
1784 care of it, just some packets are lost. Who cares. */
1785 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1788 if (status & GREG_STAT_STSTERR) {
1789 /* BigMAC SQE link test failed. */
1790 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1794 if (status & GREG_STAT_TFIFO_UND) {
1795 /* Transmit FIFO underrun, again DMA error likely. */
1796 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1801 if (status & GREG_STAT_MAXPKTERR) {
1802 /* Driver error, tried to transmit something larger
1803 * than ethernet max mtu.
1805 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1809 if (status & GREG_STAT_NORXD) {
1810 /* This is harmless, it just means the system is
1811 * quite loaded and the incoming packet rate was
1812 * faster than the interrupt handler could keep up
1815 printk(KERN_INFO "%s: Happy Meal out of receive "
1816 "descriptors, packet dropped.\n",
1820 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1821 /* All sorts of DMA receive errors. */
1822 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1823 if (status & GREG_STAT_RXERR)
1824 printk("GenericError ");
1825 if (status & GREG_STAT_RXPERR)
1826 printk("ParityError ");
1827 if (status & GREG_STAT_RXTERR)
1828 printk("RxTagBotch ");
1833 if (status & GREG_STAT_EOPERR) {
1834 /* Driver bug, didn't set EOP bit in tx descriptor given
1835 * to the happy meal.
1837 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1842 if (status & GREG_STAT_MIFIRQ) {
1843 /* MIF signalled an interrupt, were we polling it? */
1844 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1848 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1849 /* All sorts of transmit DMA errors. */
1850 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1851 if (status & GREG_STAT_TXEACK)
1852 printk("GenericError ");
1853 if (status & GREG_STAT_TXLERR)
1854 printk("LateError ");
1855 if (status & GREG_STAT_TXPERR)
1856 printk("ParityErro ");
1857 if (status & GREG_STAT_TXTERR)
1858 printk("TagBotch ");
1863 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1864 /* Bus or parity error when cpu accessed happy meal registers
1865 * or it's internal FIFO's. Should never see this.
1867 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1869 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1874 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1875 happy_meal_init(hp);
1881 /* hp->happy_lock must be held */
1882 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1884 void __iomem *tregs = hp->tcvregs;
1886 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1887 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1888 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1890 /* Use the fastest transmission protocol possible. */
1891 if (hp->sw_lpa & LPA_100FULL) {
1892 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1893 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1894 } else if (hp->sw_lpa & LPA_100HALF) {
1895 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1896 hp->sw_bmcr |= BMCR_SPEED100;
1897 } else if (hp->sw_lpa & LPA_10FULL) {
1898 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1899 hp->sw_bmcr |= BMCR_FULLDPLX;
1901 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1903 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1905 /* Finally stop polling and shut up the MIF. */
1906 happy_meal_poll_stop(hp, tregs);
1910 #define TXD(x) printk x
1915 /* hp->happy_lock must be held */
1916 static void happy_meal_tx(struct happy_meal *hp)
1918 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1919 struct happy_meal_txd *this;
1920 struct net_device *dev = hp->dev;
1925 while (elem != hp->tx_new) {
1926 struct sk_buff *skb;
1927 u32 flags, dma_addr, dma_len;
1930 TXD(("[%d]", elem));
1931 this = &txbase[elem];
1932 flags = hme_read_desc32(hp, &this->tx_flags);
1933 if (flags & TXFLAG_OWN)
1935 skb = hp->tx_skbs[elem];
1936 if (skb_shinfo(skb)->nr_frags) {
1939 last = elem + skb_shinfo(skb)->nr_frags;
1940 last &= (TX_RING_SIZE - 1);
1941 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1942 if (flags & TXFLAG_OWN)
1945 hp->tx_skbs[elem] = NULL;
1946 hp->net_stats.tx_bytes += skb->len;
1948 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1949 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1950 dma_len = hme_read_desc32(hp, &this->tx_flags);
1952 dma_len &= TXFLAG_SIZE;
1953 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TO_DEVICE);
1955 elem = NEXT_TX(elem);
1956 this = &txbase[elem];
1959 dev_kfree_skb_irq(skb);
1960 hp->net_stats.tx_packets++;
1965 if (netif_queue_stopped(dev) &&
1966 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1967 netif_wake_queue(dev);
1971 #define RXD(x) printk x
1976 /* Originally I used to handle the allocation failure by just giving back just
1977 * that one ring buffer to the happy meal. Problem is that usually when that
1978 * condition is triggered, the happy meal expects you to do something reasonable
1979 * with all of the packets it has DMA'd in. So now I just drop the entire
1980 * ring when we cannot get a new skb and give them all back to the happy meal,
1981 * maybe things will be "happier" now.
1983 * hp->happy_lock must be held
1985 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1987 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1988 struct happy_meal_rxd *this;
1989 int elem = hp->rx_new, drops = 0;
1993 this = &rxbase[elem];
1994 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1995 struct sk_buff *skb;
1996 int len = flags >> 16;
1997 u16 csum = flags & RXFLAG_CSUM;
1998 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2000 RXD(("[%d ", elem));
2002 /* Check for errors. */
2003 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2004 RXD(("ERR(%08x)]", flags));
2005 hp->net_stats.rx_errors++;
2007 hp->net_stats.rx_length_errors++;
2008 if (len & (RXFLAG_OVERFLOW >> 16)) {
2009 hp->net_stats.rx_over_errors++;
2010 hp->net_stats.rx_fifo_errors++;
2013 /* Return it to the Happy meal. */
2015 hp->net_stats.rx_dropped++;
2016 hme_write_rxd(hp, this,
2017 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2021 skb = hp->rx_skbs[elem];
2022 if (len > RX_COPY_THRESHOLD) {
2023 struct sk_buff *new_skb;
2025 /* Now refill the entry, if we can. */
2026 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2027 if (new_skb == NULL) {
2031 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
2032 hp->rx_skbs[elem] = new_skb;
2034 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
2035 hme_write_rxd(hp, this,
2036 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2037 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE));
2038 skb_reserve(new_skb, RX_OFFSET);
2040 /* Trim the original skb for the netif. */
2043 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2045 if (copy_skb == NULL) {
2050 skb_reserve(copy_skb, 2);
2051 skb_put(copy_skb, len);
2052 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROM_DEVICE);
2053 skb_copy_from_linear_data(skb, copy_skb->data, len);
2054 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROM_DEVICE);
2056 /* Reuse original ring buffer. */
2057 hme_write_rxd(hp, this,
2058 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2064 /* This card is _fucking_ hot... */
2065 skb->csum = csum_unfold(~(__force __sum16)htons(csum));
2066 skb->ip_summed = CHECKSUM_COMPLETE;
2068 RXD(("len=%d csum=%4x]", len, csum));
2069 skb->protocol = eth_type_trans(skb, dev);
2072 dev->last_rx = jiffies;
2073 hp->net_stats.rx_packets++;
2074 hp->net_stats.rx_bytes += len;
2076 elem = NEXT_RX(elem);
2077 this = &rxbase[elem];
2081 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2085 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
2087 struct net_device *dev = dev_id;
2088 struct happy_meal *hp = netdev_priv(dev);
2089 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2091 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2093 spin_lock(&hp->happy_lock);
2095 if (happy_status & GREG_STAT_ERRORS) {
2097 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2101 if (happy_status & GREG_STAT_MIFIRQ) {
2103 happy_meal_mif_interrupt(hp);
2106 if (happy_status & GREG_STAT_TXALL) {
2111 if (happy_status & GREG_STAT_RXTOHOST) {
2113 happy_meal_rx(hp, dev);
2118 spin_unlock(&hp->happy_lock);
2124 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
2126 struct quattro *qp = (struct quattro *) cookie;
2129 for (i = 0; i < 4; i++) {
2130 struct net_device *dev = qp->happy_meals[i];
2131 struct happy_meal *hp = dev->priv;
2132 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2134 HMD(("quattro_interrupt: status=%08x ", happy_status));
2136 if (!(happy_status & (GREG_STAT_ERRORS |
2139 GREG_STAT_RXTOHOST)))
2142 spin_lock(&hp->happy_lock);
2144 if (happy_status & GREG_STAT_ERRORS) {
2146 if (happy_meal_is_not_so_happy(hp, happy_status))
2150 if (happy_status & GREG_STAT_MIFIRQ) {
2152 happy_meal_mif_interrupt(hp);
2155 if (happy_status & GREG_STAT_TXALL) {
2160 if (happy_status & GREG_STAT_RXTOHOST) {
2162 happy_meal_rx(hp, dev);
2166 spin_unlock(&hp->happy_lock);
2174 static int happy_meal_open(struct net_device *dev)
2176 struct happy_meal *hp = dev->priv;
2179 HMD(("happy_meal_open: "));
2181 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2182 * into a single source which we register handling at probe time.
2184 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2185 if (request_irq(dev->irq, &happy_meal_interrupt,
2186 IRQF_SHARED, dev->name, (void *)dev)) {
2188 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2195 HMD(("to happy_meal_init\n"));
2197 spin_lock_irq(&hp->happy_lock);
2198 res = happy_meal_init(hp);
2199 spin_unlock_irq(&hp->happy_lock);
2201 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2202 free_irq(dev->irq, dev);
2206 static int happy_meal_close(struct net_device *dev)
2208 struct happy_meal *hp = dev->priv;
2210 spin_lock_irq(&hp->happy_lock);
2211 happy_meal_stop(hp, hp->gregs);
2212 happy_meal_clean_rings(hp);
2214 /* If auto-negotiation timer is running, kill it. */
2215 del_timer(&hp->happy_timer);
2217 spin_unlock_irq(&hp->happy_lock);
2219 /* On Quattro QFE cards, all hme interrupts are concentrated
2220 * into a single source which we register handling at probe
2221 * time and never unregister.
2223 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2224 free_irq(dev->irq, dev);
2230 #define SXD(x) printk x
2235 static void happy_meal_tx_timeout(struct net_device *dev)
2237 struct happy_meal *hp = dev->priv;
2239 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2241 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2242 hme_read32(hp, hp->gregs + GREG_STAT),
2243 hme_read32(hp, hp->etxregs + ETX_CFG),
2244 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2246 spin_lock_irq(&hp->happy_lock);
2247 happy_meal_init(hp);
2248 spin_unlock_irq(&hp->happy_lock);
2250 netif_wake_queue(dev);
2253 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2255 struct happy_meal *hp = dev->priv;
2259 tx_flags = TXFLAG_OWN;
2260 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2261 const u32 csum_start_off = skb_transport_offset(skb);
2262 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
2264 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2265 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2266 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2269 spin_lock_irq(&hp->happy_lock);
2271 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2272 netif_stop_queue(dev);
2273 spin_unlock_irq(&hp->happy_lock);
2274 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2280 SXD(("SX<l[%d]e[%d]>", len, entry));
2281 hp->tx_skbs[entry] = skb;
2283 if (skb_shinfo(skb)->nr_frags == 0) {
2287 mapping = hme_dma_map(hp, skb->data, len, DMA_TO_DEVICE);
2288 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2289 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2290 (tx_flags | (len & TXFLAG_SIZE)),
2292 entry = NEXT_TX(entry);
2294 u32 first_len, first_mapping;
2295 int frag, first_entry = entry;
2297 /* We must give this initial chunk to the device last.
2298 * Otherwise we could race with the device.
2300 first_len = skb_headlen(skb);
2301 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TO_DEVICE);
2302 entry = NEXT_TX(entry);
2304 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2305 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2306 u32 len, mapping, this_txflags;
2308 len = this_frag->size;
2309 mapping = hme_dma_map(hp,
2310 ((void *) page_address(this_frag->page) +
2311 this_frag->page_offset),
2312 len, DMA_TO_DEVICE);
2313 this_txflags = tx_flags;
2314 if (frag == skb_shinfo(skb)->nr_frags - 1)
2315 this_txflags |= TXFLAG_EOP;
2316 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2317 (this_txflags | (len & TXFLAG_SIZE)),
2319 entry = NEXT_TX(entry);
2321 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2322 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2328 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2329 netif_stop_queue(dev);
2332 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2334 spin_unlock_irq(&hp->happy_lock);
2336 dev->trans_start = jiffies;
2338 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2342 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2344 struct happy_meal *hp = dev->priv;
2346 spin_lock_irq(&hp->happy_lock);
2347 happy_meal_get_counters(hp, hp->bigmacregs);
2348 spin_unlock_irq(&hp->happy_lock);
2350 return &hp->net_stats;
2353 static void happy_meal_set_multicast(struct net_device *dev)
2355 struct happy_meal *hp = dev->priv;
2356 void __iomem *bregs = hp->bigmacregs;
2357 struct dev_mc_list *dmi = dev->mc_list;
2362 spin_lock_irq(&hp->happy_lock);
2364 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2365 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2366 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2367 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2368 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2369 } else if (dev->flags & IFF_PROMISC) {
2370 hme_write32(hp, bregs + BMAC_RXCFG,
2371 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2375 for (i = 0; i < 4; i++)
2378 for (i = 0; i < dev->mc_count; i++) {
2379 addrs = dmi->dmi_addr;
2385 crc = ether_crc_le(6, addrs);
2387 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2389 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2390 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2391 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2392 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2395 spin_unlock_irq(&hp->happy_lock);
2398 /* Ethtool support... */
2399 static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2401 struct happy_meal *hp = dev->priv;
2404 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2405 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2406 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2408 /* XXX hardcoded stuff for now */
2409 cmd->port = PORT_TP; /* XXX no MII support */
2410 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2411 cmd->phy_address = 0; /* XXX fixed PHYAD */
2413 /* Record PHY settings. */
2414 spin_lock_irq(&hp->happy_lock);
2415 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2416 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2417 spin_unlock_irq(&hp->happy_lock);
2419 if (hp->sw_bmcr & BMCR_ANENABLE) {
2420 cmd->autoneg = AUTONEG_ENABLE;
2422 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2423 SPEED_100 : SPEED_10;
2424 if (cmd->speed == SPEED_100)
2426 (hp->sw_lpa & (LPA_100FULL)) ?
2427 DUPLEX_FULL : DUPLEX_HALF;
2430 (hp->sw_lpa & (LPA_10FULL)) ?
2431 DUPLEX_FULL : DUPLEX_HALF;
2433 cmd->autoneg = AUTONEG_DISABLE;
2435 (hp->sw_bmcr & BMCR_SPEED100) ?
2436 SPEED_100 : SPEED_10;
2438 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2439 DUPLEX_FULL : DUPLEX_HALF;
2444 static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2446 struct happy_meal *hp = dev->priv;
2448 /* Verify the settings we care about. */
2449 if (cmd->autoneg != AUTONEG_ENABLE &&
2450 cmd->autoneg != AUTONEG_DISABLE)
2452 if (cmd->autoneg == AUTONEG_DISABLE &&
2453 ((cmd->speed != SPEED_100 &&
2454 cmd->speed != SPEED_10) ||
2455 (cmd->duplex != DUPLEX_HALF &&
2456 cmd->duplex != DUPLEX_FULL)))
2459 /* Ok, do it to it. */
2460 spin_lock_irq(&hp->happy_lock);
2461 del_timer(&hp->happy_timer);
2462 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2463 spin_unlock_irq(&hp->happy_lock);
2468 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2470 struct happy_meal *hp = dev->priv;
2472 strcpy(info->driver, "sunhme");
2473 strcpy(info->version, "2.02");
2474 if (hp->happy_flags & HFLAG_PCI) {
2475 struct pci_dev *pdev = hp->happy_dev;
2476 strcpy(info->bus_info, pci_name(pdev));
2480 struct sbus_dev *sdev = hp->happy_dev;
2481 sprintf(info->bus_info, "SBUS:%d",
2487 static u32 hme_get_link(struct net_device *dev)
2489 struct happy_meal *hp = dev->priv;
2491 spin_lock_irq(&hp->happy_lock);
2492 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2493 spin_unlock_irq(&hp->happy_lock);
2495 return (hp->sw_bmsr & BMSR_LSTATUS);
2498 static const struct ethtool_ops hme_ethtool_ops = {
2499 .get_settings = hme_get_settings,
2500 .set_settings = hme_set_settings,
2501 .get_drvinfo = hme_get_drvinfo,
2502 .get_link = hme_get_link,
2505 static int hme_version_printed;
2508 void __devinit quattro_get_ranges(struct quattro *qp)
2510 struct sbus_dev *sdev = qp->quattro_dev;
2513 err = prom_getproperty(sdev->prom_node,
2515 (char *)&qp->ranges[0],
2516 sizeof(qp->ranges));
2517 if (err == 0 || err == -1) {
2521 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2524 static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2526 struct sbus_dev *sdev = hp->happy_dev;
2529 for (rng = 0; rng < qp->nranges; rng++) {
2530 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2533 for (reg = 0; reg < 5; reg++) {
2534 if (sdev->reg_addrs[reg].which_io ==
2535 rngp->ot_child_space)
2541 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2542 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2546 /* Given a happy meal sbus device, find it's quattro parent.
2547 * If none exist, allocate and return a new one.
2549 * Return NULL on failure.
2551 static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev)
2553 struct sbus_dev *sdev;
2557 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2558 for (i = 0, sdev = qp->quattro_dev;
2559 (sdev != NULL) && (i < 4);
2560 sdev = sdev->next, i++) {
2561 if (sdev == goal_sdev)
2566 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2570 for (i = 0; i < 4; i++)
2571 qp->happy_meals[i] = NULL;
2573 qp->quattro_dev = goal_sdev;
2574 qp->next = qfe_sbus_list;
2576 quattro_get_ranges(qp);
2581 /* After all quattro cards have been probed, we call these functions
2582 * to register the IRQ handlers.
2584 static void __init quattro_sbus_register_irqs(void)
2588 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2589 struct sbus_dev *sdev = qp->quattro_dev;
2592 err = request_irq(sdev->irqs[0],
2593 quattro_sbus_interrupt,
2594 IRQF_SHARED, "Quattro",
2597 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2598 panic("QFE request irq");
2603 static void quattro_sbus_free_irqs(void)
2607 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2608 struct sbus_dev *sdev = qp->quattro_dev;
2610 free_irq(sdev->irqs[0], qp);
2613 #endif /* CONFIG_SBUS */
2616 static struct quattro * __devinit quattro_pci_find(struct pci_dev *pdev)
2618 struct pci_dev *bdev = pdev->bus->self;
2621 if (!bdev) return NULL;
2622 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2623 struct pci_dev *qpdev = qp->quattro_dev;
2628 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2632 for (i = 0; i < 4; i++)
2633 qp->happy_meals[i] = NULL;
2635 qp->quattro_dev = bdev;
2636 qp->next = qfe_pci_list;
2639 /* No range tricks necessary on PCI. */
2644 #endif /* CONFIG_PCI */
2647 static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe)
2649 struct device_node *dp = sdev->ofdev.node;
2650 struct quattro *qp = NULL;
2651 struct happy_meal *hp;
2652 struct net_device *dev;
2653 int i, qfe_slot = -1;
2655 DECLARE_MAC_BUF(mac);
2658 qp = quattro_sbus_find(sdev);
2661 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2662 if (qp->happy_meals[qfe_slot] == NULL)
2669 dev = alloc_etherdev(sizeof(struct happy_meal));
2672 SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
2674 if (hme_version_printed++ == 0)
2675 printk(KERN_INFO "%s", version);
2677 /* If user did not specify a MAC address specifically, use
2678 * the Quattro local-mac-address property...
2680 for (i = 0; i < 6; i++) {
2681 if (macaddr[i] != 0)
2684 if (i < 6) { /* a mac address was given */
2685 for (i = 0; i < 6; i++)
2686 dev->dev_addr[i] = macaddr[i];
2689 const unsigned char *addr;
2692 addr = of_get_property(dp, "local-mac-address", &len);
2694 if (qfe_slot != -1 && addr && len == 6)
2695 memcpy(dev->dev_addr, addr, 6);
2697 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2702 hp->happy_dev = sdev;
2703 hp->dma_dev = &sdev->ofdev.dev;
2705 spin_lock_init(&hp->happy_lock);
2708 if (sdev->num_registers != 5) {
2709 printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n",
2710 sdev->num_registers);
2711 goto err_out_free_netdev;
2715 hp->qfe_parent = qp;
2716 hp->qfe_ent = qfe_slot;
2717 qp->happy_meals[qfe_slot] = dev;
2718 quattro_apply_ranges(qp, hp);
2721 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2722 GREG_REG_SIZE, "HME Global Regs");
2724 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2725 goto err_out_free_netdev;
2728 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2729 ETX_REG_SIZE, "HME TX Regs");
2731 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2732 goto err_out_iounmap;
2735 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2736 ERX_REG_SIZE, "HME RX Regs");
2738 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2739 goto err_out_iounmap;
2742 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2743 BMAC_REG_SIZE, "HME BIGMAC Regs");
2744 if (!hp->bigmacregs) {
2745 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2746 goto err_out_iounmap;
2749 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2750 TCVR_REG_SIZE, "HME Tranceiver Regs");
2752 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2753 goto err_out_iounmap;
2756 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2757 if (hp->hm_revision == 0xff)
2758 hp->hm_revision = 0xa0;
2760 /* Now enable the feature flags we can. */
2761 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2762 hp->happy_flags = HFLAG_20_21;
2763 else if (hp->hm_revision != 0xa0)
2764 hp->happy_flags = HFLAG_NOT_A0;
2767 hp->happy_flags |= HFLAG_QUATTRO;
2769 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2770 hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node,
2771 "burst-sizes", 0x00);
2773 hp->happy_block = dma_alloc_coherent(hp->dma_dev,
2778 if (!hp->happy_block) {
2779 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2780 goto err_out_iounmap;
2783 /* Force check of the link first time we are brought up. */
2786 /* Force timer state to 'asleep' with count of zero. */
2787 hp->timer_state = asleep;
2788 hp->timer_ticks = 0;
2790 init_timer(&hp->happy_timer);
2793 dev->open = &happy_meal_open;
2794 dev->stop = &happy_meal_close;
2795 dev->hard_start_xmit = &happy_meal_start_xmit;
2796 dev->get_stats = &happy_meal_get_stats;
2797 dev->set_multicast_list = &happy_meal_set_multicast;
2798 dev->tx_timeout = &happy_meal_tx_timeout;
2799 dev->watchdog_timeo = 5*HZ;
2800 dev->ethtool_ops = &hme_ethtool_ops;
2802 /* Happy Meal can do it all... */
2803 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2805 dev->irq = sdev->irqs[0];
2807 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2808 /* Hook up PCI register/dma accessors. */
2809 hp->read_desc32 = sbus_hme_read_desc32;
2810 hp->write_txd = sbus_hme_write_txd;
2811 hp->write_rxd = sbus_hme_write_rxd;
2812 hp->dma_map = (u32 (*)(void *, void *, long, int))dma_map_single;
2813 hp->dma_unmap = (void (*)(void *, u32, long, int))dma_unmap_single;
2814 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2815 dma_sync_single_for_cpu;
2816 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2817 dma_sync_single_for_device;
2818 hp->read32 = sbus_hme_read32;
2819 hp->write32 = sbus_hme_write32;
2822 /* Grrr, Happy Meal comes up by default not advertising
2823 * full duplex 100baseT capabilities, fix this.
2825 spin_lock_irq(&hp->happy_lock);
2826 happy_meal_set_initial_advertisement(hp);
2827 spin_unlock_irq(&hp->happy_lock);
2829 if (register_netdev(hp->dev)) {
2830 printk(KERN_ERR "happymeal: Cannot register net device, "
2832 goto err_out_free_coherent;
2835 dev_set_drvdata(&sdev->ofdev.dev, hp);
2838 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2839 dev->name, qfe_slot);
2841 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2844 printk("%s\n", print_mac(mac, dev->dev_addr));
2848 err_out_free_coherent:
2849 dma_free_coherent(hp->dma_dev,
2856 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2858 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2860 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2862 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2864 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2866 err_out_free_netdev:
2875 #ifndef CONFIG_SPARC
2876 static int is_quattro_p(struct pci_dev *pdev)
2878 struct pci_dev *busdev = pdev->bus->self;
2879 struct list_head *tmp;
2882 if (busdev == NULL ||
2883 busdev->vendor != PCI_VENDOR_ID_DEC ||
2884 busdev->device != PCI_DEVICE_ID_DEC_21153)
2888 tmp = pdev->bus->devices.next;
2889 while (tmp != &pdev->bus->devices) {
2890 struct pci_dev *this_pdev = pci_dev_b(tmp);
2892 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2893 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2905 /* Fetch MAC address from vital product data of PCI ROM. */
2906 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2910 for (this_offset = 0x20; this_offset < len; this_offset++) {
2911 void __iomem *p = rom_base + this_offset;
2913 if (readb(p + 0) != 0x90 ||
2914 readb(p + 1) != 0x00 ||
2915 readb(p + 2) != 0x09 ||
2916 readb(p + 3) != 0x4e ||
2917 readb(p + 4) != 0x41 ||
2918 readb(p + 5) != 0x06)
2927 for (i = 0; i < 6; i++)
2928 dev_addr[i] = readb(p + i);
2936 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2939 void __iomem *p = pci_map_rom(pdev, &size);
2945 if (is_quattro_p(pdev))
2946 index = PCI_SLOT(pdev->devfn);
2948 found = readb(p) == 0x55 &&
2949 readb(p + 1) == 0xaa &&
2950 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2951 pci_unmap_rom(pdev, p);
2956 /* Sun MAC prefix then 3 random bytes. */
2960 get_random_bytes(&dev_addr[3], 3);
2963 #endif /* !(CONFIG_SPARC) */
2965 static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2966 const struct pci_device_id *ent)
2968 struct quattro *qp = NULL;
2970 struct device_node *dp;
2972 struct happy_meal *hp;
2973 struct net_device *dev;
2974 void __iomem *hpreg_base;
2975 unsigned long hpreg_res;
2976 int i, qfe_slot = -1;
2979 DECLARE_MAC_BUF(mac);
2981 /* Now make sure pci_dev cookie is there. */
2983 dp = pci_device_to_OF_node(pdev);
2984 strcpy(prom_name, dp->name);
2986 if (is_quattro_p(pdev))
2987 strcpy(prom_name, "SUNW,qfe");
2989 strcpy(prom_name, "SUNW,hme");
2994 if (pci_enable_device(pdev))
2996 pci_set_master(pdev);
2998 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2999 qp = quattro_pci_find(pdev);
3002 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3003 if (qp->happy_meals[qfe_slot] == NULL)
3009 dev = alloc_etherdev(sizeof(struct happy_meal));
3013 SET_NETDEV_DEV(dev, &pdev->dev);
3015 if (hme_version_printed++ == 0)
3016 printk(KERN_INFO "%s", version);
3018 dev->base_addr = (long) pdev;
3020 hp = (struct happy_meal *)dev->priv;
3021 memset(hp, 0, sizeof(*hp));
3023 hp->happy_dev = pdev;
3026 spin_lock_init(&hp->happy_lock);
3029 hp->qfe_parent = qp;
3030 hp->qfe_ent = qfe_slot;
3031 qp->happy_meals[qfe_slot] = dev;
3034 hpreg_res = pci_resource_start(pdev, 0);
3036 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3037 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3038 goto err_out_clear_quattro;
3040 if (pci_request_regions(pdev, DRV_NAME)) {
3041 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3043 goto err_out_clear_quattro;
3046 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == NULL) {
3047 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3048 goto err_out_free_res;
3051 for (i = 0; i < 6; i++) {
3052 if (macaddr[i] != 0)
3055 if (i < 6) { /* a mac address was given */
3056 for (i = 0; i < 6; i++)
3057 dev->dev_addr[i] = macaddr[i];
3061 const unsigned char *addr;
3064 if (qfe_slot != -1 &&
3065 (addr = of_get_property(dp,
3066 "local-mac-address", &len)) != NULL
3068 memcpy(dev->dev_addr, addr, 6);
3070 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3073 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3077 /* Layout registers. */
3078 hp->gregs = (hpreg_base + 0x0000UL);
3079 hp->etxregs = (hpreg_base + 0x2000UL);
3080 hp->erxregs = (hpreg_base + 0x4000UL);
3081 hp->bigmacregs = (hpreg_base + 0x6000UL);
3082 hp->tcvregs = (hpreg_base + 0x7000UL);
3085 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3086 if (hp->hm_revision == 0xff)
3087 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3089 /* works with this on non-sparc hosts */
3090 hp->hm_revision = 0x20;
3093 /* Now enable the feature flags we can. */
3094 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3095 hp->happy_flags = HFLAG_20_21;
3096 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3097 hp->happy_flags = HFLAG_NOT_A0;
3100 hp->happy_flags |= HFLAG_QUATTRO;
3102 /* And of course, indicate this is PCI. */
3103 hp->happy_flags |= HFLAG_PCI;
3106 /* Assume PCI happy meals can handle all burst sizes. */
3107 hp->happy_bursts = DMA_BURSTBITS;
3110 hp->happy_block = (struct hmeal_init_block *)
3111 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3114 if (!hp->happy_block) {
3115 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3116 goto err_out_iounmap;
3120 hp->timer_state = asleep;
3121 hp->timer_ticks = 0;
3123 init_timer(&hp->happy_timer);
3126 dev->open = &happy_meal_open;
3127 dev->stop = &happy_meal_close;
3128 dev->hard_start_xmit = &happy_meal_start_xmit;
3129 dev->get_stats = &happy_meal_get_stats;
3130 dev->set_multicast_list = &happy_meal_set_multicast;
3131 dev->tx_timeout = &happy_meal_tx_timeout;
3132 dev->watchdog_timeo = 5*HZ;
3133 dev->ethtool_ops = &hme_ethtool_ops;
3134 dev->irq = pdev->irq;
3137 /* Happy Meal can do it all... */
3138 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3140 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3141 /* Hook up PCI register/dma accessors. */
3142 hp->read_desc32 = pci_hme_read_desc32;
3143 hp->write_txd = pci_hme_write_txd;
3144 hp->write_rxd = pci_hme_write_rxd;
3145 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3146 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3147 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3148 pci_dma_sync_single_for_cpu;
3149 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3150 pci_dma_sync_single_for_device;
3151 hp->read32 = pci_hme_read32;
3152 hp->write32 = pci_hme_write32;
3155 /* Grrr, Happy Meal comes up by default not advertising
3156 * full duplex 100baseT capabilities, fix this.
3158 spin_lock_irq(&hp->happy_lock);
3159 happy_meal_set_initial_advertisement(hp);
3160 spin_unlock_irq(&hp->happy_lock);
3162 if (register_netdev(hp->dev)) {
3163 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3165 goto err_out_iounmap;
3168 dev_set_drvdata(&pdev->dev, hp);
3171 struct pci_dev *qpdev = qp->quattro_dev;
3174 if (!strncmp(dev->name, "eth", 3)) {
3175 int i = simple_strtoul(dev->name + 3, NULL, 10);
3176 sprintf(prom_name, "-%d", i + 3);
3178 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3179 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3180 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3181 printk("DEC 21153 PCI Bridge\n");
3183 printk("unknown bridge %04x.%04x\n",
3184 qpdev->vendor, qpdev->device);
3188 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3189 dev->name, qfe_slot);
3191 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3194 printk("%s\n", print_mac(mac, dev->dev_addr));
3202 pci_release_regions(pdev);
3204 err_out_clear_quattro:
3206 qp->happy_meals[qfe_slot] = NULL;
3214 static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3216 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3217 struct net_device *net_dev = hp->dev;
3219 unregister_netdev(net_dev);
3221 pci_free_consistent(hp->dma_dev,
3226 pci_release_regions(hp->dma_dev);
3228 free_netdev(net_dev);
3230 dev_set_drvdata(&pdev->dev, NULL);
3233 static struct pci_device_id happymeal_pci_ids[] = {
3234 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3235 { } /* Terminating entry */
3238 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3240 static struct pci_driver hme_pci_driver = {
3242 .id_table = happymeal_pci_ids,
3243 .probe = happy_meal_pci_probe,
3244 .remove = __devexit_p(happy_meal_pci_remove),
3247 static int __init happy_meal_pci_init(void)
3249 return pci_register_driver(&hme_pci_driver);
3252 static void happy_meal_pci_exit(void)
3254 pci_unregister_driver(&hme_pci_driver);
3256 while (qfe_pci_list) {
3257 struct quattro *qfe = qfe_pci_list;
3258 struct quattro *next = qfe->next;
3262 qfe_pci_list = next;
3269 static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match)
3271 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
3272 struct device_node *dp = dev->node;
3273 const char *model = of_get_property(dp, "model", NULL);
3274 int is_qfe = (match->data != NULL);
3276 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3279 return happy_meal_sbus_probe_one(sdev, is_qfe);
3282 static int __devexit hme_sbus_remove(struct of_device *dev)
3284 struct happy_meal *hp = dev_get_drvdata(&dev->dev);
3285 struct net_device *net_dev = hp->dev;
3287 unregister_netdev(net_dev);
3289 /* XXX qfe parent interrupt... */
3291 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3292 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3293 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3294 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3295 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3296 dma_free_coherent(hp->dma_dev,
3301 free_netdev(net_dev);
3303 dev_set_drvdata(&dev->dev, NULL);
3308 static struct of_device_id hme_sbus_match[] = {
3323 MODULE_DEVICE_TABLE(of, hme_sbus_match);
3325 static struct of_platform_driver hme_sbus_driver = {
3327 .match_table = hme_sbus_match,
3328 .probe = hme_sbus_probe,
3329 .remove = __devexit_p(hme_sbus_remove),
3332 static int __init happy_meal_sbus_init(void)
3336 err = of_register_driver(&hme_sbus_driver, &sbus_bus_type);
3338 quattro_sbus_register_irqs();
3343 static void happy_meal_sbus_exit(void)
3345 of_unregister_driver(&hme_sbus_driver);
3346 quattro_sbus_free_irqs();
3348 while (qfe_sbus_list) {
3349 struct quattro *qfe = qfe_sbus_list;
3350 struct quattro *next = qfe->next;
3354 qfe_sbus_list = next;
3359 static int __init happy_meal_probe(void)
3364 err = happy_meal_sbus_init();
3368 err = happy_meal_pci_init();
3371 happy_meal_sbus_exit();
3380 static void __exit happy_meal_exit(void)
3383 happy_meal_sbus_exit();
3386 happy_meal_pci_exit();
3390 module_init(happy_meal_probe);
3391 module_exit(happy_meal_exit);