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   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5   Copyright (C) 2007-2009  STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/kernel.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_ether.h>
  43 #include <linux/crc32.h>
  44 #include <linux/mii.h>
  45 #include <linux/phy.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/stm/soc.h>
  49 #include "stmmac.h"
  50
  51 #define STMMAC_RESOURCE_NAME    "stmmaceth"
  52 #define PHY_RESOURCE_NAME       "stmmacphy"
  53
  54 #undef STMMAC_DEBUG
  55 /*#define STMMAC_DEBUG*/
  56 #ifdef STMMAC_DEBUG
  57 #define DBG(nlevel, klevel, fmt, args...) \
  58                 ((void)(netif_msg_##nlevel(priv) && \
  59                 printk(KERN_##klevel fmt, ## args)))
  60 #else
  61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  62 #endif
  63
  64 #undef STMMAC_RX_DEBUG
  65 /*#define STMMAC_RX_DEBUG*/
  66 #ifdef STMMAC_RX_DEBUG
  67 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  68 #else
  69 #define RX_DBG(fmt, args...)  do { } while (0)
  70 #endif
  71
  72 #undef STMMAC_XMIT_DEBUG
  73 /*#define STMMAC_XMIT_DEBUG*/
  74 #ifdef STMMAC_TX_DEBUG
  75 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  76 #else
  77 #define TX_DBG(fmt, args...)  do { } while (0)
  78 #endif
  79
  80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  81 #define JUMBO_LEN       9000
  82
  83 /* Module parameters */
  84 #define TX_TIMEO 5000 /* default 5 seconds */
  85 static int watchdog = TX_TIMEO;
  86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  88
  89 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  90 module_param(debug, int, S_IRUGO | S_IWUSR);
  91 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  92
  93 static int phyaddr = -1;
  94 module_param(phyaddr, int, S_IRUGO);
  95 MODULE_PARM_DESC(phyaddr, "Physical device address");
  96
  97 #define DMA_TX_SIZE 256
  98 static int dma_txsize = DMA_TX_SIZE;
  99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 101
 102 #define DMA_RX_SIZE 256
 103 static int dma_rxsize = DMA_RX_SIZE;
 104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 106
 107 static int flow_ctrl = FLOW_OFF;
 108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 110
 111 static int pause = PAUSE_TIME;
 112 module_param(pause, int, S_IRUGO | S_IWUSR);
 113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 114
 115 #define TC_DEFAULT 64
 116 static int tc = TC_DEFAULT;
 117 module_param(tc, int, S_IRUGO | S_IWUSR);
 118 MODULE_PARM_DESC(tc, "DMA threshold control value");
 119
 120 #define RX_NO_COALESCE  1       /* Always interrupt on completion */
 121 #define TX_NO_COALESCE  -1      /* No moderation by default */
 122
 123 /* Pay attention to tune this parameter; take care of both
 124  * hardware capability and network stabitily/performance impact.
 125  * Many tests showed that ~4ms latency seems to be good enough. */
 126 #ifdef CONFIG_STMMAC_TIMER
 127 #define DEFAULT_PERIODIC_RATE   256
 128 static int tmrate = DEFAULT_PERIODIC_RATE;
 129 module_param(tmrate, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
 131 #endif
 132
 133 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 134 static int buf_sz = DMA_BUFFER_SIZE;
 135 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 136 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 137
 138 /* In case of Giga ETH, we can enable/disable the COE for the
 139  * transmit HW checksum computation.
 140  * Note that, if tx csum is off in HW, SG will be still supported. */
 141 static int tx_coe = HW_CSUM;
 142 module_param(tx_coe, int, S_IRUGO | S_IWUSR);
 143 MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
 144
 145 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 146                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 147                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 148
 149 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 150 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
 151
 152 /**
 153  * stmmac_verify_args - verify the driver parameters.
 154  * Description: it verifies if some wrong parameter is passed to the driver.
 155  * Note that wrong parameters are replaced with the default values.
 156  */
 157 static void stmmac_verify_args(void)
 158 {
 159         if (unlikely(watchdog < 0))
 160                 watchdog = TX_TIMEO;
 161         if (unlikely(dma_rxsize < 0))
 162                 dma_rxsize = DMA_RX_SIZE;
 163         if (unlikely(dma_txsize < 0))
 164                 dma_txsize = DMA_TX_SIZE;
 165         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 166                 buf_sz = DMA_BUFFER_SIZE;
 167         if (unlikely(flow_ctrl > 1))
 168                 flow_ctrl = FLOW_AUTO;
 169         else if (likely(flow_ctrl < 0))
 170                 flow_ctrl = FLOW_OFF;
 171         if (unlikely((pause < 0) || (pause > 0xffff)))
 172                 pause = PAUSE_TIME;
 173
 174         return;
 175 }
 176
 177 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 178 static void print_pkt(unsigned char *buf, int len)
 179 {
 180         int j;
 181         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 182         for (j = 0; j < len; j++) {
 183                 if ((j % 16) == 0)
 184                         pr_info("\n %03x:", j);
 185                 pr_info(" %02x", buf[j]);
 186         }
 187         pr_info("\n");
 188         return;
 189 }
 190 #endif
 191
 192 /* minimum number of free TX descriptors required to wake up TX process */
 193 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 194
 195 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 196 {
 197         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 198 }
 199
 200 /**
 201  * stmmac_adjust_link
 202  * @dev: net device structure
 203  * Description: it adjusts the link parameters.
 204  */
 205 static void stmmac_adjust_link(struct net_device *dev)
 206 {
 207         struct stmmac_priv *priv = netdev_priv(dev);
 208         struct phy_device *phydev = priv->phydev;
 209         unsigned long ioaddr = dev->base_addr;
 210         unsigned long flags;
 211         int new_state = 0;
 212         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 213
 214         if (phydev == NULL)
 215                 return;
 216
 217         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 218             phydev->addr, phydev->link);
 219
 220         spin_lock_irqsave(&priv->lock, flags);
 221         if (phydev->link) {
 222                 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
 223
 224                 /* Now we make sure that we can be in full duplex mode.
 225                  * If not, we operate in half-duplex mode. */
 226                 if (phydev->duplex != priv->oldduplex) {
 227                         new_state = 1;
 228                         if (!(phydev->duplex))
 229                                 ctrl &= ~priv->mac_type->hw.link.duplex;
 230                         else
 231                                 ctrl |= priv->mac_type->hw.link.duplex;
 232                         priv->oldduplex = phydev->duplex;
 233                 }
 234                 /* Flow Control operation */
 235                 if (phydev->pause)
 236                         priv->mac_type->ops->flow_ctrl(ioaddr, phydev->duplex,
 237                                                        fc, pause_time);
 238
 239                 if (phydev->speed != priv->speed) {
 240                         new_state = 1;
 241                         switch (phydev->speed) {
 242                         case 1000:
 243                                 if (likely(priv->is_gmac))
 244                                         ctrl &= ~priv->mac_type->hw.link.port;
 245                                 break;
 246                         case 100:
 247                         case 10:
 248                                 if (priv->is_gmac) {
 249                                         ctrl |= priv->mac_type->hw.link.port;
 250                                         if (phydev->speed == SPEED_100) {
 251                                                 ctrl |=
 252                                                     priv->mac_type->hw.link.
 253                                                     speed;
 254                                         } else {
 255                                                 ctrl &=
 256                                                     ~(priv->mac_type->hw.
 257                                                       link.speed);
 258                                         }
 259                                 } else {
 260                                         ctrl &= ~priv->mac_type->hw.link.port;
 261                                 }
 262                                 priv->fix_mac_speed(priv->bsp_priv,
 263                                                     phydev->speed);
 264                                 break;
 265                         default:
 266                                 if (netif_msg_link(priv))
 267                                         pr_warning("%s: Speed (%d) is not 10"
 268                                        " or 100!\n", dev->name, phydev->speed);
 269                                 break;
 270                         }
 271
 272                         priv->speed = phydev->speed;
 273                 }
 274
 275                 writel(ctrl, ioaddr + MAC_CTRL_REG);
 276
 277                 if (!priv->oldlink) {
 278                         new_state = 1;
 279                         priv->oldlink = 1;
 280                 }
 281         } else if (priv->oldlink) {
 282                 new_state = 1;
 283                 priv->oldlink = 0;
 284                 priv->speed = 0;
 285                 priv->oldduplex = -1;
 286         }
 287
 288         if (new_state && netif_msg_link(priv))
 289                 phy_print_status(phydev);
 290
 291         spin_unlock_irqrestore(&priv->lock, flags);
 292
 293         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 294 }
 295
 296 /**
 297  * stmmac_init_phy - PHY initialization
 298  * @dev: net device structure
 299  * Description: it initializes the driver's PHY state, and attaches the PHY
 300  * to the mac driver.
 301  *  Return value:
 302  *  0 on success
 303  */
 304 static int stmmac_init_phy(struct net_device *dev)
 305 {
 306         struct stmmac_priv *priv = netdev_priv(dev);
 307         struct phy_device *phydev;
 308         char phy_id[BUS_ID_SIZE];       /* PHY to connect */
 309         char bus_id[BUS_ID_SIZE];
 310
 311         priv->oldlink = 0;
 312         priv->speed = 0;
 313         priv->oldduplex = -1;
 314
 315         if (priv->phy_addr == -1) {
 316                 /* We don't have a PHY, so do nothing */
 317                 return 0;
 318         }
 319
 320         snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
 321         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, bus_id, priv->phy_addr);
 322         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
 323
 324         phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
 325                         priv->phy_interface);
 326
 327         if (IS_ERR(phydev)) {
 328                 pr_err("%s: Could not attach to PHY\n", dev->name);
 329                 return PTR_ERR(phydev);
 330         }
 331
 332         /*
 333          * Broken HW is sometimes missing the pull-up resistor on the
 334          * MDIO line, which results in reads to non-existent devices returning
 335          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 336          * device as well.
 337          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 338          */
 339         if (phydev->phy_id == 0) {
 340                 phy_disconnect(phydev);
 341                 return -ENODEV;
 342         }
 343         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 344                " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 345
 346         priv->phydev = phydev;
 347
 348         return 0;
 349 }
 350
 351 static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
 352 {
 353         u32 value = readl(ioaddr + MAC_CTRL_REG);
 354         value |= MAC_RNABLE_RX;
 355         /* Set the RE (receive enable bit into the MAC CTRL register).  */
 356         writel(value, ioaddr + MAC_CTRL_REG);
 357 }
 358
 359 static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
 360 {
 361         u32 value = readl(ioaddr + MAC_CTRL_REG);
 362         value |= MAC_ENABLE_TX;
 363         /* Set the TE (transmit enable bit into the MAC CTRL register).  */
 364         writel(value, ioaddr + MAC_CTRL_REG);
 365 }
 366
 367 static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
 368 {
 369         u32 value = readl(ioaddr + MAC_CTRL_REG);
 370         value &= ~MAC_RNABLE_RX;
 371         writel(value, ioaddr + MAC_CTRL_REG);
 372 }
 373
 374 static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
 375 {
 376         u32 value = readl(ioaddr + MAC_CTRL_REG);
 377         value &= ~MAC_ENABLE_TX;
 378         writel(value, ioaddr + MAC_CTRL_REG);
 379 }
 380
 381 /**
 382  * display_ring
 383  * @p: pointer to the ring.
 384  * @size: size of the ring.
 385  * Description: display all the descriptors within the ring.
 386  */
 387 static void display_ring(struct dma_desc *p, int size)
 388 {
 389         struct tmp_s {
 390                 u64 a;
 391                 unsigned int b;
 392                 unsigned int c;
 393         };
 394         int i;
 395         for (i = 0; i < size; i++) {
 396                 struct tmp_s *x = (struct tmp_s *)(p + i);
 397                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 398                        i, (unsigned int)virt_to_phys(&p[i]),
 399                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 400                        x->b, x->c);
 401                 pr_info("\n");
 402         }
 403 }
 404
 405 /**
 406  * init_dma_desc_rings - init the RX/TX descriptor rings
 407  * @dev: net device structure
 408  * Description:  this function initializes the DMA RX/TX descriptors
 409  * and allocates the socket buffers.
 410  */
 411 static void init_dma_desc_rings(struct net_device *dev)
 412 {
 413         int i;
 414         struct stmmac_priv *priv = netdev_priv(dev);
 415         struct sk_buff *skb;
 416         unsigned int txsize = priv->dma_tx_size;
 417         unsigned int rxsize = priv->dma_rx_size;
 418         unsigned int bfsize = priv->dma_buf_sz;
 419         int buff2_needed = 0;
 420         int dis_ic = 0;
 421
 422 #ifdef CONFIG_STMMAC_TIMER
 423         /* Using Timers disable interrupts on completion for the reception */
 424         dis_ic = 1;
 425 #endif
 426         /* Set the Buffer size according to the MTU;
 427          * indeed, in case of jumbo we need to bump-up the buffer sizes.
 428          */
 429         if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
 430                 bfsize = BUF_SIZE_16KiB;
 431         else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
 432                 bfsize = BUF_SIZE_8KiB;
 433         else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
 434                 bfsize = BUF_SIZE_4KiB;
 435         else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
 436                 bfsize = BUF_SIZE_2KiB;
 437         else
 438                 bfsize = DMA_BUFFER_SIZE;
 439
 440         /* If the MTU exceeds 8k so use the second buffer in the chain */
 441         if (bfsize >= BUF_SIZE_8KiB)
 442                 buff2_needed = 1;
 443
 444         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 445             txsize, rxsize, bfsize);
 446
 447         priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
 448         priv->rx_skbuff =
 449             kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
 450         priv->dma_rx =
 451             (struct dma_desc *)dma_alloc_coherent(priv->device,
 452                                                   rxsize *
 453                                                   sizeof(struct dma_desc),
 454                                                   &priv->dma_rx_phy,
 455                                                   GFP_KERNEL);
 456         priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
 457                                        GFP_KERNEL);
 458         priv->dma_tx =
 459             (struct dma_desc *)dma_alloc_coherent(priv->device,
 460                                                   txsize *
 461                                                   sizeof(struct dma_desc),
 462                                                   &priv->dma_tx_phy,
 463                                                   GFP_KERNEL);
 464
 465         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
 466                 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
 467                 return;
 468         }
 469
 470         DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
 471             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 472             dev->name, priv->dma_rx, priv->dma_tx,
 473             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 474
 475         /* RX INITIALIZATION */
 476         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 477                          "skb\t\tskb data\tdma data\n");
 478
 479         for (i = 0; i < rxsize; i++) {
 480                 struct dma_desc *p = priv->dma_rx + i;
 481
 482                 skb = netdev_alloc_skb_ip_align(dev, bfsize);
 483                 if (unlikely(skb == NULL)) {
 484                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 485                         break;
 486                 }
 487                 priv->rx_skbuff[i] = skb;
 488                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 489                                                 bfsize, DMA_FROM_DEVICE);
 490
 491                 p->des2 = priv->rx_skbuff_dma[i];
 492                 if (unlikely(buff2_needed))
 493                         p->des3 = p->des2 + BUF_SIZE_8KiB;
 494                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 495                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 496         }
 497         priv->cur_rx = 0;
 498         priv->dirty_rx = (unsigned int)(i - rxsize);
 499         priv->dma_buf_sz = bfsize;
 500         buf_sz = bfsize;
 501
 502         /* TX INITIALIZATION */
 503         for (i = 0; i < txsize; i++) {
 504                 priv->tx_skbuff[i] = NULL;
 505                 priv->dma_tx[i].des2 = 0;
 506         }
 507         priv->dirty_tx = 0;
 508         priv->cur_tx = 0;
 509
 510         /* Clear the Rx/Tx descriptors */
 511         priv->mac_type->ops->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
 512         priv->mac_type->ops->init_tx_desc(priv->dma_tx, txsize);
 513
 514         if (netif_msg_hw(priv)) {
 515                 pr_info("RX descriptor ring:\n");
 516                 display_ring(priv->dma_rx, rxsize);
 517                 pr_info("TX descriptor ring:\n");
 518                 display_ring(priv->dma_tx, txsize);
 519         }
 520         return;
 521 }
 522
 523 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 524 {
 525         int i;
 526
 527         for (i = 0; i < priv->dma_rx_size; i++) {
 528                 if (priv->rx_skbuff[i]) {
 529                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 530                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 531                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 532                 }
 533                 priv->rx_skbuff[i] = NULL;
 534         }
 535         return;
 536 }
 537
 538 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 539 {
 540         int i;
 541
 542         for (i = 0; i < priv->dma_tx_size; i++) {
 543                 if (priv->tx_skbuff[i] != NULL) {
 544                         struct dma_desc *p = priv->dma_tx + i;
 545                         if (p->des2)
 546                                 dma_unmap_single(priv->device, p->des2,
 547                                  priv->mac_type->ops->get_tx_len(p),
 548                                  DMA_TO_DEVICE);
 549                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 550                         priv->tx_skbuff[i] = NULL;
 551                 }
 552         }
 553         return;
 554 }
 555
 556 static void free_dma_desc_resources(struct stmmac_priv *priv)
 557 {
 558         /* Release the DMA TX/RX socket buffers */
 559         dma_free_rx_skbufs(priv);
 560         dma_free_tx_skbufs(priv);
 561
 562         /* Free the region of consistent memory previously allocated for
 563          * the DMA */
 564         dma_free_coherent(priv->device,
 565                           priv->dma_tx_size * sizeof(struct dma_desc),
 566                           priv->dma_tx, priv->dma_tx_phy);
 567         dma_free_coherent(priv->device,
 568                           priv->dma_rx_size * sizeof(struct dma_desc),
 569                           priv->dma_rx, priv->dma_rx_phy);
 570         kfree(priv->rx_skbuff_dma);
 571         kfree(priv->rx_skbuff);
 572         kfree(priv->tx_skbuff);
 573
 574         return;
 575 }
 576
 577 /**
 578  * stmmac_dma_start_tx
 579  * @ioaddr: device I/O address
 580  * Description:  this function starts the DMA tx process.
 581  */
 582 static void stmmac_dma_start_tx(unsigned long ioaddr)
 583 {
 584         u32 value = readl(ioaddr + DMA_CONTROL);
 585         value |= DMA_CONTROL_ST;
 586         writel(value, ioaddr + DMA_CONTROL);
 587         return;
 588 }
 589
 590 static void stmmac_dma_stop_tx(unsigned long ioaddr)
 591 {
 592         u32 value = readl(ioaddr + DMA_CONTROL);
 593         value &= ~DMA_CONTROL_ST;
 594         writel(value, ioaddr + DMA_CONTROL);
 595         return;
 596 }
 597
 598 /**
 599  * stmmac_dma_start_rx
 600  * @ioaddr: device I/O address
 601  * Description:  this function starts the DMA rx process.
 602  */
 603 static void stmmac_dma_start_rx(unsigned long ioaddr)
 604 {
 605         u32 value = readl(ioaddr + DMA_CONTROL);
 606         value |= DMA_CONTROL_SR;
 607         writel(value, ioaddr + DMA_CONTROL);
 608
 609         return;
 610 }
 611
 612 static void stmmac_dma_stop_rx(unsigned long ioaddr)
 613 {
 614         u32 value = readl(ioaddr + DMA_CONTROL);
 615         value &= ~DMA_CONTROL_SR;
 616         writel(value, ioaddr + DMA_CONTROL);
 617
 618         return;
 619 }
 620
 621 /**
 622  *  stmmac_dma_operation_mode - HW DMA operation mode
 623  *  @priv : pointer to the private device structure.
 624  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 625  *  or Store-And-Forward capability. It also verifies the COE for the
 626  *  transmission in case of Giga ETH.
 627  */
 628 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 629 {
 630         if (!priv->is_gmac) {
 631                 /* MAC 10/100 */
 632                 priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc, 0);
 633                 priv->tx_coe = NO_HW_CSUM;
 634         } else {
 635                 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
 636                         priv->mac_type->ops->dma_mode(priv->dev->base_addr,
 637                                                       SF_DMA_MODE, SF_DMA_MODE);
 638                         tc = SF_DMA_MODE;
 639                         priv->tx_coe = HW_CSUM;
 640                 } else {
 641                         /* Checksum computation is performed in software. */
 642                         priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc,
 643                                                       SF_DMA_MODE);
 644                         priv->tx_coe = NO_HW_CSUM;
 645                 }
 646         }
 647         tx_coe = priv->tx_coe;
 648
 649         return;
 650 }
 651
 652 #ifdef STMMAC_DEBUG
 653 /**
 654  * show_tx_process_state
 655  * @status: tx descriptor status field
 656  * Description: it shows the Transmit Process State for CSR5[22:20]
 657  */
 658 static void show_tx_process_state(unsigned int status)
 659 {
 660         unsigned int state;
 661         state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
 662
 663         switch (state) {
 664         case 0:
 665                 pr_info("- TX (Stopped): Reset or Stop command\n");
 666                 break;
 667         case 1:
 668                 pr_info("- TX (Running):Fetching the Tx desc\n");
 669                 break;
 670         case 2:
 671                 pr_info("- TX (Running): Waiting for end of tx\n");
 672                 break;
 673         case 3:
 674                 pr_info("- TX (Running): Reading the data "
 675                        "and queuing the data into the Tx buf\n");
 676                 break;
 677         case 6:
 678                 pr_info("- TX (Suspended): Tx Buff Underflow "
 679                        "or an unavailable Transmit descriptor\n");
 680                 break;
 681         case 7:
 682                 pr_info("- TX (Running): Closing Tx descriptor\n");
 683                 break;
 684         default:
 685                 break;
 686         }
 687         return;
 688 }
 689
 690 /**
 691  * show_rx_process_state
 692  * @status: rx descriptor status field
 693  * Description: it shows the  Receive Process State for CSR5[19:17]
 694  */
 695 static void show_rx_process_state(unsigned int status)
 696 {
 697         unsigned int state;
 698         state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
 699
 700         switch (state) {
 701         case 0:
 702                 pr_info("- RX (Stopped): Reset or Stop command\n");
 703                 break;
 704         case 1:
 705                 pr_info("- RX (Running): Fetching the Rx desc\n");
 706                 break;
 707         case 2:
 708                 pr_info("- RX (Running):Checking for end of pkt\n");
 709                 break;
 710         case 3:
 711                 pr_info("- RX (Running): Waiting for Rx pkt\n");
 712                 break;
 713         case 4:
 714                 pr_info("- RX (Suspended): Unavailable Rx buf\n");
 715                 break;
 716         case 5:
 717                 pr_info("- RX (Running): Closing Rx descriptor\n");
 718                 break;
 719         case 6:
 720                 pr_info("- RX(Running): Flushing the current frame"
 721                        " from the Rx buf\n");
 722                 break;
 723         case 7:
 724                 pr_info("- RX (Running): Queuing the Rx frame"
 725                        " from the Rx buf into memory\n");
 726                 break;
 727         default:
 728                 break;
 729         }
 730         return;
 731 }
 732 #endif
 733
 734 /**
 735  * stmmac_tx:
 736  * @priv: private driver structure
 737  * Description: it reclaims resources after transmission completes.
 738  */
 739 static void stmmac_tx(struct stmmac_priv *priv)
 740 {
 741         unsigned int txsize = priv->dma_tx_size;
 742         unsigned long ioaddr = priv->dev->base_addr;
 743
 744         while (priv->dirty_tx != priv->cur_tx) {
 745                 int last;
 746                 unsigned int entry = priv->dirty_tx % txsize;
 747                 struct sk_buff *skb = priv->tx_skbuff[entry];
 748                 struct dma_desc *p = priv->dma_tx + entry;
 749
 750                 /* Check if the descriptor is owned by the DMA. */
 751                 if (priv->mac_type->ops->get_tx_owner(p))
 752                         break;
 753
 754                 /* Verify tx error by looking at the last segment */
 755                 last = priv->mac_type->ops->get_tx_ls(p);
 756                 if (likely(last)) {
 757                         int tx_error =
 758                             priv->mac_type->ops->tx_status(&priv->dev->stats,
 759                                                            &priv->xstats,
 760                                                            p, ioaddr);
 761                         if (likely(tx_error == 0)) {
 762                                 priv->dev->stats.tx_packets++;
 763                                 priv->xstats.tx_pkt_n++;
 764                         } else
 765                                 priv->dev->stats.tx_errors++;
 766                 }
 767                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 768                         priv->cur_tx, priv->dirty_tx);
 769
 770                 if (likely(p->des2))
 771                         dma_unmap_single(priv->device, p->des2,
 772                                          priv->mac_type->ops->get_tx_len(p),
 773                                          DMA_TO_DEVICE);
 774                 if (unlikely(p->des3))
 775                         p->des3 = 0;
 776
 777                 if (likely(skb != NULL)) {
 778                         /*
 779                          * If there's room in the queue (limit it to size)
 780                          * we add this skb back into the pool,
 781                          * if it's the right size.
 782                          */
 783                         if ((skb_queue_len(&priv->rx_recycle) <
 784                                 priv->dma_rx_size) &&
 785                                 skb_recycle_check(skb, priv->dma_buf_sz))
 786                                 __skb_queue_head(&priv->rx_recycle, skb);
 787                         else
 788                                 dev_kfree_skb(skb);
 789
 790                         priv->tx_skbuff[entry] = NULL;
 791                 }
 792
 793                 priv->mac_type->ops->release_tx_desc(p);
 794
 795                 entry = (++priv->dirty_tx) % txsize;
 796         }
 797         if (unlikely(netif_queue_stopped(priv->dev) &&
 798                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 799                 netif_tx_lock(priv->dev);
 800                 if (netif_queue_stopped(priv->dev) &&
 801                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 802                         TX_DBG("%s: restart transmit\n", __func__);
 803                         netif_wake_queue(priv->dev);
 804                 }
 805                 netif_tx_unlock(priv->dev);
 806         }
 807         return;
 808 }
 809
 810 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
 811 {
 812 #ifndef CONFIG_STMMAC_TIMER
 813         writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA);
 814 #else
 815         priv->tm->timer_start(tmrate);
 816 #endif
 817 }
 818
 819 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
 820 {
 821 #ifndef CONFIG_STMMAC_TIMER
 822         writel(0, priv->dev->base_addr + DMA_INTR_ENA);
 823 #else
 824         priv->tm->timer_stop();
 825 #endif
 826 }
 827
 828 static int stmmac_has_work(struct stmmac_priv *priv)
 829 {
 830         unsigned int has_work = 0;
 831         int rxret, tx_work = 0;
 832
 833         rxret = priv->mac_type->ops->get_rx_owner(priv->dma_rx +
 834                 (priv->cur_rx % priv->dma_rx_size));
 835
 836         if (priv->dirty_tx != priv->cur_tx)
 837                 tx_work = 1;
 838
 839         if (likely(!rxret || tx_work))
 840                 has_work = 1;
 841
 842         return has_work;
 843 }
 844
 845 static inline void _stmmac_schedule(struct stmmac_priv *priv)
 846 {
 847         if (likely(stmmac_has_work(priv))) {
 848                 stmmac_disable_irq(priv);
 849                 napi_schedule(&priv->napi);
 850         }
 851 }
 852
 853 #ifdef CONFIG_STMMAC_TIMER
 854 void stmmac_schedule(struct net_device *dev)
 855 {
 856         struct stmmac_priv *priv = netdev_priv(dev);
 857
 858         priv->xstats.sched_timer_n++;
 859
 860         _stmmac_schedule(priv);
 861
 862         return;
 863 }
 864
 865 static void stmmac_no_timer_started(unsigned int x)
 866 {;
 867 };
 868
 869 static void stmmac_no_timer_stopped(void)
 870 {;
 871 };
 872 #endif
 873
 874 /**
 875  * stmmac_tx_err:
 876  * @priv: pointer to the private device structure
 877  * Description: it cleans the descriptors and restarts the transmission
 878  * in case of errors.
 879  */
 880 static void stmmac_tx_err(struct stmmac_priv *priv)
 881 {
 882         netif_stop_queue(priv->dev);
 883
 884         stmmac_dma_stop_tx(priv->dev->base_addr);
 885         dma_free_tx_skbufs(priv);
 886         priv->mac_type->ops->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
 887         priv->dirty_tx = 0;
 888         priv->cur_tx = 0;
 889         stmmac_dma_start_tx(priv->dev->base_addr);
 890
 891         priv->dev->stats.tx_errors++;
 892         netif_wake_queue(priv->dev);
 893
 894         return;
 895 }
 896
 897 /**
 898  * stmmac_dma_interrupt - Interrupt handler for the driver
 899  * @dev: net device structure
 900  * Description: Interrupt handler for the driver (DMA).
 901  */
 902 static void stmmac_dma_interrupt(struct net_device *dev)
 903 {
 904         unsigned long ioaddr = dev->base_addr;
 905         struct stmmac_priv *priv = netdev_priv(dev);
 906         /* read the status register (CSR5) */
 907         u32 intr_status = readl(ioaddr + DMA_STATUS);
 908
 909         DBG(intr, INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
 910
 911 #ifdef STMMAC_DEBUG
 912         /* It displays the DMA transmit process state (CSR5 register) */
 913         if (netif_msg_tx_done(priv))
 914                 show_tx_process_state(intr_status);
 915         if (netif_msg_rx_status(priv))
 916                 show_rx_process_state(intr_status);
 917 #endif
 918         /* ABNORMAL interrupts */
 919         if (unlikely(intr_status & DMA_STATUS_AIS)) {
 920                 DBG(intr, INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
 921                 if (unlikely(intr_status & DMA_STATUS_UNF)) {
 922                         DBG(intr, INFO, "transmit underflow\n");
 923                         if (unlikely(tc != SF_DMA_MODE)
 924                             && (tc <= 256)) {
 925                                 /* Try to bump up the threshold */
 926                                 tc += 64;
 927                                 priv->mac_type->ops->dma_mode(ioaddr, tc,
 928                                               SF_DMA_MODE);
 929                                 priv->xstats.threshold = tc;
 930                         }
 931                         stmmac_tx_err(priv);
 932                         priv->xstats.tx_undeflow_irq++;
 933                 }
 934                 if (unlikely(intr_status & DMA_STATUS_TJT)) {
 935                         DBG(intr, INFO, "transmit jabber\n");
 936                         priv->xstats.tx_jabber_irq++;
 937                 }
 938                 if (unlikely(intr_status & DMA_STATUS_OVF)) {
 939                         DBG(intr, INFO, "recv overflow\n");
 940                         priv->xstats.rx_overflow_irq++;
 941                 }
 942                 if (unlikely(intr_status & DMA_STATUS_RU)) {
 943                         DBG(intr, INFO, "receive buffer unavailable\n");
 944                         priv->xstats.rx_buf_unav_irq++;
 945                 }
 946                 if (unlikely(intr_status & DMA_STATUS_RPS)) {
 947                         DBG(intr, INFO, "receive process stopped\n");
 948                         priv->xstats.rx_process_stopped_irq++;
 949                 }
 950                 if (unlikely(intr_status & DMA_STATUS_RWT)) {
 951                         DBG(intr, INFO, "receive watchdog\n");
 952                         priv->xstats.rx_watchdog_irq++;
 953                 }
 954                 if (unlikely(intr_status & DMA_STATUS_ETI)) {
 955                         DBG(intr, INFO, "transmit early interrupt\n");
 956                         priv->xstats.tx_early_irq++;
 957                 }
 958                 if (unlikely(intr_status & DMA_STATUS_TPS)) {
 959                         DBG(intr, INFO, "transmit process stopped\n");
 960                         priv->xstats.tx_process_stopped_irq++;
 961                         stmmac_tx_err(priv);
 962                 }
 963                 if (unlikely(intr_status & DMA_STATUS_FBI)) {
 964                         DBG(intr, INFO, "fatal bus error\n");
 965                         priv->xstats.fatal_bus_error_irq++;
 966                         stmmac_tx_err(priv);
 967                 }
 968         }
 969
 970         /* TX/RX NORMAL interrupts */
 971         if (intr_status & DMA_STATUS_NIS) {
 972                 priv->xstats.normal_irq_n++;
 973                 if (likely((intr_status & DMA_STATUS_RI) ||
 974                          (intr_status & (DMA_STATUS_TI))))
 975                                 _stmmac_schedule(priv);
 976         }
 977
 978         /* Optional hardware blocks, interrupts should be disabled */
 979         if (unlikely(intr_status &
 980                      (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
 981                 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
 982
 983         /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
 984         writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
 985
 986         DBG(intr, INFO, "\n\n");
 987
 988         return;
 989 }
 990
 991 /**
 992  *  stmmac_open - open entry point of the driver
 993  *  @dev : pointer to the device structure.
 994  *  Description:
 995  *  This function is the open entry point of the driver.
 996  *  Return value:
 997  *  0 on success and an appropriate (-)ve integer as defined in errno.h
 998  *  file on failure.
 999  */
1000 static int stmmac_open(struct net_device *dev)
1001 {
1002         struct stmmac_priv *priv = netdev_priv(dev);
1003         unsigned long ioaddr = dev->base_addr;
1004         int ret;
1005
1006         /* Check that the MAC address is valid.  If its not, refuse
1007          * to bring the device up. The user must specify an
1008          * address using the following linux command:
1009          *      ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx  */
1010         if (!is_valid_ether_addr(dev->dev_addr)) {
1011                 random_ether_addr(dev->dev_addr);
1012                 pr_warning("%s: generated random MAC address %pM\n", dev->name,
1013                         dev->dev_addr);
1014         }
1015
1016         stmmac_verify_args();
1017
1018         ret = stmmac_init_phy(dev);
1019         if (unlikely(ret)) {
1020                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1021                 return ret;
1022         }
1023
1024         /* Request the IRQ lines */
1025         ret = request_irq(dev->irq, stmmac_interrupt,
1026                           IRQF_SHARED, dev->name, dev);
1027         if (unlikely(ret < 0)) {
1028                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1029                        __func__, dev->irq, ret);
1030                 return ret;
1031         }
1032
1033 #ifdef CONFIG_STMMAC_TIMER
1034         priv->tm = kmalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
1035         if (unlikely(priv->tm == NULL)) {
1036                 pr_err("%s: ERROR: timer memory alloc failed \n", __func__);
1037                 return -ENOMEM;
1038         }
1039         priv->tm->freq = tmrate;
1040
1041         /* Test if the HW timer can be actually used.
1042          * In case of failure continue with no timer. */
1043         if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
1044                 pr_warning("stmmaceth: cannot attach the HW timer\n");
1045                 tmrate = 0;
1046                 priv->tm->freq = 0;
1047                 priv->tm->timer_start = stmmac_no_timer_started;
1048                 priv->tm->timer_stop = stmmac_no_timer_stopped;
1049         }
1050 #endif
1051
1052         /* Create and initialize the TX/RX descriptors chains. */
1053         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1054         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1055         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1056         init_dma_desc_rings(dev);
1057
1058         /* DMA initialization and SW reset */
1059         if (unlikely(priv->mac_type->ops->dma_init(ioaddr,
1060                 priv->pbl, priv->dma_tx_phy, priv->dma_rx_phy) < 0)) {
1061
1062                 pr_err("%s: DMA initialization failed\n", __func__);
1063                 return -1;
1064         }
1065
1066         /* Copy the MAC addr into the HW  */
1067         priv->mac_type->ops->set_umac_addr(ioaddr, dev->dev_addr, 0);
1068         /* Initialize the MAC Core */
1069         priv->mac_type->ops->core_init(ioaddr);
1070
1071         priv->shutdown = 0;
1072
1073         /* Initialise the MMC (if present) to disable all interrupts. */
1074         writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
1075         writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
1076
1077         /* Enable the MAC Rx/Tx */
1078         stmmac_mac_enable_rx(ioaddr);
1079         stmmac_mac_enable_tx(ioaddr);
1080
1081         /* Set the HW DMA mode and the COE */
1082         stmmac_dma_operation_mode(priv);
1083
1084         /* Extra statistics */
1085         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1086         priv->xstats.threshold = tc;
1087
1088         /* Start the ball rolling... */
1089         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1090         stmmac_dma_start_tx(ioaddr);
1091         stmmac_dma_start_rx(ioaddr);
1092
1093 #ifdef CONFIG_STMMAC_TIMER
1094         priv->tm->timer_start(tmrate);
1095 #endif
1096         /* Dump DMA/MAC registers */
1097         if (netif_msg_hw(priv)) {
1098                 priv->mac_type->ops->dump_mac_regs(ioaddr);
1099                 priv->mac_type->ops->dump_dma_regs(ioaddr);
1100         }
1101
1102         if (priv->phydev)
1103                 phy_start(priv->phydev);
1104
1105         napi_enable(&priv->napi);
1106         skb_queue_head_init(&priv->rx_recycle);
1107         netif_start_queue(dev);
1108         return 0;
1109 }
1110
1111 /**
1112  *  stmmac_release - close entry point of the driver
1113  *  @dev : device pointer.
1114  *  Description:
1115  *  This is the stop entry point of the driver.
1116  */
1117 static int stmmac_release(struct net_device *dev)
1118 {
1119         struct stmmac_priv *priv = netdev_priv(dev);
1120
1121         /* Stop and disconnect the PHY */
1122         if (priv->phydev) {
1123                 phy_stop(priv->phydev);
1124                 phy_disconnect(priv->phydev);
1125                 priv->phydev = NULL;
1126         }
1127
1128         netif_stop_queue(dev);
1129
1130 #ifdef CONFIG_STMMAC_TIMER
1131         /* Stop and release the timer */
1132         stmmac_close_ext_timer();
1133         if (priv->tm != NULL)
1134                 kfree(priv->tm);
1135 #endif
1136         napi_disable(&priv->napi);
1137         skb_queue_purge(&priv->rx_recycle);
1138
1139         /* Free the IRQ lines */
1140         free_irq(dev->irq, dev);
1141
1142         /* Stop TX/RX DMA and clear the descriptors */
1143         stmmac_dma_stop_tx(dev->base_addr);
1144         stmmac_dma_stop_rx(dev->base_addr);
1145
1146         /* Release and free the Rx/Tx resources */
1147         free_dma_desc_resources(priv);
1148
1149         /* Disable the MAC core */
1150         stmmac_mac_disable_tx(dev->base_addr);
1151         stmmac_mac_disable_rx(dev->base_addr);
1152
1153         netif_carrier_off(dev);
1154
1155         return 0;
1156 }
1157
1158 /*
1159  * To perform emulated hardware segmentation on skb.
1160  */
1161 static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
1162 {
1163         struct sk_buff *segs, *curr_skb;
1164         int gso_segs = skb_shinfo(skb)->gso_segs;
1165
1166         /* Estimate the number of fragments in the worst case */
1167         if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
1168                 netif_stop_queue(priv->dev);
1169                 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
1170                        __func__);
1171                 if (stmmac_tx_avail(priv) < gso_segs)
1172                         return NETDEV_TX_BUSY;
1173
1174                 netif_wake_queue(priv->dev);
1175         }
1176         TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
1177                skb, skb->len);
1178
1179         segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
1180         if (unlikely(IS_ERR(segs)))
1181                 goto sw_tso_end;
1182
1183         do {
1184                 curr_skb = segs;
1185                 segs = segs->next;
1186                 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
1187                        "*next %p\n", curr_skb->len, curr_skb, segs);
1188                 curr_skb->next = NULL;
1189                 stmmac_xmit(curr_skb, priv->dev);
1190         } while (segs);
1191
1192 sw_tso_end:
1193         dev_kfree_skb(skb);
1194
1195         return NETDEV_TX_OK;
1196 }
1197
1198 static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1199                                                struct net_device *dev,
1200                                                int csum_insertion)
1201 {
1202         struct stmmac_priv *priv = netdev_priv(dev);
1203         unsigned int nopaged_len = skb_headlen(skb);
1204         unsigned int txsize = priv->dma_tx_size;
1205         unsigned int entry = priv->cur_tx % txsize;
1206         struct dma_desc *desc = priv->dma_tx + entry;
1207
1208         if (nopaged_len > BUF_SIZE_8KiB) {
1209
1210                 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1211
1212                 desc->des2 = dma_map_single(priv->device, skb->data,
1213                                             BUF_SIZE_8KiB, DMA_TO_DEVICE);
1214                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1215                 priv->mac_type->ops->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1216                                                      csum_insertion);
1217
1218                 entry = (++priv->cur_tx) % txsize;
1219                 desc = priv->dma_tx + entry;
1220
1221                 desc->des2 = dma_map_single(priv->device,
1222                                         skb->data + BUF_SIZE_8KiB,
1223                                         buf2_size, DMA_TO_DEVICE);
1224                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1225                 priv->mac_type->ops->prepare_tx_desc(desc, 0,
1226                                                      buf2_size, csum_insertion);
1227                 priv->mac_type->ops->set_tx_owner(desc);
1228                 priv->tx_skbuff[entry] = NULL;
1229         } else {
1230                 desc->des2 = dma_map_single(priv->device, skb->data,
1231                                         nopaged_len, DMA_TO_DEVICE);
1232                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1233                 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len,
1234                                                      csum_insertion);
1235         }
1236         return entry;
1237 }
1238
1239 /**
1240  *  stmmac_xmit:
1241  *  @skb : the socket buffer
1242  *  @dev : device pointer
1243  *  Description : Tx entry point of the driver.
1244  */
1245 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1246 {
1247         struct stmmac_priv *priv = netdev_priv(dev);
1248         unsigned int txsize = priv->dma_tx_size;
1249         unsigned int entry;
1250         int i, csum_insertion = 0;
1251         int nfrags = skb_shinfo(skb)->nr_frags;
1252         struct dma_desc *desc, *first;
1253
1254         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1255                 if (!netif_queue_stopped(dev)) {
1256                         netif_stop_queue(dev);
1257                         /* This is a hard error, log it. */
1258                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1259                                 __func__);
1260                 }
1261                 return NETDEV_TX_BUSY;
1262         }
1263
1264         entry = priv->cur_tx % txsize;
1265
1266 #ifdef STMMAC_XMIT_DEBUG
1267         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1268                 pr_info("stmmac xmit:\n"
1269                        "\tskb addr %p - len: %d - nopaged_len: %d\n"
1270                        "\tn_frags: %d - ip_summed: %d - %s gso\n",
1271                        skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1272                        !skb_is_gso(skb) ? "isn't" : "is");
1273 #endif
1274
1275         if (unlikely(skb_is_gso(skb)))
1276                 return stmmac_sw_tso(priv, skb);
1277
1278         if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1279                 if (likely(priv->tx_coe == NO_HW_CSUM))
1280                         skb_checksum_help(skb);
1281                 else
1282                         csum_insertion = 1;
1283         }
1284
1285         desc = priv->dma_tx + entry;
1286         first = desc;
1287
1288 #ifdef STMMAC_XMIT_DEBUG
1289         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1290                 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1291                        "\t\tn_frags: %d, ip_summed: %d\n",
1292                        skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1293 #endif
1294         priv->tx_skbuff[entry] = skb;
1295         if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1296                 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1297                 desc = priv->dma_tx + entry;
1298         } else {
1299                 unsigned int nopaged_len = skb_headlen(skb);
1300                 desc->des2 = dma_map_single(priv->device, skb->data,
1301                                         nopaged_len, DMA_TO_DEVICE);
1302                 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len,
1303                                                      csum_insertion);
1304         }
1305
1306         for (i = 0; i < nfrags; i++) {
1307                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1308                 int len = frag->size;
1309
1310                 entry = (++priv->cur_tx) % txsize;
1311                 desc = priv->dma_tx + entry;
1312
1313                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1314                 desc->des2 = dma_map_page(priv->device, frag->page,
1315                                           frag->page_offset,
1316                                           len, DMA_TO_DEVICE);
1317                 priv->tx_skbuff[entry] = NULL;
1318                 priv->mac_type->ops->prepare_tx_desc(desc, 0, len,
1319                                                      csum_insertion);
1320                 priv->mac_type->ops->set_tx_owner(desc);
1321         }
1322
1323         /* Interrupt on completition only for the latest segment */
1324         priv->mac_type->ops->close_tx_desc(desc);
1325 #ifdef CONFIG_STMMAC_TIMER
1326         /* Clean IC while using timers */
1327         priv->mac_type->ops->clear_tx_ic(desc);
1328 #endif
1329         /* To avoid raise condition */
1330         priv->mac_type->ops->set_tx_owner(first);
1331
1332         priv->cur_tx++;
1333
1334 #ifdef STMMAC_XMIT_DEBUG
1335         if (netif_msg_pktdata(priv)) {
1336                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1337                        "first=%p, nfrags=%d\n",
1338                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1339                        entry, first, nfrags);
1340                 display_ring(priv->dma_tx, txsize);
1341                 pr_info(">>> frame to be transmitted: ");
1342                 print_pkt(skb->data, skb->len);
1343         }
1344 #endif
1345         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1346                 TX_DBG("%s: stop transmitted packets\n", __func__);
1347                 netif_stop_queue(dev);
1348         }
1349
1350         dev->stats.tx_bytes += skb->len;
1351
1352         /* CSR1 enables the transmit DMA to check for new descriptor */
1353         writel(1, dev->base_addr + DMA_XMT_POLL_DEMAND);
1354
1355         return NETDEV_TX_OK;
1356 }
1357
1358 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1359 {
1360         unsigned int rxsize = priv->dma_rx_size;
1361         int bfsize = priv->dma_buf_sz;
1362         struct dma_desc *p = priv->dma_rx;
1363
1364         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1365                 unsigned int entry = priv->dirty_rx % rxsize;
1366                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1367                         struct sk_buff *skb;
1368
1369                         skb = __skb_dequeue(&priv->rx_recycle);
1370                         if (skb == NULL)
1371                                 skb = netdev_alloc_skb_ip_align(priv->dev,
1372                                                                 bfsize);
1373
1374                         if (unlikely(skb == NULL))
1375                                 break;
1376
1377                         priv->rx_skbuff[entry] = skb;
1378                         priv->rx_skbuff_dma[entry] =
1379                             dma_map_single(priv->device, skb->data, bfsize,
1380                                            DMA_FROM_DEVICE);
1381
1382                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1383                         if (unlikely(priv->is_gmac)) {
1384                                 if (bfsize >= BUF_SIZE_8KiB)
1385                                         (p + entry)->des3 =
1386                                             (p + entry)->des2 + BUF_SIZE_8KiB;
1387                         }
1388                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1389                 }
1390                 priv->mac_type->ops->set_rx_owner(p + entry);
1391         }
1392         return;
1393 }
1394
1395 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1396 {
1397         unsigned int rxsize = priv->dma_rx_size;
1398         unsigned int entry = priv->cur_rx % rxsize;
1399         unsigned int next_entry;
1400         unsigned int count = 0;
1401         struct dma_desc *p = priv->dma_rx + entry;
1402         struct dma_desc *p_next;
1403
1404 #ifdef STMMAC_RX_DEBUG
1405         if (netif_msg_hw(priv)) {
1406                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1407                 display_ring(priv->dma_rx, rxsize);
1408         }
1409 #endif
1410         count = 0;
1411         while (!priv->mac_type->ops->get_rx_owner(p)) {
1412                 int status;
1413
1414                 if (count >= limit)
1415                         break;
1416
1417                 count++;
1418
1419                 next_entry = (++priv->cur_rx) % rxsize;
1420                 p_next = priv->dma_rx + next_entry;
1421                 prefetch(p_next);
1422
1423                 /* read the status of the incoming frame */
1424                 status = (priv->mac_type->ops->rx_status(&priv->dev->stats,
1425                                                          &priv->xstats, p));
1426                 if (unlikely(status == discard_frame))
1427                         priv->dev->stats.rx_errors++;
1428                 else {
1429                         struct sk_buff *skb;
1430                         /* Length should omit the CRC */
1431                         int frame_len =
1432                             priv->mac_type->ops->get_rx_frame_len(p) - 4;
1433
1434 #ifdef STMMAC_RX_DEBUG
1435                         if (frame_len > ETH_FRAME_LEN)
1436                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1437                                         frame_len, status);
1438
1439                         if (netif_msg_hw(priv))
1440                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1441                                         p, entry, p->des2);
1442 #endif
1443                         skb = priv->rx_skbuff[entry];
1444                         if (unlikely(!skb)) {
1445                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1446                                         priv->dev->name);
1447                                 priv->dev->stats.rx_dropped++;
1448                                 break;
1449                         }
1450                         prefetch(skb->data - NET_IP_ALIGN);
1451                         priv->rx_skbuff[entry] = NULL;
1452
1453                         skb_put(skb, frame_len);
1454                         dma_unmap_single(priv->device,
1455                                          priv->rx_skbuff_dma[entry],
1456                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1457 #ifdef STMMAC_RX_DEBUG
1458                         if (netif_msg_pktdata(priv)) {
1459                                 pr_info(" frame received (%dbytes)", frame_len);
1460                                 print_pkt(skb->data, frame_len);
1461                         }
1462 #endif
1463                         skb->protocol = eth_type_trans(skb, priv->dev);
1464
1465                         if (unlikely(status == csum_none)) {
1466                                 /* always for the old mac 10/100 */
1467                                 skb->ip_summed = CHECKSUM_NONE;
1468                                 netif_receive_skb(skb);
1469                         } else {
1470                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1471                                 napi_gro_receive(&priv->napi, skb);
1472                         }
1473
1474                         priv->dev->stats.rx_packets++;
1475                         priv->dev->stats.rx_bytes += frame_len;
1476                         priv->dev->last_rx = jiffies;
1477                 }
1478                 entry = next_entry;
1479                 p = p_next;     /* use prefetched values */
1480         }
1481
1482         stmmac_rx_refill(priv);
1483
1484         priv->xstats.rx_pkt_n += count;
1485
1486         return count;
1487 }
1488
1489 /**
1490  *  stmmac_poll - stmmac poll method (NAPI)
1491  *  @napi : pointer to the napi structure.
1492  *  @budget : maximum number of packets that the current CPU can receive from
1493  *            all interfaces.
1494  *  Description :
1495  *   This function implements the the reception process.
1496  *   Also it runs the TX completion thread
1497  */
1498 static int stmmac_poll(struct napi_struct *napi, int budget)
1499 {
1500         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1501         int work_done = 0;
1502
1503         priv->xstats.poll_n++;
1504         stmmac_tx(priv);
1505         work_done = stmmac_rx(priv, budget);
1506
1507         if (work_done < budget) {
1508                 napi_complete(napi);
1509                 stmmac_enable_irq(priv);
1510         }
1511         return work_done;
1512 }
1513
1514 /**
1515  *  stmmac_tx_timeout
1516  *  @dev : Pointer to net device structure
1517  *  Description: this function is called when a packet transmission fails to
1518  *   complete within a reasonable tmrate. The driver will mark the error in the
1519  *   netdev structure and arrange for the device to be reset to a sane state
1520  *   in order to transmit a new packet.
1521  */
1522 static void stmmac_tx_timeout(struct net_device *dev)
1523 {
1524         struct stmmac_priv *priv = netdev_priv(dev);
1525
1526         /* Clear Tx resources and restart transmitting again */
1527         stmmac_tx_err(priv);
1528         return;
1529 }
1530
1531 /* Configuration changes (passed on by ifconfig) */
1532 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1533 {
1534         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1535                 return -EBUSY;
1536
1537         /* Don't allow changing the I/O address */
1538         if (map->base_addr != dev->base_addr) {
1539                 pr_warning("%s: can't change I/O address\n", dev->name);
1540                 return -EOPNOTSUPP;
1541         }
1542
1543         /* Don't allow changing the IRQ */
1544         if (map->irq != dev->irq) {
1545                 pr_warning("%s: can't change IRQ number %d\n",
1546                        dev->name, dev->irq);
1547                 return -EOPNOTSUPP;
1548         }
1549
1550         /* ignore other fields */
1551         return 0;
1552 }
1553
1554 /**
1555  *  stmmac_multicast_list - entry point for multicast addressing
1556  *  @dev : pointer to the device structure
1557  *  Description:
1558  *  This function is a driver entry point which gets called by the kernel
1559  *  whenever multicast addresses must be enabled/disabled.
1560  *  Return value:
1561  *  void.
1562  */
1563 static void stmmac_multicast_list(struct net_device *dev)
1564 {
1565         struct stmmac_priv *priv = netdev_priv(dev);
1566
1567         spin_lock(&priv->lock);
1568         priv->mac_type->ops->set_filter(dev);
1569         spin_unlock(&priv->lock);
1570         return;
1571 }
1572
1573 /**
1574  *  stmmac_change_mtu - entry point to change MTU size for the device.
1575  *  @dev : device pointer.
1576  *  @new_mtu : the new MTU size for the device.
1577  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1578  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1579  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1580  *  Return value:
1581  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1582  *  file on failure.
1583  */
1584 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1585 {
1586         struct stmmac_priv *priv = netdev_priv(dev);
1587         int max_mtu;
1588
1589         if (netif_running(dev)) {
1590                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1591                 return -EBUSY;
1592         }
1593
1594         if (priv->is_gmac)
1595                 max_mtu = JUMBO_LEN;
1596         else
1597                 max_mtu = ETH_DATA_LEN;
1598
1599         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1600                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1601                 return -EINVAL;
1602         }
1603
1604         dev->mtu = new_mtu;
1605
1606         return 0;
1607 }
1608
1609 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1610 {
1611         struct net_device *dev = (struct net_device *)dev_id;
1612         struct stmmac_priv *priv = netdev_priv(dev);
1613
1614         if (unlikely(!dev)) {
1615                 pr_err("%s: invalid dev pointer\n", __func__);
1616                 return IRQ_NONE;
1617         }
1618
1619         if (priv->is_gmac) {
1620                 unsigned long ioaddr = dev->base_addr;
1621                 /* To handle GMAC own interrupts */
1622                 priv->mac_type->ops->host_irq_status(ioaddr);
1623         }
1624         stmmac_dma_interrupt(dev);
1625
1626         return IRQ_HANDLED;
1627 }
1628
1629 #ifdef CONFIG_NET_POLL_CONTROLLER
1630 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1631  * to allow network I/O with interrupts disabled. */
1632 static void stmmac_poll_controller(struct net_device *dev)
1633 {
1634         disable_irq(dev->irq);
1635         stmmac_interrupt(dev->irq, dev);
1636         enable_irq(dev->irq);
1637 }
1638 #endif
1639
1640 /**
1641  *  stmmac_ioctl - Entry point for the Ioctl
1642  *  @dev: Device pointer.
1643  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1644  *  a proprietary structure used to pass information to the driver.
1645  *  @cmd: IOCTL command
1646  *  Description:
1647  *  Currently there are no special functionality supported in IOCTL, just the
1648  *  phy_mii_ioctl(...) can be invoked.
1649  */
1650 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1651 {
1652         struct stmmac_priv *priv = netdev_priv(dev);
1653         int ret = -EOPNOTSUPP;
1654
1655         if (!netif_running(dev))
1656                 return -EINVAL;
1657
1658         switch (cmd) {
1659         case SIOCGMIIPHY:
1660         case SIOCGMIIREG:
1661         case SIOCSMIIREG:
1662                 if (!priv->phydev)
1663                         return -EINVAL;
1664
1665                 spin_lock(&priv->lock);
1666                 ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1667                 spin_unlock(&priv->lock);
1668         default:
1669                 break;
1670         }
1671         return ret;
1672 }
1673
1674 #ifdef STMMAC_VLAN_TAG_USED
1675 static void stmmac_vlan_rx_register(struct net_device *dev,
1676                                     struct vlan_group *grp)
1677 {
1678         struct stmmac_priv *priv = netdev_priv(dev);
1679
1680         DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1681
1682         spin_lock(&priv->lock);
1683         priv->vlgrp = grp;
1684         spin_unlock(&priv->lock);
1685
1686         return;
1687 }
1688 #endif
1689
1690 static const struct net_device_ops stmmac_netdev_ops = {
1691         .ndo_open = stmmac_open,
1692         .ndo_start_xmit = stmmac_xmit,
1693         .ndo_stop = stmmac_release,
1694         .ndo_change_mtu = stmmac_change_mtu,
1695         .ndo_set_multicast_list = stmmac_multicast_list,
1696         .ndo_tx_timeout = stmmac_tx_timeout,
1697         .ndo_do_ioctl = stmmac_ioctl,
1698         .ndo_set_config = stmmac_config,
1699 #ifdef STMMAC_VLAN_TAG_USED
1700         .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1701 #endif
1702 #ifdef CONFIG_NET_POLL_CONTROLLER
1703         .ndo_poll_controller = stmmac_poll_controller,
1704 #endif
1705         .ndo_set_mac_address = eth_mac_addr,
1706 };
1707
1708 /**
1709  * stmmac_probe - Initialization of the adapter .
1710  * @dev : device pointer
1711  * Description: The function initializes the network device structure for
1712  * the STMMAC driver. It also calls the low level routines
1713  * in order to init the HW (i.e. the DMA engine)
1714  */
1715 static int stmmac_probe(struct net_device *dev)
1716 {
1717         int ret = 0;
1718         struct stmmac_priv *priv = netdev_priv(dev);
1719
1720         ether_setup(dev);
1721
1722         dev->netdev_ops = &stmmac_netdev_ops;
1723         stmmac_set_ethtool_ops(dev);
1724
1725         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1726         dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1727 #ifdef STMMAC_VLAN_TAG_USED
1728         /* Both mac100 and gmac support receive VLAN tag detection */
1729         dev->features |= NETIF_F_HW_VLAN_RX;
1730 #endif
1731         priv->msg_enable = netif_msg_init(debug, default_msg_level);
1732
1733         if (priv->is_gmac)
1734                 priv->rx_csum = 1;
1735
1736         if (flow_ctrl)
1737                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
1738
1739         priv->pause = pause;
1740         netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1741
1742         /* Get the MAC address */
1743         priv->mac_type->ops->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
1744
1745         if (!is_valid_ether_addr(dev->dev_addr))
1746                 pr_warning("\tno valid MAC address;"
1747                         "please, use ifconfig or nwhwconfig!\n");
1748
1749         ret = register_netdev(dev);
1750         if (ret) {
1751                 pr_err("%s: ERROR %i registering the device\n",
1752                        __func__, ret);
1753                 return -ENODEV;
1754         }
1755
1756         DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1757             dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1758             (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1759
1760         spin_lock_init(&priv->lock);
1761
1762         return ret;
1763 }
1764
1765 /**
1766  * stmmac_mac_device_setup
1767  * @dev : device pointer
1768  * Description: select and initialise the mac device (mac100 or Gmac).
1769  */
1770 static int stmmac_mac_device_setup(struct net_device *dev)
1771 {
1772         struct stmmac_priv *priv = netdev_priv(dev);
1773         unsigned long ioaddr = dev->base_addr;
1774
1775         struct mac_device_info *device;
1776
1777         if (priv->is_gmac)
1778                 device = gmac_setup(ioaddr);
1779         else
1780                 device = mac100_setup(ioaddr);
1781
1782         if (!device)
1783                 return -ENOMEM;
1784
1785         priv->mac_type = device;
1786
1787         priv->wolenabled = priv->mac_type->hw.pmt;      /* PMT supported */
1788         if (priv->wolenabled == PMT_SUPPORTED)
1789                 priv->wolopts = WAKE_MAGIC;             /* Magic Frame */
1790
1791         return 0;
1792 }
1793
1794 static int stmmacphy_dvr_probe(struct platform_device *pdev)
1795 {
1796         struct plat_stmmacphy_data *plat_dat;
1797         plat_dat = (struct plat_stmmacphy_data *)((pdev->dev).platform_data);
1798
1799         pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1800                plat_dat->bus_id);
1801
1802         return 0;
1803 }
1804
1805 static int stmmacphy_dvr_remove(struct platform_device *pdev)
1806 {
1807         return 0;
1808 }
1809
1810 static struct platform_driver stmmacphy_driver = {
1811         .driver = {
1812                    .name = PHY_RESOURCE_NAME,
1813                    },
1814         .probe = stmmacphy_dvr_probe,
1815         .remove = stmmacphy_dvr_remove,
1816 };
1817
1818 /**
1819  * stmmac_associate_phy
1820  * @dev: pointer to device structure
1821  * @data: points to the private structure.
1822  * Description: Scans through all the PHYs we have registered and checks if
1823  * any are associated with our MAC.  If so, then just fill in
1824  * the blanks in our local context structure
1825  */
1826 static int stmmac_associate_phy(struct device *dev, void *data)
1827 {
1828         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1829         struct plat_stmmacphy_data *plat_dat;
1830
1831         plat_dat = (struct plat_stmmacphy_data *)(dev->platform_data);
1832
1833         DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1834                 plat_dat->bus_id);
1835
1836         /* Check that this phy is for the MAC being initialised */
1837         if (priv->bus_id != plat_dat->bus_id)
1838                 return 0;
1839
1840         /* OK, this PHY is connected to the MAC.
1841            Go ahead and get the parameters */
1842         DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1843         priv->phy_irq =
1844             platform_get_irq_byname(to_platform_device(dev), "phyirq");
1845         DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1846             plat_dat->bus_id, priv->phy_irq);
1847
1848         /* Override with kernel parameters if supplied XXX CRS XXX
1849          * this needs to have multiple instances */
1850         if ((phyaddr >= 0) && (phyaddr <= 31))
1851                 plat_dat->phy_addr = phyaddr;
1852
1853         priv->phy_addr = plat_dat->phy_addr;
1854         priv->phy_mask = plat_dat->phy_mask;
1855         priv->phy_interface = plat_dat->interface;
1856         priv->phy_reset = plat_dat->phy_reset;
1857
1858         DBG(probe, DEBUG, "%s: exiting\n", __func__);
1859         return 1;       /* forces exit of driver_for_each_device() */
1860 }
1861
1862 /**
1863  * stmmac_dvr_probe
1864  * @pdev: platform device pointer
1865  * Description: the driver is initialized through platform_device.
1866  */
1867 static int stmmac_dvr_probe(struct platform_device *pdev)
1868 {
1869         int ret = 0;
1870         struct resource *res;
1871         unsigned int *addr = NULL;
1872         struct net_device *ndev = NULL;
1873         struct stmmac_priv *priv;
1874         struct plat_stmmacenet_data *plat_dat;
1875
1876         pr_info("STMMAC driver:\n\tplatform registration... ");
1877         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1878         if (!res) {
1879                 ret = -ENODEV;
1880                 goto out;
1881         }
1882         pr_info("done!\n");
1883
1884         if (!request_mem_region(res->start, (res->end - res->start),
1885                                 pdev->name)) {
1886                 pr_err("%s: ERROR: memory allocation failed"
1887                        "cannot get the I/O addr 0x%x\n",
1888                        __func__, (unsigned int)res->start);
1889                 ret = -EBUSY;
1890                 goto out;
1891         }
1892
1893         addr = ioremap(res->start, (res->end - res->start));
1894         if (!addr) {
1895                 pr_err("%s: ERROR: memory mapping failed \n", __func__);
1896                 ret = -ENOMEM;
1897                 goto out;
1898         }
1899
1900         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1901         if (!ndev) {
1902                 pr_err("%s: ERROR: allocating the device\n", __func__);
1903                 ret = -ENOMEM;
1904                 goto out;
1905         }
1906
1907         SET_NETDEV_DEV(ndev, &pdev->dev);
1908
1909         /* Get the MAC information */
1910         ndev->irq = platform_get_irq_byname(pdev, "macirq");
1911         if (ndev->irq == -ENXIO) {
1912                 pr_err("%s: ERROR: MAC IRQ configuration "
1913                        "information not found\n", __func__);
1914                 ret = -ENODEV;
1915                 goto out;
1916         }
1917
1918         priv = netdev_priv(ndev);
1919         priv->device = &(pdev->dev);
1920         priv->dev = ndev;
1921         plat_dat = (struct plat_stmmacenet_data *)((pdev->dev).platform_data);
1922         priv->bus_id = plat_dat->bus_id;
1923         priv->pbl = plat_dat->pbl;      /* TLI */
1924         priv->is_gmac = plat_dat->has_gmac;     /* GMAC is on board */
1925
1926         platform_set_drvdata(pdev, ndev);
1927
1928         /* Set the I/O base addr */
1929         ndev->base_addr = (unsigned long)addr;
1930
1931         /* MAC HW revice detection */
1932         ret = stmmac_mac_device_setup(ndev);
1933         if (ret < 0)
1934                 goto out;
1935
1936         /* Network Device Registration */
1937         ret = stmmac_probe(ndev);
1938         if (ret < 0)
1939                 goto out;
1940
1941         /* associate a PHY - it is provided by another platform bus */
1942         if (!driver_for_each_device
1943             (&(stmmacphy_driver.driver), NULL, (void *)priv,
1944              stmmac_associate_phy)) {
1945                 pr_err("No PHY device is associated with this MAC!\n");
1946                 ret = -ENODEV;
1947                 goto out;
1948         }
1949
1950         priv->fix_mac_speed = plat_dat->fix_mac_speed;
1951         priv->bsp_priv = plat_dat->bsp_priv;
1952
1953         pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1954                "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1955                pdev->id, ndev->irq, (unsigned int)addr);
1956
1957         /* MDIO bus Registration */
1958         pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1959         ret = stmmac_mdio_register(ndev);
1960         if (ret < 0)
1961                 goto out;
1962         pr_debug("registered!\n");
1963
1964 out:
1965         if (ret < 0) {
1966                 platform_set_drvdata(pdev, NULL);
1967                 release_mem_region(res->start, (res->end - res->start));
1968                 if (addr != NULL)
1969                         iounmap(addr);
1970         }
1971
1972         return ret;
1973 }
1974
1975 /**
1976  * stmmac_dvr_remove
1977  * @pdev: platform device pointer
1978  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1979  * changes the link status, releases the DMA descriptor rings,
1980  * unregisters the MDIO bus and unmaps the allocated memory.
1981  */
1982 static int stmmac_dvr_remove(struct platform_device *pdev)
1983 {
1984         struct net_device *ndev = platform_get_drvdata(pdev);
1985         struct resource *res;
1986
1987         pr_info("%s:\n\tremoving driver", __func__);
1988
1989         stmmac_dma_stop_rx(ndev->base_addr);
1990         stmmac_dma_stop_tx(ndev->base_addr);
1991
1992         stmmac_mac_disable_rx(ndev->base_addr);
1993         stmmac_mac_disable_tx(ndev->base_addr);
1994
1995         netif_carrier_off(ndev);
1996
1997         stmmac_mdio_unregister(ndev);
1998
1999         platform_set_drvdata(pdev, NULL);
2000         unregister_netdev(ndev);
2001
2002         iounmap((void *)ndev->base_addr);
2003         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2004         release_mem_region(res->start, (res->end - res->start));
2005
2006         free_netdev(ndev);
2007
2008         return 0;
2009 }
2010
2011 #ifdef CONFIG_PM
2012 static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
2013 {
2014         struct net_device *dev = platform_get_drvdata(pdev);
2015         struct stmmac_priv *priv = netdev_priv(dev);
2016         int dis_ic = 0;
2017
2018         if (!dev || !netif_running(dev))
2019                 return 0;
2020
2021         spin_lock(&priv->lock);
2022
2023         if (state.event == PM_EVENT_SUSPEND) {
2024                 netif_device_detach(dev);
2025                 netif_stop_queue(dev);
2026                 if (priv->phydev)
2027                         phy_stop(priv->phydev);
2028
2029 #ifdef CONFIG_STMMAC_TIMER
2030                 priv->tm->timer_stop();
2031                 dis_ic = 1;
2032 #endif
2033                 napi_disable(&priv->napi);
2034
2035                 /* Stop TX/RX DMA */
2036                 stmmac_dma_stop_tx(dev->base_addr);
2037                 stmmac_dma_stop_rx(dev->base_addr);
2038                 /* Clear the Rx/Tx descriptors */
2039                 priv->mac_type->ops->init_rx_desc(priv->dma_rx,
2040                                                   priv->dma_rx_size, dis_ic);
2041                 priv->mac_type->ops->init_tx_desc(priv->dma_tx,
2042                                                   priv->dma_tx_size);
2043
2044                 stmmac_mac_disable_tx(dev->base_addr);
2045
2046                 if (device_may_wakeup(&(pdev->dev))) {
2047                         /* Enable Power down mode by programming the PMT regs */
2048                         if (priv->wolenabled == PMT_SUPPORTED)
2049                                 priv->mac_type->ops->pmt(dev->base_addr,
2050                                                          priv->wolopts);
2051                 } else {
2052                         stmmac_mac_disable_rx(dev->base_addr);
2053                 }
2054         } else {
2055                 priv->shutdown = 1;
2056                 /* Although this can appear slightly redundant it actually
2057                  * makes fast the standby operation and guarantees the driver
2058                  * working if hibernation is on media. */
2059                 stmmac_release(dev);
2060         }
2061
2062         spin_unlock(&priv->lock);
2063         return 0;
2064 }
2065
2066 static int stmmac_resume(struct platform_device *pdev)
2067 {
2068         struct net_device *dev = platform_get_drvdata(pdev);
2069         struct stmmac_priv *priv = netdev_priv(dev);
2070         unsigned long ioaddr = dev->base_addr;
2071
2072         if (!netif_running(dev))
2073                 return 0;
2074
2075         spin_lock(&priv->lock);
2076
2077         if (priv->shutdown) {
2078                 /* Re-open the interface and re-init the MAC/DMA
2079                    and the rings. */
2080                 stmmac_open(dev);
2081                 goto out_resume;
2082         }
2083
2084         /* Power Down bit, into the PM register, is cleared
2085          * automatically as soon as a magic packet or a Wake-up frame
2086          * is received. Anyway, it's better to manually clear
2087          * this bit because it can generate problems while resuming
2088          * from another devices (e.g. serial console). */
2089         if (device_may_wakeup(&(pdev->dev)))
2090                 if (priv->wolenabled == PMT_SUPPORTED)
2091                         priv->mac_type->ops->pmt(dev->base_addr, 0);
2092
2093         netif_device_attach(dev);
2094
2095         /* Enable the MAC and DMA */
2096         stmmac_mac_enable_rx(ioaddr);
2097         stmmac_mac_enable_tx(ioaddr);
2098         stmmac_dma_start_tx(ioaddr);
2099         stmmac_dma_start_rx(ioaddr);
2100
2101 #ifdef CONFIG_STMMAC_TIMER
2102         priv->tm->timer_start(tmrate);
2103 #endif
2104         napi_enable(&priv->napi);
2105
2106         if (priv->phydev)
2107                 phy_start(priv->phydev);
2108
2109         netif_start_queue(dev);
2110
2111 out_resume:
2112         spin_unlock(&priv->lock);
2113         return 0;
2114 }
2115 #endif
2116
2117 static struct platform_driver stmmac_driver = {
2118         .driver = {
2119                    .name = STMMAC_RESOURCE_NAME,
2120                    },
2121         .probe = stmmac_dvr_probe,
2122         .remove = stmmac_dvr_remove,
2123 #ifdef CONFIG_PM
2124         .suspend = stmmac_suspend,
2125         .resume = stmmac_resume,
2126 #endif
2127
2128 };
2129
2130 /**
2131  * stmmac_init_module - Entry point for the driver
2132  * Description: This function is the entry point for the driver.
2133  */
2134 static int __init stmmac_init_module(void)
2135 {
2136         int ret;
2137
2138         if (platform_driver_register(&stmmacphy_driver)) {
2139                 pr_err("No PHY devices registered!\n");
2140                 return -ENODEV;
2141         }
2142
2143         ret = platform_driver_register(&stmmac_driver);
2144         return ret;
2145 }
2146
2147 /**
2148  * stmmac_cleanup_module - Cleanup routine for the driver
2149  * Description: This function is the cleanup routine for the driver.
2150  */
2151 static void __exit stmmac_cleanup_module(void)
2152 {
2153         platform_driver_unregister(&stmmacphy_driver);
2154         platform_driver_unregister(&stmmac_driver);
2155 }
2156
2157 #ifndef MODULE
2158 static int __init stmmac_cmdline_opt(char *str)
2159 {
2160         char *opt;
2161
2162         if (!str || !*str)
2163                 return -EINVAL;
2164         while ((opt = strsep(&str, ",")) != NULL) {
2165                 if (!strncmp(opt, "debug:", 6))
2166                         strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
2167                 else if (!strncmp(opt, "phyaddr:", 8))
2168                         strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
2169                 else if (!strncmp(opt, "dma_txsize:", 11))
2170                         strict_strtoul(opt + 11, 0,
2171                                        (unsigned long *)&dma_txsize);
2172                 else if (!strncmp(opt, "dma_rxsize:", 11))
2173                         strict_strtoul(opt + 11, 0,
2174                                        (unsigned long *)&dma_rxsize);
2175                 else if (!strncmp(opt, "buf_sz:", 7))
2176                         strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
2177                 else if (!strncmp(opt, "tc:", 3))
2178                         strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
2179                 else if (!strncmp(opt, "tx_coe:", 7))
2180                         strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
2181                 else if (!strncmp(opt, "watchdog:", 9))
2182                         strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
2183                 else if (!strncmp(opt, "flow_ctrl:", 10))
2184                         strict_strtoul(opt + 10, 0,
2185                                        (unsigned long *)&flow_ctrl);
2186                 else if (!strncmp(opt, "pause:", 6))
2187                         strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
2188 #ifdef CONFIG_STMMAC_TIMER
2189                 else if (!strncmp(opt, "tmrate:", 7))
2190                         strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
2191 #endif
2192         }
2193         return 0;
2194 }
2195
2196 __setup("stmmaceth=", stmmac_cmdline_opt);
2197 #endif
2198
2199 module_init(stmmac_init_module);
2200 module_exit(stmmac_cleanup_module);
2201
2202 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2203 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2204 MODULE_LICENSE("GPL");