1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/crc32.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
45 #include <linux/firmware.h>
46 #include <asm/processor.h> /* Processor type for cache alignment. */
47 #include <asm/uaccess.h>
51 * The current frame processor firmware fails to checksum a fragment
52 * of length 1. If and when this is fixed, the #define below can be removed.
54 #define HAS_BROKEN_FIRMWARE
57 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 #ifdef HAS_BROKEN_FIRMWARE
60 #define PADDING_MASK 3
64 * Define this if using the driver with the zero-copy patch
68 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72 /* The user-configurable values.
73 These may be modified when a driver module is loaded.*/
75 /* Used for tuning interrupt latency vs. overhead. */
76 static int intr_latency;
77 static int small_frames;
79 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
80 static int max_interrupt_work = 20;
82 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
83 The Starfire has a 512 element hash table based on the Ethernet CRC. */
84 static const int multicast_filter_limit = 512;
85 /* Whether to do TCP/UDP checksums in hardware */
86 static int enable_hw_cksum = 1;
88 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
90 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
91 * Setting to > 1518 effectively disables this feature.
94 * The ia64 doesn't allow for unaligned loads even of integers being
95 * misaligned on a 2 byte boundary. Thus always force copying of
96 * packets as the starfire doesn't allow for misaligned DMAs ;-(
99 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
100 * at least, having unaligned frames leads to a rather serious performance
103 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
104 static int rx_copybreak = PKT_BUF_SZ;
106 static int rx_copybreak /* = 0 */;
109 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
111 #define DMA_BURST_SIZE 64
113 #define DMA_BURST_SIZE 128
116 /* Used to pass the media type, etc.
117 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
118 The media type is usually passed in 'options[]'.
119 These variables are deprecated, use ethtool instead. -Ion
121 #define MAX_UNITS 8 /* More are supported, limit only on options */
122 static int options[MAX_UNITS] = {0, };
123 static int full_duplex[MAX_UNITS] = {0, };
125 /* Operational parameters that are set at compile time. */
127 /* The "native" ring sizes are either 256 or 2048.
128 However in some modes a descriptor may be marked to wrap the ring earlier.
130 #define RX_RING_SIZE 256
131 #define TX_RING_SIZE 32
132 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
133 #define DONE_Q_SIZE 1024
134 /* All queues must be aligned on a 256-byte boundary */
135 #define QUEUE_ALIGN 256
137 #if RX_RING_SIZE > 256
138 #define RX_Q_ENTRIES Rx2048QEntries
140 #define RX_Q_ENTRIES Rx256QEntries
143 /* Operational parameters that usually are not changed. */
144 /* Time in jiffies before concluding the transmitter is hung. */
145 #define TX_TIMEOUT (2 * HZ)
149 * We need a much better method to determine if dma_addr_t is 64-bit.
151 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
152 /* 64-bit dma_addr_t */
153 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
154 #define netdrv_addr_t __le64
155 #define cpu_to_dma(x) cpu_to_le64(x)
156 #define dma_to_cpu(x) le64_to_cpu(x)
157 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
158 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
159 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
160 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
161 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
162 #else /* 32-bit dma_addr_t */
163 #define netdrv_addr_t __le32
164 #define cpu_to_dma(x) cpu_to_le32(x)
165 #define dma_to_cpu(x) le32_to_cpu(x)
166 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
167 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
168 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
169 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
170 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
173 #define skb_first_frag_len(skb) skb_headlen(skb)
174 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
177 #define FIRMWARE_RX "adaptec/starfire_rx.bin"
178 #define FIRMWARE_TX "adaptec/starfire_tx.bin"
180 /* These identify the driver base version and may not be removed. */
181 static const char version[] __devinitconst =
182 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
183 " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
185 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
186 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
187 MODULE_LICENSE("GPL");
188 MODULE_VERSION(DRV_VERSION);
189 MODULE_FIRMWARE(FIRMWARE_RX);
190 MODULE_FIRMWARE(FIRMWARE_TX);
192 module_param(max_interrupt_work, int, 0);
193 module_param(mtu, int, 0);
194 module_param(debug, int, 0);
195 module_param(rx_copybreak, int, 0);
196 module_param(intr_latency, int, 0);
197 module_param(small_frames, int, 0);
198 module_param_array(options, int, NULL, 0);
199 module_param_array(full_duplex, int, NULL, 0);
200 module_param(enable_hw_cksum, int, 0);
201 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
202 MODULE_PARM_DESC(mtu, "MTU (all boards)");
203 MODULE_PARM_DESC(debug, "Debug level (0-6)");
204 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
205 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
206 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
207 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
208 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
209 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
214 I. Board Compatibility
216 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
218 II. Board-specific settings
220 III. Driver operation
224 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
225 ring sizes are set fixed by the hardware, but may optionally be wrapped
226 earlier by the END bit in the descriptor.
227 This driver uses that hardware queue size for the Rx ring, where a large
228 number of entries has no ill effect beyond increases the potential backlog.
229 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
230 disables the queue layer priority ordering and we have no mechanism to
231 utilize the hardware two-level priority queue. When modifying the
232 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
235 IIIb/c. Transmit/Receive Structure
237 See the Adaptec manual for the many possible structures, and options for
238 each structure. There are far too many to document all of them here.
240 For transmit this driver uses type 0/1 transmit descriptors (depending
241 on the 32/64 bitness of the architecture), and relies on automatic
242 minimum-length padding. It does not use the completion queue
243 consumer index, but instead checks for non-zero status entries.
245 For receive this driver uses type 2/3 receive descriptors. The driver
246 allocates full frame size skbuffs for the Rx ring buffers, so all frames
247 should fit in a single descriptor. The driver does not use the completion
248 queue consumer index, but instead checks for non-zero status entries.
250 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
251 is allocated and the frame is copied to the new skbuff. When the incoming
252 frame is larger, the skbuff is passed directly up the protocol stack.
253 Buffers consumed this way are replaced by newly allocated skbuffs in a later
256 A notable aspect of operation is that unaligned buffers are not permitted by
257 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
258 isn't longword aligned, which may cause problems on some machine
259 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
260 the frame into a new skbuff unconditionally. Copied frames are put into the
261 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
263 IIId. Synchronization
265 The driver runs as two independent, single-threaded flows of control. One
266 is the send-packet routine, which enforces single-threaded use by the
267 dev->tbusy flag. The other thread is the interrupt handler, which is single
268 threaded by the hardware and interrupt handling software.
270 The send packet thread has partial control over the Tx ring and the netif_queue
271 status. If the number of free Tx slots in the ring falls below a certain number
272 (currently hardcoded to 4), it signals the upper layer to stop the queue.
274 The interrupt handler has exclusive control over the Rx ring and records stats
275 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
276 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
277 number of free Tx slow is above the threshold, it signals the upper layer to
284 The Adaptec Starfire manuals, available only from Adaptec.
285 http://www.scyld.com/expert/100mbps.html
286 http://www.scyld.com/expert/NWay.html
290 - StopOnPerr is broken, don't enable
291 - Hardware ethernet padding exposes random data, perform software padding
292 instead (unverified -- works correctly for all the hardware I have)
298 enum chip_capability_flags {CanHaveMII=1, };
304 static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = {
305 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
308 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
310 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
311 static const struct chip_info {
314 } netdrv_tbl[] __devinitdata = {
315 { "Adaptec Starfire 6915", CanHaveMII },
319 /* Offsets to the device registers.
320 Unlike software-only systems, device drivers interact with complex hardware.
321 It's not useful to define symbolic names for every register bit in the
322 device. The name can only partially document the semantics and make
323 the driver longer and more difficult to read.
324 In general, only the important configuration values or bits changed
325 multiple times should be defined symbolically.
327 enum register_offsets {
328 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
329 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
330 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
331 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
332 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
333 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
334 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
336 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
337 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
338 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
339 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
340 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
341 TxMode=0x55000, VlanType=0x55064,
342 PerfFilterTable=0x56000, HashTable=0x56100,
343 TxGfpMem=0x58000, RxGfpMem=0x5a000,
347 * Bits in the interrupt status/mask registers.
348 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
349 * enables all the interrupt sources that are or'ed into those status bits.
351 enum intr_status_bits {
352 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
353 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
354 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
355 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
356 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
357 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
358 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
359 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
360 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
361 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
362 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
363 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
364 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
365 IntrTxGfp=0x02, IntrPCIPad=0x01,
367 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
368 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
369 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
372 /* Bits in the RxFilterMode register. */
374 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
375 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
376 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
380 /* Bits in the TxMode register */
382 MiiSoftReset=0x8000, MIILoopback=0x4000,
383 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
384 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
387 /* Bits in the TxDescCtrl register. */
389 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
390 TxDescSpace128=0x30, TxDescSpace256=0x40,
391 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
392 TxDescType3=0x03, TxDescType4=0x04,
393 TxNoDMACompletion=0x08,
394 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
395 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
396 TxDMABurstSizeShift=8,
399 /* Bits in the RxDescQCtrl register. */
401 RxBufferLenShift=16, RxMinDescrThreshShift=0,
402 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
403 Rx2048QEntries=0x4000, Rx256QEntries=0,
404 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
405 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
406 RxDescSpace4=0x000, RxDescSpace8=0x100,
407 RxDescSpace16=0x200, RxDescSpace32=0x300,
408 RxDescSpace64=0x400, RxDescSpace128=0x500,
412 /* Bits in the RxDMACtrl register. */
413 enum rx_dmactrl_bits {
414 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
415 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
416 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
417 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
418 RxChecksumRejectTCPOnly=0x01000000,
419 RxCompletionQ2Enable=0x800000,
420 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
421 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
422 RxDMAQ2NonIP=0x400000,
423 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
424 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
428 /* Bits in the RxCompletionAddr register */
430 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
431 RxComplProducerWrEn=0x40,
432 RxComplType0=0x00, RxComplType1=0x10,
433 RxComplType2=0x20, RxComplType3=0x30,
434 RxComplThreshShift=0,
437 /* Bits in the TxCompletionAddr register */
439 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
440 TxComplProducerWrEn=0x40,
441 TxComplIntrStatus=0x20,
442 CommonQueueMode=0x10,
443 TxComplThreshShift=0,
446 /* Bits in the GenCtrl register */
448 RxEnable=0x05, TxEnable=0x0a,
449 RxGFPEnable=0x10, TxGFPEnable=0x20,
452 /* Bits in the IntrTimerCtrl register */
453 enum intr_ctrl_bits {
454 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
455 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
456 IntrLatencyMask=0x1f,
459 /* The Rx and Tx buffer descriptors. */
460 struct starfire_rx_desc {
461 netdrv_addr_t rxaddr;
464 RxDescValid=1, RxDescEndRing=2,
467 /* Completion queue entry. */
468 struct short_rx_done_desc {
469 __le32 status; /* Low 16 bits is length. */
471 struct basic_rx_done_desc {
472 __le32 status; /* Low 16 bits is length. */
476 struct csum_rx_done_desc {
477 __le32 status; /* Low 16 bits is length. */
478 __le16 csum; /* Partial checksum */
481 struct full_rx_done_desc {
482 __le32 status; /* Low 16 bits is length. */
486 __le16 csum; /* partial checksum */
489 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
491 typedef struct full_rx_done_desc rx_done_desc;
492 #define RxComplType RxComplType3
493 #else /* not VLAN_SUPPORT */
494 typedef struct csum_rx_done_desc rx_done_desc;
495 #define RxComplType RxComplType2
496 #endif /* not VLAN_SUPPORT */
499 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
502 /* Type 1 Tx descriptor. */
503 struct starfire_tx_desc_1 {
504 __le32 status; /* Upper bits are status, lower 16 length. */
508 /* Type 2 Tx descriptor. */
509 struct starfire_tx_desc_2 {
510 __le32 status; /* Upper bits are status, lower 16 length. */
516 typedef struct starfire_tx_desc_2 starfire_tx_desc;
517 #define TX_DESC_TYPE TxDescType2
518 #else /* not ADDR_64BITS */
519 typedef struct starfire_tx_desc_1 starfire_tx_desc;
520 #define TX_DESC_TYPE TxDescType1
521 #endif /* not ADDR_64BITS */
522 #define TX_DESC_SPACING TxDescSpaceUnlim
526 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
527 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
529 struct tx_done_desc {
530 __le32 status; /* timestamp, index. */
532 __le32 intrstatus; /* interrupt status */
536 struct rx_ring_info {
540 struct tx_ring_info {
543 unsigned int used_slots;
547 struct netdev_private {
548 /* Descriptor rings first for alignment. */
549 struct starfire_rx_desc *rx_ring;
550 starfire_tx_desc *tx_ring;
551 dma_addr_t rx_ring_dma;
552 dma_addr_t tx_ring_dma;
553 /* The addresses of rx/tx-in-place skbuffs. */
554 struct rx_ring_info rx_info[RX_RING_SIZE];
555 struct tx_ring_info tx_info[TX_RING_SIZE];
556 /* Pointers to completion queues (full pages). */
557 rx_done_desc *rx_done_q;
558 dma_addr_t rx_done_q_dma;
559 unsigned int rx_done;
560 struct tx_done_desc *tx_done_q;
561 dma_addr_t tx_done_q_dma;
562 unsigned int tx_done;
563 struct napi_struct napi;
564 struct net_device *dev;
565 struct net_device_stats stats;
566 struct pci_dev *pci_dev;
568 struct vlan_group *vlgrp;
571 dma_addr_t queue_mem_dma;
572 size_t queue_mem_size;
574 /* Frequently used values: keep some adjacent for cache effect. */
576 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
577 unsigned int cur_tx, dirty_tx, reap_tx;
578 unsigned int rx_buf_sz; /* Based on MTU+slack. */
579 /* These values keep track of the transceiver/media in use. */
580 int speed100; /* Set if speed == 100MBit. */
584 /* MII transceiver section. */
585 struct mii_if_info mii_if; /* MII lib hooks/info */
586 int phy_cnt; /* MII device addresses. */
587 unsigned char phys[PHY_CNT]; /* MII device addresses. */
592 static int mdio_read(struct net_device *dev, int phy_id, int location);
593 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
594 static int netdev_open(struct net_device *dev);
595 static void check_duplex(struct net_device *dev);
596 static void tx_timeout(struct net_device *dev);
597 static void init_ring(struct net_device *dev);
598 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
599 static irqreturn_t intr_handler(int irq, void *dev_instance);
600 static void netdev_error(struct net_device *dev, int intr_status);
601 static int __netdev_rx(struct net_device *dev, int *quota);
602 static int netdev_poll(struct napi_struct *napi, int budget);
603 static void refill_rx_ring(struct net_device *dev);
604 static void netdev_error(struct net_device *dev, int intr_status);
605 static void set_rx_mode(struct net_device *dev);
606 static struct net_device_stats *get_stats(struct net_device *dev);
607 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
608 static int netdev_close(struct net_device *dev);
609 static void netdev_media_change(struct net_device *dev);
610 static const struct ethtool_ops ethtool_ops;
614 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
616 struct netdev_private *np = netdev_priv(dev);
618 spin_lock(&np->lock);
620 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
623 spin_unlock(&np->lock);
626 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
628 struct netdev_private *np = netdev_priv(dev);
630 spin_lock(&np->lock);
632 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
634 spin_unlock(&np->lock);
637 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
639 struct netdev_private *np = netdev_priv(dev);
641 spin_lock(&np->lock);
643 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
644 vlan_group_set_device(np->vlgrp, vid, NULL);
646 spin_unlock(&np->lock);
648 #endif /* VLAN_SUPPORT */
651 static const struct net_device_ops netdev_ops = {
652 .ndo_open = netdev_open,
653 .ndo_stop = netdev_close,
654 .ndo_start_xmit = start_tx,
655 .ndo_tx_timeout = tx_timeout,
656 .ndo_get_stats = get_stats,
657 .ndo_set_multicast_list = &set_rx_mode,
658 .ndo_do_ioctl = netdev_ioctl,
659 .ndo_change_mtu = eth_change_mtu,
660 .ndo_set_mac_address = eth_mac_addr,
661 .ndo_validate_addr = eth_validate_addr,
663 .ndo_vlan_rx_register = netdev_vlan_rx_register,
664 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
665 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
669 static int __devinit starfire_init_one(struct pci_dev *pdev,
670 const struct pci_device_id *ent)
672 struct netdev_private *np;
673 int i, irq, option, chip_idx = ent->driver_data;
674 struct net_device *dev;
675 static int card_idx = -1;
678 int drv_flags, io_size;
681 /* when built into the kernel, we only print version if device is found */
683 static int printed_version;
684 if (!printed_version++)
690 if (pci_enable_device (pdev))
693 ioaddr = pci_resource_start(pdev, 0);
694 io_size = pci_resource_len(pdev, 0);
695 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
696 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
700 dev = alloc_etherdev(sizeof(*np));
702 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
705 SET_NETDEV_DEV(dev, &pdev->dev);
709 if (pci_request_regions (pdev, DRV_NAME)) {
710 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
711 goto err_out_free_netdev;
714 base = ioremap(ioaddr, io_size);
716 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
717 card_idx, io_size, ioaddr);
718 goto err_out_free_res;
721 pci_set_master(pdev);
723 /* enable MWI -- it vastly improves Rx performance on sparc64 */
724 pci_try_set_mwi(pdev);
727 /* Starfire can do TCP/UDP checksumming */
729 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
730 #endif /* ZEROCOPY */
733 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
734 #endif /* VLAN_RX_KILL_VID */
736 dev->features |= NETIF_F_HIGHDMA;
737 #endif /* ADDR_64BITS */
739 /* Serial EEPROM reads are hidden by the hardware. */
740 for (i = 0; i < 6; i++)
741 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
743 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
745 for (i = 0; i < 0x20; i++)
747 (unsigned int)readb(base + EEPROMCtrl + i),
748 i % 16 != 15 ? " " : "\n");
751 /* Issue soft reset */
752 writel(MiiSoftReset, base + TxMode);
754 writel(0, base + TxMode);
756 /* Reset the chip to erase previous misconfiguration. */
757 writel(1, base + PCIDeviceConfig);
759 while (--boguscnt > 0) {
761 if ((readl(base + PCIDeviceConfig) & 1) == 0)
765 printk("%s: chipset reset never completed!\n", dev->name);
766 /* wait a little longer */
769 dev->base_addr = (unsigned long)base;
772 np = netdev_priv(dev);
775 spin_lock_init(&np->lock);
776 pci_set_drvdata(pdev, dev);
780 np->mii_if.dev = dev;
781 np->mii_if.mdio_read = mdio_read;
782 np->mii_if.mdio_write = mdio_write;
783 np->mii_if.phy_id_mask = 0x1f;
784 np->mii_if.reg_num_mask = 0x1f;
786 drv_flags = netdrv_tbl[chip_idx].drv_flags;
788 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
790 option = dev->mem_start;
792 /* The lower four bits are the media type. */
794 np->mii_if.full_duplex = 1;
796 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
797 np->mii_if.full_duplex = 1;
799 if (np->mii_if.full_duplex)
800 np->mii_if.force_media = 1;
802 np->mii_if.force_media = 0;
805 /* timer resolution is 128 * 0.8us */
806 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
807 Timer10X | EnableIntrMasking;
809 if (small_frames > 0) {
810 np->intr_timer_ctrl |= SmallFrameBypass;
811 switch (small_frames) {
813 np->intr_timer_ctrl |= SmallFrame64;
816 np->intr_timer_ctrl |= SmallFrame128;
819 np->intr_timer_ctrl |= SmallFrame256;
822 np->intr_timer_ctrl |= SmallFrame512;
823 if (small_frames > 512)
824 printk("Adjusting small_frames down to 512\n");
829 dev->netdev_ops = &netdev_ops;
830 dev->watchdog_timeo = TX_TIMEOUT;
831 SET_ETHTOOL_OPS(dev, ðtool_ops);
833 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
838 if (register_netdev(dev))
839 goto err_out_cleardev;
841 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
842 dev->name, netdrv_tbl[chip_idx].name, base,
845 if (drv_flags & CanHaveMII) {
846 int phy, phy_idx = 0;
848 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
849 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
852 while (--boguscnt > 0)
853 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
856 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
859 mii_status = mdio_read(dev, phy, MII_BMSR);
860 if (mii_status != 0) {
861 np->phys[phy_idx++] = phy;
862 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
863 printk(KERN_INFO "%s: MII PHY found at address %d, status "
864 "%#4.4x advertising %#4.4x.\n",
865 dev->name, phy, mii_status, np->mii_if.advertising);
866 /* there can be only one PHY on-board */
870 np->phy_cnt = phy_idx;
872 np->mii_if.phy_id = np->phys[0];
874 memset(&np->mii_if, 0, sizeof(np->mii_if));
877 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
878 dev->name, enable_hw_cksum ? "enabled" : "disabled");
882 pci_set_drvdata(pdev, NULL);
885 pci_release_regions (pdev);
892 /* Read the MII Management Data I/O (MDIO) interfaces. */
893 static int mdio_read(struct net_device *dev, int phy_id, int location)
895 struct netdev_private *np = netdev_priv(dev);
896 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
897 int result, boguscnt=1000;
898 /* ??? Should we add a busy-wait here? */
900 result = readl(mdio_addr);
901 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
904 if ((result & 0xffff) == 0xffff)
906 return result & 0xffff;
910 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
912 struct netdev_private *np = netdev_priv(dev);
913 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
914 writel(value, mdio_addr);
915 /* The busy-wait will occur before a read. */
919 static int netdev_open(struct net_device *dev)
921 const struct firmware *fw_rx, *fw_tx;
922 const __be32 *fw_rx_data, *fw_tx_data;
923 struct netdev_private *np = netdev_priv(dev);
924 void __iomem *ioaddr = np->base;
926 size_t tx_size, rx_size;
927 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
929 /* Do we ever need to reset the chip??? */
931 retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
935 /* Disable the Rx and Tx, and reset the chip. */
936 writel(0, ioaddr + GenCtrl);
937 writel(1, ioaddr + PCIDeviceConfig);
939 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
940 dev->name, dev->irq);
942 /* Allocate the various queues. */
943 if (!np->queue_mem) {
944 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
945 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
946 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
947 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
948 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
949 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
950 if (np->queue_mem == NULL) {
951 free_irq(dev->irq, dev);
955 np->tx_done_q = np->queue_mem;
956 np->tx_done_q_dma = np->queue_mem_dma;
957 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
958 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
959 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
960 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
961 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
962 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
965 /* Start with no carrier, it gets adjusted later */
966 netif_carrier_off(dev);
968 /* Set the size of the Rx buffers. */
969 writel((np->rx_buf_sz << RxBufferLenShift) |
970 (0 << RxMinDescrThreshShift) |
971 RxPrefetchMode | RxVariableQ |
973 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
975 ioaddr + RxDescQCtrl);
977 /* Set up the Rx DMA controller. */
978 writel(RxChecksumIgnore |
979 (0 << RxEarlyIntThreshShift) |
980 (6 << RxHighPrioThreshShift) |
981 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
984 /* Set Tx descriptor */
985 writel((2 << TxHiPriFIFOThreshShift) |
986 (0 << TxPadLenShift) |
987 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
988 TX_DESC_Q_ADDR_SIZE |
989 TX_DESC_SPACING | TX_DESC_TYPE,
990 ioaddr + TxDescCtrl);
992 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
993 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
994 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
995 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
996 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
998 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
999 writel(np->rx_done_q_dma |
1001 (0 << RxComplThreshShift),
1002 ioaddr + RxCompletionAddr);
1005 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
1007 /* Fill both the Tx SA register and the Rx perfect filter. */
1008 for (i = 0; i < 6; i++)
1009 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
1010 /* The first entry is special because it bypasses the VLAN filter.
1012 writew(0, ioaddr + PerfFilterTable);
1013 writew(0, ioaddr + PerfFilterTable + 4);
1014 writew(0, ioaddr + PerfFilterTable + 8);
1015 for (i = 1; i < 16; i++) {
1016 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1017 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1018 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1019 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1020 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1023 /* Initialize other registers. */
1024 /* Configure the PCI bus bursts and FIFO thresholds. */
1025 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1026 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1028 writel(np->tx_mode, ioaddr + TxMode);
1029 np->tx_threshold = 4;
1030 writel(np->tx_threshold, ioaddr + TxThreshold);
1032 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1034 napi_enable(&np->napi);
1036 netif_start_queue(dev);
1039 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1042 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1045 /* Enable GPIO interrupts on link change */
1046 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1048 /* Set the interrupt mask */
1049 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1050 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1051 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1052 ioaddr + IntrEnable);
1053 /* Enable PCI interrupts. */
1054 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1055 ioaddr + PCIDeviceConfig);
1058 /* Set VLAN type to 802.1q */
1059 writel(ETH_P_8021Q, ioaddr + VlanType);
1060 #endif /* VLAN_SUPPORT */
1062 retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1064 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1068 if (fw_rx->size % 4) {
1069 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1070 fw_rx->size, FIRMWARE_RX);
1074 retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1076 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1080 if (fw_tx->size % 4) {
1081 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1082 fw_tx->size, FIRMWARE_TX);
1086 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1087 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1088 rx_size = fw_rx->size / 4;
1089 tx_size = fw_tx->size / 4;
1091 /* Load Rx/Tx firmware into the frame processors */
1092 for (i = 0; i < rx_size; i++)
1093 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1094 for (i = 0; i < tx_size; i++)
1095 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1096 if (enable_hw_cksum)
1097 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1098 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1100 /* Enable the Rx and Tx units only. */
1101 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1104 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1108 release_firmware(fw_tx);
1110 release_firmware(fw_rx);
1118 static void check_duplex(struct net_device *dev)
1120 struct netdev_private *np = netdev_priv(dev);
1122 int silly_count = 1000;
1124 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1125 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1127 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1130 printk("%s: MII reset failed!\n", dev->name);
1134 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1136 if (!np->mii_if.force_media) {
1137 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1139 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1141 reg0 |= BMCR_SPEED100;
1142 if (np->mii_if.full_duplex)
1143 reg0 |= BMCR_FULLDPLX;
1144 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1146 np->speed100 ? "100" : "10",
1147 np->mii_if.full_duplex ? "full" : "half");
1149 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1153 static void tx_timeout(struct net_device *dev)
1155 struct netdev_private *np = netdev_priv(dev);
1156 void __iomem *ioaddr = np->base;
1159 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1160 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1162 /* Perhaps we should reinitialize the hardware here. */
1165 * Stop and restart the interface.
1166 * Cheat and increase the debug level temporarily.
1174 /* Trigger an immediate transmit demand. */
1176 dev->trans_start = jiffies; /* prevent tx timeout */
1177 np->stats.tx_errors++;
1178 netif_wake_queue(dev);
1182 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1183 static void init_ring(struct net_device *dev)
1185 struct netdev_private *np = netdev_priv(dev);
1188 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1189 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1191 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1193 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1194 for (i = 0; i < RX_RING_SIZE; i++) {
1195 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1196 np->rx_info[i].skb = skb;
1199 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1200 skb->dev = dev; /* Mark as being used by this device. */
1201 /* Grrr, we cannot offset to correctly align the IP header. */
1202 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1204 writew(i - 1, np->base + RxDescQIdx);
1205 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1207 /* Clear the remainder of the Rx buffer ring. */
1208 for ( ; i < RX_RING_SIZE; i++) {
1209 np->rx_ring[i].rxaddr = 0;
1210 np->rx_info[i].skb = NULL;
1211 np->rx_info[i].mapping = 0;
1213 /* Mark the last entry as wrapping the ring. */
1214 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1216 /* Clear the completion rings. */
1217 for (i = 0; i < DONE_Q_SIZE; i++) {
1218 np->rx_done_q[i].status = 0;
1219 np->tx_done_q[i].status = 0;
1222 for (i = 0; i < TX_RING_SIZE; i++)
1223 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1229 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1231 struct netdev_private *np = netdev_priv(dev);
1237 * be cautious here, wrapping the queue has weird semantics
1238 * and we may not have enough slots even when it seems we do.
1240 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1241 netif_stop_queue(dev);
1242 return NETDEV_TX_BUSY;
1245 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1246 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1247 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1248 return NETDEV_TX_OK;
1250 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1252 entry = np->cur_tx % TX_RING_SIZE;
1253 for (i = 0; i < skb_num_frags(skb); i++) {
1258 np->tx_info[entry].skb = skb;
1260 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1261 status |= TxRingWrap;
1265 status |= TxDescIntr;
1268 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1270 np->stats.tx_compressed++;
1272 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1274 np->tx_info[entry].mapping =
1275 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1277 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1278 status |= this_frag->size;
1279 np->tx_info[entry].mapping =
1280 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1283 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1284 np->tx_ring[entry].status = cpu_to_le32(status);
1286 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1287 dev->name, np->cur_tx, np->dirty_tx,
1290 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1291 np->cur_tx += np->tx_info[entry].used_slots;
1294 np->tx_info[entry].used_slots = 1;
1295 np->cur_tx += np->tx_info[entry].used_slots;
1298 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1299 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1303 /* Non-x86: explicitly flush descriptor cache lines here. */
1304 /* Ensure all descriptors are written back before the transmit is
1308 /* Update the producer index. */
1309 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1311 /* 4 is arbitrary, but should be ok */
1312 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1313 netif_stop_queue(dev);
1315 return NETDEV_TX_OK;
1319 /* The interrupt handler does all of the Rx thread work and cleans up
1320 after the Tx thread. */
1321 static irqreturn_t intr_handler(int irq, void *dev_instance)
1323 struct net_device *dev = dev_instance;
1324 struct netdev_private *np = netdev_priv(dev);
1325 void __iomem *ioaddr = np->base;
1326 int boguscnt = max_interrupt_work;
1332 u32 intr_status = readl(ioaddr + IntrClear);
1335 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1336 dev->name, intr_status);
1338 if (intr_status == 0 || intr_status == (u32) -1)
1343 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1346 if (likely(napi_schedule_prep(&np->napi))) {
1347 __napi_schedule(&np->napi);
1348 enable = readl(ioaddr + IntrEnable);
1349 enable &= ~(IntrRxDone | IntrRxEmpty);
1350 writel(enable, ioaddr + IntrEnable);
1351 /* flush PCI posting buffers */
1352 readl(ioaddr + IntrEnable);
1354 /* Paranoia check */
1355 enable = readl(ioaddr + IntrEnable);
1356 if (enable & (IntrRxDone | IntrRxEmpty)) {
1358 "%s: interrupt while in poll!\n",
1360 enable &= ~(IntrRxDone | IntrRxEmpty);
1361 writel(enable, ioaddr + IntrEnable);
1366 /* Scavenge the skbuff list based on the Tx-done queue.
1367 There are redundant checks here that may be cleaned up
1368 after the driver has proven to be reliable. */
1369 consumer = readl(ioaddr + TxConsumerIdx);
1371 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1372 dev->name, consumer);
1374 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1376 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1377 dev->name, np->dirty_tx, np->tx_done, tx_status);
1378 if ((tx_status & 0xe0000000) == 0xa0000000) {
1379 np->stats.tx_packets++;
1380 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1381 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1382 struct sk_buff *skb = np->tx_info[entry].skb;
1383 np->tx_info[entry].skb = NULL;
1384 pci_unmap_single(np->pci_dev,
1385 np->tx_info[entry].mapping,
1386 skb_first_frag_len(skb),
1388 np->tx_info[entry].mapping = 0;
1389 np->dirty_tx += np->tx_info[entry].used_slots;
1390 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1393 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1394 pci_unmap_single(np->pci_dev,
1395 np->tx_info[entry].mapping,
1396 skb_shinfo(skb)->frags[i].size,
1403 dev_kfree_skb_irq(skb);
1405 np->tx_done_q[np->tx_done].status = 0;
1406 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1408 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1410 if (netif_queue_stopped(dev) &&
1411 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1412 /* The ring is no longer full, wake the queue. */
1413 netif_wake_queue(dev);
1416 /* Stats overflow */
1417 if (intr_status & IntrStatsMax)
1420 /* Media change interrupt. */
1421 if (intr_status & IntrLinkChange)
1422 netdev_media_change(dev);
1424 /* Abnormal error summary/uncommon events handlers. */
1425 if (intr_status & IntrAbnormalSummary)
1426 netdev_error(dev, intr_status);
1428 if (--boguscnt < 0) {
1430 printk(KERN_WARNING "%s: Too much work at interrupt, "
1432 dev->name, intr_status);
1438 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1439 dev->name, (int) readl(ioaddr + IntrStatus));
1440 return IRQ_RETVAL(handled);
1445 * This routine is logically part of the interrupt/poll handler, but separated
1446 * for clarity and better register allocation.
1448 static int __netdev_rx(struct net_device *dev, int *quota)
1450 struct netdev_private *np = netdev_priv(dev);
1454 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1455 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1456 struct sk_buff *skb;
1459 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1462 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1463 if (!(desc_status & RxOK)) {
1464 /* There was an error. */
1466 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1467 np->stats.rx_errors++;
1468 if (desc_status & RxFIFOErr)
1469 np->stats.rx_fifo_errors++;
1473 if (*quota <= 0) { /* out of rx quota */
1479 pkt_len = desc_status; /* Implicitly Truncate */
1480 entry = (desc_status >> 16) & 0x7ff;
1483 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1484 /* Check if the packet is long enough to accept without copying
1485 to a minimally-sized skbuff. */
1486 if (pkt_len < rx_copybreak &&
1487 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1488 skb_reserve(skb, 2); /* 16 byte align the IP header */
1489 pci_dma_sync_single_for_cpu(np->pci_dev,
1490 np->rx_info[entry].mapping,
1491 pkt_len, PCI_DMA_FROMDEVICE);
1492 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1493 pci_dma_sync_single_for_device(np->pci_dev,
1494 np->rx_info[entry].mapping,
1495 pkt_len, PCI_DMA_FROMDEVICE);
1496 skb_put(skb, pkt_len);
1498 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1499 skb = np->rx_info[entry].skb;
1500 skb_put(skb, pkt_len);
1501 np->rx_info[entry].skb = NULL;
1502 np->rx_info[entry].mapping = 0;
1504 #ifndef final_version /* Remove after testing. */
1505 /* You will want this info for the initial debug. */
1507 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1508 skb->data, skb->data + 6,
1509 skb->data[12], skb->data[13]);
1513 skb->protocol = eth_type_trans(skb, dev);
1516 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1518 if (le16_to_cpu(desc->status2) & 0x0100) {
1519 skb->ip_summed = CHECKSUM_UNNECESSARY;
1520 np->stats.rx_compressed++;
1523 * This feature doesn't seem to be working, at least
1524 * with the two firmware versions I have. If the GFP sees
1525 * an IP fragment, it either ignores it completely, or reports
1526 * "bad checksum" on it.
1528 * Maybe I missed something -- corrections are welcome.
1529 * Until then, the printk stays. :-) -Ion
1531 else if (le16_to_cpu(desc->status2) & 0x0040) {
1532 skb->ip_summed = CHECKSUM_COMPLETE;
1533 skb->csum = le16_to_cpu(desc->csum);
1534 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1537 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1538 u16 vlid = le16_to_cpu(desc->vlanid);
1541 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1545 * vlan_hwaccel_rx expects a packet with the VLAN tag
1548 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1550 #endif /* VLAN_SUPPORT */
1551 netif_receive_skb(skb);
1552 np->stats.rx_packets++;
1557 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1560 if (*quota == 0) { /* out of rx quota */
1564 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1567 refill_rx_ring(dev);
1569 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1570 retcode, np->rx_done, desc_status);
1574 static int netdev_poll(struct napi_struct *napi, int budget)
1576 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1577 struct net_device *dev = np->dev;
1579 void __iomem *ioaddr = np->base;
1583 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1585 if (__netdev_rx(dev, "a))
1588 intr_status = readl(ioaddr + IntrStatus);
1589 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1591 napi_complete(napi);
1592 intr_status = readl(ioaddr + IntrEnable);
1593 intr_status |= IntrRxDone | IntrRxEmpty;
1594 writel(intr_status, ioaddr + IntrEnable);
1598 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1601 /* Restart Rx engine if stopped. */
1602 return budget - quota;
1605 static void refill_rx_ring(struct net_device *dev)
1607 struct netdev_private *np = netdev_priv(dev);
1608 struct sk_buff *skb;
1611 /* Refill the Rx ring buffers. */
1612 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1613 entry = np->dirty_rx % RX_RING_SIZE;
1614 if (np->rx_info[entry].skb == NULL) {
1615 skb = dev_alloc_skb(np->rx_buf_sz);
1616 np->rx_info[entry].skb = skb;
1618 break; /* Better luck next round. */
1619 np->rx_info[entry].mapping =
1620 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1621 skb->dev = dev; /* Mark as being used by this device. */
1622 np->rx_ring[entry].rxaddr =
1623 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1625 if (entry == RX_RING_SIZE - 1)
1626 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1629 writew(entry, np->base + RxDescQIdx);
1633 static void netdev_media_change(struct net_device *dev)
1635 struct netdev_private *np = netdev_priv(dev);
1636 void __iomem *ioaddr = np->base;
1637 u16 reg0, reg1, reg4, reg5;
1639 u32 new_intr_timer_ctrl;
1641 /* reset status first */
1642 mdio_read(dev, np->phys[0], MII_BMCR);
1643 mdio_read(dev, np->phys[0], MII_BMSR);
1645 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1646 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1648 if (reg1 & BMSR_LSTATUS) {
1650 if (reg0 & BMCR_ANENABLE) {
1651 /* autonegotiation is enabled */
1652 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1653 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1654 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1656 np->mii_if.full_duplex = 1;
1657 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1659 np->mii_if.full_duplex = 0;
1660 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1662 np->mii_if.full_duplex = 1;
1665 np->mii_if.full_duplex = 0;
1668 /* autonegotiation is disabled */
1669 if (reg0 & BMCR_SPEED100)
1673 if (reg0 & BMCR_FULLDPLX)
1674 np->mii_if.full_duplex = 1;
1676 np->mii_if.full_duplex = 0;
1678 netif_carrier_on(dev);
1679 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1681 np->speed100 ? "100" : "10",
1682 np->mii_if.full_duplex ? "full" : "half");
1684 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1685 if (np->mii_if.full_duplex)
1686 new_tx_mode |= FullDuplex;
1687 if (np->tx_mode != new_tx_mode) {
1688 np->tx_mode = new_tx_mode;
1689 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1691 writel(np->tx_mode, ioaddr + TxMode);
1694 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1696 new_intr_timer_ctrl |= Timer10X;
1697 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1698 np->intr_timer_ctrl = new_intr_timer_ctrl;
1699 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1702 netif_carrier_off(dev);
1703 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1708 static void netdev_error(struct net_device *dev, int intr_status)
1710 struct netdev_private *np = netdev_priv(dev);
1712 /* Came close to underrunning the Tx FIFO, increase threshold. */
1713 if (intr_status & IntrTxDataLow) {
1714 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1715 writel(++np->tx_threshold, np->base + TxThreshold);
1716 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1717 dev->name, np->tx_threshold * 16);
1719 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1721 if (intr_status & IntrRxGFPDead) {
1722 np->stats.rx_fifo_errors++;
1723 np->stats.rx_errors++;
1725 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1726 np->stats.tx_fifo_errors++;
1727 np->stats.tx_errors++;
1729 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1730 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1731 dev->name, intr_status);
1735 static struct net_device_stats *get_stats(struct net_device *dev)
1737 struct netdev_private *np = netdev_priv(dev);
1738 void __iomem *ioaddr = np->base;
1740 /* This adapter architecture needs no SMP locks. */
1741 np->stats.tx_bytes = readl(ioaddr + 0x57010);
1742 np->stats.rx_bytes = readl(ioaddr + 0x57044);
1743 np->stats.tx_packets = readl(ioaddr + 0x57000);
1744 np->stats.tx_aborted_errors =
1745 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1746 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
1747 np->stats.collisions =
1748 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1750 /* The chip only need report frame silently dropped. */
1751 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1752 writew(0, ioaddr + RxDMAStatus);
1753 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1754 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1755 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
1756 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1762 static void set_rx_mode(struct net_device *dev)
1764 struct netdev_private *np = netdev_priv(dev);
1765 void __iomem *ioaddr = np->base;
1766 u32 rx_mode = MinVLANPrio;
1767 struct netdev_hw_addr *ha;
1771 rx_mode |= VlanMode;
1774 void __iomem *filter_addr = ioaddr + HashTable + 8;
1775 for (i = 0; i < VLAN_VID_MASK; i++) {
1776 if (vlan_group_get_device(np->vlgrp, i)) {
1777 if (vlan_count >= 32)
1779 writew(i, filter_addr);
1784 if (i == VLAN_VID_MASK) {
1785 rx_mode |= PerfectFilterVlan;
1786 while (vlan_count < 32) {
1787 writew(0, filter_addr);
1793 #endif /* VLAN_SUPPORT */
1795 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1796 rx_mode |= AcceptAll;
1797 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1798 (dev->flags & IFF_ALLMULTI)) {
1799 /* Too many to match, or accept all multicasts. */
1800 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1801 } else if (netdev_mc_count(dev) <= 14) {
1802 /* Use the 16 element perfect filter, skip first two entries. */
1803 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1805 netdev_for_each_mc_addr(ha, dev) {
1806 eaddrs = (__be16 *) ha->addr;
1807 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1808 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1809 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1811 eaddrs = (__be16 *)dev->dev_addr;
1812 i = netdev_mc_count(dev) + 2;
1814 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1815 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1816 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1818 rx_mode |= AcceptBroadcast|PerfectFilter;
1820 /* Must use a multicast hash table. */
1821 void __iomem *filter_addr;
1823 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1825 memset(mc_filter, 0, sizeof(mc_filter));
1826 netdev_for_each_mc_addr(ha, dev) {
1827 /* The chip uses the upper 9 CRC bits
1828 as index into the hash table */
1829 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1830 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1832 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1834 /* Clear the perfect filter list, skip first two entries. */
1835 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1836 eaddrs = (__be16 *)dev->dev_addr;
1837 for (i = 2; i < 16; i++) {
1838 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1839 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1840 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1842 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1843 writew(mc_filter[i], filter_addr);
1844 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1846 writel(rx_mode, ioaddr + RxFilterMode);
1849 static int check_if_running(struct net_device *dev)
1851 if (!netif_running(dev))
1856 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1858 struct netdev_private *np = netdev_priv(dev);
1859 strcpy(info->driver, DRV_NAME);
1860 strcpy(info->version, DRV_VERSION);
1861 strcpy(info->bus_info, pci_name(np->pci_dev));
1864 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1866 struct netdev_private *np = netdev_priv(dev);
1867 spin_lock_irq(&np->lock);
1868 mii_ethtool_gset(&np->mii_if, ecmd);
1869 spin_unlock_irq(&np->lock);
1873 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1875 struct netdev_private *np = netdev_priv(dev);
1877 spin_lock_irq(&np->lock);
1878 res = mii_ethtool_sset(&np->mii_if, ecmd);
1879 spin_unlock_irq(&np->lock);
1884 static int nway_reset(struct net_device *dev)
1886 struct netdev_private *np = netdev_priv(dev);
1887 return mii_nway_restart(&np->mii_if);
1890 static u32 get_link(struct net_device *dev)
1892 struct netdev_private *np = netdev_priv(dev);
1893 return mii_link_ok(&np->mii_if);
1896 static u32 get_msglevel(struct net_device *dev)
1901 static void set_msglevel(struct net_device *dev, u32 val)
1906 static const struct ethtool_ops ethtool_ops = {
1907 .begin = check_if_running,
1908 .get_drvinfo = get_drvinfo,
1909 .get_settings = get_settings,
1910 .set_settings = set_settings,
1911 .nway_reset = nway_reset,
1912 .get_link = get_link,
1913 .get_msglevel = get_msglevel,
1914 .set_msglevel = set_msglevel,
1917 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1919 struct netdev_private *np = netdev_priv(dev);
1920 struct mii_ioctl_data *data = if_mii(rq);
1923 if (!netif_running(dev))
1926 spin_lock_irq(&np->lock);
1927 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1928 spin_unlock_irq(&np->lock);
1930 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1936 static int netdev_close(struct net_device *dev)
1938 struct netdev_private *np = netdev_priv(dev);
1939 void __iomem *ioaddr = np->base;
1942 netif_stop_queue(dev);
1944 napi_disable(&np->napi);
1947 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1948 dev->name, (int) readl(ioaddr + IntrStatus));
1949 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1950 dev->name, np->cur_tx, np->dirty_tx,
1951 np->cur_rx, np->dirty_rx);
1954 /* Disable interrupts by clearing the interrupt mask. */
1955 writel(0, ioaddr + IntrEnable);
1957 /* Stop the chip's Tx and Rx processes. */
1958 writel(0, ioaddr + GenCtrl);
1959 readl(ioaddr + GenCtrl);
1962 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1963 (long long) np->tx_ring_dma);
1964 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1965 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1966 i, le32_to_cpu(np->tx_ring[i].status),
1967 (long long) dma_to_cpu(np->tx_ring[i].addr),
1968 le32_to_cpu(np->tx_done_q[i].status));
1969 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1970 (long long) np->rx_ring_dma, np->rx_done_q);
1972 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1973 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1974 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1978 free_irq(dev->irq, dev);
1980 /* Free all the skbuffs in the Rx queue. */
1981 for (i = 0; i < RX_RING_SIZE; i++) {
1982 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1983 if (np->rx_info[i].skb != NULL) {
1984 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1985 dev_kfree_skb(np->rx_info[i].skb);
1987 np->rx_info[i].skb = NULL;
1988 np->rx_info[i].mapping = 0;
1990 for (i = 0; i < TX_RING_SIZE; i++) {
1991 struct sk_buff *skb = np->tx_info[i].skb;
1994 pci_unmap_single(np->pci_dev,
1995 np->tx_info[i].mapping,
1996 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1997 np->tx_info[i].mapping = 0;
1999 np->tx_info[i].skb = NULL;
2006 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
2008 struct net_device *dev = pci_get_drvdata(pdev);
2010 if (netif_running(dev)) {
2011 netif_device_detach(dev);
2015 pci_save_state(pdev);
2016 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2021 static int starfire_resume(struct pci_dev *pdev)
2023 struct net_device *dev = pci_get_drvdata(pdev);
2025 pci_set_power_state(pdev, PCI_D0);
2026 pci_restore_state(pdev);
2028 if (netif_running(dev)) {
2030 netif_device_attach(dev);
2035 #endif /* CONFIG_PM */
2038 static void __devexit starfire_remove_one (struct pci_dev *pdev)
2040 struct net_device *dev = pci_get_drvdata(pdev);
2041 struct netdev_private *np = netdev_priv(dev);
2045 unregister_netdev(dev);
2048 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2051 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2052 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2053 pci_disable_device(pdev);
2056 pci_release_regions(pdev);
2058 pci_set_drvdata(pdev, NULL);
2059 free_netdev(dev); /* Will also free np!! */
2063 static struct pci_driver starfire_driver = {
2065 .probe = starfire_init_one,
2066 .remove = __devexit_p(starfire_remove_one),
2068 .suspend = starfire_suspend,
2069 .resume = starfire_resume,
2070 #endif /* CONFIG_PM */
2071 .id_table = starfire_pci_tbl,
2075 static int __init starfire_init (void)
2077 /* when a module, this is printed whether or not devices are found in probe */
2081 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2084 /* we can do this test only at run-time... sigh */
2085 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
2086 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
2090 return pci_register_driver(&starfire_driver);
2094 static void __exit starfire_cleanup (void)
2096 pci_unregister_driver (&starfire_driver);
2100 module_init(starfire_init);
2101 module_exit(starfire_cleanup);