2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.23"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING 128
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
150 static void sky2_set_multicast(struct net_device *dev);
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (!(ctrl & GM_SMI_CT_BUSY))
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
210 __gm_phy_read(hw, port, reg, &v);
215 static void sky2_power_on(struct sky2_hw *hw)
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
255 sky2_read32(hw, B2_GP_IO);
259 static void sky2_power_aux(struct sky2_hw *hw)
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
433 adv |= fiber_fc_adv[sky2->flow_mode];
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
445 switch (sky2->speed) {
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
463 reg |= gm_fc_disable[sky2->flow_mode];
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
472 gma_write16(hw, port, GM_GP_CTRL, reg);
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
716 * sky2_reset will re-enable on resume
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
769 struct net_device *dev = hw->dev[port];
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
807 const u8 *addr = hw->dev[port]->dev_addr;
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
915 sky2_set_tx_stfwd(hw, port);
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
932 /* convert from K bytes to qwords used for hw register */
935 end = start + space - 1;
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
994 struct sky2_tx_le *le = sky2->tx_le + *slot;
996 *slot = RING_NEXT(*slot, TX_RING_SIZE);
1001 static void tx_init(struct sky2_port *sky2)
1003 struct sky2_tx_le *le;
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1009 le = get_tx_le(sky2, &sky2->tx_prod);
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1017 return sky2->tx_ring + (le - sky2->tx_le);
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1027 /* Synchronize I/O on since next processor may write to tail */
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1044 struct sky2_rx_le *le;
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1074 struct sk_buff *skb = re->skb;
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1081 pci_unmap_len_set(re, data_size, size);
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1094 struct sk_buff *skb = re->skb;
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1110 static void rx_set_checksum(struct sky2_port *sky2)
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1157 /* Clean out receive buffer area, assumes receiver hardware stopped */
1158 static void sky2_rx_clean(struct sky2_port *sky2)
1162 memset(sky2->rx_le, 0, RX_LE_BYTES);
1163 for (i = 0; i < sky2->rx_pending; i++) {
1164 struct rx_ring_info *re = sky2->rx_ring + i;
1167 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1172 skb_queue_purge(&sky2->rx_recycle);
1175 /* Basic MII support */
1176 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1178 struct mii_ioctl_data *data = if_mii(ifr);
1179 struct sky2_port *sky2 = netdev_priv(dev);
1180 struct sky2_hw *hw = sky2->hw;
1181 int err = -EOPNOTSUPP;
1183 if (!netif_running(dev))
1184 return -ENODEV; /* Phy still in reset */
1188 data->phy_id = PHY_ADDR_MARV;
1194 spin_lock_bh(&sky2->phy_lock);
1195 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1196 spin_unlock_bh(&sky2->phy_lock);
1198 data->val_out = val;
1203 if (!capable(CAP_NET_ADMIN))
1206 spin_lock_bh(&sky2->phy_lock);
1207 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1209 spin_unlock_bh(&sky2->phy_lock);
1215 #ifdef SKY2_VLAN_TAG_USED
1216 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1219 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1221 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1224 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1226 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1231 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1233 struct sky2_port *sky2 = netdev_priv(dev);
1234 struct sky2_hw *hw = sky2->hw;
1235 u16 port = sky2->port;
1237 netif_tx_lock_bh(dev);
1238 napi_disable(&hw->napi);
1241 sky2_set_vlan_mode(hw, port, grp != NULL);
1243 sky2_read32(hw, B0_Y2_SP_LISR);
1244 napi_enable(&hw->napi);
1245 netif_tx_unlock_bh(dev);
1249 /* Amount of required worst case padding in rx buffer */
1250 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1252 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
1259 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1261 struct sk_buff *skb;
1264 skb = __skb_dequeue(&sky2->rx_recycle);
1266 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1267 + sky2_rx_pad(sky2->hw));
1271 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1272 unsigned char *start;
1274 * Workaround for a bug in FIFO that cause hang
1275 * if the FIFO if the receive buffer is not 64 byte aligned.
1276 * The buffer returned from netdev_alloc_skb is
1277 * aligned except if slab debugging is enabled.
1279 start = PTR_ALIGN(skb->data, 8);
1280 skb_reserve(skb, start - skb->data);
1282 skb_reserve(skb, NET_IP_ALIGN);
1284 for (i = 0; i < sky2->rx_nfrags; i++) {
1285 struct page *page = alloc_page(GFP_ATOMIC);
1289 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1299 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1301 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1305 * Allocate and setup receiver buffer pool.
1306 * Normal case this ends up creating one list element for skb
1307 * in the receive ring. Worst case if using large MTU and each
1308 * allocation falls on a different 64 bit region, that results
1309 * in 6 list elements per ring entry.
1310 * One element is used for checksum enable/disable, and one
1311 * extra to avoid wrap.
1313 static int sky2_rx_start(struct sky2_port *sky2)
1315 struct sky2_hw *hw = sky2->hw;
1316 struct rx_ring_info *re;
1317 unsigned rxq = rxqaddr[sky2->port];
1318 unsigned i, size, thresh;
1320 sky2->rx_put = sky2->rx_next = 0;
1323 /* On PCI express lowering the watermark gives better performance */
1324 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1325 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1327 /* These chips have no ram buffer?
1328 * MAC Rx RAM Read is controlled by hardware */
1329 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1330 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1331 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1332 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1334 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1336 if (!(hw->flags & SKY2_HW_NEW_LE))
1337 rx_set_checksum(sky2);
1339 /* Space needed for frame data + headers rounded up */
1340 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1342 /* Stopping point for hardware truncation */
1343 thresh = (size - 8) / sizeof(u32);
1345 sky2->rx_nfrags = size >> PAGE_SHIFT;
1346 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1348 /* Compute residue after pages */
1349 size -= sky2->rx_nfrags << PAGE_SHIFT;
1351 /* Optimize to handle small packets and headers */
1352 if (size < copybreak)
1354 if (size < ETH_HLEN)
1357 sky2->rx_data_size = size;
1359 skb_queue_head_init(&sky2->rx_recycle);
1362 for (i = 0; i < sky2->rx_pending; i++) {
1363 re = sky2->rx_ring + i;
1365 re->skb = sky2_rx_alloc(sky2);
1369 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1370 dev_kfree_skb(re->skb);
1375 sky2_rx_submit(sky2, re);
1379 * The receiver hangs if it receives frames larger than the
1380 * packet buffer. As a workaround, truncate oversize frames, but
1381 * the register is limited to 9 bits, so if you do frames > 2052
1382 * you better get the MTU right!
1385 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1387 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1388 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1391 /* Tell chip about available buffers */
1392 sky2_rx_update(sky2, rxq);
1395 sky2_rx_clean(sky2);
1399 /* Bring up network interface. */
1400 static int sky2_up(struct net_device *dev)
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
1404 unsigned port = sky2->port;
1406 int cap, err = -ENOMEM;
1407 struct net_device *otherdev = hw->dev[sky2->port^1];
1410 * On dual port PCI-X card, there is an problem where status
1411 * can be received out of order due to split transactions
1413 if (otherdev && netif_running(otherdev) &&
1414 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1417 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1418 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1419 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1423 netif_carrier_off(dev);
1425 /* must be power of 2 */
1426 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1428 sizeof(struct sky2_tx_le),
1433 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1440 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1444 memset(sky2->rx_le, 0, RX_LE_BYTES);
1446 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1451 sky2_mac_init(hw, port);
1453 /* Register is number of 4K blocks on internal RAM buffer. */
1454 ramsize = sky2_read8(hw, B2_E_0) * 4;
1458 hw->flags |= SKY2_HW_RAM_BUFFER;
1459 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1461 rxspace = ramsize / 2;
1463 rxspace = 8 + (2*(ramsize - 16))/3;
1465 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1466 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1468 /* Make sure SyncQ is disabled */
1469 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1473 sky2_qset(hw, txqaddr[port]);
1475 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1476 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1477 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1479 /* Set almost empty threshold */
1480 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1481 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1482 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1484 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1487 #ifdef SKY2_VLAN_TAG_USED
1488 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1491 sky2->restarting = 0;
1493 err = sky2_rx_start(sky2);
1497 /* Enable interrupts from phy/mac for port */
1498 imask = sky2_read32(hw, B0_IMSK);
1499 imask |= portirq_msk[port];
1500 sky2_write32(hw, B0_IMSK, imask);
1501 sky2_read32(hw, B0_IMSK);
1503 sky2_set_multicast(dev);
1505 /* wake queue incase we are restarting */
1506 netif_wake_queue(dev);
1508 if (netif_msg_ifup(sky2))
1509 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1514 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1515 sky2->rx_le, sky2->rx_le_map);
1519 pci_free_consistent(hw->pdev,
1520 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1521 sky2->tx_le, sky2->tx_le_map);
1524 kfree(sky2->tx_ring);
1525 kfree(sky2->rx_ring);
1527 sky2->tx_ring = NULL;
1528 sky2->rx_ring = NULL;
1532 /* Modular subtraction in ring */
1533 static inline int tx_dist(unsigned tail, unsigned head)
1535 return (head - tail) & (TX_RING_SIZE - 1);
1538 /* Number of list elements available for next tx */
1539 static inline int tx_avail(const struct sky2_port *sky2)
1541 if (unlikely(sky2->restarting))
1543 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1546 /* Estimate of number of transmit list elements required */
1547 static unsigned tx_le_req(const struct sk_buff *skb)
1551 count = sizeof(dma_addr_t) / sizeof(u32);
1552 count += skb_shinfo(skb)->nr_frags * count;
1554 if (skb_is_gso(skb))
1557 if (skb->ip_summed == CHECKSUM_PARTIAL)
1564 * Put one packet in ring for transmit.
1565 * A single packet can generate multiple list elements, and
1566 * the number of ring elements will probably be less than the number
1567 * of list elements used.
1569 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572 struct sky2_hw *hw = sky2->hw;
1573 struct sky2_tx_le *le = NULL;
1574 struct tx_ring_info *re;
1581 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1582 return NETDEV_TX_BUSY;
1584 len = skb_headlen(skb);
1585 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1587 if (pci_dma_mapping_error(hw->pdev, mapping))
1590 slot = sky2->tx_prod;
1591 if (unlikely(netif_msg_tx_queued(sky2)))
1592 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1593 dev->name, slot, skb->len);
1595 /* Send high bits if needed */
1596 if (sizeof(dma_addr_t) > sizeof(u32)) {
1597 le = get_tx_le(sky2, &slot);
1598 le->addr = cpu_to_le32(upper_32_bits(mapping));
1599 le->opcode = OP_ADDR64 | HW_OWNER;
1602 /* Check for TCP Segmentation Offload */
1603 mss = skb_shinfo(skb)->gso_size;
1606 if (!(hw->flags & SKY2_HW_NEW_LE))
1607 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1609 if (mss != sky2->tx_last_mss) {
1610 le = get_tx_le(sky2, &slot);
1611 le->addr = cpu_to_le32(mss);
1613 if (hw->flags & SKY2_HW_NEW_LE)
1614 le->opcode = OP_MSS | HW_OWNER;
1616 le->opcode = OP_LRGLEN | HW_OWNER;
1617 sky2->tx_last_mss = mss;
1622 #ifdef SKY2_VLAN_TAG_USED
1623 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1624 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1626 le = get_tx_le(sky2, &slot);
1628 le->opcode = OP_VLAN|HW_OWNER;
1630 le->opcode |= OP_VLAN;
1631 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1636 /* Handle TCP checksum offload */
1637 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1638 /* On Yukon EX (some versions) encoding change. */
1639 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1640 ctrl |= CALSUM; /* auto checksum */
1642 const unsigned offset = skb_transport_offset(skb);
1645 tcpsum = offset << 16; /* sum start */
1646 tcpsum |= offset + skb->csum_offset; /* sum write */
1648 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1649 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1652 if (tcpsum != sky2->tx_tcpsum) {
1653 sky2->tx_tcpsum = tcpsum;
1655 le = get_tx_le(sky2, &slot);
1656 le->addr = cpu_to_le32(tcpsum);
1657 le->length = 0; /* initial checksum value */
1658 le->ctrl = 1; /* one packet */
1659 le->opcode = OP_TCPLISW | HW_OWNER;
1664 le = get_tx_le(sky2, &slot);
1665 le->addr = cpu_to_le32((u32) mapping);
1666 le->length = cpu_to_le16(len);
1668 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1670 re = tx_le_re(sky2, le);
1672 pci_unmap_addr_set(re, mapaddr, mapping);
1673 pci_unmap_len_set(re, maplen, len);
1675 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1676 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1678 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1679 frag->size, PCI_DMA_TODEVICE);
1681 if (pci_dma_mapping_error(hw->pdev, mapping))
1682 goto mapping_unwind;
1684 if (sizeof(dma_addr_t) > sizeof(u32)) {
1685 le = get_tx_le(sky2, &slot);
1686 le->addr = cpu_to_le32(upper_32_bits(mapping));
1688 le->opcode = OP_ADDR64 | HW_OWNER;
1691 le = get_tx_le(sky2, &slot);
1692 le->addr = cpu_to_le32((u32) mapping);
1693 le->length = cpu_to_le16(frag->size);
1695 le->opcode = OP_BUFFER | HW_OWNER;
1697 re = tx_le_re(sky2, le);
1699 pci_unmap_addr_set(re, mapaddr, mapping);
1700 pci_unmap_len_set(re, maplen, frag->size);
1705 sky2->tx_prod = slot;
1707 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1708 netif_stop_queue(dev);
1710 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1712 return NETDEV_TX_OK;
1715 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, TX_RING_SIZE)) {
1716 le = sky2->tx_le + i;
1717 re = sky2->tx_ring + i;
1719 switch(le->opcode & ~HW_OWNER) {
1722 pci_unmap_single(hw->pdev,
1723 pci_unmap_addr(re, mapaddr),
1724 pci_unmap_len(re, maplen),
1728 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1729 pci_unmap_len(re, maplen),
1736 if (net_ratelimit())
1737 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1739 return NETDEV_TX_OK;
1743 * Free ring elements from starting at tx_cons until "done"
1745 * NB: the hardware will tell us about partial completion of multi-part
1746 * buffers so make sure not to free skb to early.
1748 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1750 struct net_device *dev = sky2->netdev;
1751 struct pci_dev *pdev = sky2->hw->pdev;
1754 BUG_ON(done >= TX_RING_SIZE);
1756 for (idx = sky2->tx_cons; idx != done;
1757 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1758 struct sky2_tx_le *le = sky2->tx_le + idx;
1759 struct tx_ring_info *re = sky2->tx_ring + idx;
1761 switch(le->opcode & ~HW_OWNER) {
1764 pci_unmap_single(pdev,
1765 pci_unmap_addr(re, mapaddr),
1766 pci_unmap_len(re, maplen),
1770 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1771 pci_unmap_len(re, maplen),
1776 if (le->ctrl & EOP) {
1777 struct sk_buff *skb = re->skb;
1779 if (unlikely(netif_msg_tx_done(sky2)))
1780 printk(KERN_DEBUG "%s: tx done %u\n",
1783 dev->stats.tx_packets++;
1784 dev->stats.tx_bytes += skb->len;
1786 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1787 && skb_recycle_check(skb, sky2->rx_data_size
1788 + sky2_rx_pad(sky2->hw)))
1789 __skb_queue_head(&sky2->rx_recycle, skb);
1791 dev_kfree_skb_any(skb);
1793 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1797 sky2->tx_cons = idx;
1800 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1801 netif_wake_queue(dev);
1804 /* Cleanup all untransmitted buffers, assume transmitter not running */
1805 static void sky2_tx_clean(struct net_device *dev)
1807 struct sky2_port *sky2 = netdev_priv(dev);
1809 netif_tx_lock_bh(dev);
1810 sky2_tx_complete(sky2, sky2->tx_prod);
1811 netif_tx_unlock_bh(dev);
1814 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1816 /* Disable Force Sync bit and Enable Alloc bit */
1817 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1818 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1820 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1821 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1822 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1824 /* Reset the PCI FIFO of the async Tx queue */
1825 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1826 BMU_RST_SET | BMU_FIFO_RST);
1828 /* Reset the Tx prefetch units */
1829 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1832 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1833 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1836 /* Network shutdown */
1837 static int sky2_down(struct net_device *dev)
1839 struct sky2_port *sky2 = netdev_priv(dev);
1840 struct sky2_hw *hw = sky2->hw;
1841 unsigned port = sky2->port;
1845 /* Never really got started! */
1849 if (netif_msg_ifdown(sky2))
1850 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1852 /* explicitly shut off tx incase we're restarting */
1853 sky2->restarting = 1;
1854 netif_tx_disable(dev);
1856 /* Force flow control off */
1857 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1859 /* Stop transmitter */
1860 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1861 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1863 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1864 RB_RST_SET | RB_DIS_OP_MD);
1866 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1867 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1868 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1870 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1872 /* Workaround shared GMAC reset */
1873 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1874 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1875 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1877 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1879 /* Force any delayed status interrrupt and NAPI */
1880 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1881 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1882 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1883 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1887 /* Disable port IRQ */
1888 imask = sky2_read32(hw, B0_IMSK);
1889 imask &= ~portirq_msk[port];
1890 sky2_write32(hw, B0_IMSK, imask);
1891 sky2_read32(hw, B0_IMSK);
1893 synchronize_irq(hw->pdev->irq);
1894 napi_synchronize(&hw->napi);
1896 spin_lock_bh(&sky2->phy_lock);
1897 sky2_phy_power_down(hw, port);
1898 spin_unlock_bh(&sky2->phy_lock);
1900 /* turn off LED's */
1901 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1903 sky2_tx_reset(hw, port);
1906 sky2_rx_clean(sky2);
1908 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1909 sky2->rx_le, sky2->rx_le_map);
1910 kfree(sky2->rx_ring);
1912 pci_free_consistent(hw->pdev,
1913 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1914 sky2->tx_le, sky2->tx_le_map);
1915 kfree(sky2->tx_ring);
1920 sky2->rx_ring = NULL;
1921 sky2->tx_ring = NULL;
1926 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1928 if (hw->flags & SKY2_HW_FIBRE_PHY)
1931 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1932 if (aux & PHY_M_PS_SPEED_100)
1938 switch (aux & PHY_M_PS_SPEED_MSK) {
1939 case PHY_M_PS_SPEED_1000:
1941 case PHY_M_PS_SPEED_100:
1948 static void sky2_link_up(struct sky2_port *sky2)
1950 struct sky2_hw *hw = sky2->hw;
1951 unsigned port = sky2->port;
1953 static const char *fc_name[] = {
1961 reg = gma_read16(hw, port, GM_GP_CTRL);
1962 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1963 gma_write16(hw, port, GM_GP_CTRL, reg);
1965 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1967 netif_carrier_on(sky2->netdev);
1969 mod_timer(&hw->watchdog_timer, jiffies + 1);
1971 /* Turn on link LED */
1972 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1973 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1975 if (netif_msg_link(sky2))
1976 printk(KERN_INFO PFX
1977 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1978 sky2->netdev->name, sky2->speed,
1979 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1980 fc_name[sky2->flow_status]);
1983 static void sky2_link_down(struct sky2_port *sky2)
1985 struct sky2_hw *hw = sky2->hw;
1986 unsigned port = sky2->port;
1989 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1991 reg = gma_read16(hw, port, GM_GP_CTRL);
1992 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1993 gma_write16(hw, port, GM_GP_CTRL, reg);
1995 netif_carrier_off(sky2->netdev);
1997 /* Turn on link LED */
1998 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2000 if (netif_msg_link(sky2))
2001 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2003 sky2_phy_init(hw, port);
2006 static enum flow_control sky2_flow(int rx, int tx)
2009 return tx ? FC_BOTH : FC_RX;
2011 return tx ? FC_TX : FC_NONE;
2014 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2016 struct sky2_hw *hw = sky2->hw;
2017 unsigned port = sky2->port;
2020 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2021 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2022 if (lpa & PHY_M_AN_RF) {
2023 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2027 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2028 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2029 sky2->netdev->name);
2033 sky2->speed = sky2_phy_speed(hw, aux);
2034 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2036 /* Since the pause result bits seem to in different positions on
2037 * different chips. look at registers.
2039 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2040 /* Shift for bits in fiber PHY */
2041 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2042 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2044 if (advert & ADVERTISE_1000XPAUSE)
2045 advert |= ADVERTISE_PAUSE_CAP;
2046 if (advert & ADVERTISE_1000XPSE_ASYM)
2047 advert |= ADVERTISE_PAUSE_ASYM;
2048 if (lpa & LPA_1000XPAUSE)
2049 lpa |= LPA_PAUSE_CAP;
2050 if (lpa & LPA_1000XPAUSE_ASYM)
2051 lpa |= LPA_PAUSE_ASYM;
2054 sky2->flow_status = FC_NONE;
2055 if (advert & ADVERTISE_PAUSE_CAP) {
2056 if (lpa & LPA_PAUSE_CAP)
2057 sky2->flow_status = FC_BOTH;
2058 else if (advert & ADVERTISE_PAUSE_ASYM)
2059 sky2->flow_status = FC_RX;
2060 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2061 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2062 sky2->flow_status = FC_TX;
2065 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2066 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2067 sky2->flow_status = FC_NONE;
2069 if (sky2->flow_status & FC_TX)
2070 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2072 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2077 /* Interrupt from PHY */
2078 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2080 struct net_device *dev = hw->dev[port];
2081 struct sky2_port *sky2 = netdev_priv(dev);
2082 u16 istatus, phystat;
2084 if (!netif_running(dev))
2087 spin_lock(&sky2->phy_lock);
2088 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2089 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2091 if (netif_msg_intr(sky2))
2092 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2093 sky2->netdev->name, istatus, phystat);
2095 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2096 if (sky2_autoneg_done(sky2, phystat) == 0)
2101 if (istatus & PHY_M_IS_LSP_CHANGE)
2102 sky2->speed = sky2_phy_speed(hw, phystat);
2104 if (istatus & PHY_M_IS_DUP_CHANGE)
2106 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2108 if (istatus & PHY_M_IS_LST_CHANGE) {
2109 if (phystat & PHY_M_PS_LINK_UP)
2112 sky2_link_down(sky2);
2115 spin_unlock(&sky2->phy_lock);
2118 /* Transmit timeout is only called if we are running, carrier is up
2119 * and tx queue is full (stopped).
2121 static void sky2_tx_timeout(struct net_device *dev)
2123 struct sky2_port *sky2 = netdev_priv(dev);
2124 struct sky2_hw *hw = sky2->hw;
2126 if (netif_msg_timer(sky2))
2127 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2129 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2130 dev->name, sky2->tx_cons, sky2->tx_prod,
2131 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2132 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2134 /* can't restart safely under softirq */
2135 schedule_work(&hw->restart_work);
2138 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2140 struct sky2_port *sky2 = netdev_priv(dev);
2141 struct sky2_hw *hw = sky2->hw;
2142 unsigned port = sky2->port;
2147 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2150 if (new_mtu > ETH_DATA_LEN &&
2151 (hw->chip_id == CHIP_ID_YUKON_FE ||
2152 hw->chip_id == CHIP_ID_YUKON_FE_P))
2155 if (!netif_running(dev)) {
2160 imask = sky2_read32(hw, B0_IMSK);
2161 sky2_write32(hw, B0_IMSK, 0);
2163 dev->trans_start = jiffies; /* prevent tx timeout */
2164 netif_stop_queue(dev);
2165 napi_disable(&hw->napi);
2167 synchronize_irq(hw->pdev->irq);
2169 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2170 sky2_set_tx_stfwd(hw, port);
2172 ctl = gma_read16(hw, port, GM_GP_CTRL);
2173 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2175 sky2_rx_clean(sky2);
2179 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2180 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2182 if (dev->mtu > ETH_DATA_LEN)
2183 mode |= GM_SMOD_JUMBO_ENA;
2185 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2187 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2189 err = sky2_rx_start(sky2);
2190 sky2_write32(hw, B0_IMSK, imask);
2192 sky2_read32(hw, B0_Y2_SP_LISR);
2193 napi_enable(&hw->napi);
2198 gma_write16(hw, port, GM_GP_CTRL, ctl);
2200 netif_wake_queue(dev);
2206 /* For small just reuse existing skb for next receive */
2207 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2208 const struct rx_ring_info *re,
2211 struct sk_buff *skb;
2213 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2215 skb_reserve(skb, 2);
2216 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2217 length, PCI_DMA_FROMDEVICE);
2218 skb_copy_from_linear_data(re->skb, skb->data, length);
2219 skb->ip_summed = re->skb->ip_summed;
2220 skb->csum = re->skb->csum;
2221 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2222 length, PCI_DMA_FROMDEVICE);
2223 re->skb->ip_summed = CHECKSUM_NONE;
2224 skb_put(skb, length);
2229 /* Adjust length of skb with fragments to match received data */
2230 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2231 unsigned int length)
2236 /* put header into skb */
2237 size = min(length, hdr_space);
2242 num_frags = skb_shinfo(skb)->nr_frags;
2243 for (i = 0; i < num_frags; i++) {
2244 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2247 /* don't need this page */
2248 __free_page(frag->page);
2249 --skb_shinfo(skb)->nr_frags;
2251 size = min(length, (unsigned) PAGE_SIZE);
2254 skb->data_len += size;
2255 skb->truesize += size;
2262 /* Normal packet - take skb from ring element and put in a new one */
2263 static struct sk_buff *receive_new(struct sky2_port *sky2,
2264 struct rx_ring_info *re,
2265 unsigned int length)
2267 struct sk_buff *skb, *nskb;
2268 unsigned hdr_space = sky2->rx_data_size;
2270 /* Don't be tricky about reusing pages (yet) */
2271 nskb = sky2_rx_alloc(sky2);
2272 if (unlikely(!nskb))
2276 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2278 prefetch(skb->data);
2280 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2281 dev_kfree_skb(nskb);
2286 if (skb_shinfo(skb)->nr_frags)
2287 skb_put_frags(skb, hdr_space, length);
2289 skb_put(skb, length);
2294 * Receive one packet.
2295 * For larger packets, get new buffer.
2297 static struct sk_buff *sky2_receive(struct net_device *dev,
2298 u16 length, u32 status)
2300 struct sky2_port *sky2 = netdev_priv(dev);
2301 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2302 struct sk_buff *skb = NULL;
2303 u16 count = (status & GMR_FS_LEN) >> 16;
2305 #ifdef SKY2_VLAN_TAG_USED
2306 /* Account for vlan tag */
2307 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2311 if (unlikely(netif_msg_rx_status(sky2)))
2312 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2313 dev->name, sky2->rx_next, status, length);
2315 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2316 prefetch(sky2->rx_ring + sky2->rx_next);
2318 /* This chip has hardware problems that generates bogus status.
2319 * So do only marginal checking and expect higher level protocols
2320 * to handle crap frames.
2322 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2323 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2327 if (status & GMR_FS_ANY_ERR)
2330 if (!(status & GMR_FS_RX_OK))
2333 /* if length reported by DMA does not match PHY, packet was truncated */
2334 if (length != count)
2338 if (length < copybreak)
2339 skb = receive_copy(sky2, re, length);
2341 skb = receive_new(sky2, re, length);
2343 sky2_rx_submit(sky2, re);
2348 /* Truncation of overlength packets
2349 causes PHY length to not match MAC length */
2350 ++dev->stats.rx_length_errors;
2351 if (netif_msg_rx_err(sky2) && net_ratelimit())
2352 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2353 dev->name, status, length);
2357 ++dev->stats.rx_errors;
2358 if (status & GMR_FS_RX_FF_OV) {
2359 dev->stats.rx_over_errors++;
2363 if (netif_msg_rx_err(sky2) && net_ratelimit())
2364 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2365 dev->name, status, length);
2367 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2368 dev->stats.rx_length_errors++;
2369 if (status & GMR_FS_FRAGMENT)
2370 dev->stats.rx_frame_errors++;
2371 if (status & GMR_FS_CRC_ERR)
2372 dev->stats.rx_crc_errors++;
2377 /* Transmit complete */
2378 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2380 struct sky2_port *sky2 = netdev_priv(dev);
2382 if (likely(netif_running(dev) && !sky2->restarting)) {
2384 sky2_tx_complete(sky2, last);
2385 netif_tx_unlock(dev);
2389 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2390 u32 status, struct sk_buff *skb)
2392 #ifdef SKY2_VLAN_TAG_USED
2393 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2394 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2395 if (skb->ip_summed == CHECKSUM_NONE)
2396 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2398 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2403 if (skb->ip_summed == CHECKSUM_NONE)
2404 netif_receive_skb(skb);
2406 napi_gro_receive(&sky2->hw->napi, skb);
2409 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2410 unsigned packets, unsigned bytes)
2413 struct net_device *dev = hw->dev[port];
2415 dev->stats.rx_packets += packets;
2416 dev->stats.rx_bytes += bytes;
2417 dev->last_rx = jiffies;
2418 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2422 /* Process status response ring */
2423 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2426 unsigned int total_bytes[2] = { 0 };
2427 unsigned int total_packets[2] = { 0 };
2431 struct sky2_port *sky2;
2432 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2434 struct net_device *dev;
2435 struct sk_buff *skb;
2438 u8 opcode = le->opcode;
2440 if (!(opcode & HW_OWNER))
2443 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2445 port = le->css & CSS_LINK_BIT;
2446 dev = hw->dev[port];
2447 sky2 = netdev_priv(dev);
2448 length = le16_to_cpu(le->length);
2449 status = le32_to_cpu(le->status);
2452 switch (opcode & ~HW_OWNER) {
2454 total_packets[port]++;
2455 total_bytes[port] += length;
2456 skb = sky2_receive(dev, length, status);
2457 if (unlikely(!skb)) {
2458 dev->stats.rx_dropped++;
2462 /* This chip reports checksum status differently */
2463 if (hw->flags & SKY2_HW_NEW_LE) {
2464 if (sky2->rx_csum &&
2465 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2466 (le->css & CSS_TCPUDPCSOK))
2467 skb->ip_summed = CHECKSUM_UNNECESSARY;
2469 skb->ip_summed = CHECKSUM_NONE;
2472 skb->protocol = eth_type_trans(skb, dev);
2474 sky2_skb_rx(sky2, status, skb);
2476 /* Stop after net poll weight */
2477 if (++work_done >= to_do)
2481 #ifdef SKY2_VLAN_TAG_USED
2483 sky2->rx_tag = length;
2487 sky2->rx_tag = length;
2494 /* If this happens then driver assuming wrong format */
2495 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2496 if (net_ratelimit())
2497 printk(KERN_NOTICE "%s: unexpected"
2498 " checksum status\n",
2503 /* Both checksum counters are programmed to start at
2504 * the same offset, so unless there is a problem they
2505 * should match. This failure is an early indication that
2506 * hardware receive checksumming won't work.
2508 if (likely(status >> 16 == (status & 0xffff))) {
2509 skb = sky2->rx_ring[sky2->rx_next].skb;
2510 skb->ip_summed = CHECKSUM_COMPLETE;
2511 skb->csum = le16_to_cpu(status);
2513 printk(KERN_NOTICE PFX "%s: hardware receive "
2514 "checksum problem (status = %#x)\n",
2517 sky2_write32(sky2->hw,
2518 Q_ADDR(rxqaddr[port], Q_CSR),
2524 /* TX index reports status for both ports */
2525 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2526 sky2_tx_done(hw->dev[0], status & 0xfff);
2528 sky2_tx_done(hw->dev[1],
2529 ((status >> 24) & 0xff)
2530 | (u16)(length & 0xf) << 8);
2534 if (net_ratelimit())
2535 printk(KERN_WARNING PFX
2536 "unknown status opcode 0x%x\n", opcode);
2538 } while (hw->st_idx != idx);
2540 /* Fully processed status ring so clear irq */
2541 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2544 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2545 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2550 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2552 struct net_device *dev = hw->dev[port];
2554 if (net_ratelimit())
2555 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2558 if (status & Y2_IS_PAR_RD1) {
2559 if (net_ratelimit())
2560 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2563 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2566 if (status & Y2_IS_PAR_WR1) {
2567 if (net_ratelimit())
2568 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2571 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2574 if (status & Y2_IS_PAR_MAC1) {
2575 if (net_ratelimit())
2576 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2577 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2580 if (status & Y2_IS_PAR_RX1) {
2581 if (net_ratelimit())
2582 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2583 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2586 if (status & Y2_IS_TCP_TXA1) {
2587 if (net_ratelimit())
2588 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2590 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2594 static void sky2_hw_intr(struct sky2_hw *hw)
2596 struct pci_dev *pdev = hw->pdev;
2597 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2598 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2602 if (status & Y2_IS_TIST_OV)
2603 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2605 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2608 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2609 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2610 if (net_ratelimit())
2611 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2614 sky2_pci_write16(hw, PCI_STATUS,
2615 pci_err | PCI_STATUS_ERROR_BITS);
2616 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2619 if (status & Y2_IS_PCI_EXP) {
2620 /* PCI-Express uncorrectable Error occurred */
2623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2624 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2625 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2627 if (net_ratelimit())
2628 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2630 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2631 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2634 if (status & Y2_HWE_L1_MASK)
2635 sky2_hw_error(hw, 0, status);
2637 if (status & Y2_HWE_L1_MASK)
2638 sky2_hw_error(hw, 1, status);
2641 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2643 struct net_device *dev = hw->dev[port];
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2647 if (netif_msg_intr(sky2))
2648 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2651 if (status & GM_IS_RX_CO_OV)
2652 gma_read16(hw, port, GM_RX_IRQ_SRC);
2654 if (status & GM_IS_TX_CO_OV)
2655 gma_read16(hw, port, GM_TX_IRQ_SRC);
2657 if (status & GM_IS_RX_FF_OR) {
2658 ++dev->stats.rx_fifo_errors;
2659 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2662 if (status & GM_IS_TX_FF_UR) {
2663 ++dev->stats.tx_fifo_errors;
2664 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2668 /* This should never happen it is a bug. */
2669 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2670 u16 q, unsigned ring_size)
2672 struct net_device *dev = hw->dev[port];
2673 struct sky2_port *sky2 = netdev_priv(dev);
2675 const u64 *le = (q == Q_R1 || q == Q_R2)
2676 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2678 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2679 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2680 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2681 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2683 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2686 static int sky2_rx_hung(struct net_device *dev)
2688 struct sky2_port *sky2 = netdev_priv(dev);
2689 struct sky2_hw *hw = sky2->hw;
2690 unsigned port = sky2->port;
2691 unsigned rxq = rxqaddr[port];
2692 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2693 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2694 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2695 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2697 /* If idle and MAC or PCI is stuck */
2698 if (sky2->check.last == dev->last_rx &&
2699 ((mac_rp == sky2->check.mac_rp &&
2700 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2701 /* Check if the PCI RX hang */
2702 (fifo_rp == sky2->check.fifo_rp &&
2703 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2704 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2705 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2706 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2709 sky2->check.last = dev->last_rx;
2710 sky2->check.mac_rp = mac_rp;
2711 sky2->check.mac_lev = mac_lev;
2712 sky2->check.fifo_rp = fifo_rp;
2713 sky2->check.fifo_lev = fifo_lev;
2718 static void sky2_watchdog(unsigned long arg)
2720 struct sky2_hw *hw = (struct sky2_hw *) arg;
2722 /* Check for lost IRQ once a second */
2723 if (sky2_read32(hw, B0_ISRC)) {
2724 napi_schedule(&hw->napi);
2728 for (i = 0; i < hw->ports; i++) {
2729 struct net_device *dev = hw->dev[i];
2730 if (!netif_running(dev))
2734 /* For chips with Rx FIFO, check if stuck */
2735 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2736 sky2_rx_hung(dev)) {
2737 pr_info(PFX "%s: receiver hang detected\n",
2739 schedule_work(&hw->restart_work);
2748 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2751 /* Hardware/software error handling */
2752 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2754 if (net_ratelimit())
2755 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2757 if (status & Y2_IS_HW_ERR)
2760 if (status & Y2_IS_IRQ_MAC1)
2761 sky2_mac_intr(hw, 0);
2763 if (status & Y2_IS_IRQ_MAC2)
2764 sky2_mac_intr(hw, 1);
2766 if (status & Y2_IS_CHK_RX1)
2767 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2769 if (status & Y2_IS_CHK_RX2)
2770 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2772 if (status & Y2_IS_CHK_TXA1)
2773 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2775 if (status & Y2_IS_CHK_TXA2)
2776 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2779 static int sky2_poll(struct napi_struct *napi, int work_limit)
2781 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2782 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2786 if (unlikely(status & Y2_IS_ERROR))
2787 sky2_err_intr(hw, status);
2789 if (status & Y2_IS_IRQ_PHY1)
2790 sky2_phy_intr(hw, 0);
2792 if (status & Y2_IS_IRQ_PHY2)
2793 sky2_phy_intr(hw, 1);
2795 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2796 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2798 if (work_done >= work_limit)
2802 napi_complete(napi);
2803 sky2_read32(hw, B0_Y2_SP_LISR);
2809 static irqreturn_t sky2_intr(int irq, void *dev_id)
2811 struct sky2_hw *hw = dev_id;
2814 /* Reading this mask interrupts as side effect */
2815 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2816 if (status == 0 || status == ~0)
2819 prefetch(&hw->st_le[hw->st_idx]);
2821 napi_schedule(&hw->napi);
2826 #ifdef CONFIG_NET_POLL_CONTROLLER
2827 static void sky2_netpoll(struct net_device *dev)
2829 struct sky2_port *sky2 = netdev_priv(dev);
2831 napi_schedule(&sky2->hw->napi);
2835 /* Chip internal frequency for clock calculations */
2836 static u32 sky2_mhz(const struct sky2_hw *hw)
2838 switch (hw->chip_id) {
2839 case CHIP_ID_YUKON_EC:
2840 case CHIP_ID_YUKON_EC_U:
2841 case CHIP_ID_YUKON_EX:
2842 case CHIP_ID_YUKON_SUPR:
2843 case CHIP_ID_YUKON_UL_2:
2846 case CHIP_ID_YUKON_FE:
2849 case CHIP_ID_YUKON_FE_P:
2852 case CHIP_ID_YUKON_XL:
2860 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2862 return sky2_mhz(hw) * us;
2865 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2867 return clk / sky2_mhz(hw);
2871 static int __devinit sky2_init(struct sky2_hw *hw)
2875 /* Enable all clocks and check for bad PCI access */
2876 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2878 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2880 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2881 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2883 switch(hw->chip_id) {
2884 case CHIP_ID_YUKON_XL:
2885 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2888 case CHIP_ID_YUKON_EC_U:
2889 hw->flags = SKY2_HW_GIGABIT
2891 | SKY2_HW_ADV_POWER_CTL;
2894 case CHIP_ID_YUKON_EX:
2895 hw->flags = SKY2_HW_GIGABIT
2898 | SKY2_HW_ADV_POWER_CTL;
2900 /* New transmit checksum */
2901 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2902 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2905 case CHIP_ID_YUKON_EC:
2906 /* This rev is really old, and requires untested workarounds */
2907 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2908 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2911 hw->flags = SKY2_HW_GIGABIT;
2914 case CHIP_ID_YUKON_FE:
2917 case CHIP_ID_YUKON_FE_P:
2918 hw->flags = SKY2_HW_NEWER_PHY
2920 | SKY2_HW_AUTO_TX_SUM
2921 | SKY2_HW_ADV_POWER_CTL;
2924 case CHIP_ID_YUKON_SUPR:
2925 hw->flags = SKY2_HW_GIGABIT
2928 | SKY2_HW_AUTO_TX_SUM
2929 | SKY2_HW_ADV_POWER_CTL;
2932 case CHIP_ID_YUKON_UL_2:
2933 hw->flags = SKY2_HW_GIGABIT
2934 | SKY2_HW_ADV_POWER_CTL;
2938 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2943 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2944 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2945 hw->flags |= SKY2_HW_FIBRE_PHY;
2948 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2949 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2950 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2957 static void sky2_reset(struct sky2_hw *hw)
2959 struct pci_dev *pdev = hw->pdev;
2962 u32 hwe_mask = Y2_HWE_ALL_MASK;
2965 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2966 status = sky2_read16(hw, HCU_CCSR);
2967 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2968 HCU_CCSR_UC_STATE_MSK);
2969 sky2_write16(hw, HCU_CCSR, status);
2971 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2972 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2975 sky2_write8(hw, B0_CTST, CS_RST_SET);
2976 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2978 /* allow writes to PCI config */
2979 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2981 /* clear PCI errors, if any */
2982 status = sky2_pci_read16(hw, PCI_STATUS);
2983 status |= PCI_STATUS_ERROR_BITS;
2984 sky2_pci_write16(hw, PCI_STATUS, status);
2986 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2988 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2990 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2993 /* If error bit is stuck on ignore it */
2994 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2995 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2997 hwe_mask |= Y2_IS_PCI_EXP;
3001 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3003 for (i = 0; i < hw->ports; i++) {
3004 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3005 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3007 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3008 hw->chip_id == CHIP_ID_YUKON_SUPR)
3009 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3010 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3014 /* Clear I2C IRQ noise */
3015 sky2_write32(hw, B2_I2C_IRQ, 1);
3017 /* turn off hardware timer (unused) */
3018 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3019 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3021 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3023 /* Turn off descriptor polling */
3024 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3026 /* Turn off receive timestamp */
3027 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3028 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3030 /* enable the Tx Arbiters */
3031 for (i = 0; i < hw->ports; i++)
3032 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3034 /* Initialize ram interface */
3035 for (i = 0; i < hw->ports; i++) {
3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3039 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3040 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3042 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3043 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3045 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3052 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3054 for (i = 0; i < hw->ports; i++)
3055 sky2_gmac_reset(hw, i);
3057 memset(hw->st_le, 0, STATUS_LE_BYTES);
3060 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3061 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3063 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3064 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3066 /* Set the list last index */
3067 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3069 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3070 sky2_write8(hw, STAT_FIFO_WM, 16);
3072 /* set Status-FIFO ISR watermark */
3073 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3074 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3076 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3078 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3079 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3080 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3082 /* enable status unit */
3083 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3085 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3086 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3087 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3090 static void sky2_restart(struct work_struct *work)
3092 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3093 struct net_device *dev;
3097 for (i = 0; i < hw->ports; i++) {
3099 if (netif_running(dev))
3103 napi_disable(&hw->napi);
3104 sky2_write32(hw, B0_IMSK, 0);
3106 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3107 napi_enable(&hw->napi);
3109 for (i = 0; i < hw->ports; i++) {
3111 if (netif_running(dev)) {
3114 printk(KERN_INFO PFX "%s: could not restart %d\n",
3124 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3126 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3129 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3131 const struct sky2_port *sky2 = netdev_priv(dev);
3133 wol->supported = sky2_wol_supported(sky2->hw);
3134 wol->wolopts = sky2->wol;
3137 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3139 struct sky2_port *sky2 = netdev_priv(dev);
3140 struct sky2_hw *hw = sky2->hw;
3142 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3143 || !device_can_wakeup(&hw->pdev->dev))
3146 sky2->wol = wol->wolopts;
3148 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3149 hw->chip_id == CHIP_ID_YUKON_EX ||
3150 hw->chip_id == CHIP_ID_YUKON_FE_P)
3151 sky2_write32(hw, B0_CTST, sky2->wol
3152 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3154 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3156 if (!netif_running(dev))
3157 sky2_wol_init(sky2);
3161 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3163 if (sky2_is_copper(hw)) {
3164 u32 modes = SUPPORTED_10baseT_Half
3165 | SUPPORTED_10baseT_Full
3166 | SUPPORTED_100baseT_Half
3167 | SUPPORTED_100baseT_Full
3168 | SUPPORTED_Autoneg | SUPPORTED_TP;
3170 if (hw->flags & SKY2_HW_GIGABIT)
3171 modes |= SUPPORTED_1000baseT_Half
3172 | SUPPORTED_1000baseT_Full;
3175 return SUPPORTED_1000baseT_Half
3176 | SUPPORTED_1000baseT_Full
3181 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3183 struct sky2_port *sky2 = netdev_priv(dev);
3184 struct sky2_hw *hw = sky2->hw;
3186 ecmd->transceiver = XCVR_INTERNAL;
3187 ecmd->supported = sky2_supported_modes(hw);
3188 ecmd->phy_address = PHY_ADDR_MARV;
3189 if (sky2_is_copper(hw)) {
3190 ecmd->port = PORT_TP;
3191 ecmd->speed = sky2->speed;
3193 ecmd->speed = SPEED_1000;
3194 ecmd->port = PORT_FIBRE;
3197 ecmd->advertising = sky2->advertising;
3198 ecmd->autoneg = sky2->autoneg;
3199 ecmd->duplex = sky2->duplex;
3203 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3205 struct sky2_port *sky2 = netdev_priv(dev);
3206 const struct sky2_hw *hw = sky2->hw;
3207 u32 supported = sky2_supported_modes(hw);
3209 if (ecmd->autoneg == AUTONEG_ENABLE) {
3210 ecmd->advertising = supported;
3216 switch (ecmd->speed) {
3218 if (ecmd->duplex == DUPLEX_FULL)
3219 setting = SUPPORTED_1000baseT_Full;
3220 else if (ecmd->duplex == DUPLEX_HALF)
3221 setting = SUPPORTED_1000baseT_Half;
3226 if (ecmd->duplex == DUPLEX_FULL)
3227 setting = SUPPORTED_100baseT_Full;
3228 else if (ecmd->duplex == DUPLEX_HALF)
3229 setting = SUPPORTED_100baseT_Half;
3235 if (ecmd->duplex == DUPLEX_FULL)
3236 setting = SUPPORTED_10baseT_Full;
3237 else if (ecmd->duplex == DUPLEX_HALF)
3238 setting = SUPPORTED_10baseT_Half;
3246 if ((setting & supported) == 0)
3249 sky2->speed = ecmd->speed;
3250 sky2->duplex = ecmd->duplex;
3253 sky2->autoneg = ecmd->autoneg;
3254 sky2->advertising = ecmd->advertising;
3256 if (netif_running(dev)) {
3257 sky2_phy_reinit(sky2);
3258 sky2_set_multicast(dev);
3264 static void sky2_get_drvinfo(struct net_device *dev,
3265 struct ethtool_drvinfo *info)
3267 struct sky2_port *sky2 = netdev_priv(dev);
3269 strcpy(info->driver, DRV_NAME);
3270 strcpy(info->version, DRV_VERSION);
3271 strcpy(info->fw_version, "N/A");
3272 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3275 static const struct sky2_stat {
3276 char name[ETH_GSTRING_LEN];
3279 { "tx_bytes", GM_TXO_OK_HI },
3280 { "rx_bytes", GM_RXO_OK_HI },
3281 { "tx_broadcast", GM_TXF_BC_OK },
3282 { "rx_broadcast", GM_RXF_BC_OK },
3283 { "tx_multicast", GM_TXF_MC_OK },
3284 { "rx_multicast", GM_RXF_MC_OK },
3285 { "tx_unicast", GM_TXF_UC_OK },
3286 { "rx_unicast", GM_RXF_UC_OK },
3287 { "tx_mac_pause", GM_TXF_MPAUSE },
3288 { "rx_mac_pause", GM_RXF_MPAUSE },
3289 { "collisions", GM_TXF_COL },
3290 { "late_collision",GM_TXF_LAT_COL },
3291 { "aborted", GM_TXF_ABO_COL },
3292 { "single_collisions", GM_TXF_SNG_COL },
3293 { "multi_collisions", GM_TXF_MUL_COL },
3295 { "rx_short", GM_RXF_SHT },
3296 { "rx_runt", GM_RXE_FRAG },
3297 { "rx_64_byte_packets", GM_RXF_64B },
3298 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3299 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3300 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3301 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3302 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3303 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3304 { "rx_too_long", GM_RXF_LNG_ERR },
3305 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3306 { "rx_jabber", GM_RXF_JAB_PKT },
3307 { "rx_fcs_error", GM_RXF_FCS_ERR },
3309 { "tx_64_byte_packets", GM_TXF_64B },
3310 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3311 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3312 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3313 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3314 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3315 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3316 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3319 static u32 sky2_get_rx_csum(struct net_device *dev)
3321 struct sky2_port *sky2 = netdev_priv(dev);
3323 return sky2->rx_csum;
3326 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3328 struct sky2_port *sky2 = netdev_priv(dev);
3330 sky2->rx_csum = data;
3332 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3333 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3338 static u32 sky2_get_msglevel(struct net_device *netdev)
3340 struct sky2_port *sky2 = netdev_priv(netdev);
3341 return sky2->msg_enable;
3344 static int sky2_nway_reset(struct net_device *dev)
3346 struct sky2_port *sky2 = netdev_priv(dev);
3348 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3351 sky2_phy_reinit(sky2);
3352 sky2_set_multicast(dev);
3357 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3359 struct sky2_hw *hw = sky2->hw;
3360 unsigned port = sky2->port;
3363 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3364 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3365 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3366 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3368 for (i = 2; i < count; i++)
3369 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3372 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3374 struct sky2_port *sky2 = netdev_priv(netdev);
3375 sky2->msg_enable = value;
3378 static int sky2_get_sset_count(struct net_device *dev, int sset)
3382 return ARRAY_SIZE(sky2_stats);
3388 static void sky2_get_ethtool_stats(struct net_device *dev,
3389 struct ethtool_stats *stats, u64 * data)
3391 struct sky2_port *sky2 = netdev_priv(dev);
3393 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3396 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3400 switch (stringset) {
3402 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3403 memcpy(data + i * ETH_GSTRING_LEN,
3404 sky2_stats[i].name, ETH_GSTRING_LEN);
3409 static int sky2_set_mac_address(struct net_device *dev, void *p)
3411 struct sky2_port *sky2 = netdev_priv(dev);
3412 struct sky2_hw *hw = sky2->hw;
3413 unsigned port = sky2->port;
3414 const struct sockaddr *addr = p;
3416 if (!is_valid_ether_addr(addr->sa_data))
3417 return -EADDRNOTAVAIL;
3419 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3420 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3421 dev->dev_addr, ETH_ALEN);
3422 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3423 dev->dev_addr, ETH_ALEN);
3425 /* virtual address for data */
3426 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3428 /* physical address: used for pause frames */
3429 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3434 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3438 bit = ether_crc(ETH_ALEN, addr) & 63;
3439 filter[bit >> 3] |= 1 << (bit & 7);
3442 static void sky2_set_multicast(struct net_device *dev)
3444 struct sky2_port *sky2 = netdev_priv(dev);
3445 struct sky2_hw *hw = sky2->hw;
3446 unsigned port = sky2->port;
3447 struct dev_mc_list *list = dev->mc_list;
3451 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3453 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3454 memset(filter, 0, sizeof(filter));
3456 reg = gma_read16(hw, port, GM_RX_CTRL);
3457 reg |= GM_RXCR_UCF_ENA;
3459 if (dev->flags & IFF_PROMISC) /* promiscuous */
3460 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3461 else if (dev->flags & IFF_ALLMULTI)
3462 memset(filter, 0xff, sizeof(filter));
3463 else if (dev->mc_count == 0 && !rx_pause)
3464 reg &= ~GM_RXCR_MCF_ENA;
3467 reg |= GM_RXCR_MCF_ENA;
3470 sky2_add_filter(filter, pause_mc_addr);
3472 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3473 sky2_add_filter(filter, list->dmi_addr);
3476 gma_write16(hw, port, GM_MC_ADDR_H1,
3477 (u16) filter[0] | ((u16) filter[1] << 8));
3478 gma_write16(hw, port, GM_MC_ADDR_H2,
3479 (u16) filter[2] | ((u16) filter[3] << 8));
3480 gma_write16(hw, port, GM_MC_ADDR_H3,
3481 (u16) filter[4] | ((u16) filter[5] << 8));
3482 gma_write16(hw, port, GM_MC_ADDR_H4,
3483 (u16) filter[6] | ((u16) filter[7] << 8));
3485 gma_write16(hw, port, GM_RX_CTRL, reg);
3488 /* Can have one global because blinking is controlled by
3489 * ethtool and that is always under RTNL mutex
3491 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3493 struct sky2_hw *hw = sky2->hw;
3494 unsigned port = sky2->port;
3496 spin_lock_bh(&sky2->phy_lock);
3497 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3498 hw->chip_id == CHIP_ID_YUKON_EX ||
3499 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3507 PHY_M_LEDC_LOS_CTRL(8) |
3508 PHY_M_LEDC_INIT_CTRL(8) |
3509 PHY_M_LEDC_STA1_CTRL(8) |
3510 PHY_M_LEDC_STA0_CTRL(8));
3513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3514 PHY_M_LEDC_LOS_CTRL(9) |
3515 PHY_M_LEDC_INIT_CTRL(9) |
3516 PHY_M_LEDC_STA1_CTRL(9) |
3517 PHY_M_LEDC_STA0_CTRL(9));
3520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3521 PHY_M_LEDC_LOS_CTRL(0xa) |
3522 PHY_M_LEDC_INIT_CTRL(0xa) |
3523 PHY_M_LEDC_STA1_CTRL(0xa) |
3524 PHY_M_LEDC_STA0_CTRL(0xa));
3527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3528 PHY_M_LEDC_LOS_CTRL(1) |
3529 PHY_M_LEDC_INIT_CTRL(8) |
3530 PHY_M_LEDC_STA1_CTRL(7) |
3531 PHY_M_LEDC_STA0_CTRL(7));
3534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3536 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3537 PHY_M_LED_MO_DUP(mode) |
3538 PHY_M_LED_MO_10(mode) |
3539 PHY_M_LED_MO_100(mode) |
3540 PHY_M_LED_MO_1000(mode) |
3541 PHY_M_LED_MO_RX(mode) |
3542 PHY_M_LED_MO_TX(mode));
3544 spin_unlock_bh(&sky2->phy_lock);
3547 /* blink LED's for finding board */
3548 static int sky2_phys_id(struct net_device *dev, u32 data)
3550 struct sky2_port *sky2 = netdev_priv(dev);
3556 for (i = 0; i < data; i++) {
3557 sky2_led(sky2, MO_LED_ON);
3558 if (msleep_interruptible(500))
3560 sky2_led(sky2, MO_LED_OFF);
3561 if (msleep_interruptible(500))
3564 sky2_led(sky2, MO_LED_NORM);
3569 static void sky2_get_pauseparam(struct net_device *dev,
3570 struct ethtool_pauseparam *ecmd)
3572 struct sky2_port *sky2 = netdev_priv(dev);
3574 switch (sky2->flow_mode) {
3576 ecmd->tx_pause = ecmd->rx_pause = 0;
3579 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3582 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3585 ecmd->tx_pause = ecmd->rx_pause = 1;
3588 ecmd->autoneg = sky2->autoneg;
3591 static int sky2_set_pauseparam(struct net_device *dev,
3592 struct ethtool_pauseparam *ecmd)
3594 struct sky2_port *sky2 = netdev_priv(dev);
3596 sky2->autoneg = ecmd->autoneg;
3597 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3599 if (netif_running(dev))
3600 sky2_phy_reinit(sky2);
3605 static int sky2_get_coalesce(struct net_device *dev,
3606 struct ethtool_coalesce *ecmd)
3608 struct sky2_port *sky2 = netdev_priv(dev);
3609 struct sky2_hw *hw = sky2->hw;
3611 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3612 ecmd->tx_coalesce_usecs = 0;
3614 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3615 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3617 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3619 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3620 ecmd->rx_coalesce_usecs = 0;
3622 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3623 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3625 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3627 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3628 ecmd->rx_coalesce_usecs_irq = 0;
3630 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3631 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3634 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3639 /* Note: this affect both ports */
3640 static int sky2_set_coalesce(struct net_device *dev,
3641 struct ethtool_coalesce *ecmd)
3643 struct sky2_port *sky2 = netdev_priv(dev);
3644 struct sky2_hw *hw = sky2->hw;
3645 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3647 if (ecmd->tx_coalesce_usecs > tmax ||
3648 ecmd->rx_coalesce_usecs > tmax ||
3649 ecmd->rx_coalesce_usecs_irq > tmax)
3652 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3654 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3656 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3659 if (ecmd->tx_coalesce_usecs == 0)
3660 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3662 sky2_write32(hw, STAT_TX_TIMER_INI,
3663 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3664 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3666 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3668 if (ecmd->rx_coalesce_usecs == 0)
3669 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3671 sky2_write32(hw, STAT_LEV_TIMER_INI,
3672 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3673 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3675 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3677 if (ecmd->rx_coalesce_usecs_irq == 0)
3678 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3680 sky2_write32(hw, STAT_ISR_TIMER_INI,
3681 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3682 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3684 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3688 static void sky2_get_ringparam(struct net_device *dev,
3689 struct ethtool_ringparam *ering)
3691 struct sky2_port *sky2 = netdev_priv(dev);
3693 ering->rx_max_pending = RX_MAX_PENDING;
3694 ering->rx_mini_max_pending = 0;
3695 ering->rx_jumbo_max_pending = 0;
3696 ering->tx_max_pending = TX_RING_SIZE - 1;
3698 ering->rx_pending = sky2->rx_pending;
3699 ering->rx_mini_pending = 0;
3700 ering->rx_jumbo_pending = 0;
3701 ering->tx_pending = sky2->tx_pending;
3704 static int sky2_set_ringparam(struct net_device *dev,
3705 struct ethtool_ringparam *ering)
3707 struct sky2_port *sky2 = netdev_priv(dev);
3710 if (ering->rx_pending > RX_MAX_PENDING ||
3711 ering->rx_pending < 8 ||
3712 ering->tx_pending < MAX_SKB_TX_LE ||
3713 ering->tx_pending > TX_RING_SIZE - 1)
3716 if (netif_running(dev))
3719 sky2->rx_pending = ering->rx_pending;
3720 sky2->tx_pending = ering->tx_pending;
3722 if (netif_running(dev)) {
3731 static int sky2_get_regs_len(struct net_device *dev)
3737 * Returns copy of control register region
3738 * Note: ethtool_get_regs always provides full size (16k) buffer
3740 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3743 const struct sky2_port *sky2 = netdev_priv(dev);
3744 const void __iomem *io = sky2->hw->regs;
3749 for (b = 0; b < 128; b++) {
3750 /* This complicated switch statement is to make sure and
3751 * only access regions that are unreserved.
3752 * Some blocks are only valid on dual port cards.
3753 * and block 3 has some special diagnostic registers that
3758 /* skip diagnostic ram region */
3759 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3762 /* dual port cards only */
3763 case 5: /* Tx Arbiter 2 */
3765 case 14 ... 15: /* TX2 */
3766 case 17: case 19: /* Ram Buffer 2 */
3767 case 22 ... 23: /* Tx Ram Buffer 2 */
3768 case 25: /* Rx MAC Fifo 1 */
3769 case 27: /* Tx MAC Fifo 2 */
3770 case 31: /* GPHY 2 */
3771 case 40 ... 47: /* Pattern Ram 2 */
3772 case 52: case 54: /* TCP Segmentation 2 */
3773 case 112 ... 116: /* GMAC 2 */
3774 if (sky2->hw->ports == 1)
3777 case 0: /* Control */
3778 case 2: /* Mac address */
3779 case 4: /* Tx Arbiter 1 */
3780 case 7: /* PCI express reg */
3782 case 12 ... 13: /* TX1 */
3783 case 16: case 18:/* Rx Ram Buffer 1 */
3784 case 20 ... 21: /* Tx Ram Buffer 1 */
3785 case 24: /* Rx MAC Fifo 1 */
3786 case 26: /* Tx MAC Fifo 1 */
3787 case 28 ... 29: /* Descriptor and status unit */
3788 case 30: /* GPHY 1*/
3789 case 32 ... 39: /* Pattern Ram 1 */
3790 case 48: case 50: /* TCP Segmentation 1 */
3791 case 56 ... 60: /* PCI space */
3792 case 80 ... 84: /* GMAC 1 */
3793 memcpy_fromio(p, io, 128);
3805 /* In order to do Jumbo packets on these chips, need to turn off the
3806 * transmit store/forward. Therefore checksum offload won't work.
3808 static int no_tx_offload(struct net_device *dev)
3810 const struct sky2_port *sky2 = netdev_priv(dev);
3811 const struct sky2_hw *hw = sky2->hw;
3813 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3816 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3818 if (data && no_tx_offload(dev))
3821 return ethtool_op_set_tx_csum(dev, data);
3825 static int sky2_set_tso(struct net_device *dev, u32 data)
3827 if (data && no_tx_offload(dev))
3830 return ethtool_op_set_tso(dev, data);
3833 static int sky2_get_eeprom_len(struct net_device *dev)
3835 struct sky2_port *sky2 = netdev_priv(dev);
3836 struct sky2_hw *hw = sky2->hw;
3839 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3840 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3843 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3845 unsigned long start = jiffies;
3847 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3848 /* Can take up to 10.6 ms for write */
3849 if (time_after(jiffies, start + HZ/4)) {
3850 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3859 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3860 u16 offset, size_t length)
3864 while (length > 0) {
3867 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3868 rc = sky2_vpd_wait(hw, cap, 0);
3872 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3874 memcpy(data, &val, min(sizeof(val), length));
3875 offset += sizeof(u32);
3876 data += sizeof(u32);
3877 length -= sizeof(u32);
3883 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3884 u16 offset, unsigned int length)
3889 for (i = 0; i < length; i += sizeof(u32)) {
3890 u32 val = *(u32 *)(data + i);
3892 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3893 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3895 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3902 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3905 struct sky2_port *sky2 = netdev_priv(dev);
3906 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3911 eeprom->magic = SKY2_EEPROM_MAGIC;
3913 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3916 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3919 struct sky2_port *sky2 = netdev_priv(dev);
3920 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3925 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3928 /* Partial writes not supported */
3929 if ((eeprom->offset & 3) || (eeprom->len & 3))
3932 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3936 static const struct ethtool_ops sky2_ethtool_ops = {
3937 .get_settings = sky2_get_settings,
3938 .set_settings = sky2_set_settings,
3939 .get_drvinfo = sky2_get_drvinfo,
3940 .get_wol = sky2_get_wol,
3941 .set_wol = sky2_set_wol,
3942 .get_msglevel = sky2_get_msglevel,
3943 .set_msglevel = sky2_set_msglevel,
3944 .nway_reset = sky2_nway_reset,
3945 .get_regs_len = sky2_get_regs_len,
3946 .get_regs = sky2_get_regs,
3947 .get_link = ethtool_op_get_link,
3948 .get_eeprom_len = sky2_get_eeprom_len,
3949 .get_eeprom = sky2_get_eeprom,
3950 .set_eeprom = sky2_set_eeprom,
3951 .set_sg = ethtool_op_set_sg,
3952 .set_tx_csum = sky2_set_tx_csum,
3953 .set_tso = sky2_set_tso,
3954 .get_rx_csum = sky2_get_rx_csum,
3955 .set_rx_csum = sky2_set_rx_csum,
3956 .get_strings = sky2_get_strings,
3957 .get_coalesce = sky2_get_coalesce,
3958 .set_coalesce = sky2_set_coalesce,
3959 .get_ringparam = sky2_get_ringparam,
3960 .set_ringparam = sky2_set_ringparam,
3961 .get_pauseparam = sky2_get_pauseparam,
3962 .set_pauseparam = sky2_set_pauseparam,
3963 .phys_id = sky2_phys_id,
3964 .get_sset_count = sky2_get_sset_count,
3965 .get_ethtool_stats = sky2_get_ethtool_stats,
3968 #ifdef CONFIG_SKY2_DEBUG
3970 static struct dentry *sky2_debug;
3974 * Read and parse the first part of Vital Product Data
3976 #define VPD_SIZE 128
3977 #define VPD_MAGIC 0x82
3979 static const struct vpd_tag {
3983 { "PN", "Part Number" },
3984 { "EC", "Engineering Level" },
3985 { "MN", "Manufacturer" },
3986 { "SN", "Serial Number" },
3987 { "YA", "Asset Tag" },
3988 { "VL", "First Error Log Message" },
3989 { "VF", "Second Error Log Message" },
3990 { "VB", "Boot Agent ROM Configuration" },
3991 { "VE", "EFI UNDI Configuration" },
3994 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4002 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4003 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4005 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4006 buf = kmalloc(vpd_size, GFP_KERNEL);
4008 seq_puts(seq, "no memory!\n");
4012 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4013 seq_puts(seq, "VPD read failed\n");
4017 if (buf[0] != VPD_MAGIC) {
4018 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4022 if (len == 0 || len > vpd_size - 4) {
4023 seq_printf(seq, "Invalid id length: %d\n", len);
4027 seq_printf(seq, "%.*s\n", len, buf + 3);
4030 while (offs < vpd_size - 4) {
4033 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4035 len = buf[offs + 2];
4036 if (offs + len + 3 >= vpd_size)
4039 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4040 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4041 seq_printf(seq, " %s: %.*s\n",
4042 vpd_tags[i].label, len, buf + offs + 3);
4052 static int sky2_debug_show(struct seq_file *seq, void *v)
4054 struct net_device *dev = seq->private;
4055 const struct sky2_port *sky2 = netdev_priv(dev);
4056 struct sky2_hw *hw = sky2->hw;
4057 unsigned port = sky2->port;
4061 sky2_show_vpd(seq, hw);
4063 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4064 sky2_read32(hw, B0_ISRC),
4065 sky2_read32(hw, B0_IMSK),
4066 sky2_read32(hw, B0_Y2_SP_ICR));
4068 if (!netif_running(dev)) {
4069 seq_printf(seq, "network not running\n");
4073 napi_disable(&hw->napi);
4074 last = sky2_read16(hw, STAT_PUT_IDX);
4076 if (hw->st_idx == last)
4077 seq_puts(seq, "Status ring (empty)\n");
4079 seq_puts(seq, "Status ring\n");
4080 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4081 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4082 const struct sky2_status_le *le = hw->st_le + idx;
4083 seq_printf(seq, "[%d] %#x %d %#x\n",
4084 idx, le->opcode, le->length, le->status);
4086 seq_puts(seq, "\n");
4089 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4090 sky2->tx_cons, sky2->tx_prod,
4091 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4092 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4094 /* Dump contents of tx ring */
4096 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4097 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4098 const struct sky2_tx_le *le = sky2->tx_le + idx;
4099 u32 a = le32_to_cpu(le->addr);
4102 seq_printf(seq, "%u:", idx);
4105 switch(le->opcode & ~HW_OWNER) {
4107 seq_printf(seq, " %#x:", a);
4110 seq_printf(seq, " mtu=%d", a);
4113 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4116 seq_printf(seq, " csum=%#x", a);
4119 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4122 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4125 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4128 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4129 a, le16_to_cpu(le->length));
4132 if (le->ctrl & EOP) {
4133 seq_putc(seq, '\n');
4138 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4139 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4140 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4141 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4143 sky2_read32(hw, B0_Y2_SP_LISR);
4144 napi_enable(&hw->napi);
4148 static int sky2_debug_open(struct inode *inode, struct file *file)
4150 return single_open(file, sky2_debug_show, inode->i_private);
4153 static const struct file_operations sky2_debug_fops = {
4154 .owner = THIS_MODULE,
4155 .open = sky2_debug_open,
4157 .llseek = seq_lseek,
4158 .release = single_release,
4162 * Use network device events to create/remove/rename
4163 * debugfs file entries
4165 static int sky2_device_event(struct notifier_block *unused,
4166 unsigned long event, void *ptr)
4168 struct net_device *dev = ptr;
4169 struct sky2_port *sky2 = netdev_priv(dev);
4171 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4175 case NETDEV_CHANGENAME:
4176 if (sky2->debugfs) {
4177 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4178 sky2_debug, dev->name);
4182 case NETDEV_GOING_DOWN:
4183 if (sky2->debugfs) {
4184 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4186 debugfs_remove(sky2->debugfs);
4187 sky2->debugfs = NULL;
4192 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4195 if (IS_ERR(sky2->debugfs))
4196 sky2->debugfs = NULL;
4202 static struct notifier_block sky2_notifier = {
4203 .notifier_call = sky2_device_event,
4207 static __init void sky2_debug_init(void)
4211 ent = debugfs_create_dir("sky2", NULL);
4212 if (!ent || IS_ERR(ent))
4216 register_netdevice_notifier(&sky2_notifier);
4219 static __exit void sky2_debug_cleanup(void)
4222 unregister_netdevice_notifier(&sky2_notifier);
4223 debugfs_remove(sky2_debug);
4229 #define sky2_debug_init()
4230 #define sky2_debug_cleanup()
4233 /* Two copies of network device operations to handle special case of
4234 not allowing netpoll on second port */
4235 static const struct net_device_ops sky2_netdev_ops[2] = {
4237 .ndo_open = sky2_up,
4238 .ndo_stop = sky2_down,
4239 .ndo_start_xmit = sky2_xmit_frame,
4240 .ndo_do_ioctl = sky2_ioctl,
4241 .ndo_validate_addr = eth_validate_addr,
4242 .ndo_set_mac_address = sky2_set_mac_address,
4243 .ndo_set_multicast_list = sky2_set_multicast,
4244 .ndo_change_mtu = sky2_change_mtu,
4245 .ndo_tx_timeout = sky2_tx_timeout,
4246 #ifdef SKY2_VLAN_TAG_USED
4247 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4249 #ifdef CONFIG_NET_POLL_CONTROLLER
4250 .ndo_poll_controller = sky2_netpoll,
4254 .ndo_open = sky2_up,
4255 .ndo_stop = sky2_down,
4256 .ndo_start_xmit = sky2_xmit_frame,
4257 .ndo_do_ioctl = sky2_ioctl,
4258 .ndo_validate_addr = eth_validate_addr,
4259 .ndo_set_mac_address = sky2_set_mac_address,
4260 .ndo_set_multicast_list = sky2_set_multicast,
4261 .ndo_change_mtu = sky2_change_mtu,
4262 .ndo_tx_timeout = sky2_tx_timeout,
4263 #ifdef SKY2_VLAN_TAG_USED
4264 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4269 /* Initialize network device */
4270 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4272 int highmem, int wol)
4274 struct sky2_port *sky2;
4275 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4278 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4282 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4283 dev->irq = hw->pdev->irq;
4284 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4285 dev->watchdog_timeo = TX_WATCHDOG;
4286 dev->netdev_ops = &sky2_netdev_ops[port];
4288 sky2 = netdev_priv(dev);
4291 sky2->msg_enable = netif_msg_init(debug, default_msg);
4293 /* Auto speed and flow control */
4294 sky2->autoneg = AUTONEG_ENABLE;
4295 sky2->flow_mode = FC_BOTH;
4299 sky2->advertising = sky2_supported_modes(hw);
4300 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4303 spin_lock_init(&sky2->phy_lock);
4304 sky2->tx_pending = TX_DEF_PENDING;
4305 sky2->rx_pending = RX_DEF_PENDING;
4306 sky2->restarting = 0;
4308 hw->dev[port] = dev;
4312 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4314 dev->features |= NETIF_F_HIGHDMA;
4316 #ifdef SKY2_VLAN_TAG_USED
4317 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4318 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4319 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4320 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4324 /* read the mac address */
4325 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4326 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4331 static void __devinit sky2_show_addr(struct net_device *dev)
4333 const struct sky2_port *sky2 = netdev_priv(dev);
4335 if (netif_msg_probe(sky2))
4336 printk(KERN_INFO PFX "%s: addr %pM\n",
4337 dev->name, dev->dev_addr);
4340 /* Handle software interrupt used during MSI test */
4341 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4343 struct sky2_hw *hw = dev_id;
4344 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4349 if (status & Y2_IS_IRQ_SW) {
4350 hw->flags |= SKY2_HW_USE_MSI;
4351 wake_up(&hw->msi_wait);
4352 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4354 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4359 /* Test interrupt path by forcing a a software IRQ */
4360 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4362 struct pci_dev *pdev = hw->pdev;
4365 init_waitqueue_head (&hw->msi_wait);
4367 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4369 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4371 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4375 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4376 sky2_read8(hw, B0_CTST);
4378 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4380 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4381 /* MSI test failed, go back to INTx mode */
4382 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4383 "switching to INTx mode.\n");
4386 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4389 sky2_write32(hw, B0_IMSK, 0);
4390 sky2_read32(hw, B0_IMSK);
4392 free_irq(pdev->irq, hw);
4397 /* This driver supports yukon2 chipset only */
4398 static const char *sky2_name(u8 chipid, char *buf, int sz)
4400 const char *name[] = {
4402 "EC Ultra", /* 0xb4 */
4403 "Extreme", /* 0xb5 */
4407 "Supreme", /* 0xb9 */
4411 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4412 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4414 snprintf(buf, sz, "(chip %#x)", chipid);
4418 static int __devinit sky2_probe(struct pci_dev *pdev,
4419 const struct pci_device_id *ent)
4421 struct net_device *dev;
4423 int err, using_dac = 0, wol_default;
4427 err = pci_enable_device(pdev);
4429 dev_err(&pdev->dev, "cannot enable PCI device\n");
4433 /* Get configuration information
4434 * Note: only regular PCI config access once to test for HW issues
4435 * other PCI access through shared memory for speed and to
4436 * avoid MMCONFIG problems.
4438 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4440 dev_err(&pdev->dev, "PCI read config failed\n");
4445 dev_err(&pdev->dev, "PCI configuration read error\n");
4449 err = pci_request_regions(pdev, DRV_NAME);
4451 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4452 goto err_out_disable;
4455 pci_set_master(pdev);
4457 if (sizeof(dma_addr_t) > sizeof(u32) &&
4458 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4460 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4462 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4463 "for consistent allocations\n");
4464 goto err_out_free_regions;
4467 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4469 dev_err(&pdev->dev, "no usable DMA configuration\n");
4470 goto err_out_free_regions;
4476 /* The sk98lin vendor driver uses hardware byte swapping but
4477 * this driver uses software swapping.
4479 reg &= ~PCI_REV_DESC;
4480 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4482 dev_err(&pdev->dev, "PCI write config failed\n");
4483 goto err_out_free_regions;
4487 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4490 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4492 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4493 goto err_out_free_regions;
4498 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4500 dev_err(&pdev->dev, "cannot map device registers\n");
4501 goto err_out_free_hw;
4504 /* ring for status responses */
4505 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4507 goto err_out_iounmap;
4509 err = sky2_init(hw);
4511 goto err_out_iounmap;
4513 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4514 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4518 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4521 goto err_out_free_pci;
4524 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4525 err = sky2_test_msi(hw);
4526 if (err == -EOPNOTSUPP)
4527 pci_disable_msi(pdev);
4529 goto err_out_free_netdev;
4532 err = register_netdev(dev);
4534 dev_err(&pdev->dev, "cannot register net device\n");
4535 goto err_out_free_netdev;
4538 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4540 err = request_irq(pdev->irq, sky2_intr,
4541 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4544 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4545 goto err_out_unregister;
4547 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4548 napi_enable(&hw->napi);
4550 sky2_show_addr(dev);
4552 if (hw->ports > 1) {
4553 struct net_device *dev1;
4555 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4557 dev_warn(&pdev->dev, "allocation for second device failed\n");
4558 else if ((err = register_netdev(dev1))) {
4559 dev_warn(&pdev->dev,
4560 "register of second port failed (%d)\n", err);
4564 sky2_show_addr(dev1);
4567 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4568 INIT_WORK(&hw->restart_work, sky2_restart);
4570 pci_set_drvdata(pdev, hw);
4575 if (hw->flags & SKY2_HW_USE_MSI)
4576 pci_disable_msi(pdev);
4577 unregister_netdev(dev);
4578 err_out_free_netdev:
4581 sky2_write8(hw, B0_CTST, CS_RST_SET);
4582 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4587 err_out_free_regions:
4588 pci_release_regions(pdev);
4590 pci_disable_device(pdev);
4592 pci_set_drvdata(pdev, NULL);
4596 static void __devexit sky2_remove(struct pci_dev *pdev)
4598 struct sky2_hw *hw = pci_get_drvdata(pdev);
4604 del_timer_sync(&hw->watchdog_timer);
4605 cancel_work_sync(&hw->restart_work);
4607 for (i = hw->ports-1; i >= 0; --i)
4608 unregister_netdev(hw->dev[i]);
4610 sky2_write32(hw, B0_IMSK, 0);
4614 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4615 sky2_write8(hw, B0_CTST, CS_RST_SET);
4616 sky2_read8(hw, B0_CTST);
4618 free_irq(pdev->irq, hw);
4619 if (hw->flags & SKY2_HW_USE_MSI)
4620 pci_disable_msi(pdev);
4621 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4622 pci_release_regions(pdev);
4623 pci_disable_device(pdev);
4625 for (i = hw->ports-1; i >= 0; --i)
4626 free_netdev(hw->dev[i]);
4631 pci_set_drvdata(pdev, NULL);
4635 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4637 struct sky2_hw *hw = pci_get_drvdata(pdev);
4643 del_timer_sync(&hw->watchdog_timer);
4644 cancel_work_sync(&hw->restart_work);
4646 for (i = 0; i < hw->ports; i++) {
4647 struct net_device *dev = hw->dev[i];
4648 struct sky2_port *sky2 = netdev_priv(dev);
4650 netif_device_detach(dev);
4651 if (netif_running(dev))
4655 sky2_wol_init(sky2);
4660 sky2_write32(hw, B0_IMSK, 0);
4661 napi_disable(&hw->napi);
4664 pci_save_state(pdev);
4665 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4666 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4671 static int sky2_resume(struct pci_dev *pdev)
4673 struct sky2_hw *hw = pci_get_drvdata(pdev);
4679 err = pci_set_power_state(pdev, PCI_D0);
4683 err = pci_restore_state(pdev);
4687 pci_enable_wake(pdev, PCI_D0, 0);
4689 /* Re-enable all clocks */
4690 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4691 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4692 hw->chip_id == CHIP_ID_YUKON_FE_P)
4693 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4696 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4697 napi_enable(&hw->napi);
4699 for (i = 0; i < hw->ports; i++) {
4700 struct net_device *dev = hw->dev[i];
4702 netif_device_attach(dev);
4703 if (netif_running(dev)) {
4706 printk(KERN_ERR PFX "%s: could not up: %d\n",
4718 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4719 pci_disable_device(pdev);
4724 static void sky2_shutdown(struct pci_dev *pdev)
4726 struct sky2_hw *hw = pci_get_drvdata(pdev);
4732 del_timer_sync(&hw->watchdog_timer);
4734 for (i = 0; i < hw->ports; i++) {
4735 struct net_device *dev = hw->dev[i];
4736 struct sky2_port *sky2 = netdev_priv(dev);
4740 sky2_wol_init(sky2);
4747 pci_enable_wake(pdev, PCI_D3hot, wol);
4748 pci_enable_wake(pdev, PCI_D3cold, wol);
4750 pci_disable_device(pdev);
4751 pci_set_power_state(pdev, PCI_D3hot);
4754 static struct pci_driver sky2_driver = {
4756 .id_table = sky2_id_table,
4757 .probe = sky2_probe,
4758 .remove = __devexit_p(sky2_remove),
4760 .suspend = sky2_suspend,
4761 .resume = sky2_resume,
4763 .shutdown = sky2_shutdown,
4766 static int __init sky2_init_module(void)
4768 pr_info(PFX "driver version " DRV_VERSION "\n");
4771 return pci_register_driver(&sky2_driver);
4774 static void __exit sky2_cleanup_module(void)
4776 pci_unregister_driver(&sky2_driver);
4777 sky2_debug_cleanup();
4780 module_init(sky2_init_module);
4781 module_exit(sky2_cleanup_module);
4783 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4784 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4785 MODULE_LICENSE("GPL");
4786 MODULE_VERSION(DRV_VERSION);