2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.25"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN + TSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
145 MODULE_DEVICE_TABLE(pci, sky2_id_table);
147 /* Avoid conditionals by using array */
148 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
149 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
150 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
152 static void sky2_set_multicast(struct net_device *dev);
154 /* Access to PHY via serial interconnect */
155 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163 for (i = 0; i < PHY_RETRIES; i++) {
164 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (!(ctrl & GM_SMI_CT_BUSY))
174 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
178 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
186 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189 for (i = 0; i < PHY_RETRIES; i++) {
190 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl & GM_SMI_CT_RD_VAL) {
195 *val = gma_read16(hw, port, GM_SMI_DATA);
202 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 __gm_phy_read(hw, port, reg, &v);
217 static void sky2_power_on(struct sky2_hw *hw)
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw, B0_POWER_CTRL,
221 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
223 /* disable Core Clock Division, */
224 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
227 /* enable bits are inverted */
228 sky2_write8(hw, B2_Y2_CLK_GATE,
229 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
230 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
231 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
235 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
240 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg &= P_ASPM_CONTROL_MSK;
243 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
245 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
246 /* set all bits to 0 except bits 28 & 27 */
247 reg &= P_CTL_TIM_VMAIN_AV_MSK;
248 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
250 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
257 sky2_read32(hw, B2_GP_IO);
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 static void sky2_power_aux(struct sky2_hw *hw)
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275 /* switch power to VAUX */
276 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
277 sky2_write8(hw, B0_POWER_CTRL,
278 (PC_VAUX_ENA | PC_VCC_ENA |
279 PC_VAUX_ON | PC_VCC_OFF));
281 /* turn off "driver loaded LED" */
282 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
285 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
302 /* flow control to advertise bits */
303 static const u16 copper_fc_adv[] = {
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310 /* flow control to advertise bits when using 1000BaseX */
311 static const u16 fiber_fc_adv[] = {
312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
318 /* flow control to GMA disable bits */
319 static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
327 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
332 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
341 if (hw->chip_id == CHIP_ID_YUKON_EC)
342 /* set downshift counter to 3x and enable downshift */
343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 if (sky2_is_copper(hw)) {
353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373 /* downshift on PHY 88E1112 and 88E1149 is changed */
374 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
375 && (hw->flags & SKY2_HW_NEWER_PHY)) {
376 /* set downshift counter to 3x and enable downshift */
377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390 /* special setup for PHY 88E1112 Fiber */
391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401 if (hw->pmd_type == 'P') {
402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
419 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
420 if (sky2_is_copper(hw)) {
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2->advertising & ADVERTISED_1000baseT_Full)
436 adv |= PHY_M_AN_1000X_AFD;
437 if (sky2->advertising & ADVERTISED_1000baseT_Half)
438 adv |= PHY_M_AN_1000X_AHD;
441 /* Restart Auto-negotiation */
442 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
444 /* forced speed/duplex settings */
445 ct1000 = PHY_M_1000C_MSE;
447 /* Disable auto update for duplex flow control and duplex */
448 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
450 switch (sky2->speed) {
452 ctrl |= PHY_CT_SP1000;
453 reg |= GM_GPCR_SPEED_1000;
456 ctrl |= PHY_CT_SP100;
457 reg |= GM_GPCR_SPEED_100;
461 if (sky2->duplex == DUPLEX_FULL) {
462 reg |= GM_GPCR_DUP_FULL;
463 ctrl |= PHY_CT_DUP_MD;
464 } else if (sky2->speed < SPEED_1000)
465 sky2->flow_mode = FC_NONE;
468 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
469 if (sky2_is_copper(hw))
470 adv |= copper_fc_adv[sky2->flow_mode];
472 adv |= fiber_fc_adv[sky2->flow_mode];
474 reg |= GM_GPCR_AU_FCT_DIS;
475 reg |= gm_fc_disable[sky2->flow_mode];
477 /* Forward pause packets to GMAC? */
478 if (sky2->flow_mode & FC_RX)
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
484 gma_write16(hw, port, GM_GP_CTRL, reg);
486 if (hw->flags & SKY2_HW_GIGABIT)
487 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
489 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
490 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
492 /* Setup Phy LED's */
493 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
496 switch (hw->chip_id) {
497 case CHIP_ID_YUKON_FE:
498 /* on 88E3082 these bits are at 11..9 (shifted left) */
499 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
501 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
503 /* delete ACT LED control bits */
504 ctrl &= ~PHY_M_FELP_LED1_MSK;
505 /* change ACT LED control to blink mode */
506 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 case CHIP_ID_YUKON_FE_P:
511 /* Enable Link Partner Next Page */
512 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
513 ctrl |= PHY_M_PC_ENA_LIP_NP;
515 /* disable Energy Detect and enable scrambler */
516 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
519 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
520 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
521 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
522 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
524 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 case CHIP_ID_YUKON_XL:
528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530 /* select page 3 to access LED control register */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
533 /* set LED Function Control register */
534 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
535 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
536 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
537 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
538 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
540 /* set Polarity Control register */
541 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
542 (PHY_M_POLC_LS1_P_MIX(4) |
543 PHY_M_POLC_IS0_P_MIX(4) |
544 PHY_M_POLC_LOS_CTRL(2) |
545 PHY_M_POLC_INIT_CTRL(2) |
546 PHY_M_POLC_STA1_CTRL(2) |
547 PHY_M_POLC_STA0_CTRL(2)));
549 /* restore page register */
550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
553 case CHIP_ID_YUKON_EC_U:
554 case CHIP_ID_YUKON_EX:
555 case CHIP_ID_YUKON_SUPR:
556 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
558 /* select page 3 to access LED control register */
559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
561 /* set LED Function Control register */
562 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
563 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
564 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
565 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
566 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
568 /* set Blink Rate in LED Timer Control Register */
569 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
570 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
571 /* restore page register */
572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
577 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
579 /* turn off the Rx LED (LED_RX) */
580 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
583 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
584 /* apply fixes in PHY AFE */
585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
587 /* increase differential signal amplitude in 10BASE-T */
588 gm_phy_write(hw, port, 0x18, 0xaa99);
589 gm_phy_write(hw, port, 0x17, 0x2011);
591 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
592 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xa204);
594 gm_phy_write(hw, port, 0x17, 0x2002);
597 /* set page register to 0 */
598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
599 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
600 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
601 /* apply workaround for integrated resistors calibration */
602 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
603 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
604 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
605 hw->chip_id < CHIP_ID_YUKON_SUPR) {
606 /* no effect on Yukon-XL */
607 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
609 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
610 || sky2->speed == SPEED_100) {
611 /* turn on 100 Mbps LED (LED_LINK100) */
612 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
616 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
620 /* Enable phy interrupt on auto-negotiation complete (or link up) */
621 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
622 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
624 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
627 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
628 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
630 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
634 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
635 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
636 reg1 &= ~phy_power[port];
638 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
639 reg1 |= coma_mode[port];
641 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
643 sky2_pci_read32(hw, PCI_DEV_REG1);
645 if (hw->chip_id == CHIP_ID_YUKON_FE)
646 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
647 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
651 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
656 /* release GPHY Control reset */
657 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
659 /* release GMAC reset */
660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662 if (hw->flags & SKY2_HW_NEWER_PHY) {
663 /* select page 2 to access MAC control register */
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
666 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
667 /* allow GMII Power Down */
668 ctrl &= ~PHY_M_MAC_GMIF_PUP;
669 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
671 /* set page register back to 0 */
672 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
675 /* setup General Purpose Control Register */
676 gma_write16(hw, port, GM_GP_CTRL,
677 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
678 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
681 if (hw->chip_id != CHIP_ID_YUKON_EC) {
682 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
683 /* select page 2 to access MAC control register */
684 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
686 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
687 /* enable Power Down */
688 ctrl |= PHY_M_PC_POW_D_ENA;
689 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
691 /* set page register back to 0 */
692 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
695 /* set IEEE compatible Power Down Mode (dev. #4.99) */
696 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
700 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
701 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
702 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
706 /* Force a renegotiation */
707 static void sky2_phy_reinit(struct sky2_port *sky2)
709 spin_lock_bh(&sky2->phy_lock);
710 sky2_phy_init(sky2->hw, sky2->port);
711 spin_unlock_bh(&sky2->phy_lock);
714 /* Put device in state to listen for Wake On Lan */
715 static void sky2_wol_init(struct sky2_port *sky2)
717 struct sky2_hw *hw = sky2->hw;
718 unsigned port = sky2->port;
719 enum flow_control save_mode;
723 /* Bring hardware out of reset */
724 sky2_write16(hw, B0_CTST, CS_RST_CLR);
725 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
728 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
731 * sky2_reset will re-enable on resume
733 save_mode = sky2->flow_mode;
734 ctrl = sky2->advertising;
736 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
737 sky2->flow_mode = FC_NONE;
739 spin_lock_bh(&sky2->phy_lock);
740 sky2_phy_power_up(hw, port);
741 sky2_phy_init(hw, port);
742 spin_unlock_bh(&sky2->phy_lock);
744 sky2->flow_mode = save_mode;
745 sky2->advertising = ctrl;
747 /* Set GMAC to no flow control and auto update for speed/duplex */
748 gma_write16(hw, port, GM_GP_CTRL,
749 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
750 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
752 /* Set WOL address */
753 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
754 sky2->netdev->dev_addr, ETH_ALEN);
756 /* Turn on appropriate WOL control bits */
757 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
759 if (sky2->wol & WAKE_PHY)
760 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
762 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
764 if (sky2->wol & WAKE_MAGIC)
765 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
767 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
769 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
772 /* Turn on legacy PCI-Express PME mode */
773 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
774 reg1 |= PCI_Y2_PME_LEGACY;
775 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
778 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
782 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
784 struct net_device *dev = hw->dev[port];
786 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
787 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
788 hw->chip_id == CHIP_ID_YUKON_FE_P ||
789 hw->chip_id == CHIP_ID_YUKON_SUPR) {
790 /* Yukon-Extreme B0 and further Extreme devices */
791 /* enable Store & Forward mode for TX */
793 if (dev->mtu <= ETH_DATA_LEN)
794 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
795 TX_JUMBO_DIS | TX_STFW_ENA);
798 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
799 TX_JUMBO_ENA| TX_STFW_ENA);
801 if (dev->mtu <= ETH_DATA_LEN)
802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
804 /* set Tx GMAC FIFO Almost Empty Threshold */
805 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
806 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
810 /* Can't do offload because of lack of store/forward */
811 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
816 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
818 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
822 const u8 *addr = hw->dev[port]->dev_addr;
824 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
825 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
829 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
830 /* WA DEV_472 -- looks like crossed wires on port 2 */
831 /* clear GMAC 1 Control reset */
832 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
834 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
835 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
836 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
837 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
838 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
841 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
843 /* Enable Transmit FIFO Underrun */
844 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
846 spin_lock_bh(&sky2->phy_lock);
847 sky2_phy_power_up(hw, port);
848 sky2_phy_init(hw, port);
849 spin_unlock_bh(&sky2->phy_lock);
852 reg = gma_read16(hw, port, GM_PHY_ADDR);
853 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
855 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
856 gma_read16(hw, port, i);
857 gma_write16(hw, port, GM_PHY_ADDR, reg);
859 /* transmit control */
860 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
862 /* receive control reg: unicast + multicast + no FCS */
863 gma_write16(hw, port, GM_RX_CTRL,
864 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
866 /* transmit flow control */
867 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
869 /* transmit parameter */
870 gma_write16(hw, port, GM_TX_PARAM,
871 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
872 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
873 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
874 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
876 /* serial mode register */
877 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
878 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
880 if (hw->dev[port]->mtu > ETH_DATA_LEN)
881 reg |= GM_SMOD_JUMBO_ENA;
883 gma_write16(hw, port, GM_SERIAL_MODE, reg);
885 /* virtual address for data */
886 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
888 /* physical address: used for pause frames */
889 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
891 /* ignore counter overflows */
892 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
893 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
896 /* Configure Rx MAC FIFO */
897 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
898 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
899 if (hw->chip_id == CHIP_ID_YUKON_EX ||
900 hw->chip_id == CHIP_ID_YUKON_FE_P)
901 rx_reg |= GMF_RX_OVER_ON;
903 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
905 if (hw->chip_id == CHIP_ID_YUKON_XL) {
906 /* Hardware errata - clear flush mask */
907 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
909 /* Flush Rx MAC FIFO on any flow control or error */
910 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
913 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
914 reg = RX_GMF_FL_THR_DEF + 1;
915 /* Another magic mystery workaround from sk98lin */
916 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
917 hw->chip_rev == CHIP_REV_YU_FE2_A0)
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
921 /* Configure Tx MAC FIFO */
922 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
923 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
925 /* On chips without ram buffer, pause is controled by MAC level */
926 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
927 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
928 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
930 sky2_set_tx_stfwd(hw, port);
933 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
934 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
935 /* disable dynamic watermark */
936 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
937 reg &= ~TX_DYN_WM_ENA;
938 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
942 /* Assign Ram Buffer allocation to queue */
943 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
947 /* convert from K bytes to qwords used for hw register */
950 end = start + space - 1;
952 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
953 sky2_write32(hw, RB_ADDR(q, RB_START), start);
954 sky2_write32(hw, RB_ADDR(q, RB_END), end);
955 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
956 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
958 if (q == Q_R1 || q == Q_R2) {
959 u32 tp = space - space/4;
961 /* On receive queue's set the thresholds
962 * give receiver priority when > 3/4 full
963 * send pause when down to 2K
965 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
966 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
969 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
970 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
972 /* Enable store & forward on Tx queue's because
973 * Tx FIFO is only 1K on Yukon
975 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
978 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
979 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
982 /* Setup Bus Memory Interface */
983 static void sky2_qset(struct sky2_hw *hw, u16 q)
985 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
986 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
988 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
991 /* Setup prefetch unit registers. This is the interface between
992 * hardware and driver list elements
994 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
995 dma_addr_t addr, u32 last)
997 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
998 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1001 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1004 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1007 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1009 struct sky2_tx_le *le = sky2->tx_le + *slot;
1010 struct tx_ring_info *re = sky2->tx_ring + *slot;
1012 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1019 static void tx_init(struct sky2_port *sky2)
1021 struct sky2_tx_le *le;
1023 sky2->tx_prod = sky2->tx_cons = 0;
1024 sky2->tx_tcpsum = 0;
1025 sky2->tx_last_mss = 0;
1027 le = get_tx_le(sky2, &sky2->tx_prod);
1029 le->opcode = OP_ADDR64 | HW_OWNER;
1030 sky2->tx_last_upper = 0;
1033 /* Update chip's next pointer */
1034 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1036 /* Make sure write' to descriptors are complete before we tell hardware */
1038 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1040 /* Synchronize I/O on since next processor may write to tail */
1045 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1047 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1048 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1053 /* Build description to hardware for one receive segment */
1054 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1055 dma_addr_t map, unsigned len)
1057 struct sky2_rx_le *le;
1059 if (sizeof(dma_addr_t) > sizeof(u32)) {
1060 le = sky2_next_rx(sky2);
1061 le->addr = cpu_to_le32(upper_32_bits(map));
1062 le->opcode = OP_ADDR64 | HW_OWNER;
1065 le = sky2_next_rx(sky2);
1066 le->addr = cpu_to_le32(lower_32_bits(map));
1067 le->length = cpu_to_le16(len);
1068 le->opcode = op | HW_OWNER;
1071 /* Build description to hardware for one possibly fragmented skb */
1072 static void sky2_rx_submit(struct sky2_port *sky2,
1073 const struct rx_ring_info *re)
1077 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1079 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1080 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1084 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1087 struct sk_buff *skb = re->skb;
1090 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1091 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1094 pci_unmap_len_set(re, data_size, size);
1096 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1097 re->frag_addr[i] = pci_map_page(pdev,
1098 skb_shinfo(skb)->frags[i].page,
1099 skb_shinfo(skb)->frags[i].page_offset,
1100 skb_shinfo(skb)->frags[i].size,
1101 PCI_DMA_FROMDEVICE);
1105 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1107 struct sk_buff *skb = re->skb;
1110 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1111 PCI_DMA_FROMDEVICE);
1113 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1114 pci_unmap_page(pdev, re->frag_addr[i],
1115 skb_shinfo(skb)->frags[i].size,
1116 PCI_DMA_FROMDEVICE);
1119 /* Tell chip where to start receive checksum.
1120 * Actually has two checksums, but set both same to avoid possible byte
1123 static void rx_set_checksum(struct sky2_port *sky2)
1125 struct sky2_rx_le *le = sky2_next_rx(sky2);
1127 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1129 le->opcode = OP_TCPSTART | HW_OWNER;
1131 sky2_write32(sky2->hw,
1132 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1133 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1134 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1138 * The RX Stop command will not work for Yukon-2 if the BMU does not
1139 * reach the end of packet and since we can't make sure that we have
1140 * incoming data, we must reset the BMU while it is not doing a DMA
1141 * transfer. Since it is possible that the RX path is still active,
1142 * the RX RAM buffer will be stopped first, so any possible incoming
1143 * data will not trigger a DMA. After the RAM buffer is stopped, the
1144 * BMU is polled until any DMA in progress is ended and only then it
1147 static void sky2_rx_stop(struct sky2_port *sky2)
1149 struct sky2_hw *hw = sky2->hw;
1150 unsigned rxq = rxqaddr[sky2->port];
1153 /* disable the RAM Buffer receive queue */
1154 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1156 for (i = 0; i < 0xffff; i++)
1157 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1158 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1161 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1162 sky2->netdev->name);
1164 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1166 /* reset the Rx prefetch unit */
1167 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1171 /* Clean out receive buffer area, assumes receiver hardware stopped */
1172 static void sky2_rx_clean(struct sky2_port *sky2)
1176 memset(sky2->rx_le, 0, RX_LE_BYTES);
1177 for (i = 0; i < sky2->rx_pending; i++) {
1178 struct rx_ring_info *re = sky2->rx_ring + i;
1181 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1188 /* Basic MII support */
1189 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1191 struct mii_ioctl_data *data = if_mii(ifr);
1192 struct sky2_port *sky2 = netdev_priv(dev);
1193 struct sky2_hw *hw = sky2->hw;
1194 int err = -EOPNOTSUPP;
1196 if (!netif_running(dev))
1197 return -ENODEV; /* Phy still in reset */
1201 data->phy_id = PHY_ADDR_MARV;
1207 spin_lock_bh(&sky2->phy_lock);
1208 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1209 spin_unlock_bh(&sky2->phy_lock);
1211 data->val_out = val;
1216 if (!capable(CAP_NET_ADMIN))
1219 spin_lock_bh(&sky2->phy_lock);
1220 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1222 spin_unlock_bh(&sky2->phy_lock);
1228 #ifdef SKY2_VLAN_TAG_USED
1229 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1232 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1234 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1237 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1239 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1244 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 u16 port = sky2->port;
1250 netif_tx_lock_bh(dev);
1251 napi_disable(&hw->napi);
1254 sky2_set_vlan_mode(hw, port, grp != NULL);
1256 sky2_read32(hw, B0_Y2_SP_LISR);
1257 napi_enable(&hw->napi);
1258 netif_tx_unlock_bh(dev);
1262 /* Amount of required worst case padding in rx buffer */
1263 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1265 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1269 * Allocate an skb for receiving. If the MTU is large enough
1270 * make the skb non-linear with a fragment list of pages.
1272 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1274 struct sk_buff *skb;
1277 skb = netdev_alloc_skb(sky2->netdev,
1278 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1282 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1283 unsigned char *start;
1285 * Workaround for a bug in FIFO that cause hang
1286 * if the FIFO if the receive buffer is not 64 byte aligned.
1287 * The buffer returned from netdev_alloc_skb is
1288 * aligned except if slab debugging is enabled.
1290 start = PTR_ALIGN(skb->data, 8);
1291 skb_reserve(skb, start - skb->data);
1293 skb_reserve(skb, NET_IP_ALIGN);
1295 for (i = 0; i < sky2->rx_nfrags; i++) {
1296 struct page *page = alloc_page(GFP_ATOMIC);
1300 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1310 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1312 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1316 * Allocate and setup receiver buffer pool.
1317 * Normal case this ends up creating one list element for skb
1318 * in the receive ring. Worst case if using large MTU and each
1319 * allocation falls on a different 64 bit region, that results
1320 * in 6 list elements per ring entry.
1321 * One element is used for checksum enable/disable, and one
1322 * extra to avoid wrap.
1324 static int sky2_rx_start(struct sky2_port *sky2)
1326 struct sky2_hw *hw = sky2->hw;
1327 struct rx_ring_info *re;
1328 unsigned rxq = rxqaddr[sky2->port];
1329 unsigned i, size, thresh;
1331 sky2->rx_put = sky2->rx_next = 0;
1334 /* On PCI express lowering the watermark gives better performance */
1335 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1336 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1338 /* These chips have no ram buffer?
1339 * MAC Rx RAM Read is controlled by hardware */
1340 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1341 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1342 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1343 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1345 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1347 if (!(hw->flags & SKY2_HW_NEW_LE))
1348 rx_set_checksum(sky2);
1350 /* Space needed for frame data + headers rounded up */
1351 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1353 /* Stopping point for hardware truncation */
1354 thresh = (size - 8) / sizeof(u32);
1356 sky2->rx_nfrags = size >> PAGE_SHIFT;
1357 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1359 /* Compute residue after pages */
1360 size -= sky2->rx_nfrags << PAGE_SHIFT;
1362 /* Optimize to handle small packets and headers */
1363 if (size < copybreak)
1365 if (size < ETH_HLEN)
1368 sky2->rx_data_size = size;
1371 for (i = 0; i < sky2->rx_pending; i++) {
1372 re = sky2->rx_ring + i;
1374 re->skb = sky2_rx_alloc(sky2);
1378 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1379 dev_kfree_skb(re->skb);
1384 sky2_rx_submit(sky2, re);
1388 * The receiver hangs if it receives frames larger than the
1389 * packet buffer. As a workaround, truncate oversize frames, but
1390 * the register is limited to 9 bits, so if you do frames > 2052
1391 * you better get the MTU right!
1394 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1396 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1397 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1400 /* Tell chip about available buffers */
1401 sky2_rx_update(sky2, rxq);
1404 sky2_rx_clean(sky2);
1408 /* Bring up network interface. */
1409 static int sky2_up(struct net_device *dev)
1411 struct sky2_port *sky2 = netdev_priv(dev);
1412 struct sky2_hw *hw = sky2->hw;
1413 unsigned port = sky2->port;
1415 int cap, err = -ENOMEM;
1416 struct net_device *otherdev = hw->dev[sky2->port^1];
1419 * On dual port PCI-X card, there is an problem where status
1420 * can be received out of order due to split transactions
1422 if (otherdev && netif_running(otherdev) &&
1423 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1426 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1427 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1428 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1432 netif_carrier_off(dev);
1434 /* must be power of 2 */
1435 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1436 sky2->tx_ring_size *
1437 sizeof(struct sky2_tx_le),
1442 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1449 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1453 memset(sky2->rx_le, 0, RX_LE_BYTES);
1455 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1460 sky2_mac_init(hw, port);
1462 /* Register is number of 4K blocks on internal RAM buffer. */
1463 ramsize = sky2_read8(hw, B2_E_0) * 4;
1467 hw->flags |= SKY2_HW_RAM_BUFFER;
1468 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1470 rxspace = ramsize / 2;
1472 rxspace = 8 + (2*(ramsize - 16))/3;
1474 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1475 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1477 /* Make sure SyncQ is disabled */
1478 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1482 sky2_qset(hw, txqaddr[port]);
1484 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1485 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1486 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1488 /* Set almost empty threshold */
1489 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1490 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1491 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1493 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1494 sky2->tx_ring_size - 1);
1496 #ifdef SKY2_VLAN_TAG_USED
1497 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1500 err = sky2_rx_start(sky2);
1504 /* Enable interrupts from phy/mac for port */
1505 imask = sky2_read32(hw, B0_IMSK);
1506 imask |= portirq_msk[port];
1507 sky2_write32(hw, B0_IMSK, imask);
1508 sky2_read32(hw, B0_IMSK);
1510 if (netif_msg_ifup(sky2))
1511 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1517 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1518 sky2->rx_le, sky2->rx_le_map);
1522 pci_free_consistent(hw->pdev,
1523 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1524 sky2->tx_le, sky2->tx_le_map);
1527 kfree(sky2->tx_ring);
1528 kfree(sky2->rx_ring);
1530 sky2->tx_ring = NULL;
1531 sky2->rx_ring = NULL;
1535 /* Modular subtraction in ring */
1536 static inline int tx_inuse(const struct sky2_port *sky2)
1538 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1541 /* Number of list elements available for next tx */
1542 static inline int tx_avail(const struct sky2_port *sky2)
1544 return sky2->tx_pending - tx_inuse(sky2);
1547 /* Estimate of number of transmit list elements required */
1548 static unsigned tx_le_req(const struct sk_buff *skb)
1552 count = sizeof(dma_addr_t) / sizeof(u32);
1553 count += skb_shinfo(skb)->nr_frags * count;
1555 if (skb_is_gso(skb))
1558 if (skb->ip_summed == CHECKSUM_PARTIAL)
1564 static void sky2_tx_unmap(struct pci_dev *pdev,
1565 const struct tx_ring_info *re)
1567 if (re->flags & TX_MAP_SINGLE)
1568 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1569 pci_unmap_len(re, maplen),
1571 else if (re->flags & TX_MAP_PAGE)
1572 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1573 pci_unmap_len(re, maplen),
1578 * Put one packet in ring for transmit.
1579 * A single packet can generate multiple list elements, and
1580 * the number of ring elements will probably be less than the number
1581 * of list elements used.
1583 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1584 struct net_device *dev)
1586 struct sky2_port *sky2 = netdev_priv(dev);
1587 struct sky2_hw *hw = sky2->hw;
1588 struct sky2_tx_le *le = NULL;
1589 struct tx_ring_info *re;
1597 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1598 return NETDEV_TX_BUSY;
1600 len = skb_headlen(skb);
1601 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1603 if (pci_dma_mapping_error(hw->pdev, mapping))
1606 slot = sky2->tx_prod;
1607 if (unlikely(netif_msg_tx_queued(sky2)))
1608 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1609 dev->name, slot, skb->len);
1611 /* Send high bits if needed */
1612 upper = upper_32_bits(mapping);
1613 if (upper != sky2->tx_last_upper) {
1614 le = get_tx_le(sky2, &slot);
1615 le->addr = cpu_to_le32(upper);
1616 sky2->tx_last_upper = upper;
1617 le->opcode = OP_ADDR64 | HW_OWNER;
1620 /* Check for TCP Segmentation Offload */
1621 mss = skb_shinfo(skb)->gso_size;
1624 if (!(hw->flags & SKY2_HW_NEW_LE))
1625 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1627 if (mss != sky2->tx_last_mss) {
1628 le = get_tx_le(sky2, &slot);
1629 le->addr = cpu_to_le32(mss);
1631 if (hw->flags & SKY2_HW_NEW_LE)
1632 le->opcode = OP_MSS | HW_OWNER;
1634 le->opcode = OP_LRGLEN | HW_OWNER;
1635 sky2->tx_last_mss = mss;
1640 #ifdef SKY2_VLAN_TAG_USED
1641 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1642 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1644 le = get_tx_le(sky2, &slot);
1646 le->opcode = OP_VLAN|HW_OWNER;
1648 le->opcode |= OP_VLAN;
1649 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1654 /* Handle TCP checksum offload */
1655 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1656 /* On Yukon EX (some versions) encoding change. */
1657 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1658 ctrl |= CALSUM; /* auto checksum */
1660 const unsigned offset = skb_transport_offset(skb);
1663 tcpsum = offset << 16; /* sum start */
1664 tcpsum |= offset + skb->csum_offset; /* sum write */
1666 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1667 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1670 if (tcpsum != sky2->tx_tcpsum) {
1671 sky2->tx_tcpsum = tcpsum;
1673 le = get_tx_le(sky2, &slot);
1674 le->addr = cpu_to_le32(tcpsum);
1675 le->length = 0; /* initial checksum value */
1676 le->ctrl = 1; /* one packet */
1677 le->opcode = OP_TCPLISW | HW_OWNER;
1682 re = sky2->tx_ring + slot;
1683 re->flags = TX_MAP_SINGLE;
1684 pci_unmap_addr_set(re, mapaddr, mapping);
1685 pci_unmap_len_set(re, maplen, len);
1687 le = get_tx_le(sky2, &slot);
1688 le->addr = cpu_to_le32(lower_32_bits(mapping));
1689 le->length = cpu_to_le16(len);
1691 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1694 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1695 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1697 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1698 frag->size, PCI_DMA_TODEVICE);
1700 if (pci_dma_mapping_error(hw->pdev, mapping))
1701 goto mapping_unwind;
1703 upper = upper_32_bits(mapping);
1704 if (upper != sky2->tx_last_upper) {
1705 le = get_tx_le(sky2, &slot);
1706 le->addr = cpu_to_le32(upper);
1707 sky2->tx_last_upper = upper;
1708 le->opcode = OP_ADDR64 | HW_OWNER;
1711 re = sky2->tx_ring + slot;
1712 re->flags = TX_MAP_PAGE;
1713 pci_unmap_addr_set(re, mapaddr, mapping);
1714 pci_unmap_len_set(re, maplen, frag->size);
1716 le = get_tx_le(sky2, &slot);
1717 le->addr = cpu_to_le32(lower_32_bits(mapping));
1718 le->length = cpu_to_le16(frag->size);
1720 le->opcode = OP_BUFFER | HW_OWNER;
1726 sky2->tx_prod = slot;
1728 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1729 netif_stop_queue(dev);
1731 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1733 return NETDEV_TX_OK;
1736 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1737 re = sky2->tx_ring + i;
1739 sky2_tx_unmap(hw->pdev, re);
1743 if (net_ratelimit())
1744 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1746 return NETDEV_TX_OK;
1750 * Free ring elements from starting at tx_cons until "done"
1753 * 1. The hardware will tell us about partial completion of multi-part
1754 * buffers so make sure not to free skb to early.
1755 * 2. This may run in parallel start_xmit because the it only
1756 * looks at the tail of the queue of FIFO (tx_cons), not
1757 * the head (tx_prod)
1759 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1761 struct net_device *dev = sky2->netdev;
1764 BUG_ON(done >= sky2->tx_ring_size);
1766 for (idx = sky2->tx_cons; idx != done;
1767 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1768 struct tx_ring_info *re = sky2->tx_ring + idx;
1769 struct sk_buff *skb = re->skb;
1771 sky2_tx_unmap(sky2->hw->pdev, re);
1774 if (unlikely(netif_msg_tx_done(sky2)))
1775 printk(KERN_DEBUG "%s: tx done %u\n",
1778 dev->stats.tx_packets++;
1779 dev->stats.tx_bytes += skb->len;
1781 dev_kfree_skb_any(skb);
1783 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1787 sky2->tx_cons = idx;
1790 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1791 netif_wake_queue(dev);
1794 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1796 /* Disable Force Sync bit and Enable Alloc bit */
1797 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1798 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1800 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1801 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1802 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1804 /* Reset the PCI FIFO of the async Tx queue */
1805 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1806 BMU_RST_SET | BMU_FIFO_RST);
1808 /* Reset the Tx prefetch units */
1809 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1812 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1813 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1816 /* Network shutdown */
1817 static int sky2_down(struct net_device *dev)
1819 struct sky2_port *sky2 = netdev_priv(dev);
1820 struct sky2_hw *hw = sky2->hw;
1821 unsigned port = sky2->port;
1825 /* Never really got started! */
1829 if (netif_msg_ifdown(sky2))
1830 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1832 /* Force flow control off */
1833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1835 /* Stop transmitter */
1836 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1837 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1839 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1840 RB_RST_SET | RB_DIS_OP_MD);
1842 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1843 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1844 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1846 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1848 /* Workaround shared GMAC reset */
1849 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1850 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1851 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1853 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1855 /* Force any delayed status interrrupt and NAPI */
1856 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1857 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1858 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1859 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1863 /* Disable port IRQ */
1864 imask = sky2_read32(hw, B0_IMSK);
1865 imask &= ~portirq_msk[port];
1866 sky2_write32(hw, B0_IMSK, imask);
1867 sky2_read32(hw, B0_IMSK);
1869 synchronize_irq(hw->pdev->irq);
1870 napi_synchronize(&hw->napi);
1872 spin_lock_bh(&sky2->phy_lock);
1873 sky2_phy_power_down(hw, port);
1874 spin_unlock_bh(&sky2->phy_lock);
1876 sky2_tx_reset(hw, port);
1878 /* Free any pending frames stuck in HW queue */
1879 sky2_tx_complete(sky2, sky2->tx_prod);
1881 sky2_rx_clean(sky2);
1883 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1884 sky2->rx_le, sky2->rx_le_map);
1885 kfree(sky2->rx_ring);
1887 pci_free_consistent(hw->pdev,
1888 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1889 sky2->tx_le, sky2->tx_le_map);
1890 kfree(sky2->tx_ring);
1895 sky2->rx_ring = NULL;
1896 sky2->tx_ring = NULL;
1901 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1903 if (hw->flags & SKY2_HW_FIBRE_PHY)
1906 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1907 if (aux & PHY_M_PS_SPEED_100)
1913 switch (aux & PHY_M_PS_SPEED_MSK) {
1914 case PHY_M_PS_SPEED_1000:
1916 case PHY_M_PS_SPEED_100:
1923 static void sky2_link_up(struct sky2_port *sky2)
1925 struct sky2_hw *hw = sky2->hw;
1926 unsigned port = sky2->port;
1928 static const char *fc_name[] = {
1936 reg = gma_read16(hw, port, GM_GP_CTRL);
1937 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1938 gma_write16(hw, port, GM_GP_CTRL, reg);
1940 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1942 netif_carrier_on(sky2->netdev);
1944 mod_timer(&hw->watchdog_timer, jiffies + 1);
1946 /* Turn on link LED */
1947 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1948 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1950 if (netif_msg_link(sky2))
1951 printk(KERN_INFO PFX
1952 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1953 sky2->netdev->name, sky2->speed,
1954 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1955 fc_name[sky2->flow_status]);
1958 static void sky2_link_down(struct sky2_port *sky2)
1960 struct sky2_hw *hw = sky2->hw;
1961 unsigned port = sky2->port;
1964 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1966 reg = gma_read16(hw, port, GM_GP_CTRL);
1967 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1968 gma_write16(hw, port, GM_GP_CTRL, reg);
1970 netif_carrier_off(sky2->netdev);
1972 /* Turn on link LED */
1973 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1975 if (netif_msg_link(sky2))
1976 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1978 sky2_phy_init(hw, port);
1981 static enum flow_control sky2_flow(int rx, int tx)
1984 return tx ? FC_BOTH : FC_RX;
1986 return tx ? FC_TX : FC_NONE;
1989 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1991 struct sky2_hw *hw = sky2->hw;
1992 unsigned port = sky2->port;
1995 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1996 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1997 if (lpa & PHY_M_AN_RF) {
1998 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2002 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2003 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2004 sky2->netdev->name);
2008 sky2->speed = sky2_phy_speed(hw, aux);
2009 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2011 /* Since the pause result bits seem to in different positions on
2012 * different chips. look at registers.
2014 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2015 /* Shift for bits in fiber PHY */
2016 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2017 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2019 if (advert & ADVERTISE_1000XPAUSE)
2020 advert |= ADVERTISE_PAUSE_CAP;
2021 if (advert & ADVERTISE_1000XPSE_ASYM)
2022 advert |= ADVERTISE_PAUSE_ASYM;
2023 if (lpa & LPA_1000XPAUSE)
2024 lpa |= LPA_PAUSE_CAP;
2025 if (lpa & LPA_1000XPAUSE_ASYM)
2026 lpa |= LPA_PAUSE_ASYM;
2029 sky2->flow_status = FC_NONE;
2030 if (advert & ADVERTISE_PAUSE_CAP) {
2031 if (lpa & LPA_PAUSE_CAP)
2032 sky2->flow_status = FC_BOTH;
2033 else if (advert & ADVERTISE_PAUSE_ASYM)
2034 sky2->flow_status = FC_RX;
2035 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2036 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2037 sky2->flow_status = FC_TX;
2040 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2041 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2042 sky2->flow_status = FC_NONE;
2044 if (sky2->flow_status & FC_TX)
2045 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2047 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2052 /* Interrupt from PHY */
2053 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2055 struct net_device *dev = hw->dev[port];
2056 struct sky2_port *sky2 = netdev_priv(dev);
2057 u16 istatus, phystat;
2059 if (!netif_running(dev))
2062 spin_lock(&sky2->phy_lock);
2063 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2064 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2066 if (netif_msg_intr(sky2))
2067 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2068 sky2->netdev->name, istatus, phystat);
2070 if (istatus & PHY_M_IS_AN_COMPL) {
2071 if (sky2_autoneg_done(sky2, phystat) == 0)
2076 if (istatus & PHY_M_IS_LSP_CHANGE)
2077 sky2->speed = sky2_phy_speed(hw, phystat);
2079 if (istatus & PHY_M_IS_DUP_CHANGE)
2081 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2083 if (istatus & PHY_M_IS_LST_CHANGE) {
2084 if (phystat & PHY_M_PS_LINK_UP)
2087 sky2_link_down(sky2);
2090 spin_unlock(&sky2->phy_lock);
2093 /* Transmit timeout is only called if we are running, carrier is up
2094 * and tx queue is full (stopped).
2096 static void sky2_tx_timeout(struct net_device *dev)
2098 struct sky2_port *sky2 = netdev_priv(dev);
2099 struct sky2_hw *hw = sky2->hw;
2101 if (netif_msg_timer(sky2))
2102 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2104 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2105 dev->name, sky2->tx_cons, sky2->tx_prod,
2106 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2107 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2109 /* can't restart safely under softirq */
2110 schedule_work(&hw->restart_work);
2113 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2115 struct sky2_port *sky2 = netdev_priv(dev);
2116 struct sky2_hw *hw = sky2->hw;
2117 unsigned port = sky2->port;
2122 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2125 if (new_mtu > ETH_DATA_LEN &&
2126 (hw->chip_id == CHIP_ID_YUKON_FE ||
2127 hw->chip_id == CHIP_ID_YUKON_FE_P))
2130 if (!netif_running(dev)) {
2135 imask = sky2_read32(hw, B0_IMSK);
2136 sky2_write32(hw, B0_IMSK, 0);
2138 dev->trans_start = jiffies; /* prevent tx timeout */
2139 netif_stop_queue(dev);
2140 napi_disable(&hw->napi);
2142 synchronize_irq(hw->pdev->irq);
2144 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2145 sky2_set_tx_stfwd(hw, port);
2147 ctl = gma_read16(hw, port, GM_GP_CTRL);
2148 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2150 sky2_rx_clean(sky2);
2154 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2155 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2157 if (dev->mtu > ETH_DATA_LEN)
2158 mode |= GM_SMOD_JUMBO_ENA;
2160 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2162 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2164 err = sky2_rx_start(sky2);
2165 sky2_write32(hw, B0_IMSK, imask);
2167 sky2_read32(hw, B0_Y2_SP_LISR);
2168 napi_enable(&hw->napi);
2173 gma_write16(hw, port, GM_GP_CTRL, ctl);
2175 netif_wake_queue(dev);
2181 /* For small just reuse existing skb for next receive */
2182 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2183 const struct rx_ring_info *re,
2186 struct sk_buff *skb;
2188 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2190 skb_reserve(skb, 2);
2191 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2192 length, PCI_DMA_FROMDEVICE);
2193 skb_copy_from_linear_data(re->skb, skb->data, length);
2194 skb->ip_summed = re->skb->ip_summed;
2195 skb->csum = re->skb->csum;
2196 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2197 length, PCI_DMA_FROMDEVICE);
2198 re->skb->ip_summed = CHECKSUM_NONE;
2199 skb_put(skb, length);
2204 /* Adjust length of skb with fragments to match received data */
2205 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2206 unsigned int length)
2211 /* put header into skb */
2212 size = min(length, hdr_space);
2217 num_frags = skb_shinfo(skb)->nr_frags;
2218 for (i = 0; i < num_frags; i++) {
2219 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2222 /* don't need this page */
2223 __free_page(frag->page);
2224 --skb_shinfo(skb)->nr_frags;
2226 size = min(length, (unsigned) PAGE_SIZE);
2229 skb->data_len += size;
2230 skb->truesize += size;
2237 /* Normal packet - take skb from ring element and put in a new one */
2238 static struct sk_buff *receive_new(struct sky2_port *sky2,
2239 struct rx_ring_info *re,
2240 unsigned int length)
2242 struct sk_buff *skb, *nskb;
2243 unsigned hdr_space = sky2->rx_data_size;
2245 /* Don't be tricky about reusing pages (yet) */
2246 nskb = sky2_rx_alloc(sky2);
2247 if (unlikely(!nskb))
2251 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2253 prefetch(skb->data);
2255 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2256 dev_kfree_skb(nskb);
2261 if (skb_shinfo(skb)->nr_frags)
2262 skb_put_frags(skb, hdr_space, length);
2264 skb_put(skb, length);
2269 * Receive one packet.
2270 * For larger packets, get new buffer.
2272 static struct sk_buff *sky2_receive(struct net_device *dev,
2273 u16 length, u32 status)
2275 struct sky2_port *sky2 = netdev_priv(dev);
2276 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2277 struct sk_buff *skb = NULL;
2278 u16 count = (status & GMR_FS_LEN) >> 16;
2280 #ifdef SKY2_VLAN_TAG_USED
2281 /* Account for vlan tag */
2282 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2286 if (unlikely(netif_msg_rx_status(sky2)))
2287 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2288 dev->name, sky2->rx_next, status, length);
2290 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2291 prefetch(sky2->rx_ring + sky2->rx_next);
2293 /* This chip has hardware problems that generates bogus status.
2294 * So do only marginal checking and expect higher level protocols
2295 * to handle crap frames.
2297 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2298 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2302 if (status & GMR_FS_ANY_ERR)
2305 if (!(status & GMR_FS_RX_OK))
2308 /* if length reported by DMA does not match PHY, packet was truncated */
2309 if (length != count)
2313 if (length < copybreak)
2314 skb = receive_copy(sky2, re, length);
2316 skb = receive_new(sky2, re, length);
2318 sky2_rx_submit(sky2, re);
2323 /* Truncation of overlength packets
2324 causes PHY length to not match MAC length */
2325 ++dev->stats.rx_length_errors;
2326 if (netif_msg_rx_err(sky2) && net_ratelimit())
2327 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2328 dev->name, status, length);
2332 ++dev->stats.rx_errors;
2333 if (status & GMR_FS_RX_FF_OV) {
2334 dev->stats.rx_over_errors++;
2338 if (netif_msg_rx_err(sky2) && net_ratelimit())
2339 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2340 dev->name, status, length);
2342 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2343 dev->stats.rx_length_errors++;
2344 if (status & GMR_FS_FRAGMENT)
2345 dev->stats.rx_frame_errors++;
2346 if (status & GMR_FS_CRC_ERR)
2347 dev->stats.rx_crc_errors++;
2352 /* Transmit complete */
2353 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2355 struct sky2_port *sky2 = netdev_priv(dev);
2357 if (netif_running(dev))
2358 sky2_tx_complete(sky2, last);
2361 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2362 u32 status, struct sk_buff *skb)
2364 #ifdef SKY2_VLAN_TAG_USED
2365 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2366 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2367 if (skb->ip_summed == CHECKSUM_NONE)
2368 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2370 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2375 if (skb->ip_summed == CHECKSUM_NONE)
2376 netif_receive_skb(skb);
2378 napi_gro_receive(&sky2->hw->napi, skb);
2381 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2382 unsigned packets, unsigned bytes)
2385 struct net_device *dev = hw->dev[port];
2387 dev->stats.rx_packets += packets;
2388 dev->stats.rx_bytes += bytes;
2389 dev->last_rx = jiffies;
2390 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2394 /* Process status response ring */
2395 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2398 unsigned int total_bytes[2] = { 0 };
2399 unsigned int total_packets[2] = { 0 };
2403 struct sky2_port *sky2;
2404 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2406 struct net_device *dev;
2407 struct sk_buff *skb;
2410 u8 opcode = le->opcode;
2412 if (!(opcode & HW_OWNER))
2415 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2417 port = le->css & CSS_LINK_BIT;
2418 dev = hw->dev[port];
2419 sky2 = netdev_priv(dev);
2420 length = le16_to_cpu(le->length);
2421 status = le32_to_cpu(le->status);
2424 switch (opcode & ~HW_OWNER) {
2426 total_packets[port]++;
2427 total_bytes[port] += length;
2428 skb = sky2_receive(dev, length, status);
2429 if (unlikely(!skb)) {
2430 dev->stats.rx_dropped++;
2434 /* This chip reports checksum status differently */
2435 if (hw->flags & SKY2_HW_NEW_LE) {
2436 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2437 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2438 (le->css & CSS_TCPUDPCSOK))
2439 skb->ip_summed = CHECKSUM_UNNECESSARY;
2441 skb->ip_summed = CHECKSUM_NONE;
2444 skb->protocol = eth_type_trans(skb, dev);
2446 sky2_skb_rx(sky2, status, skb);
2448 /* Stop after net poll weight */
2449 if (++work_done >= to_do)
2453 #ifdef SKY2_VLAN_TAG_USED
2455 sky2->rx_tag = length;
2459 sky2->rx_tag = length;
2463 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2466 /* If this happens then driver assuming wrong format */
2467 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2468 if (net_ratelimit())
2469 printk(KERN_NOTICE "%s: unexpected"
2470 " checksum status\n",
2475 /* Both checksum counters are programmed to start at
2476 * the same offset, so unless there is a problem they
2477 * should match. This failure is an early indication that
2478 * hardware receive checksumming won't work.
2480 if (likely(status >> 16 == (status & 0xffff))) {
2481 skb = sky2->rx_ring[sky2->rx_next].skb;
2482 skb->ip_summed = CHECKSUM_COMPLETE;
2483 skb->csum = le16_to_cpu(status);
2485 printk(KERN_NOTICE PFX "%s: hardware receive "
2486 "checksum problem (status = %#x)\n",
2488 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2490 sky2_write32(sky2->hw,
2491 Q_ADDR(rxqaddr[port], Q_CSR),
2497 /* TX index reports status for both ports */
2498 sky2_tx_done(hw->dev[0], status & 0xfff);
2500 sky2_tx_done(hw->dev[1],
2501 ((status >> 24) & 0xff)
2502 | (u16)(length & 0xf) << 8);
2506 if (net_ratelimit())
2507 printk(KERN_WARNING PFX
2508 "unknown status opcode 0x%x\n", opcode);
2510 } while (hw->st_idx != idx);
2512 /* Fully processed status ring so clear irq */
2513 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2516 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2517 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2522 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2524 struct net_device *dev = hw->dev[port];
2526 if (net_ratelimit())
2527 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2530 if (status & Y2_IS_PAR_RD1) {
2531 if (net_ratelimit())
2532 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2535 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2538 if (status & Y2_IS_PAR_WR1) {
2539 if (net_ratelimit())
2540 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2543 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2546 if (status & Y2_IS_PAR_MAC1) {
2547 if (net_ratelimit())
2548 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2549 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2552 if (status & Y2_IS_PAR_RX1) {
2553 if (net_ratelimit())
2554 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2555 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2558 if (status & Y2_IS_TCP_TXA1) {
2559 if (net_ratelimit())
2560 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2562 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2566 static void sky2_hw_intr(struct sky2_hw *hw)
2568 struct pci_dev *pdev = hw->pdev;
2569 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2570 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2574 if (status & Y2_IS_TIST_OV)
2575 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2577 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2580 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2581 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2582 if (net_ratelimit())
2583 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2586 sky2_pci_write16(hw, PCI_STATUS,
2587 pci_err | PCI_STATUS_ERROR_BITS);
2588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2591 if (status & Y2_IS_PCI_EXP) {
2592 /* PCI-Express uncorrectable Error occurred */
2595 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2596 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2597 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2599 if (net_ratelimit())
2600 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2602 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2606 if (status & Y2_HWE_L1_MASK)
2607 sky2_hw_error(hw, 0, status);
2609 if (status & Y2_HWE_L1_MASK)
2610 sky2_hw_error(hw, 1, status);
2613 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2615 struct net_device *dev = hw->dev[port];
2616 struct sky2_port *sky2 = netdev_priv(dev);
2617 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2619 if (netif_msg_intr(sky2))
2620 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2623 if (status & GM_IS_RX_CO_OV)
2624 gma_read16(hw, port, GM_RX_IRQ_SRC);
2626 if (status & GM_IS_TX_CO_OV)
2627 gma_read16(hw, port, GM_TX_IRQ_SRC);
2629 if (status & GM_IS_RX_FF_OR) {
2630 ++dev->stats.rx_fifo_errors;
2631 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2634 if (status & GM_IS_TX_FF_UR) {
2635 ++dev->stats.tx_fifo_errors;
2636 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2640 /* This should never happen it is a bug. */
2641 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2643 struct net_device *dev = hw->dev[port];
2644 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2646 dev_err(&hw->pdev->dev, PFX
2647 "%s: descriptor error q=%#x get=%u put=%u\n",
2648 dev->name, (unsigned) q, (unsigned) idx,
2649 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2651 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2654 static int sky2_rx_hung(struct net_device *dev)
2656 struct sky2_port *sky2 = netdev_priv(dev);
2657 struct sky2_hw *hw = sky2->hw;
2658 unsigned port = sky2->port;
2659 unsigned rxq = rxqaddr[port];
2660 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2661 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2662 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2663 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2665 /* If idle and MAC or PCI is stuck */
2666 if (sky2->check.last == dev->last_rx &&
2667 ((mac_rp == sky2->check.mac_rp &&
2668 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2669 /* Check if the PCI RX hang */
2670 (fifo_rp == sky2->check.fifo_rp &&
2671 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2672 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2673 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2674 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2677 sky2->check.last = dev->last_rx;
2678 sky2->check.mac_rp = mac_rp;
2679 sky2->check.mac_lev = mac_lev;
2680 sky2->check.fifo_rp = fifo_rp;
2681 sky2->check.fifo_lev = fifo_lev;
2686 static void sky2_watchdog(unsigned long arg)
2688 struct sky2_hw *hw = (struct sky2_hw *) arg;
2690 /* Check for lost IRQ once a second */
2691 if (sky2_read32(hw, B0_ISRC)) {
2692 napi_schedule(&hw->napi);
2696 for (i = 0; i < hw->ports; i++) {
2697 struct net_device *dev = hw->dev[i];
2698 if (!netif_running(dev))
2702 /* For chips with Rx FIFO, check if stuck */
2703 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2704 sky2_rx_hung(dev)) {
2705 pr_info(PFX "%s: receiver hang detected\n",
2707 schedule_work(&hw->restart_work);
2716 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2719 /* Hardware/software error handling */
2720 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2722 if (net_ratelimit())
2723 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2725 if (status & Y2_IS_HW_ERR)
2728 if (status & Y2_IS_IRQ_MAC1)
2729 sky2_mac_intr(hw, 0);
2731 if (status & Y2_IS_IRQ_MAC2)
2732 sky2_mac_intr(hw, 1);
2734 if (status & Y2_IS_CHK_RX1)
2735 sky2_le_error(hw, 0, Q_R1);
2737 if (status & Y2_IS_CHK_RX2)
2738 sky2_le_error(hw, 1, Q_R2);
2740 if (status & Y2_IS_CHK_TXA1)
2741 sky2_le_error(hw, 0, Q_XA1);
2743 if (status & Y2_IS_CHK_TXA2)
2744 sky2_le_error(hw, 1, Q_XA2);
2747 static int sky2_poll(struct napi_struct *napi, int work_limit)
2749 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2750 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2754 if (unlikely(status & Y2_IS_ERROR))
2755 sky2_err_intr(hw, status);
2757 if (status & Y2_IS_IRQ_PHY1)
2758 sky2_phy_intr(hw, 0);
2760 if (status & Y2_IS_IRQ_PHY2)
2761 sky2_phy_intr(hw, 1);
2763 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2764 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2766 if (work_done >= work_limit)
2770 napi_complete(napi);
2771 sky2_read32(hw, B0_Y2_SP_LISR);
2777 static irqreturn_t sky2_intr(int irq, void *dev_id)
2779 struct sky2_hw *hw = dev_id;
2782 /* Reading this mask interrupts as side effect */
2783 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2784 if (status == 0 || status == ~0)
2787 prefetch(&hw->st_le[hw->st_idx]);
2789 napi_schedule(&hw->napi);
2794 #ifdef CONFIG_NET_POLL_CONTROLLER
2795 static void sky2_netpoll(struct net_device *dev)
2797 struct sky2_port *sky2 = netdev_priv(dev);
2799 napi_schedule(&sky2->hw->napi);
2803 /* Chip internal frequency for clock calculations */
2804 static u32 sky2_mhz(const struct sky2_hw *hw)
2806 switch (hw->chip_id) {
2807 case CHIP_ID_YUKON_EC:
2808 case CHIP_ID_YUKON_EC_U:
2809 case CHIP_ID_YUKON_EX:
2810 case CHIP_ID_YUKON_SUPR:
2811 case CHIP_ID_YUKON_UL_2:
2814 case CHIP_ID_YUKON_FE:
2817 case CHIP_ID_YUKON_FE_P:
2820 case CHIP_ID_YUKON_XL:
2828 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2830 return sky2_mhz(hw) * us;
2833 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2835 return clk / sky2_mhz(hw);
2839 static int __devinit sky2_init(struct sky2_hw *hw)
2843 /* Enable all clocks and check for bad PCI access */
2844 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2846 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2848 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2849 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2851 switch(hw->chip_id) {
2852 case CHIP_ID_YUKON_XL:
2853 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2856 case CHIP_ID_YUKON_EC_U:
2857 hw->flags = SKY2_HW_GIGABIT
2859 | SKY2_HW_ADV_POWER_CTL;
2862 case CHIP_ID_YUKON_EX:
2863 hw->flags = SKY2_HW_GIGABIT
2866 | SKY2_HW_ADV_POWER_CTL;
2868 /* New transmit checksum */
2869 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2870 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2873 case CHIP_ID_YUKON_EC:
2874 /* This rev is really old, and requires untested workarounds */
2875 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2876 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2879 hw->flags = SKY2_HW_GIGABIT;
2882 case CHIP_ID_YUKON_FE:
2885 case CHIP_ID_YUKON_FE_P:
2886 hw->flags = SKY2_HW_NEWER_PHY
2888 | SKY2_HW_AUTO_TX_SUM
2889 | SKY2_HW_ADV_POWER_CTL;
2892 case CHIP_ID_YUKON_SUPR:
2893 hw->flags = SKY2_HW_GIGABIT
2896 | SKY2_HW_AUTO_TX_SUM
2897 | SKY2_HW_ADV_POWER_CTL;
2900 case CHIP_ID_YUKON_UL_2:
2901 hw->flags = SKY2_HW_GIGABIT
2902 | SKY2_HW_ADV_POWER_CTL;
2906 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2911 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2912 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2913 hw->flags |= SKY2_HW_FIBRE_PHY;
2916 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2917 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2918 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2925 static void sky2_reset(struct sky2_hw *hw)
2927 struct pci_dev *pdev = hw->pdev;
2930 u32 hwe_mask = Y2_HWE_ALL_MASK;
2933 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2934 status = sky2_read16(hw, HCU_CCSR);
2935 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2936 HCU_CCSR_UC_STATE_MSK);
2937 sky2_write16(hw, HCU_CCSR, status);
2939 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2940 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2943 sky2_write8(hw, B0_CTST, CS_RST_SET);
2944 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2946 /* allow writes to PCI config */
2947 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2949 /* clear PCI errors, if any */
2950 status = sky2_pci_read16(hw, PCI_STATUS);
2951 status |= PCI_STATUS_ERROR_BITS;
2952 sky2_pci_write16(hw, PCI_STATUS, status);
2954 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2956 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2958 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2961 /* If error bit is stuck on ignore it */
2962 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2963 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2965 hwe_mask |= Y2_IS_PCI_EXP;
2969 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2971 for (i = 0; i < hw->ports; i++) {
2972 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2973 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2975 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2976 hw->chip_id == CHIP_ID_YUKON_SUPR)
2977 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2978 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2982 /* Clear I2C IRQ noise */
2983 sky2_write32(hw, B2_I2C_IRQ, 1);
2985 /* turn off hardware timer (unused) */
2986 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2987 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2989 /* Turn off descriptor polling */
2990 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2992 /* Turn off receive timestamp */
2993 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2994 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2996 /* enable the Tx Arbiters */
2997 for (i = 0; i < hw->ports; i++)
2998 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3000 /* Initialize ram interface */
3001 for (i = 0; i < hw->ports; i++) {
3002 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3004 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3005 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3006 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3008 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3009 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3011 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3018 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3020 for (i = 0; i < hw->ports; i++)
3021 sky2_gmac_reset(hw, i);
3023 memset(hw->st_le, 0, STATUS_LE_BYTES);
3026 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3027 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3029 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3030 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3032 /* Set the list last index */
3033 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3035 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3036 sky2_write8(hw, STAT_FIFO_WM, 16);
3038 /* set Status-FIFO ISR watermark */
3039 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3040 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3042 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3044 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3045 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3046 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3048 /* enable status unit */
3049 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3051 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3052 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3053 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3056 /* Take device down (offline).
3057 * Equivalent to doing dev_stop() but this does not
3058 * inform upper layers of the transistion.
3060 static void sky2_detach(struct net_device *dev)
3062 if (netif_running(dev)) {
3063 netif_device_detach(dev); /* stop txq */
3068 /* Bring device back after doing sky2_detach */
3069 static int sky2_reattach(struct net_device *dev)
3073 if (netif_running(dev)) {
3076 printk(KERN_INFO PFX "%s: could not restart %d\n",
3080 netif_device_attach(dev);
3081 sky2_set_multicast(dev);
3088 static void sky2_restart(struct work_struct *work)
3090 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3094 for (i = 0; i < hw->ports; i++)
3095 sky2_detach(hw->dev[i]);
3097 napi_disable(&hw->napi);
3098 sky2_write32(hw, B0_IMSK, 0);
3100 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3101 napi_enable(&hw->napi);
3103 for (i = 0; i < hw->ports; i++)
3104 sky2_reattach(hw->dev[i]);
3109 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3111 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3114 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3116 const struct sky2_port *sky2 = netdev_priv(dev);
3118 wol->supported = sky2_wol_supported(sky2->hw);
3119 wol->wolopts = sky2->wol;
3122 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3124 struct sky2_port *sky2 = netdev_priv(dev);
3125 struct sky2_hw *hw = sky2->hw;
3127 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3128 || !device_can_wakeup(&hw->pdev->dev))
3131 sky2->wol = wol->wolopts;
3133 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3134 hw->chip_id == CHIP_ID_YUKON_EX ||
3135 hw->chip_id == CHIP_ID_YUKON_FE_P)
3136 sky2_write32(hw, B0_CTST, sky2->wol
3137 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3139 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3141 if (!netif_running(dev))
3142 sky2_wol_init(sky2);
3146 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3148 if (sky2_is_copper(hw)) {
3149 u32 modes = SUPPORTED_10baseT_Half
3150 | SUPPORTED_10baseT_Full
3151 | SUPPORTED_100baseT_Half
3152 | SUPPORTED_100baseT_Full
3153 | SUPPORTED_Autoneg | SUPPORTED_TP;
3155 if (hw->flags & SKY2_HW_GIGABIT)
3156 modes |= SUPPORTED_1000baseT_Half
3157 | SUPPORTED_1000baseT_Full;
3160 return SUPPORTED_1000baseT_Half
3161 | SUPPORTED_1000baseT_Full
3166 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3168 struct sky2_port *sky2 = netdev_priv(dev);
3169 struct sky2_hw *hw = sky2->hw;
3171 ecmd->transceiver = XCVR_INTERNAL;
3172 ecmd->supported = sky2_supported_modes(hw);
3173 ecmd->phy_address = PHY_ADDR_MARV;
3174 if (sky2_is_copper(hw)) {
3175 ecmd->port = PORT_TP;
3176 ecmd->speed = sky2->speed;
3178 ecmd->speed = SPEED_1000;
3179 ecmd->port = PORT_FIBRE;
3182 ecmd->advertising = sky2->advertising;
3183 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3184 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3185 ecmd->duplex = sky2->duplex;
3189 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3191 struct sky2_port *sky2 = netdev_priv(dev);
3192 const struct sky2_hw *hw = sky2->hw;
3193 u32 supported = sky2_supported_modes(hw);
3195 if (ecmd->autoneg == AUTONEG_ENABLE) {
3196 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3197 ecmd->advertising = supported;
3203 switch (ecmd->speed) {
3205 if (ecmd->duplex == DUPLEX_FULL)
3206 setting = SUPPORTED_1000baseT_Full;
3207 else if (ecmd->duplex == DUPLEX_HALF)
3208 setting = SUPPORTED_1000baseT_Half;
3213 if (ecmd->duplex == DUPLEX_FULL)
3214 setting = SUPPORTED_100baseT_Full;
3215 else if (ecmd->duplex == DUPLEX_HALF)
3216 setting = SUPPORTED_100baseT_Half;
3222 if (ecmd->duplex == DUPLEX_FULL)
3223 setting = SUPPORTED_10baseT_Full;
3224 else if (ecmd->duplex == DUPLEX_HALF)
3225 setting = SUPPORTED_10baseT_Half;
3233 if ((setting & supported) == 0)
3236 sky2->speed = ecmd->speed;
3237 sky2->duplex = ecmd->duplex;
3238 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3241 sky2->advertising = ecmd->advertising;
3243 if (netif_running(dev)) {
3244 sky2_phy_reinit(sky2);
3245 sky2_set_multicast(dev);
3251 static void sky2_get_drvinfo(struct net_device *dev,
3252 struct ethtool_drvinfo *info)
3254 struct sky2_port *sky2 = netdev_priv(dev);
3256 strcpy(info->driver, DRV_NAME);
3257 strcpy(info->version, DRV_VERSION);
3258 strcpy(info->fw_version, "N/A");
3259 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3262 static const struct sky2_stat {
3263 char name[ETH_GSTRING_LEN];
3266 { "tx_bytes", GM_TXO_OK_HI },
3267 { "rx_bytes", GM_RXO_OK_HI },
3268 { "tx_broadcast", GM_TXF_BC_OK },
3269 { "rx_broadcast", GM_RXF_BC_OK },
3270 { "tx_multicast", GM_TXF_MC_OK },
3271 { "rx_multicast", GM_RXF_MC_OK },
3272 { "tx_unicast", GM_TXF_UC_OK },
3273 { "rx_unicast", GM_RXF_UC_OK },
3274 { "tx_mac_pause", GM_TXF_MPAUSE },
3275 { "rx_mac_pause", GM_RXF_MPAUSE },
3276 { "collisions", GM_TXF_COL },
3277 { "late_collision",GM_TXF_LAT_COL },
3278 { "aborted", GM_TXF_ABO_COL },
3279 { "single_collisions", GM_TXF_SNG_COL },
3280 { "multi_collisions", GM_TXF_MUL_COL },
3282 { "rx_short", GM_RXF_SHT },
3283 { "rx_runt", GM_RXE_FRAG },
3284 { "rx_64_byte_packets", GM_RXF_64B },
3285 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3286 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3287 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3288 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3289 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3290 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3291 { "rx_too_long", GM_RXF_LNG_ERR },
3292 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3293 { "rx_jabber", GM_RXF_JAB_PKT },
3294 { "rx_fcs_error", GM_RXF_FCS_ERR },
3296 { "tx_64_byte_packets", GM_TXF_64B },
3297 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3298 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3299 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3300 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3301 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3302 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3303 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3306 static u32 sky2_get_rx_csum(struct net_device *dev)
3308 struct sky2_port *sky2 = netdev_priv(dev);
3310 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3313 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3315 struct sky2_port *sky2 = netdev_priv(dev);
3318 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3320 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3322 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3323 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3328 static u32 sky2_get_msglevel(struct net_device *netdev)
3330 struct sky2_port *sky2 = netdev_priv(netdev);
3331 return sky2->msg_enable;
3334 static int sky2_nway_reset(struct net_device *dev)
3336 struct sky2_port *sky2 = netdev_priv(dev);
3338 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3341 sky2_phy_reinit(sky2);
3342 sky2_set_multicast(dev);
3347 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3349 struct sky2_hw *hw = sky2->hw;
3350 unsigned port = sky2->port;
3353 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3354 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3355 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3356 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3358 for (i = 2; i < count; i++)
3359 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3362 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3364 struct sky2_port *sky2 = netdev_priv(netdev);
3365 sky2->msg_enable = value;
3368 static int sky2_get_sset_count(struct net_device *dev, int sset)
3372 return ARRAY_SIZE(sky2_stats);
3378 static void sky2_get_ethtool_stats(struct net_device *dev,
3379 struct ethtool_stats *stats, u64 * data)
3381 struct sky2_port *sky2 = netdev_priv(dev);
3383 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3386 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3390 switch (stringset) {
3392 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3393 memcpy(data + i * ETH_GSTRING_LEN,
3394 sky2_stats[i].name, ETH_GSTRING_LEN);
3399 static int sky2_set_mac_address(struct net_device *dev, void *p)
3401 struct sky2_port *sky2 = netdev_priv(dev);
3402 struct sky2_hw *hw = sky2->hw;
3403 unsigned port = sky2->port;
3404 const struct sockaddr *addr = p;
3406 if (!is_valid_ether_addr(addr->sa_data))
3407 return -EADDRNOTAVAIL;
3409 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3410 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3411 dev->dev_addr, ETH_ALEN);
3412 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3413 dev->dev_addr, ETH_ALEN);
3415 /* virtual address for data */
3416 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3418 /* physical address: used for pause frames */
3419 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3424 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3428 bit = ether_crc(ETH_ALEN, addr) & 63;
3429 filter[bit >> 3] |= 1 << (bit & 7);
3432 static void sky2_set_multicast(struct net_device *dev)
3434 struct sky2_port *sky2 = netdev_priv(dev);
3435 struct sky2_hw *hw = sky2->hw;
3436 unsigned port = sky2->port;
3437 struct dev_mc_list *list = dev->mc_list;
3441 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3443 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3444 memset(filter, 0, sizeof(filter));
3446 reg = gma_read16(hw, port, GM_RX_CTRL);
3447 reg |= GM_RXCR_UCF_ENA;
3449 if (dev->flags & IFF_PROMISC) /* promiscuous */
3450 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3451 else if (dev->flags & IFF_ALLMULTI)
3452 memset(filter, 0xff, sizeof(filter));
3453 else if (dev->mc_count == 0 && !rx_pause)
3454 reg &= ~GM_RXCR_MCF_ENA;
3457 reg |= GM_RXCR_MCF_ENA;
3460 sky2_add_filter(filter, pause_mc_addr);
3462 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3463 sky2_add_filter(filter, list->dmi_addr);
3466 gma_write16(hw, port, GM_MC_ADDR_H1,
3467 (u16) filter[0] | ((u16) filter[1] << 8));
3468 gma_write16(hw, port, GM_MC_ADDR_H2,
3469 (u16) filter[2] | ((u16) filter[3] << 8));
3470 gma_write16(hw, port, GM_MC_ADDR_H3,
3471 (u16) filter[4] | ((u16) filter[5] << 8));
3472 gma_write16(hw, port, GM_MC_ADDR_H4,
3473 (u16) filter[6] | ((u16) filter[7] << 8));
3475 gma_write16(hw, port, GM_RX_CTRL, reg);
3478 /* Can have one global because blinking is controlled by
3479 * ethtool and that is always under RTNL mutex
3481 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3483 struct sky2_hw *hw = sky2->hw;
3484 unsigned port = sky2->port;
3486 spin_lock_bh(&sky2->phy_lock);
3487 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3488 hw->chip_id == CHIP_ID_YUKON_EX ||
3489 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3491 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3492 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3496 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3497 PHY_M_LEDC_LOS_CTRL(8) |
3498 PHY_M_LEDC_INIT_CTRL(8) |
3499 PHY_M_LEDC_STA1_CTRL(8) |
3500 PHY_M_LEDC_STA0_CTRL(8));
3503 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3504 PHY_M_LEDC_LOS_CTRL(9) |
3505 PHY_M_LEDC_INIT_CTRL(9) |
3506 PHY_M_LEDC_STA1_CTRL(9) |
3507 PHY_M_LEDC_STA0_CTRL(9));
3510 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3511 PHY_M_LEDC_LOS_CTRL(0xa) |
3512 PHY_M_LEDC_INIT_CTRL(0xa) |
3513 PHY_M_LEDC_STA1_CTRL(0xa) |
3514 PHY_M_LEDC_STA0_CTRL(0xa));
3517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3518 PHY_M_LEDC_LOS_CTRL(1) |
3519 PHY_M_LEDC_INIT_CTRL(8) |
3520 PHY_M_LEDC_STA1_CTRL(7) |
3521 PHY_M_LEDC_STA0_CTRL(7));
3524 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3526 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3527 PHY_M_LED_MO_DUP(mode) |
3528 PHY_M_LED_MO_10(mode) |
3529 PHY_M_LED_MO_100(mode) |
3530 PHY_M_LED_MO_1000(mode) |
3531 PHY_M_LED_MO_RX(mode) |
3532 PHY_M_LED_MO_TX(mode));
3534 spin_unlock_bh(&sky2->phy_lock);
3537 /* blink LED's for finding board */
3538 static int sky2_phys_id(struct net_device *dev, u32 data)
3540 struct sky2_port *sky2 = netdev_priv(dev);
3546 for (i = 0; i < data; i++) {
3547 sky2_led(sky2, MO_LED_ON);
3548 if (msleep_interruptible(500))
3550 sky2_led(sky2, MO_LED_OFF);
3551 if (msleep_interruptible(500))
3554 sky2_led(sky2, MO_LED_NORM);
3559 static void sky2_get_pauseparam(struct net_device *dev,
3560 struct ethtool_pauseparam *ecmd)
3562 struct sky2_port *sky2 = netdev_priv(dev);
3564 switch (sky2->flow_mode) {
3566 ecmd->tx_pause = ecmd->rx_pause = 0;
3569 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3572 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3575 ecmd->tx_pause = ecmd->rx_pause = 1;
3578 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3579 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3582 static int sky2_set_pauseparam(struct net_device *dev,
3583 struct ethtool_pauseparam *ecmd)
3585 struct sky2_port *sky2 = netdev_priv(dev);
3587 if (ecmd->autoneg == AUTONEG_ENABLE)
3588 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3590 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3592 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3594 if (netif_running(dev))
3595 sky2_phy_reinit(sky2);
3600 static int sky2_get_coalesce(struct net_device *dev,
3601 struct ethtool_coalesce *ecmd)
3603 struct sky2_port *sky2 = netdev_priv(dev);
3604 struct sky2_hw *hw = sky2->hw;
3606 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3607 ecmd->tx_coalesce_usecs = 0;
3609 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3610 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3612 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3614 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3615 ecmd->rx_coalesce_usecs = 0;
3617 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3618 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3620 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3622 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3623 ecmd->rx_coalesce_usecs_irq = 0;
3625 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3626 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3629 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3634 /* Note: this affect both ports */
3635 static int sky2_set_coalesce(struct net_device *dev,
3636 struct ethtool_coalesce *ecmd)
3638 struct sky2_port *sky2 = netdev_priv(dev);
3639 struct sky2_hw *hw = sky2->hw;
3640 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3642 if (ecmd->tx_coalesce_usecs > tmax ||
3643 ecmd->rx_coalesce_usecs > tmax ||
3644 ecmd->rx_coalesce_usecs_irq > tmax)
3647 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3649 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3651 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3654 if (ecmd->tx_coalesce_usecs == 0)
3655 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3657 sky2_write32(hw, STAT_TX_TIMER_INI,
3658 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3659 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3661 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3663 if (ecmd->rx_coalesce_usecs == 0)
3664 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3666 sky2_write32(hw, STAT_LEV_TIMER_INI,
3667 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3668 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3670 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3672 if (ecmd->rx_coalesce_usecs_irq == 0)
3673 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3675 sky2_write32(hw, STAT_ISR_TIMER_INI,
3676 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3677 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3679 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3683 static void sky2_get_ringparam(struct net_device *dev,
3684 struct ethtool_ringparam *ering)
3686 struct sky2_port *sky2 = netdev_priv(dev);
3688 ering->rx_max_pending = RX_MAX_PENDING;
3689 ering->rx_mini_max_pending = 0;
3690 ering->rx_jumbo_max_pending = 0;
3691 ering->tx_max_pending = TX_MAX_PENDING;
3693 ering->rx_pending = sky2->rx_pending;
3694 ering->rx_mini_pending = 0;
3695 ering->rx_jumbo_pending = 0;
3696 ering->tx_pending = sky2->tx_pending;
3699 static int sky2_set_ringparam(struct net_device *dev,
3700 struct ethtool_ringparam *ering)
3702 struct sky2_port *sky2 = netdev_priv(dev);
3704 if (ering->rx_pending > RX_MAX_PENDING ||
3705 ering->rx_pending < 8 ||
3706 ering->tx_pending < TX_MIN_PENDING ||
3707 ering->tx_pending > TX_MAX_PENDING)
3712 sky2->rx_pending = ering->rx_pending;
3713 sky2->tx_pending = ering->tx_pending;
3714 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3716 return sky2_reattach(dev);
3719 static int sky2_get_regs_len(struct net_device *dev)
3725 * Returns copy of control register region
3726 * Note: ethtool_get_regs always provides full size (16k) buffer
3728 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3731 const struct sky2_port *sky2 = netdev_priv(dev);
3732 const void __iomem *io = sky2->hw->regs;
3737 for (b = 0; b < 128; b++) {
3738 /* This complicated switch statement is to make sure and
3739 * only access regions that are unreserved.
3740 * Some blocks are only valid on dual port cards.
3741 * and block 3 has some special diagnostic registers that
3746 /* skip diagnostic ram region */
3747 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3750 /* dual port cards only */
3751 case 5: /* Tx Arbiter 2 */
3753 case 14 ... 15: /* TX2 */
3754 case 17: case 19: /* Ram Buffer 2 */
3755 case 22 ... 23: /* Tx Ram Buffer 2 */
3756 case 25: /* Rx MAC Fifo 1 */
3757 case 27: /* Tx MAC Fifo 2 */
3758 case 31: /* GPHY 2 */
3759 case 40 ... 47: /* Pattern Ram 2 */
3760 case 52: case 54: /* TCP Segmentation 2 */
3761 case 112 ... 116: /* GMAC 2 */
3762 if (sky2->hw->ports == 1)
3765 case 0: /* Control */
3766 case 2: /* Mac address */
3767 case 4: /* Tx Arbiter 1 */
3768 case 7: /* PCI express reg */
3770 case 12 ... 13: /* TX1 */
3771 case 16: case 18:/* Rx Ram Buffer 1 */
3772 case 20 ... 21: /* Tx Ram Buffer 1 */
3773 case 24: /* Rx MAC Fifo 1 */
3774 case 26: /* Tx MAC Fifo 1 */
3775 case 28 ... 29: /* Descriptor and status unit */
3776 case 30: /* GPHY 1*/
3777 case 32 ... 39: /* Pattern Ram 1 */
3778 case 48: case 50: /* TCP Segmentation 1 */
3779 case 56 ... 60: /* PCI space */
3780 case 80 ... 84: /* GMAC 1 */
3781 memcpy_fromio(p, io, 128);
3793 /* In order to do Jumbo packets on these chips, need to turn off the
3794 * transmit store/forward. Therefore checksum offload won't work.
3796 static int no_tx_offload(struct net_device *dev)
3798 const struct sky2_port *sky2 = netdev_priv(dev);
3799 const struct sky2_hw *hw = sky2->hw;
3801 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3804 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3806 if (data && no_tx_offload(dev))
3809 return ethtool_op_set_tx_csum(dev, data);
3813 static int sky2_set_tso(struct net_device *dev, u32 data)
3815 if (data && no_tx_offload(dev))
3818 return ethtool_op_set_tso(dev, data);
3821 static int sky2_get_eeprom_len(struct net_device *dev)
3823 struct sky2_port *sky2 = netdev_priv(dev);
3824 struct sky2_hw *hw = sky2->hw;
3827 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3828 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3831 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3833 unsigned long start = jiffies;
3835 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3836 /* Can take up to 10.6 ms for write */
3837 if (time_after(jiffies, start + HZ/4)) {
3838 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3847 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3848 u16 offset, size_t length)
3852 while (length > 0) {
3855 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3856 rc = sky2_vpd_wait(hw, cap, 0);
3860 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3862 memcpy(data, &val, min(sizeof(val), length));
3863 offset += sizeof(u32);
3864 data += sizeof(u32);
3865 length -= sizeof(u32);
3871 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3872 u16 offset, unsigned int length)
3877 for (i = 0; i < length; i += sizeof(u32)) {
3878 u32 val = *(u32 *)(data + i);
3880 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3881 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3883 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3890 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3893 struct sky2_port *sky2 = netdev_priv(dev);
3894 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3899 eeprom->magic = SKY2_EEPROM_MAGIC;
3901 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3904 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3907 struct sky2_port *sky2 = netdev_priv(dev);
3908 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3913 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3916 /* Partial writes not supported */
3917 if ((eeprom->offset & 3) || (eeprom->len & 3))
3920 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3924 static const struct ethtool_ops sky2_ethtool_ops = {
3925 .get_settings = sky2_get_settings,
3926 .set_settings = sky2_set_settings,
3927 .get_drvinfo = sky2_get_drvinfo,
3928 .get_wol = sky2_get_wol,
3929 .set_wol = sky2_set_wol,
3930 .get_msglevel = sky2_get_msglevel,
3931 .set_msglevel = sky2_set_msglevel,
3932 .nway_reset = sky2_nway_reset,
3933 .get_regs_len = sky2_get_regs_len,
3934 .get_regs = sky2_get_regs,
3935 .get_link = ethtool_op_get_link,
3936 .get_eeprom_len = sky2_get_eeprom_len,
3937 .get_eeprom = sky2_get_eeprom,
3938 .set_eeprom = sky2_set_eeprom,
3939 .set_sg = ethtool_op_set_sg,
3940 .set_tx_csum = sky2_set_tx_csum,
3941 .set_tso = sky2_set_tso,
3942 .get_rx_csum = sky2_get_rx_csum,
3943 .set_rx_csum = sky2_set_rx_csum,
3944 .get_strings = sky2_get_strings,
3945 .get_coalesce = sky2_get_coalesce,
3946 .set_coalesce = sky2_set_coalesce,
3947 .get_ringparam = sky2_get_ringparam,
3948 .set_ringparam = sky2_set_ringparam,
3949 .get_pauseparam = sky2_get_pauseparam,
3950 .set_pauseparam = sky2_set_pauseparam,
3951 .phys_id = sky2_phys_id,
3952 .get_sset_count = sky2_get_sset_count,
3953 .get_ethtool_stats = sky2_get_ethtool_stats,
3956 #ifdef CONFIG_SKY2_DEBUG
3958 static struct dentry *sky2_debug;
3962 * Read and parse the first part of Vital Product Data
3964 #define VPD_SIZE 128
3965 #define VPD_MAGIC 0x82
3967 static const struct vpd_tag {
3971 { "PN", "Part Number" },
3972 { "EC", "Engineering Level" },
3973 { "MN", "Manufacturer" },
3974 { "SN", "Serial Number" },
3975 { "YA", "Asset Tag" },
3976 { "VL", "First Error Log Message" },
3977 { "VF", "Second Error Log Message" },
3978 { "VB", "Boot Agent ROM Configuration" },
3979 { "VE", "EFI UNDI Configuration" },
3982 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3990 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3991 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3993 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3994 buf = kmalloc(vpd_size, GFP_KERNEL);
3996 seq_puts(seq, "no memory!\n");
4000 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4001 seq_puts(seq, "VPD read failed\n");
4005 if (buf[0] != VPD_MAGIC) {
4006 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4010 if (len == 0 || len > vpd_size - 4) {
4011 seq_printf(seq, "Invalid id length: %d\n", len);
4015 seq_printf(seq, "%.*s\n", len, buf + 3);
4018 while (offs < vpd_size - 4) {
4021 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4023 len = buf[offs + 2];
4024 if (offs + len + 3 >= vpd_size)
4027 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4028 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4029 seq_printf(seq, " %s: %.*s\n",
4030 vpd_tags[i].label, len, buf + offs + 3);
4040 static int sky2_debug_show(struct seq_file *seq, void *v)
4042 struct net_device *dev = seq->private;
4043 const struct sky2_port *sky2 = netdev_priv(dev);
4044 struct sky2_hw *hw = sky2->hw;
4045 unsigned port = sky2->port;
4049 sky2_show_vpd(seq, hw);
4051 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4052 sky2_read32(hw, B0_ISRC),
4053 sky2_read32(hw, B0_IMSK),
4054 sky2_read32(hw, B0_Y2_SP_ICR));
4056 if (!netif_running(dev)) {
4057 seq_printf(seq, "network not running\n");
4061 napi_disable(&hw->napi);
4062 last = sky2_read16(hw, STAT_PUT_IDX);
4064 if (hw->st_idx == last)
4065 seq_puts(seq, "Status ring (empty)\n");
4067 seq_puts(seq, "Status ring\n");
4068 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4069 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4070 const struct sky2_status_le *le = hw->st_le + idx;
4071 seq_printf(seq, "[%d] %#x %d %#x\n",
4072 idx, le->opcode, le->length, le->status);
4074 seq_puts(seq, "\n");
4077 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4078 sky2->tx_cons, sky2->tx_prod,
4079 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4080 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4082 /* Dump contents of tx ring */
4084 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4085 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4086 const struct sky2_tx_le *le = sky2->tx_le + idx;
4087 u32 a = le32_to_cpu(le->addr);
4090 seq_printf(seq, "%u:", idx);
4093 switch(le->opcode & ~HW_OWNER) {
4095 seq_printf(seq, " %#x:", a);
4098 seq_printf(seq, " mtu=%d", a);
4101 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4104 seq_printf(seq, " csum=%#x", a);
4107 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4110 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4113 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4116 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4117 a, le16_to_cpu(le->length));
4120 if (le->ctrl & EOP) {
4121 seq_putc(seq, '\n');
4126 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4127 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4128 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4129 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4131 sky2_read32(hw, B0_Y2_SP_LISR);
4132 napi_enable(&hw->napi);
4136 static int sky2_debug_open(struct inode *inode, struct file *file)
4138 return single_open(file, sky2_debug_show, inode->i_private);
4141 static const struct file_operations sky2_debug_fops = {
4142 .owner = THIS_MODULE,
4143 .open = sky2_debug_open,
4145 .llseek = seq_lseek,
4146 .release = single_release,
4150 * Use network device events to create/remove/rename
4151 * debugfs file entries
4153 static int sky2_device_event(struct notifier_block *unused,
4154 unsigned long event, void *ptr)
4156 struct net_device *dev = ptr;
4157 struct sky2_port *sky2 = netdev_priv(dev);
4159 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4163 case NETDEV_CHANGENAME:
4164 if (sky2->debugfs) {
4165 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4166 sky2_debug, dev->name);
4170 case NETDEV_GOING_DOWN:
4171 if (sky2->debugfs) {
4172 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4174 debugfs_remove(sky2->debugfs);
4175 sky2->debugfs = NULL;
4180 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4183 if (IS_ERR(sky2->debugfs))
4184 sky2->debugfs = NULL;
4190 static struct notifier_block sky2_notifier = {
4191 .notifier_call = sky2_device_event,
4195 static __init void sky2_debug_init(void)
4199 ent = debugfs_create_dir("sky2", NULL);
4200 if (!ent || IS_ERR(ent))
4204 register_netdevice_notifier(&sky2_notifier);
4207 static __exit void sky2_debug_cleanup(void)
4210 unregister_netdevice_notifier(&sky2_notifier);
4211 debugfs_remove(sky2_debug);
4217 #define sky2_debug_init()
4218 #define sky2_debug_cleanup()
4221 /* Two copies of network device operations to handle special case of
4222 not allowing netpoll on second port */
4223 static const struct net_device_ops sky2_netdev_ops[2] = {
4225 .ndo_open = sky2_up,
4226 .ndo_stop = sky2_down,
4227 .ndo_start_xmit = sky2_xmit_frame,
4228 .ndo_do_ioctl = sky2_ioctl,
4229 .ndo_validate_addr = eth_validate_addr,
4230 .ndo_set_mac_address = sky2_set_mac_address,
4231 .ndo_set_multicast_list = sky2_set_multicast,
4232 .ndo_change_mtu = sky2_change_mtu,
4233 .ndo_tx_timeout = sky2_tx_timeout,
4234 #ifdef SKY2_VLAN_TAG_USED
4235 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4237 #ifdef CONFIG_NET_POLL_CONTROLLER
4238 .ndo_poll_controller = sky2_netpoll,
4242 .ndo_open = sky2_up,
4243 .ndo_stop = sky2_down,
4244 .ndo_start_xmit = sky2_xmit_frame,
4245 .ndo_do_ioctl = sky2_ioctl,
4246 .ndo_validate_addr = eth_validate_addr,
4247 .ndo_set_mac_address = sky2_set_mac_address,
4248 .ndo_set_multicast_list = sky2_set_multicast,
4249 .ndo_change_mtu = sky2_change_mtu,
4250 .ndo_tx_timeout = sky2_tx_timeout,
4251 #ifdef SKY2_VLAN_TAG_USED
4252 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4257 /* Initialize network device */
4258 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4260 int highmem, int wol)
4262 struct sky2_port *sky2;
4263 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4266 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4270 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4271 dev->irq = hw->pdev->irq;
4272 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4273 dev->watchdog_timeo = TX_WATCHDOG;
4274 dev->netdev_ops = &sky2_netdev_ops[port];
4276 sky2 = netdev_priv(dev);
4279 sky2->msg_enable = netif_msg_init(debug, default_msg);
4281 /* Auto speed and flow control */
4282 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4283 if (hw->chip_id != CHIP_ID_YUKON_XL)
4284 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4286 sky2->flow_mode = FC_BOTH;
4290 sky2->advertising = sky2_supported_modes(hw);
4293 spin_lock_init(&sky2->phy_lock);
4295 sky2->tx_pending = TX_DEF_PENDING;
4296 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4297 sky2->rx_pending = RX_DEF_PENDING;
4299 hw->dev[port] = dev;
4303 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4305 dev->features |= NETIF_F_HIGHDMA;
4307 #ifdef SKY2_VLAN_TAG_USED
4308 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4309 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4310 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4311 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4315 /* read the mac address */
4316 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4317 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4322 static void __devinit sky2_show_addr(struct net_device *dev)
4324 const struct sky2_port *sky2 = netdev_priv(dev);
4326 if (netif_msg_probe(sky2))
4327 printk(KERN_INFO PFX "%s: addr %pM\n",
4328 dev->name, dev->dev_addr);
4331 /* Handle software interrupt used during MSI test */
4332 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4334 struct sky2_hw *hw = dev_id;
4335 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4340 if (status & Y2_IS_IRQ_SW) {
4341 hw->flags |= SKY2_HW_USE_MSI;
4342 wake_up(&hw->msi_wait);
4343 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4345 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4350 /* Test interrupt path by forcing a a software IRQ */
4351 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4353 struct pci_dev *pdev = hw->pdev;
4356 init_waitqueue_head (&hw->msi_wait);
4358 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4360 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4362 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4366 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4367 sky2_read8(hw, B0_CTST);
4369 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4371 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4372 /* MSI test failed, go back to INTx mode */
4373 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4374 "switching to INTx mode.\n");
4377 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4380 sky2_write32(hw, B0_IMSK, 0);
4381 sky2_read32(hw, B0_IMSK);
4383 free_irq(pdev->irq, hw);
4388 /* This driver supports yukon2 chipset only */
4389 static const char *sky2_name(u8 chipid, char *buf, int sz)
4391 const char *name[] = {
4393 "EC Ultra", /* 0xb4 */
4394 "Extreme", /* 0xb5 */
4398 "Supreme", /* 0xb9 */
4402 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4403 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4405 snprintf(buf, sz, "(chip %#x)", chipid);
4409 static int __devinit sky2_probe(struct pci_dev *pdev,
4410 const struct pci_device_id *ent)
4412 struct net_device *dev;
4414 int err, using_dac = 0, wol_default;
4418 err = pci_enable_device(pdev);
4420 dev_err(&pdev->dev, "cannot enable PCI device\n");
4424 /* Get configuration information
4425 * Note: only regular PCI config access once to test for HW issues
4426 * other PCI access through shared memory for speed and to
4427 * avoid MMCONFIG problems.
4429 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4431 dev_err(&pdev->dev, "PCI read config failed\n");
4436 dev_err(&pdev->dev, "PCI configuration read error\n");
4440 err = pci_request_regions(pdev, DRV_NAME);
4442 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4443 goto err_out_disable;
4446 pci_set_master(pdev);
4448 if (sizeof(dma_addr_t) > sizeof(u32) &&
4449 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4451 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4453 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4454 "for consistent allocations\n");
4455 goto err_out_free_regions;
4458 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4460 dev_err(&pdev->dev, "no usable DMA configuration\n");
4461 goto err_out_free_regions;
4467 /* The sk98lin vendor driver uses hardware byte swapping but
4468 * this driver uses software swapping.
4470 reg &= ~PCI_REV_DESC;
4471 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4473 dev_err(&pdev->dev, "PCI write config failed\n");
4474 goto err_out_free_regions;
4478 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4481 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4483 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4484 goto err_out_free_regions;
4489 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4491 dev_err(&pdev->dev, "cannot map device registers\n");
4492 goto err_out_free_hw;
4495 /* ring for status responses */
4496 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4498 goto err_out_iounmap;
4500 err = sky2_init(hw);
4502 goto err_out_iounmap;
4504 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4505 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4509 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4512 goto err_out_free_pci;
4515 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4516 err = sky2_test_msi(hw);
4517 if (err == -EOPNOTSUPP)
4518 pci_disable_msi(pdev);
4520 goto err_out_free_netdev;
4523 err = register_netdev(dev);
4525 dev_err(&pdev->dev, "cannot register net device\n");
4526 goto err_out_free_netdev;
4529 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4531 err = request_irq(pdev->irq, sky2_intr,
4532 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4535 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4536 goto err_out_unregister;
4538 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4539 napi_enable(&hw->napi);
4541 sky2_show_addr(dev);
4543 if (hw->ports > 1) {
4544 struct net_device *dev1;
4546 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4548 dev_warn(&pdev->dev, "allocation for second device failed\n");
4549 else if ((err = register_netdev(dev1))) {
4550 dev_warn(&pdev->dev,
4551 "register of second port failed (%d)\n", err);
4555 sky2_show_addr(dev1);
4558 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4559 INIT_WORK(&hw->restart_work, sky2_restart);
4561 pci_set_drvdata(pdev, hw);
4566 if (hw->flags & SKY2_HW_USE_MSI)
4567 pci_disable_msi(pdev);
4568 unregister_netdev(dev);
4569 err_out_free_netdev:
4572 sky2_write8(hw, B0_CTST, CS_RST_SET);
4573 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4578 err_out_free_regions:
4579 pci_release_regions(pdev);
4581 pci_disable_device(pdev);
4583 pci_set_drvdata(pdev, NULL);
4587 static void __devexit sky2_remove(struct pci_dev *pdev)
4589 struct sky2_hw *hw = pci_get_drvdata(pdev);
4595 del_timer_sync(&hw->watchdog_timer);
4596 cancel_work_sync(&hw->restart_work);
4598 for (i = hw->ports-1; i >= 0; --i)
4599 unregister_netdev(hw->dev[i]);
4601 sky2_write32(hw, B0_IMSK, 0);
4605 sky2_write8(hw, B0_CTST, CS_RST_SET);
4606 sky2_read8(hw, B0_CTST);
4608 free_irq(pdev->irq, hw);
4609 if (hw->flags & SKY2_HW_USE_MSI)
4610 pci_disable_msi(pdev);
4611 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4612 pci_release_regions(pdev);
4613 pci_disable_device(pdev);
4615 for (i = hw->ports-1; i >= 0; --i)
4616 free_netdev(hw->dev[i]);
4621 pci_set_drvdata(pdev, NULL);
4625 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4627 struct sky2_hw *hw = pci_get_drvdata(pdev);
4633 del_timer_sync(&hw->watchdog_timer);
4634 cancel_work_sync(&hw->restart_work);
4637 for (i = 0; i < hw->ports; i++) {
4638 struct net_device *dev = hw->dev[i];
4639 struct sky2_port *sky2 = netdev_priv(dev);
4644 sky2_wol_init(sky2);
4649 sky2_write32(hw, B0_IMSK, 0);
4650 napi_disable(&hw->napi);
4654 pci_save_state(pdev);
4655 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4656 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4661 static int sky2_resume(struct pci_dev *pdev)
4663 struct sky2_hw *hw = pci_get_drvdata(pdev);
4669 err = pci_set_power_state(pdev, PCI_D0);
4673 err = pci_restore_state(pdev);
4677 pci_enable_wake(pdev, PCI_D0, 0);
4679 /* Re-enable all clocks */
4680 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4681 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4682 hw->chip_id == CHIP_ID_YUKON_FE_P)
4683 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4686 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4687 napi_enable(&hw->napi);
4690 for (i = 0; i < hw->ports; i++) {
4691 err = sky2_reattach(hw->dev[i]);
4701 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4702 pci_disable_device(pdev);
4707 static void sky2_shutdown(struct pci_dev *pdev)
4709 struct sky2_hw *hw = pci_get_drvdata(pdev);
4716 del_timer_sync(&hw->watchdog_timer);
4718 for (i = 0; i < hw->ports; i++) {
4719 struct net_device *dev = hw->dev[i];
4720 struct sky2_port *sky2 = netdev_priv(dev);
4724 sky2_wol_init(sky2);
4732 pci_enable_wake(pdev, PCI_D3hot, wol);
4733 pci_enable_wake(pdev, PCI_D3cold, wol);
4735 pci_disable_device(pdev);
4736 pci_set_power_state(pdev, PCI_D3hot);
4739 static struct pci_driver sky2_driver = {
4741 .id_table = sky2_id_table,
4742 .probe = sky2_probe,
4743 .remove = __devexit_p(sky2_remove),
4745 .suspend = sky2_suspend,
4746 .resume = sky2_resume,
4748 .shutdown = sky2_shutdown,
4751 static int __init sky2_init_module(void)
4753 pr_info(PFX "driver version " DRV_VERSION "\n");
4756 return pci_register_driver(&sky2_driver);
4759 static void __exit sky2_cleanup_module(void)
4761 pci_unregister_driver(&sky2_driver);
4762 sky2_debug_cleanup();
4765 module_init(sky2_init_module);
4766 module_exit(sky2_cleanup_module);
4768 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4769 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4770 MODULE_LICENSE("GPL");
4771 MODULE_VERSION(DRV_VERSION);