2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/sched.h>
43 #include <linux/seq_file.h>
44 #include <linux/mii.h>
49 #define DRV_NAME "skge"
50 #define DRV_VERSION "1.13"
52 #define DEFAULT_TX_RING_SIZE 128
53 #define DEFAULT_RX_RING_SIZE 512
54 #define MAX_TX_RING_SIZE 1024
55 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
56 #define MAX_RX_RING_SIZE 4096
57 #define RX_COPY_THRESHOLD 128
58 #define RX_BUF_SIZE 1536
59 #define PHY_RETRIES 1000
60 #define ETH_JUMBO_MTU 9000
61 #define TX_WATCHDOG (5 * HZ)
62 #define NAPI_WEIGHT 64
66 #define SKGE_EEPROM_MAGIC 0x9933aabb
69 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
70 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
71 MODULE_LICENSE("GPL");
72 MODULE_VERSION(DRV_VERSION);
74 static const u32 default_msg
75 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
76 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
78 static int debug = -1; /* defaults above */
79 module_param(debug, int, 0);
80 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
82 static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
83 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
84 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
85 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
86 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
87 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
88 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
89 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
90 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
91 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
92 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
93 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
96 MODULE_DEVICE_TABLE(pci, skge_id_table);
98 static int skge_up(struct net_device *dev);
99 static int skge_down(struct net_device *dev);
100 static void skge_phy_reset(struct skge_port *skge);
101 static void skge_tx_clean(struct net_device *dev);
102 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
104 static void genesis_get_stats(struct skge_port *skge, u64 *data);
105 static void yukon_get_stats(struct skge_port *skge, u64 *data);
106 static void yukon_init(struct skge_hw *hw, int port);
107 static void genesis_mac_init(struct skge_hw *hw, int port);
108 static void genesis_link_up(struct skge_port *skge);
109 static void skge_set_multicast(struct net_device *dev);
111 /* Avoid conditionals by using array */
112 static const int txqaddr[] = { Q_XA1, Q_XA2 };
113 static const int rxqaddr[] = { Q_R1, Q_R2 };
114 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
115 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
116 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
117 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
119 static int skge_get_regs_len(struct net_device *dev)
125 * Returns copy of whole control register region
126 * Note: skip RAM address register because accessing it will
129 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
132 const struct skge_port *skge = netdev_priv(dev);
133 const void __iomem *io = skge->hw->regs;
136 memset(p, 0, regs->len);
137 memcpy_fromio(p, io, B3_RAM_ADDR);
139 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
140 regs->len - B3_RI_WTO_R1);
143 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
144 static u32 wol_supported(const struct skge_hw *hw)
146 if (hw->chip_id == CHIP_ID_GENESIS)
149 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
152 return WAKE_MAGIC | WAKE_PHY;
155 static void skge_wol_init(struct skge_port *skge)
157 struct skge_hw *hw = skge->hw;
158 int port = skge->port;
161 skge_write16(hw, B0_CTST, CS_RST_CLR);
162 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
165 skge_write8(hw, B0_POWER_CTRL,
166 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
168 /* WA code for COMA mode -- clear PHY reset */
169 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
170 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
171 u32 reg = skge_read32(hw, B2_GP_IO);
174 skge_write32(hw, B2_GP_IO, reg);
177 skge_write32(hw, SK_REG(port, GPHY_CTRL),
179 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
180 GPC_ANEG_1 | GPC_RST_SET);
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
184 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
185 GPC_ANEG_1 | GPC_RST_CLR);
187 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
189 /* Force to 10/100 skge_reset will re-enable on resume */
190 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
191 PHY_AN_100FULL | PHY_AN_100HALF |
192 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
194 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
195 gm_phy_write(hw, port, PHY_MARV_CTRL,
196 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
197 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
200 /* Set GMAC to no flow control and auto update for speed/duplex */
201 gma_write16(hw, port, GM_GP_CTRL,
202 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
203 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
205 /* Set WOL address */
206 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
207 skge->netdev->dev_addr, ETH_ALEN);
209 /* Turn on appropriate WOL control bits */
210 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
212 if (skge->wol & WAKE_PHY)
213 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
215 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
217 if (skge->wol & WAKE_MAGIC)
218 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
220 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
222 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
223 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
226 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
229 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
231 struct skge_port *skge = netdev_priv(dev);
233 wol->supported = wol_supported(skge->hw);
234 wol->wolopts = skge->wol;
237 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
239 struct skge_port *skge = netdev_priv(dev);
240 struct skge_hw *hw = skge->hw;
242 if ((wol->wolopts & ~wol_supported(hw)) ||
243 !device_can_wakeup(&hw->pdev->dev))
246 skge->wol = wol->wolopts;
248 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
253 /* Determine supported/advertised modes based on hardware.
254 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
256 static u32 skge_supported_modes(const struct skge_hw *hw)
261 supported = SUPPORTED_10baseT_Half
262 | SUPPORTED_10baseT_Full
263 | SUPPORTED_100baseT_Half
264 | SUPPORTED_100baseT_Full
265 | SUPPORTED_1000baseT_Half
266 | SUPPORTED_1000baseT_Full
267 | SUPPORTED_Autoneg| SUPPORTED_TP;
269 if (hw->chip_id == CHIP_ID_GENESIS)
270 supported &= ~(SUPPORTED_10baseT_Half
271 | SUPPORTED_10baseT_Full
272 | SUPPORTED_100baseT_Half
273 | SUPPORTED_100baseT_Full);
275 else if (hw->chip_id == CHIP_ID_YUKON)
276 supported &= ~SUPPORTED_1000baseT_Half;
278 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
279 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
284 static int skge_get_settings(struct net_device *dev,
285 struct ethtool_cmd *ecmd)
287 struct skge_port *skge = netdev_priv(dev);
288 struct skge_hw *hw = skge->hw;
290 ecmd->transceiver = XCVR_INTERNAL;
291 ecmd->supported = skge_supported_modes(hw);
294 ecmd->port = PORT_TP;
295 ecmd->phy_address = hw->phy_addr;
297 ecmd->port = PORT_FIBRE;
299 ecmd->advertising = skge->advertising;
300 ecmd->autoneg = skge->autoneg;
301 ecmd->speed = skge->speed;
302 ecmd->duplex = skge->duplex;
306 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
308 struct skge_port *skge = netdev_priv(dev);
309 const struct skge_hw *hw = skge->hw;
310 u32 supported = skge_supported_modes(hw);
313 if (ecmd->autoneg == AUTONEG_ENABLE) {
314 ecmd->advertising = supported;
320 switch (ecmd->speed) {
322 if (ecmd->duplex == DUPLEX_FULL)
323 setting = SUPPORTED_1000baseT_Full;
324 else if (ecmd->duplex == DUPLEX_HALF)
325 setting = SUPPORTED_1000baseT_Half;
330 if (ecmd->duplex == DUPLEX_FULL)
331 setting = SUPPORTED_100baseT_Full;
332 else if (ecmd->duplex == DUPLEX_HALF)
333 setting = SUPPORTED_100baseT_Half;
339 if (ecmd->duplex == DUPLEX_FULL)
340 setting = SUPPORTED_10baseT_Full;
341 else if (ecmd->duplex == DUPLEX_HALF)
342 setting = SUPPORTED_10baseT_Half;
350 if ((setting & supported) == 0)
353 skge->speed = ecmd->speed;
354 skge->duplex = ecmd->duplex;
357 skge->autoneg = ecmd->autoneg;
358 skge->advertising = ecmd->advertising;
360 if (netif_running(dev)) {
372 static void skge_get_drvinfo(struct net_device *dev,
373 struct ethtool_drvinfo *info)
375 struct skge_port *skge = netdev_priv(dev);
377 strcpy(info->driver, DRV_NAME);
378 strcpy(info->version, DRV_VERSION);
379 strcpy(info->fw_version, "N/A");
380 strcpy(info->bus_info, pci_name(skge->hw->pdev));
383 static const struct skge_stat {
384 char name[ETH_GSTRING_LEN];
388 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
389 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
391 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
392 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
393 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
394 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
395 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
396 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
397 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
398 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
400 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
401 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
402 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
403 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
404 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
405 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
407 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
408 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
409 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
410 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
411 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
414 static int skge_get_sset_count(struct net_device *dev, int sset)
418 return ARRAY_SIZE(skge_stats);
424 static void skge_get_ethtool_stats(struct net_device *dev,
425 struct ethtool_stats *stats, u64 *data)
427 struct skge_port *skge = netdev_priv(dev);
429 if (skge->hw->chip_id == CHIP_ID_GENESIS)
430 genesis_get_stats(skge, data);
432 yukon_get_stats(skge, data);
435 /* Use hardware MIB variables for critical path statistics and
436 * transmit feedback not reported at interrupt.
437 * Other errors are accounted for in interrupt handler.
439 static struct net_device_stats *skge_get_stats(struct net_device *dev)
441 struct skge_port *skge = netdev_priv(dev);
442 u64 data[ARRAY_SIZE(skge_stats)];
444 if (skge->hw->chip_id == CHIP_ID_GENESIS)
445 genesis_get_stats(skge, data);
447 yukon_get_stats(skge, data);
449 dev->stats.tx_bytes = data[0];
450 dev->stats.rx_bytes = data[1];
451 dev->stats.tx_packets = data[2] + data[4] + data[6];
452 dev->stats.rx_packets = data[3] + data[5] + data[7];
453 dev->stats.multicast = data[3] + data[5];
454 dev->stats.collisions = data[10];
455 dev->stats.tx_aborted_errors = data[12];
460 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
466 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
467 memcpy(data + i * ETH_GSTRING_LEN,
468 skge_stats[i].name, ETH_GSTRING_LEN);
473 static void skge_get_ring_param(struct net_device *dev,
474 struct ethtool_ringparam *p)
476 struct skge_port *skge = netdev_priv(dev);
478 p->rx_max_pending = MAX_RX_RING_SIZE;
479 p->tx_max_pending = MAX_TX_RING_SIZE;
480 p->rx_mini_max_pending = 0;
481 p->rx_jumbo_max_pending = 0;
483 p->rx_pending = skge->rx_ring.count;
484 p->tx_pending = skge->tx_ring.count;
485 p->rx_mini_pending = 0;
486 p->rx_jumbo_pending = 0;
489 static int skge_set_ring_param(struct net_device *dev,
490 struct ethtool_ringparam *p)
492 struct skge_port *skge = netdev_priv(dev);
495 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
496 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
499 skge->rx_ring.count = p->rx_pending;
500 skge->tx_ring.count = p->tx_pending;
502 if (netif_running(dev)) {
512 static u32 skge_get_msglevel(struct net_device *netdev)
514 struct skge_port *skge = netdev_priv(netdev);
515 return skge->msg_enable;
518 static void skge_set_msglevel(struct net_device *netdev, u32 value)
520 struct skge_port *skge = netdev_priv(netdev);
521 skge->msg_enable = value;
524 static int skge_nway_reset(struct net_device *dev)
526 struct skge_port *skge = netdev_priv(dev);
528 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
531 skge_phy_reset(skge);
535 static int skge_set_sg(struct net_device *dev, u32 data)
537 struct skge_port *skge = netdev_priv(dev);
538 struct skge_hw *hw = skge->hw;
540 if (hw->chip_id == CHIP_ID_GENESIS && data)
542 return ethtool_op_set_sg(dev, data);
545 static int skge_set_tx_csum(struct net_device *dev, u32 data)
547 struct skge_port *skge = netdev_priv(dev);
548 struct skge_hw *hw = skge->hw;
550 if (hw->chip_id == CHIP_ID_GENESIS && data)
553 return ethtool_op_set_tx_csum(dev, data);
556 static u32 skge_get_rx_csum(struct net_device *dev)
558 struct skge_port *skge = netdev_priv(dev);
560 return skge->rx_csum;
563 /* Only Yukon supports checksum offload. */
564 static int skge_set_rx_csum(struct net_device *dev, u32 data)
566 struct skge_port *skge = netdev_priv(dev);
568 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
571 skge->rx_csum = data;
575 static void skge_get_pauseparam(struct net_device *dev,
576 struct ethtool_pauseparam *ecmd)
578 struct skge_port *skge = netdev_priv(dev);
580 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
581 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
582 ecmd->tx_pause = (ecmd->rx_pause ||
583 (skge->flow_control == FLOW_MODE_LOC_SEND));
585 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
588 static int skge_set_pauseparam(struct net_device *dev,
589 struct ethtool_pauseparam *ecmd)
591 struct skge_port *skge = netdev_priv(dev);
592 struct ethtool_pauseparam old;
595 skge_get_pauseparam(dev, &old);
597 if (ecmd->autoneg != old.autoneg)
598 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
600 if (ecmd->rx_pause && ecmd->tx_pause)
601 skge->flow_control = FLOW_MODE_SYMMETRIC;
602 else if (ecmd->rx_pause && !ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYM_OR_REM;
604 else if (!ecmd->rx_pause && ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_LOC_SEND;
607 skge->flow_control = FLOW_MODE_NONE;
610 if (netif_running(dev)) {
622 /* Chip internal frequency for clock calculations */
623 static inline u32 hwkhz(const struct skge_hw *hw)
625 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
628 /* Chip HZ to microseconds */
629 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
631 return (ticks * 1000) / hwkhz(hw);
634 /* Microseconds to chip HZ */
635 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
637 return hwkhz(hw) * usec / 1000;
640 static int skge_get_coalesce(struct net_device *dev,
641 struct ethtool_coalesce *ecmd)
643 struct skge_port *skge = netdev_priv(dev);
644 struct skge_hw *hw = skge->hw;
645 int port = skge->port;
647 ecmd->rx_coalesce_usecs = 0;
648 ecmd->tx_coalesce_usecs = 0;
650 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
651 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
652 u32 msk = skge_read32(hw, B2_IRQM_MSK);
654 if (msk & rxirqmask[port])
655 ecmd->rx_coalesce_usecs = delay;
656 if (msk & txirqmask[port])
657 ecmd->tx_coalesce_usecs = delay;
663 /* Note: interrupt timer is per board, but can turn on/off per port */
664 static int skge_set_coalesce(struct net_device *dev,
665 struct ethtool_coalesce *ecmd)
667 struct skge_port *skge = netdev_priv(dev);
668 struct skge_hw *hw = skge->hw;
669 int port = skge->port;
670 u32 msk = skge_read32(hw, B2_IRQM_MSK);
673 if (ecmd->rx_coalesce_usecs == 0)
674 msk &= ~rxirqmask[port];
675 else if (ecmd->rx_coalesce_usecs < 25 ||
676 ecmd->rx_coalesce_usecs > 33333)
679 msk |= rxirqmask[port];
680 delay = ecmd->rx_coalesce_usecs;
683 if (ecmd->tx_coalesce_usecs == 0)
684 msk &= ~txirqmask[port];
685 else if (ecmd->tx_coalesce_usecs < 25 ||
686 ecmd->tx_coalesce_usecs > 33333)
689 msk |= txirqmask[port];
690 delay = min(delay, ecmd->rx_coalesce_usecs);
693 skge_write32(hw, B2_IRQM_MSK, msk);
695 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
697 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
698 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
703 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
704 static void skge_led(struct skge_port *skge, enum led_mode mode)
706 struct skge_hw *hw = skge->hw;
707 int port = skge->port;
709 spin_lock_bh(&hw->phy_lock);
710 if (hw->chip_id == CHIP_ID_GENESIS) {
713 if (hw->phy_type == SK_PHY_BCOM)
714 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
716 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
717 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
719 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
720 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
721 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
725 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
726 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
728 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
729 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
734 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
735 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
736 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
738 if (hw->phy_type == SK_PHY_BCOM)
739 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
741 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
742 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
743 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
750 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
751 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
752 PHY_M_LED_MO_DUP(MO_LED_OFF) |
753 PHY_M_LED_MO_10(MO_LED_OFF) |
754 PHY_M_LED_MO_100(MO_LED_OFF) |
755 PHY_M_LED_MO_1000(MO_LED_OFF) |
756 PHY_M_LED_MO_RX(MO_LED_OFF));
759 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
760 PHY_M_LED_PULS_DUR(PULS_170MS) |
761 PHY_M_LED_BLINK_RT(BLINK_84MS) |
765 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
766 PHY_M_LED_MO_RX(MO_LED_OFF) |
767 (skge->speed == SPEED_100 ?
768 PHY_M_LED_MO_100(MO_LED_ON) : 0));
771 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
772 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
773 PHY_M_LED_MO_DUP(MO_LED_ON) |
774 PHY_M_LED_MO_10(MO_LED_ON) |
775 PHY_M_LED_MO_100(MO_LED_ON) |
776 PHY_M_LED_MO_1000(MO_LED_ON) |
777 PHY_M_LED_MO_RX(MO_LED_ON));
780 spin_unlock_bh(&hw->phy_lock);
783 /* blink LED's for finding board */
784 static int skge_phys_id(struct net_device *dev, u32 data)
786 struct skge_port *skge = netdev_priv(dev);
788 enum led_mode mode = LED_MODE_TST;
790 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
791 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
796 skge_led(skge, mode);
797 mode ^= LED_MODE_TST;
799 if (msleep_interruptible(BLINK_MS))
804 /* back to regular LED state */
805 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
810 static int skge_get_eeprom_len(struct net_device *dev)
812 struct skge_port *skge = netdev_priv(dev);
815 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
816 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
819 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
823 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
826 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
827 } while (!(offset & PCI_VPD_ADDR_F));
829 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
833 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
835 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
836 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
837 offset | PCI_VPD_ADDR_F);
840 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
841 } while (offset & PCI_VPD_ADDR_F);
844 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
847 struct skge_port *skge = netdev_priv(dev);
848 struct pci_dev *pdev = skge->hw->pdev;
849 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
850 int length = eeprom->len;
851 u16 offset = eeprom->offset;
856 eeprom->magic = SKGE_EEPROM_MAGIC;
859 u32 val = skge_vpd_read(pdev, cap, offset);
860 int n = min_t(int, length, sizeof(val));
862 memcpy(data, &val, n);
870 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
873 struct skge_port *skge = netdev_priv(dev);
874 struct pci_dev *pdev = skge->hw->pdev;
875 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
876 int length = eeprom->len;
877 u16 offset = eeprom->offset;
882 if (eeprom->magic != SKGE_EEPROM_MAGIC)
887 int n = min_t(int, length, sizeof(val));
890 val = skge_vpd_read(pdev, cap, offset);
891 memcpy(&val, data, n);
893 skge_vpd_write(pdev, cap, offset, val);
902 static const struct ethtool_ops skge_ethtool_ops = {
903 .get_settings = skge_get_settings,
904 .set_settings = skge_set_settings,
905 .get_drvinfo = skge_get_drvinfo,
906 .get_regs_len = skge_get_regs_len,
907 .get_regs = skge_get_regs,
908 .get_wol = skge_get_wol,
909 .set_wol = skge_set_wol,
910 .get_msglevel = skge_get_msglevel,
911 .set_msglevel = skge_set_msglevel,
912 .nway_reset = skge_nway_reset,
913 .get_link = ethtool_op_get_link,
914 .get_eeprom_len = skge_get_eeprom_len,
915 .get_eeprom = skge_get_eeprom,
916 .set_eeprom = skge_set_eeprom,
917 .get_ringparam = skge_get_ring_param,
918 .set_ringparam = skge_set_ring_param,
919 .get_pauseparam = skge_get_pauseparam,
920 .set_pauseparam = skge_set_pauseparam,
921 .get_coalesce = skge_get_coalesce,
922 .set_coalesce = skge_set_coalesce,
923 .set_sg = skge_set_sg,
924 .set_tx_csum = skge_set_tx_csum,
925 .get_rx_csum = skge_get_rx_csum,
926 .set_rx_csum = skge_set_rx_csum,
927 .get_strings = skge_get_strings,
928 .phys_id = skge_phys_id,
929 .get_sset_count = skge_get_sset_count,
930 .get_ethtool_stats = skge_get_ethtool_stats,
934 * Allocate ring elements and chain them together
935 * One-to-one association of board descriptors with ring elements
937 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
939 struct skge_tx_desc *d;
940 struct skge_element *e;
943 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
947 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
949 if (i == ring->count - 1) {
950 e->next = ring->start;
951 d->next_offset = base;
954 d->next_offset = base + (i+1) * sizeof(*d);
957 ring->to_use = ring->to_clean = ring->start;
962 /* Allocate and setup a new buffer for receiving */
963 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
964 struct sk_buff *skb, unsigned int bufsize)
966 struct skge_rx_desc *rd = e->desc;
969 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
973 rd->dma_hi = map >> 32;
975 rd->csum1_start = ETH_HLEN;
976 rd->csum2_start = ETH_HLEN;
982 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
983 pci_unmap_addr_set(e, mapaddr, map);
984 pci_unmap_len_set(e, maplen, bufsize);
987 /* Resume receiving using existing skb,
988 * Note: DMA address is not changed by chip.
989 * MTU not changed while receiver active.
991 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
993 struct skge_rx_desc *rd = e->desc;
996 rd->csum2_start = ETH_HLEN;
1000 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
1004 /* Free all buffers in receive ring, assumes receiver stopped */
1005 static void skge_rx_clean(struct skge_port *skge)
1007 struct skge_hw *hw = skge->hw;
1008 struct skge_ring *ring = &skge->rx_ring;
1009 struct skge_element *e;
1013 struct skge_rx_desc *rd = e->desc;
1016 pci_unmap_single(hw->pdev,
1017 pci_unmap_addr(e, mapaddr),
1018 pci_unmap_len(e, maplen),
1019 PCI_DMA_FROMDEVICE);
1020 dev_kfree_skb(e->skb);
1023 } while ((e = e->next) != ring->start);
1027 /* Allocate buffers for receive ring
1028 * For receive: to_clean is next received frame.
1030 static int skge_rx_fill(struct net_device *dev)
1032 struct skge_port *skge = netdev_priv(dev);
1033 struct skge_ring *ring = &skge->rx_ring;
1034 struct skge_element *e;
1038 struct sk_buff *skb;
1040 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1045 skb_reserve(skb, NET_IP_ALIGN);
1046 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1047 } while ( (e = e->next) != ring->start);
1049 ring->to_clean = ring->start;
1053 static const char *skge_pause(enum pause_status status)
1056 case FLOW_STAT_NONE:
1058 case FLOW_STAT_REM_SEND:
1060 case FLOW_STAT_LOC_SEND:
1062 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1065 return "indeterminated";
1070 static void skge_link_up(struct skge_port *skge)
1072 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1073 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1075 netif_carrier_on(skge->netdev);
1076 netif_wake_queue(skge->netdev);
1078 netif_info(skge, link, skge->netdev,
1079 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1081 skge->duplex == DUPLEX_FULL ? "full" : "half",
1082 skge_pause(skge->flow_status));
1085 static void skge_link_down(struct skge_port *skge)
1087 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1088 netif_carrier_off(skge->netdev);
1089 netif_stop_queue(skge->netdev);
1091 netif_info(skge, link, skge->netdev, "Link is down\n");
1095 static void xm_link_down(struct skge_hw *hw, int port)
1097 struct net_device *dev = hw->dev[port];
1098 struct skge_port *skge = netdev_priv(dev);
1100 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1102 if (netif_carrier_ok(dev))
1103 skge_link_down(skge);
1106 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1110 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1111 *val = xm_read16(hw, port, XM_PHY_DATA);
1113 if (hw->phy_type == SK_PHY_XMAC)
1116 for (i = 0; i < PHY_RETRIES; i++) {
1117 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1124 *val = xm_read16(hw, port, XM_PHY_DATA);
1129 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1132 if (__xm_phy_read(hw, port, reg, &v))
1133 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
1137 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1141 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1142 for (i = 0; i < PHY_RETRIES; i++) {
1143 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1150 xm_write16(hw, port, XM_PHY_DATA, val);
1151 for (i = 0; i < PHY_RETRIES; i++) {
1152 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1159 static void genesis_init(struct skge_hw *hw)
1161 /* set blink source counter */
1162 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1163 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1165 /* configure mac arbiter */
1166 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1168 /* configure mac arbiter timeout values */
1169 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1170 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1171 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1172 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1174 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1175 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1176 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1177 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1179 /* configure packet arbiter timeout */
1180 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1181 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1182 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1183 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1184 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1187 static void genesis_reset(struct skge_hw *hw, int port)
1189 const u8 zero[8] = { 0 };
1192 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1194 /* reset the statistics module */
1195 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1196 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1197 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1198 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1199 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1201 /* disable Broadcom PHY IRQ */
1202 if (hw->phy_type == SK_PHY_BCOM)
1203 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1205 xm_outhash(hw, port, XM_HSM, zero);
1207 /* Flush TX and RX fifo */
1208 reg = xm_read32(hw, port, XM_MODE);
1209 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1210 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1214 /* Convert mode to MII values */
1215 static const u16 phy_pause_map[] = {
1216 [FLOW_MODE_NONE] = 0,
1217 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1218 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1219 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1222 /* special defines for FIBER (88E1011S only) */
1223 static const u16 fiber_pause_map[] = {
1224 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1225 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1226 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1227 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1231 /* Check status of Broadcom phy link */
1232 static void bcom_check_link(struct skge_hw *hw, int port)
1234 struct net_device *dev = hw->dev[port];
1235 struct skge_port *skge = netdev_priv(dev);
1238 /* read twice because of latch */
1239 xm_phy_read(hw, port, PHY_BCOM_STAT);
1240 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1242 if ((status & PHY_ST_LSYNC) == 0) {
1243 xm_link_down(hw, port);
1247 if (skge->autoneg == AUTONEG_ENABLE) {
1250 if (!(status & PHY_ST_AN_OVER))
1253 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1254 if (lpa & PHY_B_AN_RF) {
1255 netdev_notice(dev, "remote fault\n");
1259 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1261 /* Check Duplex mismatch */
1262 switch (aux & PHY_B_AS_AN_RES_MSK) {
1263 case PHY_B_RES_1000FD:
1264 skge->duplex = DUPLEX_FULL;
1266 case PHY_B_RES_1000HD:
1267 skge->duplex = DUPLEX_HALF;
1270 netdev_notice(dev, "duplex mismatch\n");
1274 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1275 switch (aux & PHY_B_AS_PAUSE_MSK) {
1276 case PHY_B_AS_PAUSE_MSK:
1277 skge->flow_status = FLOW_STAT_SYMMETRIC;
1280 skge->flow_status = FLOW_STAT_REM_SEND;
1283 skge->flow_status = FLOW_STAT_LOC_SEND;
1286 skge->flow_status = FLOW_STAT_NONE;
1288 skge->speed = SPEED_1000;
1291 if (!netif_carrier_ok(dev))
1292 genesis_link_up(skge);
1295 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1296 * Phy on for 100 or 10Mbit operation
1298 static void bcom_phy_init(struct skge_port *skge)
1300 struct skge_hw *hw = skge->hw;
1301 int port = skge->port;
1303 u16 id1, r, ext, ctl;
1305 /* magic workaround patterns for Broadcom */
1306 static const struct {
1310 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1311 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1312 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1313 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1315 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1316 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1319 /* read Id from external PHY (all have the same address) */
1320 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1322 /* Optimize MDIO transfer by suppressing preamble. */
1323 r = xm_read16(hw, port, XM_MMU_CMD);
1325 xm_write16(hw, port, XM_MMU_CMD,r);
1328 case PHY_BCOM_ID1_C0:
1330 * Workaround BCOM Errata for the C0 type.
1331 * Write magic patterns to reserved registers.
1333 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1334 xm_phy_write(hw, port,
1335 C0hack[i].reg, C0hack[i].val);
1338 case PHY_BCOM_ID1_A1:
1340 * Workaround BCOM Errata for the A1 type.
1341 * Write magic patterns to reserved registers.
1343 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1344 xm_phy_write(hw, port,
1345 A1hack[i].reg, A1hack[i].val);
1350 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1351 * Disable Power Management after reset.
1353 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1354 r |= PHY_B_AC_DIS_PM;
1355 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1358 xm_read16(hw, port, XM_ISRC);
1360 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1361 ctl = PHY_CT_SP1000; /* always 1000mbit */
1363 if (skge->autoneg == AUTONEG_ENABLE) {
1365 * Workaround BCOM Errata #1 for the C5 type.
1366 * 1000Base-T Link Acquisition Failure in Slave Mode
1367 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1369 u16 adv = PHY_B_1000C_RD;
1370 if (skge->advertising & ADVERTISED_1000baseT_Half)
1371 adv |= PHY_B_1000C_AHD;
1372 if (skge->advertising & ADVERTISED_1000baseT_Full)
1373 adv |= PHY_B_1000C_AFD;
1374 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1376 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1378 if (skge->duplex == DUPLEX_FULL)
1379 ctl |= PHY_CT_DUP_MD;
1380 /* Force to slave */
1381 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1384 /* Set autonegotiation pause parameters */
1385 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1386 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1388 /* Handle Jumbo frames */
1389 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1390 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1391 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1393 ext |= PHY_B_PEC_HIGH_LA;
1397 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1398 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1400 /* Use link status change interrupt */
1401 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1404 static void xm_phy_init(struct skge_port *skge)
1406 struct skge_hw *hw = skge->hw;
1407 int port = skge->port;
1410 if (skge->autoneg == AUTONEG_ENABLE) {
1411 if (skge->advertising & ADVERTISED_1000baseT_Half)
1412 ctrl |= PHY_X_AN_HD;
1413 if (skge->advertising & ADVERTISED_1000baseT_Full)
1414 ctrl |= PHY_X_AN_FD;
1416 ctrl |= fiber_pause_map[skge->flow_control];
1418 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1420 /* Restart Auto-negotiation */
1421 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1423 /* Set DuplexMode in Config register */
1424 if (skge->duplex == DUPLEX_FULL)
1425 ctrl |= PHY_CT_DUP_MD;
1427 * Do NOT enable Auto-negotiation here. This would hold
1428 * the link down because no IDLEs are transmitted
1432 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1434 /* Poll PHY for status changes */
1435 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1438 static int xm_check_link(struct net_device *dev)
1440 struct skge_port *skge = netdev_priv(dev);
1441 struct skge_hw *hw = skge->hw;
1442 int port = skge->port;
1445 /* read twice because of latch */
1446 xm_phy_read(hw, port, PHY_XMAC_STAT);
1447 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1449 if ((status & PHY_ST_LSYNC) == 0) {
1450 xm_link_down(hw, port);
1454 if (skge->autoneg == AUTONEG_ENABLE) {
1457 if (!(status & PHY_ST_AN_OVER))
1460 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1461 if (lpa & PHY_B_AN_RF) {
1462 netdev_notice(dev, "remote fault\n");
1466 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1468 /* Check Duplex mismatch */
1469 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1471 skge->duplex = DUPLEX_FULL;
1474 skge->duplex = DUPLEX_HALF;
1477 netdev_notice(dev, "duplex mismatch\n");
1481 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1482 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1483 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1484 (lpa & PHY_X_P_SYM_MD))
1485 skge->flow_status = FLOW_STAT_SYMMETRIC;
1486 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1487 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1488 /* Enable PAUSE receive, disable PAUSE transmit */
1489 skge->flow_status = FLOW_STAT_REM_SEND;
1490 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1491 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1492 /* Disable PAUSE receive, enable PAUSE transmit */
1493 skge->flow_status = FLOW_STAT_LOC_SEND;
1495 skge->flow_status = FLOW_STAT_NONE;
1497 skge->speed = SPEED_1000;
1500 if (!netif_carrier_ok(dev))
1501 genesis_link_up(skge);
1505 /* Poll to check for link coming up.
1507 * Since internal PHY is wired to a level triggered pin, can't
1508 * get an interrupt when carrier is detected, need to poll for
1511 static void xm_link_timer(unsigned long arg)
1513 struct skge_port *skge = (struct skge_port *) arg;
1514 struct net_device *dev = skge->netdev;
1515 struct skge_hw *hw = skge->hw;
1516 int port = skge->port;
1518 unsigned long flags;
1520 if (!netif_running(dev))
1523 spin_lock_irqsave(&hw->phy_lock, flags);
1526 * Verify that the link by checking GPIO register three times.
1527 * This pin has the signal from the link_sync pin connected to it.
1529 for (i = 0; i < 3; i++) {
1530 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1534 /* Re-enable interrupt to detect link down */
1535 if (xm_check_link(dev)) {
1536 u16 msk = xm_read16(hw, port, XM_IMSK);
1537 msk &= ~XM_IS_INP_ASS;
1538 xm_write16(hw, port, XM_IMSK, msk);
1539 xm_read16(hw, port, XM_ISRC);
1542 mod_timer(&skge->link_timer,
1543 round_jiffies(jiffies + LINK_HZ));
1545 spin_unlock_irqrestore(&hw->phy_lock, flags);
1548 static void genesis_mac_init(struct skge_hw *hw, int port)
1550 struct net_device *dev = hw->dev[port];
1551 struct skge_port *skge = netdev_priv(dev);
1552 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1555 const u8 zero[6] = { 0 };
1557 for (i = 0; i < 10; i++) {
1558 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1560 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1565 netdev_warn(dev, "genesis reset failed\n");
1568 /* Unreset the XMAC. */
1569 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1572 * Perform additional initialization for external PHYs,
1573 * namely for the 1000baseTX cards that use the XMAC's
1576 if (hw->phy_type != SK_PHY_XMAC) {
1577 /* Take external Phy out of reset */
1578 r = skge_read32(hw, B2_GP_IO);
1580 r |= GP_DIR_0|GP_IO_0;
1582 r |= GP_DIR_2|GP_IO_2;
1584 skge_write32(hw, B2_GP_IO, r);
1586 /* Enable GMII interface */
1587 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1591 switch(hw->phy_type) {
1596 bcom_phy_init(skge);
1597 bcom_check_link(hw, port);
1600 /* Set Station Address */
1601 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1603 /* We don't use match addresses so clear */
1604 for (i = 1; i < 16; i++)
1605 xm_outaddr(hw, port, XM_EXM(i), zero);
1607 /* Clear MIB counters */
1608 xm_write16(hw, port, XM_STAT_CMD,
1609 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1610 /* Clear two times according to Errata #3 */
1611 xm_write16(hw, port, XM_STAT_CMD,
1612 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1614 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1615 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1617 /* We don't need the FCS appended to the packet. */
1618 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1620 r |= XM_RX_BIG_PK_OK;
1622 if (skge->duplex == DUPLEX_HALF) {
1624 * If in manual half duplex mode the other side might be in
1625 * full duplex mode, so ignore if a carrier extension is not seen
1626 * on frames received
1628 r |= XM_RX_DIS_CEXT;
1630 xm_write16(hw, port, XM_RX_CMD, r);
1632 /* We want short frames padded to 60 bytes. */
1633 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1635 /* Increase threshold for jumbo frames on dual port */
1636 if (hw->ports > 1 && jumbo)
1637 xm_write16(hw, port, XM_TX_THR, 1020);
1639 xm_write16(hw, port, XM_TX_THR, 512);
1642 * Enable the reception of all error frames. This is is
1643 * a necessary evil due to the design of the XMAC. The
1644 * XMAC's receive FIFO is only 8K in size, however jumbo
1645 * frames can be up to 9000 bytes in length. When bad
1646 * frame filtering is enabled, the XMAC's RX FIFO operates
1647 * in 'store and forward' mode. For this to work, the
1648 * entire frame has to fit into the FIFO, but that means
1649 * that jumbo frames larger than 8192 bytes will be
1650 * truncated. Disabling all bad frame filtering causes
1651 * the RX FIFO to operate in streaming mode, in which
1652 * case the XMAC will start transferring frames out of the
1653 * RX FIFO as soon as the FIFO threshold is reached.
1655 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1659 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1660 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1661 * and 'Octets Rx OK Hi Cnt Ov'.
1663 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1666 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1667 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1668 * and 'Octets Tx OK Hi Cnt Ov'.
1670 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1672 /* Configure MAC arbiter */
1673 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1675 /* configure timeout values */
1676 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1677 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1678 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1679 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1681 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1682 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1683 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1684 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1686 /* Configure Rx MAC FIFO */
1687 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1688 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1689 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1691 /* Configure Tx MAC FIFO */
1692 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1693 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1694 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1697 /* Enable frame flushing if jumbo frames used */
1698 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1700 /* enable timeout timers if normal frames */
1701 skge_write16(hw, B3_PA_CTRL,
1702 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1706 static void genesis_stop(struct skge_port *skge)
1708 struct skge_hw *hw = skge->hw;
1709 int port = skge->port;
1710 unsigned retries = 1000;
1713 /* Disable Tx and Rx */
1714 cmd = xm_read16(hw, port, XM_MMU_CMD);
1715 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1716 xm_write16(hw, port, XM_MMU_CMD, cmd);
1718 genesis_reset(hw, port);
1720 /* Clear Tx packet arbiter timeout IRQ */
1721 skge_write16(hw, B3_PA_CTRL,
1722 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1725 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1727 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1728 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1730 } while (--retries > 0);
1732 /* For external PHYs there must be special handling */
1733 if (hw->phy_type != SK_PHY_XMAC) {
1734 u32 reg = skge_read32(hw, B2_GP_IO);
1742 skge_write32(hw, B2_GP_IO, reg);
1743 skge_read32(hw, B2_GP_IO);
1746 xm_write16(hw, port, XM_MMU_CMD,
1747 xm_read16(hw, port, XM_MMU_CMD)
1748 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1750 xm_read16(hw, port, XM_MMU_CMD);
1754 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1756 struct skge_hw *hw = skge->hw;
1757 int port = skge->port;
1759 unsigned long timeout = jiffies + HZ;
1761 xm_write16(hw, port,
1762 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1764 /* wait for update to complete */
1765 while (xm_read16(hw, port, XM_STAT_CMD)
1766 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1767 if (time_after(jiffies, timeout))
1772 /* special case for 64 bit octet counter */
1773 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1774 | xm_read32(hw, port, XM_TXO_OK_LO);
1775 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1776 | xm_read32(hw, port, XM_RXO_OK_LO);
1778 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1779 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1782 static void genesis_mac_intr(struct skge_hw *hw, int port)
1784 struct net_device *dev = hw->dev[port];
1785 struct skge_port *skge = netdev_priv(dev);
1786 u16 status = xm_read16(hw, port, XM_ISRC);
1788 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1789 "mac interrupt status 0x%x\n", status);
1791 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1792 xm_link_down(hw, port);
1793 mod_timer(&skge->link_timer, jiffies + 1);
1796 if (status & XM_IS_TXF_UR) {
1797 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1798 ++dev->stats.tx_fifo_errors;
1802 static void genesis_link_up(struct skge_port *skge)
1804 struct skge_hw *hw = skge->hw;
1805 int port = skge->port;
1809 cmd = xm_read16(hw, port, XM_MMU_CMD);
1812 * enabling pause frame reception is required for 1000BT
1813 * because the XMAC is not reset if the link is going down
1815 if (skge->flow_status == FLOW_STAT_NONE ||
1816 skge->flow_status == FLOW_STAT_LOC_SEND)
1817 /* Disable Pause Frame Reception */
1818 cmd |= XM_MMU_IGN_PF;
1820 /* Enable Pause Frame Reception */
1821 cmd &= ~XM_MMU_IGN_PF;
1823 xm_write16(hw, port, XM_MMU_CMD, cmd);
1825 mode = xm_read32(hw, port, XM_MODE);
1826 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1827 skge->flow_status == FLOW_STAT_LOC_SEND) {
1829 * Configure Pause Frame Generation
1830 * Use internal and external Pause Frame Generation.
1831 * Sending pause frames is edge triggered.
1832 * Send a Pause frame with the maximum pause time if
1833 * internal oder external FIFO full condition occurs.
1834 * Send a zero pause time frame to re-start transmission.
1836 /* XM_PAUSE_DA = '010000C28001' (default) */
1837 /* XM_MAC_PTIME = 0xffff (maximum) */
1838 /* remember this value is defined in big endian (!) */
1839 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1841 mode |= XM_PAUSE_MODE;
1842 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1845 * disable pause frame generation is required for 1000BT
1846 * because the XMAC is not reset if the link is going down
1848 /* Disable Pause Mode in Mode Register */
1849 mode &= ~XM_PAUSE_MODE;
1851 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1854 xm_write32(hw, port, XM_MODE, mode);
1856 /* Turn on detection of Tx underrun */
1857 msk = xm_read16(hw, port, XM_IMSK);
1858 msk &= ~XM_IS_TXF_UR;
1859 xm_write16(hw, port, XM_IMSK, msk);
1861 xm_read16(hw, port, XM_ISRC);
1863 /* get MMU Command Reg. */
1864 cmd = xm_read16(hw, port, XM_MMU_CMD);
1865 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1866 cmd |= XM_MMU_GMII_FD;
1869 * Workaround BCOM Errata (#10523) for all BCom Phys
1870 * Enable Power Management after link up
1872 if (hw->phy_type == SK_PHY_BCOM) {
1873 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1874 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1875 & ~PHY_B_AC_DIS_PM);
1876 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1880 xm_write16(hw, port, XM_MMU_CMD,
1881 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1886 static inline void bcom_phy_intr(struct skge_port *skge)
1888 struct skge_hw *hw = skge->hw;
1889 int port = skge->port;
1892 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1893 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1894 "phy interrupt status 0x%x\n", isrc);
1896 if (isrc & PHY_B_IS_PSE)
1897 pr_err("%s: uncorrectable pair swap error\n",
1898 hw->dev[port]->name);
1900 /* Workaround BCom Errata:
1901 * enable and disable loopback mode if "NO HCD" occurs.
1903 if (isrc & PHY_B_IS_NO_HDCL) {
1904 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1905 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1906 ctrl | PHY_CT_LOOP);
1907 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1908 ctrl & ~PHY_CT_LOOP);
1911 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1912 bcom_check_link(hw, port);
1916 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1920 gma_write16(hw, port, GM_SMI_DATA, val);
1921 gma_write16(hw, port, GM_SMI_CTRL,
1922 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1923 for (i = 0; i < PHY_RETRIES; i++) {
1926 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1930 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
1934 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1938 gma_write16(hw, port, GM_SMI_CTRL,
1939 GM_SMI_CT_PHY_AD(hw->phy_addr)
1940 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1942 for (i = 0; i < PHY_RETRIES; i++) {
1944 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1950 *val = gma_read16(hw, port, GM_SMI_DATA);
1954 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1957 if (__gm_phy_read(hw, port, reg, &v))
1958 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
1962 /* Marvell Phy Initialization */
1963 static void yukon_init(struct skge_hw *hw, int port)
1965 struct skge_port *skge = netdev_priv(hw->dev[port]);
1966 u16 ctrl, ct1000, adv;
1968 if (skge->autoneg == AUTONEG_ENABLE) {
1969 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1971 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1972 PHY_M_EC_MAC_S_MSK);
1973 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1975 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1977 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1980 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1981 if (skge->autoneg == AUTONEG_DISABLE)
1982 ctrl &= ~PHY_CT_ANE;
1984 ctrl |= PHY_CT_RESET;
1985 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1991 if (skge->autoneg == AUTONEG_ENABLE) {
1993 if (skge->advertising & ADVERTISED_1000baseT_Full)
1994 ct1000 |= PHY_M_1000C_AFD;
1995 if (skge->advertising & ADVERTISED_1000baseT_Half)
1996 ct1000 |= PHY_M_1000C_AHD;
1997 if (skge->advertising & ADVERTISED_100baseT_Full)
1998 adv |= PHY_M_AN_100_FD;
1999 if (skge->advertising & ADVERTISED_100baseT_Half)
2000 adv |= PHY_M_AN_100_HD;
2001 if (skge->advertising & ADVERTISED_10baseT_Full)
2002 adv |= PHY_M_AN_10_FD;
2003 if (skge->advertising & ADVERTISED_10baseT_Half)
2004 adv |= PHY_M_AN_10_HD;
2006 /* Set Flow-control capabilities */
2007 adv |= phy_pause_map[skge->flow_control];
2009 if (skge->advertising & ADVERTISED_1000baseT_Full)
2010 adv |= PHY_M_AN_1000X_AFD;
2011 if (skge->advertising & ADVERTISED_1000baseT_Half)
2012 adv |= PHY_M_AN_1000X_AHD;
2014 adv |= fiber_pause_map[skge->flow_control];
2017 /* Restart Auto-negotiation */
2018 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2020 /* forced speed/duplex settings */
2021 ct1000 = PHY_M_1000C_MSE;
2023 if (skge->duplex == DUPLEX_FULL)
2024 ctrl |= PHY_CT_DUP_MD;
2026 switch (skge->speed) {
2028 ctrl |= PHY_CT_SP1000;
2031 ctrl |= PHY_CT_SP100;
2035 ctrl |= PHY_CT_RESET;
2038 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2040 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2041 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2043 /* Enable phy interrupt on autonegotiation complete (or link up) */
2044 if (skge->autoneg == AUTONEG_ENABLE)
2045 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2047 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2050 static void yukon_reset(struct skge_hw *hw, int port)
2052 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2053 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2054 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2055 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2056 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2058 gma_write16(hw, port, GM_RX_CTRL,
2059 gma_read16(hw, port, GM_RX_CTRL)
2060 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2063 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2064 static int is_yukon_lite_a0(struct skge_hw *hw)
2069 if (hw->chip_id != CHIP_ID_YUKON)
2072 reg = skge_read32(hw, B2_FAR);
2073 skge_write8(hw, B2_FAR + 3, 0xff);
2074 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2075 skge_write32(hw, B2_FAR, reg);
2079 static void yukon_mac_init(struct skge_hw *hw, int port)
2081 struct skge_port *skge = netdev_priv(hw->dev[port]);
2084 const u8 *addr = hw->dev[port]->dev_addr;
2086 /* WA code for COMA mode -- set PHY reset */
2087 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2088 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2089 reg = skge_read32(hw, B2_GP_IO);
2090 reg |= GP_DIR_9 | GP_IO_9;
2091 skge_write32(hw, B2_GP_IO, reg);
2095 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2096 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2098 /* WA code for COMA mode -- clear PHY reset */
2099 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2100 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2101 reg = skge_read32(hw, B2_GP_IO);
2104 skge_write32(hw, B2_GP_IO, reg);
2107 /* Set hardware config mode */
2108 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2109 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2110 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2112 /* Clear GMC reset */
2113 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2114 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2115 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2117 if (skge->autoneg == AUTONEG_DISABLE) {
2118 reg = GM_GPCR_AU_ALL_DIS;
2119 gma_write16(hw, port, GM_GP_CTRL,
2120 gma_read16(hw, port, GM_GP_CTRL) | reg);
2122 switch (skge->speed) {
2124 reg &= ~GM_GPCR_SPEED_100;
2125 reg |= GM_GPCR_SPEED_1000;
2128 reg &= ~GM_GPCR_SPEED_1000;
2129 reg |= GM_GPCR_SPEED_100;
2132 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2136 if (skge->duplex == DUPLEX_FULL)
2137 reg |= GM_GPCR_DUP_FULL;
2139 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2141 switch (skge->flow_control) {
2142 case FLOW_MODE_NONE:
2143 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2144 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2146 case FLOW_MODE_LOC_SEND:
2147 /* disable Rx flow-control */
2148 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2150 case FLOW_MODE_SYMMETRIC:
2151 case FLOW_MODE_SYM_OR_REM:
2152 /* enable Tx & Rx flow-control */
2156 gma_write16(hw, port, GM_GP_CTRL, reg);
2157 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2159 yukon_init(hw, port);
2162 reg = gma_read16(hw, port, GM_PHY_ADDR);
2163 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2165 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2166 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2167 gma_write16(hw, port, GM_PHY_ADDR, reg);
2169 /* transmit control */
2170 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2172 /* receive control reg: unicast + multicast + no FCS */
2173 gma_write16(hw, port, GM_RX_CTRL,
2174 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2176 /* transmit flow control */
2177 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2179 /* transmit parameter */
2180 gma_write16(hw, port, GM_TX_PARAM,
2181 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2182 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2183 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2185 /* configure the Serial Mode Register */
2186 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2188 | IPG_DATA_VAL(IPG_DATA_DEF);
2190 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2191 reg |= GM_SMOD_JUMBO_ENA;
2193 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2195 /* physical address: used for pause frames */
2196 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2197 /* virtual address for data */
2198 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2200 /* enable interrupt mask for counter overflows */
2201 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2202 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2203 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2205 /* Initialize Mac Fifo */
2207 /* Configure Rx MAC FIFO */
2208 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2209 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2211 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2212 if (is_yukon_lite_a0(hw))
2213 reg &= ~GMF_RX_F_FL_ON;
2215 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2216 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2218 * because Pause Packet Truncation in GMAC is not working
2219 * we have to increase the Flush Threshold to 64 bytes
2220 * in order to flush pause packets in Rx FIFO on Yukon-1
2222 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2224 /* Configure Tx MAC FIFO */
2225 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2226 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2229 /* Go into power down mode */
2230 static void yukon_suspend(struct skge_hw *hw, int port)
2234 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2235 ctrl |= PHY_M_PC_POL_R_DIS;
2236 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2238 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2239 ctrl |= PHY_CT_RESET;
2240 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2242 /* switch IEEE compatible power down mode on */
2243 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2244 ctrl |= PHY_CT_PDOWN;
2245 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2248 static void yukon_stop(struct skge_port *skge)
2250 struct skge_hw *hw = skge->hw;
2251 int port = skge->port;
2253 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2254 yukon_reset(hw, port);
2256 gma_write16(hw, port, GM_GP_CTRL,
2257 gma_read16(hw, port, GM_GP_CTRL)
2258 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2259 gma_read16(hw, port, GM_GP_CTRL);
2261 yukon_suspend(hw, port);
2263 /* set GPHY Control reset */
2264 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2265 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2268 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2270 struct skge_hw *hw = skge->hw;
2271 int port = skge->port;
2274 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2275 | gma_read32(hw, port, GM_TXO_OK_LO);
2276 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2277 | gma_read32(hw, port, GM_RXO_OK_LO);
2279 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2280 data[i] = gma_read32(hw, port,
2281 skge_stats[i].gma_offset);
2284 static void yukon_mac_intr(struct skge_hw *hw, int port)
2286 struct net_device *dev = hw->dev[port];
2287 struct skge_port *skge = netdev_priv(dev);
2288 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2290 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2291 "mac interrupt status 0x%x\n", status);
2293 if (status & GM_IS_RX_FF_OR) {
2294 ++dev->stats.rx_fifo_errors;
2295 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2298 if (status & GM_IS_TX_FF_UR) {
2299 ++dev->stats.tx_fifo_errors;
2300 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2305 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2307 switch (aux & PHY_M_PS_SPEED_MSK) {
2308 case PHY_M_PS_SPEED_1000:
2310 case PHY_M_PS_SPEED_100:
2317 static void yukon_link_up(struct skge_port *skge)
2319 struct skge_hw *hw = skge->hw;
2320 int port = skge->port;
2323 /* Enable Transmit FIFO Underrun */
2324 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2326 reg = gma_read16(hw, port, GM_GP_CTRL);
2327 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2328 reg |= GM_GPCR_DUP_FULL;
2331 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2332 gma_write16(hw, port, GM_GP_CTRL, reg);
2334 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2338 static void yukon_link_down(struct skge_port *skge)
2340 struct skge_hw *hw = skge->hw;
2341 int port = skge->port;
2344 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2345 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2346 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2348 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2349 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2350 ctrl |= PHY_M_AN_ASP;
2351 /* restore Asymmetric Pause bit */
2352 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2355 skge_link_down(skge);
2357 yukon_init(hw, port);
2360 static void yukon_phy_intr(struct skge_port *skge)
2362 struct skge_hw *hw = skge->hw;
2363 int port = skge->port;
2364 const char *reason = NULL;
2365 u16 istatus, phystat;
2367 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2368 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2370 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2371 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2373 if (istatus & PHY_M_IS_AN_COMPL) {
2374 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2376 reason = "remote fault";
2380 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2381 reason = "master/slave fault";
2385 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2386 reason = "speed/duplex";
2390 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2391 ? DUPLEX_FULL : DUPLEX_HALF;
2392 skge->speed = yukon_speed(hw, phystat);
2394 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2395 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2396 case PHY_M_PS_PAUSE_MSK:
2397 skge->flow_status = FLOW_STAT_SYMMETRIC;
2399 case PHY_M_PS_RX_P_EN:
2400 skge->flow_status = FLOW_STAT_REM_SEND;
2402 case PHY_M_PS_TX_P_EN:
2403 skge->flow_status = FLOW_STAT_LOC_SEND;
2406 skge->flow_status = FLOW_STAT_NONE;
2409 if (skge->flow_status == FLOW_STAT_NONE ||
2410 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2411 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2413 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2414 yukon_link_up(skge);
2418 if (istatus & PHY_M_IS_LSP_CHANGE)
2419 skge->speed = yukon_speed(hw, phystat);
2421 if (istatus & PHY_M_IS_DUP_CHANGE)
2422 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2423 if (istatus & PHY_M_IS_LST_CHANGE) {
2424 if (phystat & PHY_M_PS_LINK_UP)
2425 yukon_link_up(skge);
2427 yukon_link_down(skge);
2431 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2433 /* XXX restart autonegotiation? */
2436 static void skge_phy_reset(struct skge_port *skge)
2438 struct skge_hw *hw = skge->hw;
2439 int port = skge->port;
2440 struct net_device *dev = hw->dev[port];
2442 netif_stop_queue(skge->netdev);
2443 netif_carrier_off(skge->netdev);
2445 spin_lock_bh(&hw->phy_lock);
2446 if (hw->chip_id == CHIP_ID_GENESIS) {
2447 genesis_reset(hw, port);
2448 genesis_mac_init(hw, port);
2450 yukon_reset(hw, port);
2451 yukon_init(hw, port);
2453 spin_unlock_bh(&hw->phy_lock);
2455 skge_set_multicast(dev);
2458 /* Basic MII support */
2459 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2461 struct mii_ioctl_data *data = if_mii(ifr);
2462 struct skge_port *skge = netdev_priv(dev);
2463 struct skge_hw *hw = skge->hw;
2464 int err = -EOPNOTSUPP;
2466 if (!netif_running(dev))
2467 return -ENODEV; /* Phy still in reset */
2471 data->phy_id = hw->phy_addr;
2476 spin_lock_bh(&hw->phy_lock);
2477 if (hw->chip_id == CHIP_ID_GENESIS)
2478 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2480 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2481 spin_unlock_bh(&hw->phy_lock);
2482 data->val_out = val;
2487 spin_lock_bh(&hw->phy_lock);
2488 if (hw->chip_id == CHIP_ID_GENESIS)
2489 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2492 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2494 spin_unlock_bh(&hw->phy_lock);
2500 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2506 end = start + len - 1;
2508 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2509 skge_write32(hw, RB_ADDR(q, RB_START), start);
2510 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2511 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2512 skge_write32(hw, RB_ADDR(q, RB_END), end);
2514 if (q == Q_R1 || q == Q_R2) {
2515 /* Set thresholds on receive queue's */
2516 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2518 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2521 /* Enable store & forward on Tx queue's because
2522 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2524 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2527 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2530 /* Setup Bus Memory Interface */
2531 static void skge_qset(struct skge_port *skge, u16 q,
2532 const struct skge_element *e)
2534 struct skge_hw *hw = skge->hw;
2535 u32 watermark = 0x600;
2536 u64 base = skge->dma + (e->desc - skge->mem);
2538 /* optimization to reduce window on 32bit/33mhz */
2539 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2542 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2543 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2544 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2545 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2548 static int skge_up(struct net_device *dev)
2550 struct skge_port *skge = netdev_priv(dev);
2551 struct skge_hw *hw = skge->hw;
2552 int port = skge->port;
2553 u32 chunk, ram_addr;
2554 size_t rx_size, tx_size;
2557 if (!is_valid_ether_addr(dev->dev_addr))
2560 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2562 if (dev->mtu > RX_BUF_SIZE)
2563 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2565 skge->rx_buf_size = RX_BUF_SIZE;
2568 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2569 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2570 skge->mem_size = tx_size + rx_size;
2571 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2575 BUG_ON(skge->dma & 7);
2577 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2578 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2583 memset(skge->mem, 0, skge->mem_size);
2585 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2589 err = skge_rx_fill(dev);
2593 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2594 skge->dma + rx_size);
2598 /* Initialize MAC */
2599 spin_lock_bh(&hw->phy_lock);
2600 if (hw->chip_id == CHIP_ID_GENESIS)
2601 genesis_mac_init(hw, port);
2603 yukon_mac_init(hw, port);
2604 spin_unlock_bh(&hw->phy_lock);
2606 /* Configure RAMbuffers - equally between ports and tx/rx */
2607 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2608 ram_addr = hw->ram_offset + 2 * chunk * port;
2610 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2611 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2613 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2614 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2615 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2617 /* Start receiver BMU */
2619 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2620 skge_led(skge, LED_MODE_ON);
2622 spin_lock_irq(&hw->hw_lock);
2623 hw->intr_mask |= portmask[port];
2624 skge_write32(hw, B0_IMSK, hw->intr_mask);
2625 spin_unlock_irq(&hw->hw_lock);
2627 napi_enable(&skge->napi);
2631 skge_rx_clean(skge);
2632 kfree(skge->rx_ring.start);
2634 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2641 static void skge_rx_stop(struct skge_hw *hw, int port)
2643 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2644 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2645 RB_RST_SET|RB_DIS_OP_MD);
2646 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2649 static int skge_down(struct net_device *dev)
2651 struct skge_port *skge = netdev_priv(dev);
2652 struct skge_hw *hw = skge->hw;
2653 int port = skge->port;
2655 if (skge->mem == NULL)
2658 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2660 netif_tx_disable(dev);
2662 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2663 del_timer_sync(&skge->link_timer);
2665 napi_disable(&skge->napi);
2666 netif_carrier_off(dev);
2668 spin_lock_irq(&hw->hw_lock);
2669 hw->intr_mask &= ~portmask[port];
2670 skge_write32(hw, B0_IMSK, hw->intr_mask);
2671 spin_unlock_irq(&hw->hw_lock);
2673 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2674 if (hw->chip_id == CHIP_ID_GENESIS)
2679 /* Stop transmitter */
2680 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2681 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2682 RB_RST_SET|RB_DIS_OP_MD);
2685 /* Disable Force Sync bit and Enable Alloc bit */
2686 skge_write8(hw, SK_REG(port, TXA_CTRL),
2687 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2689 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2690 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2691 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2693 /* Reset PCI FIFO */
2694 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2695 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2697 /* Reset the RAM Buffer async Tx queue */
2698 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2700 skge_rx_stop(hw, port);
2702 if (hw->chip_id == CHIP_ID_GENESIS) {
2703 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2704 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2706 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2707 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2710 skge_led(skge, LED_MODE_OFF);
2712 netif_tx_lock_bh(dev);
2714 netif_tx_unlock_bh(dev);
2716 skge_rx_clean(skge);
2718 kfree(skge->rx_ring.start);
2719 kfree(skge->tx_ring.start);
2720 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2725 static inline int skge_avail(const struct skge_ring *ring)
2728 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2729 + (ring->to_clean - ring->to_use) - 1;
2732 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2733 struct net_device *dev)
2735 struct skge_port *skge = netdev_priv(dev);
2736 struct skge_hw *hw = skge->hw;
2737 struct skge_element *e;
2738 struct skge_tx_desc *td;
2743 if (skb_padto(skb, ETH_ZLEN))
2744 return NETDEV_TX_OK;
2746 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2747 return NETDEV_TX_BUSY;
2749 e = skge->tx_ring.to_use;
2751 BUG_ON(td->control & BMU_OWN);
2753 len = skb_headlen(skb);
2754 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2755 pci_unmap_addr_set(e, mapaddr, map);
2756 pci_unmap_len_set(e, maplen, len);
2759 td->dma_hi = map >> 32;
2761 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2762 const int offset = skb_transport_offset(skb);
2764 /* This seems backwards, but it is what the sk98lin
2765 * does. Looks like hardware is wrong?
2767 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2768 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2769 control = BMU_TCP_CHECK;
2771 control = BMU_UDP_CHECK;
2774 td->csum_start = offset;
2775 td->csum_write = offset + skb->csum_offset;
2777 control = BMU_CHECK;
2779 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2780 control |= BMU_EOF| BMU_IRQ_EOF;
2782 struct skge_tx_desc *tf = td;
2784 control |= BMU_STFWD;
2785 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2786 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2788 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2789 frag->size, PCI_DMA_TODEVICE);
2794 BUG_ON(tf->control & BMU_OWN);
2797 tf->dma_hi = (u64) map >> 32;
2798 pci_unmap_addr_set(e, mapaddr, map);
2799 pci_unmap_len_set(e, maplen, frag->size);
2801 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2803 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2805 /* Make sure all the descriptors written */
2807 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2810 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2812 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2813 "tx queued, slot %td, len %d\n",
2814 e - skge->tx_ring.start, skb->len);
2816 skge->tx_ring.to_use = e->next;
2819 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2820 netdev_dbg(dev, "transmit queue full\n");
2821 netif_stop_queue(dev);
2824 return NETDEV_TX_OK;
2828 /* Free resources associated with this reing element */
2829 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2832 struct pci_dev *pdev = skge->hw->pdev;
2834 /* skb header vs. fragment */
2835 if (control & BMU_STF)
2836 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2837 pci_unmap_len(e, maplen),
2840 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2841 pci_unmap_len(e, maplen),
2844 if (control & BMU_EOF) {
2845 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2846 "tx done slot %td\n", e - skge->tx_ring.start);
2848 dev_kfree_skb(e->skb);
2852 /* Free all buffers in transmit ring */
2853 static void skge_tx_clean(struct net_device *dev)
2855 struct skge_port *skge = netdev_priv(dev);
2856 struct skge_element *e;
2858 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2859 struct skge_tx_desc *td = e->desc;
2860 skge_tx_free(skge, e, td->control);
2864 skge->tx_ring.to_clean = e;
2867 static void skge_tx_timeout(struct net_device *dev)
2869 struct skge_port *skge = netdev_priv(dev);
2871 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2873 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2875 netif_wake_queue(dev);
2878 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2882 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2885 if (!netif_running(dev)) {
2901 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2903 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2907 crc = ether_crc_le(ETH_ALEN, addr);
2909 filter[bit/8] |= 1 << (bit%8);
2912 static void genesis_set_multicast(struct net_device *dev)
2914 struct skge_port *skge = netdev_priv(dev);
2915 struct skge_hw *hw = skge->hw;
2916 int port = skge->port;
2917 int i, count = netdev_mc_count(dev);
2918 struct dev_mc_list *list = dev->mc_list;
2922 mode = xm_read32(hw, port, XM_MODE);
2923 mode |= XM_MD_ENA_HASH;
2924 if (dev->flags & IFF_PROMISC)
2925 mode |= XM_MD_ENA_PROM;
2927 mode &= ~XM_MD_ENA_PROM;
2929 if (dev->flags & IFF_ALLMULTI)
2930 memset(filter, 0xff, sizeof(filter));
2932 memset(filter, 0, sizeof(filter));
2934 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2935 skge->flow_status == FLOW_STAT_SYMMETRIC)
2936 genesis_add_filter(filter, pause_mc_addr);
2938 for (i = 0; list && i < count; i++, list = list->next)
2939 genesis_add_filter(filter, list->dmi_addr);
2942 xm_write32(hw, port, XM_MODE, mode);
2943 xm_outhash(hw, port, XM_HSM, filter);
2946 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2948 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2949 filter[bit/8] |= 1 << (bit%8);
2952 static void yukon_set_multicast(struct net_device *dev)
2954 struct skge_port *skge = netdev_priv(dev);
2955 struct skge_hw *hw = skge->hw;
2956 int port = skge->port;
2957 struct dev_mc_list *list = dev->mc_list;
2958 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2959 skge->flow_status == FLOW_STAT_SYMMETRIC);
2963 memset(filter, 0, sizeof(filter));
2965 reg = gma_read16(hw, port, GM_RX_CTRL);
2966 reg |= GM_RXCR_UCF_ENA;
2968 if (dev->flags & IFF_PROMISC) /* promiscuous */
2969 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2970 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2971 memset(filter, 0xff, sizeof(filter));
2972 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2973 reg &= ~GM_RXCR_MCF_ENA;
2976 reg |= GM_RXCR_MCF_ENA;
2979 yukon_add_filter(filter, pause_mc_addr);
2981 for (i = 0; list && i < netdev_mc_count(dev); i++, list = list->next)
2982 yukon_add_filter(filter, list->dmi_addr);
2986 gma_write16(hw, port, GM_MC_ADDR_H1,
2987 (u16)filter[0] | ((u16)filter[1] << 8));
2988 gma_write16(hw, port, GM_MC_ADDR_H2,
2989 (u16)filter[2] | ((u16)filter[3] << 8));
2990 gma_write16(hw, port, GM_MC_ADDR_H3,
2991 (u16)filter[4] | ((u16)filter[5] << 8));
2992 gma_write16(hw, port, GM_MC_ADDR_H4,
2993 (u16)filter[6] | ((u16)filter[7] << 8));
2995 gma_write16(hw, port, GM_RX_CTRL, reg);
2998 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3000 if (hw->chip_id == CHIP_ID_GENESIS)
3001 return status >> XMR_FS_LEN_SHIFT;
3003 return status >> GMR_FS_LEN_SHIFT;
3006 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3008 if (hw->chip_id == CHIP_ID_GENESIS)
3009 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3011 return (status & GMR_FS_ANY_ERR) ||
3012 (status & GMR_FS_RX_OK) == 0;
3015 static void skge_set_multicast(struct net_device *dev)
3017 struct skge_port *skge = netdev_priv(dev);
3018 struct skge_hw *hw = skge->hw;
3020 if (hw->chip_id == CHIP_ID_GENESIS)
3021 genesis_set_multicast(dev);
3023 yukon_set_multicast(dev);
3028 /* Get receive buffer from descriptor.
3029 * Handles copy of small buffers and reallocation failures
3031 static struct sk_buff *skge_rx_get(struct net_device *dev,
3032 struct skge_element *e,
3033 u32 control, u32 status, u16 csum)
3035 struct skge_port *skge = netdev_priv(dev);
3036 struct sk_buff *skb;
3037 u16 len = control & BMU_BBC;
3039 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3040 "rx slot %td status 0x%x len %d\n",
3041 e - skge->rx_ring.start, status, len);
3043 if (len > skge->rx_buf_size)
3046 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3049 if (bad_phy_status(skge->hw, status))
3052 if (phy_length(skge->hw, status) != len)
3055 if (len < RX_COPY_THRESHOLD) {
3056 skb = netdev_alloc_skb_ip_align(dev, len);
3060 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3061 pci_unmap_addr(e, mapaddr),
3062 len, PCI_DMA_FROMDEVICE);
3063 skb_copy_from_linear_data(e->skb, skb->data, len);
3064 pci_dma_sync_single_for_device(skge->hw->pdev,
3065 pci_unmap_addr(e, mapaddr),
3066 len, PCI_DMA_FROMDEVICE);
3067 skge_rx_reuse(e, skge->rx_buf_size);
3069 struct sk_buff *nskb;
3071 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3075 pci_unmap_single(skge->hw->pdev,
3076 pci_unmap_addr(e, mapaddr),
3077 pci_unmap_len(e, maplen),
3078 PCI_DMA_FROMDEVICE);
3080 prefetch(skb->data);
3081 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3085 if (skge->rx_csum) {
3087 skb->ip_summed = CHECKSUM_COMPLETE;
3090 skb->protocol = eth_type_trans(skb, dev);
3095 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3096 "rx err, slot %td control 0x%x status 0x%x\n",
3097 e - skge->rx_ring.start, control, status);
3099 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3100 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3101 dev->stats.rx_length_errors++;
3102 if (status & XMR_FS_FRA_ERR)
3103 dev->stats.rx_frame_errors++;
3104 if (status & XMR_FS_FCS_ERR)
3105 dev->stats.rx_crc_errors++;
3107 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3108 dev->stats.rx_length_errors++;
3109 if (status & GMR_FS_FRAGMENT)
3110 dev->stats.rx_frame_errors++;
3111 if (status & GMR_FS_CRC_ERR)
3112 dev->stats.rx_crc_errors++;
3116 skge_rx_reuse(e, skge->rx_buf_size);
3120 /* Free all buffers in Tx ring which are no longer owned by device */
3121 static void skge_tx_done(struct net_device *dev)
3123 struct skge_port *skge = netdev_priv(dev);
3124 struct skge_ring *ring = &skge->tx_ring;
3125 struct skge_element *e;
3127 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3129 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3130 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3132 if (control & BMU_OWN)
3135 skge_tx_free(skge, e, control);
3137 skge->tx_ring.to_clean = e;
3139 /* Can run lockless until we need to synchronize to restart queue. */
3142 if (unlikely(netif_queue_stopped(dev) &&
3143 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3145 if (unlikely(netif_queue_stopped(dev) &&
3146 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3147 netif_wake_queue(dev);
3150 netif_tx_unlock(dev);
3154 static int skge_poll(struct napi_struct *napi, int to_do)
3156 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3157 struct net_device *dev = skge->netdev;
3158 struct skge_hw *hw = skge->hw;
3159 struct skge_ring *ring = &skge->rx_ring;
3160 struct skge_element *e;
3165 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3167 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3168 struct skge_rx_desc *rd = e->desc;
3169 struct sk_buff *skb;
3173 control = rd->control;
3174 if (control & BMU_OWN)
3177 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3179 netif_receive_skb(skb);
3186 /* restart receiver */
3188 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3190 if (work_done < to_do) {
3191 unsigned long flags;
3193 spin_lock_irqsave(&hw->hw_lock, flags);
3194 __napi_complete(napi);
3195 hw->intr_mask |= napimask[skge->port];
3196 skge_write32(hw, B0_IMSK, hw->intr_mask);
3197 skge_read32(hw, B0_IMSK);
3198 spin_unlock_irqrestore(&hw->hw_lock, flags);
3204 /* Parity errors seem to happen when Genesis is connected to a switch
3205 * with no other ports present. Heartbeat error??
3207 static void skge_mac_parity(struct skge_hw *hw, int port)
3209 struct net_device *dev = hw->dev[port];
3211 ++dev->stats.tx_heartbeat_errors;
3213 if (hw->chip_id == CHIP_ID_GENESIS)
3214 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3217 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3218 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3219 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3220 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3223 static void skge_mac_intr(struct skge_hw *hw, int port)
3225 if (hw->chip_id == CHIP_ID_GENESIS)
3226 genesis_mac_intr(hw, port);
3228 yukon_mac_intr(hw, port);
3231 /* Handle device specific framing and timeout interrupts */
3232 static void skge_error_irq(struct skge_hw *hw)
3234 struct pci_dev *pdev = hw->pdev;
3235 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3237 if (hw->chip_id == CHIP_ID_GENESIS) {
3238 /* clear xmac errors */
3239 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3240 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3241 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3242 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3244 /* Timestamp (unused) overflow */
3245 if (hwstatus & IS_IRQ_TIST_OV)
3246 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3249 if (hwstatus & IS_RAM_RD_PAR) {
3250 dev_err(&pdev->dev, "Ram read data parity error\n");
3251 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3254 if (hwstatus & IS_RAM_WR_PAR) {
3255 dev_err(&pdev->dev, "Ram write data parity error\n");
3256 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3259 if (hwstatus & IS_M1_PAR_ERR)
3260 skge_mac_parity(hw, 0);
3262 if (hwstatus & IS_M2_PAR_ERR)
3263 skge_mac_parity(hw, 1);
3265 if (hwstatus & IS_R1_PAR_ERR) {
3266 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3268 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3271 if (hwstatus & IS_R2_PAR_ERR) {
3272 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3274 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3277 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3278 u16 pci_status, pci_cmd;
3280 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3281 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3283 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3284 pci_cmd, pci_status);
3286 /* Write the error bits back to clear them. */
3287 pci_status &= PCI_STATUS_ERROR_BITS;
3288 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3289 pci_write_config_word(pdev, PCI_COMMAND,
3290 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3291 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3292 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3294 /* if error still set then just ignore it */
3295 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3296 if (hwstatus & IS_IRQ_STAT) {
3297 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3298 hw->intr_mask &= ~IS_HW_ERR;
3304 * Interrupt from PHY are handled in tasklet (softirq)
3305 * because accessing phy registers requires spin wait which might
3306 * cause excess interrupt latency.
3308 static void skge_extirq(unsigned long arg)
3310 struct skge_hw *hw = (struct skge_hw *) arg;
3313 for (port = 0; port < hw->ports; port++) {
3314 struct net_device *dev = hw->dev[port];
3316 if (netif_running(dev)) {
3317 struct skge_port *skge = netdev_priv(dev);
3319 spin_lock(&hw->phy_lock);
3320 if (hw->chip_id != CHIP_ID_GENESIS)
3321 yukon_phy_intr(skge);
3322 else if (hw->phy_type == SK_PHY_BCOM)
3323 bcom_phy_intr(skge);
3324 spin_unlock(&hw->phy_lock);
3328 spin_lock_irq(&hw->hw_lock);
3329 hw->intr_mask |= IS_EXT_REG;
3330 skge_write32(hw, B0_IMSK, hw->intr_mask);
3331 skge_read32(hw, B0_IMSK);
3332 spin_unlock_irq(&hw->hw_lock);
3335 static irqreturn_t skge_intr(int irq, void *dev_id)
3337 struct skge_hw *hw = dev_id;
3341 spin_lock(&hw->hw_lock);
3342 /* Reading this register masks IRQ */
3343 status = skge_read32(hw, B0_SP_ISRC);
3344 if (status == 0 || status == ~0)
3348 status &= hw->intr_mask;
3349 if (status & IS_EXT_REG) {
3350 hw->intr_mask &= ~IS_EXT_REG;
3351 tasklet_schedule(&hw->phy_task);
3354 if (status & (IS_XA1_F|IS_R1_F)) {
3355 struct skge_port *skge = netdev_priv(hw->dev[0]);
3356 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3357 napi_schedule(&skge->napi);
3360 if (status & IS_PA_TO_TX1)
3361 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3363 if (status & IS_PA_TO_RX1) {
3364 ++hw->dev[0]->stats.rx_over_errors;
3365 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3369 if (status & IS_MAC1)
3370 skge_mac_intr(hw, 0);
3373 struct skge_port *skge = netdev_priv(hw->dev[1]);
3375 if (status & (IS_XA2_F|IS_R2_F)) {
3376 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3377 napi_schedule(&skge->napi);
3380 if (status & IS_PA_TO_RX2) {
3381 ++hw->dev[1]->stats.rx_over_errors;
3382 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3385 if (status & IS_PA_TO_TX2)
3386 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3388 if (status & IS_MAC2)
3389 skge_mac_intr(hw, 1);
3392 if (status & IS_HW_ERR)
3395 skge_write32(hw, B0_IMSK, hw->intr_mask);
3396 skge_read32(hw, B0_IMSK);
3398 spin_unlock(&hw->hw_lock);
3400 return IRQ_RETVAL(handled);
3403 #ifdef CONFIG_NET_POLL_CONTROLLER
3404 static void skge_netpoll(struct net_device *dev)
3406 struct skge_port *skge = netdev_priv(dev);
3408 disable_irq(dev->irq);
3409 skge_intr(dev->irq, skge->hw);
3410 enable_irq(dev->irq);
3414 static int skge_set_mac_address(struct net_device *dev, void *p)
3416 struct skge_port *skge = netdev_priv(dev);
3417 struct skge_hw *hw = skge->hw;
3418 unsigned port = skge->port;
3419 const struct sockaddr *addr = p;
3422 if (!is_valid_ether_addr(addr->sa_data))
3423 return -EADDRNOTAVAIL;
3425 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3427 if (!netif_running(dev)) {
3428 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3429 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3432 spin_lock_bh(&hw->phy_lock);
3433 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3434 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3436 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3437 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3439 if (hw->chip_id == CHIP_ID_GENESIS)
3440 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3442 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3443 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3446 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3447 spin_unlock_bh(&hw->phy_lock);
3453 static const struct {
3457 { CHIP_ID_GENESIS, "Genesis" },
3458 { CHIP_ID_YUKON, "Yukon" },
3459 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3460 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3463 static const char *skge_board_name(const struct skge_hw *hw)
3466 static char buf[16];
3468 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3469 if (skge_chips[i].id == hw->chip_id)
3470 return skge_chips[i].name;
3472 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3478 * Setup the board data structure, but don't bring up
3481 static int skge_reset(struct skge_hw *hw)
3484 u16 ctst, pci_status;
3485 u8 t8, mac_cfg, pmd_type;
3488 ctst = skge_read16(hw, B0_CTST);
3491 skge_write8(hw, B0_CTST, CS_RST_SET);
3492 skge_write8(hw, B0_CTST, CS_RST_CLR);
3494 /* clear PCI errors, if any */
3495 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3496 skge_write8(hw, B2_TST_CTRL2, 0);
3498 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3499 pci_write_config_word(hw->pdev, PCI_STATUS,
3500 pci_status | PCI_STATUS_ERROR_BITS);
3501 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3502 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3504 /* restore CLK_RUN bits (for Yukon-Lite) */
3505 skge_write16(hw, B0_CTST,
3506 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3508 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3509 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3510 pmd_type = skge_read8(hw, B2_PMD_TYP);
3511 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3513 switch (hw->chip_id) {
3514 case CHIP_ID_GENESIS:
3515 switch (hw->phy_type) {
3517 hw->phy_addr = PHY_ADDR_XMAC;
3520 hw->phy_addr = PHY_ADDR_BCOM;
3523 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3530 case CHIP_ID_YUKON_LITE:
3531 case CHIP_ID_YUKON_LP:
3532 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3535 hw->phy_addr = PHY_ADDR_MARV;
3539 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3544 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3545 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3546 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3548 /* read the adapters RAM size */
3549 t8 = skge_read8(hw, B2_E_0);
3550 if (hw->chip_id == CHIP_ID_GENESIS) {
3552 /* special case: 4 x 64k x 36, offset = 0x80000 */
3553 hw->ram_size = 0x100000;
3554 hw->ram_offset = 0x80000;
3556 hw->ram_size = t8 * 512;
3559 hw->ram_size = 0x20000;
3561 hw->ram_size = t8 * 4096;
3563 hw->intr_mask = IS_HW_ERR;
3565 /* Use PHY IRQ for all but fiber based Genesis board */
3566 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3567 hw->intr_mask |= IS_EXT_REG;
3569 if (hw->chip_id == CHIP_ID_GENESIS)
3572 /* switch power to VCC (WA for VAUX problem) */
3573 skge_write8(hw, B0_POWER_CTRL,
3574 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3576 /* avoid boards with stuck Hardware error bits */
3577 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3578 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3579 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3580 hw->intr_mask &= ~IS_HW_ERR;
3583 /* Clear PHY COMA */
3584 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3585 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3586 reg &= ~PCI_PHY_COMA;
3587 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3588 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3591 for (i = 0; i < hw->ports; i++) {
3592 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3593 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3597 /* turn off hardware timer (unused) */
3598 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3599 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3600 skge_write8(hw, B0_LED, LED_STAT_ON);
3602 /* enable the Tx Arbiters */
3603 for (i = 0; i < hw->ports; i++)
3604 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3606 /* Initialize ram interface */
3607 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3609 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3610 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3611 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3612 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3613 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3614 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3615 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3616 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3617 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3618 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3619 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3620 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3622 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3624 /* Set interrupt moderation for Transmit only
3625 * Receive interrupts avoided by NAPI
3627 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3628 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3629 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3631 skge_write32(hw, B0_IMSK, hw->intr_mask);
3633 for (i = 0; i < hw->ports; i++) {
3634 if (hw->chip_id == CHIP_ID_GENESIS)
3635 genesis_reset(hw, i);
3644 #ifdef CONFIG_SKGE_DEBUG
3646 static struct dentry *skge_debug;
3648 static int skge_debug_show(struct seq_file *seq, void *v)
3650 struct net_device *dev = seq->private;
3651 const struct skge_port *skge = netdev_priv(dev);
3652 const struct skge_hw *hw = skge->hw;
3653 const struct skge_element *e;
3655 if (!netif_running(dev))
3658 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3659 skge_read32(hw, B0_IMSK));
3661 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3662 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3663 const struct skge_tx_desc *t = e->desc;
3664 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3665 t->control, t->dma_hi, t->dma_lo, t->status,
3666 t->csum_offs, t->csum_write, t->csum_start);
3669 seq_printf(seq, "\nRx Ring: \n");
3670 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3671 const struct skge_rx_desc *r = e->desc;
3673 if (r->control & BMU_OWN)
3676 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3677 r->control, r->dma_hi, r->dma_lo, r->status,
3678 r->timestamp, r->csum1, r->csum1_start);
3684 static int skge_debug_open(struct inode *inode, struct file *file)
3686 return single_open(file, skge_debug_show, inode->i_private);
3689 static const struct file_operations skge_debug_fops = {
3690 .owner = THIS_MODULE,
3691 .open = skge_debug_open,
3693 .llseek = seq_lseek,
3694 .release = single_release,
3698 * Use network device events to create/remove/rename
3699 * debugfs file entries
3701 static int skge_device_event(struct notifier_block *unused,
3702 unsigned long event, void *ptr)
3704 struct net_device *dev = ptr;
3705 struct skge_port *skge;
3708 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3711 skge = netdev_priv(dev);
3713 case NETDEV_CHANGENAME:
3714 if (skge->debugfs) {
3715 d = debugfs_rename(skge_debug, skge->debugfs,
3716 skge_debug, dev->name);
3720 netdev_info(dev, "rename failed\n");
3721 debugfs_remove(skge->debugfs);
3726 case NETDEV_GOING_DOWN:
3727 if (skge->debugfs) {
3728 debugfs_remove(skge->debugfs);
3729 skge->debugfs = NULL;
3734 d = debugfs_create_file(dev->name, S_IRUGO,
3737 if (!d || IS_ERR(d))
3738 netdev_info(dev, "debugfs create failed\n");
3748 static struct notifier_block skge_notifier = {
3749 .notifier_call = skge_device_event,
3753 static __init void skge_debug_init(void)
3757 ent = debugfs_create_dir("skge", NULL);
3758 if (!ent || IS_ERR(ent)) {
3759 pr_info("debugfs create directory failed\n");
3764 register_netdevice_notifier(&skge_notifier);
3767 static __exit void skge_debug_cleanup(void)
3770 unregister_netdevice_notifier(&skge_notifier);
3771 debugfs_remove(skge_debug);
3777 #define skge_debug_init()
3778 #define skge_debug_cleanup()
3781 static const struct net_device_ops skge_netdev_ops = {
3782 .ndo_open = skge_up,
3783 .ndo_stop = skge_down,
3784 .ndo_start_xmit = skge_xmit_frame,
3785 .ndo_do_ioctl = skge_ioctl,
3786 .ndo_get_stats = skge_get_stats,
3787 .ndo_tx_timeout = skge_tx_timeout,
3788 .ndo_change_mtu = skge_change_mtu,
3789 .ndo_validate_addr = eth_validate_addr,
3790 .ndo_set_multicast_list = skge_set_multicast,
3791 .ndo_set_mac_address = skge_set_mac_address,
3792 #ifdef CONFIG_NET_POLL_CONTROLLER
3793 .ndo_poll_controller = skge_netpoll,
3798 /* Initialize network device */
3799 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3802 struct skge_port *skge;
3803 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3806 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3810 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3811 dev->netdev_ops = &skge_netdev_ops;
3812 dev->ethtool_ops = &skge_ethtool_ops;
3813 dev->watchdog_timeo = TX_WATCHDOG;
3814 dev->irq = hw->pdev->irq;
3817 dev->features |= NETIF_F_HIGHDMA;
3819 skge = netdev_priv(dev);
3820 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3823 skge->msg_enable = netif_msg_init(debug, default_msg);
3825 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3826 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3828 /* Auto speed and flow control */
3829 skge->autoneg = AUTONEG_ENABLE;
3830 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3833 skge->advertising = skge_supported_modes(hw);
3835 if (device_can_wakeup(&hw->pdev->dev)) {
3836 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3837 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3840 hw->dev[port] = dev;
3844 /* Only used for Genesis XMAC */
3845 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3847 if (hw->chip_id != CHIP_ID_GENESIS) {
3848 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3852 /* read the mac address */
3853 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3854 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3856 /* device is off until link detection */
3857 netif_carrier_off(dev);
3858 netif_stop_queue(dev);
3863 static void __devinit skge_show_addr(struct net_device *dev)
3865 const struct skge_port *skge = netdev_priv(dev);
3867 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3870 static int __devinit skge_probe(struct pci_dev *pdev,
3871 const struct pci_device_id *ent)
3873 struct net_device *dev, *dev1;
3875 int err, using_dac = 0;
3877 err = pci_enable_device(pdev);
3879 dev_err(&pdev->dev, "cannot enable PCI device\n");
3883 err = pci_request_regions(pdev, DRV_NAME);
3885 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3886 goto err_out_disable_pdev;
3889 pci_set_master(pdev);
3891 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3893 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3894 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3896 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3900 dev_err(&pdev->dev, "no usable DMA configuration\n");
3901 goto err_out_free_regions;
3905 /* byte swap descriptors in hardware */
3909 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3910 reg |= PCI_REV_DESC;
3911 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3916 /* space for skge@pci:0000:04:00.0 */
3917 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" )
3918 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3920 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3921 goto err_out_free_regions;
3923 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3926 spin_lock_init(&hw->hw_lock);
3927 spin_lock_init(&hw->phy_lock);
3928 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3930 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3932 dev_err(&pdev->dev, "cannot map device registers\n");
3933 goto err_out_free_hw;
3936 err = skge_reset(hw);
3938 goto err_out_iounmap;
3940 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3942 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3943 skge_board_name(hw), hw->chip_rev);
3945 dev = skge_devinit(hw, 0, using_dac);
3947 goto err_out_led_off;
3949 /* Some motherboards are broken and has zero in ROM. */
3950 if (!is_valid_ether_addr(dev->dev_addr))
3951 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3953 err = register_netdev(dev);
3955 dev_err(&pdev->dev, "cannot register net device\n");
3956 goto err_out_free_netdev;
3959 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
3961 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3962 dev->name, pdev->irq);
3963 goto err_out_unregister;
3965 skge_show_addr(dev);
3967 if (hw->ports > 1) {
3968 dev1 = skge_devinit(hw, 1, using_dac);
3969 if (dev1 && register_netdev(dev1) == 0)
3970 skge_show_addr(dev1);
3972 /* Failure to register second port need not be fatal */
3973 dev_warn(&pdev->dev, "register of second port failed\n");
3980 pci_set_drvdata(pdev, hw);
3985 unregister_netdev(dev);
3986 err_out_free_netdev:
3989 skge_write16(hw, B0_LED, LED_STAT_OFF);
3994 err_out_free_regions:
3995 pci_release_regions(pdev);
3996 err_out_disable_pdev:
3997 pci_disable_device(pdev);
3998 pci_set_drvdata(pdev, NULL);
4003 static void __devexit skge_remove(struct pci_dev *pdev)
4005 struct skge_hw *hw = pci_get_drvdata(pdev);
4006 struct net_device *dev0, *dev1;
4011 flush_scheduled_work();
4013 if ((dev1 = hw->dev[1]))
4014 unregister_netdev(dev1);
4016 unregister_netdev(dev0);
4018 tasklet_disable(&hw->phy_task);
4020 spin_lock_irq(&hw->hw_lock);
4022 skge_write32(hw, B0_IMSK, 0);
4023 skge_read32(hw, B0_IMSK);
4024 spin_unlock_irq(&hw->hw_lock);
4026 skge_write16(hw, B0_LED, LED_STAT_OFF);
4027 skge_write8(hw, B0_CTST, CS_RST_SET);
4029 free_irq(pdev->irq, hw);
4030 pci_release_regions(pdev);
4031 pci_disable_device(pdev);
4038 pci_set_drvdata(pdev, NULL);
4042 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
4044 struct skge_hw *hw = pci_get_drvdata(pdev);
4045 int i, err, wol = 0;
4050 err = pci_save_state(pdev);
4054 for (i = 0; i < hw->ports; i++) {
4055 struct net_device *dev = hw->dev[i];
4056 struct skge_port *skge = netdev_priv(dev);
4058 if (netif_running(dev))
4061 skge_wol_init(skge);
4066 skge_write32(hw, B0_IMSK, 0);
4068 pci_prepare_to_sleep(pdev);
4073 static int skge_resume(struct pci_dev *pdev)
4075 struct skge_hw *hw = pci_get_drvdata(pdev);
4081 err = pci_back_from_sleep(pdev);
4085 err = pci_restore_state(pdev);
4089 err = skge_reset(hw);
4093 for (i = 0; i < hw->ports; i++) {
4094 struct net_device *dev = hw->dev[i];
4096 if (netif_running(dev)) {
4100 netdev_err(dev, "could not up: %d\n", err);
4111 static void skge_shutdown(struct pci_dev *pdev)
4113 struct skge_hw *hw = pci_get_drvdata(pdev);
4119 for (i = 0; i < hw->ports; i++) {
4120 struct net_device *dev = hw->dev[i];
4121 struct skge_port *skge = netdev_priv(dev);
4124 skge_wol_init(skge);
4128 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4129 pci_enable_wake(pdev, PCI_D3hot, wol);
4131 pci_disable_device(pdev);
4132 pci_set_power_state(pdev, PCI_D3hot);
4136 static struct pci_driver skge_driver = {
4138 .id_table = skge_id_table,
4139 .probe = skge_probe,
4140 .remove = __devexit_p(skge_remove),
4142 .suspend = skge_suspend,
4143 .resume = skge_resume,
4145 .shutdown = skge_shutdown,
4148 static int __init skge_init_module(void)
4151 return pci_register_driver(&skge_driver);
4154 static void __exit skge_cleanup_module(void)
4156 pci_unregister_driver(&skge_driver);
4157 skge_debug_cleanup();
4160 module_init(skge_init_module);
4161 module_exit(skge_cleanup_module);