2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.7"
47 #define PFX DRV_NAME " "
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct skge_port *skge);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
109 static int skge_get_regs_len(struct net_device *dev)
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142 struct skge_port *skge = netdev_priv(dev);
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
159 skge->wol = wol->wolopts == WAKE_MAGIC;
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
176 static u32 skge_supported_modes(const struct skge_hw *hw)
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
217 ecmd->port = PORT_FIBRE;
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
239 switch (ecmd->speed) {
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
269 if ((setting & supported) == 0)
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
279 if (netif_running(dev))
280 skge_phy_reset(skge);
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
288 struct skge_port *skge = netdev_priv(dev);
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
327 static int skge_get_stats_count(struct net_device *dev)
329 return ARRAY_SIZE(skge_stats);
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
335 struct skge_port *skge = netdev_priv(dev);
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
340 yukon_get_stats(skge, data);
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
355 yukon_get_stats(skge, data);
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[3] + data[5];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
365 return &skge->net_stats;
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
384 struct skge_port *skge = netdev_priv(dev);
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
400 struct skge_port *skge = netdev_priv(dev);
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
410 if (netif_running(dev)) {
420 static u32 skge_get_msglevel(struct net_device *netdev)
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
426 static void skge_set_msglevel(struct net_device *netdev, u32 value)
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
432 static int skge_nway_reset(struct net_device *dev)
434 struct skge_port *skge = netdev_priv(dev);
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
439 skge_phy_reset(skge);
443 static int skge_set_sg(struct net_device *dev, u32 data)
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
450 return ethtool_op_set_sg(dev, data);
453 static int skge_set_tx_csum(struct net_device *dev, u32 data)
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
461 return ethtool_op_set_tx_csum(dev, data);
464 static u32 skge_get_rx_csum(struct net_device *dev)
466 struct skge_port *skge = netdev_priv(dev);
468 return skge->rx_csum;
471 /* Only Yukon supports checksum offload. */
472 static int skge_set_rx_csum(struct net_device *dev, u32 data)
474 struct skge_port *skge = netdev_priv(dev);
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
479 skge->rx_csum = data;
483 static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
486 struct skge_port *skge = netdev_priv(dev);
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
493 ecmd->autoneg = skge->autoneg;
496 static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
499 struct skge_port *skge = netdev_priv(dev);
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
504 else if (ecmd->rx_pause && !ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_REM_SEND;
506 else if (!ecmd->rx_pause && ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_LOC_SEND;
509 skge->flow_control = FLOW_MODE_NONE;
511 if (netif_running(dev))
512 skge_phy_reset(skge);
516 /* Chip internal frequency for clock calculations */
517 static inline u32 hwkhz(const struct skge_hw *hw)
519 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
522 /* Chip HZ to microseconds */
523 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
525 return (ticks * 1000) / hwkhz(hw);
528 /* Microseconds to chip HZ */
529 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
531 return hwkhz(hw) * usec / 1000;
534 static int skge_get_coalesce(struct net_device *dev,
535 struct ethtool_coalesce *ecmd)
537 struct skge_port *skge = netdev_priv(dev);
538 struct skge_hw *hw = skge->hw;
539 int port = skge->port;
541 ecmd->rx_coalesce_usecs = 0;
542 ecmd->tx_coalesce_usecs = 0;
544 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
545 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
546 u32 msk = skge_read32(hw, B2_IRQM_MSK);
548 if (msk & rxirqmask[port])
549 ecmd->rx_coalesce_usecs = delay;
550 if (msk & txirqmask[port])
551 ecmd->tx_coalesce_usecs = delay;
557 /* Note: interrupt timer is per board, but can turn on/off per port */
558 static int skge_set_coalesce(struct net_device *dev,
559 struct ethtool_coalesce *ecmd)
561 struct skge_port *skge = netdev_priv(dev);
562 struct skge_hw *hw = skge->hw;
563 int port = skge->port;
564 u32 msk = skge_read32(hw, B2_IRQM_MSK);
567 if (ecmd->rx_coalesce_usecs == 0)
568 msk &= ~rxirqmask[port];
569 else if (ecmd->rx_coalesce_usecs < 25 ||
570 ecmd->rx_coalesce_usecs > 33333)
573 msk |= rxirqmask[port];
574 delay = ecmd->rx_coalesce_usecs;
577 if (ecmd->tx_coalesce_usecs == 0)
578 msk &= ~txirqmask[port];
579 else if (ecmd->tx_coalesce_usecs < 25 ||
580 ecmd->tx_coalesce_usecs > 33333)
583 msk |= txirqmask[port];
584 delay = min(delay, ecmd->rx_coalesce_usecs);
587 skge_write32(hw, B2_IRQM_MSK, msk);
589 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
591 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
592 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
597 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
598 static void skge_led(struct skge_port *skge, enum led_mode mode)
600 struct skge_hw *hw = skge->hw;
601 int port = skge->port;
603 mutex_lock(&hw->phy_mutex);
604 if (hw->chip_id == CHIP_ID_GENESIS) {
607 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
608 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
609 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
610 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
614 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
617 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
618 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
623 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
624 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
625 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
627 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
633 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
634 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
635 PHY_M_LED_MO_DUP(MO_LED_OFF) |
636 PHY_M_LED_MO_10(MO_LED_OFF) |
637 PHY_M_LED_MO_100(MO_LED_OFF) |
638 PHY_M_LED_MO_1000(MO_LED_OFF) |
639 PHY_M_LED_MO_RX(MO_LED_OFF));
642 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
643 PHY_M_LED_PULS_DUR(PULS_170MS) |
644 PHY_M_LED_BLINK_RT(BLINK_84MS) |
648 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
649 PHY_M_LED_MO_RX(MO_LED_OFF) |
650 (skge->speed == SPEED_100 ?
651 PHY_M_LED_MO_100(MO_LED_ON) : 0));
654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
655 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
656 PHY_M_LED_MO_DUP(MO_LED_ON) |
657 PHY_M_LED_MO_10(MO_LED_ON) |
658 PHY_M_LED_MO_100(MO_LED_ON) |
659 PHY_M_LED_MO_1000(MO_LED_ON) |
660 PHY_M_LED_MO_RX(MO_LED_ON));
663 mutex_unlock(&hw->phy_mutex);
666 /* blink LED's for finding board */
667 static int skge_phys_id(struct net_device *dev, u32 data)
669 struct skge_port *skge = netdev_priv(dev);
671 enum led_mode mode = LED_MODE_TST;
673 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
674 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
679 skge_led(skge, mode);
680 mode ^= LED_MODE_TST;
682 if (msleep_interruptible(BLINK_MS))
687 /* back to regular LED state */
688 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
693 static struct ethtool_ops skge_ethtool_ops = {
694 .get_settings = skge_get_settings,
695 .set_settings = skge_set_settings,
696 .get_drvinfo = skge_get_drvinfo,
697 .get_regs_len = skge_get_regs_len,
698 .get_regs = skge_get_regs,
699 .get_wol = skge_get_wol,
700 .set_wol = skge_set_wol,
701 .get_msglevel = skge_get_msglevel,
702 .set_msglevel = skge_set_msglevel,
703 .nway_reset = skge_nway_reset,
704 .get_link = ethtool_op_get_link,
705 .get_ringparam = skge_get_ring_param,
706 .set_ringparam = skge_set_ring_param,
707 .get_pauseparam = skge_get_pauseparam,
708 .set_pauseparam = skge_set_pauseparam,
709 .get_coalesce = skge_get_coalesce,
710 .set_coalesce = skge_set_coalesce,
711 .get_sg = ethtool_op_get_sg,
712 .set_sg = skge_set_sg,
713 .get_tx_csum = ethtool_op_get_tx_csum,
714 .set_tx_csum = skge_set_tx_csum,
715 .get_rx_csum = skge_get_rx_csum,
716 .set_rx_csum = skge_set_rx_csum,
717 .get_strings = skge_get_strings,
718 .phys_id = skge_phys_id,
719 .get_stats_count = skge_get_stats_count,
720 .get_ethtool_stats = skge_get_ethtool_stats,
721 .get_perm_addr = ethtool_op_get_perm_addr,
725 * Allocate ring elements and chain them together
726 * One-to-one association of board descriptors with ring elements
728 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
730 struct skge_tx_desc *d;
731 struct skge_element *e;
734 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
738 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
740 if (i == ring->count - 1) {
741 e->next = ring->start;
742 d->next_offset = base;
745 d->next_offset = base + (i+1) * sizeof(*d);
748 ring->to_use = ring->to_clean = ring->start;
753 /* Allocate and setup a new buffer for receiving */
754 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
755 struct sk_buff *skb, unsigned int bufsize)
757 struct skge_rx_desc *rd = e->desc;
760 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
764 rd->dma_hi = map >> 32;
766 rd->csum1_start = ETH_HLEN;
767 rd->csum2_start = ETH_HLEN;
773 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
774 pci_unmap_addr_set(e, mapaddr, map);
775 pci_unmap_len_set(e, maplen, bufsize);
778 /* Resume receiving using existing skb,
779 * Note: DMA address is not changed by chip.
780 * MTU not changed while receiver active.
782 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
784 struct skge_rx_desc *rd = e->desc;
787 rd->csum2_start = ETH_HLEN;
791 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
795 /* Free all buffers in receive ring, assumes receiver stopped */
796 static void skge_rx_clean(struct skge_port *skge)
798 struct skge_hw *hw = skge->hw;
799 struct skge_ring *ring = &skge->rx_ring;
800 struct skge_element *e;
804 struct skge_rx_desc *rd = e->desc;
807 pci_unmap_single(hw->pdev,
808 pci_unmap_addr(e, mapaddr),
809 pci_unmap_len(e, maplen),
811 dev_kfree_skb(e->skb);
814 } while ((e = e->next) != ring->start);
818 /* Allocate buffers for receive ring
819 * For receive: to_clean is next received frame.
821 static int skge_rx_fill(struct net_device *dev)
823 struct skge_port *skge = netdev_priv(dev);
824 struct skge_ring *ring = &skge->rx_ring;
825 struct skge_element *e;
831 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
836 skb_reserve(skb, NET_IP_ALIGN);
837 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
838 } while ( (e = e->next) != ring->start);
840 ring->to_clean = ring->start;
844 static void skge_link_up(struct skge_port *skge)
846 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
847 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
849 netif_carrier_on(skge->netdev);
850 netif_wake_queue(skge->netdev);
852 if (netif_msg_link(skge))
854 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
855 skge->netdev->name, skge->speed,
856 skge->duplex == DUPLEX_FULL ? "full" : "half",
857 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
858 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
859 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
860 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
864 static void skge_link_down(struct skge_port *skge)
866 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
867 netif_carrier_off(skge->netdev);
868 netif_stop_queue(skge->netdev);
870 if (netif_msg_link(skge))
871 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
874 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
878 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
879 *val = xm_read16(hw, port, XM_PHY_DATA);
881 for (i = 0; i < PHY_RETRIES; i++) {
882 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
889 *val = xm_read16(hw, port, XM_PHY_DATA);
894 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
897 if (__xm_phy_read(hw, port, reg, &v))
898 printk(KERN_WARNING PFX "%s: phy read timed out\n",
899 hw->dev[port]->name);
903 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
907 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
908 for (i = 0; i < PHY_RETRIES; i++) {
909 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
916 xm_write16(hw, port, XM_PHY_DATA, val);
917 for (i = 0; i < PHY_RETRIES; i++) {
918 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
925 static void genesis_init(struct skge_hw *hw)
927 /* set blink source counter */
928 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
929 skge_write8(hw, B2_BSC_CTRL, BSC_START);
931 /* configure mac arbiter */
932 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
934 /* configure mac arbiter timeout values */
935 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_RCINI_RX1, 0);
941 skge_write8(hw, B3_MA_RCINI_RX2, 0);
942 skge_write8(hw, B3_MA_RCINI_TX1, 0);
943 skge_write8(hw, B3_MA_RCINI_TX2, 0);
945 /* configure packet arbiter timeout */
946 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
947 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
953 static void genesis_reset(struct skge_hw *hw, int port)
955 const u8 zero[8] = { 0 };
957 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
959 /* reset the statistics module */
960 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
961 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
962 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
963 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
964 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
966 /* disable Broadcom PHY IRQ */
967 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
969 xm_outhash(hw, port, XM_HSM, zero);
973 /* Convert mode to MII values */
974 static const u16 phy_pause_map[] = {
975 [FLOW_MODE_NONE] = 0,
976 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
977 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
978 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
982 /* Check status of Broadcom phy link */
983 static void bcom_check_link(struct skge_hw *hw, int port)
985 struct net_device *dev = hw->dev[port];
986 struct skge_port *skge = netdev_priv(dev);
989 /* read twice because of latch */
990 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
991 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
993 if ((status & PHY_ST_LSYNC) == 0) {
994 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
995 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
996 xm_write16(hw, port, XM_MMU_CMD, cmd);
997 /* dummy read to ensure writing */
998 (void) xm_read16(hw, port, XM_MMU_CMD);
1000 if (netif_carrier_ok(dev))
1001 skge_link_down(skge);
1003 if (skge->autoneg == AUTONEG_ENABLE &&
1004 (status & PHY_ST_AN_OVER)) {
1005 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1006 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1008 if (lpa & PHY_B_AN_RF) {
1009 printk(KERN_NOTICE PFX "%s: remote fault\n",
1014 /* Check Duplex mismatch */
1015 switch (aux & PHY_B_AS_AN_RES_MSK) {
1016 case PHY_B_RES_1000FD:
1017 skge->duplex = DUPLEX_FULL;
1019 case PHY_B_RES_1000HD:
1020 skge->duplex = DUPLEX_HALF;
1023 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1029 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1030 switch (aux & PHY_B_AS_PAUSE_MSK) {
1031 case PHY_B_AS_PAUSE_MSK:
1032 skge->flow_control = FLOW_MODE_SYMMETRIC;
1035 skge->flow_control = FLOW_MODE_REM_SEND;
1038 skge->flow_control = FLOW_MODE_LOC_SEND;
1041 skge->flow_control = FLOW_MODE_NONE;
1044 skge->speed = SPEED_1000;
1047 if (!netif_carrier_ok(dev))
1048 genesis_link_up(skge);
1052 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1053 * Phy on for 100 or 10Mbit operation
1055 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1057 struct skge_hw *hw = skge->hw;
1058 int port = skge->port;
1060 u16 id1, r, ext, ctl;
1062 /* magic workaround patterns for Broadcom */
1063 static const struct {
1067 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1068 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1069 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1070 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1072 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1073 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1076 /* read Id from external PHY (all have the same address) */
1077 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1079 /* Optimize MDIO transfer by suppressing preamble. */
1080 r = xm_read16(hw, port, XM_MMU_CMD);
1082 xm_write16(hw, port, XM_MMU_CMD,r);
1085 case PHY_BCOM_ID1_C0:
1087 * Workaround BCOM Errata for the C0 type.
1088 * Write magic patterns to reserved registers.
1090 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1091 xm_phy_write(hw, port,
1092 C0hack[i].reg, C0hack[i].val);
1095 case PHY_BCOM_ID1_A1:
1097 * Workaround BCOM Errata for the A1 type.
1098 * Write magic patterns to reserved registers.
1100 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1101 xm_phy_write(hw, port,
1102 A1hack[i].reg, A1hack[i].val);
1107 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1108 * Disable Power Management after reset.
1110 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1111 r |= PHY_B_AC_DIS_PM;
1112 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1115 xm_read16(hw, port, XM_ISRC);
1117 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1118 ctl = PHY_CT_SP1000; /* always 1000mbit */
1120 if (skge->autoneg == AUTONEG_ENABLE) {
1122 * Workaround BCOM Errata #1 for the C5 type.
1123 * 1000Base-T Link Acquisition Failure in Slave Mode
1124 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1126 u16 adv = PHY_B_1000C_RD;
1127 if (skge->advertising & ADVERTISED_1000baseT_Half)
1128 adv |= PHY_B_1000C_AHD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Full)
1130 adv |= PHY_B_1000C_AFD;
1131 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1133 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1135 if (skge->duplex == DUPLEX_FULL)
1136 ctl |= PHY_CT_DUP_MD;
1137 /* Force to slave */
1138 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1141 /* Set autonegotiation pause parameters */
1142 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1143 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1145 /* Handle Jumbo frames */
1147 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1148 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1150 ext |= PHY_B_PEC_HIGH_LA;
1154 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1155 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1157 /* Use link status change interrupt */
1158 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1160 bcom_check_link(hw, port);
1163 static void genesis_mac_init(struct skge_hw *hw, int port)
1165 struct net_device *dev = hw->dev[port];
1166 struct skge_port *skge = netdev_priv(dev);
1167 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1170 const u8 zero[6] = { 0 };
1172 for (i = 0; i < 10; i++) {
1173 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1175 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1180 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1183 /* Unreset the XMAC. */
1184 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1187 * Perform additional initialization for external PHYs,
1188 * namely for the 1000baseTX cards that use the XMAC's
1191 /* Take external Phy out of reset */
1192 r = skge_read32(hw, B2_GP_IO);
1194 r |= GP_DIR_0|GP_IO_0;
1196 r |= GP_DIR_2|GP_IO_2;
1198 skge_write32(hw, B2_GP_IO, r);
1201 /* Enable GMII interface */
1202 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1204 bcom_phy_init(skge, jumbo);
1206 /* Set Station Address */
1207 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1209 /* We don't use match addresses so clear */
1210 for (i = 1; i < 16; i++)
1211 xm_outaddr(hw, port, XM_EXM(i), zero);
1213 /* Clear MIB counters */
1214 xm_write16(hw, port, XM_STAT_CMD,
1215 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1216 /* Clear two times according to Errata #3 */
1217 xm_write16(hw, port, XM_STAT_CMD,
1218 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1220 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1221 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1223 /* We don't need the FCS appended to the packet. */
1224 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1226 r |= XM_RX_BIG_PK_OK;
1228 if (skge->duplex == DUPLEX_HALF) {
1230 * If in manual half duplex mode the other side might be in
1231 * full duplex mode, so ignore if a carrier extension is not seen
1232 * on frames received
1234 r |= XM_RX_DIS_CEXT;
1236 xm_write16(hw, port, XM_RX_CMD, r);
1239 /* We want short frames padded to 60 bytes. */
1240 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1243 * Bump up the transmit threshold. This helps hold off transmit
1244 * underruns when we're blasting traffic from both ports at once.
1246 xm_write16(hw, port, XM_TX_THR, 512);
1249 * Enable the reception of all error frames. This is is
1250 * a necessary evil due to the design of the XMAC. The
1251 * XMAC's receive FIFO is only 8K in size, however jumbo
1252 * frames can be up to 9000 bytes in length. When bad
1253 * frame filtering is enabled, the XMAC's RX FIFO operates
1254 * in 'store and forward' mode. For this to work, the
1255 * entire frame has to fit into the FIFO, but that means
1256 * that jumbo frames larger than 8192 bytes will be
1257 * truncated. Disabling all bad frame filtering causes
1258 * the RX FIFO to operate in streaming mode, in which
1259 * case the XMAC will start transferring frames out of the
1260 * RX FIFO as soon as the FIFO threshold is reached.
1262 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1266 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1267 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1268 * and 'Octets Rx OK Hi Cnt Ov'.
1270 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1273 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1274 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1275 * and 'Octets Tx OK Hi Cnt Ov'.
1277 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1279 /* Configure MAC arbiter */
1280 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1282 /* configure timeout values */
1283 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1284 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1285 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1288 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1289 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1290 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1293 /* Configure Rx MAC FIFO */
1294 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1295 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1298 /* Configure Tx MAC FIFO */
1299 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1300 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1304 /* Enable frame flushing if jumbo frames used */
1305 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1307 /* enable timeout timers if normal frames */
1308 skge_write16(hw, B3_PA_CTRL,
1309 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1313 static void genesis_stop(struct skge_port *skge)
1315 struct skge_hw *hw = skge->hw;
1316 int port = skge->port;
1319 genesis_reset(hw, port);
1321 /* Clear Tx packet arbiter timeout IRQ */
1322 skge_write16(hw, B3_PA_CTRL,
1323 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1326 * If the transfer sticks at the MAC the STOP command will not
1327 * terminate if we don't flush the XMAC's transmit FIFO !
1329 xm_write32(hw, port, XM_MODE,
1330 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1334 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1336 /* For external PHYs there must be special handling */
1337 reg = skge_read32(hw, B2_GP_IO);
1345 skge_write32(hw, B2_GP_IO, reg);
1346 skge_read32(hw, B2_GP_IO);
1348 xm_write16(hw, port, XM_MMU_CMD,
1349 xm_read16(hw, port, XM_MMU_CMD)
1350 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1352 xm_read16(hw, port, XM_MMU_CMD);
1356 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1358 struct skge_hw *hw = skge->hw;
1359 int port = skge->port;
1361 unsigned long timeout = jiffies + HZ;
1363 xm_write16(hw, port,
1364 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1366 /* wait for update to complete */
1367 while (xm_read16(hw, port, XM_STAT_CMD)
1368 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1369 if (time_after(jiffies, timeout))
1374 /* special case for 64 bit octet counter */
1375 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1376 | xm_read32(hw, port, XM_TXO_OK_LO);
1377 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1378 | xm_read32(hw, port, XM_RXO_OK_LO);
1380 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1381 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1384 static void genesis_mac_intr(struct skge_hw *hw, int port)
1386 struct skge_port *skge = netdev_priv(hw->dev[port]);
1387 u16 status = xm_read16(hw, port, XM_ISRC);
1389 if (netif_msg_intr(skge))
1390 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1391 skge->netdev->name, status);
1393 if (status & XM_IS_TXF_UR) {
1394 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1395 ++skge->net_stats.tx_fifo_errors;
1397 if (status & XM_IS_RXF_OV) {
1398 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1399 ++skge->net_stats.rx_fifo_errors;
1403 static void genesis_link_up(struct skge_port *skge)
1405 struct skge_hw *hw = skge->hw;
1406 int port = skge->port;
1410 cmd = xm_read16(hw, port, XM_MMU_CMD);
1413 * enabling pause frame reception is required for 1000BT
1414 * because the XMAC is not reset if the link is going down
1416 if (skge->flow_control == FLOW_MODE_NONE ||
1417 skge->flow_control == FLOW_MODE_LOC_SEND)
1418 /* Disable Pause Frame Reception */
1419 cmd |= XM_MMU_IGN_PF;
1421 /* Enable Pause Frame Reception */
1422 cmd &= ~XM_MMU_IGN_PF;
1424 xm_write16(hw, port, XM_MMU_CMD, cmd);
1426 mode = xm_read32(hw, port, XM_MODE);
1427 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1428 skge->flow_control == FLOW_MODE_LOC_SEND) {
1430 * Configure Pause Frame Generation
1431 * Use internal and external Pause Frame Generation.
1432 * Sending pause frames is edge triggered.
1433 * Send a Pause frame with the maximum pause time if
1434 * internal oder external FIFO full condition occurs.
1435 * Send a zero pause time frame to re-start transmission.
1437 /* XM_PAUSE_DA = '010000C28001' (default) */
1438 /* XM_MAC_PTIME = 0xffff (maximum) */
1439 /* remember this value is defined in big endian (!) */
1440 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1442 mode |= XM_PAUSE_MODE;
1443 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1446 * disable pause frame generation is required for 1000BT
1447 * because the XMAC is not reset if the link is going down
1449 /* Disable Pause Mode in Mode Register */
1450 mode &= ~XM_PAUSE_MODE;
1452 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1455 xm_write32(hw, port, XM_MODE, mode);
1458 /* disable GP0 interrupt bit for external Phy */
1459 msk |= XM_IS_INP_ASS;
1461 xm_write16(hw, port, XM_IMSK, msk);
1462 xm_read16(hw, port, XM_ISRC);
1464 /* get MMU Command Reg. */
1465 cmd = xm_read16(hw, port, XM_MMU_CMD);
1466 if (skge->duplex == DUPLEX_FULL)
1467 cmd |= XM_MMU_GMII_FD;
1470 * Workaround BCOM Errata (#10523) for all BCom Phys
1471 * Enable Power Management after link up
1473 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1474 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1475 & ~PHY_B_AC_DIS_PM);
1476 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1479 xm_write16(hw, port, XM_MMU_CMD,
1480 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1485 static inline void bcom_phy_intr(struct skge_port *skge)
1487 struct skge_hw *hw = skge->hw;
1488 int port = skge->port;
1491 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1492 if (netif_msg_intr(skge))
1493 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1494 skge->netdev->name, isrc);
1496 if (isrc & PHY_B_IS_PSE)
1497 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1498 hw->dev[port]->name);
1500 /* Workaround BCom Errata:
1501 * enable and disable loopback mode if "NO HCD" occurs.
1503 if (isrc & PHY_B_IS_NO_HDCL) {
1504 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1505 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1506 ctrl | PHY_CT_LOOP);
1507 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1508 ctrl & ~PHY_CT_LOOP);
1511 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1512 bcom_check_link(hw, port);
1516 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1520 gma_write16(hw, port, GM_SMI_DATA, val);
1521 gma_write16(hw, port, GM_SMI_CTRL,
1522 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1523 for (i = 0; i < PHY_RETRIES; i++) {
1526 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1530 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1531 hw->dev[port]->name);
1535 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1539 gma_write16(hw, port, GM_SMI_CTRL,
1540 GM_SMI_CT_PHY_AD(hw->phy_addr)
1541 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1543 for (i = 0; i < PHY_RETRIES; i++) {
1545 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1551 *val = gma_read16(hw, port, GM_SMI_DATA);
1555 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1558 if (__gm_phy_read(hw, port, reg, &v))
1559 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1560 hw->dev[port]->name);
1564 /* Marvell Phy Initialization */
1565 static void yukon_init(struct skge_hw *hw, int port)
1567 struct skge_port *skge = netdev_priv(hw->dev[port]);
1568 u16 ctrl, ct1000, adv;
1570 if (skge->autoneg == AUTONEG_ENABLE) {
1571 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1573 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1574 PHY_M_EC_MAC_S_MSK);
1575 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1577 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1579 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1582 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1583 if (skge->autoneg == AUTONEG_DISABLE)
1584 ctrl &= ~PHY_CT_ANE;
1586 ctrl |= PHY_CT_RESET;
1587 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1593 if (skge->autoneg == AUTONEG_ENABLE) {
1595 if (skge->advertising & ADVERTISED_1000baseT_Full)
1596 ct1000 |= PHY_M_1000C_AFD;
1597 if (skge->advertising & ADVERTISED_1000baseT_Half)
1598 ct1000 |= PHY_M_1000C_AHD;
1599 if (skge->advertising & ADVERTISED_100baseT_Full)
1600 adv |= PHY_M_AN_100_FD;
1601 if (skge->advertising & ADVERTISED_100baseT_Half)
1602 adv |= PHY_M_AN_100_HD;
1603 if (skge->advertising & ADVERTISED_10baseT_Full)
1604 adv |= PHY_M_AN_10_FD;
1605 if (skge->advertising & ADVERTISED_10baseT_Half)
1606 adv |= PHY_M_AN_10_HD;
1607 } else /* special defines for FIBER (88E1011S only) */
1608 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1610 /* Set Flow-control capabilities */
1611 adv |= phy_pause_map[skge->flow_control];
1613 /* Restart Auto-negotiation */
1614 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1616 /* forced speed/duplex settings */
1617 ct1000 = PHY_M_1000C_MSE;
1619 if (skge->duplex == DUPLEX_FULL)
1620 ctrl |= PHY_CT_DUP_MD;
1622 switch (skge->speed) {
1624 ctrl |= PHY_CT_SP1000;
1627 ctrl |= PHY_CT_SP100;
1631 ctrl |= PHY_CT_RESET;
1634 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1636 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1637 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1639 /* Enable phy interrupt on autonegotiation complete (or link up) */
1640 if (skge->autoneg == AUTONEG_ENABLE)
1641 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1643 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1646 static void yukon_reset(struct skge_hw *hw, int port)
1648 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1649 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1650 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1651 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1652 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1654 gma_write16(hw, port, GM_RX_CTRL,
1655 gma_read16(hw, port, GM_RX_CTRL)
1656 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1659 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1660 static int is_yukon_lite_a0(struct skge_hw *hw)
1665 if (hw->chip_id != CHIP_ID_YUKON)
1668 reg = skge_read32(hw, B2_FAR);
1669 skge_write8(hw, B2_FAR + 3, 0xff);
1670 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1671 skge_write32(hw, B2_FAR, reg);
1675 static void yukon_mac_init(struct skge_hw *hw, int port)
1677 struct skge_port *skge = netdev_priv(hw->dev[port]);
1680 const u8 *addr = hw->dev[port]->dev_addr;
1682 /* WA code for COMA mode -- set PHY reset */
1683 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1684 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1685 reg = skge_read32(hw, B2_GP_IO);
1686 reg |= GP_DIR_9 | GP_IO_9;
1687 skge_write32(hw, B2_GP_IO, reg);
1691 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1692 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1694 /* WA code for COMA mode -- clear PHY reset */
1695 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1696 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1697 reg = skge_read32(hw, B2_GP_IO);
1700 skge_write32(hw, B2_GP_IO, reg);
1703 /* Set hardware config mode */
1704 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1705 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1706 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1708 /* Clear GMC reset */
1709 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1710 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1711 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1713 if (skge->autoneg == AUTONEG_DISABLE) {
1714 reg = GM_GPCR_AU_ALL_DIS;
1715 gma_write16(hw, port, GM_GP_CTRL,
1716 gma_read16(hw, port, GM_GP_CTRL) | reg);
1718 switch (skge->speed) {
1720 reg &= ~GM_GPCR_SPEED_100;
1721 reg |= GM_GPCR_SPEED_1000;
1724 reg &= ~GM_GPCR_SPEED_1000;
1725 reg |= GM_GPCR_SPEED_100;
1728 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1732 if (skge->duplex == DUPLEX_FULL)
1733 reg |= GM_GPCR_DUP_FULL;
1735 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1737 switch (skge->flow_control) {
1738 case FLOW_MODE_NONE:
1739 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1740 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1742 case FLOW_MODE_LOC_SEND:
1743 /* disable Rx flow-control */
1744 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1747 gma_write16(hw, port, GM_GP_CTRL, reg);
1748 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1750 yukon_init(hw, port);
1753 reg = gma_read16(hw, port, GM_PHY_ADDR);
1754 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1756 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1757 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1758 gma_write16(hw, port, GM_PHY_ADDR, reg);
1760 /* transmit control */
1761 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1763 /* receive control reg: unicast + multicast + no FCS */
1764 gma_write16(hw, port, GM_RX_CTRL,
1765 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1767 /* transmit flow control */
1768 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1770 /* transmit parameter */
1771 gma_write16(hw, port, GM_TX_PARAM,
1772 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1773 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1774 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1776 /* serial mode register */
1777 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1778 if (hw->dev[port]->mtu > 1500)
1779 reg |= GM_SMOD_JUMBO_ENA;
1781 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1783 /* physical address: used for pause frames */
1784 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1785 /* virtual address for data */
1786 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1788 /* enable interrupt mask for counter overflows */
1789 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1790 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1791 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1793 /* Initialize Mac Fifo */
1795 /* Configure Rx MAC FIFO */
1796 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1797 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1799 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1800 if (is_yukon_lite_a0(hw))
1801 reg &= ~GMF_RX_F_FL_ON;
1803 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1804 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1806 * because Pause Packet Truncation in GMAC is not working
1807 * we have to increase the Flush Threshold to 64 bytes
1808 * in order to flush pause packets in Rx FIFO on Yukon-1
1810 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1812 /* Configure Tx MAC FIFO */
1813 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1814 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1817 /* Go into power down mode */
1818 static void yukon_suspend(struct skge_hw *hw, int port)
1822 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1823 ctrl |= PHY_M_PC_POL_R_DIS;
1824 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1826 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1827 ctrl |= PHY_CT_RESET;
1828 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1830 /* switch IEEE compatible power down mode on */
1831 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1832 ctrl |= PHY_CT_PDOWN;
1833 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1836 static void yukon_stop(struct skge_port *skge)
1838 struct skge_hw *hw = skge->hw;
1839 int port = skge->port;
1841 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1842 yukon_reset(hw, port);
1844 gma_write16(hw, port, GM_GP_CTRL,
1845 gma_read16(hw, port, GM_GP_CTRL)
1846 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1847 gma_read16(hw, port, GM_GP_CTRL);
1849 yukon_suspend(hw, port);
1851 /* set GPHY Control reset */
1852 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1853 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1856 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1858 struct skge_hw *hw = skge->hw;
1859 int port = skge->port;
1862 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1863 | gma_read32(hw, port, GM_TXO_OK_LO);
1864 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1865 | gma_read32(hw, port, GM_RXO_OK_LO);
1867 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1868 data[i] = gma_read32(hw, port,
1869 skge_stats[i].gma_offset);
1872 static void yukon_mac_intr(struct skge_hw *hw, int port)
1874 struct net_device *dev = hw->dev[port];
1875 struct skge_port *skge = netdev_priv(dev);
1876 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1878 if (netif_msg_intr(skge))
1879 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1882 if (status & GM_IS_RX_FF_OR) {
1883 ++skge->net_stats.rx_fifo_errors;
1884 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1887 if (status & GM_IS_TX_FF_UR) {
1888 ++skge->net_stats.tx_fifo_errors;
1889 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1894 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1896 switch (aux & PHY_M_PS_SPEED_MSK) {
1897 case PHY_M_PS_SPEED_1000:
1899 case PHY_M_PS_SPEED_100:
1906 static void yukon_link_up(struct skge_port *skge)
1908 struct skge_hw *hw = skge->hw;
1909 int port = skge->port;
1912 /* Enable Transmit FIFO Underrun */
1913 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1915 reg = gma_read16(hw, port, GM_GP_CTRL);
1916 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1917 reg |= GM_GPCR_DUP_FULL;
1920 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1921 gma_write16(hw, port, GM_GP_CTRL, reg);
1923 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1927 static void yukon_link_down(struct skge_port *skge)
1929 struct skge_hw *hw = skge->hw;
1930 int port = skge->port;
1933 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1935 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1936 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1937 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1939 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1940 /* restore Asymmetric Pause bit */
1941 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1942 gm_phy_read(hw, port,
1948 yukon_reset(hw, port);
1949 skge_link_down(skge);
1951 yukon_init(hw, port);
1954 static void yukon_phy_intr(struct skge_port *skge)
1956 struct skge_hw *hw = skge->hw;
1957 int port = skge->port;
1958 const char *reason = NULL;
1959 u16 istatus, phystat;
1961 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1962 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1964 if (netif_msg_intr(skge))
1965 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1966 skge->netdev->name, istatus, phystat);
1968 if (istatus & PHY_M_IS_AN_COMPL) {
1969 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1971 reason = "remote fault";
1975 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1976 reason = "master/slave fault";
1980 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1981 reason = "speed/duplex";
1985 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1986 ? DUPLEX_FULL : DUPLEX_HALF;
1987 skge->speed = yukon_speed(hw, phystat);
1989 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1990 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1991 case PHY_M_PS_PAUSE_MSK:
1992 skge->flow_control = FLOW_MODE_SYMMETRIC;
1994 case PHY_M_PS_RX_P_EN:
1995 skge->flow_control = FLOW_MODE_REM_SEND;
1997 case PHY_M_PS_TX_P_EN:
1998 skge->flow_control = FLOW_MODE_LOC_SEND;
2001 skge->flow_control = FLOW_MODE_NONE;
2004 if (skge->flow_control == FLOW_MODE_NONE ||
2005 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2006 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2008 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2009 yukon_link_up(skge);
2013 if (istatus & PHY_M_IS_LSP_CHANGE)
2014 skge->speed = yukon_speed(hw, phystat);
2016 if (istatus & PHY_M_IS_DUP_CHANGE)
2017 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2018 if (istatus & PHY_M_IS_LST_CHANGE) {
2019 if (phystat & PHY_M_PS_LINK_UP)
2020 yukon_link_up(skge);
2022 yukon_link_down(skge);
2026 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2027 skge->netdev->name, reason);
2029 /* XXX restart autonegotiation? */
2032 static void skge_phy_reset(struct skge_port *skge)
2034 struct skge_hw *hw = skge->hw;
2035 int port = skge->port;
2037 netif_stop_queue(skge->netdev);
2038 netif_carrier_off(skge->netdev);
2040 mutex_lock(&hw->phy_mutex);
2041 if (hw->chip_id == CHIP_ID_GENESIS) {
2042 genesis_reset(hw, port);
2043 genesis_mac_init(hw, port);
2045 yukon_reset(hw, port);
2046 yukon_init(hw, port);
2048 mutex_unlock(&hw->phy_mutex);
2051 /* Basic MII support */
2052 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054 struct mii_ioctl_data *data = if_mii(ifr);
2055 struct skge_port *skge = netdev_priv(dev);
2056 struct skge_hw *hw = skge->hw;
2057 int err = -EOPNOTSUPP;
2059 if (!netif_running(dev))
2060 return -ENODEV; /* Phy still in reset */
2064 data->phy_id = hw->phy_addr;
2069 mutex_lock(&hw->phy_mutex);
2070 if (hw->chip_id == CHIP_ID_GENESIS)
2071 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2073 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2074 mutex_unlock(&hw->phy_mutex);
2075 data->val_out = val;
2080 if (!capable(CAP_NET_ADMIN))
2083 mutex_lock(&hw->phy_mutex);
2084 if (hw->chip_id == CHIP_ID_GENESIS)
2085 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2088 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2090 mutex_unlock(&hw->phy_mutex);
2096 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2102 end = start + len - 1;
2104 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2105 skge_write32(hw, RB_ADDR(q, RB_START), start);
2106 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2107 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2108 skge_write32(hw, RB_ADDR(q, RB_END), end);
2110 if (q == Q_R1 || q == Q_R2) {
2111 /* Set thresholds on receive queue's */
2112 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2114 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2117 /* Enable store & forward on Tx queue's because
2118 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2120 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2123 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2126 /* Setup Bus Memory Interface */
2127 static void skge_qset(struct skge_port *skge, u16 q,
2128 const struct skge_element *e)
2130 struct skge_hw *hw = skge->hw;
2131 u32 watermark = 0x600;
2132 u64 base = skge->dma + (e->desc - skge->mem);
2134 /* optimization to reduce window on 32bit/33mhz */
2135 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2138 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2139 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2140 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2141 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2144 static int skge_up(struct net_device *dev)
2146 struct skge_port *skge = netdev_priv(dev);
2147 struct skge_hw *hw = skge->hw;
2148 int port = skge->port;
2149 u32 chunk, ram_addr;
2150 size_t rx_size, tx_size;
2153 if (netif_msg_ifup(skge))
2154 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2156 if (dev->mtu > RX_BUF_SIZE)
2157 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2159 skge->rx_buf_size = RX_BUF_SIZE;
2162 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2163 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2164 skge->mem_size = tx_size + rx_size;
2165 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2169 BUG_ON(skge->dma & 7);
2171 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2172 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2177 memset(skge->mem, 0, skge->mem_size);
2179 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2183 err = skge_rx_fill(dev);
2187 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2188 skge->dma + rx_size);
2192 /* Initialize MAC */
2193 mutex_lock(&hw->phy_mutex);
2194 if (hw->chip_id == CHIP_ID_GENESIS)
2195 genesis_mac_init(hw, port);
2197 yukon_mac_init(hw, port);
2198 mutex_unlock(&hw->phy_mutex);
2200 /* Configure RAMbuffers */
2201 chunk = hw->ram_size / ((hw->ports + 1)*2);
2202 ram_addr = hw->ram_offset + 2 * chunk * port;
2204 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2205 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2207 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2208 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2209 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2211 /* Start receiver BMU */
2213 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2214 skge_led(skge, LED_MODE_ON);
2216 netif_poll_enable(dev);
2220 skge_rx_clean(skge);
2221 kfree(skge->rx_ring.start);
2223 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2229 static int skge_down(struct net_device *dev)
2231 struct skge_port *skge = netdev_priv(dev);
2232 struct skge_hw *hw = skge->hw;
2233 int port = skge->port;
2235 if (skge->mem == NULL)
2238 if (netif_msg_ifdown(skge))
2239 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2241 netif_stop_queue(dev);
2243 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2244 if (hw->chip_id == CHIP_ID_GENESIS)
2249 /* Stop transmitter */
2250 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2251 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2252 RB_RST_SET|RB_DIS_OP_MD);
2255 /* Disable Force Sync bit and Enable Alloc bit */
2256 skge_write8(hw, SK_REG(port, TXA_CTRL),
2257 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2259 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2260 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2261 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2263 /* Reset PCI FIFO */
2264 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2265 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2267 /* Reset the RAM Buffer async Tx queue */
2268 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2270 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2271 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2272 RB_RST_SET|RB_DIS_OP_MD);
2273 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2275 if (hw->chip_id == CHIP_ID_GENESIS) {
2276 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2277 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2279 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2280 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2283 skge_led(skge, LED_MODE_OFF);
2285 netif_poll_disable(dev);
2286 skge_tx_clean(skge);
2287 skge_rx_clean(skge);
2289 kfree(skge->rx_ring.start);
2290 kfree(skge->tx_ring.start);
2291 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2296 static inline int skge_avail(const struct skge_ring *ring)
2298 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2299 + (ring->to_clean - ring->to_use) - 1;
2302 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2304 struct skge_port *skge = netdev_priv(dev);
2305 struct skge_hw *hw = skge->hw;
2306 struct skge_element *e;
2307 struct skge_tx_desc *td;
2311 unsigned long flags;
2313 if (skb_padto(skb, ETH_ZLEN))
2314 return NETDEV_TX_OK;
2316 if (!spin_trylock_irqsave(&skge->tx_lock, flags))
2317 /* Collision - tell upper layer to requeue */
2318 return NETDEV_TX_LOCKED;
2320 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
2321 if (!netif_queue_stopped(dev)) {
2322 netif_stop_queue(dev);
2324 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2327 spin_unlock_irqrestore(&skge->tx_lock, flags);
2328 return NETDEV_TX_BUSY;
2331 e = skge->tx_ring.to_use;
2333 BUG_ON(td->control & BMU_OWN);
2335 len = skb_headlen(skb);
2336 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2337 pci_unmap_addr_set(e, mapaddr, map);
2338 pci_unmap_len_set(e, maplen, len);
2341 td->dma_hi = map >> 32;
2343 if (skb->ip_summed == CHECKSUM_HW) {
2344 int offset = skb->h.raw - skb->data;
2346 /* This seems backwards, but it is what the sk98lin
2347 * does. Looks like hardware is wrong?
2349 if (skb->h.ipiph->protocol == IPPROTO_UDP
2350 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2351 control = BMU_TCP_CHECK;
2353 control = BMU_UDP_CHECK;
2356 td->csum_start = offset;
2357 td->csum_write = offset + skb->csum;
2359 control = BMU_CHECK;
2361 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2362 control |= BMU_EOF| BMU_IRQ_EOF;
2364 struct skge_tx_desc *tf = td;
2366 control |= BMU_STFWD;
2367 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2368 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2370 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2371 frag->size, PCI_DMA_TODEVICE);
2376 BUG_ON(tf->control & BMU_OWN);
2379 tf->dma_hi = (u64) map >> 32;
2380 pci_unmap_addr_set(e, mapaddr, map);
2381 pci_unmap_len_set(e, maplen, frag->size);
2383 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2385 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2387 /* Make sure all the descriptors written */
2389 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2392 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2394 if (unlikely(netif_msg_tx_queued(skge)))
2395 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2396 dev->name, e - skge->tx_ring.start, skb->len);
2398 skge->tx_ring.to_use = e->next;
2399 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2400 pr_debug("%s: transmit queue full\n", dev->name);
2401 netif_stop_queue(dev);
2404 spin_unlock_irqrestore(&skge->tx_lock, flags);
2406 dev->trans_start = jiffies;
2408 return NETDEV_TX_OK;
2412 /* Free resources associated with this reing element */
2413 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2416 struct pci_dev *pdev = skge->hw->pdev;
2420 /* skb header vs. fragment */
2421 if (control & BMU_STF)
2422 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2423 pci_unmap_len(e, maplen),
2426 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2427 pci_unmap_len(e, maplen),
2430 if (control & BMU_EOF) {
2431 if (unlikely(netif_msg_tx_done(skge)))
2432 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2433 skge->netdev->name, e - skge->tx_ring.start);
2435 dev_kfree_skb_any(e->skb);
2440 /* Free all buffers in transmit ring */
2441 static void skge_tx_clean(struct skge_port *skge)
2443 struct skge_element *e;
2444 unsigned long flags;
2446 spin_lock_irqsave(&skge->tx_lock, flags);
2447 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2448 struct skge_tx_desc *td = e->desc;
2449 skge_tx_free(skge, e, td->control);
2453 skge->tx_ring.to_clean = e;
2454 netif_wake_queue(skge->netdev);
2455 spin_unlock_irqrestore(&skge->tx_lock, flags);
2458 static void skge_tx_timeout(struct net_device *dev)
2460 struct skge_port *skge = netdev_priv(dev);
2462 if (netif_msg_timer(skge))
2463 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2465 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2466 skge_tx_clean(skge);
2469 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2473 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2476 if (!netif_running(dev)) {
2492 static void genesis_set_multicast(struct net_device *dev)
2494 struct skge_port *skge = netdev_priv(dev);
2495 struct skge_hw *hw = skge->hw;
2496 int port = skge->port;
2497 int i, count = dev->mc_count;
2498 struct dev_mc_list *list = dev->mc_list;
2502 mode = xm_read32(hw, port, XM_MODE);
2503 mode |= XM_MD_ENA_HASH;
2504 if (dev->flags & IFF_PROMISC)
2505 mode |= XM_MD_ENA_PROM;
2507 mode &= ~XM_MD_ENA_PROM;
2509 if (dev->flags & IFF_ALLMULTI)
2510 memset(filter, 0xff, sizeof(filter));
2512 memset(filter, 0, sizeof(filter));
2513 for (i = 0; list && i < count; i++, list = list->next) {
2515 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2517 filter[bit/8] |= 1 << (bit%8);
2521 xm_write32(hw, port, XM_MODE, mode);
2522 xm_outhash(hw, port, XM_HSM, filter);
2525 static void yukon_set_multicast(struct net_device *dev)
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 int port = skge->port;
2530 struct dev_mc_list *list = dev->mc_list;
2534 memset(filter, 0, sizeof(filter));
2536 reg = gma_read16(hw, port, GM_RX_CTRL);
2537 reg |= GM_RXCR_UCF_ENA;
2539 if (dev->flags & IFF_PROMISC) /* promiscuous */
2540 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2541 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2542 memset(filter, 0xff, sizeof(filter));
2543 else if (dev->mc_count == 0) /* no multicast */
2544 reg &= ~GM_RXCR_MCF_ENA;
2547 reg |= GM_RXCR_MCF_ENA;
2549 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2550 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2551 filter[bit/8] |= 1 << (bit%8);
2556 gma_write16(hw, port, GM_MC_ADDR_H1,
2557 (u16)filter[0] | ((u16)filter[1] << 8));
2558 gma_write16(hw, port, GM_MC_ADDR_H2,
2559 (u16)filter[2] | ((u16)filter[3] << 8));
2560 gma_write16(hw, port, GM_MC_ADDR_H3,
2561 (u16)filter[4] | ((u16)filter[5] << 8));
2562 gma_write16(hw, port, GM_MC_ADDR_H4,
2563 (u16)filter[6] | ((u16)filter[7] << 8));
2565 gma_write16(hw, port, GM_RX_CTRL, reg);
2568 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2570 if (hw->chip_id == CHIP_ID_GENESIS)
2571 return status >> XMR_FS_LEN_SHIFT;
2573 return status >> GMR_FS_LEN_SHIFT;
2576 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2578 if (hw->chip_id == CHIP_ID_GENESIS)
2579 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2581 return (status & GMR_FS_ANY_ERR) ||
2582 (status & GMR_FS_RX_OK) == 0;
2586 /* Get receive buffer from descriptor.
2587 * Handles copy of small buffers and reallocation failures
2589 static struct sk_buff *skge_rx_get(struct net_device *dev,
2590 struct skge_element *e,
2591 u32 control, u32 status, u16 csum)
2593 struct skge_port *skge = netdev_priv(dev);
2594 struct sk_buff *skb;
2595 u16 len = control & BMU_BBC;
2597 if (unlikely(netif_msg_rx_status(skge)))
2598 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2599 dev->name, e - skge->rx_ring.start,
2602 if (len > skge->rx_buf_size)
2605 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2608 if (bad_phy_status(skge->hw, status))
2611 if (phy_length(skge->hw, status) != len)
2614 if (len < RX_COPY_THRESHOLD) {
2615 skb = netdev_alloc_skb(dev, len + 2);
2619 skb_reserve(skb, 2);
2620 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2621 pci_unmap_addr(e, mapaddr),
2622 len, PCI_DMA_FROMDEVICE);
2623 memcpy(skb->data, e->skb->data, len);
2624 pci_dma_sync_single_for_device(skge->hw->pdev,
2625 pci_unmap_addr(e, mapaddr),
2626 len, PCI_DMA_FROMDEVICE);
2627 skge_rx_reuse(e, skge->rx_buf_size);
2629 struct sk_buff *nskb;
2630 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2634 skb_reserve(nskb, NET_IP_ALIGN);
2635 pci_unmap_single(skge->hw->pdev,
2636 pci_unmap_addr(e, mapaddr),
2637 pci_unmap_len(e, maplen),
2638 PCI_DMA_FROMDEVICE);
2640 prefetch(skb->data);
2641 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2645 if (skge->rx_csum) {
2647 skb->ip_summed = CHECKSUM_HW;
2650 skb->protocol = eth_type_trans(skb, dev);
2655 if (netif_msg_rx_err(skge))
2656 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2657 dev->name, e - skge->rx_ring.start,
2660 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2661 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2662 skge->net_stats.rx_length_errors++;
2663 if (status & XMR_FS_FRA_ERR)
2664 skge->net_stats.rx_frame_errors++;
2665 if (status & XMR_FS_FCS_ERR)
2666 skge->net_stats.rx_crc_errors++;
2668 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2669 skge->net_stats.rx_length_errors++;
2670 if (status & GMR_FS_FRAGMENT)
2671 skge->net_stats.rx_frame_errors++;
2672 if (status & GMR_FS_CRC_ERR)
2673 skge->net_stats.rx_crc_errors++;
2677 skge_rx_reuse(e, skge->rx_buf_size);
2681 /* Free all buffers in Tx ring which are no longer owned by device */
2682 static void skge_txirq(struct net_device *dev)
2684 struct skge_port *skge = netdev_priv(dev);
2685 struct skge_ring *ring = &skge->tx_ring;
2686 struct skge_element *e;
2690 spin_lock(&skge->tx_lock);
2691 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2692 struct skge_tx_desc *td = e->desc;
2694 if (td->control & BMU_OWN)
2697 skge_tx_free(skge, e, td->control);
2699 skge->tx_ring.to_clean = e;
2701 if (netif_queue_stopped(skge->netdev)
2702 && skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2703 netif_wake_queue(skge->netdev);
2705 spin_unlock(&skge->tx_lock);
2708 static int skge_poll(struct net_device *dev, int *budget)
2710 struct skge_port *skge = netdev_priv(dev);
2711 struct skge_hw *hw = skge->hw;
2712 struct skge_ring *ring = &skge->rx_ring;
2713 struct skge_element *e;
2714 int to_do = min(dev->quota, *budget);
2717 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2718 struct skge_rx_desc *rd = e->desc;
2719 struct sk_buff *skb;
2723 control = rd->control;
2724 if (control & BMU_OWN)
2727 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
2729 dev->last_rx = jiffies;
2730 netif_receive_skb(skb);
2737 /* restart receiver */
2739 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2741 *budget -= work_done;
2742 dev->quota -= work_done;
2744 if (work_done >= to_do)
2745 return 1; /* not done */
2747 netif_rx_complete(dev);
2749 spin_lock_irq(&hw->hw_lock);
2750 hw->intr_mask |= rxirqmask[skge->port];
2751 skge_write32(hw, B0_IMSK, hw->intr_mask);
2752 skge_read32(hw, B0_IMSK);
2753 spin_unlock_irq(&hw->hw_lock);
2758 /* Parity errors seem to happen when Genesis is connected to a switch
2759 * with no other ports present. Heartbeat error??
2761 static void skge_mac_parity(struct skge_hw *hw, int port)
2763 struct net_device *dev = hw->dev[port];
2766 struct skge_port *skge = netdev_priv(dev);
2767 ++skge->net_stats.tx_heartbeat_errors;
2770 if (hw->chip_id == CHIP_ID_GENESIS)
2771 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2774 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2775 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2776 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2777 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2780 static void skge_mac_intr(struct skge_hw *hw, int port)
2782 if (hw->chip_id == CHIP_ID_GENESIS)
2783 genesis_mac_intr(hw, port);
2785 yukon_mac_intr(hw, port);
2788 /* Handle device specific framing and timeout interrupts */
2789 static void skge_error_irq(struct skge_hw *hw)
2791 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2793 if (hw->chip_id == CHIP_ID_GENESIS) {
2794 /* clear xmac errors */
2795 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2796 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2797 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2798 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2800 /* Timestamp (unused) overflow */
2801 if (hwstatus & IS_IRQ_TIST_OV)
2802 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2805 if (hwstatus & IS_RAM_RD_PAR) {
2806 printk(KERN_ERR PFX "Ram read data parity error\n");
2807 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2810 if (hwstatus & IS_RAM_WR_PAR) {
2811 printk(KERN_ERR PFX "Ram write data parity error\n");
2812 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2815 if (hwstatus & IS_M1_PAR_ERR)
2816 skge_mac_parity(hw, 0);
2818 if (hwstatus & IS_M2_PAR_ERR)
2819 skge_mac_parity(hw, 1);
2821 if (hwstatus & IS_R1_PAR_ERR) {
2822 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2824 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2827 if (hwstatus & IS_R2_PAR_ERR) {
2828 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2830 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2833 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2834 u16 pci_status, pci_cmd;
2836 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2837 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2839 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2840 pci_name(hw->pdev), pci_cmd, pci_status);
2842 /* Write the error bits back to clear them. */
2843 pci_status &= PCI_STATUS_ERROR_BITS;
2844 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2845 pci_write_config_word(hw->pdev, PCI_COMMAND,
2846 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2847 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2848 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2850 /* if error still set then just ignore it */
2851 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2852 if (hwstatus & IS_IRQ_STAT) {
2853 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
2854 hw->intr_mask &= ~IS_HW_ERR;
2860 * Interrupt from PHY are handled in work queue
2861 * because accessing phy registers requires spin wait which might
2862 * cause excess interrupt latency.
2864 static void skge_extirq(void *arg)
2866 struct skge_hw *hw = arg;
2869 mutex_lock(&hw->phy_mutex);
2870 for (port = 0; port < hw->ports; port++) {
2871 struct net_device *dev = hw->dev[port];
2872 struct skge_port *skge = netdev_priv(dev);
2874 if (netif_running(dev)) {
2875 if (hw->chip_id != CHIP_ID_GENESIS)
2876 yukon_phy_intr(skge);
2878 bcom_phy_intr(skge);
2881 mutex_unlock(&hw->phy_mutex);
2883 spin_lock_irq(&hw->hw_lock);
2884 hw->intr_mask |= IS_EXT_REG;
2885 skge_write32(hw, B0_IMSK, hw->intr_mask);
2886 skge_read32(hw, B0_IMSK);
2887 spin_unlock_irq(&hw->hw_lock);
2890 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2892 struct skge_hw *hw = dev_id;
2895 /* Reading this register masks IRQ */
2896 status = skge_read32(hw, B0_SP_ISRC);
2900 spin_lock(&hw->hw_lock);
2901 status &= hw->intr_mask;
2902 if (status & IS_EXT_REG) {
2903 hw->intr_mask &= ~IS_EXT_REG;
2904 schedule_work(&hw->phy_work);
2907 if (status & IS_XA1_F) {
2908 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F);
2909 skge_txirq(hw->dev[0]);
2912 if (status & IS_R1_F) {
2913 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2914 hw->intr_mask &= ~IS_R1_F;
2915 netif_rx_schedule(hw->dev[0]);
2918 if (status & IS_PA_TO_TX1)
2919 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2921 if (status & IS_PA_TO_RX1) {
2922 struct skge_port *skge = netdev_priv(hw->dev[0]);
2924 ++skge->net_stats.rx_over_errors;
2925 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2929 if (status & IS_MAC1)
2930 skge_mac_intr(hw, 0);
2933 if (status & IS_XA2_F) {
2934 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F);
2935 skge_txirq(hw->dev[1]);
2938 if (status & IS_R2_F) {
2939 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2940 hw->intr_mask &= ~IS_R2_F;
2941 netif_rx_schedule(hw->dev[1]);
2944 if (status & IS_PA_TO_RX2) {
2945 struct skge_port *skge = netdev_priv(hw->dev[1]);
2946 ++skge->net_stats.rx_over_errors;
2947 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2950 if (status & IS_PA_TO_TX2)
2951 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2953 if (status & IS_MAC2)
2954 skge_mac_intr(hw, 1);
2957 if (status & IS_HW_ERR)
2960 skge_write32(hw, B0_IMSK, hw->intr_mask);
2961 skge_read32(hw, B0_IMSK);
2962 spin_unlock(&hw->hw_lock);
2967 #ifdef CONFIG_NET_POLL_CONTROLLER
2968 static void skge_netpoll(struct net_device *dev)
2970 struct skge_port *skge = netdev_priv(dev);
2972 disable_irq(dev->irq);
2973 skge_intr(dev->irq, skge->hw, NULL);
2974 enable_irq(dev->irq);
2978 static int skge_set_mac_address(struct net_device *dev, void *p)
2980 struct skge_port *skge = netdev_priv(dev);
2981 struct skge_hw *hw = skge->hw;
2982 unsigned port = skge->port;
2983 const struct sockaddr *addr = p;
2985 if (!is_valid_ether_addr(addr->sa_data))
2986 return -EADDRNOTAVAIL;
2988 mutex_lock(&hw->phy_mutex);
2989 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2990 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2991 dev->dev_addr, ETH_ALEN);
2992 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2993 dev->dev_addr, ETH_ALEN);
2995 if (hw->chip_id == CHIP_ID_GENESIS)
2996 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2998 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2999 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3001 mutex_unlock(&hw->phy_mutex);
3006 static const struct {
3010 { CHIP_ID_GENESIS, "Genesis" },
3011 { CHIP_ID_YUKON, "Yukon" },
3012 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3013 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3016 static const char *skge_board_name(const struct skge_hw *hw)
3019 static char buf[16];
3021 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3022 if (skge_chips[i].id == hw->chip_id)
3023 return skge_chips[i].name;
3025 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3031 * Setup the board data structure, but don't bring up
3034 static int skge_reset(struct skge_hw *hw)
3037 u16 ctst, pci_status;
3038 u8 t8, mac_cfg, pmd_type, phy_type;
3041 ctst = skge_read16(hw, B0_CTST);
3044 skge_write8(hw, B0_CTST, CS_RST_SET);
3045 skge_write8(hw, B0_CTST, CS_RST_CLR);
3047 /* clear PCI errors, if any */
3048 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3049 skge_write8(hw, B2_TST_CTRL2, 0);
3051 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3052 pci_write_config_word(hw->pdev, PCI_STATUS,
3053 pci_status | PCI_STATUS_ERROR_BITS);
3054 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3055 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3057 /* restore CLK_RUN bits (for Yukon-Lite) */
3058 skge_write16(hw, B0_CTST,
3059 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3061 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3062 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3063 pmd_type = skge_read8(hw, B2_PMD_TYP);
3064 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3066 switch (hw->chip_id) {
3067 case CHIP_ID_GENESIS:
3070 hw->phy_addr = PHY_ADDR_BCOM;
3073 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3074 pci_name(hw->pdev), phy_type);
3080 case CHIP_ID_YUKON_LITE:
3081 case CHIP_ID_YUKON_LP:
3082 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3085 hw->phy_addr = PHY_ADDR_MARV;
3089 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3090 pci_name(hw->pdev), hw->chip_id);
3094 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3095 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3096 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3098 /* read the adapters RAM size */
3099 t8 = skge_read8(hw, B2_E_0);
3100 if (hw->chip_id == CHIP_ID_GENESIS) {
3102 /* special case: 4 x 64k x 36, offset = 0x80000 */
3103 hw->ram_size = 0x100000;
3104 hw->ram_offset = 0x80000;
3106 hw->ram_size = t8 * 512;
3109 hw->ram_size = 0x20000;
3111 hw->ram_size = t8 * 4096;
3113 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3115 hw->intr_mask |= IS_PORT_2;
3117 if (hw->chip_id == CHIP_ID_GENESIS)
3120 /* switch power to VCC (WA for VAUX problem) */
3121 skge_write8(hw, B0_POWER_CTRL,
3122 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3124 /* avoid boards with stuck Hardware error bits */
3125 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3126 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3127 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3128 hw->intr_mask &= ~IS_HW_ERR;
3131 /* Clear PHY COMA */
3132 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3133 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3134 reg &= ~PCI_PHY_COMA;
3135 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3136 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3139 for (i = 0; i < hw->ports; i++) {
3140 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3141 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3145 /* turn off hardware timer (unused) */
3146 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3147 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3148 skge_write8(hw, B0_LED, LED_STAT_ON);
3150 /* enable the Tx Arbiters */
3151 for (i = 0; i < hw->ports; i++)
3152 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3154 /* Initialize ram interface */
3155 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3157 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3158 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3159 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3160 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3161 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3162 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3163 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3164 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3165 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3166 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3167 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3168 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3170 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3172 /* Set interrupt moderation for Transmit only
3173 * Receive interrupts avoided by NAPI
3175 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3176 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3177 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3179 skge_write32(hw, B0_IMSK, hw->intr_mask);
3181 mutex_lock(&hw->phy_mutex);
3182 for (i = 0; i < hw->ports; i++) {
3183 if (hw->chip_id == CHIP_ID_GENESIS)
3184 genesis_reset(hw, i);
3188 mutex_unlock(&hw->phy_mutex);
3193 /* Initialize network device */
3194 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3197 struct skge_port *skge;
3198 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3201 printk(KERN_ERR "skge etherdev alloc failed");
3205 SET_MODULE_OWNER(dev);
3206 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3207 dev->open = skge_up;
3208 dev->stop = skge_down;
3209 dev->do_ioctl = skge_ioctl;
3210 dev->hard_start_xmit = skge_xmit_frame;
3211 dev->get_stats = skge_get_stats;
3212 if (hw->chip_id == CHIP_ID_GENESIS)
3213 dev->set_multicast_list = genesis_set_multicast;
3215 dev->set_multicast_list = yukon_set_multicast;
3217 dev->set_mac_address = skge_set_mac_address;
3218 dev->change_mtu = skge_change_mtu;
3219 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3220 dev->tx_timeout = skge_tx_timeout;
3221 dev->watchdog_timeo = TX_WATCHDOG;
3222 dev->poll = skge_poll;
3223 dev->weight = NAPI_WEIGHT;
3224 #ifdef CONFIG_NET_POLL_CONTROLLER
3225 dev->poll_controller = skge_netpoll;
3227 dev->irq = hw->pdev->irq;
3228 dev->features = NETIF_F_LLTX;
3230 dev->features |= NETIF_F_HIGHDMA;
3232 skge = netdev_priv(dev);
3235 skge->msg_enable = netif_msg_init(debug, default_msg);
3236 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3237 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3239 /* Auto speed and flow control */
3240 skge->autoneg = AUTONEG_ENABLE;
3241 skge->flow_control = FLOW_MODE_SYMMETRIC;
3244 skge->advertising = skge_supported_modes(hw);
3246 hw->dev[port] = dev;
3250 spin_lock_init(&skge->tx_lock);
3252 if (hw->chip_id != CHIP_ID_GENESIS) {
3253 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3257 /* read the mac address */
3258 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3259 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3261 /* device is off until link detection */
3262 netif_carrier_off(dev);
3263 netif_stop_queue(dev);
3268 static void __devinit skge_show_addr(struct net_device *dev)
3270 const struct skge_port *skge = netdev_priv(dev);
3272 if (netif_msg_probe(skge))
3273 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3275 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3276 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3279 static int __devinit skge_probe(struct pci_dev *pdev,
3280 const struct pci_device_id *ent)
3282 struct net_device *dev, *dev1;
3284 int err, using_dac = 0;
3286 err = pci_enable_device(pdev);
3288 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3293 err = pci_request_regions(pdev, DRV_NAME);
3295 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3297 goto err_out_disable_pdev;
3300 pci_set_master(pdev);
3302 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3304 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3305 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3307 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3311 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3313 goto err_out_free_regions;
3317 /* byte swap descriptors in hardware */
3321 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3322 reg |= PCI_REV_DESC;
3323 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3328 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3330 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3332 goto err_out_free_regions;
3336 mutex_init(&hw->phy_mutex);
3337 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3338 spin_lock_init(&hw->hw_lock);
3340 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3342 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3344 goto err_out_free_hw;
3347 err = skge_reset(hw);
3349 goto err_out_iounmap;
3351 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3352 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3353 skge_board_name(hw), hw->chip_rev);
3355 dev = skge_devinit(hw, 0, using_dac);
3357 goto err_out_led_off;
3359 if (!is_valid_ether_addr(dev->dev_addr)) {
3360 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3363 goto err_out_free_netdev;
3366 err = register_netdev(dev);
3368 printk(KERN_ERR PFX "%s: cannot register net device\n",
3370 goto err_out_free_netdev;
3373 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3375 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3376 dev->name, pdev->irq);
3377 goto err_out_unregister;
3379 skge_show_addr(dev);
3381 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3382 if (register_netdev(dev1) == 0)
3383 skge_show_addr(dev1);
3385 /* Failure to register second port need not be fatal */
3386 printk(KERN_WARNING PFX "register of second port failed\n");
3391 pci_set_drvdata(pdev, hw);
3396 unregister_netdev(dev);
3397 err_out_free_netdev:
3400 skge_write16(hw, B0_LED, LED_STAT_OFF);
3405 err_out_free_regions:
3406 pci_release_regions(pdev);
3407 err_out_disable_pdev:
3408 pci_disable_device(pdev);
3409 pci_set_drvdata(pdev, NULL);
3414 static void __devexit skge_remove(struct pci_dev *pdev)
3416 struct skge_hw *hw = pci_get_drvdata(pdev);
3417 struct net_device *dev0, *dev1;
3422 if ((dev1 = hw->dev[1]))
3423 unregister_netdev(dev1);
3425 unregister_netdev(dev0);
3427 spin_lock_irq(&hw->hw_lock);
3429 skge_write32(hw, B0_IMSK, 0);
3430 skge_read32(hw, B0_IMSK);
3431 spin_unlock_irq(&hw->hw_lock);
3433 skge_write16(hw, B0_LED, LED_STAT_OFF);
3434 skge_write8(hw, B0_CTST, CS_RST_SET);
3436 flush_scheduled_work();
3438 free_irq(pdev->irq, hw);
3439 pci_release_regions(pdev);
3440 pci_disable_device(pdev);
3447 pci_set_drvdata(pdev, NULL);
3451 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3453 struct skge_hw *hw = pci_get_drvdata(pdev);
3456 pci_save_state(pdev);
3457 for (i = 0; i < hw->ports; i++) {
3458 struct net_device *dev = hw->dev[i];
3460 if (netif_running(dev)) {
3461 struct skge_port *skge = netdev_priv(dev);
3463 netif_carrier_off(dev);
3465 netif_stop_queue(dev);
3470 netif_device_detach(dev);
3473 skge_write32(hw, B0_IMSK, 0);
3474 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3475 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3480 static int skge_resume(struct pci_dev *pdev)
3482 struct skge_hw *hw = pci_get_drvdata(pdev);
3485 pci_set_power_state(pdev, PCI_D0);
3486 pci_restore_state(pdev);
3487 pci_enable_wake(pdev, PCI_D0, 0);
3489 err = skge_reset(hw);
3493 for (i = 0; i < hw->ports; i++) {
3494 struct net_device *dev = hw->dev[i];
3496 netif_device_attach(dev);
3497 if (netif_running(dev)) {
3501 printk(KERN_ERR PFX "%s: could not up: %d\n",
3513 static struct pci_driver skge_driver = {
3515 .id_table = skge_id_table,
3516 .probe = skge_probe,
3517 .remove = __devexit_p(skge_remove),
3519 .suspend = skge_suspend,
3520 .resume = skge_resume,
3524 static int __init skge_init_module(void)
3526 return pci_register_driver(&skge_driver);
3529 static void __exit skge_cleanup_module(void)
3531 pci_unregister_driver(&skge_driver);
3534 module_init(skge_init_module);
3535 module_exit(skge_cleanup_module);