2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
18 See the file COPYING in this distribution for more information.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/netdevice.h>
27 #include <linux/rtnetlink.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/pci.h>
31 #include <linux/mii.h>
32 #include <linux/delay.h>
33 #include <linux/crc32.h>
34 #include <linux/dma-mapping.h>
37 #define PHY_MAX_ADDR 32
38 #define PHY_ID_ANY 0x1f
39 #define MII_REG_ANY 0x1f
41 #define DRV_VERSION "1.4"
42 #define DRV_NAME "sis190"
43 #define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
45 #define sis190_rx_skb netif_rx
46 #define sis190_rx_quota(count, quota) count
48 #define MAC_ADDR_LEN 6
50 #define NUM_TX_DESC 64 /* [8..1024] */
51 #define NUM_RX_DESC 64 /* [8..8192] */
52 #define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
53 #define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
54 #define RX_BUF_SIZE 1536
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
58 #define SIS190_TX_TIMEOUT (6*HZ)
59 #define SIS190_PHY_TIMEOUT (10*HZ)
60 #define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
61 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
64 /* Enhanced PHY access register bit definitions */
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
67 #define EhnMIIdataShift 16
68 #define EhnMIIpmdShift 6 /* 7016 only */
69 #define EhnMIIregShift 11
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
73 /* Write/read MMIO register */
74 #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
75 #define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
76 #define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
77 #define SIS_R8(reg) readb (ioaddr + (reg))
78 #define SIS_R16(reg) readw (ioaddr + (reg))
79 #define SIS_R32(reg) readl (ioaddr + (reg))
81 #define SIS_PCI_COMMIT() SIS_R32(IntrControl)
83 enum sis190_registers {
85 TxDescStartAddr = 0x04,
86 rsv0 = 0x08, // reserved
87 TxSts = 0x0c, // unused (Control/Status)
89 RxDescStartAddr = 0x14,
90 rsv1 = 0x18, // reserved
91 RxSts = 0x1c, // unused
95 IntrTimer = 0x2c, // unused (Interupt Timer)
96 PMControl = 0x30, // unused (Power Mgmt Control/Status)
97 rsv2 = 0x34, // reserved
100 StationControl = 0x40,
102 GIoCR = 0x48, // unused (GMAC IO Compensation)
103 GIoCtrl = 0x4c, // unused (GMAC IO Control)
105 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
106 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
107 rsv3 = 0x5c, // reserved
111 // Undocumented = 0x6c,
113 RxWolData = 0x74, // unused (Rx WOL Data Access)
114 RxMPSControl = 0x78, // unused (Rx MPS Control)
115 rsv4 = 0x7c, // reserved
118 enum sis190_register_content {
120 SoftInt = 0x40000000, // unused
121 Timeup = 0x20000000, // unused
122 PauseFrame = 0x00080000, // unused
123 MagicPacket = 0x00040000, // unused
124 WakeupFrame = 0x00020000, // unused
125 LinkChange = 0x00010000,
126 RxQEmpty = 0x00000080,
128 TxQ1Empty = 0x00000020, // unused
129 TxQ1Int = 0x00000010,
130 TxQ0Empty = 0x00000008, // unused
131 TxQ0Int = 0x00000004,
137 CmdRxEnb = 0x08, // unused
139 RxBufEmpty = 0x01, // unused
142 Cfg9346_Lock = 0x00, // unused
143 Cfg9346_Unlock = 0xc0, // unused
146 AcceptErr = 0x20, // unused
147 AcceptRunt = 0x10, // unused
148 AcceptBroadcast = 0x0800,
149 AcceptMulticast = 0x0400,
150 AcceptMyPhys = 0x0200,
151 AcceptAllPhys = 0x0100,
155 RxCfgDMAShift = 8, // 0x1a in RxControl ?
158 TxInterFrameGapShift = 24,
159 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
161 LinkStatus = 0x02, // unused
162 FullDup = 0x01, // unused
165 TBILinkOK = 0x02000000, // unused
182 enum _DescStatusBit {
184 OWNbit = 0x80000000, // RXOWN/TXOWN
185 INTbit = 0x40000000, // RXINT/TXINT
186 CRCbit = 0x00020000, // CRCOFF/CRCEN
187 PADbit = 0x00010000, // PREADD/PADEN
189 RingEnd = 0x80000000,
191 LSEN = 0x08000000, // TSO ? -- FR
210 ColCountMask = 0x0000ffff,
224 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
233 RxSizeMask = 0x0000ffff
235 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
236 * provide two (unused with Linux) Tx queues. No publically
237 * available documentation alas.
241 enum sis190_eeprom_access_register_bits {
242 EECS = 0x00000001, // unused
243 EECLK = 0x00000002, // unused
244 EEDO = 0x00000008, // unused
245 EEDI = 0x00000004, // unused
248 EEWOP = 0x00000100 // unused
251 /* EEPROM Addresses */
252 enum sis190_eeprom_address {
253 EEPROMSignature = 0x00,
254 EEPROMCLK = 0x01, // unused
259 enum sis190_feature {
265 struct sis190_private {
266 void __iomem *mmio_addr;
267 struct pci_dev *pci_dev;
268 struct net_device *dev;
277 struct RxDesc *RxDescRing;
278 struct TxDesc *TxDescRing;
279 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
280 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
281 struct work_struct phy_task;
282 struct timer_list timer;
284 struct mii_if_info mii_if;
285 struct list_head first_phy;
291 struct list_head list;
298 enum sis190_phy_type {
305 static struct mii_chip_info {
310 } mii_chip_table[] = {
311 { "Atheros PHY", { 0x004d, 0xd010 }, LAN, 0 },
312 { "Atheros PHY AR8012", { 0x004d, 0xd020 }, LAN, 0 },
313 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
314 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
315 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
316 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
317 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
321 static const struct {
323 } sis_chip_info[] = {
324 { "SiS 190 PCI Fast Ethernet adapter" },
325 { "SiS 191 PCI Gigabit Ethernet adapter" },
328 static DEFINE_PCI_DEVICE_TABLE(sis190_pci_tbl) = {
329 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
334 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
336 static int rx_copybreak = 200;
342 MODULE_DESCRIPTION("SiS sis190/191 Gigabit Ethernet driver");
343 module_param(rx_copybreak, int, 0);
344 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
345 module_param_named(debug, debug.msg_enable, int, 0);
346 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
347 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
348 MODULE_VERSION(DRV_VERSION);
349 MODULE_LICENSE("GPL");
351 static const u32 sis190_intr_mask =
352 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
355 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
356 * The chips use a 64 element hash table based on the Ethernet CRC.
358 static const int multicast_filter_limit = 32;
360 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
364 SIS_W32(GMIIControl, ctl);
368 for (i = 0; i < 100; i++) {
369 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
375 pr_err("PHY command failed !\n");
378 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
380 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
381 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
382 (((u32) val) << EhnMIIdataShift));
385 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
387 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
388 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
390 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
393 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
395 struct sis190_private *tp = netdev_priv(dev);
397 mdio_write(tp->mmio_addr, phy_id, reg, val);
400 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
402 struct sis190_private *tp = netdev_priv(dev);
404 return mdio_read(tp->mmio_addr, phy_id, reg);
407 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
409 mdio_read(ioaddr, phy_id, reg);
410 return mdio_read(ioaddr, phy_id, reg);
413 static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
418 if (!(SIS_R32(ROMControl) & 0x0002))
421 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
423 for (i = 0; i < 200; i++) {
424 if (!(SIS_R32(ROMInterface) & EEREQ)) {
425 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
434 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
436 SIS_W32(IntrMask, 0x00);
437 SIS_W32(IntrStatus, 0xffffffff);
441 static void sis190_asic_down(void __iomem *ioaddr)
443 /* Stop the chip's Tx and Rx DMA processes. */
445 SIS_W32(TxControl, 0x1a00);
446 SIS_W32(RxControl, 0x1a00);
448 sis190_irq_mask_and_ack(ioaddr);
451 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
453 desc->size |= cpu_to_le32(RingEnd);
456 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
458 u32 eor = le32_to_cpu(desc->size) & RingEnd;
461 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
463 desc->status = cpu_to_le32(OWNbit | INTbit);
466 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
469 desc->addr = cpu_to_le32(mapping);
470 sis190_give_to_asic(desc, rx_buf_sz);
473 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
476 desc->addr = cpu_to_le32(0xdeadbeef);
477 desc->size &= cpu_to_le32(RingEnd);
482 static struct sk_buff *sis190_alloc_rx_skb(struct sis190_private *tp,
485 u32 rx_buf_sz = tp->rx_buf_sz;
488 skb = netdev_alloc_skb(tp->dev, rx_buf_sz);
492 mapping = pci_map_single(tp->pci_dev, skb->data, tp->rx_buf_sz,
494 sis190_map_to_asic(desc, mapping, rx_buf_sz);
496 sis190_make_unusable_by_asic(desc);
501 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
506 for (cur = start; cur < end; cur++) {
507 unsigned int i = cur % NUM_RX_DESC;
509 if (tp->Rx_skbuff[i])
512 tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp, tp->RxDescRing + i);
514 if (!tp->Rx_skbuff[i])
520 static bool sis190_try_rx_copy(struct sis190_private *tp,
521 struct sk_buff **sk_buff, int pkt_size,
527 if (pkt_size >= rx_copybreak)
530 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
534 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, tp->rx_buf_sz,
536 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
543 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
545 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
547 if ((status & CRCOK) && !(status & ErrMask))
550 if (!(status & CRCOK))
551 stats->rx_crc_errors++;
552 else if (status & OVRUN)
553 stats->rx_over_errors++;
554 else if (status & (SHORT | LIMIT))
555 stats->rx_length_errors++;
556 else if (status & (MIIER | NIBON | COLON))
557 stats->rx_frame_errors++;
563 static int sis190_rx_interrupt(struct net_device *dev,
564 struct sis190_private *tp, void __iomem *ioaddr)
566 struct net_device_stats *stats = &dev->stats;
567 u32 rx_left, cur_rx = tp->cur_rx;
570 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
571 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
573 for (; rx_left > 0; rx_left--, cur_rx++) {
574 unsigned int entry = cur_rx % NUM_RX_DESC;
575 struct RxDesc *desc = tp->RxDescRing + entry;
578 if (le32_to_cpu(desc->status) & OWNbit)
581 status = le32_to_cpu(desc->PSize);
583 //netif_info(tp, intr, dev, "Rx PSize = %08x\n", status);
585 if (sis190_rx_pkt_err(status, stats) < 0)
586 sis190_give_to_asic(desc, tp->rx_buf_sz);
588 struct sk_buff *skb = tp->Rx_skbuff[entry];
589 dma_addr_t addr = le32_to_cpu(desc->addr);
590 int pkt_size = (status & RxSizeMask) - 4;
591 struct pci_dev *pdev = tp->pci_dev;
593 if (unlikely(pkt_size > tp->rx_buf_sz)) {
594 netif_info(tp, intr, dev,
595 "(frag) status = %08x\n", status);
597 stats->rx_length_errors++;
598 sis190_give_to_asic(desc, tp->rx_buf_sz);
603 if (sis190_try_rx_copy(tp, &skb, pkt_size, addr)) {
604 pci_dma_sync_single_for_device(pdev, addr,
605 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
606 sis190_give_to_asic(desc, tp->rx_buf_sz);
608 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
610 tp->Rx_skbuff[entry] = NULL;
611 sis190_make_unusable_by_asic(desc);
614 skb_put(skb, pkt_size);
615 skb->protocol = eth_type_trans(skb, dev);
620 stats->rx_bytes += pkt_size;
621 if ((status & BCAST) == MCAST)
625 count = cur_rx - tp->cur_rx;
628 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
630 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
631 tp->dirty_rx += delta;
633 if ((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx)
634 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
639 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
644 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
646 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
648 memset(desc, 0x00, sizeof(*desc));
651 static inline int sis190_tx_pkt_err(u32 status, struct net_device_stats *stats)
653 #define TxErrMask (WND | TABRT | FIFO | LINK)
655 if (!unlikely(status & TxErrMask))
659 stats->tx_window_errors++;
661 stats->tx_aborted_errors++;
663 stats->tx_fifo_errors++;
665 stats->tx_carrier_errors++;
672 static void sis190_tx_interrupt(struct net_device *dev,
673 struct sis190_private *tp, void __iomem *ioaddr)
675 struct net_device_stats *stats = &dev->stats;
676 u32 pending, dirty_tx = tp->dirty_tx;
678 * It would not be needed if queueing was allowed to be enabled
679 * again too early (hint: think preempt and unclocked smp systems).
681 unsigned int queue_stopped;
684 pending = tp->cur_tx - dirty_tx;
685 queue_stopped = (pending == NUM_TX_DESC);
687 for (; pending; pending--, dirty_tx++) {
688 unsigned int entry = dirty_tx % NUM_TX_DESC;
689 struct TxDesc *txd = tp->TxDescRing + entry;
690 u32 status = le32_to_cpu(txd->status);
696 skb = tp->Tx_skbuff[entry];
698 if (likely(sis190_tx_pkt_err(status, stats) == 0)) {
700 stats->tx_bytes += skb->len;
701 stats->collisions += ((status & ColCountMask) - 1);
704 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
705 tp->Tx_skbuff[entry] = NULL;
706 dev_kfree_skb_irq(skb);
709 if (tp->dirty_tx != dirty_tx) {
710 tp->dirty_tx = dirty_tx;
713 netif_wake_queue(dev);
718 * The interrupt handler does all of the Rx thread work and cleans up after
721 static irqreturn_t sis190_interrupt(int irq, void *__dev)
723 struct net_device *dev = __dev;
724 struct sis190_private *tp = netdev_priv(dev);
725 void __iomem *ioaddr = tp->mmio_addr;
726 unsigned int handled = 0;
729 status = SIS_R32(IntrStatus);
731 if ((status == 0xffffffff) || !status)
736 if (unlikely(!netif_running(dev))) {
737 sis190_asic_down(ioaddr);
741 SIS_W32(IntrStatus, status);
743 // netif_info(tp, intr, dev, "status = %08x\n", status);
745 if (status & LinkChange) {
746 netif_info(tp, intr, dev, "link change\n");
747 schedule_work(&tp->phy_task);
751 sis190_rx_interrupt(dev, tp, ioaddr);
753 if (status & TxQ0Int)
754 sis190_tx_interrupt(dev, tp, ioaddr);
756 return IRQ_RETVAL(handled);
759 #ifdef CONFIG_NET_POLL_CONTROLLER
760 static void sis190_netpoll(struct net_device *dev)
762 struct sis190_private *tp = netdev_priv(dev);
763 struct pci_dev *pdev = tp->pci_dev;
765 disable_irq(pdev->irq);
766 sis190_interrupt(pdev->irq, dev);
767 enable_irq(pdev->irq);
771 static void sis190_free_rx_skb(struct sis190_private *tp,
772 struct sk_buff **sk_buff, struct RxDesc *desc)
774 struct pci_dev *pdev = tp->pci_dev;
776 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
778 dev_kfree_skb(*sk_buff);
780 sis190_make_unusable_by_asic(desc);
783 static void sis190_rx_clear(struct sis190_private *tp)
787 for (i = 0; i < NUM_RX_DESC; i++) {
788 if (!tp->Rx_skbuff[i])
790 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
794 static void sis190_init_ring_indexes(struct sis190_private *tp)
796 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
799 static int sis190_init_ring(struct net_device *dev)
801 struct sis190_private *tp = netdev_priv(dev);
803 sis190_init_ring_indexes(tp);
805 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
806 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
808 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
811 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
820 static void sis190_set_rx_mode(struct net_device *dev)
822 struct sis190_private *tp = netdev_priv(dev);
823 void __iomem *ioaddr = tp->mmio_addr;
825 u32 mc_filter[2]; /* Multicast hash filter */
828 if (dev->flags & IFF_PROMISC) {
830 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
832 mc_filter[1] = mc_filter[0] = 0xffffffff;
833 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
834 (dev->flags & IFF_ALLMULTI)) {
835 /* Too many to filter perfectly -- accept all multicasts. */
836 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
837 mc_filter[1] = mc_filter[0] = 0xffffffff;
839 struct dev_mc_list *mclist;
841 rx_mode = AcceptBroadcast | AcceptMyPhys;
842 mc_filter[1] = mc_filter[0] = 0;
843 netdev_for_each_mc_addr(mclist, dev) {
845 ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
846 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
847 rx_mode |= AcceptMulticast;
851 spin_lock_irqsave(&tp->lock, flags);
853 SIS_W16(RxMacControl, rx_mode | 0x2);
854 SIS_W32(RxHashTable, mc_filter[0]);
855 SIS_W32(RxHashTable + 4, mc_filter[1]);
857 spin_unlock_irqrestore(&tp->lock, flags);
860 static void sis190_soft_reset(void __iomem *ioaddr)
862 SIS_W32(IntrControl, 0x8000);
864 SIS_W32(IntrControl, 0x0);
865 sis190_asic_down(ioaddr);
868 static void sis190_hw_start(struct net_device *dev)
870 struct sis190_private *tp = netdev_priv(dev);
871 void __iomem *ioaddr = tp->mmio_addr;
873 sis190_soft_reset(ioaddr);
875 SIS_W32(TxDescStartAddr, tp->tx_dma);
876 SIS_W32(RxDescStartAddr, tp->rx_dma);
878 SIS_W32(IntrStatus, 0xffffffff);
879 SIS_W32(IntrMask, 0x0);
880 SIS_W32(GMIIControl, 0x0);
881 SIS_W32(TxMacControl, 0x60);
882 SIS_W16(RxMacControl, 0x02);
883 SIS_W32(RxHashTable, 0x0);
885 SIS_W32(RxWolCtrl, 0x0);
886 SIS_W32(RxWolData, 0x0);
890 sis190_set_rx_mode(dev);
892 /* Enable all known interrupts by setting the interrupt mask. */
893 SIS_W32(IntrMask, sis190_intr_mask);
895 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
896 SIS_W32(RxControl, 0x1a1d);
898 netif_start_queue(dev);
901 static void sis190_phy_task(struct work_struct *work)
903 struct sis190_private *tp =
904 container_of(work, struct sis190_private, phy_task);
905 struct net_device *dev = tp->dev;
906 void __iomem *ioaddr = tp->mmio_addr;
907 int phy_id = tp->mii_if.phy_id;
912 if (!netif_running(dev))
915 val = mdio_read(ioaddr, phy_id, MII_BMCR);
916 if (val & BMCR_RESET) {
917 // FIXME: needlessly high ? -- FR 02/07/2005
918 mod_timer(&tp->timer, jiffies + HZ/10);
919 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
920 BMSR_ANEGCOMPLETE)) {
921 netif_carrier_off(dev);
922 netif_warn(tp, link, dev, "auto-negotiating...\n");
923 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
931 { LPA_1000FULL, 0x07000c00 | 0x00001000,
932 "1000 Mbps Full Duplex" },
933 { LPA_1000HALF, 0x07000c00,
934 "1000 Mbps Half Duplex" },
935 { LPA_100FULL, 0x04000800 | 0x00001000,
936 "100 Mbps Full Duplex" },
937 { LPA_100HALF, 0x04000800,
938 "100 Mbps Half Duplex" },
939 { LPA_10FULL, 0x04000400 | 0x00001000,
940 "10 Mbps Full Duplex" },
941 { LPA_10HALF, 0x04000400,
942 "10 Mbps Half Duplex" },
943 { 0, 0x04000400, "unknown" }
945 u16 adv, autoexp, gigadv, gigrec;
947 val = mdio_read(ioaddr, phy_id, 0x1f);
948 netif_info(tp, link, dev, "mii ext = %04x\n", val);
950 val = mdio_read(ioaddr, phy_id, MII_LPA);
951 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
952 autoexp = mdio_read(ioaddr, phy_id, MII_EXPANSION);
953 netif_info(tp, link, dev, "mii lpa=%04x adv=%04x exp=%04x\n",
956 if (val & LPA_NPAGE && autoexp & EXPANSION_NWAY) {
957 /* check for gigabit speed */
958 gigadv = mdio_read(ioaddr, phy_id, MII_CTRL1000);
959 gigrec = mdio_read(ioaddr, phy_id, MII_STAT1000);
960 val = (gigadv & (gigrec >> 2));
961 if (val & ADVERTISE_1000FULL)
963 else if (val & ADVERTISE_1000HALF)
969 for (p = reg31; p->val; p++) {
970 if ((val & p->val) == p->val)
975 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
977 if ((tp->features & F_HAS_RGMII) &&
978 (tp->features & F_PHY_BCM5461)) {
979 // Set Tx Delay in RGMII mode.
980 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
982 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
983 p->ctl |= 0x03000000;
986 SIS_W32(StationControl, p->ctl);
988 if (tp->features & F_HAS_RGMII) {
989 SIS_W32(RGDelay, 0x0441);
990 SIS_W32(RGDelay, 0x0440);
993 tp->negotiated_lpa = p->val;
995 netif_info(tp, link, dev, "link on %s mode\n", p->msg);
996 netif_carrier_on(dev);
1003 static void sis190_phy_timer(unsigned long __opaque)
1005 struct net_device *dev = (struct net_device *)__opaque;
1006 struct sis190_private *tp = netdev_priv(dev);
1008 if (likely(netif_running(dev)))
1009 schedule_work(&tp->phy_task);
1012 static inline void sis190_delete_timer(struct net_device *dev)
1014 struct sis190_private *tp = netdev_priv(dev);
1016 del_timer_sync(&tp->timer);
1019 static inline void sis190_request_timer(struct net_device *dev)
1021 struct sis190_private *tp = netdev_priv(dev);
1022 struct timer_list *timer = &tp->timer;
1025 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1026 timer->data = (unsigned long)dev;
1027 timer->function = sis190_phy_timer;
1031 static void sis190_set_rxbufsize(struct sis190_private *tp,
1032 struct net_device *dev)
1034 unsigned int mtu = dev->mtu;
1036 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1037 /* RxDesc->size has a licence to kill the lower bits */
1038 if (tp->rx_buf_sz & 0x07) {
1040 tp->rx_buf_sz &= RX_BUF_MASK;
1044 static int sis190_open(struct net_device *dev)
1046 struct sis190_private *tp = netdev_priv(dev);
1047 struct pci_dev *pdev = tp->pci_dev;
1050 sis190_set_rxbufsize(tp, dev);
1053 * Rx and Tx descriptors need 256 bytes alignment.
1054 * pci_alloc_consistent() guarantees a stronger alignment.
1056 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1057 if (!tp->TxDescRing)
1060 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1061 if (!tp->RxDescRing)
1064 rc = sis190_init_ring(dev);
1068 sis190_request_timer(dev);
1070 rc = request_irq(dev->irq, sis190_interrupt, IRQF_SHARED, dev->name, dev);
1072 goto err_release_timer_2;
1074 sis190_hw_start(dev);
1078 err_release_timer_2:
1079 sis190_delete_timer(dev);
1080 sis190_rx_clear(tp);
1082 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1085 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1090 static void sis190_tx_clear(struct sis190_private *tp)
1094 for (i = 0; i < NUM_TX_DESC; i++) {
1095 struct sk_buff *skb = tp->Tx_skbuff[i];
1100 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1101 tp->Tx_skbuff[i] = NULL;
1104 tp->dev->stats.tx_dropped++;
1106 tp->cur_tx = tp->dirty_tx = 0;
1109 static void sis190_down(struct net_device *dev)
1111 struct sis190_private *tp = netdev_priv(dev);
1112 void __iomem *ioaddr = tp->mmio_addr;
1113 unsigned int poll_locked = 0;
1115 sis190_delete_timer(dev);
1117 netif_stop_queue(dev);
1120 spin_lock_irq(&tp->lock);
1122 sis190_asic_down(ioaddr);
1124 spin_unlock_irq(&tp->lock);
1126 synchronize_irq(dev->irq);
1131 synchronize_sched();
1133 } while (SIS_R32(IntrMask));
1135 sis190_tx_clear(tp);
1136 sis190_rx_clear(tp);
1139 static int sis190_close(struct net_device *dev)
1141 struct sis190_private *tp = netdev_priv(dev);
1142 struct pci_dev *pdev = tp->pci_dev;
1146 free_irq(dev->irq, dev);
1148 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1149 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1151 tp->TxDescRing = NULL;
1152 tp->RxDescRing = NULL;
1157 static netdev_tx_t sis190_start_xmit(struct sk_buff *skb,
1158 struct net_device *dev)
1160 struct sis190_private *tp = netdev_priv(dev);
1161 void __iomem *ioaddr = tp->mmio_addr;
1162 u32 len, entry, dirty_tx;
1163 struct TxDesc *desc;
1166 if (unlikely(skb->len < ETH_ZLEN)) {
1167 if (skb_padto(skb, ETH_ZLEN)) {
1168 dev->stats.tx_dropped++;
1176 entry = tp->cur_tx % NUM_TX_DESC;
1177 desc = tp->TxDescRing + entry;
1179 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1180 netif_stop_queue(dev);
1181 netif_err(tp, tx_err, dev,
1182 "BUG! Tx Ring full when queue awake!\n");
1183 return NETDEV_TX_BUSY;
1186 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1188 tp->Tx_skbuff[entry] = skb;
1190 desc->PSize = cpu_to_le32(len);
1191 desc->addr = cpu_to_le32(mapping);
1193 desc->size = cpu_to_le32(len);
1194 if (entry == (NUM_TX_DESC - 1))
1195 desc->size |= cpu_to_le32(RingEnd);
1199 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1200 if (tp->negotiated_lpa & (LPA_1000HALF | LPA_100HALF | LPA_10HALF)) {
1202 desc->status |= cpu_to_le32(COLEN | CRSEN | BKFEN);
1203 if (tp->negotiated_lpa & (LPA_1000HALF | LPA_1000FULL))
1204 desc->status |= cpu_to_le32(EXTEN | BSTEN); /* gigabit HD */
1211 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1213 dirty_tx = tp->dirty_tx;
1214 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1215 netif_stop_queue(dev);
1217 if (dirty_tx != tp->dirty_tx)
1218 netif_wake_queue(dev);
1221 return NETDEV_TX_OK;
1224 static void sis190_free_phy(struct list_head *first_phy)
1226 struct sis190_phy *cur, *next;
1228 list_for_each_entry_safe(cur, next, first_phy, list) {
1234 * sis190_default_phy - Select default PHY for sis190 mac.
1235 * @dev: the net device to probe for
1237 * Select first detected PHY with link as default.
1238 * If no one is link on, select PHY whose types is HOME as default.
1239 * If HOME doesn't exist, select LAN.
1241 static u16 sis190_default_phy(struct net_device *dev)
1243 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1244 struct sis190_private *tp = netdev_priv(dev);
1245 struct mii_if_info *mii_if = &tp->mii_if;
1246 void __iomem *ioaddr = tp->mmio_addr;
1249 phy_home = phy_default = phy_lan = NULL;
1251 list_for_each_entry(phy, &tp->first_phy, list) {
1252 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1254 // Link ON & Not select default PHY & not ghost PHY.
1255 if ((status & BMSR_LSTATUS) &&
1257 (phy->type != UNKNOWN)) {
1260 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1261 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1262 status | BMCR_ANENABLE | BMCR_ISOLATE);
1263 if (phy->type == HOME)
1265 else if (phy->type == LAN)
1272 phy_default = phy_home;
1274 phy_default = phy_lan;
1276 phy_default = list_first_entry(&tp->first_phy,
1277 struct sis190_phy, list);
1280 if (mii_if->phy_id != phy_default->phy_id) {
1281 mii_if->phy_id = phy_default->phy_id;
1282 if (netif_msg_probe(tp))
1283 pr_info("%s: Using transceiver at address %d as default\n",
1284 pci_name(tp->pci_dev), mii_if->phy_id);
1287 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1288 status &= (~BMCR_ISOLATE);
1290 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1291 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1296 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1297 struct sis190_phy *phy, unsigned int phy_id,
1300 void __iomem *ioaddr = tp->mmio_addr;
1301 struct mii_chip_info *p;
1303 INIT_LIST_HEAD(&phy->list);
1304 phy->status = mii_status;
1305 phy->phy_id = phy_id;
1307 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1308 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1310 for (p = mii_chip_table; p->type; p++) {
1311 if ((p->id[0] == phy->id[0]) &&
1312 (p->id[1] == (phy->id[1] & 0xfff0))) {
1318 phy->type = (p->type == MIX) ?
1319 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1320 LAN : HOME) : p->type;
1321 tp->features |= p->feature;
1322 if (netif_msg_probe(tp))
1323 pr_info("%s: %s transceiver at address %d\n",
1324 pci_name(tp->pci_dev), p->name, phy_id);
1326 phy->type = UNKNOWN;
1327 if (netif_msg_probe(tp))
1328 pr_info("%s: unknown PHY 0x%x:0x%x transceiver at address %d\n",
1329 pci_name(tp->pci_dev),
1330 phy->id[0], (phy->id[1] & 0xfff0), phy_id);
1334 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1336 if (tp->features & F_PHY_88E1111) {
1337 void __iomem *ioaddr = tp->mmio_addr;
1338 int phy_id = tp->mii_if.phy_id;
1344 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1346 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1348 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1354 * sis190_mii_probe - Probe MII PHY for sis190
1355 * @dev: the net device to probe for
1357 * Search for total of 32 possible mii phy addresses.
1358 * Identify and set current phy if found one,
1359 * return error if it failed to found.
1361 static int __devinit sis190_mii_probe(struct net_device *dev)
1363 struct sis190_private *tp = netdev_priv(dev);
1364 struct mii_if_info *mii_if = &tp->mii_if;
1365 void __iomem *ioaddr = tp->mmio_addr;
1369 INIT_LIST_HEAD(&tp->first_phy);
1371 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1372 struct sis190_phy *phy;
1375 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1377 // Try next mii if the current one is not accessible.
1378 if (status == 0xffff || status == 0x0000)
1381 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1383 sis190_free_phy(&tp->first_phy);
1388 sis190_init_phy(dev, tp, phy, phy_id, status);
1390 list_add(&tp->first_phy, &phy->list);
1393 if (list_empty(&tp->first_phy)) {
1394 if (netif_msg_probe(tp))
1395 pr_info("%s: No MII transceivers found!\n",
1396 pci_name(tp->pci_dev));
1401 /* Select default PHY for mac */
1402 sis190_default_phy(dev);
1404 sis190_mii_probe_88e1111_fixup(tp);
1407 mii_if->mdio_read = __mdio_read;
1408 mii_if->mdio_write = __mdio_write;
1409 mii_if->phy_id_mask = PHY_ID_ANY;
1410 mii_if->reg_num_mask = MII_REG_ANY;
1415 static void sis190_mii_remove(struct net_device *dev)
1417 struct sis190_private *tp = netdev_priv(dev);
1419 sis190_free_phy(&tp->first_phy);
1422 static void sis190_release_board(struct pci_dev *pdev)
1424 struct net_device *dev = pci_get_drvdata(pdev);
1425 struct sis190_private *tp = netdev_priv(dev);
1427 iounmap(tp->mmio_addr);
1428 pci_release_regions(pdev);
1429 pci_disable_device(pdev);
1433 static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1435 struct sis190_private *tp;
1436 struct net_device *dev;
1437 void __iomem *ioaddr;
1440 dev = alloc_etherdev(sizeof(*tp));
1442 if (netif_msg_drv(&debug))
1443 pr_err("unable to alloc new ethernet\n");
1448 SET_NETDEV_DEV(dev, &pdev->dev);
1450 tp = netdev_priv(dev);
1452 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1454 rc = pci_enable_device(pdev);
1456 if (netif_msg_probe(tp))
1457 pr_err("%s: enable failure\n", pci_name(pdev));
1458 goto err_free_dev_1;
1463 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1464 if (netif_msg_probe(tp))
1465 pr_err("%s: region #0 is no MMIO resource\n",
1467 goto err_pci_disable_2;
1469 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1470 if (netif_msg_probe(tp))
1471 pr_err("%s: invalid PCI region size(s)\n",
1473 goto err_pci_disable_2;
1476 rc = pci_request_regions(pdev, DRV_NAME);
1478 if (netif_msg_probe(tp))
1479 pr_err("%s: could not request regions\n",
1481 goto err_pci_disable_2;
1484 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1486 if (netif_msg_probe(tp))
1487 pr_err("%s: DMA configuration failed\n",
1489 goto err_free_res_3;
1492 pci_set_master(pdev);
1494 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1496 if (netif_msg_probe(tp))
1497 pr_err("%s: cannot remap MMIO, aborting\n",
1500 goto err_free_res_3;
1504 tp->mmio_addr = ioaddr;
1506 sis190_irq_mask_and_ack(ioaddr);
1508 sis190_soft_reset(ioaddr);
1513 pci_release_regions(pdev);
1515 pci_disable_device(pdev);
1523 static void sis190_tx_timeout(struct net_device *dev)
1525 struct sis190_private *tp = netdev_priv(dev);
1526 void __iomem *ioaddr = tp->mmio_addr;
1529 /* Disable Tx, if not already */
1530 tmp8 = SIS_R8(TxControl);
1531 if (tmp8 & CmdTxEnb)
1532 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1534 netif_info(tp, tx_err, dev, "Transmit timeout, status %08x %08x\n",
1535 SIS_R32(TxControl), SIS_R32(TxSts));
1537 /* Disable interrupts by clearing the interrupt mask. */
1538 SIS_W32(IntrMask, 0x0000);
1540 /* Stop a shared interrupt from scavenging while we are. */
1541 spin_lock_irq(&tp->lock);
1542 sis190_tx_clear(tp);
1543 spin_unlock_irq(&tp->lock);
1545 /* ...and finally, reset everything. */
1546 sis190_hw_start(dev);
1548 netif_wake_queue(dev);
1551 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1553 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1556 static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1557 struct net_device *dev)
1559 struct sis190_private *tp = netdev_priv(dev);
1560 void __iomem *ioaddr = tp->mmio_addr;
1564 if (netif_msg_probe(tp))
1565 pr_info("%s: Read MAC address from EEPROM\n", pci_name(pdev));
1567 /* Check to see if there is a sane EEPROM */
1568 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1570 if ((sig == 0xffff) || (sig == 0x0000)) {
1571 if (netif_msg_probe(tp))
1572 pr_info("%s: Error EEPROM read %x\n",
1573 pci_name(pdev), sig);
1577 /* Get MAC address from EEPROM */
1578 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1579 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1581 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(w);
1584 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1590 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
1592 * @dev: network device to get address for
1594 * SiS96x model, use APC CMOS RAM to store MAC address.
1595 * APC CMOS RAM is accessed through ISA bridge.
1596 * MAC address is read into @net_dev->dev_addr.
1598 static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1599 struct net_device *dev)
1601 static const u16 __devinitdata ids[] = { 0x0965, 0x0966, 0x0968 };
1602 struct sis190_private *tp = netdev_priv(dev);
1603 struct pci_dev *isa_bridge;
1607 if (netif_msg_probe(tp))
1608 pr_info("%s: Read MAC address from APC\n", pci_name(pdev));
1610 for (i = 0; i < ARRAY_SIZE(ids); i++) {
1611 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1617 if (netif_msg_probe(tp))
1618 pr_info("%s: Can not find ISA bridge\n",
1623 /* Enable port 78h & 79h to access APC Registers. */
1624 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1625 reg = (tmp8 & ~0x02);
1626 pci_write_config_byte(isa_bridge, 0x48, reg);
1628 pci_read_config_byte(isa_bridge, 0x48, ®);
1630 for (i = 0; i < MAC_ADDR_LEN; i++) {
1631 outb(0x9 + i, 0x78);
1632 dev->dev_addr[i] = inb(0x79);
1638 sis190_set_rgmii(tp, reg);
1640 /* Restore the value to ISA Bridge */
1641 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1642 pci_dev_put(isa_bridge);
1648 * sis190_init_rxfilter - Initialize the Rx filter
1649 * @dev: network device to initialize
1651 * Set receive filter address to our MAC address
1652 * and enable packet filtering.
1654 static inline void sis190_init_rxfilter(struct net_device *dev)
1656 struct sis190_private *tp = netdev_priv(dev);
1657 void __iomem *ioaddr = tp->mmio_addr;
1661 ctl = SIS_R16(RxMacControl);
1663 * Disable packet filtering before setting filter.
1664 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1665 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1667 SIS_W16(RxMacControl, ctl & ~0x0f00);
1669 for (i = 0; i < MAC_ADDR_LEN; i++)
1670 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1672 SIS_W16(RxMacControl, ctl);
1676 static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
1677 struct net_device *dev)
1681 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1685 pci_read_config_byte(pdev, 0x73, ®);
1687 if (reg & 0x00000001)
1688 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1693 static void sis190_set_speed_auto(struct net_device *dev)
1695 struct sis190_private *tp = netdev_priv(dev);
1696 void __iomem *ioaddr = tp->mmio_addr;
1697 int phy_id = tp->mii_if.phy_id;
1700 netif_info(tp, link, dev, "Enabling Auto-negotiation\n");
1702 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1704 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1706 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1707 ADVERTISE_100FULL | ADVERTISE_10FULL |
1708 ADVERTISE_100HALF | ADVERTISE_10HALF);
1710 // Enable 1000 Full Mode.
1711 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1713 // Enable auto-negotiation and restart auto-negotiation.
1714 mdio_write(ioaddr, phy_id, MII_BMCR,
1715 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1718 static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1720 struct sis190_private *tp = netdev_priv(dev);
1722 return mii_ethtool_gset(&tp->mii_if, cmd);
1725 static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1727 struct sis190_private *tp = netdev_priv(dev);
1729 return mii_ethtool_sset(&tp->mii_if, cmd);
1732 static void sis190_get_drvinfo(struct net_device *dev,
1733 struct ethtool_drvinfo *info)
1735 struct sis190_private *tp = netdev_priv(dev);
1737 strcpy(info->driver, DRV_NAME);
1738 strcpy(info->version, DRV_VERSION);
1739 strcpy(info->bus_info, pci_name(tp->pci_dev));
1742 static int sis190_get_regs_len(struct net_device *dev)
1744 return SIS190_REGS_SIZE;
1747 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1750 struct sis190_private *tp = netdev_priv(dev);
1751 unsigned long flags;
1753 if (regs->len > SIS190_REGS_SIZE)
1754 regs->len = SIS190_REGS_SIZE;
1756 spin_lock_irqsave(&tp->lock, flags);
1757 memcpy_fromio(p, tp->mmio_addr, regs->len);
1758 spin_unlock_irqrestore(&tp->lock, flags);
1761 static int sis190_nway_reset(struct net_device *dev)
1763 struct sis190_private *tp = netdev_priv(dev);
1765 return mii_nway_restart(&tp->mii_if);
1768 static u32 sis190_get_msglevel(struct net_device *dev)
1770 struct sis190_private *tp = netdev_priv(dev);
1772 return tp->msg_enable;
1775 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1777 struct sis190_private *tp = netdev_priv(dev);
1779 tp->msg_enable = value;
1782 static const struct ethtool_ops sis190_ethtool_ops = {
1783 .get_settings = sis190_get_settings,
1784 .set_settings = sis190_set_settings,
1785 .get_drvinfo = sis190_get_drvinfo,
1786 .get_regs_len = sis190_get_regs_len,
1787 .get_regs = sis190_get_regs,
1788 .get_link = ethtool_op_get_link,
1789 .get_msglevel = sis190_get_msglevel,
1790 .set_msglevel = sis190_set_msglevel,
1791 .nway_reset = sis190_nway_reset,
1794 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1796 struct sis190_private *tp = netdev_priv(dev);
1798 return !netif_running(dev) ? -EINVAL :
1799 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1802 static const struct net_device_ops sis190_netdev_ops = {
1803 .ndo_open = sis190_open,
1804 .ndo_stop = sis190_close,
1805 .ndo_do_ioctl = sis190_ioctl,
1806 .ndo_start_xmit = sis190_start_xmit,
1807 .ndo_tx_timeout = sis190_tx_timeout,
1808 .ndo_set_multicast_list = sis190_set_rx_mode,
1809 .ndo_change_mtu = eth_change_mtu,
1810 .ndo_set_mac_address = eth_mac_addr,
1811 .ndo_validate_addr = eth_validate_addr,
1812 #ifdef CONFIG_NET_POLL_CONTROLLER
1813 .ndo_poll_controller = sis190_netpoll,
1817 static int __devinit sis190_init_one(struct pci_dev *pdev,
1818 const struct pci_device_id *ent)
1820 static int printed_version = 0;
1821 struct sis190_private *tp;
1822 struct net_device *dev;
1823 void __iomem *ioaddr;
1826 if (!printed_version) {
1827 if (netif_msg_drv(&debug))
1828 pr_info(SIS190_DRIVER_NAME " loaded\n");
1829 printed_version = 1;
1832 dev = sis190_init_board(pdev);
1838 pci_set_drvdata(pdev, dev);
1840 tp = netdev_priv(dev);
1841 ioaddr = tp->mmio_addr;
1843 rc = sis190_get_mac_addr(pdev, dev);
1845 goto err_release_board;
1847 sis190_init_rxfilter(dev);
1849 INIT_WORK(&tp->phy_task, sis190_phy_task);
1851 dev->netdev_ops = &sis190_netdev_ops;
1853 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1854 dev->irq = pdev->irq;
1855 dev->base_addr = (unsigned long) 0xdead;
1856 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1858 spin_lock_init(&tp->lock);
1860 rc = sis190_mii_probe(dev);
1862 goto err_release_board;
1864 rc = register_netdev(dev);
1866 goto err_remove_mii;
1868 if (netif_msg_probe(tp)) {
1869 netdev_info(dev, "%s: %s at %p (IRQ: %d), %pM\n",
1871 sis_chip_info[ent->driver_data].name,
1872 ioaddr, dev->irq, dev->dev_addr);
1873 netdev_info(dev, "%s mode.\n",
1874 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1877 netif_carrier_off(dev);
1879 sis190_set_speed_auto(dev);
1884 sis190_mii_remove(dev);
1886 sis190_release_board(pdev);
1890 static void __devexit sis190_remove_one(struct pci_dev *pdev)
1892 struct net_device *dev = pci_get_drvdata(pdev);
1894 sis190_mii_remove(dev);
1895 flush_scheduled_work();
1896 unregister_netdev(dev);
1897 sis190_release_board(pdev);
1898 pci_set_drvdata(pdev, NULL);
1901 static struct pci_driver sis190_pci_driver = {
1903 .id_table = sis190_pci_tbl,
1904 .probe = sis190_init_one,
1905 .remove = __devexit_p(sis190_remove_one),
1908 static int __init sis190_init_module(void)
1910 return pci_register_driver(&sis190_pci_driver);
1913 static void __exit sis190_cleanup_module(void)
1915 pci_unregister_driver(&sis190_pci_driver);
1918 module_init(sis190_init_module);
1919 module_exit(sis190_cleanup_module);