1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/seq_file.h>
16 #include "falcon_hwdefs.h"
18 #include "workarounds.h"
21 /* We expect these MMDs to be in the package. SFT9001 also has a
22 * clause 22 extension MMD, but since it doesn't have all the generic
23 * MMD registers it is pointless to include it here.
25 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \
26 MDIO_MMDREG_DEVS_PCS | \
27 MDIO_MMDREG_DEVS_PHYXS | \
30 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
31 (1 << LOOPBACK_PCS) | \
32 (1 << LOOPBACK_PMAPMD) | \
33 (1 << LOOPBACK_NETWORK))
35 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
36 (1 << LOOPBACK_PHYXS) | \
37 (1 << LOOPBACK_PCS) | \
38 (1 << LOOPBACK_PMAPMD) | \
39 (1 << LOOPBACK_NETWORK))
41 /* We complain if we fail to see the link partner as 10G capable this many
42 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
44 #define MAX_BAD_LP_TRIES (5)
47 #define PMA_PMD_LASI_CTRL 36866
48 #define PMA_PMD_LASI_STATUS 36869
49 #define PMA_PMD_LS_ALARM_LBN 0
50 #define PMA_PMD_LS_ALARM_WIDTH 1
51 #define PMA_PMD_TX_ALARM_LBN 1
52 #define PMA_PMD_TX_ALARM_WIDTH 1
53 #define PMA_PMD_RX_ALARM_LBN 2
54 #define PMA_PMD_RX_ALARM_WIDTH 1
55 #define PMA_PMD_AN_ALARM_LBN 3
56 #define PMA_PMD_AN_ALARM_WIDTH 1
58 /* Extended control register */
59 #define PMA_PMD_XCONTROL_REG 49152
60 #define PMA_PMD_EXT_GMII_EN_LBN 1
61 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
62 #define PMA_PMD_EXT_CLK_OUT_LBN 2
63 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
64 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
65 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
66 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
67 #define PMA_PMD_EXT_CLK312_WIDTH 1
68 #define PMA_PMD_EXT_LPOWER_LBN 12
69 #define PMA_PMD_EXT_LPOWER_WIDTH 1
70 #define PMA_PMD_EXT_ROBUST_LBN 14
71 #define PMA_PMD_EXT_ROBUST_WIDTH 1
72 #define PMA_PMD_EXT_SSR_LBN 15
73 #define PMA_PMD_EXT_SSR_WIDTH 1
75 /* extended status register */
76 #define PMA_PMD_XSTATUS_REG 49153
77 #define PMA_PMD_XSTAT_FLP_LBN (12)
79 /* LED control register */
80 #define PMA_PMD_LED_CTRL_REG 49159
81 #define PMA_PMA_LED_ACTIVITY_LBN (3)
83 /* LED function override register */
84 #define PMA_PMD_LED_OVERR_REG 49161
85 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
86 #define PMA_PMD_LED_LINK_LBN (0)
87 #define PMA_PMD_LED_SPEED_LBN (2)
88 #define PMA_PMD_LED_TX_LBN (4)
89 #define PMA_PMD_LED_RX_LBN (6)
90 /* Override settings */
91 #define PMA_PMD_LED_AUTO (0) /* H/W control */
92 #define PMA_PMD_LED_ON (1)
93 #define PMA_PMD_LED_OFF (2)
94 #define PMA_PMD_LED_FLASH (3)
95 #define PMA_PMD_LED_MASK 3
96 /* All LEDs under hardware control */
97 #define PMA_PMD_LED_FULL_AUTO (0)
98 /* Green and Amber under hardware control, Red off */
99 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
101 #define PMA_PMD_SPEED_ENABLE_REG 49192
102 #define PMA_PMD_100TX_ADV_LBN 1
103 #define PMA_PMD_100TX_ADV_WIDTH 1
104 #define PMA_PMD_1000T_ADV_LBN 2
105 #define PMA_PMD_1000T_ADV_WIDTH 1
106 #define PMA_PMD_10000T_ADV_LBN 3
107 #define PMA_PMD_10000T_ADV_WIDTH 1
108 #define PMA_PMD_SPEED_LBN 4
109 #define PMA_PMD_SPEED_WIDTH 4
111 /* Cable diagnostics - SFT9001 only */
112 #define PMA_PMD_CDIAG_CTRL_REG 49213
113 #define CDIAG_CTRL_IMMED_LBN 15
114 #define CDIAG_CTRL_BRK_LINK_LBN 12
115 #define CDIAG_CTRL_IN_PROG_LBN 11
116 #define CDIAG_CTRL_LEN_UNIT_LBN 10
117 #define CDIAG_CTRL_LEN_METRES 1
118 #define PMA_PMD_CDIAG_RES_REG 49174
119 #define CDIAG_RES_A_LBN 12
120 #define CDIAG_RES_B_LBN 8
121 #define CDIAG_RES_C_LBN 4
122 #define CDIAG_RES_D_LBN 0
123 #define CDIAG_RES_WIDTH 4
124 #define CDIAG_RES_OPEN 2
125 #define CDIAG_RES_OK 1
126 #define CDIAG_RES_INVALID 0
127 /* Set of 4 registers for pairs A-D */
128 #define PMA_PMD_CDIAG_LEN_REG 49175
130 /* Serdes control registers - SFT9001 only */
131 #define PMA_PMD_CSERDES_CTRL_REG 64258
132 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
133 #define PMA_PMD_CSERDES_DEFAULT 0x000f
135 /* Misc register defines - SFX7101 only */
136 #define PCS_CLOCK_CTRL_REG 55297
137 #define PLL312_RST_N_LBN 2
139 #define PCS_SOFT_RST2_REG 55302
140 #define SERDES_RST_N_LBN 13
141 #define XGXS_RST_N_LBN 12
143 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
144 #define CLK312_EN_LBN 3
146 /* PHYXS registers */
147 #define PHYXS_XCONTROL_REG 49152
148 #define PHYXS_RESET_LBN 15
149 #define PHYXS_RESET_WIDTH 1
151 #define PHYXS_TEST1 (49162)
152 #define LOOPBACK_NEAR_LBN (8)
153 #define LOOPBACK_NEAR_WIDTH (1)
155 #define PCS_10GBASET_STAT1 32
156 #define PCS_10GBASET_BLKLK_LBN 0
157 #define PCS_10GBASET_BLKLK_WIDTH 1
159 /* Boot status register */
160 #define PCS_BOOT_STATUS_REG 53248
161 #define PCS_BOOT_FATAL_ERR_LBN (0)
162 #define PCS_BOOT_PROGRESS_LBN (1)
163 #define PCS_BOOT_PROGRESS_WIDTH (2)
164 #define PCS_BOOT_COMPLETE_LBN (3)
166 #define PCS_BOOT_MAX_DELAY (100)
167 #define PCS_BOOT_POLL_DELAY (10)
169 /* 100M/1G PHY registers */
170 #define GPHY_XCONTROL_REG 49152
171 #define GPHY_ISOLATE_LBN 10
172 #define GPHY_ISOLATE_WIDTH 1
173 #define GPHY_DUPLEX_LBN 8
174 #define GPHY_DUPLEX_WIDTH 1
175 #define GPHY_LOOPBACK_NEAR_LBN 14
176 #define GPHY_LOOPBACK_NEAR_WIDTH 1
178 #define C22EXT_STATUS_REG 49153
179 #define C22EXT_STATUS_LINK_LBN 2
180 #define C22EXT_STATUS_LINK_WIDTH 1
182 #define C22EXT_MSTSLV_REG 49162
183 #define C22EXT_MSTSLV_1000_HD_LBN 10
184 #define C22EXT_MSTSLV_1000_HD_WIDTH 1
185 #define C22EXT_MSTSLV_1000_FD_LBN 11
186 #define C22EXT_MSTSLV_1000_FD_WIDTH 1
188 /* Time to wait between powering down the LNPGA and turning off the power
190 #define LNPGA_PDOWN_WAIT (HZ / 5)
192 struct tenxpress_phy_data {
193 enum efx_loopback_mode loopback_mode;
194 enum efx_phy_mode phy_mode;
198 static ssize_t show_phy_short_reach(struct device *dev,
199 struct device_attribute *attr, char *buf)
201 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
204 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
205 MDIO_PMAPMD_10GBT_TXPWR);
206 return sprintf(buf, "%d\n",
207 !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
210 static ssize_t set_phy_short_reach(struct device *dev,
211 struct device_attribute *attr,
212 const char *buf, size_t count)
214 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
217 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
218 MDIO_PMAPMD_10GBT_TXPWR,
219 MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN,
220 count != 0 && *buf != '0');
221 efx_reconfigure_port(efx);
227 static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
228 set_phy_short_reach);
230 /* Check that the C166 has booted successfully */
231 static int tenxpress_phy_check(struct efx_nic *efx)
233 int phy_id = efx->mii.phy_id;
234 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
237 /* Wait for the boot to complete (or not) */
239 boot_stat = mdio_clause45_read(efx, phy_id,
241 PCS_BOOT_STATUS_REG);
242 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
245 udelay(PCS_BOOT_POLL_DELAY);
249 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
251 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
252 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
259 static int tenxpress_init(struct efx_nic *efx)
261 int phy_id = efx->mii.phy_id;
265 if (efx->phy_type == PHY_TYPE_SFX7101) {
266 /* Enable 312.5 MHz clock */
267 mdio_clause45_write(efx, phy_id,
268 MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
271 /* Enable 312.5 MHz clock and GMII */
272 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
273 PMA_PMD_XCONTROL_REG);
274 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
275 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
276 (1 << PMA_PMD_EXT_CLK312_LBN) |
277 (1 << PMA_PMD_EXT_ROBUST_LBN));
279 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
280 PMA_PMD_XCONTROL_REG, reg);
281 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
282 GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN,
286 rc = tenxpress_phy_check(efx);
290 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
291 if (efx->phy_type == PHY_TYPE_SFX7101) {
292 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
293 PMA_PMD_LED_CTRL_REG,
294 PMA_PMA_LED_ACTIVITY_LBN,
296 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
297 PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
303 static int tenxpress_phy_init(struct efx_nic *efx)
305 struct tenxpress_phy_data *phy_data;
308 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
311 efx->phy_data = phy_data;
312 phy_data->phy_mode = efx->phy_mode;
314 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
315 if (efx->phy_type == PHY_TYPE_SFT9001A) {
317 reg = mdio_clause45_read(efx, efx->mii.phy_id,
319 PMA_PMD_XCONTROL_REG);
320 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
321 mdio_clause45_write(efx, efx->mii.phy_id,
323 PMA_PMD_XCONTROL_REG, reg);
327 rc = mdio_clause45_wait_reset_mmds(efx,
328 TENXPRESS_REQUIRED_DEVS);
332 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
337 rc = tenxpress_init(efx);
341 if (efx->phy_type == PHY_TYPE_SFT9001B) {
342 rc = device_create_file(&efx->pci_dev->dev,
343 &dev_attr_phy_short_reach);
348 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
350 /* Let XGXS and SerDes out of reset */
351 falcon_reset_xaui(efx);
356 kfree(efx->phy_data);
357 efx->phy_data = NULL;
361 /* Perform a "special software reset" on the PHY. The caller is
362 * responsible for saving and restoring the PHY hardware registers
363 * properly, and masking/unmasking LASI */
364 static int tenxpress_special_reset(struct efx_nic *efx)
368 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
369 * a special software reset can glitch the XGMAC sufficiently for stats
370 * requests to fail. Since we don't often special_reset, just lock. */
371 spin_lock(&efx->stats_lock);
374 reg = mdio_clause45_read(efx, efx->mii.phy_id,
375 MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
376 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
377 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
378 PMA_PMD_XCONTROL_REG, reg);
382 /* Wait for the blocks to come out of reset */
383 rc = mdio_clause45_wait_reset_mmds(efx,
384 TENXPRESS_REQUIRED_DEVS);
388 /* Try and reconfigure the device */
389 rc = tenxpress_init(efx);
393 /* Wait for the XGXS state machine to churn */
396 spin_unlock(&efx->stats_lock);
400 static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
402 struct tenxpress_phy_data *pd = efx->phy_data;
403 int phy_id = efx->mii.phy_id;
410 /* Check that AN has started but not completed. */
411 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
413 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
414 return; /* LP status is unknown */
415 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN));
420 /* Nothing to do if all is well and was previously so. */
421 if (!pd->bad_lp_tries)
424 /* Use the RX (red) LED as an error indicator once we've seen AN
425 * failure several times in a row, and also log a message. */
426 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
427 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
428 PMA_PMD_LED_OVERR_REG);
429 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
431 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
433 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
434 EFX_ERR(efx, "appears to be plugged into a port"
435 " that is not 10GBASE-T capable. The PHY"
436 " supports 10GBASE-T ONLY, so no link can"
437 " be established\n");
439 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
440 PMA_PMD_LED_OVERR_REG, reg);
441 pd->bad_lp_tries = bad_lp;
445 static bool sfx7101_link_ok(struct efx_nic *efx)
447 return mdio_clause45_links_ok(efx,
448 MDIO_MMDREG_DEVS_PMAPMD |
449 MDIO_MMDREG_DEVS_PCS |
450 MDIO_MMDREG_DEVS_PHYXS);
453 static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
455 int phy_id = efx->mii.phy_id;
458 if (efx_phy_mode_disabled(efx->phy_mode))
460 else if (efx->loopback_mode == LOOPBACK_GPHY)
462 else if (efx->loopback_mode)
463 return mdio_clause45_links_ok(efx,
464 MDIO_MMDREG_DEVS_PMAPMD |
465 MDIO_MMDREG_DEVS_PHYXS);
467 /* We must use the same definition of link state as LASI,
468 * otherwise we can miss a link state transition
470 if (ecmd->speed == 10000) {
471 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
473 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
475 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
477 return reg & (1 << C22EXT_STATUS_LINK_LBN);
481 static void tenxpress_ext_loopback(struct efx_nic *efx)
483 int phy_id = efx->mii.phy_id;
485 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
486 PHYXS_TEST1, LOOPBACK_NEAR_LBN,
487 efx->loopback_mode == LOOPBACK_PHYXS);
488 if (efx->phy_type != PHY_TYPE_SFX7101)
489 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
491 GPHY_LOOPBACK_NEAR_LBN,
492 efx->loopback_mode == LOOPBACK_GPHY);
495 static void tenxpress_low_power(struct efx_nic *efx)
497 int phy_id = efx->mii.phy_id;
499 if (efx->phy_type == PHY_TYPE_SFX7101)
500 mdio_clause45_set_mmds_lpower(
501 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
502 TENXPRESS_REQUIRED_DEVS);
504 mdio_clause45_set_flag(
505 efx, phy_id, MDIO_MMD_PMAPMD,
506 PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN,
507 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
510 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
512 struct tenxpress_phy_data *phy_data = efx->phy_data;
513 struct ethtool_cmd ecmd;
514 bool phy_mode_change, loop_reset, loop_toggle, loopback;
516 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
517 phy_data->phy_mode = efx->phy_mode;
521 tenxpress_low_power(efx);
523 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
524 phy_data->phy_mode != PHY_MODE_NORMAL);
525 loopback = LOOPBACK_MASK(efx) & efx->phy_op->loopbacks;
526 loop_toggle = LOOPBACK_CHANGED(phy_data, efx, efx->phy_op->loopbacks);
527 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
528 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
530 if (loop_reset || loop_toggle || loopback || phy_mode_change) {
533 efx->phy_op->get_settings(efx, &ecmd);
535 if (loop_reset || phy_mode_change) {
536 tenxpress_special_reset(efx);
538 /* Reset XAUI if we were in 10G, and are staying
539 * in 10G. If we're moving into and out of 10G
540 * then xaui will be reset anyway */
542 falcon_reset_xaui(efx);
545 if (efx->phy_type != PHY_TYPE_SFX7101) {
546 /* Only change autoneg once, on coming out or
547 * going into loopback */
549 ecmd.autoneg = !loopback;
551 ecmd.duplex = DUPLEX_FULL;
552 if (efx->loopback_mode == LOOPBACK_GPHY)
553 ecmd.speed = SPEED_1000;
555 ecmd.speed = SPEED_10000;
559 rc = efx->phy_op->set_settings(efx, &ecmd);
563 mdio_clause45_transmit_disable(efx);
564 mdio_clause45_phy_reconfigure(efx);
565 tenxpress_ext_loopback(efx);
567 phy_data->loopback_mode = efx->loopback_mode;
568 phy_data->phy_mode = efx->phy_mode;
570 if (efx->phy_type == PHY_TYPE_SFX7101) {
571 efx->link_speed = 10000;
573 efx->link_up = sfx7101_link_ok(efx);
575 efx->phy_op->get_settings(efx, &ecmd);
576 efx->link_speed = ecmd.speed;
577 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
578 efx->link_up = sft9001_link_ok(efx, &ecmd);
580 efx->link_fc = mdio_clause45_get_pause(efx);
583 /* Poll PHY for interrupt */
584 static void tenxpress_phy_poll(struct efx_nic *efx)
586 struct tenxpress_phy_data *phy_data = efx->phy_data;
587 bool change = false, link_ok;
590 if (efx->phy_type == PHY_TYPE_SFX7101) {
591 link_ok = sfx7101_link_ok(efx);
592 if (link_ok != efx->link_up) {
595 link_fc = mdio_clause45_get_pause(efx);
596 if (link_fc != efx->link_fc)
599 sfx7101_check_bad_lp(efx, link_ok);
600 } else if (efx->loopback_mode) {
601 bool link_ok = sft9001_link_ok(efx, NULL);
602 if (link_ok != efx->link_up)
605 u32 status = mdio_clause45_read(efx, efx->mii.phy_id,
607 PMA_PMD_LASI_STATUS);
608 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
613 falcon_sim_phy_event(efx);
615 if (phy_data->phy_mode != PHY_MODE_NORMAL)
619 static void tenxpress_phy_fini(struct efx_nic *efx)
623 if (efx->phy_type == PHY_TYPE_SFT9001B)
624 device_remove_file(&efx->pci_dev->dev,
625 &dev_attr_phy_short_reach);
627 if (efx->phy_type == PHY_TYPE_SFX7101) {
628 /* Power down the LNPGA */
629 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
630 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
631 PMA_PMD_XCONTROL_REG, reg);
633 /* Waiting here ensures that the board fini, which can turn
634 * off the power to the PHY, won't get run until the LNPGA
635 * powerdown has been given long enough to complete. */
636 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
639 kfree(efx->phy_data);
640 efx->phy_data = NULL;
644 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
645 * (which probably aren't wired anyway) are left in AUTO mode */
646 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
651 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
652 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
653 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
655 reg = PMA_PMD_LED_DEFAULT;
657 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
658 PMA_PMD_LED_OVERR_REG, reg);
661 static const char *const sfx7101_test_names[] = {
666 sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
670 if (!(flags & ETH_TEST_FL_OFFLINE))
673 /* BIST is automatically run after a special software reset */
674 rc = tenxpress_special_reset(efx);
675 results[0] = rc ? -1 : 1;
679 static const char *const sft9001_test_names[] = {
681 "cable.pairA.status",
682 "cable.pairB.status",
683 "cable.pairC.status",
684 "cable.pairD.status",
685 "cable.pairA.length",
686 "cable.pairB.length",
687 "cable.pairC.length",
688 "cable.pairD.length",
691 static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
693 struct ethtool_cmd ecmd;
694 int phy_id = efx->mii.phy_id;
695 int rc = 0, rc2, i, res_reg;
697 if (!(flags & ETH_TEST_FL_OFFLINE))
700 efx->phy_op->get_settings(efx, &ecmd);
702 /* Initialise cable diagnostic results to unknown failure */
703 for (i = 1; i < 9; ++i)
706 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
707 * A cable fault is not a self-test failure, but a timeout is. */
708 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
709 PMA_PMD_CDIAG_CTRL_REG,
710 (1 << CDIAG_CTRL_IMMED_LBN) |
711 (1 << CDIAG_CTRL_BRK_LINK_LBN) |
712 (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN));
714 while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
715 PMA_PMD_CDIAG_CTRL_REG) &
716 (1 << CDIAG_CTRL_IN_PROG_LBN)) {
723 res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
724 PMA_PMD_CDIAG_RES_REG);
725 for (i = 0; i < 4; i++) {
727 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
728 & ((1 << CDIAG_RES_WIDTH) - 1);
729 int len_reg = mdio_clause45_read(efx, efx->mii.phy_id,
731 PMA_PMD_CDIAG_LEN_REG + i);
732 if (pair_res == CDIAG_RES_OK)
734 else if (pair_res == CDIAG_RES_INVALID)
737 results[1 + i] = -pair_res;
738 if (pair_res != CDIAG_RES_INVALID &&
739 pair_res != CDIAG_RES_OPEN &&
741 results[5 + i] = len_reg;
744 /* We must reset to exit cable diagnostic mode. The BIST will
745 * also run when we do this. */
747 rc2 = tenxpress_special_reset(efx);
748 results[0] = rc2 ? -1 : 1;
752 rc2 = efx->phy_op->set_settings(efx, &ecmd);
759 static u32 tenxpress_get_xnp_lpa(struct efx_nic *efx)
761 int phy = efx->mii.phy_id;
765 if (efx->phy_type != PHY_TYPE_SFX7101) {
766 reg = mdio_clause45_read(efx, phy, MDIO_MMD_C22EXT,
768 if (reg & (1 << C22EXT_MSTSLV_1000_HD_LBN))
769 lpa |= ADVERTISED_1000baseT_Half;
770 if (reg & (1 << C22EXT_MSTSLV_1000_FD_LBN))
771 lpa |= ADVERTISED_1000baseT_Full;
773 reg = mdio_clause45_read(efx, phy, MDIO_MMD_AN, MDIO_AN_10GBT_STATUS);
774 if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
775 lpa |= ADVERTISED_10000baseT_Full;
779 static void sfx7101_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
781 mdio_clause45_get_settings_ext(efx, ecmd, ADVERTISED_10000baseT_Full,
782 tenxpress_get_xnp_lpa(efx));
783 ecmd->supported |= SUPPORTED_10000baseT_Full;
784 ecmd->advertising |= ADVERTISED_10000baseT_Full;
787 static void sft9001_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
789 int phy_id = efx->mii.phy_id;
793 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
794 PMA_PMD_SPEED_ENABLE_REG);
795 if (EFX_WORKAROUND_13204(efx) && (reg & (1 << PMA_PMD_100TX_ADV_LBN)))
796 xnp_adv |= ADVERTISED_100baseT_Full;
797 if (reg & (1 << PMA_PMD_1000T_ADV_LBN))
798 xnp_adv |= ADVERTISED_1000baseT_Full;
799 if (reg & (1 << PMA_PMD_10000T_ADV_LBN))
800 xnp_adv |= ADVERTISED_10000baseT_Full;
802 mdio_clause45_get_settings_ext(efx, ecmd, xnp_adv,
803 tenxpress_get_xnp_lpa(efx));
805 ecmd->supported |= (SUPPORTED_100baseT_Half |
806 SUPPORTED_100baseT_Full |
807 SUPPORTED_1000baseT_Full);
809 /* Use the vendor defined C22ext register for duplex settings */
810 if (ecmd->speed != SPEED_10000 && !ecmd->autoneg) {
811 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
813 ecmd->duplex = (reg & (1 << GPHY_DUPLEX_LBN) ?
814 DUPLEX_FULL : DUPLEX_HALF);
818 static int sft9001_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
820 int phy_id = efx->mii.phy_id;
823 rc = mdio_clause45_set_settings(efx, ecmd);
827 if (ecmd->speed != SPEED_10000 && !ecmd->autoneg)
828 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
829 GPHY_XCONTROL_REG, GPHY_DUPLEX_LBN,
830 ecmd->duplex == DUPLEX_FULL);
835 static bool sft9001_set_xnp_advertise(struct efx_nic *efx, u32 advertising)
837 int phy = efx->mii.phy_id;
838 int reg = mdio_clause45_read(efx, phy, MDIO_MMD_PMAPMD,
839 PMA_PMD_SPEED_ENABLE_REG);
842 reg &= ~((1 << 2) | (1 << 3));
843 if (EFX_WORKAROUND_13204(efx) &&
844 (advertising & ADVERTISED_100baseT_Full))
845 reg |= 1 << PMA_PMD_100TX_ADV_LBN;
846 if (advertising & ADVERTISED_1000baseT_Full)
847 reg |= 1 << PMA_PMD_1000T_ADV_LBN;
848 if (advertising & ADVERTISED_10000baseT_Full)
849 reg |= 1 << PMA_PMD_10000T_ADV_LBN;
850 mdio_clause45_write(efx, phy, MDIO_MMD_PMAPMD,
851 PMA_PMD_SPEED_ENABLE_REG, reg);
853 enabled = (advertising &
854 (ADVERTISED_1000baseT_Half |
855 ADVERTISED_1000baseT_Full |
856 ADVERTISED_10000baseT_Full));
857 if (EFX_WORKAROUND_13204(efx))
858 enabled |= (advertising & ADVERTISED_100baseT_Full);
862 struct efx_phy_operations falcon_sfx7101_phy_ops = {
864 .init = tenxpress_phy_init,
865 .reconfigure = tenxpress_phy_reconfigure,
866 .poll = tenxpress_phy_poll,
867 .fini = tenxpress_phy_fini,
868 .clear_interrupt = efx_port_dummy_op_void,
869 .get_settings = sfx7101_get_settings,
870 .set_settings = mdio_clause45_set_settings,
871 .num_tests = ARRAY_SIZE(sfx7101_test_names),
872 .test_names = sfx7101_test_names,
873 .run_tests = sfx7101_run_tests,
874 .mmds = TENXPRESS_REQUIRED_DEVS,
875 .loopbacks = SFX7101_LOOPBACKS,
878 struct efx_phy_operations falcon_sft9001_phy_ops = {
879 .macs = EFX_GMAC | EFX_XMAC,
880 .init = tenxpress_phy_init,
881 .reconfigure = tenxpress_phy_reconfigure,
882 .poll = tenxpress_phy_poll,
883 .fini = tenxpress_phy_fini,
884 .clear_interrupt = efx_port_dummy_op_void,
885 .get_settings = sft9001_get_settings,
886 .set_settings = sft9001_set_settings,
887 .set_xnp_advertise = sft9001_set_xnp_advertise,
888 .num_tests = ARRAY_SIZE(sft9001_test_names),
889 .test_names = sft9001_test_names,
890 .run_tests = sft9001_run_tests,
891 .mmds = TENXPRESS_REQUIRED_DEVS,
892 .loopbacks = SFT9001_LOOPBACKS,