1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/version.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_vlan.h>
21 #include <linux/timer.h>
22 #include <linux/mdio.h>
23 #include <linux/list.h>
24 #include <linux/pci.h>
25 #include <linux/device.h>
26 #include <linux/highmem.h>
27 #include <linux/workqueue.h>
28 #include <linux/i2c.h>
33 /**************************************************************************
37 **************************************************************************/
38 #ifndef EFX_DRIVER_NAME
39 #define EFX_DRIVER_NAME "sfc"
41 #define EFX_DRIVER_VERSION "2.3"
43 #ifdef EFX_ENABLE_DEBUG
44 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
45 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
47 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
48 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
51 /* Un-rate-limited logging */
52 #define EFX_ERR(efx, fmt, args...) \
53 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
55 #define EFX_INFO(efx, fmt, args...) \
56 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
58 #ifdef EFX_ENABLE_DEBUG
59 #define EFX_LOG(efx, fmt, args...) \
60 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
62 #define EFX_LOG(efx, fmt, args...) \
63 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
66 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
68 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
70 /* Rate-limited logging */
71 #define EFX_ERR_RL(efx, fmt, args...) \
72 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
74 #define EFX_INFO_RL(efx, fmt, args...) \
75 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
77 #define EFX_LOG_RL(efx, fmt, args...) \
78 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
80 /**************************************************************************
84 **************************************************************************/
86 #define EFX_MAX_CHANNELS 32
87 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
89 #define EFX_TX_QUEUE_OFFLOAD_CSUM 0
90 #define EFX_TX_QUEUE_NO_CSUM 1
91 #define EFX_TX_QUEUE_COUNT 2
94 * struct efx_special_buffer - An Efx special buffer
95 * @addr: CPU base address of the buffer
96 * @dma_addr: DMA base address of the buffer
97 * @len: Buffer length, in bytes
98 * @index: Buffer index within controller;s buffer table
99 * @entries: Number of buffer table entries
101 * Special buffers are used for the event queues and the TX and RX
102 * descriptor queues for each channel. They are *not* used for the
103 * actual transmit and receive buffers.
105 * Note that for Falcon, TX and RX descriptor queues live in host memory.
106 * Allocation and freeing procedures must take this into account.
108 struct efx_special_buffer {
117 * struct efx_tx_buffer - An Efx TX buffer
118 * @skb: The associated socket buffer.
119 * Set only on the final fragment of a packet; %NULL for all other
120 * fragments. When this fragment completes, then we can free this
122 * @tsoh: The associated TSO header structure, or %NULL if this
123 * buffer is not a TSO header.
124 * @dma_addr: DMA address of the fragment.
125 * @len: Length of this fragment.
126 * This field is zero when the queue slot is empty.
127 * @continuation: True if this fragment is not the end of a packet.
128 * @unmap_single: True if pci_unmap_single should be used.
129 * @unmap_len: Length of this fragment to unmap
131 struct efx_tx_buffer {
132 const struct sk_buff *skb;
133 struct efx_tso_header *tsoh;
138 unsigned short unmap_len;
142 * struct efx_tx_queue - An Efx TX queue
144 * This is a ring buffer of TX fragments.
145 * Since the TX completion path always executes on the same
146 * CPU and the xmit path can operate on different CPUs,
147 * performance is increased by ensuring that the completion
148 * path and the xmit path operate on different cache lines.
149 * This is particularly important if the xmit path is always
150 * executing on one CPU which is different from the completion
151 * path. There is also a cache line for members which are
152 * read but not written on the fast path.
154 * @efx: The associated Efx NIC
155 * @queue: DMA queue number
156 * @channel: The associated channel
157 * @buffer: The software buffer ring
158 * @txd: The hardware descriptor ring
159 * @flushed: Used when handling queue flushing
160 * @read_count: Current read pointer.
161 * This is the number of buffers that have been removed from both rings.
162 * @stopped: Stopped count.
163 * Set if this TX queue is currently stopping its port.
164 * @insert_count: Current insert pointer
165 * This is the number of buffers that have been added to the
167 * @write_count: Current write pointer
168 * This is the number of buffers that have been added to the
170 * @old_read_count: The value of read_count when last checked.
171 * This is here for performance reasons. The xmit path will
172 * only get the up-to-date value of read_count if this
173 * variable indicates that the queue is full. This is to
174 * avoid cache-line ping-pong between the xmit path and the
176 * @tso_headers_free: A list of TSO headers allocated for this TX queue
177 * that are not in use, and so available for new TSO sends. The list
178 * is protected by the TX queue lock.
179 * @tso_bursts: Number of times TSO xmit invoked by kernel
180 * @tso_long_headers: Number of packets with headers too long for standard
182 * @tso_packets: Number of packets via the TSO xmit path
184 struct efx_tx_queue {
185 /* Members which don't change on the fast path */
186 struct efx_nic *efx ____cacheline_aligned_in_smp;
188 struct efx_channel *channel;
190 struct efx_tx_buffer *buffer;
191 struct efx_special_buffer txd;
194 /* Members used mainly on the completion path */
195 unsigned int read_count ____cacheline_aligned_in_smp;
198 /* Members used only on the xmit path */
199 unsigned int insert_count ____cacheline_aligned_in_smp;
200 unsigned int write_count;
201 unsigned int old_read_count;
202 struct efx_tso_header *tso_headers_free;
203 unsigned int tso_bursts;
204 unsigned int tso_long_headers;
205 unsigned int tso_packets;
209 * struct efx_rx_buffer - An Efx RX data buffer
210 * @dma_addr: DMA base address of the buffer
211 * @skb: The associated socket buffer, if any.
212 * If both this and page are %NULL, the buffer slot is currently free.
213 * @page: The associated page buffer, if any.
214 * If both this and skb are %NULL, the buffer slot is currently free.
215 * @data: Pointer to ethernet header
216 * @len: Buffer length, in bytes.
217 * @unmap_addr: DMA address to unmap
219 struct efx_rx_buffer {
225 dma_addr_t unmap_addr;
229 * struct efx_rx_queue - An Efx RX queue
230 * @efx: The associated Efx NIC
231 * @queue: DMA queue number
232 * @channel: The associated channel
233 * @buffer: The software buffer ring
234 * @rxd: The hardware descriptor ring
235 * @added_count: Number of buffers added to the receive queue.
236 * @notified_count: Number of buffers given to NIC (<= @added_count).
237 * @removed_count: Number of buffers removed from the receive queue.
238 * @add_lock: Receive queue descriptor add spin lock.
239 * This lock must be held in order to add buffers to the RX
240 * descriptor ring (rxd and buffer) and to update added_count (but
241 * not removed_count).
242 * @max_fill: RX descriptor maximum fill level (<= ring size)
243 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
245 * @fast_fill_limit: The level to which a fast fill will fill
246 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
247 * @min_fill: RX descriptor minimum non-zero fill level.
248 * This records the minimum fill level observed when a ring
249 * refill was triggered.
250 * @min_overfill: RX descriptor minimum overflow fill level.
251 * This records the minimum fill level at which RX queue
252 * overflow was observed. It should never be set.
253 * @alloc_page_count: RX allocation strategy counter.
254 * @alloc_skb_count: RX allocation strategy counter.
255 * @work: Descriptor push work thread
256 * @buf_page: Page for next RX buffer.
257 * We can use a single page for multiple RX buffers. This tracks
258 * the remaining space in the allocation.
259 * @buf_dma_addr: Page's DMA address.
260 * @buf_data: Page's host address.
261 * @flushed: Use when handling queue flushing
263 struct efx_rx_queue {
266 struct efx_channel *channel;
267 struct efx_rx_buffer *buffer;
268 struct efx_special_buffer rxd;
274 unsigned int max_fill;
275 unsigned int fast_fill_trigger;
276 unsigned int fast_fill_limit;
277 unsigned int min_fill;
278 unsigned int min_overfill;
279 unsigned int alloc_page_count;
280 unsigned int alloc_skb_count;
281 struct delayed_work work;
282 unsigned int slow_fill_count;
284 struct page *buf_page;
285 dma_addr_t buf_dma_addr;
291 * struct efx_buffer - An Efx general-purpose buffer
292 * @addr: host base address of the buffer
293 * @dma_addr: DMA base address of the buffer
294 * @len: Buffer length, in bytes
296 * Falcon uses these buffers for its interrupt status registers and
306 /* Flags for channel->used_flags */
307 #define EFX_USED_BY_RX 1
308 #define EFX_USED_BY_TX 2
309 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
311 enum efx_rx_alloc_method {
312 RX_ALLOC_METHOD_AUTO = 0,
313 RX_ALLOC_METHOD_SKB = 1,
314 RX_ALLOC_METHOD_PAGE = 2,
318 * struct efx_channel - An Efx channel
320 * A channel comprises an event queue, at least one TX queue, at least
321 * one RX queue, and an associated tasklet for processing the event
324 * @efx: Associated Efx NIC
325 * @channel: Channel instance number
326 * @name: Name for channel and IRQ
327 * @used_flags: Channel is used by net driver
328 * @enabled: Channel enabled indicator
329 * @irq: IRQ number (MSI and MSI-X only)
330 * @irq_moderation: IRQ moderation value (in hardware ticks)
331 * @napi_dev: Net device used with NAPI
332 * @napi_str: NAPI control structure
333 * @reset_work: Scheduled reset work thread
334 * @work_pending: Is work pending via NAPI?
335 * @eventq: Event queue buffer
336 * @eventq_read_ptr: Event queue read pointer
337 * @last_eventq_read_ptr: Last event queue read pointer value.
338 * @eventq_magic: Event queue magic value for driver-generated test events
339 * @irq_count: Number of IRQs since last adaptive moderation decision
340 * @irq_mod_score: IRQ moderation score
341 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
342 * and diagnostic counters
343 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
345 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
346 * @n_rx_ip_frag_err: Count of RX IP fragment errors
347 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
348 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
349 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
350 * @n_rx_overlength: Count of RX_OVERLENGTH errors
351 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
356 char name[IFNAMSIZ + 6];
360 unsigned int irq_moderation;
361 struct net_device *napi_dev;
362 struct napi_struct napi_str;
364 struct efx_special_buffer eventq;
365 unsigned int eventq_read_ptr;
366 unsigned int last_eventq_read_ptr;
367 unsigned int eventq_magic;
369 unsigned int irq_count;
370 unsigned int irq_mod_score;
373 int rx_alloc_push_pages;
375 unsigned n_rx_tobe_disc;
376 unsigned n_rx_ip_frag_err;
377 unsigned n_rx_ip_hdr_chksum_err;
378 unsigned n_rx_tcp_udp_chksum_err;
379 unsigned n_rx_frm_trunc;
380 unsigned n_rx_overlength;
381 unsigned n_skbuff_leaks;
383 /* Used to pipeline received packets in order to optimise memory
384 * access with prefetches.
386 struct efx_rx_buffer *rx_pkt;
392 * struct efx_board - board information
393 * @type: Board model type
394 * @major: Major rev. ('A', 'B' ...)
395 * @minor: Minor rev. (0, 1, ...)
396 * @init: Initialisation function
397 * @init_leds: Sets up board LEDs. May be called repeatedly.
398 * @set_id_led: Turns the identification LED on or off
399 * @blink: Starts/stops blinking
400 * @monitor: Board-specific health check function
401 * @fini: Cleanup function
402 * @blink_state: Current blink state
403 * @blink_resubmit: Blink timer resubmission flag
404 * @blink_timer: Blink timer
405 * @hwmon_client: I2C client for hardware monitor
406 * @ioexp_client: I2C client for power/port control
412 int (*init) (struct efx_nic *nic);
413 /* As the LEDs are typically attached to the PHY, LEDs
414 * have a separate init callback that happens later than
416 void (*init_leds)(struct efx_nic *efx);
417 void (*set_id_led) (struct efx_nic *efx, bool state);
418 int (*monitor) (struct efx_nic *nic);
419 void (*blink) (struct efx_nic *efx, bool start);
420 void (*fini) (struct efx_nic *nic);
423 struct timer_list blink_timer;
424 struct i2c_client *hwmon_client, *ioexp_client;
427 #define STRING_TABLE_LOOKUP(val, member) \
428 member ## _names[val]
431 /* Be careful if altering to correct macro below */
432 EFX_INT_MODE_MSIX = 0,
433 EFX_INT_MODE_MSI = 1,
434 EFX_INT_MODE_LEGACY = 2,
435 EFX_INT_MODE_MAX /* Insert any new items before this */
437 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
441 PHY_TYPE_TXC43128 = 1,
442 PHY_TYPE_88E1111 = 2,
443 PHY_TYPE_SFX7101 = 3,
444 PHY_TYPE_QT2022C2 = 4,
446 PHY_TYPE_SFT9001A = 8,
447 PHY_TYPE_QT2025C = 9,
448 PHY_TYPE_SFT9001B = 10,
449 PHY_TYPE_MAX /* Insert any new items before this */
452 #define EFX_IS10G(efx) ((efx)->link_speed == 10000)
463 * Alignment of page-allocated RX buffers
465 * Controls the number of bytes inserted at the start of an RX buffer.
466 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
467 * of the skb->head for hardware DMA].
469 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
470 #define EFX_PAGE_IP_ALIGN 0
472 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
476 * Alignment of the skb->head which wraps a page-allocated RX buffer
478 * The skb allocated to wrap an rx_buffer can have this alignment. Since
479 * the data is memcpy'd from the rx_buf, it does not need to be equal to
482 #define EFX_PAGE_SKB_ALIGN 2
484 /* Forward declaration */
487 /* Pseudo bit-mask flow control field */
489 EFX_FC_RX = FLOW_CTRL_RX,
490 EFX_FC_TX = FLOW_CTRL_TX,
494 /* Supported MAC bit-mask */
500 static inline enum efx_fc_type efx_fc_resolve(enum efx_fc_type wanted_fc,
503 BUILD_BUG_ON(EFX_FC_AUTO & (EFX_FC_RX | EFX_FC_TX));
505 if (!(wanted_fc & EFX_FC_AUTO))
508 return mii_resolve_flowctrl_fdx(mii_advertise_flowctrl(wanted_fc), lpa);
512 * struct efx_mac_operations - Efx MAC operations table
513 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
514 * @update_stats: Update statistics
515 * @irq: Hardware MAC event callback. Serialised by the mac_lock
516 * @poll: Poll for hardware state. Serialised by the mac_lock
518 struct efx_mac_operations {
519 void (*reconfigure) (struct efx_nic *efx);
520 void (*update_stats) (struct efx_nic *efx);
521 void (*irq) (struct efx_nic *efx);
522 void (*poll) (struct efx_nic *efx);
526 * struct efx_phy_operations - Efx PHY operations table
527 * @init: Initialise PHY
528 * @fini: Shut down PHY
529 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
530 * @clear_interrupt: Clear down interrupt
532 * @poll: Poll for hardware state. Serialised by the mac_lock.
533 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
534 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
535 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
536 * (only needed where AN bit is set in mmds)
537 * @num_tests: Number of PHY-specific tests/results
538 * @test_names: Names of the tests/results
539 * @run_tests: Run tests and record results as appropriate.
540 * Flags are the ethtool tests flags.
541 * @mmds: MMD presence mask
542 * @loopbacks: Supported loopback modes mask
544 struct efx_phy_operations {
545 enum efx_mac_type macs;
546 int (*init) (struct efx_nic *efx);
547 void (*fini) (struct efx_nic *efx);
548 void (*reconfigure) (struct efx_nic *efx);
549 void (*clear_interrupt) (struct efx_nic *efx);
550 void (*poll) (struct efx_nic *efx);
551 void (*get_settings) (struct efx_nic *efx,
552 struct ethtool_cmd *ecmd);
553 int (*set_settings) (struct efx_nic *efx,
554 struct ethtool_cmd *ecmd);
555 void (*set_npage_adv) (struct efx_nic *efx, u32);
557 const char *const *test_names;
558 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
564 * @enum efx_phy_mode - PHY operating mode flags
565 * @PHY_MODE_NORMAL: on and should pass traffic
566 * @PHY_MODE_TX_DISABLED: on with TX disabled
567 * @PHY_MODE_LOW_POWER: set to low power through MDIO
568 * @PHY_MODE_OFF: switched off through external control
569 * @PHY_MODE_SPECIAL: on but will not pass traffic
573 PHY_MODE_TX_DISABLED = 1,
574 PHY_MODE_LOW_POWER = 2,
576 PHY_MODE_SPECIAL = 8,
579 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
581 return !!(mode & ~PHY_MODE_TX_DISABLED);
585 * Efx extended statistics
587 * Not all statistics are provided by all supported MACs. The purpose
588 * is this structure is to contain the raw statistics provided by each
591 struct efx_mac_stats {
595 unsigned long tx_packets;
596 unsigned long tx_bad;
597 unsigned long tx_pause;
598 unsigned long tx_control;
599 unsigned long tx_unicast;
600 unsigned long tx_multicast;
601 unsigned long tx_broadcast;
602 unsigned long tx_lt64;
604 unsigned long tx_65_to_127;
605 unsigned long tx_128_to_255;
606 unsigned long tx_256_to_511;
607 unsigned long tx_512_to_1023;
608 unsigned long tx_1024_to_15xx;
609 unsigned long tx_15xx_to_jumbo;
610 unsigned long tx_gtjumbo;
611 unsigned long tx_collision;
612 unsigned long tx_single_collision;
613 unsigned long tx_multiple_collision;
614 unsigned long tx_excessive_collision;
615 unsigned long tx_deferred;
616 unsigned long tx_late_collision;
617 unsigned long tx_excessive_deferred;
618 unsigned long tx_non_tcpudp;
619 unsigned long tx_mac_src_error;
620 unsigned long tx_ip_src_error;
624 unsigned long rx_packets;
625 unsigned long rx_good;
626 unsigned long rx_bad;
627 unsigned long rx_pause;
628 unsigned long rx_control;
629 unsigned long rx_unicast;
630 unsigned long rx_multicast;
631 unsigned long rx_broadcast;
632 unsigned long rx_lt64;
634 unsigned long rx_65_to_127;
635 unsigned long rx_128_to_255;
636 unsigned long rx_256_to_511;
637 unsigned long rx_512_to_1023;
638 unsigned long rx_1024_to_15xx;
639 unsigned long rx_15xx_to_jumbo;
640 unsigned long rx_gtjumbo;
641 unsigned long rx_bad_lt64;
642 unsigned long rx_bad_64_to_15xx;
643 unsigned long rx_bad_15xx_to_jumbo;
644 unsigned long rx_bad_gtjumbo;
645 unsigned long rx_overflow;
646 unsigned long rx_missed;
647 unsigned long rx_false_carrier;
648 unsigned long rx_symbol_error;
649 unsigned long rx_align_error;
650 unsigned long rx_length_error;
651 unsigned long rx_internal_error;
652 unsigned long rx_good_lt64;
655 /* Number of bits used in a multicast filter hash address */
656 #define EFX_MCAST_HASH_BITS 8
658 /* Number of (single-bit) entries in a multicast filter hash */
659 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
661 /* An Efx multicast filter hash */
662 union efx_multicast_hash {
663 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
664 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
668 * struct efx_nic - an Efx NIC
669 * @name: Device name (net device name or bus id before net device registered)
670 * @pci_dev: The PCI device
671 * @type: Controller type attributes
672 * @legacy_irq: IRQ number
673 * @workqueue: Workqueue for port reconfigures and the HW monitor.
674 * Work items do not hold and must not acquire RTNL.
675 * @workqueue_name: Name of workqueue
676 * @reset_work: Scheduled reset workitem
677 * @monitor_work: Hardware monitor workitem
678 * @membase_phys: Memory BAR value as physical address
679 * @membase: Memory BAR value
680 * @biu_lock: BIU (bus interface unit) lock
681 * @interrupt_mode: Interrupt mode
682 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
683 * @irq_rx_moderation: IRQ moderation time for RX event queues
684 * @i2c_adap: I2C adapter
685 * @board_info: Board-level information
686 * @state: Device state flag. Serialised by the rtnl_lock.
687 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
688 * @tx_queue: TX DMA queues
689 * @rx_queue: RX DMA queues
691 * @next_buffer_table: First available buffer table id
692 * @n_rx_queues: Number of RX queues
693 * @n_channels: Number of channels in use
694 * @rx_buffer_len: RX buffer length
695 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
696 * @int_error_count: Number of internal errors seen recently
697 * @int_error_expire: Time at which error count will be expired
698 * @irq_status: Interrupt status buffer
699 * @last_irq_cpu: Last CPU to handle interrupt.
700 * This register is written with the SMP processor ID whenever an
701 * interrupt is handled. It is used by falcon_test_interrupt()
702 * to verify that an interrupt has occurred.
703 * @spi_flash: SPI flash device
704 * This field will be %NULL if no flash device is present.
705 * @spi_eeprom: SPI EEPROM device
706 * This field will be %NULL if no EEPROM device is present.
707 * @spi_lock: SPI bus lock
708 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
709 * @nic_data: Hardware dependant state
710 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
711 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
712 * @port_enabled: Port enabled indicator.
713 * Serialises efx_stop_all(), efx_start_all(), efx_monitor(),
714 * efx_phy_work(), and efx_mac_work() with kernel interfaces. Safe to read
715 * under any one of the rtnl_lock, mac_lock, or netif_tx_lock, but all
716 * three must be held to modify it.
717 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
718 * @port_initialized: Port initialized?
719 * @net_dev: Operating system network device. Consider holding the rtnl lock
720 * @rx_checksum_enabled: RX checksumming enabled
721 * @netif_stop_count: Port stop count
722 * @netif_stop_lock: Port stop lock
723 * @mac_stats: MAC statistics. These include all statistics the MACs
724 * can provide. Generic code converts these into a standard
725 * &struct net_device_stats.
726 * @stats_buffer: DMA buffer for statistics
727 * @stats_lock: Statistics update lock. Serialises statistics fetches
728 * @stats_disable_count: Nest count for disabling statistics fetches
729 * @mac_op: MAC interface
730 * @mac_address: Permanent MAC address
731 * @phy_type: PHY type
732 * @phy_lock: PHY access lock
733 * @phy_op: PHY interface
734 * @phy_data: PHY private data (including PHY-specific stats)
735 * @mdio: PHY MDIO interface
736 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
737 * @mac_up: MAC link state
738 * @link_up: Link status
739 * @link_fd: Link is full duplex
740 * @link_fc: Actualy flow control flags
741 * @link_speed: Link speed (Mbps)
742 * @n_link_state_changes: Number of times the link has changed state
743 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
744 * @multicast_hash: Multicast hash table
745 * @wanted_fc: Wanted flow control flags
746 * @phy_work: work item for dealing with PHY events
747 * @mac_work: work item for dealing with MAC events
748 * @loopback_mode: Loopback status
749 * @loopback_modes: Supported loopback mode bitmask
750 * @loopback_selftest: Offline self-test private state
752 * The @priv field of the corresponding &struct net_device points to
757 struct pci_dev *pci_dev;
758 const struct efx_nic_type *type;
760 struct workqueue_struct *workqueue;
761 char workqueue_name[16];
762 struct work_struct reset_work;
763 struct delayed_work monitor_work;
764 resource_size_t membase_phys;
765 void __iomem *membase;
767 enum efx_int_mode interrupt_mode;
768 bool irq_rx_adaptive;
769 unsigned int irq_rx_moderation;
771 struct i2c_adapter i2c_adap;
772 struct efx_board board_info;
774 enum nic_state state;
775 enum reset_type reset_pending;
777 struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
778 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
779 struct efx_channel channel[EFX_MAX_CHANNELS];
781 unsigned next_buffer_table;
784 unsigned int rx_buffer_len;
785 unsigned int rx_buffer_order;
787 unsigned int_error_count;
788 unsigned long int_error_expire;
790 struct efx_buffer irq_status;
791 volatile signed int last_irq_cpu;
793 struct efx_spi_device *spi_flash;
794 struct efx_spi_device *spi_eeprom;
795 struct mutex spi_lock;
797 unsigned n_rx_nodesc_drop_cnt;
799 struct falcon_nic_data *nic_data;
801 struct mutex mac_lock;
802 struct work_struct mac_work;
806 bool port_initialized;
807 struct net_device *net_dev;
808 bool rx_checksum_enabled;
810 atomic_t netif_stop_count;
811 spinlock_t netif_stop_lock;
813 struct efx_mac_stats mac_stats;
814 struct efx_buffer stats_buffer;
815 spinlock_t stats_lock;
816 unsigned int stats_disable_count;
818 struct efx_mac_operations *mac_op;
819 unsigned char mac_address[ETH_ALEN];
821 enum phy_type phy_type;
823 struct work_struct phy_work;
824 struct efx_phy_operations *phy_op;
826 struct mdio_if_info mdio;
827 enum efx_phy_mode phy_mode;
832 enum efx_fc_type link_fc;
833 unsigned int link_speed;
834 unsigned int n_link_state_changes;
837 union efx_multicast_hash multicast_hash;
838 enum efx_fc_type wanted_fc;
841 enum efx_loopback_mode loopback_mode;
842 unsigned int loopback_modes;
844 void *loopback_selftest;
847 static inline int efx_dev_registered(struct efx_nic *efx)
849 return efx->net_dev->reg_state == NETREG_REGISTERED;
852 /* Net device name, for inclusion in log messages if it has been registered.
853 * Use efx->name not efx->net_dev->name so that races with (un)registration
856 static inline const char *efx_dev_name(struct efx_nic *efx)
858 return efx_dev_registered(efx) ? efx->name : "";
862 * struct efx_nic_type - Efx device type definition
863 * @mem_bar: Memory BAR number
864 * @mem_map_size: Memory BAR mapped size
865 * @txd_ptr_tbl_base: TX descriptor ring base address
866 * @rxd_ptr_tbl_base: RX descriptor ring base address
867 * @buf_tbl_base: Buffer table base address
868 * @evq_ptr_tbl_base: Event queue pointer table base address
869 * @evq_rptr_tbl_base: Event queue read-pointer table base address
870 * @max_dma_mask: Maximum possible DMA mask
871 * @rx_buffer_padding: Padding added to each RX buffer
872 * @max_interrupt_mode: Highest capability interrupt mode supported
873 * from &enum efx_init_mode.
874 * @phys_addr_channels: Number of channels with physically addressed
877 struct efx_nic_type {
878 unsigned int mem_bar;
879 unsigned int mem_map_size;
880 unsigned int txd_ptr_tbl_base;
881 unsigned int rxd_ptr_tbl_base;
882 unsigned int buf_tbl_base;
883 unsigned int evq_ptr_tbl_base;
884 unsigned int evq_rptr_tbl_base;
888 unsigned int rx_buffer_padding;
889 unsigned int max_interrupt_mode;
890 unsigned int phys_addr_channels;
893 /**************************************************************************
895 * Prototypes and inline functions
897 *************************************************************************/
899 /* Iterate over all used channels */
900 #define efx_for_each_channel(_channel, _efx) \
901 for (_channel = &_efx->channel[0]; \
902 _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
904 if (!_channel->used_flags) \
908 /* Iterate over all used TX queues */
909 #define efx_for_each_tx_queue(_tx_queue, _efx) \
910 for (_tx_queue = &_efx->tx_queue[0]; \
911 _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
914 /* Iterate over all TX queues belonging to a channel */
915 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
916 for (_tx_queue = &_channel->efx->tx_queue[0]; \
917 _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
919 if (_tx_queue->channel != _channel) \
923 /* Iterate over all used RX queues */
924 #define efx_for_each_rx_queue(_rx_queue, _efx) \
925 for (_rx_queue = &_efx->rx_queue[0]; \
926 _rx_queue < &_efx->rx_queue[_efx->n_rx_queues]; \
929 /* Iterate over all RX queues belonging to a channel */
930 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
931 for (_rx_queue = &_channel->efx->rx_queue[_channel->channel]; \
934 if (_rx_queue->channel != _channel) \
938 /* Returns a pointer to the specified receive buffer in the RX
941 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
944 return (&rx_queue->buffer[index]);
947 /* Set bit in a little-endian bitfield */
948 static inline void set_bit_le(unsigned nr, unsigned char *addr)
950 addr[nr / 8] |= (1 << (nr % 8));
953 /* Clear bit in a little-endian bitfield */
954 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
956 addr[nr / 8] &= ~(1 << (nr % 8));
961 * EFX_MAX_FRAME_LEN - calculate maximum frame length
963 * This calculates the maximum frame length that will be used for a
964 * given MTU. The frame length will be equal to the MTU plus a
965 * constant amount of header space and padding. This is the quantity
966 * that the net driver will program into the MAC as the maximum frame
969 * The 10G MAC used in Falcon requires 8-byte alignment on the frame
970 * length, so we round up to the nearest 8.
972 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
973 * XGMII cycle). If the frame length reaches the maximum value in the
974 * same cycle, the XMAC can miss the IPG altogether. We work around
975 * this by adding a further 16 bytes.
977 #define EFX_MAX_FRAME_LEN(mtu) \
978 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
981 #endif /* EFX_NET_DRIVER_H */