1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include "net_driver.h"
28 #include "workarounds.h"
30 /* Falcon hardware control.
31 * Falcon is the internal codename for the SFC4000 controller that is
32 * present in SFE400X evaluation boards
35 /**************************************************************************
39 **************************************************************************
42 static int disable_dma_stats;
44 /* This is set to 16 for a good reason. In summary, if larger than
45 * 16, the descriptor cache holds more than a default socket
46 * buffer's worth of packets (for UDP we can only have at most one
47 * socket buffer's worth outstanding). This combined with the fact
48 * that we only get 1 TX event per descriptor cache means the NIC
51 #define TX_DC_ENTRIES 16
52 #define TX_DC_ENTRIES_ORDER 0
53 #define TX_DC_BASE 0x130000
55 #define RX_DC_ENTRIES 64
56 #define RX_DC_ENTRIES_ORDER 2
57 #define RX_DC_BASE 0x100000
59 static const unsigned int
60 /* "Large" EEPROM device: Atmel AT25640 or similar
61 * 8 KB, 16-bit address, 32 B write block */
62 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
63 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
64 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
65 /* Default flash device: Atmel AT25F1024
66 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
67 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
68 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
69 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
70 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
71 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
73 /* RX FIFO XOFF watermark
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
79 static int rx_xoff_thresh_bytes = -1;
80 module_param(rx_xoff_thresh_bytes, int, 0644);
81 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
83 /* RX FIFO XON watermark
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
89 static int rx_xon_thresh_bytes = -1;
90 module_param(rx_xon_thresh_bytes, int, 0644);
91 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
93 /* If FALCON_MAX_INT_ERRORS internal errors occur within
94 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
97 #define FALCON_INT_ERROR_EXPIRE 3600
98 #define FALCON_MAX_INT_ERRORS 5
100 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
102 #define FALCON_FLUSH_INTERVAL 10
103 #define FALCON_FLUSH_POLL_COUNT 100
105 /**************************************************************************
109 **************************************************************************
112 /* Size and alignment of special buffers (4KB) */
113 #define FALCON_BUF_SIZE 4096
115 /* Dummy SRAM size code */
116 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
118 #define FALCON_IS_DUAL_FUNC(efx) \
119 (falcon_rev(efx) < FALCON_REV_B0)
121 /**************************************************************************
123 * Falcon hardware access
125 **************************************************************************/
127 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
130 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
134 /* Read the current event from the event queue */
135 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
138 return (((efx_qword_t *) (channel->eventq.addr)) + index);
141 /* See if an event is present
143 * We check both the high and low dword of the event for all ones. We
144 * wrote all ones when we cleared the event, and no valid event can
145 * have all ones in either its high or low dwords. This approach is
146 * robust against reordering.
148 * Note that using a single 64-bit comparison is incorrect; even
149 * though the CPU read will be atomic, the DMA write may not be.
151 static inline int falcon_event_present(efx_qword_t *event)
153 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
154 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
157 /**************************************************************************
159 * I2C bus - this is a bit-bashing interface using GPIO pins
160 * Note that it uses the output enables to tristate the outputs
161 * SDA is the data pin and SCL is the clock
163 **************************************************************************
165 static void falcon_setsda(void *data, int state)
167 struct efx_nic *efx = (struct efx_nic *)data;
170 efx_reado(efx, ®, FR_AB_GPIO_CTL);
171 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
172 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
175 static void falcon_setscl(void *data, int state)
177 struct efx_nic *efx = (struct efx_nic *)data;
180 efx_reado(efx, ®, FR_AB_GPIO_CTL);
181 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
182 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
185 static int falcon_getsda(void *data)
187 struct efx_nic *efx = (struct efx_nic *)data;
190 efx_reado(efx, ®, FR_AB_GPIO_CTL);
191 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
194 static int falcon_getscl(void *data)
196 struct efx_nic *efx = (struct efx_nic *)data;
199 efx_reado(efx, ®, FR_AB_GPIO_CTL);
200 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
203 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
204 .setsda = falcon_setsda,
205 .setscl = falcon_setscl,
206 .getsda = falcon_getsda,
207 .getscl = falcon_getscl,
209 /* Wait up to 50 ms for slave to let us pull SCL high */
210 .timeout = DIV_ROUND_UP(HZ, 20),
213 /**************************************************************************
215 * Falcon special buffer handling
216 * Special buffers are used for event queues and the TX and RX
219 *************************************************************************/
222 * Initialise a Falcon special buffer
224 * This will define a buffer (previously allocated via
225 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
226 * it to be used for event queues, descriptor rings etc.
229 falcon_init_special_buffer(struct efx_nic *efx,
230 struct efx_special_buffer *buffer)
232 efx_qword_t buf_desc;
237 EFX_BUG_ON_PARANOID(!buffer->addr);
239 /* Write buffer descriptors to NIC */
240 for (i = 0; i < buffer->entries; i++) {
241 index = buffer->index + i;
242 dma_addr = buffer->dma_addr + (i * 4096);
243 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
244 index, (unsigned long long)dma_addr);
245 EFX_POPULATE_QWORD_3(buf_desc,
246 FRF_AZ_BUF_ADR_REGION, 0,
247 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
248 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
249 falcon_write_buf_tbl(efx, &buf_desc, index);
253 /* Unmaps a buffer from Falcon and clears the buffer table entries */
255 falcon_fini_special_buffer(struct efx_nic *efx,
256 struct efx_special_buffer *buffer)
258 efx_oword_t buf_tbl_upd;
259 unsigned int start = buffer->index;
260 unsigned int end = (buffer->index + buffer->entries - 1);
262 if (!buffer->entries)
265 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
266 buffer->index, buffer->index + buffer->entries - 1);
268 EFX_POPULATE_OWORD_4(buf_tbl_upd,
269 FRF_AZ_BUF_UPD_CMD, 0,
270 FRF_AZ_BUF_CLR_CMD, 1,
271 FRF_AZ_BUF_CLR_END_ID, end,
272 FRF_AZ_BUF_CLR_START_ID, start);
273 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
277 * Allocate a new Falcon special buffer
279 * This allocates memory for a new buffer, clears it and allocates a
280 * new buffer ID range. It does not write into Falcon's buffer table.
282 * This call will allocate 4KB buffers, since Falcon can't use 8KB
283 * buffers for event queues and descriptor rings.
285 static int falcon_alloc_special_buffer(struct efx_nic *efx,
286 struct efx_special_buffer *buffer,
289 len = ALIGN(len, FALCON_BUF_SIZE);
291 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
296 buffer->entries = len / FALCON_BUF_SIZE;
297 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
299 /* All zeros is a potentially valid event so memset to 0xff */
300 memset(buffer->addr, 0xff, len);
302 /* Select new buffer ID */
303 buffer->index = efx->next_buffer_table;
304 efx->next_buffer_table += buffer->entries;
306 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
307 "(virt %p phys %llx)\n", buffer->index,
308 buffer->index + buffer->entries - 1,
309 (u64)buffer->dma_addr, len,
310 buffer->addr, (u64)virt_to_phys(buffer->addr));
315 static void falcon_free_special_buffer(struct efx_nic *efx,
316 struct efx_special_buffer *buffer)
321 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
322 "(virt %p phys %llx)\n", buffer->index,
323 buffer->index + buffer->entries - 1,
324 (u64)buffer->dma_addr, buffer->len,
325 buffer->addr, (u64)virt_to_phys(buffer->addr));
327 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
333 /**************************************************************************
335 * Falcon generic buffer handling
336 * These buffers are used for interrupt status and MAC stats
338 **************************************************************************/
340 static int falcon_alloc_buffer(struct efx_nic *efx,
341 struct efx_buffer *buffer, unsigned int len)
343 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
348 memset(buffer->addr, 0, len);
352 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
355 pci_free_consistent(efx->pci_dev, buffer->len,
356 buffer->addr, buffer->dma_addr);
361 /**************************************************************************
365 **************************************************************************/
367 /* Returns a pointer to the specified transmit descriptor in the TX
368 * descriptor queue belonging to the specified channel.
370 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
373 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
376 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
377 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
382 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
383 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
384 efx_writed_page(tx_queue->efx, ®,
385 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
389 /* For each entry inserted into the software descriptor ring, create a
390 * descriptor in the hardware TX descriptor ring (in host memory), and
393 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
396 struct efx_tx_buffer *buffer;
400 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
403 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
404 buffer = &tx_queue->buffer[write_ptr];
405 txd = falcon_tx_desc(tx_queue, write_ptr);
406 ++tx_queue->write_count;
408 /* Create TX descriptor ring entry */
409 EFX_POPULATE_QWORD_4(*txd,
410 FSF_AZ_TX_KER_CONT, buffer->continuation,
411 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
412 FSF_AZ_TX_KER_BUF_REGION, 0,
413 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
414 } while (tx_queue->write_count != tx_queue->insert_count);
416 wmb(); /* Ensure descriptors are written before they are fetched */
417 falcon_notify_tx_desc(tx_queue);
420 /* Allocate hardware resources for a TX queue */
421 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
423 struct efx_nic *efx = tx_queue->efx;
424 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
425 EFX_TXQ_SIZE & EFX_TXQ_MASK);
426 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
427 EFX_TXQ_SIZE * sizeof(efx_qword_t));
430 void falcon_init_tx(struct efx_tx_queue *tx_queue)
432 efx_oword_t tx_desc_ptr;
433 struct efx_nic *efx = tx_queue->efx;
435 tx_queue->flushed = false;
437 /* Pin TX descriptor ring */
438 falcon_init_special_buffer(efx, &tx_queue->txd);
440 /* Push TX descriptor ring to card */
441 EFX_POPULATE_OWORD_10(tx_desc_ptr,
442 FRF_AZ_TX_DESCQ_EN, 1,
443 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
444 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
445 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
446 FRF_AZ_TX_DESCQ_EVQ_ID,
447 tx_queue->channel->channel,
448 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
449 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
450 FRF_AZ_TX_DESCQ_SIZE,
451 __ffs(tx_queue->txd.entries),
452 FRF_AZ_TX_DESCQ_TYPE, 0,
453 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
455 if (falcon_rev(efx) >= FALCON_REV_B0) {
456 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
457 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
458 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
462 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
465 if (falcon_rev(efx) < FALCON_REV_B0) {
468 /* Only 128 bits in this register */
469 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
471 efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG);
472 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
473 clear_bit_le(tx_queue->queue, (void *)®);
475 set_bit_le(tx_queue->queue, (void *)®);
476 efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG);
480 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
482 struct efx_nic *efx = tx_queue->efx;
483 efx_oword_t tx_flush_descq;
485 /* Post a flush command */
486 EFX_POPULATE_OWORD_2(tx_flush_descq,
487 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
488 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
489 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
492 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
494 struct efx_nic *efx = tx_queue->efx;
495 efx_oword_t tx_desc_ptr;
497 /* The queue should have been flushed */
498 WARN_ON(!tx_queue->flushed);
500 /* Remove TX descriptor ring from card */
501 EFX_ZERO_OWORD(tx_desc_ptr);
502 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
505 /* Unpin TX descriptor ring */
506 falcon_fini_special_buffer(efx, &tx_queue->txd);
509 /* Free buffers backing TX queue */
510 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
512 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
515 /**************************************************************************
519 **************************************************************************/
521 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
522 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
525 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
528 /* This creates an entry in the RX descriptor queue */
529 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
532 struct efx_rx_buffer *rx_buf;
535 rxd = falcon_rx_desc(rx_queue, index);
536 rx_buf = efx_rx_buffer(rx_queue, index);
537 EFX_POPULATE_QWORD_3(*rxd,
538 FSF_AZ_RX_KER_BUF_SIZE,
540 rx_queue->efx->type->rx_buffer_padding,
541 FSF_AZ_RX_KER_BUF_REGION, 0,
542 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
545 /* This writes to the RX_DESC_WPTR register for the specified receive
548 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
553 while (rx_queue->notified_count != rx_queue->added_count) {
554 falcon_build_rx_desc(rx_queue,
555 rx_queue->notified_count &
557 ++rx_queue->notified_count;
561 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
562 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
563 efx_writed_page(rx_queue->efx, ®,
564 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
567 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
569 struct efx_nic *efx = rx_queue->efx;
570 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
571 EFX_RXQ_SIZE & EFX_RXQ_MASK);
572 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
573 EFX_RXQ_SIZE * sizeof(efx_qword_t));
576 void falcon_init_rx(struct efx_rx_queue *rx_queue)
578 efx_oword_t rx_desc_ptr;
579 struct efx_nic *efx = rx_queue->efx;
580 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
581 bool iscsi_digest_en = is_b0;
583 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
584 rx_queue->queue, rx_queue->rxd.index,
585 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
587 rx_queue->flushed = false;
589 /* Pin RX descriptor ring */
590 falcon_init_special_buffer(efx, &rx_queue->rxd);
592 /* Push RX descriptor ring to card */
593 EFX_POPULATE_OWORD_10(rx_desc_ptr,
594 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
595 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
596 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
597 FRF_AZ_RX_DESCQ_EVQ_ID,
598 rx_queue->channel->channel,
599 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
600 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
601 FRF_AZ_RX_DESCQ_SIZE,
602 __ffs(rx_queue->rxd.entries),
603 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
604 /* For >=B0 this is scatter so disable */
605 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
606 FRF_AZ_RX_DESCQ_EN, 1);
607 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
611 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
613 struct efx_nic *efx = rx_queue->efx;
614 efx_oword_t rx_flush_descq;
616 /* Post a flush command */
617 EFX_POPULATE_OWORD_2(rx_flush_descq,
618 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
619 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
620 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
623 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
625 efx_oword_t rx_desc_ptr;
626 struct efx_nic *efx = rx_queue->efx;
628 /* The queue should already have been flushed */
629 WARN_ON(!rx_queue->flushed);
631 /* Remove RX descriptor ring from card */
632 EFX_ZERO_OWORD(rx_desc_ptr);
633 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
636 /* Unpin RX descriptor ring */
637 falcon_fini_special_buffer(efx, &rx_queue->rxd);
640 /* Free buffers backing RX queue */
641 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
643 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
646 /**************************************************************************
648 * Falcon event queue processing
649 * Event queues are processed by per-channel tasklets.
651 **************************************************************************/
653 /* Update a channel's event queue's read pointer (RPTR) register
655 * This writes the EVQ_RPTR_REG register for the specified channel's
658 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
659 * whereas channel->eventq_read_ptr contains the index of the "next to
662 void falcon_eventq_read_ack(struct efx_channel *channel)
665 struct efx_nic *efx = channel->efx;
667 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
668 efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base,
672 /* Use HW to insert a SW defined event */
673 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
675 efx_oword_t drv_ev_reg;
677 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
678 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
679 drv_ev_reg.u32[0] = event->u32[0];
680 drv_ev_reg.u32[1] = event->u32[1];
681 drv_ev_reg.u32[2] = 0;
682 drv_ev_reg.u32[3] = 0;
683 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
684 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
687 /* Handle a transmit completion event
689 * Falcon batches TX completion events; the message we receive is of
690 * the form "complete all TX events up to this index".
692 static void falcon_handle_tx_event(struct efx_channel *channel,
695 unsigned int tx_ev_desc_ptr;
696 unsigned int tx_ev_q_label;
697 struct efx_tx_queue *tx_queue;
698 struct efx_nic *efx = channel->efx;
700 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
701 /* Transmit completion */
702 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
703 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
704 tx_queue = &efx->tx_queue[tx_ev_q_label];
705 channel->irq_mod_score +=
706 (tx_ev_desc_ptr - tx_queue->read_count) &
708 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
709 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
710 /* Rewrite the FIFO write pointer */
711 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
712 tx_queue = &efx->tx_queue[tx_ev_q_label];
714 if (efx_dev_registered(efx))
715 netif_tx_lock(efx->net_dev);
716 falcon_notify_tx_desc(tx_queue);
717 if (efx_dev_registered(efx))
718 netif_tx_unlock(efx->net_dev);
719 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
720 EFX_WORKAROUND_10727(efx)) {
721 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
723 EFX_ERR(efx, "channel %d unexpected TX event "
724 EFX_QWORD_FMT"\n", channel->channel,
725 EFX_QWORD_VAL(*event));
729 /* Detect errors included in the rx_evt_pkt_ok bit. */
730 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
731 const efx_qword_t *event,
735 struct efx_nic *efx = rx_queue->efx;
736 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
737 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
738 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
739 bool rx_ev_other_err, rx_ev_pause_frm;
740 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
741 unsigned rx_ev_pkt_type;
743 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
744 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
745 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
746 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
747 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
748 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
749 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
750 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
751 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
752 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
753 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
754 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
755 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
756 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
757 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
758 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
760 /* Every error apart from tobe_disc and pause_frm */
761 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
762 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
763 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
765 /* Count errors that are not in MAC stats. Ignore expected
766 * checksum errors during self-test. */
768 ++rx_queue->channel->n_rx_frm_trunc;
769 else if (rx_ev_tobe_disc)
770 ++rx_queue->channel->n_rx_tobe_disc;
771 else if (!efx->loopback_selftest) {
772 if (rx_ev_ip_hdr_chksum_err)
773 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
774 else if (rx_ev_tcp_udp_chksum_err)
775 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
777 if (rx_ev_ip_frag_err)
778 ++rx_queue->channel->n_rx_ip_frag_err;
780 /* The frame must be discarded if any of these are true. */
781 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
782 rx_ev_tobe_disc | rx_ev_pause_frm);
784 /* TOBE_DISC is expected on unicast mismatches; don't print out an
785 * error message. FRM_TRUNC indicates RXDP dropped the packet due
786 * to a FIFO overflow.
788 #ifdef EFX_ENABLE_DEBUG
789 if (rx_ev_other_err) {
790 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
791 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
792 rx_queue->queue, EFX_QWORD_VAL(*event),
793 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
794 rx_ev_ip_hdr_chksum_err ?
795 " [IP_HDR_CHKSUM_ERR]" : "",
796 rx_ev_tcp_udp_chksum_err ?
797 " [TCP_UDP_CHKSUM_ERR]" : "",
798 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
799 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
800 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
801 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
802 rx_ev_pause_frm ? " [PAUSE]" : "");
807 /* Handle receive events that are not in-order. */
808 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
811 struct efx_nic *efx = rx_queue->efx;
812 unsigned expected, dropped;
814 expected = rx_queue->removed_count & EFX_RXQ_MASK;
815 dropped = (index - expected) & EFX_RXQ_MASK;
816 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
817 dropped, index, expected);
819 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
820 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
823 /* Handle a packet received event
825 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
826 * wrong destination address
827 * Also "is multicast" and "matches multicast filter" flags can be used to
828 * discard non-matching multicast packets.
830 static void falcon_handle_rx_event(struct efx_channel *channel,
831 const efx_qword_t *event)
833 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
834 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
835 unsigned expected_ptr;
836 bool rx_ev_pkt_ok, discard = false, checksummed;
837 struct efx_rx_queue *rx_queue;
838 struct efx_nic *efx = channel->efx;
840 /* Basic packet information */
841 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
842 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
843 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
844 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
845 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
846 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
849 rx_queue = &efx->rx_queue[channel->channel];
851 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
852 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
853 if (unlikely(rx_ev_desc_ptr != expected_ptr))
854 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
856 if (likely(rx_ev_pkt_ok)) {
857 /* If packet is marked as OK and packet type is TCP/IPv4 or
858 * UDP/IPv4, then we can rely on the hardware checksum.
861 efx->rx_checksum_enabled &&
862 (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
863 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP);
865 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
870 /* Detect multicast packets that didn't match the filter */
871 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
872 if (rx_ev_mcast_pkt) {
873 unsigned int rx_ev_mcast_hash_match =
874 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
876 if (unlikely(!rx_ev_mcast_hash_match))
880 channel->irq_mod_score += 2;
882 /* Handle received packet */
883 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
884 checksummed, discard);
887 /* Global events are basically PHY events */
888 static void falcon_handle_global_event(struct efx_channel *channel,
891 struct efx_nic *efx = channel->efx;
892 bool handled = false;
894 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
895 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
896 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
897 efx->phy_op->clear_interrupt(efx);
898 queue_work(efx->workqueue, &efx->phy_work);
902 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
903 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
904 queue_work(efx->workqueue, &efx->mac_work);
908 if (falcon_rev(efx) <= FALCON_REV_A1 ?
909 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
910 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
911 EFX_ERR(efx, "channel %d seen global RX_RESET "
912 "event. Resetting.\n", channel->channel);
914 atomic_inc(&efx->rx_reset);
915 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
916 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
921 EFX_ERR(efx, "channel %d unknown global event "
922 EFX_QWORD_FMT "\n", channel->channel,
923 EFX_QWORD_VAL(*event));
926 static void falcon_handle_driver_event(struct efx_channel *channel,
929 struct efx_nic *efx = channel->efx;
930 unsigned int ev_sub_code;
931 unsigned int ev_sub_data;
933 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
934 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
936 switch (ev_sub_code) {
937 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
938 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
939 channel->channel, ev_sub_data);
941 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
942 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
943 channel->channel, ev_sub_data);
945 case FSE_AZ_EVQ_INIT_DONE_EV:
946 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
947 channel->channel, ev_sub_data);
949 case FSE_AZ_SRM_UPD_DONE_EV:
950 EFX_TRACE(efx, "channel %d SRAM update done\n",
953 case FSE_AZ_WAKE_UP_EV:
954 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
955 channel->channel, ev_sub_data);
957 case FSE_AZ_TIMER_EV:
958 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
959 channel->channel, ev_sub_data);
961 case FSE_AA_RX_RECOVER_EV:
962 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
963 "Resetting.\n", channel->channel);
964 atomic_inc(&efx->rx_reset);
965 efx_schedule_reset(efx,
966 EFX_WORKAROUND_6555(efx) ?
967 RESET_TYPE_RX_RECOVERY :
970 case FSE_BZ_RX_DSC_ERROR_EV:
971 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
972 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
973 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
975 case FSE_BZ_TX_DSC_ERROR_EV:
976 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
977 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
978 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
981 EFX_TRACE(efx, "channel %d unknown driver event code %d "
982 "data %04x\n", channel->channel, ev_sub_code,
988 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
990 unsigned int read_ptr;
991 efx_qword_t event, *p_event;
995 read_ptr = channel->eventq_read_ptr;
998 p_event = falcon_event(channel, read_ptr);
1001 if (!falcon_event_present(&event))
1005 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1006 channel->channel, EFX_QWORD_VAL(event));
1008 /* Clear this event by marking it all ones */
1009 EFX_SET_QWORD(*p_event);
1011 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1014 case FSE_AZ_EV_CODE_RX_EV:
1015 falcon_handle_rx_event(channel, &event);
1018 case FSE_AZ_EV_CODE_TX_EV:
1019 falcon_handle_tx_event(channel, &event);
1021 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1022 channel->eventq_magic = EFX_QWORD_FIELD(
1023 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1024 EFX_LOG(channel->efx, "channel %d received generated "
1025 "event "EFX_QWORD_FMT"\n", channel->channel,
1026 EFX_QWORD_VAL(event));
1028 case FSE_AZ_EV_CODE_GLOBAL_EV:
1029 falcon_handle_global_event(channel, &event);
1031 case FSE_AZ_EV_CODE_DRIVER_EV:
1032 falcon_handle_driver_event(channel, &event);
1035 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1036 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1037 ev_code, EFX_QWORD_VAL(event));
1040 /* Increment read pointer */
1041 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1043 } while (rx_packets < rx_quota);
1045 channel->eventq_read_ptr = read_ptr;
1049 void falcon_set_int_moderation(struct efx_channel *channel)
1051 efx_dword_t timer_cmd;
1052 struct efx_nic *efx = channel->efx;
1054 /* Set timer register */
1055 if (channel->irq_moderation) {
1056 EFX_POPULATE_DWORD_2(timer_cmd,
1057 FRF_AB_TC_TIMER_MODE,
1058 FFE_BB_TIMER_MODE_INT_HLDOFF,
1059 FRF_AB_TC_TIMER_VAL,
1060 channel->irq_moderation - 1);
1062 EFX_POPULATE_DWORD_2(timer_cmd,
1063 FRF_AB_TC_TIMER_MODE,
1064 FFE_BB_TIMER_MODE_DIS,
1065 FRF_AB_TC_TIMER_VAL, 0);
1067 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1068 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1073 /* Allocate buffer table entries for event queue */
1074 int falcon_probe_eventq(struct efx_channel *channel)
1076 struct efx_nic *efx = channel->efx;
1077 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1078 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1079 return falcon_alloc_special_buffer(efx, &channel->eventq,
1080 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1083 void falcon_init_eventq(struct efx_channel *channel)
1085 efx_oword_t evq_ptr;
1086 struct efx_nic *efx = channel->efx;
1088 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1089 channel->channel, channel->eventq.index,
1090 channel->eventq.index + channel->eventq.entries - 1);
1092 /* Pin event queue buffer */
1093 falcon_init_special_buffer(efx, &channel->eventq);
1095 /* Fill event queue with all ones (i.e. empty events) */
1096 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1098 /* Push event queue to card */
1099 EFX_POPULATE_OWORD_3(evq_ptr,
1101 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1102 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1103 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1106 falcon_set_int_moderation(channel);
1109 void falcon_fini_eventq(struct efx_channel *channel)
1111 efx_oword_t eventq_ptr;
1112 struct efx_nic *efx = channel->efx;
1114 /* Remove event queue from card */
1115 EFX_ZERO_OWORD(eventq_ptr);
1116 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1119 /* Unpin event queue */
1120 falcon_fini_special_buffer(efx, &channel->eventq);
1123 /* Free buffers backing event queue */
1124 void falcon_remove_eventq(struct efx_channel *channel)
1126 falcon_free_special_buffer(channel->efx, &channel->eventq);
1130 /* Generates a test event on the event queue. A subsequent call to
1131 * process_eventq() should pick up the event and place the value of
1132 * "magic" into channel->eventq_magic;
1134 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1136 efx_qword_t test_event;
1138 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1139 FSE_AZ_EV_CODE_DRV_GEN_EV,
1140 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1141 falcon_generate_event(channel, &test_event);
1144 void falcon_sim_phy_event(struct efx_nic *efx)
1146 efx_qword_t phy_event;
1148 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1149 FSE_AZ_EV_CODE_GLOBAL_EV);
1151 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1153 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1155 falcon_generate_event(&efx->channel[0], &phy_event);
1158 /**************************************************************************
1162 **************************************************************************/
1165 static void falcon_poll_flush_events(struct efx_nic *efx)
1167 struct efx_channel *channel = &efx->channel[0];
1168 struct efx_tx_queue *tx_queue;
1169 struct efx_rx_queue *rx_queue;
1170 unsigned int read_ptr = channel->eventq_read_ptr;
1171 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1174 efx_qword_t *event = falcon_event(channel, read_ptr);
1175 int ev_code, ev_sub_code, ev_queue;
1178 if (!falcon_event_present(event))
1181 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1182 ev_sub_code = EFX_QWORD_FIELD(*event,
1183 FSF_AZ_DRIVER_EV_SUBCODE);
1184 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1185 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1186 ev_queue = EFX_QWORD_FIELD(*event,
1187 FSF_AZ_DRIVER_EV_SUBDATA);
1188 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1189 tx_queue = efx->tx_queue + ev_queue;
1190 tx_queue->flushed = true;
1192 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1193 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1194 ev_queue = EFX_QWORD_FIELD(
1195 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1196 ev_failed = EFX_QWORD_FIELD(
1197 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1198 if (ev_queue < efx->n_rx_queues) {
1199 rx_queue = efx->rx_queue + ev_queue;
1201 /* retry the rx flush */
1203 falcon_flush_rx_queue(rx_queue);
1205 rx_queue->flushed = true;
1209 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1210 } while (read_ptr != end_ptr);
1213 /* Handle tx and rx flushes at the same time, since they run in
1214 * parallel in the hardware and there's no reason for us to
1216 int falcon_flush_queues(struct efx_nic *efx)
1218 struct efx_rx_queue *rx_queue;
1219 struct efx_tx_queue *tx_queue;
1223 /* Issue flush requests */
1224 efx_for_each_tx_queue(tx_queue, efx) {
1225 tx_queue->flushed = false;
1226 falcon_flush_tx_queue(tx_queue);
1228 efx_for_each_rx_queue(rx_queue, efx) {
1229 rx_queue->flushed = false;
1230 falcon_flush_rx_queue(rx_queue);
1233 /* Poll the evq looking for flush completions. Since we're not pushing
1234 * any more rx or tx descriptors at this point, we're in no danger of
1235 * overflowing the evq whilst we wait */
1236 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1237 msleep(FALCON_FLUSH_INTERVAL);
1238 falcon_poll_flush_events(efx);
1240 /* Check if every queue has been succesfully flushed */
1241 outstanding = false;
1242 efx_for_each_tx_queue(tx_queue, efx)
1243 outstanding |= !tx_queue->flushed;
1244 efx_for_each_rx_queue(rx_queue, efx)
1245 outstanding |= !rx_queue->flushed;
1250 /* Mark the queues as all flushed. We're going to return failure
1251 * leading to a reset, or fake up success anyway. "flushed" now
1252 * indicates that we tried to flush. */
1253 efx_for_each_tx_queue(tx_queue, efx) {
1254 if (!tx_queue->flushed)
1255 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1257 tx_queue->flushed = true;
1259 efx_for_each_rx_queue(rx_queue, efx) {
1260 if (!rx_queue->flushed)
1261 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1263 rx_queue->flushed = true;
1266 if (EFX_WORKAROUND_7803(efx))
1272 /**************************************************************************
1274 * Falcon hardware interrupts
1275 * The hardware interrupt handler does very little work; all the event
1276 * queue processing is carried out by per-channel tasklets.
1278 **************************************************************************/
1280 /* Enable/disable/generate Falcon interrupts */
1281 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1284 efx_oword_t int_en_reg_ker;
1286 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1287 FRF_AZ_KER_INT_KER, force,
1288 FRF_AZ_DRV_INT_EN_KER, enabled);
1289 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1292 void falcon_enable_interrupts(struct efx_nic *efx)
1294 efx_oword_t int_adr_reg_ker;
1295 struct efx_channel *channel;
1297 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1298 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1300 /* Program address */
1301 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1302 FRF_AZ_NORM_INT_VEC_DIS_KER,
1303 EFX_INT_MODE_USE_MSI(efx),
1304 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1305 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1307 /* Enable interrupts */
1308 falcon_interrupts(efx, 1, 0);
1310 /* Force processing of all the channels to get the EVQ RPTRs up to
1312 efx_for_each_channel(channel, efx)
1313 efx_schedule_channel(channel);
1316 void falcon_disable_interrupts(struct efx_nic *efx)
1318 /* Disable interrupts */
1319 falcon_interrupts(efx, 0, 0);
1322 /* Generate a Falcon test interrupt
1323 * Interrupt must already have been enabled, otherwise nasty things
1326 void falcon_generate_interrupt(struct efx_nic *efx)
1328 falcon_interrupts(efx, 1, 1);
1331 /* Acknowledge a legacy interrupt from Falcon
1333 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1335 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1336 * BIU. Interrupt acknowledge is read sensitive so must write instead
1337 * (then read to ensure the BIU collector is flushed)
1339 * NB most hardware supports MSI interrupts
1341 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1345 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1346 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
1347 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1350 /* Process a fatal interrupt
1351 * Disable bus mastering ASAP and schedule a reset
1353 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1355 struct falcon_nic_data *nic_data = efx->nic_data;
1356 efx_oword_t *int_ker = efx->irq_status.addr;
1357 efx_oword_t fatal_intr;
1358 int error, mem_perr;
1360 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1361 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1363 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1364 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1365 EFX_OWORD_VAL(fatal_intr),
1366 error ? "disabling bus mastering" : "no recognised error");
1370 /* If this is a memory parity error dump which blocks are offending */
1371 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1374 efx_reado(efx, ®, FR_AZ_MEM_STAT);
1375 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1376 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1379 /* Disable both devices */
1380 pci_clear_master(efx->pci_dev);
1381 if (FALCON_IS_DUAL_FUNC(efx))
1382 pci_clear_master(nic_data->pci_dev2);
1383 falcon_disable_interrupts(efx);
1385 /* Count errors and reset or disable the NIC accordingly */
1386 if (efx->int_error_count == 0 ||
1387 time_after(jiffies, efx->int_error_expire)) {
1388 efx->int_error_count = 0;
1389 efx->int_error_expire =
1390 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1392 if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) {
1393 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1394 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1396 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1397 "NIC will be disabled\n");
1398 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1404 /* Handle a legacy interrupt from Falcon
1405 * Acknowledges the interrupt and schedule event queue processing.
1407 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1409 struct efx_nic *efx = dev_id;
1410 efx_oword_t *int_ker = efx->irq_status.addr;
1411 irqreturn_t result = IRQ_NONE;
1412 struct efx_channel *channel;
1417 /* Read the ISR which also ACKs the interrupts */
1418 efx_readd(efx, ®, FR_BZ_INT_ISR0);
1419 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1421 /* Check to see if we have a serious error condition */
1422 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1423 if (unlikely(syserr))
1424 return falcon_fatal_interrupt(efx);
1426 /* Schedule processing of any interrupting queues */
1427 efx_for_each_channel(channel, efx) {
1429 falcon_event_present(
1430 falcon_event(channel, channel->eventq_read_ptr))) {
1431 efx_schedule_channel(channel);
1432 result = IRQ_HANDLED;
1437 if (result == IRQ_HANDLED) {
1438 efx->last_irq_cpu = raw_smp_processor_id();
1439 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1440 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1447 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1449 struct efx_nic *efx = dev_id;
1450 efx_oword_t *int_ker = efx->irq_status.addr;
1451 struct efx_channel *channel;
1455 /* Check to see if this is our interrupt. If it isn't, we
1456 * exit without having touched the hardware.
1458 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1459 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1460 raw_smp_processor_id());
1463 efx->last_irq_cpu = raw_smp_processor_id();
1464 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1465 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1467 /* Check to see if we have a serious error condition */
1468 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1469 if (unlikely(syserr))
1470 return falcon_fatal_interrupt(efx);
1472 /* Determine interrupting queues, clear interrupt status
1473 * register and acknowledge the device interrupt.
1475 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1476 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1477 EFX_ZERO_OWORD(*int_ker);
1478 wmb(); /* Ensure the vector is cleared before interrupt ack */
1479 falcon_irq_ack_a1(efx);
1481 /* Schedule processing of any interrupting queues */
1482 channel = &efx->channel[0];
1485 efx_schedule_channel(channel);
1493 /* Handle an MSI interrupt from Falcon
1495 * Handle an MSI hardware interrupt. This routine schedules event
1496 * queue processing. No interrupt acknowledgement cycle is necessary.
1497 * Also, we never need to check that the interrupt is for us, since
1498 * MSI interrupts cannot be shared.
1500 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1502 struct efx_channel *channel = dev_id;
1503 struct efx_nic *efx = channel->efx;
1504 efx_oword_t *int_ker = efx->irq_status.addr;
1507 efx->last_irq_cpu = raw_smp_processor_id();
1508 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1509 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1511 /* Check to see if we have a serious error condition */
1512 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1513 if (unlikely(syserr))
1514 return falcon_fatal_interrupt(efx);
1516 /* Schedule processing of the channel */
1517 efx_schedule_channel(channel);
1523 /* Setup RSS indirection table.
1524 * This maps from the hash value of the packet to RXQ
1526 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1529 unsigned long offset;
1532 if (falcon_rev(efx) < FALCON_REV_B0)
1535 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1536 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1538 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1539 i % efx->n_rx_queues);
1540 efx_writed(efx, &dword, offset);
1545 /* Hook interrupt handler(s)
1546 * Try MSI and then legacy interrupts.
1548 int falcon_init_interrupt(struct efx_nic *efx)
1550 struct efx_channel *channel;
1553 if (!EFX_INT_MODE_USE_MSI(efx)) {
1554 irq_handler_t handler;
1555 if (falcon_rev(efx) >= FALCON_REV_B0)
1556 handler = falcon_legacy_interrupt_b0;
1558 handler = falcon_legacy_interrupt_a1;
1560 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1563 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1570 /* Hook MSI or MSI-X interrupt */
1571 efx_for_each_channel(channel, efx) {
1572 rc = request_irq(channel->irq, falcon_msi_interrupt,
1573 IRQF_PROBE_SHARED, /* Not shared */
1574 channel->name, channel);
1576 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1584 efx_for_each_channel(channel, efx)
1585 free_irq(channel->irq, channel);
1590 void falcon_fini_interrupt(struct efx_nic *efx)
1592 struct efx_channel *channel;
1595 /* Disable MSI/MSI-X interrupts */
1596 efx_for_each_channel(channel, efx) {
1598 free_irq(channel->irq, channel);
1601 /* ACK legacy interrupt */
1602 if (falcon_rev(efx) >= FALCON_REV_B0)
1603 efx_reado(efx, ®, FR_BZ_INT_ISR0);
1605 falcon_irq_ack_a1(efx);
1607 /* Disable legacy interrupt */
1608 if (efx->legacy_irq)
1609 free_irq(efx->legacy_irq, efx);
1612 /**************************************************************************
1616 **************************************************************************
1619 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1621 static int falcon_spi_poll(struct efx_nic *efx)
1624 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
1625 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1628 /* Wait for SPI command completion */
1629 static int falcon_spi_wait(struct efx_nic *efx)
1631 /* Most commands will finish quickly, so we start polling at
1632 * very short intervals. Sometimes the command may have to
1633 * wait for VPD or expansion ROM access outside of our
1634 * control, so we allow up to 100 ms. */
1635 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1638 for (i = 0; i < 10; i++) {
1639 if (!falcon_spi_poll(efx))
1645 if (!falcon_spi_poll(efx))
1647 if (time_after_eq(jiffies, timeout)) {
1648 EFX_ERR(efx, "timed out waiting for SPI\n");
1651 schedule_timeout_uninterruptible(1);
1655 int falcon_spi_cmd(const struct efx_spi_device *spi,
1656 unsigned int command, int address,
1657 const void *in, void *out, size_t len)
1659 struct efx_nic *efx = spi->efx;
1660 bool addressed = (address >= 0);
1661 bool reading = (out != NULL);
1665 /* Input validation */
1666 if (len > FALCON_SPI_MAX_LEN)
1668 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1670 /* Check that previous command is not still running */
1671 rc = falcon_spi_poll(efx);
1675 /* Program address register, if we have an address */
1677 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1678 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
1681 /* Program data register, if we have data */
1683 memcpy(®, in, len);
1684 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
1687 /* Issue read/write command */
1688 EFX_POPULATE_OWORD_7(reg,
1689 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1690 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1691 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1692 FRF_AB_EE_SPI_HCMD_READ, reading,
1693 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1694 FRF_AB_EE_SPI_HCMD_ADBCNT,
1695 (addressed ? spi->addr_len : 0),
1696 FRF_AB_EE_SPI_HCMD_ENC, command);
1697 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
1699 /* Wait for read/write to complete */
1700 rc = falcon_spi_wait(efx);
1706 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
1707 memcpy(out, ®, len);
1714 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1716 return min(FALCON_SPI_MAX_LEN,
1717 (spi->block_size - (start & (spi->block_size - 1))));
1721 efx_spi_munge_command(const struct efx_spi_device *spi,
1722 const u8 command, const unsigned int address)
1724 return command | (((address >> 8) & spi->munge_address) << 3);
1727 /* Wait up to 10 ms for buffered write completion */
1728 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1730 struct efx_nic *efx = spi->efx;
1731 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1736 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1737 &status, sizeof(status));
1740 if (!(status & SPI_STATUS_NRDY))
1742 if (time_after_eq(jiffies, timeout)) {
1743 EFX_ERR(efx, "SPI write timeout on device %d"
1744 " last status=0x%02x\n",
1745 spi->device_id, status);
1748 schedule_timeout_uninterruptible(1);
1752 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1753 size_t len, size_t *retlen, u8 *buffer)
1755 size_t block_len, pos = 0;
1756 unsigned int command;
1760 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1762 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1763 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1764 buffer + pos, block_len);
1769 /* Avoid locking up the system */
1771 if (signal_pending(current)) {
1782 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1783 size_t len, size_t *retlen, const u8 *buffer)
1785 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1786 size_t block_len, pos = 0;
1787 unsigned int command;
1791 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1795 block_len = min(len - pos,
1796 falcon_spi_write_limit(spi, start + pos));
1797 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1798 rc = falcon_spi_cmd(spi, command, start + pos,
1799 buffer + pos, NULL, block_len);
1803 rc = falcon_spi_wait_write(spi);
1807 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1808 rc = falcon_spi_cmd(spi, command, start + pos,
1809 NULL, verify_buffer, block_len);
1810 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1817 /* Avoid locking up the system */
1819 if (signal_pending(current)) {
1830 /**************************************************************************
1834 **************************************************************************
1837 static int falcon_reset_macs(struct efx_nic *efx)
1842 if (falcon_rev(efx) < FALCON_REV_B0) {
1843 /* It's not safe to use GLB_CTL_REG to reset the
1844 * macs, so instead use the internal MAC resets
1846 if (!EFX_IS10G(efx)) {
1847 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1848 efx_writeo(efx, ®, FR_AB_GM_CFG1);
1851 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1852 efx_writeo(efx, ®, FR_AB_GM_CFG1);
1856 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1857 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1859 for (count = 0; count < 10000; count++) {
1860 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
1861 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1867 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1872 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1873 * the drain sequence with the statistics fetch */
1874 efx_stats_disable(efx);
1876 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1877 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1878 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
1880 efx_reado(efx, ®, FR_AB_GLB_CTL);
1881 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1882 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1883 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1884 efx_writeo(efx, ®, FR_AB_GLB_CTL);
1888 efx_reado(efx, ®, FR_AB_GLB_CTL);
1889 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1890 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1891 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1892 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1897 EFX_ERR(efx, "MAC reset failed\n");
1904 efx_stats_enable(efx);
1906 /* If we've reset the EM block and the link is up, then
1907 * we'll have to kick the XAUI link so the PHY can recover */
1908 if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1909 falcon_reset_xaui(efx);
1914 void falcon_drain_tx_fifo(struct efx_nic *efx)
1918 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1919 (efx->loopback_mode != LOOPBACK_NONE))
1922 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1923 /* There is no point in draining more than once */
1924 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1927 falcon_reset_macs(efx);
1930 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1934 if (falcon_rev(efx) < FALCON_REV_B0)
1937 /* Isolate the MAC -> RX */
1938 efx_reado(efx, ®, FR_AZ_RX_CFG);
1939 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1940 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1942 if (!efx->link_state.up)
1943 falcon_drain_tx_fifo(efx);
1946 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1948 struct efx_link_state *link_state = &efx->link_state;
1953 switch (link_state->speed) {
1954 case 10000: link_speed = 3; break;
1955 case 1000: link_speed = 2; break;
1956 case 100: link_speed = 1; break;
1957 default: link_speed = 0; break;
1959 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1960 * as advertised. Disable to ensure packets are not
1961 * indefinitely held and TX queue can be flushed at any point
1962 * while the link is down. */
1963 EFX_POPULATE_OWORD_5(reg,
1964 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1965 FRF_AB_MAC_BCAD_ACPT, 1,
1966 FRF_AB_MAC_UC_PROM, efx->promiscuous,
1967 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
1968 FRF_AB_MAC_SPEED, link_speed);
1969 /* On B0, MAC backpressure can be disabled and packets get
1971 if (falcon_rev(efx) >= FALCON_REV_B0) {
1972 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
1976 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
1978 /* Restore the multicast hash registers. */
1979 falcon_set_multicast_hash(efx);
1981 /* Transmission of pause frames when RX crosses the threshold is
1982 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1983 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1984 tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
1985 efx_reado(efx, ®, FR_AZ_RX_CFG);
1986 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
1988 /* Unisolate the MAC -> RX */
1989 if (falcon_rev(efx) >= FALCON_REV_B0)
1990 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1991 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1994 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2000 if (disable_dma_stats)
2003 /* Statistics fetch will fail if the MAC is in TX drain */
2004 if (falcon_rev(efx) >= FALCON_REV_B0) {
2006 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2007 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2011 dma_done = (efx->stats_buffer.addr + done_offset);
2012 *dma_done = FALCON_STATS_NOT_DONE;
2013 wmb(); /* ensure done flag is clear */
2015 /* Initiate DMA transfer of stats */
2016 EFX_POPULATE_OWORD_2(reg,
2017 FRF_AB_MAC_STAT_DMA_CMD, 1,
2018 FRF_AB_MAC_STAT_DMA_ADR,
2019 efx->stats_buffer.dma_addr);
2020 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
2022 /* Wait for transfer to complete */
2023 for (i = 0; i < 400; i++) {
2024 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2025 rmb(); /* Ensure the stats are valid. */
2031 EFX_ERR(efx, "timed out waiting for statistics\n");
2035 /**************************************************************************
2037 * PHY access via GMII
2039 **************************************************************************
2042 /* Wait for GMII access to complete */
2043 static int falcon_gmii_wait(struct efx_nic *efx)
2045 efx_dword_t md_stat;
2048 /* wait upto 50ms - taken max from datasheet */
2049 for (count = 0; count < 5000; count++) {
2050 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2051 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2052 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2053 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2054 EFX_ERR(efx, "error from GMII access "
2056 EFX_DWORD_VAL(md_stat));
2063 EFX_ERR(efx, "timed out waiting for GMII\n");
2067 /* Write an MDIO register of a PHY connected to Falcon. */
2068 static int falcon_mdio_write(struct net_device *net_dev,
2069 int prtad, int devad, u16 addr, u16 value)
2071 struct efx_nic *efx = netdev_priv(net_dev);
2075 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2076 prtad, devad, addr, value);
2078 spin_lock_bh(&efx->phy_lock);
2080 /* Check MDIO not currently being accessed */
2081 rc = falcon_gmii_wait(efx);
2085 /* Write the address/ID register */
2086 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2087 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
2089 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2090 FRF_AB_MD_DEV_ADR, devad);
2091 efx_writeo(efx, ®, FR_AB_MD_ID);
2094 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2095 efx_writeo(efx, ®, FR_AB_MD_TXD);
2097 EFX_POPULATE_OWORD_2(reg,
2100 efx_writeo(efx, ®, FR_AB_MD_CS);
2102 /* Wait for data to be written */
2103 rc = falcon_gmii_wait(efx);
2105 /* Abort the write operation */
2106 EFX_POPULATE_OWORD_2(reg,
2109 efx_writeo(efx, ®, FR_AB_MD_CS);
2114 spin_unlock_bh(&efx->phy_lock);
2118 /* Read an MDIO register of a PHY connected to Falcon. */
2119 static int falcon_mdio_read(struct net_device *net_dev,
2120 int prtad, int devad, u16 addr)
2122 struct efx_nic *efx = netdev_priv(net_dev);
2126 spin_lock_bh(&efx->phy_lock);
2128 /* Check MDIO not currently being accessed */
2129 rc = falcon_gmii_wait(efx);
2133 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2134 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
2136 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2137 FRF_AB_MD_DEV_ADR, devad);
2138 efx_writeo(efx, ®, FR_AB_MD_ID);
2140 /* Request data to be read */
2141 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2142 efx_writeo(efx, ®, FR_AB_MD_CS);
2144 /* Wait for data to become available */
2145 rc = falcon_gmii_wait(efx);
2147 efx_reado(efx, ®, FR_AB_MD_RXD);
2148 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2149 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2150 prtad, devad, addr, rc);
2152 /* Abort the read operation */
2153 EFX_POPULATE_OWORD_2(reg,
2156 efx_writeo(efx, ®, FR_AB_MD_CS);
2158 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2159 prtad, devad, addr, rc);
2163 spin_unlock_bh(&efx->phy_lock);
2167 int falcon_switch_mac(struct efx_nic *efx)
2169 struct efx_mac_operations *old_mac_op = efx->mac_op;
2170 efx_oword_t nic_stat;
2174 /* Don't try to fetch MAC stats while we're switching MACs */
2175 efx_stats_disable(efx);
2177 /* Internal loopbacks override the phy speed setting */
2178 if (efx->loopback_mode == LOOPBACK_GMAC) {
2179 efx->link_state.speed = 1000;
2180 efx->link_state.fd = true;
2181 } else if (LOOPBACK_INTERNAL(efx)) {
2182 efx->link_state.speed = 10000;
2183 efx->link_state.fd = true;
2186 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2187 efx->mac_op = (EFX_IS10G(efx) ?
2188 &falcon_xmac_operations : &falcon_gmac_operations);
2190 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2191 * changed, because this function is run post online reset */
2192 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2193 strap_val = EFX_IS10G(efx) ? 5 : 3;
2194 if (falcon_rev(efx) >= FALCON_REV_B0) {
2195 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2196 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2197 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2199 /* Falcon A1 does not support 1G/10G speed switching
2200 * and must not be used with a PHY that does. */
2201 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2205 if (old_mac_op == efx->mac_op)
2208 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2209 /* Not all macs support a mac-level link state */
2212 rc = falcon_reset_macs(efx);
2214 efx_stats_enable(efx);
2218 /* This call is responsible for hooking in the MAC and PHY operations */
2219 int falcon_probe_port(struct efx_nic *efx)
2223 switch (efx->phy_type) {
2224 case PHY_TYPE_SFX7101:
2225 efx->phy_op = &falcon_sfx7101_phy_ops;
2227 case PHY_TYPE_SFT9001A:
2228 case PHY_TYPE_SFT9001B:
2229 efx->phy_op = &falcon_sft9001_phy_ops;
2231 case PHY_TYPE_QT2022C2:
2232 case PHY_TYPE_QT2025C:
2233 efx->phy_op = &falcon_qt202x_phy_ops;
2236 EFX_ERR(efx, "Unknown PHY type %d\n",
2241 if (efx->phy_op->macs & EFX_XMAC)
2242 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2243 (1 << LOOPBACK_XGXS) |
2244 (1 << LOOPBACK_XAUI));
2245 if (efx->phy_op->macs & EFX_GMAC)
2246 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2247 efx->loopback_modes |= efx->phy_op->loopbacks;
2249 /* Set up MDIO structure for PHY */
2250 efx->mdio.mmds = efx->phy_op->mmds;
2251 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2252 efx->mdio.mdio_read = falcon_mdio_read;
2253 efx->mdio.mdio_write = falcon_mdio_write;
2255 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2256 if (falcon_rev(efx) >= FALCON_REV_B0)
2257 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2259 efx->wanted_fc = EFX_FC_RX;
2261 /* Allocate buffer for stats */
2262 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2263 FALCON_MAC_STATS_SIZE);
2266 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2267 (u64)efx->stats_buffer.dma_addr,
2268 efx->stats_buffer.addr,
2269 (u64)virt_to_phys(efx->stats_buffer.addr));
2274 void falcon_remove_port(struct efx_nic *efx)
2276 falcon_free_buffer(efx, &efx->stats_buffer);
2279 /**************************************************************************
2281 * Multicast filtering
2283 **************************************************************************
2286 void falcon_set_multicast_hash(struct efx_nic *efx)
2288 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2290 /* Broadcast packets go through the multicast hash filter.
2291 * ether_crc_le() of the broadcast address is 0xbe2612ff
2292 * so we always add bit 0xff to the mask.
2294 set_bit_le(0xff, mc_hash->byte);
2296 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2297 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2301 /**************************************************************************
2305 **************************************************************************/
2307 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2309 struct falcon_nvconfig *nvconfig;
2310 struct efx_spi_device *spi;
2312 int rc, magic_num, struct_ver;
2313 __le16 *word, *limit;
2316 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2320 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2323 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2325 mutex_lock(&efx->spi_lock);
2326 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2327 mutex_unlock(&efx->spi_lock);
2329 EFX_ERR(efx, "Failed to read %s\n",
2330 efx->spi_flash ? "flash" : "EEPROM");
2335 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2336 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2339 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2340 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2343 if (struct_ver < 2) {
2344 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2346 } else if (struct_ver < 4) {
2347 word = &nvconfig->board_magic_num;
2348 limit = (__le16 *) (nvconfig + 1);
2351 limit = region + FALCON_NVCONFIG_END;
2353 for (csum = 0; word < limit; ++word)
2354 csum += le16_to_cpu(*word);
2356 if (~csum & 0xffff) {
2357 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2363 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2370 /* Registers tested in the falcon register test */
2374 } efx_test_registers[] = {
2376 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2378 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2380 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2381 { FR_AZ_TX_RESERVED,
2382 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2384 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2385 { FR_AZ_SRM_TX_DC_CFG,
2386 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2388 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2389 { FR_AZ_RX_DC_PF_WM,
2390 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2392 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2394 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2396 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2398 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2400 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2402 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2403 { FR_AB_XM_RX_PARAM,
2404 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2406 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2408 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2410 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2413 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2414 const efx_oword_t *mask)
2416 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2417 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2420 int falcon_test_registers(struct efx_nic *efx)
2422 unsigned address = 0, i, j;
2423 efx_oword_t mask, imask, original, reg, buf;
2425 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2426 WARN_ON(!LOOPBACK_INTERNAL(efx));
2428 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2429 address = efx_test_registers[i].address;
2430 mask = imask = efx_test_registers[i].mask;
2431 EFX_INVERT_OWORD(imask);
2433 efx_reado(efx, &original, address);
2435 /* bit sweep on and off */
2436 for (j = 0; j < 128; j++) {
2437 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2440 /* Test this testable bit can be set in isolation */
2441 EFX_AND_OWORD(reg, original, mask);
2442 EFX_SET_OWORD32(reg, j, j, 1);
2444 efx_writeo(efx, ®, address);
2445 efx_reado(efx, &buf, address);
2447 if (efx_masked_compare_oword(®, &buf, &mask))
2450 /* Test this testable bit can be cleared in isolation */
2451 EFX_OR_OWORD(reg, original, mask);
2452 EFX_SET_OWORD32(reg, j, j, 0);
2454 efx_writeo(efx, ®, address);
2455 efx_reado(efx, &buf, address);
2457 if (efx_masked_compare_oword(®, &buf, &mask))
2461 efx_writeo(efx, &original, address);
2467 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2468 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2469 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2473 /**************************************************************************
2477 **************************************************************************
2480 /* Resets NIC to known state. This routine must be called in process
2481 * context and is allowed to sleep. */
2482 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2484 struct falcon_nic_data *nic_data = efx->nic_data;
2485 efx_oword_t glb_ctl_reg_ker;
2488 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2490 /* Initiate device reset */
2491 if (method == RESET_TYPE_WORLD) {
2492 rc = pci_save_state(efx->pci_dev);
2494 EFX_ERR(efx, "failed to backup PCI state of primary "
2495 "function prior to hardware reset\n");
2498 if (FALCON_IS_DUAL_FUNC(efx)) {
2499 rc = pci_save_state(nic_data->pci_dev2);
2501 EFX_ERR(efx, "failed to backup PCI state of "
2502 "secondary function prior to "
2503 "hardware reset\n");
2508 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2509 FRF_AB_EXT_PHY_RST_DUR,
2510 FFE_AB_EXT_PHY_RST_DUR_10240US,
2513 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2514 /* exclude PHY from "invisible" reset */
2515 FRF_AB_EXT_PHY_RST_CTL,
2516 method == RESET_TYPE_INVISIBLE,
2517 /* exclude EEPROM/flash and PCIe */
2518 FRF_AB_PCIE_CORE_RST_CTL, 1,
2519 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2520 FRF_AB_PCIE_SD_RST_CTL, 1,
2521 FRF_AB_EE_RST_CTL, 1,
2522 FRF_AB_EXT_PHY_RST_DUR,
2523 FFE_AB_EXT_PHY_RST_DUR_10240US,
2526 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2528 EFX_LOG(efx, "waiting for hardware reset\n");
2529 schedule_timeout_uninterruptible(HZ / 20);
2531 /* Restore PCI configuration if needed */
2532 if (method == RESET_TYPE_WORLD) {
2533 if (FALCON_IS_DUAL_FUNC(efx)) {
2534 rc = pci_restore_state(nic_data->pci_dev2);
2536 EFX_ERR(efx, "failed to restore PCI config for "
2537 "the secondary function\n");
2541 rc = pci_restore_state(efx->pci_dev);
2543 EFX_ERR(efx, "failed to restore PCI config for the "
2544 "primary function\n");
2547 EFX_LOG(efx, "successfully restored PCI config\n");
2550 /* Assert that reset complete */
2551 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2552 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2554 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2557 EFX_LOG(efx, "hardware reset complete\n");
2561 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2564 pci_restore_state(efx->pci_dev);
2571 /* Zeroes out the SRAM contents. This routine must be called in
2572 * process context and is allowed to sleep.
2574 static int falcon_reset_sram(struct efx_nic *efx)
2576 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2579 /* Set the SRAM wake/sleep GPIO appropriately. */
2580 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2581 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2582 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2583 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2585 /* Initiate SRAM reset */
2586 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2587 FRF_AZ_SRM_INIT_EN, 1,
2588 FRF_AZ_SRM_NB_SZ, 0);
2589 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2591 /* Wait for SRAM reset to complete */
2594 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2596 /* SRAM reset is slow; expect around 16ms */
2597 schedule_timeout_uninterruptible(HZ / 50);
2599 /* Check for reset complete */
2600 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2601 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2602 EFX_LOG(efx, "SRAM reset complete\n");
2606 } while (++count < 20); /* wait upto 0.4 sec */
2608 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2612 static int falcon_spi_device_init(struct efx_nic *efx,
2613 struct efx_spi_device **spi_device_ret,
2614 unsigned int device_id, u32 device_type)
2616 struct efx_spi_device *spi_device;
2618 if (device_type != 0) {
2619 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2622 spi_device->device_id = device_id;
2624 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2625 spi_device->addr_len =
2626 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2627 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2628 spi_device->addr_len == 1);
2629 spi_device->erase_command =
2630 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2631 spi_device->erase_size =
2632 1 << SPI_DEV_TYPE_FIELD(device_type,
2633 SPI_DEV_TYPE_ERASE_SIZE);
2634 spi_device->block_size =
2635 1 << SPI_DEV_TYPE_FIELD(device_type,
2636 SPI_DEV_TYPE_BLOCK_SIZE);
2638 spi_device->efx = efx;
2643 kfree(*spi_device_ret);
2644 *spi_device_ret = spi_device;
2649 static void falcon_remove_spi_devices(struct efx_nic *efx)
2651 kfree(efx->spi_eeprom);
2652 efx->spi_eeprom = NULL;
2653 kfree(efx->spi_flash);
2654 efx->spi_flash = NULL;
2657 /* Extract non-volatile configuration */
2658 static int falcon_probe_nvconfig(struct efx_nic *efx)
2660 struct falcon_nvconfig *nvconfig;
2664 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2668 rc = falcon_read_nvram(efx, nvconfig);
2669 if (rc == -EINVAL) {
2670 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2671 efx->phy_type = PHY_TYPE_NONE;
2672 efx->mdio.prtad = MDIO_PRTAD_NONE;
2678 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2679 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2681 efx->phy_type = v2->port0_phy_type;
2682 efx->mdio.prtad = v2->port0_phy_addr;
2683 board_rev = le16_to_cpu(v2->board_revision);
2685 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2686 rc = falcon_spi_device_init(
2687 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2688 le32_to_cpu(v3->spi_device_type
2689 [FFE_AB_SPI_DEVICE_FLASH]));
2692 rc = falcon_spi_device_init(
2693 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2694 le32_to_cpu(v3->spi_device_type
2695 [FFE_AB_SPI_DEVICE_EEPROM]));
2701 /* Read the MAC addresses */
2702 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2704 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2706 falcon_probe_board(efx, board_rev);
2712 falcon_remove_spi_devices(efx);
2718 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2719 * count, port speed). Set workaround and feature flags accordingly.
2721 static int falcon_probe_nic_variant(struct efx_nic *efx)
2723 efx_oword_t altera_build;
2724 efx_oword_t nic_stat;
2726 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2727 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2728 EFX_ERR(efx, "Falcon FPGA not supported\n");
2732 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2734 switch (falcon_rev(efx)) {
2737 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2741 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2742 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2751 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2755 /* Initial assumed speed */
2756 efx->link_state.speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2761 /* Probe all SPI devices on the NIC */
2762 static void falcon_probe_spi_devices(struct efx_nic *efx)
2764 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2767 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2768 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2769 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2771 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2772 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2773 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2774 EFX_LOG(efx, "Booted from %s\n",
2775 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2777 /* Disable VPD and set clock dividers to safe
2778 * values for initial programming. */
2780 EFX_LOG(efx, "Booted from internal ASIC settings;"
2781 " setting SPI config\n");
2782 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2783 /* 125 MHz / 7 ~= 20 MHz */
2784 FRF_AB_EE_SF_CLOCK_DIV, 7,
2785 /* 125 MHz / 63 ~= 2 MHz */
2786 FRF_AB_EE_EE_CLOCK_DIV, 63);
2787 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2790 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2791 falcon_spi_device_init(efx, &efx->spi_flash,
2792 FFE_AB_SPI_DEVICE_FLASH,
2793 default_flash_type);
2794 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2795 falcon_spi_device_init(efx, &efx->spi_eeprom,
2796 FFE_AB_SPI_DEVICE_EEPROM,
2800 int falcon_probe_nic(struct efx_nic *efx)
2802 struct falcon_nic_data *nic_data;
2803 struct falcon_board *board;
2806 /* Allocate storage for hardware specific data */
2807 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2810 efx->nic_data = nic_data;
2812 /* Determine number of ports etc. */
2813 rc = falcon_probe_nic_variant(efx);
2817 /* Probe secondary function if expected */
2818 if (FALCON_IS_DUAL_FUNC(efx)) {
2819 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2821 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2823 if (dev->bus == efx->pci_dev->bus &&
2824 dev->devfn == efx->pci_dev->devfn + 1) {
2825 nic_data->pci_dev2 = dev;
2829 if (!nic_data->pci_dev2) {
2830 EFX_ERR(efx, "failed to find secondary function\n");
2836 /* Now we can reset the NIC */
2837 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2839 EFX_ERR(efx, "failed to reset NIC\n");
2843 /* Allocate memory for INT_KER */
2844 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2847 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2849 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2850 (u64)efx->irq_status.dma_addr,
2851 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2853 falcon_probe_spi_devices(efx);
2855 /* Read in the non-volatile configuration */
2856 rc = falcon_probe_nvconfig(efx);
2860 /* Initialise I2C adapter */
2861 board = falcon_board(efx);
2862 board->i2c_adap.owner = THIS_MODULE;
2863 board->i2c_data = falcon_i2c_bit_operations;
2864 board->i2c_data.data = efx;
2865 board->i2c_adap.algo_data = &board->i2c_data;
2866 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
2867 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
2868 sizeof(board->i2c_adap.name));
2869 rc = i2c_bit_add_bus(&board->i2c_adap);
2873 rc = falcon_board(efx)->init(efx);
2875 EFX_ERR(efx, "failed to initialise board\n");
2882 BUG_ON(i2c_del_adapter(&board->i2c_adap));
2883 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
2885 falcon_remove_spi_devices(efx);
2886 falcon_free_buffer(efx, &efx->irq_status);
2889 if (nic_data->pci_dev2) {
2890 pci_dev_put(nic_data->pci_dev2);
2891 nic_data->pci_dev2 = NULL;
2895 kfree(efx->nic_data);
2899 static void falcon_init_rx_cfg(struct efx_nic *efx)
2901 /* Prior to Siena the RX DMA engine will split each frame at
2902 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2903 * be so large that that never happens. */
2904 const unsigned huge_buf_size = (3 * 4096) >> 5;
2905 /* RX control FIFO thresholds (32 entries) */
2906 const unsigned ctrl_xon_thr = 20;
2907 const unsigned ctrl_xoff_thr = 25;
2908 /* RX data FIFO thresholds (256-byte units; size varies) */
2909 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2910 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2913 efx_reado(efx, ®, FR_AZ_RX_CFG);
2914 if (falcon_rev(efx) <= FALCON_REV_A1) {
2915 /* Data FIFO size is 5.5K */
2916 if (data_xon_thr < 0)
2917 data_xon_thr = 512 >> 8;
2918 if (data_xoff_thr < 0)
2919 data_xoff_thr = 2048 >> 8;
2920 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2921 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2923 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2924 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2925 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2926 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2928 /* Data FIFO size is 80K; register fields moved */
2929 if (data_xon_thr < 0)
2930 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2931 if (data_xoff_thr < 0)
2932 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2933 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2934 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2936 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2937 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2938 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2939 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2940 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2942 efx_writeo(efx, ®, FR_AZ_RX_CFG);
2945 /* This call performs hardware-specific global initialisation, such as
2946 * defining the descriptor cache sizes and number of RSS channels.
2947 * It does not set up any buffers, descriptor rings or event queues.
2949 int falcon_init_nic(struct efx_nic *efx)
2954 /* Use on-chip SRAM */
2955 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2956 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2957 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2959 /* Set the source of the GMAC clock */
2960 if (falcon_rev(efx) == FALCON_REV_B0) {
2961 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2962 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2963 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2966 rc = falcon_reset_sram(efx);
2970 /* Set positions of descriptor caches in SRAM. */
2971 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2972 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
2973 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2974 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
2976 /* Set TX descriptor cache size. */
2977 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2978 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2979 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
2981 /* Set RX descriptor cache size. Set low watermark to size-8, as
2982 * this allows most efficient prefetching.
2984 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2985 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2986 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
2987 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2988 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
2990 /* Clear the parity enables on the TX data fifos as
2991 * they produce false parity errors because of timing issues
2993 if (EFX_WORKAROUND_5129(efx)) {
2994 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
2995 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
2996 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
2999 /* Enable all the genuinely fatal interrupts. (They are still
3000 * masked by the overall interrupt mask, controlled by
3001 * falcon_interrupts()).
3003 * Note: All other fatal interrupts are enabled
3005 EFX_POPULATE_OWORD_3(temp,
3006 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3007 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3008 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3009 EFX_INVERT_OWORD(temp);
3010 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3012 if (EFX_WORKAROUND_7244(efx)) {
3013 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3014 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3015 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3016 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3017 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3018 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3021 falcon_setup_rss_indir_table(efx);
3023 /* XXX This is documented only for Falcon A0/A1 */
3024 /* Setup RX. Wait for descriptor is broken and must
3025 * be disabled. RXDP recovery shouldn't be needed, but is.
3027 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3028 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3029 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3030 if (EFX_WORKAROUND_5583(efx))
3031 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3032 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3034 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3035 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3037 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3038 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3039 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3040 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3041 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3042 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3043 /* Enable SW_EV to inherit in char driver - assume harmless here */
3044 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3045 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3046 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3047 /* Squash TX of packets of 16 bytes or less */
3048 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3049 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3050 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3052 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3053 * descriptors (which is bad).
3055 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3056 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3057 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3059 falcon_init_rx_cfg(efx);
3061 /* Set destination of both TX and RX Flush events */
3062 if (falcon_rev(efx) >= FALCON_REV_B0) {
3063 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3064 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3070 void falcon_remove_nic(struct efx_nic *efx)
3072 struct falcon_nic_data *nic_data = efx->nic_data;
3073 struct falcon_board *board = falcon_board(efx);
3076 falcon_board(efx)->fini(efx);
3078 /* Remove I2C adapter and clear it in preparation for a retry */
3079 rc = i2c_del_adapter(&board->i2c_adap);
3081 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
3083 falcon_remove_spi_devices(efx);
3084 falcon_free_buffer(efx, &efx->irq_status);
3086 falcon_reset_hw(efx, RESET_TYPE_ALL);
3088 /* Release the second function after the reset */
3089 if (nic_data->pci_dev2) {
3090 pci_dev_put(nic_data->pci_dev2);
3091 nic_data->pci_dev2 = NULL;
3094 /* Tear down the private nic state */
3095 kfree(efx->nic_data);
3096 efx->nic_data = NULL;
3099 void falcon_update_nic_stats(struct efx_nic *efx)
3103 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3104 efx->n_rx_nodesc_drop_cnt +=
3105 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3108 /**************************************************************************
3110 * Revision-dependent attributes used by efx.c
3112 **************************************************************************
3115 struct efx_nic_type falcon_a_nic_type = {
3116 .mem_map_size = 0x20000,
3117 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3118 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3119 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3120 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3121 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3122 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3123 .rx_buffer_padding = 0x24,
3124 .max_interrupt_mode = EFX_INT_MODE_MSI,
3125 .phys_addr_channels = 4,
3128 struct efx_nic_type falcon_b_nic_type = {
3129 /* Map everything up to and including the RSS indirection
3130 * table. Don't map MSI-X table, MSI-X PBA since Linux
3131 * requires that they not be mapped. */
3132 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3133 FR_BZ_RX_INDIRECTION_TBL_STEP *
3134 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3135 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3136 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3137 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3138 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3139 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3140 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
3141 .rx_buffer_padding = 0,
3142 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3143 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3144 * interrupt handler only supports 32