1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
29 #include "workarounds.h"
31 /* Falcon hardware control.
32 * Falcon is the internal codename for the SFC4000 controller that is
33 * present in SFE400X evaluation boards
37 * struct falcon_nic_data - Falcon NIC state
38 * @next_buffer_table: First available buffer table id
39 * @pci_dev2: The secondary PCI device if present
40 * @i2c_data: Operations and state for I2C bit-bashing algorithm
41 * @int_error_count: Number of internal errors seen recently
42 * @int_error_expire: Time at which error count will be expired
44 struct falcon_nic_data {
45 unsigned next_buffer_table;
46 struct pci_dev *pci_dev2;
47 struct i2c_algo_bit_data i2c_data;
49 unsigned int_error_count;
50 unsigned long int_error_expire;
53 /**************************************************************************
57 **************************************************************************
60 static int disable_dma_stats;
62 /* This is set to 16 for a good reason. In summary, if larger than
63 * 16, the descriptor cache holds more than a default socket
64 * buffer's worth of packets (for UDP we can only have at most one
65 * socket buffer's worth outstanding). This combined with the fact
66 * that we only get 1 TX event per descriptor cache means the NIC
69 #define TX_DC_ENTRIES 16
70 #define TX_DC_ENTRIES_ORDER 0
71 #define TX_DC_BASE 0x130000
73 #define RX_DC_ENTRIES 64
74 #define RX_DC_ENTRIES_ORDER 2
75 #define RX_DC_BASE 0x100000
77 static const unsigned int
78 /* "Large" EEPROM device: Atmel AT25640 or similar
79 * 8 KB, 16-bit address, 32 B write block */
80 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
81 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
82 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
83 /* Default flash device: Atmel AT25F1024
84 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
85 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
86 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
87 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
88 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
89 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
91 /* RX FIFO XOFF watermark
93 * When the amount of the RX FIFO increases used increases past this
94 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
95 * This also has an effect on RX/TX arbitration
97 static int rx_xoff_thresh_bytes = -1;
98 module_param(rx_xoff_thresh_bytes, int, 0644);
99 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
101 /* RX FIFO XON watermark
103 * When the amount of the RX FIFO used decreases below this
104 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
105 * This also has an effect on RX/TX arbitration
107 static int rx_xon_thresh_bytes = -1;
108 module_param(rx_xon_thresh_bytes, int, 0644);
109 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
111 /* If FALCON_MAX_INT_ERRORS internal errors occur within
112 * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
115 #define FALCON_INT_ERROR_EXPIRE 3600
116 #define FALCON_MAX_INT_ERRORS 5
118 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
120 #define FALCON_FLUSH_INTERVAL 10
121 #define FALCON_FLUSH_POLL_COUNT 100
123 /**************************************************************************
127 **************************************************************************
130 /* DMA address mask */
131 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
133 /* TX DMA length mask (13-bit) */
134 #define FALCON_TX_DMA_MASK (4096 - 1)
136 /* Size and alignment of special buffers (4KB) */
137 #define FALCON_BUF_SIZE 4096
139 /* Dummy SRAM size code */
140 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
142 #define FALCON_IS_DUAL_FUNC(efx) \
143 (falcon_rev(efx) < FALCON_REV_B0)
145 /**************************************************************************
147 * Falcon hardware access
149 **************************************************************************/
151 static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
154 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
158 /* Read the current event from the event queue */
159 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
162 return (((efx_qword_t *) (channel->eventq.addr)) + index);
165 /* See if an event is present
167 * We check both the high and low dword of the event for all ones. We
168 * wrote all ones when we cleared the event, and no valid event can
169 * have all ones in either its high or low dwords. This approach is
170 * robust against reordering.
172 * Note that using a single 64-bit comparison is incorrect; even
173 * though the CPU read will be atomic, the DMA write may not be.
175 static inline int falcon_event_present(efx_qword_t *event)
177 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
178 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
181 /**************************************************************************
183 * I2C bus - this is a bit-bashing interface using GPIO pins
184 * Note that it uses the output enables to tristate the outputs
185 * SDA is the data pin and SCL is the clock
187 **************************************************************************
189 static void falcon_setsda(void *data, int state)
191 struct efx_nic *efx = (struct efx_nic *)data;
194 efx_reado(efx, ®, FR_AB_GPIO_CTL);
195 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
196 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
199 static void falcon_setscl(void *data, int state)
201 struct efx_nic *efx = (struct efx_nic *)data;
204 efx_reado(efx, ®, FR_AB_GPIO_CTL);
205 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
206 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
209 static int falcon_getsda(void *data)
211 struct efx_nic *efx = (struct efx_nic *)data;
214 efx_reado(efx, ®, FR_AB_GPIO_CTL);
215 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
218 static int falcon_getscl(void *data)
220 struct efx_nic *efx = (struct efx_nic *)data;
223 efx_reado(efx, ®, FR_AB_GPIO_CTL);
224 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
227 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
228 .setsda = falcon_setsda,
229 .setscl = falcon_setscl,
230 .getsda = falcon_getsda,
231 .getscl = falcon_getscl,
233 /* Wait up to 50 ms for slave to let us pull SCL high */
234 .timeout = DIV_ROUND_UP(HZ, 20),
237 /**************************************************************************
239 * Falcon special buffer handling
240 * Special buffers are used for event queues and the TX and RX
243 *************************************************************************/
246 * Initialise a Falcon special buffer
248 * This will define a buffer (previously allocated via
249 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
250 * it to be used for event queues, descriptor rings etc.
253 falcon_init_special_buffer(struct efx_nic *efx,
254 struct efx_special_buffer *buffer)
256 efx_qword_t buf_desc;
261 EFX_BUG_ON_PARANOID(!buffer->addr);
263 /* Write buffer descriptors to NIC */
264 for (i = 0; i < buffer->entries; i++) {
265 index = buffer->index + i;
266 dma_addr = buffer->dma_addr + (i * 4096);
267 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
268 index, (unsigned long long)dma_addr);
269 EFX_POPULATE_QWORD_3(buf_desc,
270 FRF_AZ_BUF_ADR_REGION, 0,
271 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
272 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
273 falcon_write_buf_tbl(efx, &buf_desc, index);
277 /* Unmaps a buffer from Falcon and clears the buffer table entries */
279 falcon_fini_special_buffer(struct efx_nic *efx,
280 struct efx_special_buffer *buffer)
282 efx_oword_t buf_tbl_upd;
283 unsigned int start = buffer->index;
284 unsigned int end = (buffer->index + buffer->entries - 1);
286 if (!buffer->entries)
289 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
290 buffer->index, buffer->index + buffer->entries - 1);
292 EFX_POPULATE_OWORD_4(buf_tbl_upd,
293 FRF_AZ_BUF_UPD_CMD, 0,
294 FRF_AZ_BUF_CLR_CMD, 1,
295 FRF_AZ_BUF_CLR_END_ID, end,
296 FRF_AZ_BUF_CLR_START_ID, start);
297 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
301 * Allocate a new Falcon special buffer
303 * This allocates memory for a new buffer, clears it and allocates a
304 * new buffer ID range. It does not write into Falcon's buffer table.
306 * This call will allocate 4KB buffers, since Falcon can't use 8KB
307 * buffers for event queues and descriptor rings.
309 static int falcon_alloc_special_buffer(struct efx_nic *efx,
310 struct efx_special_buffer *buffer,
313 struct falcon_nic_data *nic_data = efx->nic_data;
315 len = ALIGN(len, FALCON_BUF_SIZE);
317 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
322 buffer->entries = len / FALCON_BUF_SIZE;
323 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
325 /* All zeros is a potentially valid event so memset to 0xff */
326 memset(buffer->addr, 0xff, len);
328 /* Select new buffer ID */
329 buffer->index = nic_data->next_buffer_table;
330 nic_data->next_buffer_table += buffer->entries;
332 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
333 "(virt %p phys %llx)\n", buffer->index,
334 buffer->index + buffer->entries - 1,
335 (u64)buffer->dma_addr, len,
336 buffer->addr, (u64)virt_to_phys(buffer->addr));
341 static void falcon_free_special_buffer(struct efx_nic *efx,
342 struct efx_special_buffer *buffer)
347 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
348 "(virt %p phys %llx)\n", buffer->index,
349 buffer->index + buffer->entries - 1,
350 (u64)buffer->dma_addr, buffer->len,
351 buffer->addr, (u64)virt_to_phys(buffer->addr));
353 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
359 /**************************************************************************
361 * Falcon generic buffer handling
362 * These buffers are used for interrupt status and MAC stats
364 **************************************************************************/
366 static int falcon_alloc_buffer(struct efx_nic *efx,
367 struct efx_buffer *buffer, unsigned int len)
369 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
374 memset(buffer->addr, 0, len);
378 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
381 pci_free_consistent(efx->pci_dev, buffer->len,
382 buffer->addr, buffer->dma_addr);
387 /**************************************************************************
391 **************************************************************************/
393 /* Returns a pointer to the specified transmit descriptor in the TX
394 * descriptor queue belonging to the specified channel.
396 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
399 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
402 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
403 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
408 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
409 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
410 efx_writed_page(tx_queue->efx, ®,
411 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
415 /* For each entry inserted into the software descriptor ring, create a
416 * descriptor in the hardware TX descriptor ring (in host memory), and
419 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
422 struct efx_tx_buffer *buffer;
426 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
429 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
430 buffer = &tx_queue->buffer[write_ptr];
431 txd = falcon_tx_desc(tx_queue, write_ptr);
432 ++tx_queue->write_count;
434 /* Create TX descriptor ring entry */
435 EFX_POPULATE_QWORD_4(*txd,
436 FSF_AZ_TX_KER_CONT, buffer->continuation,
437 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
438 FSF_AZ_TX_KER_BUF_REGION, 0,
439 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
440 } while (tx_queue->write_count != tx_queue->insert_count);
442 wmb(); /* Ensure descriptors are written before they are fetched */
443 falcon_notify_tx_desc(tx_queue);
446 /* Allocate hardware resources for a TX queue */
447 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
449 struct efx_nic *efx = tx_queue->efx;
450 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
451 EFX_TXQ_SIZE & EFX_TXQ_MASK);
452 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
453 EFX_TXQ_SIZE * sizeof(efx_qword_t));
456 void falcon_init_tx(struct efx_tx_queue *tx_queue)
458 efx_oword_t tx_desc_ptr;
459 struct efx_nic *efx = tx_queue->efx;
461 tx_queue->flushed = false;
463 /* Pin TX descriptor ring */
464 falcon_init_special_buffer(efx, &tx_queue->txd);
466 /* Push TX descriptor ring to card */
467 EFX_POPULATE_OWORD_10(tx_desc_ptr,
468 FRF_AZ_TX_DESCQ_EN, 1,
469 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
470 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
471 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
472 FRF_AZ_TX_DESCQ_EVQ_ID,
473 tx_queue->channel->channel,
474 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
475 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
476 FRF_AZ_TX_DESCQ_SIZE,
477 __ffs(tx_queue->txd.entries),
478 FRF_AZ_TX_DESCQ_TYPE, 0,
479 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
481 if (falcon_rev(efx) >= FALCON_REV_B0) {
482 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
483 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
484 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
488 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
491 if (falcon_rev(efx) < FALCON_REV_B0) {
494 /* Only 128 bits in this register */
495 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
497 efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG);
498 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
499 clear_bit_le(tx_queue->queue, (void *)®);
501 set_bit_le(tx_queue->queue, (void *)®);
502 efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG);
506 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
508 struct efx_nic *efx = tx_queue->efx;
509 efx_oword_t tx_flush_descq;
511 /* Post a flush command */
512 EFX_POPULATE_OWORD_2(tx_flush_descq,
513 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
514 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
515 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
518 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
520 struct efx_nic *efx = tx_queue->efx;
521 efx_oword_t tx_desc_ptr;
523 /* The queue should have been flushed */
524 WARN_ON(!tx_queue->flushed);
526 /* Remove TX descriptor ring from card */
527 EFX_ZERO_OWORD(tx_desc_ptr);
528 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
531 /* Unpin TX descriptor ring */
532 falcon_fini_special_buffer(efx, &tx_queue->txd);
535 /* Free buffers backing TX queue */
536 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
538 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
541 /**************************************************************************
545 **************************************************************************/
547 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
548 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
551 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
554 /* This creates an entry in the RX descriptor queue */
555 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
558 struct efx_rx_buffer *rx_buf;
561 rxd = falcon_rx_desc(rx_queue, index);
562 rx_buf = efx_rx_buffer(rx_queue, index);
563 EFX_POPULATE_QWORD_3(*rxd,
564 FSF_AZ_RX_KER_BUF_SIZE,
566 rx_queue->efx->type->rx_buffer_padding,
567 FSF_AZ_RX_KER_BUF_REGION, 0,
568 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
571 /* This writes to the RX_DESC_WPTR register for the specified receive
574 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
579 while (rx_queue->notified_count != rx_queue->added_count) {
580 falcon_build_rx_desc(rx_queue,
581 rx_queue->notified_count &
583 ++rx_queue->notified_count;
587 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
588 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
589 efx_writed_page(rx_queue->efx, ®,
590 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
593 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
595 struct efx_nic *efx = rx_queue->efx;
596 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
597 EFX_RXQ_SIZE & EFX_RXQ_MASK);
598 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
599 EFX_RXQ_SIZE * sizeof(efx_qword_t));
602 void falcon_init_rx(struct efx_rx_queue *rx_queue)
604 efx_oword_t rx_desc_ptr;
605 struct efx_nic *efx = rx_queue->efx;
606 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
607 bool iscsi_digest_en = is_b0;
609 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
610 rx_queue->queue, rx_queue->rxd.index,
611 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
613 rx_queue->flushed = false;
615 /* Pin RX descriptor ring */
616 falcon_init_special_buffer(efx, &rx_queue->rxd);
618 /* Push RX descriptor ring to card */
619 EFX_POPULATE_OWORD_10(rx_desc_ptr,
620 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
621 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
622 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
623 FRF_AZ_RX_DESCQ_EVQ_ID,
624 rx_queue->channel->channel,
625 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
626 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
627 FRF_AZ_RX_DESCQ_SIZE,
628 __ffs(rx_queue->rxd.entries),
629 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
630 /* For >=B0 this is scatter so disable */
631 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
632 FRF_AZ_RX_DESCQ_EN, 1);
633 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
637 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
639 struct efx_nic *efx = rx_queue->efx;
640 efx_oword_t rx_flush_descq;
642 /* Post a flush command */
643 EFX_POPULATE_OWORD_2(rx_flush_descq,
644 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
645 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
646 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
649 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
651 efx_oword_t rx_desc_ptr;
652 struct efx_nic *efx = rx_queue->efx;
654 /* The queue should already have been flushed */
655 WARN_ON(!rx_queue->flushed);
657 /* Remove RX descriptor ring from card */
658 EFX_ZERO_OWORD(rx_desc_ptr);
659 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
662 /* Unpin RX descriptor ring */
663 falcon_fini_special_buffer(efx, &rx_queue->rxd);
666 /* Free buffers backing RX queue */
667 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
669 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
672 /**************************************************************************
674 * Falcon event queue processing
675 * Event queues are processed by per-channel tasklets.
677 **************************************************************************/
679 /* Update a channel's event queue's read pointer (RPTR) register
681 * This writes the EVQ_RPTR_REG register for the specified channel's
684 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
685 * whereas channel->eventq_read_ptr contains the index of the "next to
688 void falcon_eventq_read_ack(struct efx_channel *channel)
691 struct efx_nic *efx = channel->efx;
693 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
694 efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base,
698 /* Use HW to insert a SW defined event */
699 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
701 efx_oword_t drv_ev_reg;
703 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
704 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
705 drv_ev_reg.u32[0] = event->u32[0];
706 drv_ev_reg.u32[1] = event->u32[1];
707 drv_ev_reg.u32[2] = 0;
708 drv_ev_reg.u32[3] = 0;
709 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
710 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
713 /* Handle a transmit completion event
715 * Falcon batches TX completion events; the message we receive is of
716 * the form "complete all TX events up to this index".
718 static void falcon_handle_tx_event(struct efx_channel *channel,
721 unsigned int tx_ev_desc_ptr;
722 unsigned int tx_ev_q_label;
723 struct efx_tx_queue *tx_queue;
724 struct efx_nic *efx = channel->efx;
726 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
727 /* Transmit completion */
728 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
729 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
730 tx_queue = &efx->tx_queue[tx_ev_q_label];
731 channel->irq_mod_score +=
732 (tx_ev_desc_ptr - tx_queue->read_count) &
734 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
735 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
736 /* Rewrite the FIFO write pointer */
737 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
738 tx_queue = &efx->tx_queue[tx_ev_q_label];
740 if (efx_dev_registered(efx))
741 netif_tx_lock(efx->net_dev);
742 falcon_notify_tx_desc(tx_queue);
743 if (efx_dev_registered(efx))
744 netif_tx_unlock(efx->net_dev);
745 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
746 EFX_WORKAROUND_10727(efx)) {
747 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
749 EFX_ERR(efx, "channel %d unexpected TX event "
750 EFX_QWORD_FMT"\n", channel->channel,
751 EFX_QWORD_VAL(*event));
755 /* Detect errors included in the rx_evt_pkt_ok bit. */
756 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
757 const efx_qword_t *event,
761 struct efx_nic *efx = rx_queue->efx;
762 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
763 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
764 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
765 bool rx_ev_other_err, rx_ev_pause_frm;
766 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
767 unsigned rx_ev_pkt_type;
769 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
770 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
771 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
772 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
773 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
774 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
775 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR);
776 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
777 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
778 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
779 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
780 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
781 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
782 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
783 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
784 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
786 /* Every error apart from tobe_disc and pause_frm */
787 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
788 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
789 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
791 /* Count errors that are not in MAC stats. Ignore expected
792 * checksum errors during self-test. */
794 ++rx_queue->channel->n_rx_frm_trunc;
795 else if (rx_ev_tobe_disc)
796 ++rx_queue->channel->n_rx_tobe_disc;
797 else if (!efx->loopback_selftest) {
798 if (rx_ev_ip_hdr_chksum_err)
799 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
800 else if (rx_ev_tcp_udp_chksum_err)
801 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
803 if (rx_ev_ip_frag_err)
804 ++rx_queue->channel->n_rx_ip_frag_err;
806 /* The frame must be discarded if any of these are true. */
807 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
808 rx_ev_tobe_disc | rx_ev_pause_frm);
810 /* TOBE_DISC is expected on unicast mismatches; don't print out an
811 * error message. FRM_TRUNC indicates RXDP dropped the packet due
812 * to a FIFO overflow.
814 #ifdef EFX_ENABLE_DEBUG
815 if (rx_ev_other_err) {
816 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
817 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
818 rx_queue->queue, EFX_QWORD_VAL(*event),
819 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
820 rx_ev_ip_hdr_chksum_err ?
821 " [IP_HDR_CHKSUM_ERR]" : "",
822 rx_ev_tcp_udp_chksum_err ?
823 " [TCP_UDP_CHKSUM_ERR]" : "",
824 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
825 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
826 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
827 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
828 rx_ev_pause_frm ? " [PAUSE]" : "");
833 /* Handle receive events that are not in-order. */
834 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
837 struct efx_nic *efx = rx_queue->efx;
838 unsigned expected, dropped;
840 expected = rx_queue->removed_count & EFX_RXQ_MASK;
841 dropped = (index - expected) & EFX_RXQ_MASK;
842 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
843 dropped, index, expected);
845 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
846 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
849 /* Handle a packet received event
851 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
852 * wrong destination address
853 * Also "is multicast" and "matches multicast filter" flags can be used to
854 * discard non-matching multicast packets.
856 static void falcon_handle_rx_event(struct efx_channel *channel,
857 const efx_qword_t *event)
859 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
860 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
861 unsigned expected_ptr;
862 bool rx_ev_pkt_ok, discard = false, checksummed;
863 struct efx_rx_queue *rx_queue;
864 struct efx_nic *efx = channel->efx;
866 /* Basic packet information */
867 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
868 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
869 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
870 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
871 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
872 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
875 rx_queue = &efx->rx_queue[channel->channel];
877 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
878 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
879 if (unlikely(rx_ev_desc_ptr != expected_ptr))
880 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
882 if (likely(rx_ev_pkt_ok)) {
883 /* If packet is marked as OK and packet type is TCP/IPv4 or
884 * UDP/IPv4, then we can rely on the hardware checksum.
887 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP ||
888 rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP;
890 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
895 /* Detect multicast packets that didn't match the filter */
896 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
897 if (rx_ev_mcast_pkt) {
898 unsigned int rx_ev_mcast_hash_match =
899 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
901 if (unlikely(!rx_ev_mcast_hash_match))
905 channel->irq_mod_score += 2;
907 /* Handle received packet */
908 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
909 checksummed, discard);
912 /* Global events are basically PHY events */
913 static void falcon_handle_global_event(struct efx_channel *channel,
916 struct efx_nic *efx = channel->efx;
917 bool handled = false;
919 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
920 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
921 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
922 efx->phy_op->clear_interrupt(efx);
923 queue_work(efx->workqueue, &efx->phy_work);
927 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
928 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
929 queue_work(efx->workqueue, &efx->mac_work);
933 if (falcon_rev(efx) <= FALCON_REV_A1 ?
934 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
935 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
936 EFX_ERR(efx, "channel %d seen global RX_RESET "
937 "event. Resetting.\n", channel->channel);
939 atomic_inc(&efx->rx_reset);
940 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
941 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
946 EFX_ERR(efx, "channel %d unknown global event "
947 EFX_QWORD_FMT "\n", channel->channel,
948 EFX_QWORD_VAL(*event));
951 static void falcon_handle_driver_event(struct efx_channel *channel,
954 struct efx_nic *efx = channel->efx;
955 unsigned int ev_sub_code;
956 unsigned int ev_sub_data;
958 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
959 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
961 switch (ev_sub_code) {
962 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
963 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
964 channel->channel, ev_sub_data);
966 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
967 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
968 channel->channel, ev_sub_data);
970 case FSE_AZ_EVQ_INIT_DONE_EV:
971 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
972 channel->channel, ev_sub_data);
974 case FSE_AZ_SRM_UPD_DONE_EV:
975 EFX_TRACE(efx, "channel %d SRAM update done\n",
978 case FSE_AZ_WAKE_UP_EV:
979 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
980 channel->channel, ev_sub_data);
982 case FSE_AZ_TIMER_EV:
983 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
984 channel->channel, ev_sub_data);
986 case FSE_AA_RX_RECOVER_EV:
987 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
988 "Resetting.\n", channel->channel);
989 atomic_inc(&efx->rx_reset);
990 efx_schedule_reset(efx,
991 EFX_WORKAROUND_6555(efx) ?
992 RESET_TYPE_RX_RECOVERY :
995 case FSE_BZ_RX_DSC_ERROR_EV:
996 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
997 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
998 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1000 case FSE_BZ_TX_DSC_ERROR_EV:
1001 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1002 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1003 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1006 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1007 "data %04x\n", channel->channel, ev_sub_code,
1013 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1015 unsigned int read_ptr;
1016 efx_qword_t event, *p_event;
1020 read_ptr = channel->eventq_read_ptr;
1023 p_event = falcon_event(channel, read_ptr);
1026 if (!falcon_event_present(&event))
1030 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1031 channel->channel, EFX_QWORD_VAL(event));
1033 /* Clear this event by marking it all ones */
1034 EFX_SET_QWORD(*p_event);
1036 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1039 case FSE_AZ_EV_CODE_RX_EV:
1040 falcon_handle_rx_event(channel, &event);
1043 case FSE_AZ_EV_CODE_TX_EV:
1044 falcon_handle_tx_event(channel, &event);
1046 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1047 channel->eventq_magic = EFX_QWORD_FIELD(
1048 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1049 EFX_LOG(channel->efx, "channel %d received generated "
1050 "event "EFX_QWORD_FMT"\n", channel->channel,
1051 EFX_QWORD_VAL(event));
1053 case FSE_AZ_EV_CODE_GLOBAL_EV:
1054 falcon_handle_global_event(channel, &event);
1056 case FSE_AZ_EV_CODE_DRIVER_EV:
1057 falcon_handle_driver_event(channel, &event);
1060 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1061 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1062 ev_code, EFX_QWORD_VAL(event));
1065 /* Increment read pointer */
1066 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1068 } while (rx_packets < rx_quota);
1070 channel->eventq_read_ptr = read_ptr;
1074 void falcon_set_int_moderation(struct efx_channel *channel)
1076 efx_dword_t timer_cmd;
1077 struct efx_nic *efx = channel->efx;
1079 /* Set timer register */
1080 if (channel->irq_moderation) {
1081 /* Round to resolution supported by hardware. The value we
1082 * program is based at 0. So actual interrupt moderation
1083 * achieved is ((x + 1) * res).
1085 channel->irq_moderation -= (channel->irq_moderation %
1086 FALCON_IRQ_MOD_RESOLUTION);
1087 if (channel->irq_moderation < FALCON_IRQ_MOD_RESOLUTION)
1088 channel->irq_moderation = FALCON_IRQ_MOD_RESOLUTION;
1089 EFX_POPULATE_DWORD_2(timer_cmd,
1090 FRF_AB_TC_TIMER_MODE,
1091 FFE_BB_TIMER_MODE_INT_HLDOFF,
1092 FRF_AB_TC_TIMER_VAL,
1093 channel->irq_moderation /
1094 FALCON_IRQ_MOD_RESOLUTION - 1);
1096 EFX_POPULATE_DWORD_2(timer_cmd,
1097 FRF_AB_TC_TIMER_MODE,
1098 FFE_BB_TIMER_MODE_DIS,
1099 FRF_AB_TC_TIMER_VAL, 0);
1101 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1102 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1107 /* Allocate buffer table entries for event queue */
1108 int falcon_probe_eventq(struct efx_channel *channel)
1110 struct efx_nic *efx = channel->efx;
1111 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1112 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1113 return falcon_alloc_special_buffer(efx, &channel->eventq,
1114 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1117 void falcon_init_eventq(struct efx_channel *channel)
1119 efx_oword_t evq_ptr;
1120 struct efx_nic *efx = channel->efx;
1122 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1123 channel->channel, channel->eventq.index,
1124 channel->eventq.index + channel->eventq.entries - 1);
1126 /* Pin event queue buffer */
1127 falcon_init_special_buffer(efx, &channel->eventq);
1129 /* Fill event queue with all ones (i.e. empty events) */
1130 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1132 /* Push event queue to card */
1133 EFX_POPULATE_OWORD_3(evq_ptr,
1135 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1136 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1137 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1140 falcon_set_int_moderation(channel);
1143 void falcon_fini_eventq(struct efx_channel *channel)
1145 efx_oword_t eventq_ptr;
1146 struct efx_nic *efx = channel->efx;
1148 /* Remove event queue from card */
1149 EFX_ZERO_OWORD(eventq_ptr);
1150 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1153 /* Unpin event queue */
1154 falcon_fini_special_buffer(efx, &channel->eventq);
1157 /* Free buffers backing event queue */
1158 void falcon_remove_eventq(struct efx_channel *channel)
1160 falcon_free_special_buffer(channel->efx, &channel->eventq);
1164 /* Generates a test event on the event queue. A subsequent call to
1165 * process_eventq() should pick up the event and place the value of
1166 * "magic" into channel->eventq_magic;
1168 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1170 efx_qword_t test_event;
1172 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1173 FSE_AZ_EV_CODE_DRV_GEN_EV,
1174 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1175 falcon_generate_event(channel, &test_event);
1178 void falcon_sim_phy_event(struct efx_nic *efx)
1180 efx_qword_t phy_event;
1182 EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE,
1183 FSE_AZ_EV_CODE_GLOBAL_EV);
1185 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1);
1187 EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1);
1189 falcon_generate_event(&efx->channel[0], &phy_event);
1192 /**************************************************************************
1196 **************************************************************************/
1199 static void falcon_poll_flush_events(struct efx_nic *efx)
1201 struct efx_channel *channel = &efx->channel[0];
1202 struct efx_tx_queue *tx_queue;
1203 struct efx_rx_queue *rx_queue;
1204 unsigned int read_ptr = channel->eventq_read_ptr;
1205 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1208 efx_qword_t *event = falcon_event(channel, read_ptr);
1209 int ev_code, ev_sub_code, ev_queue;
1212 if (!falcon_event_present(event))
1215 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1216 ev_sub_code = EFX_QWORD_FIELD(*event,
1217 FSF_AZ_DRIVER_EV_SUBCODE);
1218 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1219 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1220 ev_queue = EFX_QWORD_FIELD(*event,
1221 FSF_AZ_DRIVER_EV_SUBDATA);
1222 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1223 tx_queue = efx->tx_queue + ev_queue;
1224 tx_queue->flushed = true;
1226 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1227 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1228 ev_queue = EFX_QWORD_FIELD(
1229 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1230 ev_failed = EFX_QWORD_FIELD(
1231 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1232 if (ev_queue < efx->n_rx_queues) {
1233 rx_queue = efx->rx_queue + ev_queue;
1235 /* retry the rx flush */
1237 falcon_flush_rx_queue(rx_queue);
1239 rx_queue->flushed = true;
1243 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1244 } while (read_ptr != end_ptr);
1247 /* Handle tx and rx flushes at the same time, since they run in
1248 * parallel in the hardware and there's no reason for us to
1250 int falcon_flush_queues(struct efx_nic *efx)
1252 struct efx_rx_queue *rx_queue;
1253 struct efx_tx_queue *tx_queue;
1257 /* Issue flush requests */
1258 efx_for_each_tx_queue(tx_queue, efx) {
1259 tx_queue->flushed = false;
1260 falcon_flush_tx_queue(tx_queue);
1262 efx_for_each_rx_queue(rx_queue, efx) {
1263 rx_queue->flushed = false;
1264 falcon_flush_rx_queue(rx_queue);
1267 /* Poll the evq looking for flush completions. Since we're not pushing
1268 * any more rx or tx descriptors at this point, we're in no danger of
1269 * overflowing the evq whilst we wait */
1270 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1271 msleep(FALCON_FLUSH_INTERVAL);
1272 falcon_poll_flush_events(efx);
1274 /* Check if every queue has been succesfully flushed */
1275 outstanding = false;
1276 efx_for_each_tx_queue(tx_queue, efx)
1277 outstanding |= !tx_queue->flushed;
1278 efx_for_each_rx_queue(rx_queue, efx)
1279 outstanding |= !rx_queue->flushed;
1284 /* Mark the queues as all flushed. We're going to return failure
1285 * leading to a reset, or fake up success anyway. "flushed" now
1286 * indicates that we tried to flush. */
1287 efx_for_each_tx_queue(tx_queue, efx) {
1288 if (!tx_queue->flushed)
1289 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1291 tx_queue->flushed = true;
1293 efx_for_each_rx_queue(rx_queue, efx) {
1294 if (!rx_queue->flushed)
1295 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1297 rx_queue->flushed = true;
1300 if (EFX_WORKAROUND_7803(efx))
1306 /**************************************************************************
1308 * Falcon hardware interrupts
1309 * The hardware interrupt handler does very little work; all the event
1310 * queue processing is carried out by per-channel tasklets.
1312 **************************************************************************/
1314 /* Enable/disable/generate Falcon interrupts */
1315 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1318 efx_oword_t int_en_reg_ker;
1320 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1321 FRF_AZ_KER_INT_KER, force,
1322 FRF_AZ_DRV_INT_EN_KER, enabled);
1323 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1326 void falcon_enable_interrupts(struct efx_nic *efx)
1328 efx_oword_t int_adr_reg_ker;
1329 struct efx_channel *channel;
1331 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1332 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1334 /* Program address */
1335 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1336 FRF_AZ_NORM_INT_VEC_DIS_KER,
1337 EFX_INT_MODE_USE_MSI(efx),
1338 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1339 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1341 /* Enable interrupts */
1342 falcon_interrupts(efx, 1, 0);
1344 /* Force processing of all the channels to get the EVQ RPTRs up to
1346 efx_for_each_channel(channel, efx)
1347 efx_schedule_channel(channel);
1350 void falcon_disable_interrupts(struct efx_nic *efx)
1352 /* Disable interrupts */
1353 falcon_interrupts(efx, 0, 0);
1356 /* Generate a Falcon test interrupt
1357 * Interrupt must already have been enabled, otherwise nasty things
1360 void falcon_generate_interrupt(struct efx_nic *efx)
1362 falcon_interrupts(efx, 1, 1);
1365 /* Acknowledge a legacy interrupt from Falcon
1367 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1369 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1370 * BIU. Interrupt acknowledge is read sensitive so must write instead
1371 * (then read to ensure the BIU collector is flushed)
1373 * NB most hardware supports MSI interrupts
1375 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1379 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1380 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
1381 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1384 /* Process a fatal interrupt
1385 * Disable bus mastering ASAP and schedule a reset
1387 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1389 struct falcon_nic_data *nic_data = efx->nic_data;
1390 efx_oword_t *int_ker = efx->irq_status.addr;
1391 efx_oword_t fatal_intr;
1392 int error, mem_perr;
1394 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1395 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1397 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1398 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1399 EFX_OWORD_VAL(fatal_intr),
1400 error ? "disabling bus mastering" : "no recognised error");
1404 /* If this is a memory parity error dump which blocks are offending */
1405 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1408 efx_reado(efx, ®, FR_AZ_MEM_STAT);
1409 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1410 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1413 /* Disable both devices */
1414 pci_clear_master(efx->pci_dev);
1415 if (FALCON_IS_DUAL_FUNC(efx))
1416 pci_clear_master(nic_data->pci_dev2);
1417 falcon_disable_interrupts(efx);
1419 /* Count errors and reset or disable the NIC accordingly */
1420 if (nic_data->int_error_count == 0 ||
1421 time_after(jiffies, nic_data->int_error_expire)) {
1422 nic_data->int_error_count = 0;
1423 nic_data->int_error_expire =
1424 jiffies + FALCON_INT_ERROR_EXPIRE * HZ;
1426 if (++nic_data->int_error_count < FALCON_MAX_INT_ERRORS) {
1427 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1428 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1430 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1431 "NIC will be disabled\n");
1432 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1438 /* Handle a legacy interrupt from Falcon
1439 * Acknowledges the interrupt and schedule event queue processing.
1441 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1443 struct efx_nic *efx = dev_id;
1444 efx_oword_t *int_ker = efx->irq_status.addr;
1445 irqreturn_t result = IRQ_NONE;
1446 struct efx_channel *channel;
1451 /* Read the ISR which also ACKs the interrupts */
1452 efx_readd(efx, ®, FR_BZ_INT_ISR0);
1453 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1455 /* Check to see if we have a serious error condition */
1456 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1457 if (unlikely(syserr))
1458 return falcon_fatal_interrupt(efx);
1460 /* Schedule processing of any interrupting queues */
1461 efx_for_each_channel(channel, efx) {
1463 falcon_event_present(
1464 falcon_event(channel, channel->eventq_read_ptr))) {
1465 efx_schedule_channel(channel);
1466 result = IRQ_HANDLED;
1471 if (result == IRQ_HANDLED) {
1472 efx->last_irq_cpu = raw_smp_processor_id();
1473 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1474 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1481 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1483 struct efx_nic *efx = dev_id;
1484 efx_oword_t *int_ker = efx->irq_status.addr;
1485 struct efx_channel *channel;
1489 /* Check to see if this is our interrupt. If it isn't, we
1490 * exit without having touched the hardware.
1492 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1493 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1494 raw_smp_processor_id());
1497 efx->last_irq_cpu = raw_smp_processor_id();
1498 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1499 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1501 /* Check to see if we have a serious error condition */
1502 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1503 if (unlikely(syserr))
1504 return falcon_fatal_interrupt(efx);
1506 /* Determine interrupting queues, clear interrupt status
1507 * register and acknowledge the device interrupt.
1509 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1510 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1511 EFX_ZERO_OWORD(*int_ker);
1512 wmb(); /* Ensure the vector is cleared before interrupt ack */
1513 falcon_irq_ack_a1(efx);
1515 /* Schedule processing of any interrupting queues */
1516 channel = &efx->channel[0];
1519 efx_schedule_channel(channel);
1527 /* Handle an MSI interrupt from Falcon
1529 * Handle an MSI hardware interrupt. This routine schedules event
1530 * queue processing. No interrupt acknowledgement cycle is necessary.
1531 * Also, we never need to check that the interrupt is for us, since
1532 * MSI interrupts cannot be shared.
1534 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1536 struct efx_channel *channel = dev_id;
1537 struct efx_nic *efx = channel->efx;
1538 efx_oword_t *int_ker = efx->irq_status.addr;
1541 efx->last_irq_cpu = raw_smp_processor_id();
1542 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1543 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1545 /* Check to see if we have a serious error condition */
1546 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1547 if (unlikely(syserr))
1548 return falcon_fatal_interrupt(efx);
1550 /* Schedule processing of the channel */
1551 efx_schedule_channel(channel);
1557 /* Setup RSS indirection table.
1558 * This maps from the hash value of the packet to RXQ
1560 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1563 unsigned long offset;
1566 if (falcon_rev(efx) < FALCON_REV_B0)
1569 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1570 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1572 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1573 i % efx->n_rx_queues);
1574 efx_writed(efx, &dword, offset);
1579 /* Hook interrupt handler(s)
1580 * Try MSI and then legacy interrupts.
1582 int falcon_init_interrupt(struct efx_nic *efx)
1584 struct efx_channel *channel;
1587 if (!EFX_INT_MODE_USE_MSI(efx)) {
1588 irq_handler_t handler;
1589 if (falcon_rev(efx) >= FALCON_REV_B0)
1590 handler = falcon_legacy_interrupt_b0;
1592 handler = falcon_legacy_interrupt_a1;
1594 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1597 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1604 /* Hook MSI or MSI-X interrupt */
1605 efx_for_each_channel(channel, efx) {
1606 rc = request_irq(channel->irq, falcon_msi_interrupt,
1607 IRQF_PROBE_SHARED, /* Not shared */
1608 channel->name, channel);
1610 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1618 efx_for_each_channel(channel, efx)
1619 free_irq(channel->irq, channel);
1624 void falcon_fini_interrupt(struct efx_nic *efx)
1626 struct efx_channel *channel;
1629 /* Disable MSI/MSI-X interrupts */
1630 efx_for_each_channel(channel, efx) {
1632 free_irq(channel->irq, channel);
1635 /* ACK legacy interrupt */
1636 if (falcon_rev(efx) >= FALCON_REV_B0)
1637 efx_reado(efx, ®, FR_BZ_INT_ISR0);
1639 falcon_irq_ack_a1(efx);
1641 /* Disable legacy interrupt */
1642 if (efx->legacy_irq)
1643 free_irq(efx->legacy_irq, efx);
1646 /**************************************************************************
1650 **************************************************************************
1653 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1655 static int falcon_spi_poll(struct efx_nic *efx)
1658 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
1659 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1662 /* Wait for SPI command completion */
1663 static int falcon_spi_wait(struct efx_nic *efx)
1665 /* Most commands will finish quickly, so we start polling at
1666 * very short intervals. Sometimes the command may have to
1667 * wait for VPD or expansion ROM access outside of our
1668 * control, so we allow up to 100 ms. */
1669 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1672 for (i = 0; i < 10; i++) {
1673 if (!falcon_spi_poll(efx))
1679 if (!falcon_spi_poll(efx))
1681 if (time_after_eq(jiffies, timeout)) {
1682 EFX_ERR(efx, "timed out waiting for SPI\n");
1685 schedule_timeout_uninterruptible(1);
1689 int falcon_spi_cmd(const struct efx_spi_device *spi,
1690 unsigned int command, int address,
1691 const void *in, void *out, size_t len)
1693 struct efx_nic *efx = spi->efx;
1694 bool addressed = (address >= 0);
1695 bool reading = (out != NULL);
1699 /* Input validation */
1700 if (len > FALCON_SPI_MAX_LEN)
1702 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1704 /* Check that previous command is not still running */
1705 rc = falcon_spi_poll(efx);
1709 /* Program address register, if we have an address */
1711 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1712 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
1715 /* Program data register, if we have data */
1717 memcpy(®, in, len);
1718 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
1721 /* Issue read/write command */
1722 EFX_POPULATE_OWORD_7(reg,
1723 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
1724 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
1725 FRF_AB_EE_SPI_HCMD_DABCNT, len,
1726 FRF_AB_EE_SPI_HCMD_READ, reading,
1727 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
1728 FRF_AB_EE_SPI_HCMD_ADBCNT,
1729 (addressed ? spi->addr_len : 0),
1730 FRF_AB_EE_SPI_HCMD_ENC, command);
1731 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
1733 /* Wait for read/write to complete */
1734 rc = falcon_spi_wait(efx);
1740 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
1741 memcpy(out, ®, len);
1748 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1750 return min(FALCON_SPI_MAX_LEN,
1751 (spi->block_size - (start & (spi->block_size - 1))));
1755 efx_spi_munge_command(const struct efx_spi_device *spi,
1756 const u8 command, const unsigned int address)
1758 return command | (((address >> 8) & spi->munge_address) << 3);
1761 /* Wait up to 10 ms for buffered write completion */
1762 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1764 struct efx_nic *efx = spi->efx;
1765 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1770 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1771 &status, sizeof(status));
1774 if (!(status & SPI_STATUS_NRDY))
1776 if (time_after_eq(jiffies, timeout)) {
1777 EFX_ERR(efx, "SPI write timeout on device %d"
1778 " last status=0x%02x\n",
1779 spi->device_id, status);
1782 schedule_timeout_uninterruptible(1);
1786 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1787 size_t len, size_t *retlen, u8 *buffer)
1789 size_t block_len, pos = 0;
1790 unsigned int command;
1794 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1796 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1797 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1798 buffer + pos, block_len);
1803 /* Avoid locking up the system */
1805 if (signal_pending(current)) {
1816 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1817 size_t len, size_t *retlen, const u8 *buffer)
1819 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1820 size_t block_len, pos = 0;
1821 unsigned int command;
1825 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1829 block_len = min(len - pos,
1830 falcon_spi_write_limit(spi, start + pos));
1831 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1832 rc = falcon_spi_cmd(spi, command, start + pos,
1833 buffer + pos, NULL, block_len);
1837 rc = falcon_spi_wait_write(spi);
1841 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1842 rc = falcon_spi_cmd(spi, command, start + pos,
1843 NULL, verify_buffer, block_len);
1844 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1851 /* Avoid locking up the system */
1853 if (signal_pending(current)) {
1864 /**************************************************************************
1868 **************************************************************************
1871 static int falcon_reset_macs(struct efx_nic *efx)
1876 if (falcon_rev(efx) < FALCON_REV_B0) {
1877 /* It's not safe to use GLB_CTL_REG to reset the
1878 * macs, so instead use the internal MAC resets
1880 if (!EFX_IS10G(efx)) {
1881 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1882 efx_writeo(efx, ®, FR_AB_GM_CFG1);
1885 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1886 efx_writeo(efx, ®, FR_AB_GM_CFG1);
1890 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1891 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
1893 for (count = 0; count < 10000; count++) {
1894 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
1895 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1901 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1906 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1907 * the drain sequence with the statistics fetch */
1908 efx_stats_disable(efx);
1910 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1911 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1912 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
1914 efx_reado(efx, ®, FR_AB_GLB_CTL);
1915 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1916 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1917 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1918 efx_writeo(efx, ®, FR_AB_GLB_CTL);
1922 efx_reado(efx, ®, FR_AB_GLB_CTL);
1923 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1924 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1925 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
1926 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1931 EFX_ERR(efx, "MAC reset failed\n");
1938 efx_stats_enable(efx);
1940 /* If we've reset the EM block and the link is up, then
1941 * we'll have to kick the XAUI link so the PHY can recover */
1942 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1943 falcon_reset_xaui(efx);
1948 void falcon_drain_tx_fifo(struct efx_nic *efx)
1952 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1953 (efx->loopback_mode != LOOPBACK_NONE))
1956 efx_reado(efx, ®, FR_AB_MAC_CTRL);
1957 /* There is no point in draining more than once */
1958 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1961 falcon_reset_macs(efx);
1964 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1968 if (falcon_rev(efx) < FALCON_REV_B0)
1971 /* Isolate the MAC -> RX */
1972 efx_reado(efx, ®, FR_AZ_RX_CFG);
1973 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1974 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1977 falcon_drain_tx_fifo(efx);
1980 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1986 switch (efx->link_speed) {
1987 case 10000: link_speed = 3; break;
1988 case 1000: link_speed = 2; break;
1989 case 100: link_speed = 1; break;
1990 default: link_speed = 0; break;
1992 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1993 * as advertised. Disable to ensure packets are not
1994 * indefinitely held and TX queue can be flushed at any point
1995 * while the link is down. */
1996 EFX_POPULATE_OWORD_5(reg,
1997 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
1998 FRF_AB_MAC_BCAD_ACPT, 1,
1999 FRF_AB_MAC_UC_PROM, efx->promiscuous,
2000 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
2001 FRF_AB_MAC_SPEED, link_speed);
2002 /* On B0, MAC backpressure can be disabled and packets get
2004 if (falcon_rev(efx) >= FALCON_REV_B0) {
2005 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
2009 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
2011 /* Restore the multicast hash registers. */
2012 falcon_set_multicast_hash(efx);
2014 /* Transmission of pause frames when RX crosses the threshold is
2015 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2016 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2017 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2018 efx_reado(efx, ®, FR_AZ_RX_CFG);
2019 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2021 /* Unisolate the MAC -> RX */
2022 if (falcon_rev(efx) >= FALCON_REV_B0)
2023 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2024 efx_writeo(efx, ®, FR_AZ_RX_CFG);
2027 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2033 if (disable_dma_stats)
2036 /* Statistics fetch will fail if the MAC is in TX drain */
2037 if (falcon_rev(efx) >= FALCON_REV_B0) {
2039 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2040 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2044 dma_done = (efx->stats_buffer.addr + done_offset);
2045 *dma_done = FALCON_STATS_NOT_DONE;
2046 wmb(); /* ensure done flag is clear */
2048 /* Initiate DMA transfer of stats */
2049 EFX_POPULATE_OWORD_2(reg,
2050 FRF_AB_MAC_STAT_DMA_CMD, 1,
2051 FRF_AB_MAC_STAT_DMA_ADR,
2052 efx->stats_buffer.dma_addr);
2053 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
2055 /* Wait for transfer to complete */
2056 for (i = 0; i < 400; i++) {
2057 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2058 rmb(); /* Ensure the stats are valid. */
2064 EFX_ERR(efx, "timed out waiting for statistics\n");
2068 /**************************************************************************
2070 * PHY access via GMII
2072 **************************************************************************
2075 /* Wait for GMII access to complete */
2076 static int falcon_gmii_wait(struct efx_nic *efx)
2078 efx_dword_t md_stat;
2081 /* wait upto 50ms - taken max from datasheet */
2082 for (count = 0; count < 5000; count++) {
2083 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2084 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2085 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2086 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
2087 EFX_ERR(efx, "error from GMII access "
2089 EFX_DWORD_VAL(md_stat));
2096 EFX_ERR(efx, "timed out waiting for GMII\n");
2100 /* Write an MDIO register of a PHY connected to Falcon. */
2101 static int falcon_mdio_write(struct net_device *net_dev,
2102 int prtad, int devad, u16 addr, u16 value)
2104 struct efx_nic *efx = netdev_priv(net_dev);
2108 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2109 prtad, devad, addr, value);
2111 spin_lock_bh(&efx->phy_lock);
2113 /* Check MDIO not currently being accessed */
2114 rc = falcon_gmii_wait(efx);
2118 /* Write the address/ID register */
2119 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2120 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
2122 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2123 FRF_AB_MD_DEV_ADR, devad);
2124 efx_writeo(efx, ®, FR_AB_MD_ID);
2127 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2128 efx_writeo(efx, ®, FR_AB_MD_TXD);
2130 EFX_POPULATE_OWORD_2(reg,
2133 efx_writeo(efx, ®, FR_AB_MD_CS);
2135 /* Wait for data to be written */
2136 rc = falcon_gmii_wait(efx);
2138 /* Abort the write operation */
2139 EFX_POPULATE_OWORD_2(reg,
2142 efx_writeo(efx, ®, FR_AB_MD_CS);
2147 spin_unlock_bh(&efx->phy_lock);
2151 /* Read an MDIO register of a PHY connected to Falcon. */
2152 static int falcon_mdio_read(struct net_device *net_dev,
2153 int prtad, int devad, u16 addr)
2155 struct efx_nic *efx = netdev_priv(net_dev);
2159 spin_lock_bh(&efx->phy_lock);
2161 /* Check MDIO not currently being accessed */
2162 rc = falcon_gmii_wait(efx);
2166 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2167 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
2169 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2170 FRF_AB_MD_DEV_ADR, devad);
2171 efx_writeo(efx, ®, FR_AB_MD_ID);
2173 /* Request data to be read */
2174 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2175 efx_writeo(efx, ®, FR_AB_MD_CS);
2177 /* Wait for data to become available */
2178 rc = falcon_gmii_wait(efx);
2180 efx_reado(efx, ®, FR_AB_MD_RXD);
2181 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2182 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2183 prtad, devad, addr, rc);
2185 /* Abort the read operation */
2186 EFX_POPULATE_OWORD_2(reg,
2189 efx_writeo(efx, ®, FR_AB_MD_CS);
2191 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2192 prtad, devad, addr, rc);
2196 spin_unlock_bh(&efx->phy_lock);
2200 static int falcon_probe_phy(struct efx_nic *efx)
2202 switch (efx->phy_type) {
2203 case PHY_TYPE_SFX7101:
2204 efx->phy_op = &falcon_sfx7101_phy_ops;
2206 case PHY_TYPE_SFT9001A:
2207 case PHY_TYPE_SFT9001B:
2208 efx->phy_op = &falcon_sft9001_phy_ops;
2210 case PHY_TYPE_QT2022C2:
2211 case PHY_TYPE_QT2025C:
2212 efx->phy_op = &falcon_xfp_phy_ops;
2215 EFX_ERR(efx, "Unknown PHY type %d\n",
2220 if (efx->phy_op->macs & EFX_XMAC)
2221 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2222 (1 << LOOPBACK_XGXS) |
2223 (1 << LOOPBACK_XAUI));
2224 if (efx->phy_op->macs & EFX_GMAC)
2225 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2226 efx->loopback_modes |= efx->phy_op->loopbacks;
2231 int falcon_switch_mac(struct efx_nic *efx)
2233 struct efx_mac_operations *old_mac_op = efx->mac_op;
2234 efx_oword_t nic_stat;
2238 /* Don't try to fetch MAC stats while we're switching MACs */
2239 efx_stats_disable(efx);
2241 /* Internal loopbacks override the phy speed setting */
2242 if (efx->loopback_mode == LOOPBACK_GMAC) {
2243 efx->link_speed = 1000;
2244 efx->link_fd = true;
2245 } else if (LOOPBACK_INTERNAL(efx)) {
2246 efx->link_speed = 10000;
2247 efx->link_fd = true;
2250 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2251 efx->mac_op = (EFX_IS10G(efx) ?
2252 &falcon_xmac_operations : &falcon_gmac_operations);
2254 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2255 * changed, because this function is run post online reset */
2256 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2257 strap_val = EFX_IS10G(efx) ? 5 : 3;
2258 if (falcon_rev(efx) >= FALCON_REV_B0) {
2259 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2260 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2261 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2263 /* Falcon A1 does not support 1G/10G speed switching
2264 * and must not be used with a PHY that does. */
2265 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
2269 if (old_mac_op == efx->mac_op)
2272 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2273 /* Not all macs support a mac-level link state */
2276 rc = falcon_reset_macs(efx);
2278 efx_stats_enable(efx);
2282 /* This call is responsible for hooking in the MAC and PHY operations */
2283 int falcon_probe_port(struct efx_nic *efx)
2287 /* Hook in PHY operations table */
2288 rc = falcon_probe_phy(efx);
2292 /* Set up MDIO structure for PHY */
2293 efx->mdio.mmds = efx->phy_op->mmds;
2294 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2295 efx->mdio.mdio_read = falcon_mdio_read;
2296 efx->mdio.mdio_write = falcon_mdio_write;
2298 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2299 if (falcon_rev(efx) >= FALCON_REV_B0)
2300 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2302 efx->wanted_fc = EFX_FC_RX;
2304 /* Allocate buffer for stats */
2305 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2306 FALCON_MAC_STATS_SIZE);
2309 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
2310 (u64)efx->stats_buffer.dma_addr,
2311 efx->stats_buffer.addr,
2312 (u64)virt_to_phys(efx->stats_buffer.addr));
2317 void falcon_remove_port(struct efx_nic *efx)
2319 falcon_free_buffer(efx, &efx->stats_buffer);
2322 /**************************************************************************
2324 * Multicast filtering
2326 **************************************************************************
2329 void falcon_set_multicast_hash(struct efx_nic *efx)
2331 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2333 /* Broadcast packets go through the multicast hash filter.
2334 * ether_crc_le() of the broadcast address is 0xbe2612ff
2335 * so we always add bit 0xff to the mask.
2337 set_bit_le(0xff, mc_hash->byte);
2339 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2340 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2344 /**************************************************************************
2348 **************************************************************************/
2350 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2352 struct falcon_nvconfig *nvconfig;
2353 struct efx_spi_device *spi;
2355 int rc, magic_num, struct_ver;
2356 __le16 *word, *limit;
2359 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2363 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2366 nvconfig = region + FALCON_NVCONFIG_OFFSET;
2368 mutex_lock(&efx->spi_lock);
2369 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2370 mutex_unlock(&efx->spi_lock);
2372 EFX_ERR(efx, "Failed to read %s\n",
2373 efx->spi_flash ? "flash" : "EEPROM");
2378 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2379 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2382 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
2383 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2386 if (struct_ver < 2) {
2387 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2389 } else if (struct_ver < 4) {
2390 word = &nvconfig->board_magic_num;
2391 limit = (__le16 *) (nvconfig + 1);
2394 limit = region + FALCON_NVCONFIG_END;
2396 for (csum = 0; word < limit; ++word)
2397 csum += le16_to_cpu(*word);
2399 if (~csum & 0xffff) {
2400 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2406 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2413 /* Registers tested in the falcon register test */
2417 } efx_test_registers[] = {
2419 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2421 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2423 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2424 { FR_AZ_TX_RESERVED,
2425 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2427 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2428 { FR_AZ_SRM_TX_DC_CFG,
2429 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2431 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2432 { FR_AZ_RX_DC_PF_WM,
2433 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2435 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2437 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2439 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2441 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2443 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2445 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2446 { FR_AB_XM_RX_PARAM,
2447 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2449 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2451 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2453 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2456 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2457 const efx_oword_t *mask)
2459 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2460 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2463 int falcon_test_registers(struct efx_nic *efx)
2465 unsigned address = 0, i, j;
2466 efx_oword_t mask, imask, original, reg, buf;
2468 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2469 WARN_ON(!LOOPBACK_INTERNAL(efx));
2471 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2472 address = efx_test_registers[i].address;
2473 mask = imask = efx_test_registers[i].mask;
2474 EFX_INVERT_OWORD(imask);
2476 efx_reado(efx, &original, address);
2478 /* bit sweep on and off */
2479 for (j = 0; j < 128; j++) {
2480 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2483 /* Test this testable bit can be set in isolation */
2484 EFX_AND_OWORD(reg, original, mask);
2485 EFX_SET_OWORD32(reg, j, j, 1);
2487 efx_writeo(efx, ®, address);
2488 efx_reado(efx, &buf, address);
2490 if (efx_masked_compare_oword(®, &buf, &mask))
2493 /* Test this testable bit can be cleared in isolation */
2494 EFX_OR_OWORD(reg, original, mask);
2495 EFX_SET_OWORD32(reg, j, j, 0);
2497 efx_writeo(efx, ®, address);
2498 efx_reado(efx, &buf, address);
2500 if (efx_masked_compare_oword(®, &buf, &mask))
2504 efx_writeo(efx, &original, address);
2510 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2511 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2512 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2516 /**************************************************************************
2520 **************************************************************************
2523 /* Resets NIC to known state. This routine must be called in process
2524 * context and is allowed to sleep. */
2525 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2527 struct falcon_nic_data *nic_data = efx->nic_data;
2528 efx_oword_t glb_ctl_reg_ker;
2531 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2533 /* Initiate device reset */
2534 if (method == RESET_TYPE_WORLD) {
2535 rc = pci_save_state(efx->pci_dev);
2537 EFX_ERR(efx, "failed to backup PCI state of primary "
2538 "function prior to hardware reset\n");
2541 if (FALCON_IS_DUAL_FUNC(efx)) {
2542 rc = pci_save_state(nic_data->pci_dev2);
2544 EFX_ERR(efx, "failed to backup PCI state of "
2545 "secondary function prior to "
2546 "hardware reset\n");
2551 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2552 FRF_AB_EXT_PHY_RST_DUR,
2553 FFE_AB_EXT_PHY_RST_DUR_10240US,
2556 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2557 /* exclude PHY from "invisible" reset */
2558 FRF_AB_EXT_PHY_RST_CTL,
2559 method == RESET_TYPE_INVISIBLE,
2560 /* exclude EEPROM/flash and PCIe */
2561 FRF_AB_PCIE_CORE_RST_CTL, 1,
2562 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
2563 FRF_AB_PCIE_SD_RST_CTL, 1,
2564 FRF_AB_EE_RST_CTL, 1,
2565 FRF_AB_EXT_PHY_RST_DUR,
2566 FFE_AB_EXT_PHY_RST_DUR_10240US,
2569 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2571 EFX_LOG(efx, "waiting for hardware reset\n");
2572 schedule_timeout_uninterruptible(HZ / 20);
2574 /* Restore PCI configuration if needed */
2575 if (method == RESET_TYPE_WORLD) {
2576 if (FALCON_IS_DUAL_FUNC(efx)) {
2577 rc = pci_restore_state(nic_data->pci_dev2);
2579 EFX_ERR(efx, "failed to restore PCI config for "
2580 "the secondary function\n");
2584 rc = pci_restore_state(efx->pci_dev);
2586 EFX_ERR(efx, "failed to restore PCI config for the "
2587 "primary function\n");
2590 EFX_LOG(efx, "successfully restored PCI config\n");
2593 /* Assert that reset complete */
2594 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2595 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2597 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2600 EFX_LOG(efx, "hardware reset complete\n");
2604 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2607 pci_restore_state(efx->pci_dev);
2614 /* Zeroes out the SRAM contents. This routine must be called in
2615 * process context and is allowed to sleep.
2617 static int falcon_reset_sram(struct efx_nic *efx)
2619 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2622 /* Set the SRAM wake/sleep GPIO appropriately. */
2623 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2624 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2625 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2626 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2628 /* Initiate SRAM reset */
2629 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2630 FRF_AZ_SRM_INIT_EN, 1,
2631 FRF_AZ_SRM_NB_SZ, 0);
2632 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2634 /* Wait for SRAM reset to complete */
2637 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2639 /* SRAM reset is slow; expect around 16ms */
2640 schedule_timeout_uninterruptible(HZ / 50);
2642 /* Check for reset complete */
2643 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2644 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2645 EFX_LOG(efx, "SRAM reset complete\n");
2649 } while (++count < 20); /* wait upto 0.4 sec */
2651 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2655 static int falcon_spi_device_init(struct efx_nic *efx,
2656 struct efx_spi_device **spi_device_ret,
2657 unsigned int device_id, u32 device_type)
2659 struct efx_spi_device *spi_device;
2661 if (device_type != 0) {
2662 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
2665 spi_device->device_id = device_id;
2667 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2668 spi_device->addr_len =
2669 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2670 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2671 spi_device->addr_len == 1);
2672 spi_device->erase_command =
2673 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2674 spi_device->erase_size =
2675 1 << SPI_DEV_TYPE_FIELD(device_type,
2676 SPI_DEV_TYPE_ERASE_SIZE);
2677 spi_device->block_size =
2678 1 << SPI_DEV_TYPE_FIELD(device_type,
2679 SPI_DEV_TYPE_BLOCK_SIZE);
2681 spi_device->efx = efx;
2686 kfree(*spi_device_ret);
2687 *spi_device_ret = spi_device;
2692 static void falcon_remove_spi_devices(struct efx_nic *efx)
2694 kfree(efx->spi_eeprom);
2695 efx->spi_eeprom = NULL;
2696 kfree(efx->spi_flash);
2697 efx->spi_flash = NULL;
2700 /* Extract non-volatile configuration */
2701 static int falcon_probe_nvconfig(struct efx_nic *efx)
2703 struct falcon_nvconfig *nvconfig;
2707 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2711 rc = falcon_read_nvram(efx, nvconfig);
2712 if (rc == -EINVAL) {
2713 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2714 efx->phy_type = PHY_TYPE_NONE;
2715 efx->mdio.prtad = MDIO_PRTAD_NONE;
2721 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2722 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2724 efx->phy_type = v2->port0_phy_type;
2725 efx->mdio.prtad = v2->port0_phy_addr;
2726 board_rev = le16_to_cpu(v2->board_revision);
2728 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2729 rc = falcon_spi_device_init(
2730 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
2731 le32_to_cpu(v3->spi_device_type
2732 [FFE_AB_SPI_DEVICE_FLASH]));
2735 rc = falcon_spi_device_init(
2736 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
2737 le32_to_cpu(v3->spi_device_type
2738 [FFE_AB_SPI_DEVICE_EEPROM]));
2744 /* Read the MAC addresses */
2745 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2747 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2749 falcon_probe_board(efx, board_rev);
2755 falcon_remove_spi_devices(efx);
2761 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2762 * count, port speed). Set workaround and feature flags accordingly.
2764 static int falcon_probe_nic_variant(struct efx_nic *efx)
2766 efx_oword_t altera_build;
2767 efx_oword_t nic_stat;
2769 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2770 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2771 EFX_ERR(efx, "Falcon FPGA not supported\n");
2775 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2777 switch (falcon_rev(efx)) {
2780 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2784 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
2785 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2794 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2798 /* Initial assumed speed */
2799 efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000;
2804 /* Probe all SPI devices on the NIC */
2805 static void falcon_probe_spi_devices(struct efx_nic *efx)
2807 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2810 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2811 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2812 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2814 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2815 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
2816 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
2817 EFX_LOG(efx, "Booted from %s\n",
2818 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
2820 /* Disable VPD and set clock dividers to safe
2821 * values for initial programming. */
2823 EFX_LOG(efx, "Booted from internal ASIC settings;"
2824 " setting SPI config\n");
2825 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
2826 /* 125 MHz / 7 ~= 20 MHz */
2827 FRF_AB_EE_SF_CLOCK_DIV, 7,
2828 /* 125 MHz / 63 ~= 2 MHz */
2829 FRF_AB_EE_EE_CLOCK_DIV, 63);
2830 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2833 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
2834 falcon_spi_device_init(efx, &efx->spi_flash,
2835 FFE_AB_SPI_DEVICE_FLASH,
2836 default_flash_type);
2837 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
2838 falcon_spi_device_init(efx, &efx->spi_eeprom,
2839 FFE_AB_SPI_DEVICE_EEPROM,
2843 int falcon_probe_nic(struct efx_nic *efx)
2845 struct falcon_nic_data *nic_data;
2848 /* Allocate storage for hardware specific data */
2849 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2852 efx->nic_data = nic_data;
2854 /* Determine number of ports etc. */
2855 rc = falcon_probe_nic_variant(efx);
2859 /* Probe secondary function if expected */
2860 if (FALCON_IS_DUAL_FUNC(efx)) {
2861 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2863 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2865 if (dev->bus == efx->pci_dev->bus &&
2866 dev->devfn == efx->pci_dev->devfn + 1) {
2867 nic_data->pci_dev2 = dev;
2871 if (!nic_data->pci_dev2) {
2872 EFX_ERR(efx, "failed to find secondary function\n");
2878 /* Now we can reset the NIC */
2879 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2881 EFX_ERR(efx, "failed to reset NIC\n");
2885 /* Allocate memory for INT_KER */
2886 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2889 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2891 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
2892 (u64)efx->irq_status.dma_addr,
2893 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
2895 falcon_probe_spi_devices(efx);
2897 /* Read in the non-volatile configuration */
2898 rc = falcon_probe_nvconfig(efx);
2902 /* Initialise I2C adapter */
2903 efx->i2c_adap.owner = THIS_MODULE;
2904 nic_data->i2c_data = falcon_i2c_bit_operations;
2905 nic_data->i2c_data.data = efx;
2906 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2907 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2908 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2909 rc = i2c_bit_add_bus(&efx->i2c_adap);
2916 falcon_remove_spi_devices(efx);
2917 falcon_free_buffer(efx, &efx->irq_status);
2920 if (nic_data->pci_dev2) {
2921 pci_dev_put(nic_data->pci_dev2);
2922 nic_data->pci_dev2 = NULL;
2926 kfree(efx->nic_data);
2930 static void falcon_init_rx_cfg(struct efx_nic *efx)
2932 /* Prior to Siena the RX DMA engine will split each frame at
2933 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
2934 * be so large that that never happens. */
2935 const unsigned huge_buf_size = (3 * 4096) >> 5;
2936 /* RX control FIFO thresholds (32 entries) */
2937 const unsigned ctrl_xon_thr = 20;
2938 const unsigned ctrl_xoff_thr = 25;
2939 /* RX data FIFO thresholds (256-byte units; size varies) */
2940 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2941 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2944 efx_reado(efx, ®, FR_AZ_RX_CFG);
2945 if (falcon_rev(efx) <= FALCON_REV_A1) {
2946 /* Data FIFO size is 5.5K */
2947 if (data_xon_thr < 0)
2948 data_xon_thr = 512 >> 8;
2949 if (data_xoff_thr < 0)
2950 data_xoff_thr = 2048 >> 8;
2951 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
2952 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
2954 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
2955 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
2956 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
2957 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
2959 /* Data FIFO size is 80K; register fields moved */
2960 if (data_xon_thr < 0)
2961 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2962 if (data_xoff_thr < 0)
2963 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2964 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
2965 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
2967 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
2968 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
2969 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
2970 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2971 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2973 efx_writeo(efx, ®, FR_AZ_RX_CFG);
2976 /* This call performs hardware-specific global initialisation, such as
2977 * defining the descriptor cache sizes and number of RSS channels.
2978 * It does not set up any buffers, descriptor rings or event queues.
2980 int falcon_init_nic(struct efx_nic *efx)
2985 /* Use on-chip SRAM */
2986 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2987 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2988 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2990 /* Set the source of the GMAC clock */
2991 if (falcon_rev(efx) == FALCON_REV_B0) {
2992 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2993 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2994 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
2997 rc = falcon_reset_sram(efx);
3001 /* Set positions of descriptor caches in SRAM. */
3002 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
3003 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3004 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
3005 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3007 /* Set TX descriptor cache size. */
3008 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3009 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3010 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3012 /* Set RX descriptor cache size. Set low watermark to size-8, as
3013 * this allows most efficient prefetching.
3015 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3016 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3017 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3018 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3019 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3021 /* Clear the parity enables on the TX data fifos as
3022 * they produce false parity errors because of timing issues
3024 if (EFX_WORKAROUND_5129(efx)) {
3025 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3026 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3027 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3030 /* Enable all the genuinely fatal interrupts. (They are still
3031 * masked by the overall interrupt mask, controlled by
3032 * falcon_interrupts()).
3034 * Note: All other fatal interrupts are enabled
3036 EFX_POPULATE_OWORD_3(temp,
3037 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3038 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3039 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3040 EFX_INVERT_OWORD(temp);
3041 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3043 if (EFX_WORKAROUND_7244(efx)) {
3044 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3045 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3046 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3047 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3048 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3049 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3052 falcon_setup_rss_indir_table(efx);
3054 /* XXX This is documented only for Falcon A0/A1 */
3055 /* Setup RX. Wait for descriptor is broken and must
3056 * be disabled. RXDP recovery shouldn't be needed, but is.
3058 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3059 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3060 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3061 if (EFX_WORKAROUND_5583(efx))
3062 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3063 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3065 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3066 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3068 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3069 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3070 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3071 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3072 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3073 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3074 /* Enable SW_EV to inherit in char driver - assume harmless here */
3075 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3076 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3077 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3078 /* Squash TX of packets of 16 bytes or less */
3079 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3080 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3081 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3083 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3084 * descriptors (which is bad).
3086 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3087 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3088 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3090 falcon_init_rx_cfg(efx);
3092 /* Set destination of both TX and RX Flush events */
3093 if (falcon_rev(efx) >= FALCON_REV_B0) {
3094 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3095 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3101 void falcon_remove_nic(struct efx_nic *efx)
3103 struct falcon_nic_data *nic_data = efx->nic_data;
3106 /* Remove I2C adapter and clear it in preparation for a retry */
3107 rc = i2c_del_adapter(&efx->i2c_adap);
3109 memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap));
3111 falcon_remove_spi_devices(efx);
3112 falcon_free_buffer(efx, &efx->irq_status);
3114 falcon_reset_hw(efx, RESET_TYPE_ALL);
3116 /* Release the second function after the reset */
3117 if (nic_data->pci_dev2) {
3118 pci_dev_put(nic_data->pci_dev2);
3119 nic_data->pci_dev2 = NULL;
3122 /* Tear down the private nic state */
3123 kfree(efx->nic_data);
3124 efx->nic_data = NULL;
3127 void falcon_update_nic_stats(struct efx_nic *efx)
3131 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3132 efx->n_rx_nodesc_drop_cnt +=
3133 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3136 /**************************************************************************
3138 * Revision-dependent attributes used by efx.c
3140 **************************************************************************
3143 struct efx_nic_type falcon_a_nic_type = {
3145 .mem_map_size = 0x20000,
3146 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
3147 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
3148 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
3149 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
3150 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
3151 .max_dma_mask = FALCON_DMA_MASK,
3152 .tx_dma_mask = FALCON_TX_DMA_MASK,
3153 .bug5391_mask = 0xf,
3154 .rx_buffer_padding = 0x24,
3155 .max_interrupt_mode = EFX_INT_MODE_MSI,
3156 .phys_addr_channels = 4,
3159 struct efx_nic_type falcon_b_nic_type = {
3161 /* Map everything up to and including the RSS indirection
3162 * table. Don't map MSI-X table, MSI-X PBA since Linux
3163 * requires that they not be mapped. */
3164 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
3165 FR_BZ_RX_INDIRECTION_TBL_STEP *
3166 FR_BZ_RX_INDIRECTION_TBL_ROWS),
3167 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
3168 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
3169 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
3170 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
3171 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
3172 .max_dma_mask = FALCON_DMA_MASK,
3173 .tx_dma_mask = FALCON_TX_DMA_MASK,
3175 .rx_buffer_padding = 0,
3176 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3177 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3178 * interrupt handler only supports 32