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   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  * napi: This parameter used to enable/disable NAPI (polling Rx)
  46  *     Possible values '1' for enable and '0' for disable. Default is '1'
  47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48  *      Possible values '1' for enable and '0' for disable. Default is '0'
  49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50  *                 Possible values '1' for enable , '0' for disable.
  51  *                 Default is '2' - which means disable in promisc mode
  52  *                 and enable in non-promiscuous mode.
  53  ************************************************************************/
  54
  55 #include <linux/module.h>
  56 #include <linux/types.h>
  57 #include <linux/errno.h>
  58 #include <linux/ioport.h>
  59 #include <linux/pci.h>
  60 #include <linux/dma-mapping.h>
  61 #include <linux/kernel.h>
  62 #include <linux/netdevice.h>
  63 #include <linux/etherdevice.h>
  64 #include <linux/skbuff.h>
  65 #include <linux/init.h>
  66 #include <linux/delay.h>
  67 #include <linux/stddef.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/timex.h>
  70 #include <linux/ethtool.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/if_vlan.h>
  73 #include <linux/ip.h>
  74 #include <linux/tcp.h>
  75 #include <net/tcp.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/uaccess.h>
  79 #include <asm/io.h>
  80 #include <asm/div64.h>
  81 #include <asm/irq.h>
  82
  83 /* local include */
  84 #include "s2io.h"
  85 #include "s2io-regs.h"
  86
  87 #define DRV_VERSION "2.0.23.1"
  88
  89 /* S2io Driver name & version. */
  90 static char s2io_driver_name[] = "Neterion";
  91 static char s2io_driver_version[] = DRV_VERSION;
  92
  93 static int rxd_size[2] = {32,48};
  94 static int rxd_count[2] = {127,85};
  95
  96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  97 {
  98         int ret;
  99
 100         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 101                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 102
 103         return ret;
 104 }
 105
 106 /*
 107  * Cards with following subsystem_id have a link state indication
 108  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 109  * macro below identifies these cards given the subsystem_id.
 110  */
 111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 112         (dev_type == XFRAME_I_DEVICE) ?                 \
 113                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 114                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 115
 116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 117                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 119 #define PANIC   1
 120 #define LOW     2
 121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
 122 {
 123         struct mac_info *mac_control;
 124
 125         mac_control = &sp->mac_control;
 126         if (rxb_size <= rxd_count[sp->rxd_mode])
 127                 return PANIC;
 128         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 129                 return  LOW;
 130         return 0;
 131 }
 132
 133 /* Ethtool related variables and Macros. */
 134 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 135         "Register test\t(offline)",
 136         "Eeprom test\t(offline)",
 137         "Link test\t(online)",
 138         "RLDRAM test\t(offline)",
 139         "BIST Test\t(offline)"
 140 };
 141
 142 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 143         {"tmac_frms"},
 144         {"tmac_data_octets"},
 145         {"tmac_drop_frms"},
 146         {"tmac_mcst_frms"},
 147         {"tmac_bcst_frms"},
 148         {"tmac_pause_ctrl_frms"},
 149         {"tmac_ttl_octets"},
 150         {"tmac_ucst_frms"},
 151         {"tmac_nucst_frms"},
 152         {"tmac_any_err_frms"},
 153         {"tmac_ttl_less_fb_octets"},
 154         {"tmac_vld_ip_octets"},
 155         {"tmac_vld_ip"},
 156         {"tmac_drop_ip"},
 157         {"tmac_icmp"},
 158         {"tmac_rst_tcp"},
 159         {"tmac_tcp"},
 160         {"tmac_udp"},
 161         {"rmac_vld_frms"},
 162         {"rmac_data_octets"},
 163         {"rmac_fcs_err_frms"},
 164         {"rmac_drop_frms"},
 165         {"rmac_vld_mcst_frms"},
 166         {"rmac_vld_bcst_frms"},
 167         {"rmac_in_rng_len_err_frms"},
 168         {"rmac_out_rng_len_err_frms"},
 169         {"rmac_long_frms"},
 170         {"rmac_pause_ctrl_frms"},
 171         {"rmac_unsup_ctrl_frms"},
 172         {"rmac_ttl_octets"},
 173         {"rmac_accepted_ucst_frms"},
 174         {"rmac_accepted_nucst_frms"},
 175         {"rmac_discarded_frms"},
 176         {"rmac_drop_events"},
 177         {"rmac_ttl_less_fb_octets"},
 178         {"rmac_ttl_frms"},
 179         {"rmac_usized_frms"},
 180         {"rmac_osized_frms"},
 181         {"rmac_frag_frms"},
 182         {"rmac_jabber_frms"},
 183         {"rmac_ttl_64_frms"},
 184         {"rmac_ttl_65_127_frms"},
 185         {"rmac_ttl_128_255_frms"},
 186         {"rmac_ttl_256_511_frms"},
 187         {"rmac_ttl_512_1023_frms"},
 188         {"rmac_ttl_1024_1518_frms"},
 189         {"rmac_ip"},
 190         {"rmac_ip_octets"},
 191         {"rmac_hdr_err_ip"},
 192         {"rmac_drop_ip"},
 193         {"rmac_icmp"},
 194         {"rmac_tcp"},
 195         {"rmac_udp"},
 196         {"rmac_err_drp_udp"},
 197         {"rmac_xgmii_err_sym"},
 198         {"rmac_frms_q0"},
 199         {"rmac_frms_q1"},
 200         {"rmac_frms_q2"},
 201         {"rmac_frms_q3"},
 202         {"rmac_frms_q4"},
 203         {"rmac_frms_q5"},
 204         {"rmac_frms_q6"},
 205         {"rmac_frms_q7"},
 206         {"rmac_full_q0"},
 207         {"rmac_full_q1"},
 208         {"rmac_full_q2"},
 209         {"rmac_full_q3"},
 210         {"rmac_full_q4"},
 211         {"rmac_full_q5"},
 212         {"rmac_full_q6"},
 213         {"rmac_full_q7"},
 214         {"rmac_pause_cnt"},
 215         {"rmac_xgmii_data_err_cnt"},
 216         {"rmac_xgmii_ctrl_err_cnt"},
 217         {"rmac_accepted_ip"},
 218         {"rmac_err_tcp"},
 219         {"rd_req_cnt"},
 220         {"new_rd_req_cnt"},
 221         {"new_rd_req_rtry_cnt"},
 222         {"rd_rtry_cnt"},
 223         {"wr_rtry_rd_ack_cnt"},
 224         {"wr_req_cnt"},
 225         {"new_wr_req_cnt"},
 226         {"new_wr_req_rtry_cnt"},
 227         {"wr_rtry_cnt"},
 228         {"wr_disc_cnt"},
 229         {"rd_rtry_wr_ack_cnt"},
 230         {"txp_wr_cnt"},
 231         {"txd_rd_cnt"},
 232         {"txd_wr_cnt"},
 233         {"rxd_rd_cnt"},
 234         {"rxd_wr_cnt"},
 235         {"txf_rd_cnt"},
 236         {"rxf_wr_cnt"}
 237 };
 238
 239 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 240         {"rmac_ttl_1519_4095_frms"},
 241         {"rmac_ttl_4096_8191_frms"},
 242         {"rmac_ttl_8192_max_frms"},
 243         {"rmac_ttl_gt_max_frms"},
 244         {"rmac_osized_alt_frms"},
 245         {"rmac_jabber_alt_frms"},
 246         {"rmac_gt_max_alt_frms"},
 247         {"rmac_vlan_frms"},
 248         {"rmac_len_discard"},
 249         {"rmac_fcs_discard"},
 250         {"rmac_pf_discard"},
 251         {"rmac_da_discard"},
 252         {"rmac_red_discard"},
 253         {"rmac_rts_discard"},
 254         {"rmac_ingm_full_discard"},
 255         {"link_fault_cnt"}
 256 };
 257
 258 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 259         {"\n DRIVER STATISTICS"},
 260         {"single_bit_ecc_errs"},
 261         {"double_bit_ecc_errs"},
 262         {"parity_err_cnt"},
 263         {"serious_err_cnt"},
 264         {"soft_reset_cnt"},
 265         {"fifo_full_cnt"},
 266         {"ring_full_cnt"},
 267         ("alarm_transceiver_temp_high"),
 268         ("alarm_transceiver_temp_low"),
 269         ("alarm_laser_bias_current_high"),
 270         ("alarm_laser_bias_current_low"),
 271         ("alarm_laser_output_power_high"),
 272         ("alarm_laser_output_power_low"),
 273         ("warn_transceiver_temp_high"),
 274         ("warn_transceiver_temp_low"),
 275         ("warn_laser_bias_current_high"),
 276         ("warn_laser_bias_current_low"),
 277         ("warn_laser_output_power_high"),
 278         ("warn_laser_output_power_low"),
 279         ("lro_aggregated_pkts"),
 280         ("lro_flush_both_count"),
 281         ("lro_out_of_sequence_pkts"),
 282         ("lro_flush_due_to_max_pkts"),
 283         ("lro_avg_aggr_pkts"),
 284         ("mem_alloc_fail_cnt"),
 285         ("watchdog_timer_cnt"),
 286         ("mem_allocated"),
 287         ("mem_freed"),
 288         ("link_up_cnt"),
 289         ("link_down_cnt"),
 290         ("link_up_time"),
 291         ("link_down_time"),
 292         ("tx_tcode_buf_abort_cnt"),
 293         ("tx_tcode_desc_abort_cnt"),
 294         ("tx_tcode_parity_err_cnt"),
 295         ("tx_tcode_link_loss_cnt"),
 296         ("tx_tcode_list_proc_err_cnt"),
 297         ("rx_tcode_parity_err_cnt"),
 298         ("rx_tcode_abort_cnt"),
 299         ("rx_tcode_parity_abort_cnt"),
 300         ("rx_tcode_rda_fail_cnt"),
 301         ("rx_tcode_unkn_prot_cnt"),
 302         ("rx_tcode_fcs_err_cnt"),
 303         ("rx_tcode_buf_size_err_cnt"),
 304         ("rx_tcode_rxd_corrupt_cnt"),
 305         ("rx_tcode_unkn_err_cnt")
 306 };
 307
 308 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
 309 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
 310                                         ETH_GSTRING_LEN
 311 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
 312
 313 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
 314 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
 315
 316 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
 317 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
 318
 319 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 320 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 321
 322 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 323                         init_timer(&timer);                     \
 324                         timer.function = handle;                \
 325                         timer.data = (unsigned long) arg;       \
 326                         mod_timer(&timer, (jiffies + exp))      \
 327
 328 /* Add the vlan */
 329 static void s2io_vlan_rx_register(struct net_device *dev,
 330                                         struct vlan_group *grp)
 331 {
 332         struct s2io_nic *nic = dev->priv;
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&nic->tx_lock, flags);
 336         nic->vlgrp = grp;
 337         spin_unlock_irqrestore(&nic->tx_lock, flags);
 338 }
 339
 340 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
 341 static int vlan_strip_flag;
 342
 343 /*
 344  * Constants to be programmed into the Xena's registers, to configure
 345  * the XAUI.
 346  */
 347
 348 #define END_SIGN        0x0
 349 static const u64 herc_act_dtx_cfg[] = {
 350         /* Set address */
 351         0x8000051536750000ULL, 0x80000515367500E0ULL,
 352         /* Write data */
 353         0x8000051536750004ULL, 0x80000515367500E4ULL,
 354         /* Set address */
 355         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 356         /* Write data */
 357         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 358         /* Set address */
 359         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 360         /* Write data */
 361         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 362         /* Set address */
 363         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 364         /* Write data */
 365         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 366         /* Done */
 367         END_SIGN
 368 };
 369
 370 static const u64 xena_dtx_cfg[] = {
 371         /* Set address */
 372         0x8000051500000000ULL, 0x80000515000000E0ULL,
 373         /* Write data */
 374         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 375         /* Set address */
 376         0x8001051500000000ULL, 0x80010515000000E0ULL,
 377         /* Write data */
 378         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 379         /* Set address */
 380         0x8002051500000000ULL, 0x80020515000000E0ULL,
 381         /* Write data */
 382         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 383         END_SIGN
 384 };
 385
 386 /*
 387  * Constants for Fixing the MacAddress problem seen mostly on
 388  * Alpha machines.
 389  */
 390 static const u64 fix_mac[] = {
 391         0x0060000000000000ULL, 0x0060600000000000ULL,
 392         0x0040600000000000ULL, 0x0000600000000000ULL,
 393         0x0020600000000000ULL, 0x0060600000000000ULL,
 394         0x0020600000000000ULL, 0x0060600000000000ULL,
 395         0x0020600000000000ULL, 0x0060600000000000ULL,
 396         0x0020600000000000ULL, 0x0060600000000000ULL,
 397         0x0020600000000000ULL, 0x0060600000000000ULL,
 398         0x0020600000000000ULL, 0x0060600000000000ULL,
 399         0x0020600000000000ULL, 0x0060600000000000ULL,
 400         0x0020600000000000ULL, 0x0060600000000000ULL,
 401         0x0020600000000000ULL, 0x0060600000000000ULL,
 402         0x0020600000000000ULL, 0x0060600000000000ULL,
 403         0x0020600000000000ULL, 0x0000600000000000ULL,
 404         0x0040600000000000ULL, 0x0060600000000000ULL,
 405         END_SIGN
 406 };
 407
 408 MODULE_LICENSE("GPL");
 409 MODULE_VERSION(DRV_VERSION);
 410
 411
 412 /* Module Loadable parameters. */
 413 S2IO_PARM_INT(tx_fifo_num, 1);
 414 S2IO_PARM_INT(rx_ring_num, 1);
 415
 416
 417 S2IO_PARM_INT(rx_ring_mode, 1);
 418 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 419 S2IO_PARM_INT(rmac_pause_time, 0x100);
 420 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 421 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 422 S2IO_PARM_INT(shared_splits, 0);
 423 S2IO_PARM_INT(tmac_util_period, 5);
 424 S2IO_PARM_INT(rmac_util_period, 5);
 425 S2IO_PARM_INT(bimodal, 0);
 426 S2IO_PARM_INT(l3l4hdr_size, 128);
 427 /* Frequency of Rx desc syncs expressed as power of 2 */
 428 S2IO_PARM_INT(rxsync_frequency, 3);
 429 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 430 S2IO_PARM_INT(intr_type, 0);
 431 /* Large receive offload feature */
 432 S2IO_PARM_INT(lro, 0);
 433 /* Max pkts to be aggregated by LRO at one time. If not specified,
 434  * aggregation happens until we hit max IP pkt size(64K)
 435  */
 436 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 437 S2IO_PARM_INT(indicate_max_pkts, 0);
 438
 439 S2IO_PARM_INT(napi, 1);
 440 S2IO_PARM_INT(ufo, 0);
 441 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 442
 443 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 444     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 445 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 446     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 447 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 448     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 449
 450 module_param_array(tx_fifo_len, uint, NULL, 0);
 451 module_param_array(rx_ring_sz, uint, NULL, 0);
 452 module_param_array(rts_frm_len, uint, NULL, 0);
 453
 454 /*
 455  * S2IO device table.
 456  * This table lists all the devices that this driver supports.
 457  */
 458 static struct pci_device_id s2io_tbl[] __devinitdata = {
 459         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 460          PCI_ANY_ID, PCI_ANY_ID},
 461         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 462          PCI_ANY_ID, PCI_ANY_ID},
 463         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 464          PCI_ANY_ID, PCI_ANY_ID},
 465         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 466          PCI_ANY_ID, PCI_ANY_ID},
 467         {0,}
 468 };
 469
 470 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 471
 472 static struct pci_error_handlers s2io_err_handler = {
 473         .error_detected = s2io_io_error_detected,
 474         .slot_reset = s2io_io_slot_reset,
 475         .resume = s2io_io_resume,
 476 };
 477
 478 static struct pci_driver s2io_driver = {
 479       .name = "S2IO",
 480       .id_table = s2io_tbl,
 481       .probe = s2io_init_nic,
 482       .remove = __devexit_p(s2io_rem_nic),
 483       .err_handler = &s2io_err_handler,
 484 };
 485
 486 /* A simplifier macro used both by init and free shared_mem Fns(). */
 487 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 488
 489 /**
 490  * init_shared_mem - Allocation and Initialization of Memory
 491  * @nic: Device private variable.
 492  * Description: The function allocates all the memory areas shared
 493  * between the NIC and the driver. This includes Tx descriptors,
 494  * Rx descriptors and the statistics block.
 495  */
 496
 497 static int init_shared_mem(struct s2io_nic *nic)
 498 {
 499         u32 size;
 500         void *tmp_v_addr, *tmp_v_addr_next;
 501         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 502         struct RxD_block *pre_rxd_blk = NULL;
 503         int i, j, blk_cnt;
 504         int lst_size, lst_per_page;
 505         struct net_device *dev = nic->dev;
 506         unsigned long tmp;
 507         struct buffAdd *ba;
 508
 509         struct mac_info *mac_control;
 510         struct config_param *config;
 511         unsigned long long mem_allocated = 0;
 512
 513         mac_control = &nic->mac_control;
 514         config = &nic->config;
 515
 516
 517         /* Allocation and initialization of TXDLs in FIOFs */
 518         size = 0;
 519         for (i = 0; i < config->tx_fifo_num; i++) {
 520                 size += config->tx_cfg[i].fifo_len;
 521         }
 522         if (size > MAX_AVAILABLE_TXDS) {
 523                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 524                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 525                 return -EINVAL;
 526         }
 527
 528         lst_size = (sizeof(struct TxD) * config->max_txds);
 529         lst_per_page = PAGE_SIZE / lst_size;
 530
 531         for (i = 0; i < config->tx_fifo_num; i++) {
 532                 int fifo_len = config->tx_cfg[i].fifo_len;
 533                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 534                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 535                                                           GFP_KERNEL);
 536                 if (!mac_control->fifos[i].list_info) {
 537                         DBG_PRINT(INFO_DBG,
 538                                   "Malloc failed for list_info\n");
 539                         return -ENOMEM;
 540                 }
 541                 mem_allocated += list_holder_size;
 542                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 543         }
 544         for (i = 0; i < config->tx_fifo_num; i++) {
 545                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 546                                                 lst_per_page);
 547                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 548                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 549                     config->tx_cfg[i].fifo_len - 1;
 550                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 551                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 552                     config->tx_cfg[i].fifo_len - 1;
 553                 mac_control->fifos[i].fifo_no = i;
 554                 mac_control->fifos[i].nic = nic;
 555                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 556
 557                 for (j = 0; j < page_num; j++) {
 558                         int k = 0;
 559                         dma_addr_t tmp_p;
 560                         void *tmp_v;
 561                         tmp_v = pci_alloc_consistent(nic->pdev,
 562                                                      PAGE_SIZE, &tmp_p);
 563                         if (!tmp_v) {
 564                                 DBG_PRINT(INFO_DBG,
 565                                           "pci_alloc_consistent ");
 566                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 567                                 return -ENOMEM;
 568                         }
 569                         /* If we got a zero DMA address(can happen on
 570                          * certain platforms like PPC), reallocate.
 571                          * Store virtual address of page we don't want,
 572                          * to be freed later.
 573                          */
 574                         if (!tmp_p) {
 575                                 mac_control->zerodma_virt_addr = tmp_v;
 576                                 DBG_PRINT(INIT_DBG,
 577                                 "%s: Zero DMA address for TxDL. ", dev->name);
 578                                 DBG_PRINT(INIT_DBG,
 579                                 "Virtual address %p\n", tmp_v);
 580                                 tmp_v = pci_alloc_consistent(nic->pdev,
 581                                                      PAGE_SIZE, &tmp_p);
 582                                 if (!tmp_v) {
 583                                         DBG_PRINT(INFO_DBG,
 584                                           "pci_alloc_consistent ");
 585                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 586                                         return -ENOMEM;
 587                                 }
 588                                 mem_allocated += PAGE_SIZE;
 589                         }
 590                         while (k < lst_per_page) {
 591                                 int l = (j * lst_per_page) + k;
 592                                 if (l == config->tx_cfg[i].fifo_len)
 593                                         break;
 594                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 595                                     tmp_v + (k * lst_size);
 596                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 597                                     tmp_p + (k * lst_size);
 598                                 k++;
 599                         }
 600                 }
 601         }
 602
 603         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 604         if (!nic->ufo_in_band_v)
 605                 return -ENOMEM;
 606          mem_allocated += (size * sizeof(u64));
 607
 608         /* Allocation and initialization of RXDs in Rings */
 609         size = 0;
 610         for (i = 0; i < config->rx_ring_num; i++) {
 611                 if (config->rx_cfg[i].num_rxd %
 612                     (rxd_count[nic->rxd_mode] + 1)) {
 613                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 614                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 615                                   i);
 616                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 617                         return FAILURE;
 618                 }
 619                 size += config->rx_cfg[i].num_rxd;
 620                 mac_control->rings[i].block_count =
 621                         config->rx_cfg[i].num_rxd /
 622                         (rxd_count[nic->rxd_mode] + 1 );
 623                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 624                         mac_control->rings[i].block_count;
 625         }
 626         if (nic->rxd_mode == RXD_MODE_1)
 627                 size = (size * (sizeof(struct RxD1)));
 628         else
 629                 size = (size * (sizeof(struct RxD3)));
 630
 631         for (i = 0; i < config->rx_ring_num; i++) {
 632                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 633                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 634                 mac_control->rings[i].rx_curr_get_info.ring_len =
 635                     config->rx_cfg[i].num_rxd - 1;
 636                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 637                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 638                 mac_control->rings[i].rx_curr_put_info.ring_len =
 639                     config->rx_cfg[i].num_rxd - 1;
 640                 mac_control->rings[i].nic = nic;
 641                 mac_control->rings[i].ring_no = i;
 642
 643                 blk_cnt = config->rx_cfg[i].num_rxd /
 644                                 (rxd_count[nic->rxd_mode] + 1);
 645                 /*  Allocating all the Rx blocks */
 646                 for (j = 0; j < blk_cnt; j++) {
 647                         struct rx_block_info *rx_blocks;
 648                         int l;
 649
 650                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 651                         size = SIZE_OF_BLOCK; //size is always page size
 652                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 653                                                           &tmp_p_addr);
 654                         if (tmp_v_addr == NULL) {
 655                                 /*
 656                                  * In case of failure, free_shared_mem()
 657                                  * is called, which should free any
 658                                  * memory that was alloced till the
 659                                  * failure happened.
 660                                  */
 661                                 rx_blocks->block_virt_addr = tmp_v_addr;
 662                                 return -ENOMEM;
 663                         }
 664                         mem_allocated += size;
 665                         memset(tmp_v_addr, 0, size);
 666                         rx_blocks->block_virt_addr = tmp_v_addr;
 667                         rx_blocks->block_dma_addr = tmp_p_addr;
 668                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
 669                                                   rxd_count[nic->rxd_mode],
 670                                                   GFP_KERNEL);
 671                         if (!rx_blocks->rxds)
 672                                 return -ENOMEM;
 673                         mem_allocated +=
 674                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 675                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 676                                 rx_blocks->rxds[l].virt_addr =
 677                                         rx_blocks->block_virt_addr +
 678                                         (rxd_size[nic->rxd_mode] * l);
 679                                 rx_blocks->rxds[l].dma_addr =
 680                                         rx_blocks->block_dma_addr +
 681                                         (rxd_size[nic->rxd_mode] * l);
 682                         }
 683                 }
 684                 /* Interlinking all Rx Blocks */
 685                 for (j = 0; j < blk_cnt; j++) {
 686                         tmp_v_addr =
 687                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 688                         tmp_v_addr_next =
 689                                 mac_control->rings[i].rx_blocks[(j + 1) %
 690                                               blk_cnt].block_virt_addr;
 691                         tmp_p_addr =
 692                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 693                         tmp_p_addr_next =
 694                                 mac_control->rings[i].rx_blocks[(j + 1) %
 695                                               blk_cnt].block_dma_addr;
 696
 697                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
 698                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 699                             (unsigned long) tmp_v_addr_next;
 700                         pre_rxd_blk->pNext_RxD_Blk_physical =
 701                             (u64) tmp_p_addr_next;
 702                 }
 703         }
 704         if (nic->rxd_mode == RXD_MODE_3B) {
 705                 /*
 706                  * Allocation of Storages for buffer addresses in 2BUFF mode
 707                  * and the buffers as well.
 708                  */
 709                 for (i = 0; i < config->rx_ring_num; i++) {
 710                         blk_cnt = config->rx_cfg[i].num_rxd /
 711                            (rxd_count[nic->rxd_mode]+ 1);
 712                         mac_control->rings[i].ba =
 713                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
 714                                      GFP_KERNEL);
 715                         if (!mac_control->rings[i].ba)
 716                                 return -ENOMEM;
 717                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
 718                         for (j = 0; j < blk_cnt; j++) {
 719                                 int k = 0;
 720                                 mac_control->rings[i].ba[j] =
 721                                         kmalloc((sizeof(struct buffAdd) *
 722                                                 (rxd_count[nic->rxd_mode] + 1)),
 723                                                 GFP_KERNEL);
 724                                 if (!mac_control->rings[i].ba[j])
 725                                         return -ENOMEM;
 726                                 mem_allocated += (sizeof(struct buffAdd) *  \
 727                                         (rxd_count[nic->rxd_mode] + 1));
 728                                 while (k != rxd_count[nic->rxd_mode]) {
 729                                         ba = &mac_control->rings[i].ba[j][k];
 730
 731                                         ba->ba_0_org = (void *) kmalloc
 732                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 733                                         if (!ba->ba_0_org)
 734                                                 return -ENOMEM;
 735                                         mem_allocated +=
 736                                                 (BUF0_LEN + ALIGN_SIZE);
 737                                         tmp = (unsigned long)ba->ba_0_org;
 738                                         tmp += ALIGN_SIZE;
 739                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 740                                         ba->ba_0 = (void *) tmp;
 741
 742                                         ba->ba_1_org = (void *) kmalloc
 743                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 744                                         if (!ba->ba_1_org)
 745                                                 return -ENOMEM;
 746                                         mem_allocated
 747                                                 += (BUF1_LEN + ALIGN_SIZE);
 748                                         tmp = (unsigned long) ba->ba_1_org;
 749                                         tmp += ALIGN_SIZE;
 750                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 751                                         ba->ba_1 = (void *) tmp;
 752                                         k++;
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         /* Allocation and initialization of Statistics block */
 759         size = sizeof(struct stat_block);
 760         mac_control->stats_mem = pci_alloc_consistent
 761             (nic->pdev, size, &mac_control->stats_mem_phy);
 762
 763         if (!mac_control->stats_mem) {
 764                 /*
 765                  * In case of failure, free_shared_mem() is called, which
 766                  * should free any memory that was alloced till the
 767                  * failure happened.
 768                  */
 769                 return -ENOMEM;
 770         }
 771         mem_allocated += size;
 772         mac_control->stats_mem_sz = size;
 773
 774         tmp_v_addr = mac_control->stats_mem;
 775         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
 776         memset(tmp_v_addr, 0, size);
 777         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 778                   (unsigned long long) tmp_p_addr);
 779         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 780         return SUCCESS;
 781 }
 782
 783 /**
 784  * free_shared_mem - Free the allocated Memory
 785  * @nic:  Device private variable.
 786  * Description: This function is to free all memory locations allocated by
 787  * the init_shared_mem() function and return it to the kernel.
 788  */
 789
 790 static void free_shared_mem(struct s2io_nic *nic)
 791 {
 792         int i, j, blk_cnt, size;
 793         u32 ufo_size = 0;
 794         void *tmp_v_addr;
 795         dma_addr_t tmp_p_addr;
 796         struct mac_info *mac_control;
 797         struct config_param *config;
 798         int lst_size, lst_per_page;
 799         struct net_device *dev;
 800         int page_num = 0;
 801
 802         if (!nic)
 803                 return;
 804
 805         dev = nic->dev;
 806
 807         mac_control = &nic->mac_control;
 808         config = &nic->config;
 809
 810         lst_size = (sizeof(struct TxD) * config->max_txds);
 811         lst_per_page = PAGE_SIZE / lst_size;
 812
 813         for (i = 0; i < config->tx_fifo_num; i++) {
 814                 ufo_size += config->tx_cfg[i].fifo_len;
 815                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 816                                                         lst_per_page);
 817                 for (j = 0; j < page_num; j++) {
 818                         int mem_blks = (j * lst_per_page);
 819                         if (!mac_control->fifos[i].list_info)
 820                                 return;
 821                         if (!mac_control->fifos[i].list_info[mem_blks].
 822                                  list_virt_addr)
 823                                 break;
 824                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 825                                             mac_control->fifos[i].
 826                                             list_info[mem_blks].
 827                                             list_virt_addr,
 828                                             mac_control->fifos[i].
 829                                             list_info[mem_blks].
 830                                             list_phy_addr);
 831                         nic->mac_control.stats_info->sw_stat.mem_freed
 832                                                 += PAGE_SIZE;
 833                 }
 834                 /* If we got a zero DMA address during allocation,
 835                  * free the page now
 836                  */
 837                 if (mac_control->zerodma_virt_addr) {
 838                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 839                                             mac_control->zerodma_virt_addr,
 840                                             (dma_addr_t)0);
 841                         DBG_PRINT(INIT_DBG,
 842                                 "%s: Freeing TxDL with zero DMA addr. ",
 843                                 dev->name);
 844                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 845                                 mac_control->zerodma_virt_addr);
 846                         nic->mac_control.stats_info->sw_stat.mem_freed
 847                                                 += PAGE_SIZE;
 848                 }
 849                 kfree(mac_control->fifos[i].list_info);
 850                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 851                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
 852         }
 853
 854         size = SIZE_OF_BLOCK;
 855         for (i = 0; i < config->rx_ring_num; i++) {
 856                 blk_cnt = mac_control->rings[i].block_count;
 857                 for (j = 0; j < blk_cnt; j++) {
 858                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 859                                 block_virt_addr;
 860                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 861                                 block_dma_addr;
 862                         if (tmp_v_addr == NULL)
 863                                 break;
 864                         pci_free_consistent(nic->pdev, size,
 865                                             tmp_v_addr, tmp_p_addr);
 866                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
 867                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 868                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 869                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 870                 }
 871         }
 872
 873         if (nic->rxd_mode == RXD_MODE_3B) {
 874                 /* Freeing buffer storage addresses in 2BUFF mode. */
 875                 for (i = 0; i < config->rx_ring_num; i++) {
 876                         blk_cnt = config->rx_cfg[i].num_rxd /
 877                             (rxd_count[nic->rxd_mode] + 1);
 878                         for (j = 0; j < blk_cnt; j++) {
 879                                 int k = 0;
 880                                 if (!mac_control->rings[i].ba[j])
 881                                         continue;
 882                                 while (k != rxd_count[nic->rxd_mode]) {
 883                                         struct buffAdd *ba =
 884                                                 &mac_control->rings[i].ba[j][k];
 885                                         kfree(ba->ba_0_org);
 886                                         nic->mac_control.stats_info->sw_stat.\
 887                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
 888                                         kfree(ba->ba_1_org);
 889                                         nic->mac_control.stats_info->sw_stat.\
 890                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
 891                                         k++;
 892                                 }
 893                                 kfree(mac_control->rings[i].ba[j]);
 894                                 nic->mac_control.stats_info->sw_stat.mem_freed                          += (sizeof(struct buffAdd) *
 895                                 (rxd_count[nic->rxd_mode] + 1));
 896                         }
 897                         kfree(mac_control->rings[i].ba);
 898                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 899                         (sizeof(struct buffAdd *) * blk_cnt);
 900                 }
 901         }
 902
 903         if (mac_control->stats_mem) {
 904                 pci_free_consistent(nic->pdev,
 905                                     mac_control->stats_mem_sz,
 906                                     mac_control->stats_mem,
 907                                     mac_control->stats_mem_phy);
 908                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 909                         mac_control->stats_mem_sz;
 910         }
 911         if (nic->ufo_in_band_v) {
 912                 kfree(nic->ufo_in_band_v);
 913                 nic->mac_control.stats_info->sw_stat.mem_freed
 914                         += (ufo_size * sizeof(u64));
 915         }
 916 }
 917
 918 /**
 919  * s2io_verify_pci_mode -
 920  */
 921
 922 static int s2io_verify_pci_mode(struct s2io_nic *nic)
 923 {
 924         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 925         register u64 val64 = 0;
 926         int     mode;
 927
 928         val64 = readq(&bar0->pci_mode);
 929         mode = (u8)GET_PCI_MODE(val64);
 930
 931         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 932                 return -1;      /* Unknown PCI mode */
 933         return mode;
 934 }
 935
 936 #define NEC_VENID   0x1033
 937 #define NEC_DEVID   0x0125
 938 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 939 {
 940         struct pci_dev *tdev = NULL;
 941         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 942                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
 943                         if (tdev->bus == s2io_pdev->bus->parent)
 944                                 pci_dev_put(tdev);
 945                                 return 1;
 946                 }
 947         }
 948         return 0;
 949 }
 950
 951 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 952 /**
 953  * s2io_print_pci_mode -
 954  */
 955 static int s2io_print_pci_mode(struct s2io_nic *nic)
 956 {
 957         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 958         register u64 val64 = 0;
 959         int     mode;
 960         struct config_param *config = &nic->config;
 961
 962         val64 = readq(&bar0->pci_mode);
 963         mode = (u8)GET_PCI_MODE(val64);
 964
 965         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 966                 return -1;      /* Unknown PCI mode */
 967
 968         config->bus_speed = bus_speed[mode];
 969
 970         if (s2io_on_nec_bridge(nic->pdev)) {
 971                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 972                                                         nic->dev->name);
 973                 return mode;
 974         }
 975
 976         if (val64 & PCI_MODE_32_BITS) {
 977                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 978         } else {
 979                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 980         }
 981
 982         switch(mode) {
 983                 case PCI_MODE_PCI_33:
 984                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 985                         break;
 986                 case PCI_MODE_PCI_66:
 987                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 988                         break;
 989                 case PCI_MODE_PCIX_M1_66:
 990                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 991                         break;
 992                 case PCI_MODE_PCIX_M1_100:
 993                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 994                         break;
 995                 case PCI_MODE_PCIX_M1_133:
 996                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 997                         break;
 998                 case PCI_MODE_PCIX_M2_66:
 999                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1000                         break;
1001                 case PCI_MODE_PCIX_M2_100:
1002                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1003                         break;
1004                 case PCI_MODE_PCIX_M2_133:
1005                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1006                         break;
1007                 default:
1008                         return -1;      /* Unsupported bus speed */
1009         }
1010
1011         return mode;
1012 }
1013
1014 /**
1015  *  init_nic - Initialization of hardware
1016  *  @nic: device peivate variable
1017  *  Description: The function sequentially configures every block
1018  *  of the H/W from their reset values.
1019  *  Return Value:  SUCCESS on success and
1020  *  '-1' on failure (endian settings incorrect).
1021  */
1022
1023 static int init_nic(struct s2io_nic *nic)
1024 {
1025         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1026         struct net_device *dev = nic->dev;
1027         register u64 val64 = 0;
1028         void __iomem *add;
1029         u32 time;
1030         int i, j;
1031         struct mac_info *mac_control;
1032         struct config_param *config;
1033         int dtx_cnt = 0;
1034         unsigned long long mem_share;
1035         int mem_size;
1036
1037         mac_control = &nic->mac_control;
1038         config = &nic->config;
1039
1040         /* to set the swapper controle on the card */
1041         if(s2io_set_swapper(nic)) {
1042                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1043                 return -1;
1044         }
1045
1046         /*
1047          * Herc requires EOI to be removed from reset before XGXS, so..
1048          */
1049         if (nic->device_type & XFRAME_II_DEVICE) {
1050                 val64 = 0xA500000000ULL;
1051                 writeq(val64, &bar0->sw_reset);
1052                 msleep(500);
1053                 val64 = readq(&bar0->sw_reset);
1054         }
1055
1056         /* Remove XGXS from reset state */
1057         val64 = 0;
1058         writeq(val64, &bar0->sw_reset);
1059         msleep(500);
1060         val64 = readq(&bar0->sw_reset);
1061
1062         /*  Enable Receiving broadcasts */
1063         add = &bar0->mac_cfg;
1064         val64 = readq(&bar0->mac_cfg);
1065         val64 |= MAC_RMAC_BCAST_ENABLE;
1066         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1067         writel((u32) val64, add);
1068         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1069         writel((u32) (val64 >> 32), (add + 4));
1070
1071         /* Read registers in all blocks */
1072         val64 = readq(&bar0->mac_int_mask);
1073         val64 = readq(&bar0->mc_int_mask);
1074         val64 = readq(&bar0->xgxs_int_mask);
1075
1076         /*  Set MTU */
1077         val64 = dev->mtu;
1078         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1079
1080         if (nic->device_type & XFRAME_II_DEVICE) {
1081                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1082                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1083                                           &bar0->dtx_control, UF);
1084                         if (dtx_cnt & 0x1)
1085                                 msleep(1); /* Necessary!! */
1086                         dtx_cnt++;
1087                 }
1088         } else {
1089                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1090                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1091                                           &bar0->dtx_control, UF);
1092                         val64 = readq(&bar0->dtx_control);
1093                         dtx_cnt++;
1094                 }
1095         }
1096
1097         /*  Tx DMA Initialization */
1098         val64 = 0;
1099         writeq(val64, &bar0->tx_fifo_partition_0);
1100         writeq(val64, &bar0->tx_fifo_partition_1);
1101         writeq(val64, &bar0->tx_fifo_partition_2);
1102         writeq(val64, &bar0->tx_fifo_partition_3);
1103
1104
1105         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1106                 val64 |=
1107                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1108                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1109                                     ((i * 32) + 5), 3);
1110
1111                 if (i == (config->tx_fifo_num - 1)) {
1112                         if (i % 2 == 0)
1113                                 i++;
1114                 }
1115
1116                 switch (i) {
1117                 case 1:
1118                         writeq(val64, &bar0->tx_fifo_partition_0);
1119                         val64 = 0;
1120                         break;
1121                 case 3:
1122                         writeq(val64, &bar0->tx_fifo_partition_1);
1123                         val64 = 0;
1124                         break;
1125                 case 5:
1126                         writeq(val64, &bar0->tx_fifo_partition_2);
1127                         val64 = 0;
1128                         break;
1129                 case 7:
1130                         writeq(val64, &bar0->tx_fifo_partition_3);
1131                         break;
1132                 }
1133         }
1134
1135         /*
1136          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1137          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1138          */
1139         if ((nic->device_type == XFRAME_I_DEVICE) &&
1140                 (nic->pdev->revision < 4))
1141                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1142
1143         val64 = readq(&bar0->tx_fifo_partition_0);
1144         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1145                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1146
1147         /*
1148          * Initialization of Tx_PA_CONFIG register to ignore packet
1149          * integrity checking.
1150          */
1151         val64 = readq(&bar0->tx_pa_cfg);
1152         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1153             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1154         writeq(val64, &bar0->tx_pa_cfg);
1155
1156         /* Rx DMA intialization. */
1157         val64 = 0;
1158         for (i = 0; i < config->rx_ring_num; i++) {
1159                 val64 |=
1160                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1161                          3);
1162         }
1163         writeq(val64, &bar0->rx_queue_priority);
1164
1165         /*
1166          * Allocating equal share of memory to all the
1167          * configured Rings.
1168          */
1169         val64 = 0;
1170         if (nic->device_type & XFRAME_II_DEVICE)
1171                 mem_size = 32;
1172         else
1173                 mem_size = 64;
1174
1175         for (i = 0; i < config->rx_ring_num; i++) {
1176                 switch (i) {
1177                 case 0:
1178                         mem_share = (mem_size / config->rx_ring_num +
1179                                      mem_size % config->rx_ring_num);
1180                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1181                         continue;
1182                 case 1:
1183                         mem_share = (mem_size / config->rx_ring_num);
1184                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1185                         continue;
1186                 case 2:
1187                         mem_share = (mem_size / config->rx_ring_num);
1188                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1189                         continue;
1190                 case 3:
1191                         mem_share = (mem_size / config->rx_ring_num);
1192                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1193                         continue;
1194                 case 4:
1195                         mem_share = (mem_size / config->rx_ring_num);
1196                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1197                         continue;
1198                 case 5:
1199                         mem_share = (mem_size / config->rx_ring_num);
1200                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1201                         continue;
1202                 case 6:
1203                         mem_share = (mem_size / config->rx_ring_num);
1204                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1205                         continue;
1206                 case 7:
1207                         mem_share = (mem_size / config->rx_ring_num);
1208                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1209                         continue;
1210                 }
1211         }
1212         writeq(val64, &bar0->rx_queue_cfg);
1213
1214         /*
1215          * Filling Tx round robin registers
1216          * as per the number of FIFOs
1217          */
1218         switch (config->tx_fifo_num) {
1219         case 1:
1220                 val64 = 0x0000000000000000ULL;
1221                 writeq(val64, &bar0->tx_w_round_robin_0);
1222                 writeq(val64, &bar0->tx_w_round_robin_1);
1223                 writeq(val64, &bar0->tx_w_round_robin_2);
1224                 writeq(val64, &bar0->tx_w_round_robin_3);
1225                 writeq(val64, &bar0->tx_w_round_robin_4);
1226                 break;
1227         case 2:
1228                 val64 = 0x0000010000010000ULL;
1229                 writeq(val64, &bar0->tx_w_round_robin_0);
1230                 val64 = 0x0100000100000100ULL;
1231                 writeq(val64, &bar0->tx_w_round_robin_1);
1232                 val64 = 0x0001000001000001ULL;
1233                 writeq(val64, &bar0->tx_w_round_robin_2);
1234                 val64 = 0x0000010000010000ULL;
1235                 writeq(val64, &bar0->tx_w_round_robin_3);
1236                 val64 = 0x0100000000000000ULL;
1237                 writeq(val64, &bar0->tx_w_round_robin_4);
1238                 break;
1239         case 3:
1240                 val64 = 0x0001000102000001ULL;
1241                 writeq(val64, &bar0->tx_w_round_robin_0);
1242                 val64 = 0x0001020000010001ULL;
1243                 writeq(val64, &bar0->tx_w_round_robin_1);
1244                 val64 = 0x0200000100010200ULL;
1245                 writeq(val64, &bar0->tx_w_round_robin_2);
1246                 val64 = 0x0001000102000001ULL;
1247                 writeq(val64, &bar0->tx_w_round_robin_3);
1248                 val64 = 0x0001020000000000ULL;
1249                 writeq(val64, &bar0->tx_w_round_robin_4);
1250                 break;
1251         case 4:
1252                 val64 = 0x0001020300010200ULL;
1253                 writeq(val64, &bar0->tx_w_round_robin_0);
1254                 val64 = 0x0100000102030001ULL;
1255                 writeq(val64, &bar0->tx_w_round_robin_1);
1256                 val64 = 0x0200010000010203ULL;
1257                 writeq(val64, &bar0->tx_w_round_robin_2);
1258                 val64 = 0x0001020001000001ULL;
1259                 writeq(val64, &bar0->tx_w_round_robin_3);
1260                 val64 = 0x0203000100000000ULL;
1261                 writeq(val64, &bar0->tx_w_round_robin_4);
1262                 break;
1263         case 5:
1264                 val64 = 0x0001000203000102ULL;
1265                 writeq(val64, &bar0->tx_w_round_robin_0);
1266                 val64 = 0x0001020001030004ULL;
1267                 writeq(val64, &bar0->tx_w_round_robin_1);
1268                 val64 = 0x0001000203000102ULL;
1269                 writeq(val64, &bar0->tx_w_round_robin_2);
1270                 val64 = 0x0001020001030004ULL;
1271                 writeq(val64, &bar0->tx_w_round_robin_3);
1272                 val64 = 0x0001000000000000ULL;
1273                 writeq(val64, &bar0->tx_w_round_robin_4);
1274                 break;
1275         case 6:
1276                 val64 = 0x0001020304000102ULL;
1277                 writeq(val64, &bar0->tx_w_round_robin_0);
1278                 val64 = 0x0304050001020001ULL;
1279                 writeq(val64, &bar0->tx_w_round_robin_1);
1280                 val64 = 0x0203000100000102ULL;
1281                 writeq(val64, &bar0->tx_w_round_robin_2);
1282                 val64 = 0x0304000102030405ULL;
1283                 writeq(val64, &bar0->tx_w_round_robin_3);
1284                 val64 = 0x0001000200000000ULL;
1285                 writeq(val64, &bar0->tx_w_round_robin_4);
1286                 break;
1287         case 7:
1288                 val64 = 0x0001020001020300ULL;
1289                 writeq(val64, &bar0->tx_w_round_robin_0);
1290                 val64 = 0x0102030400010203ULL;
1291                 writeq(val64, &bar0->tx_w_round_robin_1);
1292                 val64 = 0x0405060001020001ULL;
1293                 writeq(val64, &bar0->tx_w_round_robin_2);
1294                 val64 = 0x0304050000010200ULL;
1295                 writeq(val64, &bar0->tx_w_round_robin_3);
1296                 val64 = 0x0102030000000000ULL;
1297                 writeq(val64, &bar0->tx_w_round_robin_4);
1298                 break;
1299         case 8:
1300                 val64 = 0x0001020300040105ULL;
1301                 writeq(val64, &bar0->tx_w_round_robin_0);
1302                 val64 = 0x0200030106000204ULL;
1303                 writeq(val64, &bar0->tx_w_round_robin_1);
1304                 val64 = 0x0103000502010007ULL;
1305                 writeq(val64, &bar0->tx_w_round_robin_2);
1306                 val64 = 0x0304010002060500ULL;
1307                 writeq(val64, &bar0->tx_w_round_robin_3);
1308                 val64 = 0x0103020400000000ULL;
1309                 writeq(val64, &bar0->tx_w_round_robin_4);
1310                 break;
1311         }
1312
1313         /* Enable all configured Tx FIFO partitions */
1314         val64 = readq(&bar0->tx_fifo_partition_0);
1315         val64 |= (TX_FIFO_PARTITION_EN);
1316         writeq(val64, &bar0->tx_fifo_partition_0);
1317
1318         /* Filling the Rx round robin registers as per the
1319          * number of Rings and steering based on QoS.
1320          */
1321         switch (config->rx_ring_num) {
1322         case 1:
1323                 val64 = 0x8080808080808080ULL;
1324                 writeq(val64, &bar0->rts_qos_steering);
1325                 break;
1326         case 2:
1327                 val64 = 0x0000010000010000ULL;
1328                 writeq(val64, &bar0->rx_w_round_robin_0);
1329                 val64 = 0x0100000100000100ULL;
1330                 writeq(val64, &bar0->rx_w_round_robin_1);
1331                 val64 = 0x0001000001000001ULL;
1332                 writeq(val64, &bar0->rx_w_round_robin_2);
1333                 val64 = 0x0000010000010000ULL;
1334                 writeq(val64, &bar0->rx_w_round_robin_3);
1335                 val64 = 0x0100000000000000ULL;
1336                 writeq(val64, &bar0->rx_w_round_robin_4);
1337
1338                 val64 = 0x8080808040404040ULL;
1339                 writeq(val64, &bar0->rts_qos_steering);
1340                 break;
1341         case 3:
1342                 val64 = 0x0001000102000001ULL;
1343                 writeq(val64, &bar0->rx_w_round_robin_0);
1344                 val64 = 0x0001020000010001ULL;
1345                 writeq(val64, &bar0->rx_w_round_robin_1);
1346                 val64 = 0x0200000100010200ULL;
1347                 writeq(val64, &bar0->rx_w_round_robin_2);
1348                 val64 = 0x0001000102000001ULL;
1349                 writeq(val64, &bar0->rx_w_round_robin_3);
1350                 val64 = 0x0001020000000000ULL;
1351                 writeq(val64, &bar0->rx_w_round_robin_4);
1352
1353                 val64 = 0x8080804040402020ULL;
1354                 writeq(val64, &bar0->rts_qos_steering);
1355                 break;
1356         case 4:
1357                 val64 = 0x0001020300010200ULL;
1358                 writeq(val64, &bar0->rx_w_round_robin_0);
1359                 val64 = 0x0100000102030001ULL;
1360                 writeq(val64, &bar0->rx_w_round_robin_1);
1361                 val64 = 0x0200010000010203ULL;
1362                 writeq(val64, &bar0->rx_w_round_robin_2);
1363                 val64 = 0x0001020001000001ULL;
1364                 writeq(val64, &bar0->rx_w_round_robin_3);
1365                 val64 = 0x0203000100000000ULL;
1366                 writeq(val64, &bar0->rx_w_round_robin_4);
1367
1368                 val64 = 0x8080404020201010ULL;
1369                 writeq(val64, &bar0->rts_qos_steering);
1370                 break;
1371         case 5:
1372                 val64 = 0x0001000203000102ULL;
1373                 writeq(val64, &bar0->rx_w_round_robin_0);
1374                 val64 = 0x0001020001030004ULL;
1375                 writeq(val64, &bar0->rx_w_round_robin_1);
1376                 val64 = 0x0001000203000102ULL;
1377                 writeq(val64, &bar0->rx_w_round_robin_2);
1378                 val64 = 0x0001020001030004ULL;
1379                 writeq(val64, &bar0->rx_w_round_robin_3);
1380                 val64 = 0x0001000000000000ULL;
1381                 writeq(val64, &bar0->rx_w_round_robin_4);
1382
1383                 val64 = 0x8080404020201008ULL;
1384                 writeq(val64, &bar0->rts_qos_steering);
1385                 break;
1386         case 6:
1387                 val64 = 0x0001020304000102ULL;
1388                 writeq(val64, &bar0->rx_w_round_robin_0);
1389                 val64 = 0x0304050001020001ULL;
1390                 writeq(val64, &bar0->rx_w_round_robin_1);
1391                 val64 = 0x0203000100000102ULL;
1392                 writeq(val64, &bar0->rx_w_round_robin_2);
1393                 val64 = 0x0304000102030405ULL;
1394                 writeq(val64, &bar0->rx_w_round_robin_3);
1395                 val64 = 0x0001000200000000ULL;
1396                 writeq(val64, &bar0->rx_w_round_robin_4);
1397
1398                 val64 = 0x8080404020100804ULL;
1399                 writeq(val64, &bar0->rts_qos_steering);
1400                 break;
1401         case 7:
1402                 val64 = 0x0001020001020300ULL;
1403                 writeq(val64, &bar0->rx_w_round_robin_0);
1404                 val64 = 0x0102030400010203ULL;
1405                 writeq(val64, &bar0->rx_w_round_robin_1);
1406                 val64 = 0x0405060001020001ULL;
1407                 writeq(val64, &bar0->rx_w_round_robin_2);
1408                 val64 = 0x0304050000010200ULL;
1409                 writeq(val64, &bar0->rx_w_round_robin_3);
1410                 val64 = 0x0102030000000000ULL;
1411                 writeq(val64, &bar0->rx_w_round_robin_4);
1412
1413                 val64 = 0x8080402010080402ULL;
1414                 writeq(val64, &bar0->rts_qos_steering);
1415                 break;
1416         case 8:
1417                 val64 = 0x0001020300040105ULL;
1418                 writeq(val64, &bar0->rx_w_round_robin_0);
1419                 val64 = 0x0200030106000204ULL;
1420                 writeq(val64, &bar0->rx_w_round_robin_1);
1421                 val64 = 0x0103000502010007ULL;
1422                 writeq(val64, &bar0->rx_w_round_robin_2);
1423                 val64 = 0x0304010002060500ULL;
1424                 writeq(val64, &bar0->rx_w_round_robin_3);
1425                 val64 = 0x0103020400000000ULL;
1426                 writeq(val64, &bar0->rx_w_round_robin_4);
1427
1428                 val64 = 0x8040201008040201ULL;
1429                 writeq(val64, &bar0->rts_qos_steering);
1430                 break;
1431         }
1432
1433         /* UDP Fix */
1434         val64 = 0;
1435         for (i = 0; i < 8; i++)
1436                 writeq(val64, &bar0->rts_frm_len_n[i]);
1437
1438         /* Set the default rts frame length for the rings configured */
1439         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1440         for (i = 0 ; i < config->rx_ring_num ; i++)
1441                 writeq(val64, &bar0->rts_frm_len_n[i]);
1442
1443         /* Set the frame length for the configured rings
1444          * desired by the user
1445          */
1446         for (i = 0; i < config->rx_ring_num; i++) {
1447                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1448                  * specified frame length steering.
1449                  * If the user provides the frame length then program
1450                  * the rts_frm_len register for those values or else
1451                  * leave it as it is.
1452                  */
1453                 if (rts_frm_len[i] != 0) {
1454                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1455                                 &bar0->rts_frm_len_n[i]);
1456                 }
1457         }
1458
1459         /* Disable differentiated services steering logic */
1460         for (i = 0; i < 64; i++) {
1461                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1462                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1463                                 dev->name);
1464                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1465                         return FAILURE;
1466                 }
1467         }
1468
1469         /* Program statistics memory */
1470         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1471
1472         if (nic->device_type == XFRAME_II_DEVICE) {
1473                 val64 = STAT_BC(0x320);
1474                 writeq(val64, &bar0->stat_byte_cnt);
1475         }
1476
1477         /*
1478          * Initializing the sampling rate for the device to calculate the
1479          * bandwidth utilization.
1480          */
1481         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1482             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1483         writeq(val64, &bar0->mac_link_util);
1484
1485
1486         /*
1487          * Initializing the Transmit and Receive Traffic Interrupt
1488          * Scheme.
1489          */
1490         /*
1491          * TTI Initialization. Default Tx timer gets us about
1492          * 250 interrupts per sec. Continuous interrupts are enabled
1493          * by default.
1494          */
1495         if (nic->device_type == XFRAME_II_DEVICE) {
1496                 int count = (nic->config.bus_speed * 125)/2;
1497                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1498         } else {
1499
1500                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1501         }
1502         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1503             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1504             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1505                 if (use_continuous_tx_intrs)
1506                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1507         writeq(val64, &bar0->tti_data1_mem);
1508
1509         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1510             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1511             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1512         writeq(val64, &bar0->tti_data2_mem);
1513
1514         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1515         writeq(val64, &bar0->tti_command_mem);
1516
1517         /*
1518          * Once the operation completes, the Strobe bit of the command
1519          * register will be reset. We poll for this particular condition
1520          * We wait for a maximum of 500ms for the operation to complete,
1521          * if it's not complete by then we return error.
1522          */
1523         time = 0;
1524         while (TRUE) {
1525                 val64 = readq(&bar0->tti_command_mem);
1526                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1527                         break;
1528                 }
1529                 if (time > 10) {
1530                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1531                                   dev->name);
1532                         return -1;
1533                 }
1534                 msleep(50);
1535                 time++;
1536         }
1537
1538         if (nic->config.bimodal) {
1539                 int k = 0;
1540                 for (k = 0; k < config->rx_ring_num; k++) {
1541                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1542                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1543                         writeq(val64, &bar0->tti_command_mem);
1544
1545                 /*
1546                  * Once the operation completes, the Strobe bit of the command
1547                  * register will be reset. We poll for this particular condition
1548                  * We wait for a maximum of 500ms for the operation to complete,
1549                  * if it's not complete by then we return error.
1550                 */
1551                         time = 0;
1552                         while (TRUE) {
1553                                 val64 = readq(&bar0->tti_command_mem);
1554                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1555                                         break;
1556                                 }
1557                                 if (time > 10) {
1558                                         DBG_PRINT(ERR_DBG,
1559                                                 "%s: TTI init Failed\n",
1560                                         dev->name);
1561                                         return -1;
1562                                 }
1563                                 time++;
1564                                 msleep(50);
1565                         }
1566                 }
1567         } else {
1568
1569                 /* RTI Initialization */
1570                 if (nic->device_type == XFRAME_II_DEVICE) {
1571                         /*
1572                          * Programmed to generate Apprx 500 Intrs per
1573                          * second
1574                          */
1575                         int count = (nic->config.bus_speed * 125)/4;
1576                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1577                 } else {
1578                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1579                 }
1580                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1581                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1582                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1583
1584                 writeq(val64, &bar0->rti_data1_mem);
1585
1586                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1587                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1588                 if (nic->intr_type == MSI_X)
1589                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1590                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1591                 else
1592                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1593                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1594                 writeq(val64, &bar0->rti_data2_mem);
1595
1596                 for (i = 0; i < config->rx_ring_num; i++) {
1597                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1598                                         | RTI_CMD_MEM_OFFSET(i);
1599                         writeq(val64, &bar0->rti_command_mem);
1600
1601                         /*
1602                          * Once the operation completes, the Strobe bit of the
1603                          * command register will be reset. We poll for this
1604                          * particular condition. We wait for a maximum of 500ms
1605                          * for the operation to complete, if it's not complete
1606                          * by then we return error.
1607                          */
1608                         time = 0;
1609                         while (TRUE) {
1610                                 val64 = readq(&bar0->rti_command_mem);
1611                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1612                                         break;
1613                                 }
1614                                 if (time > 10) {
1615                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1616                                                   dev->name);
1617                                         return -1;
1618                                 }
1619                                 time++;
1620                                 msleep(50);
1621                         }
1622                 }
1623         }
1624
1625         /*
1626          * Initializing proper values as Pause threshold into all
1627          * the 8 Queues on Rx side.
1628          */
1629         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1630         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1631
1632         /* Disable RMAC PAD STRIPPING */
1633         add = &bar0->mac_cfg;
1634         val64 = readq(&bar0->mac_cfg);
1635         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1636         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1637         writel((u32) (val64), add);
1638         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1639         writel((u32) (val64 >> 32), (add + 4));
1640         val64 = readq(&bar0->mac_cfg);
1641
1642         /* Enable FCS stripping by adapter */
1643         add = &bar0->mac_cfg;
1644         val64 = readq(&bar0->mac_cfg);
1645         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1646         if (nic->device_type == XFRAME_II_DEVICE)
1647                 writeq(val64, &bar0->mac_cfg);
1648         else {
1649                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1650                 writel((u32) (val64), add);
1651                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1652                 writel((u32) (val64 >> 32), (add + 4));
1653         }
1654
1655         /*
1656          * Set the time value to be inserted in the pause frame
1657          * generated by xena.
1658          */
1659         val64 = readq(&bar0->rmac_pause_cfg);
1660         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1661         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1662         writeq(val64, &bar0->rmac_pause_cfg);
1663
1664         /*
1665          * Set the Threshold Limit for Generating the pause frame
1666          * If the amount of data in any Queue exceeds ratio of
1667          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1668          * pause frame is generated
1669          */
1670         val64 = 0;
1671         for (i = 0; i < 4; i++) {
1672                 val64 |=
1673                     (((u64) 0xFF00 | nic->mac_control.
1674                       mc_pause_threshold_q0q3)
1675                      << (i * 2 * 8));
1676         }
1677         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1678
1679         val64 = 0;
1680         for (i = 0; i < 4; i++) {
1681                 val64 |=
1682                     (((u64) 0xFF00 | nic->mac_control.
1683                       mc_pause_threshold_q4q7)
1684                      << (i * 2 * 8));
1685         }
1686         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1687
1688         /*
1689          * TxDMA will stop Read request if the number of read split has
1690          * exceeded the limit pointed by shared_splits
1691          */
1692         val64 = readq(&bar0->pic_control);
1693         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1694         writeq(val64, &bar0->pic_control);
1695
1696         if (nic->config.bus_speed == 266) {
1697                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1698                 writeq(0x0, &bar0->read_retry_delay);
1699                 writeq(0x0, &bar0->write_retry_delay);
1700         }
1701
1702         /*
1703          * Programming the Herc to split every write transaction
1704          * that does not start on an ADB to reduce disconnects.
1705          */
1706         if (nic->device_type == XFRAME_II_DEVICE) {
1707                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1708                         MISC_LINK_STABILITY_PRD(3);
1709                 writeq(val64, &bar0->misc_control);
1710                 val64 = readq(&bar0->pic_control2);
1711                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1712                 writeq(val64, &bar0->pic_control2);
1713         }
1714         if (strstr(nic->product_name, "CX4")) {
1715                 val64 = TMAC_AVG_IPG(0x17);
1716                 writeq(val64, &bar0->tmac_avg_ipg);
1717         }
1718
1719         return SUCCESS;
1720 }
1721 #define LINK_UP_DOWN_INTERRUPT          1
1722 #define MAC_RMAC_ERR_TIMER              2
1723
1724 static int s2io_link_fault_indication(struct s2io_nic *nic)
1725 {
1726         if (nic->intr_type != INTA)
1727                 return MAC_RMAC_ERR_TIMER;
1728         if (nic->device_type == XFRAME_II_DEVICE)
1729                 return LINK_UP_DOWN_INTERRUPT;
1730         else
1731                 return MAC_RMAC_ERR_TIMER;
1732 }
1733
1734 /**
1735  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1736  *  @nic: device private variable,
1737  *  @mask: A mask indicating which Intr block must be modified and,
1738  *  @flag: A flag indicating whether to enable or disable the Intrs.
1739  *  Description: This function will either disable or enable the interrupts
1740  *  depending on the flag argument. The mask argument can be used to
1741  *  enable/disable any Intr block.
1742  *  Return Value: NONE.
1743  */
1744
1745 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1746 {
1747         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1748         register u64 val64 = 0, temp64 = 0;
1749
1750         /*  Top level interrupt classification */
1751         /*  PIC Interrupts */
1752         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1753                 /*  Enable PIC Intrs in the general intr mask register */
1754                 val64 = TXPIC_INT_M;
1755                 if (flag == ENABLE_INTRS) {
1756                         temp64 = readq(&bar0->general_int_mask);
1757                         temp64 &= ~((u64) val64);
1758                         writeq(temp64, &bar0->general_int_mask);
1759                         /*
1760                          * If Hercules adapter enable GPIO otherwise
1761                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1762                          * interrupts for now.
1763                          * TODO
1764                          */
1765                         if (s2io_link_fault_indication(nic) ==
1766                                         LINK_UP_DOWN_INTERRUPT ) {
1767                                 temp64 = readq(&bar0->pic_int_mask);
1768                                 temp64 &= ~((u64) PIC_INT_GPIO);
1769                                 writeq(temp64, &bar0->pic_int_mask);
1770                                 temp64 = readq(&bar0->gpio_int_mask);
1771                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1772                                 writeq(temp64, &bar0->gpio_int_mask);
1773                         } else {
1774                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1775                         }
1776                         /*
1777                          * No MSI Support is available presently, so TTI and
1778                          * RTI interrupts are also disabled.
1779                          */
1780                 } else if (flag == DISABLE_INTRS) {
1781                         /*
1782                          * Disable PIC Intrs in the general
1783                          * intr mask register
1784                          */
1785                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1786                         temp64 = readq(&bar0->general_int_mask);
1787                         val64 |= temp64;
1788                         writeq(val64, &bar0->general_int_mask);
1789                 }
1790         }
1791
1792         /*  MAC Interrupts */
1793         /*  Enabling/Disabling MAC interrupts */
1794         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1795                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1796                 if (flag == ENABLE_INTRS) {
1797                         temp64 = readq(&bar0->general_int_mask);
1798                         temp64 &= ~((u64) val64);
1799                         writeq(temp64, &bar0->general_int_mask);
1800                         /*
1801                          * All MAC block error interrupts are disabled for now
1802                          * TODO
1803                          */
1804                 } else if (flag == DISABLE_INTRS) {
1805                         /*
1806                          * Disable MAC Intrs in the general intr mask register
1807                          */
1808                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1809                         writeq(DISABLE_ALL_INTRS,
1810                                &bar0->mac_rmac_err_mask);
1811
1812                         temp64 = readq(&bar0->general_int_mask);
1813                         val64 |= temp64;
1814                         writeq(val64, &bar0->general_int_mask);
1815                 }
1816         }
1817
1818         /*  Tx traffic interrupts */
1819         if (mask & TX_TRAFFIC_INTR) {
1820                 val64 = TXTRAFFIC_INT_M;
1821                 if (flag == ENABLE_INTRS) {
1822                         temp64 = readq(&bar0->general_int_mask);
1823                         temp64 &= ~((u64) val64);
1824                         writeq(temp64, &bar0->general_int_mask);
1825                         /*
1826                          * Enable all the Tx side interrupts
1827                          * writing 0 Enables all 64 TX interrupt levels
1828                          */
1829                         writeq(0x0, &bar0->tx_traffic_mask);
1830                 } else if (flag == DISABLE_INTRS) {
1831                         /*
1832                          * Disable Tx Traffic Intrs in the general intr mask
1833                          * register.
1834                          */
1835                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1836                         temp64 = readq(&bar0->general_int_mask);
1837                         val64 |= temp64;
1838                         writeq(val64, &bar0->general_int_mask);
1839                 }
1840         }
1841
1842         /*  Rx traffic interrupts */
1843         if (mask & RX_TRAFFIC_INTR) {
1844                 val64 = RXTRAFFIC_INT_M;
1845                 if (flag == ENABLE_INTRS) {
1846                         temp64 = readq(&bar0->general_int_mask);
1847                         temp64 &= ~((u64) val64);
1848                         writeq(temp64, &bar0->general_int_mask);
1849                         /* writing 0 Enables all 8 RX interrupt levels */
1850                         writeq(0x0, &bar0->rx_traffic_mask);
1851                 } else if (flag == DISABLE_INTRS) {
1852                         /*
1853                          * Disable Rx Traffic Intrs in the general intr mask
1854                          * register.
1855                          */
1856                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1857                         temp64 = readq(&bar0->general_int_mask);
1858                         val64 |= temp64;
1859                         writeq(val64, &bar0->general_int_mask);
1860                 }
1861         }
1862 }
1863
1864 /**
1865  *  verify_pcc_quiescent- Checks for PCC quiescent state
1866  *  Return: 1 If PCC is quiescence
1867  *          0 If PCC is not quiescence
1868  */
1869 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
1870 {
1871         int ret = 0, herc;
1872         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1873         u64 val64 = readq(&bar0->adapter_status);
1874
1875         herc = (sp->device_type == XFRAME_II_DEVICE);
1876
1877         if (flag == FALSE) {
1878                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
1879                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
1880                                 ret = 1;
1881                 } else {
1882                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1883                                 ret = 1;
1884                 }
1885         } else {
1886                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
1887                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1888                              ADAPTER_STATUS_RMAC_PCC_IDLE))
1889                                 ret = 1;
1890                 } else {
1891                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1892                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
1893                                 ret = 1;
1894                 }
1895         }
1896
1897         return ret;
1898 }
1899 /**
1900  *  verify_xena_quiescence - Checks whether the H/W is ready
1901  *  Description: Returns whether the H/W is ready to go or not. Depending
1902  *  on whether adapter enable bit was written or not the comparison
1903  *  differs and the calling function passes the input argument flag to
1904  *  indicate this.
1905  *  Return: 1 If xena is quiescence
1906  *          0 If Xena is not quiescence
1907  */
1908
1909 static int verify_xena_quiescence(struct s2io_nic *sp)
1910 {
1911         int  mode;
1912         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1913         u64 val64 = readq(&bar0->adapter_status);
1914         mode = s2io_verify_pci_mode(sp);
1915
1916         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1917                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1918                 return 0;
1919         }
1920         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1921         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1922                 return 0;
1923         }
1924         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1925                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1926                 return 0;
1927         }
1928         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1929                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1930                 return 0;
1931         }
1932         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1933                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1934                 return 0;
1935         }
1936         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1937                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1938                 return 0;
1939         }
1940         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1941                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1942                 return 0;
1943         }
1944         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1945                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1946                 return 0;
1947         }
1948
1949         /*
1950          * In PCI 33 mode, the P_PLL is not used, and therefore,
1951          * the the P_PLL_LOCK bit in the adapter_status register will
1952          * not be asserted.
1953          */
1954         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1955                 sp->device_type == XFRAME_II_DEVICE && mode !=
1956                 PCI_MODE_PCI_33) {
1957                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1958                 return 0;
1959         }
1960         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1961                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1962                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1963                 return 0;
1964         }
1965         return 1;
1966 }
1967
1968 /**
1969  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1970  * @sp: Pointer to device specifc structure
1971  * Description :
1972  * New procedure to clear mac address reading  problems on Alpha platforms
1973  *
1974  */
1975
1976 static void fix_mac_address(struct s2io_nic * sp)
1977 {
1978         struct XENA_dev_config __iomem *bar0 = sp->bar0;
1979         u64 val64;
1980         int i = 0;
1981
1982         while (fix_mac[i] != END_SIGN) {
1983                 writeq(fix_mac[i++], &bar0->gpio_control);
1984                 udelay(10);
1985                 val64 = readq(&bar0->gpio_control);
1986         }
1987 }
1988
1989 /**
1990  *  start_nic - Turns the device on
1991  *  @nic : device private variable.
1992  *  Description:
1993  *  This function actually turns the device on. Before this  function is
1994  *  called,all Registers are configured from their reset states
1995  *  and shared memory is allocated but the NIC is still quiescent. On
1996  *  calling this function, the device interrupts are cleared and the NIC is
1997  *  literally switched on by writing into the adapter control register.
1998  *  Return Value:
1999  *  SUCCESS on success and -1 on failure.
2000  */
2001
2002 static int start_nic(struct s2io_nic *nic)
2003 {
2004         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2005         struct net_device *dev = nic->dev;
2006         register u64 val64 = 0;
2007         u16 subid, i;
2008         struct mac_info *mac_control;
2009         struct config_param *config;
2010
2011         mac_control = &nic->mac_control;
2012         config = &nic->config;
2013
2014         /*  PRC Initialization and configuration */
2015         for (i = 0; i < config->rx_ring_num; i++) {
2016                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2017                        &bar0->prc_rxd0_n[i]);
2018
2019                 val64 = readq(&bar0->prc_ctrl_n[i]);
2020                 if (nic->config.bimodal)
2021                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2022                 if (nic->rxd_mode == RXD_MODE_1)
2023                         val64 |= PRC_CTRL_RC_ENABLED;
2024                 else
2025                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2026                 if (nic->device_type == XFRAME_II_DEVICE)
2027                         val64 |= PRC_CTRL_GROUP_READS;
2028                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2029                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2030                 writeq(val64, &bar0->prc_ctrl_n[i]);
2031         }
2032
2033         if (nic->rxd_mode == RXD_MODE_3B) {
2034                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2035                 val64 = readq(&bar0->rx_pa_cfg);
2036                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2037                 writeq(val64, &bar0->rx_pa_cfg);
2038         }
2039
2040         if (vlan_tag_strip == 0) {
2041                 val64 = readq(&bar0->rx_pa_cfg);
2042                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2043                 writeq(val64, &bar0->rx_pa_cfg);
2044                 vlan_strip_flag = 0;
2045         }
2046
2047         /*
2048          * Enabling MC-RLDRAM. After enabling the device, we timeout
2049          * for around 100ms, which is approximately the time required
2050          * for the device to be ready for operation.
2051          */
2052         val64 = readq(&bar0->mc_rldram_mrs);
2053         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2054         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2055         val64 = readq(&bar0->mc_rldram_mrs);
2056
2057         msleep(100);    /* Delay by around 100 ms. */
2058
2059         /* Enabling ECC Protection. */
2060         val64 = readq(&bar0->adapter_control);
2061         val64 &= ~ADAPTER_ECC_EN;
2062         writeq(val64, &bar0->adapter_control);
2063
2064         /*
2065          * Clearing any possible Link state change interrupts that
2066          * could have popped up just before Enabling the card.
2067          */
2068         val64 = readq(&bar0->mac_rmac_err_reg);
2069         if (val64)
2070                 writeq(val64, &bar0->mac_rmac_err_reg);
2071
2072         /*
2073          * Verify if the device is ready to be enabled, if so enable
2074          * it.
2075          */
2076         val64 = readq(&bar0->adapter_status);
2077         if (!verify_xena_quiescence(nic)) {
2078                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2079                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2080                           (unsigned long long) val64);
2081                 return FAILURE;
2082         }
2083
2084         /*
2085          * With some switches, link might be already up at this point.
2086          * Because of this weird behavior, when we enable laser,
2087          * we may not get link. We need to handle this. We cannot
2088          * figure out which switch is misbehaving. So we are forced to
2089          * make a global change.
2090          */
2091
2092         /* Enabling Laser. */
2093         val64 = readq(&bar0->adapter_control);
2094         val64 |= ADAPTER_EOI_TX_ON;
2095         writeq(val64, &bar0->adapter_control);
2096
2097         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2098                 /*
2099                  * Dont see link state interrupts initally on some switches,
2100                  * so directly scheduling the link state task here.
2101                  */
2102                 schedule_work(&nic->set_link_task);
2103         }
2104         /* SXE-002: Initialize link and activity LED */
2105         subid = nic->pdev->subsystem_device;
2106         if (((subid & 0xFF) >= 0x07) &&
2107             (nic->device_type == XFRAME_I_DEVICE)) {
2108                 val64 = readq(&bar0->gpio_control);
2109                 val64 |= 0x0000800000000000ULL;
2110                 writeq(val64, &bar0->gpio_control);
2111                 val64 = 0x0411040400000000ULL;
2112                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2113         }
2114
2115         return SUCCESS;
2116 }
2117 /**
2118  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2119  */
2120 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2121                                         TxD *txdlp, int get_off)
2122 {
2123         struct s2io_nic *nic = fifo_data->nic;
2124         struct sk_buff *skb;
2125         struct TxD *txds;
2126         u16 j, frg_cnt;
2127
2128         txds = txdlp;
2129         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2130                 pci_unmap_single(nic->pdev, (dma_addr_t)
2131                         txds->Buffer_Pointer, sizeof(u64),
2132                         PCI_DMA_TODEVICE);
2133                 txds++;
2134         }
2135
2136         skb = (struct sk_buff *) ((unsigned long)
2137                         txds->Host_Control);
2138         if (!skb) {
2139                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2140                 return NULL;
2141         }
2142         pci_unmap_single(nic->pdev, (dma_addr_t)
2143                          txds->Buffer_Pointer,
2144                          skb->len - skb->data_len,
2145                          PCI_DMA_TODEVICE);
2146         frg_cnt = skb_shinfo(skb)->nr_frags;
2147         if (frg_cnt) {
2148                 txds++;
2149                 for (j = 0; j < frg_cnt; j++, txds++) {
2150                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2151                         if (!txds->Buffer_Pointer)
2152                                 break;
2153                         pci_unmap_page(nic->pdev, (dma_addr_t)
2154                                         txds->Buffer_Pointer,
2155                                        frag->size, PCI_DMA_TODEVICE);
2156                 }
2157         }
2158         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2159         return(skb);
2160 }
2161
2162 /**
2163  *  free_tx_buffers - Free all queued Tx buffers
2164  *  @nic : device private variable.
2165  *  Description:
2166  *  Free all queued Tx buffers.
2167  *  Return Value: void
2168 */
2169
2170 static void free_tx_buffers(struct s2io_nic *nic)
2171 {
2172         struct net_device *dev = nic->dev;
2173         struct sk_buff *skb;
2174         struct TxD *txdp;
2175         int i, j;
2176         struct mac_info *mac_control;
2177         struct config_param *config;
2178         int cnt = 0;
2179
2180         mac_control = &nic->mac_control;
2181         config = &nic->config;
2182
2183         for (i = 0; i < config->tx_fifo_num; i++) {
2184                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2185                         txdp = (struct TxD *) \
2186                         mac_control->fifos[i].list_info[j].list_virt_addr;
2187                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2188                         if (skb) {
2189                                 nic->mac_control.stats_info->sw_stat.mem_freed
2190                                         += skb->truesize;
2191                                 dev_kfree_skb(skb);
2192                                 cnt++;
2193                         }
2194                 }
2195                 DBG_PRINT(INTR_DBG,
2196                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2197                           dev->name, cnt, i);
2198                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2199                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2200         }
2201 }
2202
2203 /**
2204  *   stop_nic -  To stop the nic
2205  *   @nic ; device private variable.
2206  *   Description:
2207  *   This function does exactly the opposite of what the start_nic()
2208  *   function does. This function is called to stop the device.
2209  *   Return Value:
2210  *   void.
2211  */
2212
2213 static void stop_nic(struct s2io_nic *nic)
2214 {
2215         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2216         register u64 val64 = 0;
2217         u16 interruptible;
2218         struct mac_info *mac_control;
2219         struct config_param *config;
2220
2221         mac_control = &nic->mac_control;
2222         config = &nic->config;
2223
2224         /*  Disable all interrupts */
2225         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2226         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2227         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2228         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2229
2230         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2231         val64 = readq(&bar0->adapter_control);
2232         val64 &= ~(ADAPTER_CNTL_EN);
2233         writeq(val64, &bar0->adapter_control);
2234 }
2235
2236 /**
2237  *  fill_rx_buffers - Allocates the Rx side skbs
2238  *  @nic:  device private variable
2239  *  @ring_no: ring number
2240  *  Description:
2241  *  The function allocates Rx side skbs and puts the physical
2242  *  address of these buffers into the RxD buffer pointers, so that the NIC
2243  *  can DMA the received frame into these locations.
2244  *  The NIC supports 3 receive modes, viz
2245  *  1. single buffer,
2246  *  2. three buffer and
2247  *  3. Five buffer modes.
2248  *  Each mode defines how many fragments the received frame will be split
2249  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2250  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2251  *  is split into 3 fragments. As of now only single buffer mode is
2252  *  supported.
2253  *   Return Value:
2254  *  SUCCESS on success or an appropriate -ve value on failure.
2255  */
2256
2257 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2258 {
2259         struct net_device *dev = nic->dev;
2260         struct sk_buff *skb;
2261         struct RxD_t *rxdp;
2262         int off, off1, size, block_no, block_no1;
2263         u32 alloc_tab = 0;
2264         u32 alloc_cnt;
2265         struct mac_info *mac_control;
2266         struct config_param *config;
2267         u64 tmp;
2268         struct buffAdd *ba;
2269         unsigned long flags;
2270         struct RxD_t *first_rxdp = NULL;
2271         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2272         struct RxD1 *rxdp1;
2273         struct RxD3 *rxdp3;
2274
2275         mac_control = &nic->mac_control;
2276         config = &nic->config;
2277         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2278             atomic_read(&nic->rx_bufs_left[ring_no]);
2279
2280         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2281         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2282         while (alloc_tab < alloc_cnt) {
2283                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2284                     block_index;
2285                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2286
2287                 rxdp = mac_control->rings[ring_no].
2288                                 rx_blocks[block_no].rxds[off].virt_addr;
2289
2290                 if ((block_no == block_no1) && (off == off1) &&
2291                                         (rxdp->Host_Control)) {
2292                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2293                                   dev->name);
2294                         DBG_PRINT(INTR_DBG, " info equated\n");
2295                         goto end;
2296                 }
2297                 if (off && (off == rxd_count[nic->rxd_mode])) {
2298                         mac_control->rings[ring_no].rx_curr_put_info.
2299                             block_index++;
2300                         if (mac_control->rings[ring_no].rx_curr_put_info.
2301                             block_index == mac_control->rings[ring_no].
2302                                         block_count)
2303                                 mac_control->rings[ring_no].rx_curr_put_info.
2304                                         block_index = 0;
2305                         block_no = mac_control->rings[ring_no].
2306                                         rx_curr_put_info.block_index;
2307                         if (off == rxd_count[nic->rxd_mode])
2308                                 off = 0;
2309                         mac_control->rings[ring_no].rx_curr_put_info.
2310                                 offset = off;
2311                         rxdp = mac_control->rings[ring_no].
2312                                 rx_blocks[block_no].block_virt_addr;
2313                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2314                                   dev->name, rxdp);
2315                 }
2316                 if(!napi) {
2317                         spin_lock_irqsave(&nic->put_lock, flags);
2318                         mac_control->rings[ring_no].put_pos =
2319                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2320                         spin_unlock_irqrestore(&nic->put_lock, flags);
2321                 } else {
2322                         mac_control->rings[ring_no].put_pos =
2323                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2324                 }
2325                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2326                         ((nic->rxd_mode == RXD_MODE_3B) &&
2327                                 (rxdp->Control_2 & BIT(0)))) {
2328                         mac_control->rings[ring_no].rx_curr_put_info.
2329                                         offset = off;
2330                         goto end;
2331                 }
2332                 /* calculate size of skb based on ring mode */
2333                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2334                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2335                 if (nic->rxd_mode == RXD_MODE_1)
2336                         size += NET_IP_ALIGN;
2337                 else
2338                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2339
2340                 /* allocate skb */
2341                 skb = dev_alloc_skb(size);
2342                 if(!skb) {
2343                         DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2344                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2345                         if (first_rxdp) {
2346                                 wmb();
2347                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2348                         }
2349                         nic->mac_control.stats_info->sw_stat. \
2350                                 mem_alloc_fail_cnt++;
2351                         return -ENOMEM ;
2352                 }
2353                 nic->mac_control.stats_info->sw_stat.mem_allocated
2354                         += skb->truesize;
2355                 if (nic->rxd_mode == RXD_MODE_1) {
2356                         /* 1 buffer mode - normal operation mode */
2357                         rxdp1 = (struct RxD1*)rxdp;
2358                         memset(rxdp, 0, sizeof(struct RxD1));
2359                         skb_reserve(skb, NET_IP_ALIGN);
2360                         rxdp1->Buffer0_ptr = pci_map_single
2361                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2362                                 PCI_DMA_FROMDEVICE);
2363                         rxdp->Control_2 =
2364                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2365
2366                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2367                         /*
2368                          * 2 buffer mode -
2369                          * 2 buffer mode provides 128
2370                          * byte aligned receive buffers.
2371                          */
2372
2373                         rxdp3 = (struct RxD3*)rxdp;
2374                         /* save buffer pointers to avoid frequent dma mapping */
2375                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2376                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2377                         memset(rxdp, 0, sizeof(struct RxD3));
2378                         /* restore the buffer pointers for dma sync*/
2379                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2380                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2381
2382                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2383                         skb_reserve(skb, BUF0_LEN);
2384                         tmp = (u64)(unsigned long) skb->data;
2385                         tmp += ALIGN_SIZE;
2386                         tmp &= ~ALIGN_SIZE;
2387                         skb->data = (void *) (unsigned long)tmp;
2388                         skb_reset_tail_pointer(skb);
2389
2390                         if (!(rxdp3->Buffer0_ptr))
2391                                 rxdp3->Buffer0_ptr =
2392                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2393                                            PCI_DMA_FROMDEVICE);
2394                         else
2395                                 pci_dma_sync_single_for_device(nic->pdev,
2396                                 (dma_addr_t) rxdp3->Buffer0_ptr,
2397                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2398                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2399                         if (nic->rxd_mode == RXD_MODE_3B) {
2400                                 /* Two buffer mode */
2401
2402                                 /*
2403                                  * Buffer2 will have L3/L4 header plus
2404                                  * L4 payload
2405                                  */
2406                                 rxdp3->Buffer2_ptr = pci_map_single
2407                                 (nic->pdev, skb->data, dev->mtu + 4,
2408                                                 PCI_DMA_FROMDEVICE);
2409
2410                                 /* Buffer-1 will be dummy buffer. Not used */
2411                                 if (!(rxdp3->Buffer1_ptr)) {
2412                                         rxdp3->Buffer1_ptr =
2413                                                 pci_map_single(nic->pdev,
2414                                                 ba->ba_1, BUF1_LEN,
2415                                                 PCI_DMA_FROMDEVICE);
2416                                 }
2417                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2418                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2419                                                                 (dev->mtu + 4);
2420                         }
2421                         rxdp->Control_2 |= BIT(0);
2422                 }
2423                 rxdp->Host_Control = (unsigned long) (skb);
2424                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2425                         rxdp->Control_1 |= RXD_OWN_XENA;
2426                 off++;
2427                 if (off == (rxd_count[nic->rxd_mode] + 1))
2428                         off = 0;
2429                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2430
2431                 rxdp->Control_2 |= SET_RXD_MARKER;
2432                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2433                         if (first_rxdp) {
2434                                 wmb();
2435                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2436                         }
2437                         first_rxdp = rxdp;
2438                 }
2439                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2440                 alloc_tab++;
2441         }
2442
2443       end:
2444         /* Transfer ownership of first descriptor to adapter just before
2445          * exiting. Before that, use memory barrier so that ownership
2446          * and other fields are seen by adapter correctly.
2447          */
2448         if (first_rxdp) {
2449                 wmb();
2450                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2451         }
2452
2453         return SUCCESS;
2454 }
2455
2456 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2457 {
2458         struct net_device *dev = sp->dev;
2459         int j;
2460         struct sk_buff *skb;
2461         struct RxD_t *rxdp;
2462         struct mac_info *mac_control;
2463         struct buffAdd *ba;
2464         struct RxD1 *rxdp1;
2465         struct RxD3 *rxdp3;
2466
2467         mac_control = &sp->mac_control;
2468         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2469                 rxdp = mac_control->rings[ring_no].
2470                                 rx_blocks[blk].rxds[j].virt_addr;
2471                 skb = (struct sk_buff *)
2472                         ((unsigned long) rxdp->Host_Control);
2473                 if (!skb) {
2474                         continue;
2475                 }
2476                 if (sp->rxd_mode == RXD_MODE_1) {
2477                         rxdp1 = (struct RxD1*)rxdp;
2478                         pci_unmap_single(sp->pdev, (dma_addr_t)
2479                                 rxdp1->Buffer0_ptr,
2480                                 dev->mtu +
2481                                 HEADER_ETHERNET_II_802_3_SIZE
2482                                 + HEADER_802_2_SIZE +
2483                                 HEADER_SNAP_SIZE,
2484                                 PCI_DMA_FROMDEVICE);
2485                         memset(rxdp, 0, sizeof(struct RxD1));
2486                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2487                         rxdp3 = (struct RxD3*)rxdp;
2488                         ba = &mac_control->rings[ring_no].
2489                                 ba[blk][j];
2490                         pci_unmap_single(sp->pdev, (dma_addr_t)
2491                                 rxdp3->Buffer0_ptr,
2492                                 BUF0_LEN,
2493                                 PCI_DMA_FROMDEVICE);
2494                         pci_unmap_single(sp->pdev, (dma_addr_t)
2495                                 rxdp3->Buffer1_ptr,
2496                                 BUF1_LEN,
2497                                 PCI_DMA_FROMDEVICE);
2498                         pci_unmap_single(sp->pdev, (dma_addr_t)
2499                                 rxdp3->Buffer2_ptr,
2500                                 dev->mtu + 4,
2501                                 PCI_DMA_FROMDEVICE);
2502                         memset(rxdp, 0, sizeof(struct RxD3));
2503                 }
2504                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2505                 dev_kfree_skb(skb);
2506                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2507         }
2508 }
2509
2510 /**
2511  *  free_rx_buffers - Frees all Rx buffers
2512  *  @sp: device private variable.
2513  *  Description:
2514  *  This function will free all Rx buffers allocated by host.
2515  *  Return Value:
2516  *  NONE.
2517  */
2518
2519 static void free_rx_buffers(struct s2io_nic *sp)
2520 {
2521         struct net_device *dev = sp->dev;
2522         int i, blk = 0, buf_cnt = 0;
2523         struct mac_info *mac_control;
2524         struct config_param *config;
2525
2526         mac_control = &sp->mac_control;
2527         config = &sp->config;
2528
2529         for (i = 0; i < config->rx_ring_num; i++) {
2530                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2531                         free_rxd_blk(sp,i,blk);
2532
2533                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2534                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2535                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2536                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2537                 atomic_set(&sp->rx_bufs_left[i], 0);
2538                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2539                           dev->name, buf_cnt, i);
2540         }
2541 }
2542
2543 /**
2544  * s2io_poll - Rx interrupt handler for NAPI support
2545  * @dev : pointer to the device structure.
2546  * @budget : The number of packets that were budgeted to be processed
2547  * during  one pass through the 'Poll" function.
2548  * Description:
2549  * Comes into picture only if NAPI support has been incorporated. It does
2550  * the same thing that rx_intr_handler does, but not in a interrupt context
2551  * also It will process only a given number of packets.
2552  * Return value:
2553  * 0 on success and 1 if there are No Rx packets to be processed.
2554  */
2555
2556 static int s2io_poll(struct net_device *dev, int *budget)
2557 {
2558         struct s2io_nic *nic = dev->priv;
2559         int pkt_cnt = 0, org_pkts_to_process;
2560         struct mac_info *mac_control;
2561         struct config_param *config;
2562         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2563         int i;
2564
2565         atomic_inc(&nic->isr_cnt);
2566         mac_control = &nic->mac_control;
2567         config = &nic->config;
2568
2569         nic->pkts_to_process = *budget;
2570         if (nic->pkts_to_process > dev->quota)
2571                 nic->pkts_to_process = dev->quota;
2572         org_pkts_to_process = nic->pkts_to_process;
2573
2574         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2575         readl(&bar0->rx_traffic_int);
2576
2577         for (i = 0; i < config->rx_ring_num; i++) {
2578                 rx_intr_handler(&mac_control->rings[i]);
2579                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2580                 if (!nic->pkts_to_process) {
2581                         /* Quota for the current iteration has been met */
2582                         goto no_rx;
2583                 }
2584         }
2585         if (!pkt_cnt)
2586                 pkt_cnt = 1;
2587
2588         dev->quota -= pkt_cnt;
2589         *budget -= pkt_cnt;
2590         netif_rx_complete(dev);
2591
2592         for (i = 0; i < config->rx_ring_num; i++) {
2593                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2594                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2595                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2596                         break;
2597                 }
2598         }
2599         /* Re enable the Rx interrupts. */
2600         writeq(0x0, &bar0->rx_traffic_mask);
2601         readl(&bar0->rx_traffic_mask);
2602         atomic_dec(&nic->isr_cnt);
2603         return 0;
2604
2605 no_rx:
2606         dev->quota -= pkt_cnt;
2607         *budget -= pkt_cnt;
2608
2609         for (i = 0; i < config->rx_ring_num; i++) {
2610                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2611                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2612                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2613                         break;
2614                 }
2615         }
2616         atomic_dec(&nic->isr_cnt);
2617         return 1;
2618 }
2619
2620 #ifdef CONFIG_NET_POLL_CONTROLLER
2621 /**
2622  * s2io_netpoll - netpoll event handler entry point
2623  * @dev : pointer to the device structure.
2624  * Description:
2625  *      This function will be called by upper layer to check for events on the
2626  * interface in situations where interrupts are disabled. It is used for
2627  * specific in-kernel networking tasks, such as remote consoles and kernel
2628  * debugging over the network (example netdump in RedHat).
2629  */
2630 static void s2io_netpoll(struct net_device *dev)
2631 {
2632         struct s2io_nic *nic = dev->priv;
2633         struct mac_info *mac_control;
2634         struct config_param *config;
2635         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2636         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2637         int i;
2638
2639         if (pci_channel_offline(nic->pdev))
2640                 return;
2641
2642         disable_irq(dev->irq);
2643
2644         atomic_inc(&nic->isr_cnt);
2645         mac_control = &nic->mac_control;
2646         config = &nic->config;
2647
2648         writeq(val64, &bar0->rx_traffic_int);
2649         writeq(val64, &bar0->tx_traffic_int);
2650
2651         /* we need to free up the transmitted skbufs or else netpoll will
2652          * run out of skbs and will fail and eventually netpoll application such
2653          * as netdump will fail.
2654          */
2655         for (i = 0; i < config->tx_fifo_num; i++)
2656                 tx_intr_handler(&mac_control->fifos[i]);
2657
2658         /* check for received packet and indicate up to network */
2659         for (i = 0; i < config->rx_ring_num; i++)
2660                 rx_intr_handler(&mac_control->rings[i]);
2661
2662         for (i = 0; i < config->rx_ring_num; i++) {
2663                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2664                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2665                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2666                         break;
2667                 }
2668         }
2669         atomic_dec(&nic->isr_cnt);
2670         enable_irq(dev->irq);
2671         return;
2672 }
2673 #endif
2674
2675 /**
2676  *  rx_intr_handler - Rx interrupt handler
2677  *  @nic: device private variable.
2678  *  Description:
2679  *  If the interrupt is because of a received frame or if the
2680  *  receive ring contains fresh as yet un-processed frames,this function is
2681  *  called. It picks out the RxD at which place the last Rx processing had
2682  *  stopped and sends the skb to the OSM's Rx handler and then increments
2683  *  the offset.
2684  *  Return Value:
2685  *  NONE.
2686  */
2687 static void rx_intr_handler(struct ring_info *ring_data)
2688 {
2689         struct s2io_nic *nic = ring_data->nic;
2690         struct net_device *dev = (struct net_device *) nic->dev;
2691         int get_block, put_block, put_offset;
2692         struct rx_curr_get_info get_info, put_info;
2693         struct RxD_t *rxdp;
2694         struct sk_buff *skb;
2695         int pkt_cnt = 0;
2696         int i;
2697         struct RxD1* rxdp1;
2698         struct RxD3* rxdp3;
2699
2700         spin_lock(&nic->rx_lock);
2701         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2702                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2703                           __FUNCTION__, dev->name);
2704                 spin_unlock(&nic->rx_lock);
2705                 return;
2706         }
2707
2708         get_info = ring_data->rx_curr_get_info;
2709         get_block = get_info.block_index;
2710         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2711         put_block = put_info.block_index;
2712         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2713         if (!napi) {
2714                 spin_lock(&nic->put_lock);
2715                 put_offset = ring_data->put_pos;
2716                 spin_unlock(&nic->put_lock);
2717         } else
2718                 put_offset = ring_data->put_pos;
2719
2720         while (RXD_IS_UP2DT(rxdp)) {
2721                 /*
2722                  * If your are next to put index then it's
2723                  * FIFO full condition
2724                  */
2725                 if ((get_block == put_block) &&
2726                     (get_info.offset + 1) == put_info.offset) {
2727                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2728                         break;
2729                 }
2730                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2731                 if (skb == NULL) {
2732                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2733                                   dev->name);
2734                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2735                         spin_unlock(&nic->rx_lock);
2736                         return;
2737                 }
2738                 if (nic->rxd_mode == RXD_MODE_1) {
2739                         rxdp1 = (struct RxD1*)rxdp;
2740                         pci_unmap_single(nic->pdev, (dma_addr_t)
2741                                 rxdp1->Buffer0_ptr,
2742                                 dev->mtu +
2743                                 HEADER_ETHERNET_II_802_3_SIZE +
2744                                 HEADER_802_2_SIZE +
2745                                 HEADER_SNAP_SIZE,
2746                                 PCI_DMA_FROMDEVICE);
2747                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2748                         rxdp3 = (struct RxD3*)rxdp;
2749                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2750                                 rxdp3->Buffer0_ptr,
2751                                 BUF0_LEN, PCI_DMA_FROMDEVICE);
2752                         pci_unmap_single(nic->pdev, (dma_addr_t)
2753                                 rxdp3->Buffer2_ptr,
2754                                 dev->mtu + 4,
2755                                 PCI_DMA_FROMDEVICE);
2756                 }
2757                 prefetch(skb->data);
2758                 rx_osm_handler(ring_data, rxdp);
2759                 get_info.offset++;
2760                 ring_data->rx_curr_get_info.offset = get_info.offset;
2761                 rxdp = ring_data->rx_blocks[get_block].
2762                                 rxds[get_info.offset].virt_addr;
2763                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2764                         get_info.offset = 0;
2765                         ring_data->rx_curr_get_info.offset = get_info.offset;
2766                         get_block++;
2767                         if (get_block == ring_data->block_count)
2768                                 get_block = 0;
2769                         ring_data->rx_curr_get_info.block_index = get_block;
2770                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2771                 }
2772
2773                 nic->pkts_to_process -= 1;
2774                 if ((napi) && (!nic->pkts_to_process))
2775                         break;
2776                 pkt_cnt++;
2777                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2778                         break;
2779         }
2780         if (nic->lro) {
2781                 /* Clear all LRO sessions before exiting */
2782                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2783                         struct lro *lro = &nic->lro0_n[i];
2784                         if (lro->in_use) {
2785                                 update_L3L4_header(nic, lro);
2786                                 queue_rx_frame(lro->parent);
2787                                 clear_lro_session(lro);
2788                         }
2789                 }
2790         }
2791
2792         spin_unlock(&nic->rx_lock);
2793 }
2794
2795 /**
2796  *  tx_intr_handler - Transmit interrupt handler
2797  *  @nic : device private variable
2798  *  Description:
2799  *  If an interrupt was raised to indicate DMA complete of the
2800  *  Tx packet, this function is called. It identifies the last TxD
2801  *  whose buffer was freed and frees all skbs whose data have already
2802  *  DMA'ed into the NICs internal memory.
2803  *  Return Value:
2804  *  NONE
2805  */
2806
2807 static void tx_intr_handler(struct fifo_info *fifo_data)
2808 {
2809         struct s2io_nic *nic = fifo_data->nic;
2810         struct net_device *dev = (struct net_device *) nic->dev;
2811         struct tx_curr_get_info get_info, put_info;
2812         struct sk_buff *skb;
2813         struct TxD *txdlp;
2814         u8 err_mask;
2815
2816         get_info = fifo_data->tx_curr_get_info;
2817         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2818         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2819             list_virt_addr;
2820         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2821                (get_info.offset != put_info.offset) &&
2822                (txdlp->Host_Control)) {
2823                 /* Check for TxD errors */
2824                 if (txdlp->Control_1 & TXD_T_CODE) {
2825                         unsigned long long err;
2826                         err = txdlp->Control_1 & TXD_T_CODE;
2827                         if (err & 0x1) {
2828                                 nic->mac_control.stats_info->sw_stat.
2829                                                 parity_err_cnt++;
2830                         }
2831
2832                         /* update t_code statistics */
2833                         err_mask = err >> 48;
2834                         switch(err_mask) {
2835                                 case 2:
2836                                         nic->mac_control.stats_info->sw_stat.
2837                                                         tx_buf_abort_cnt++;
2838                                 break;
2839
2840                                 case 3:
2841                                         nic->mac_control.stats_info->sw_stat.
2842                                                         tx_desc_abort_cnt++;
2843                                 break;
2844
2845                                 case 7:
2846                                         nic->mac_control.stats_info->sw_stat.
2847                                                         tx_parity_err_cnt++;
2848                                 break;
2849
2850                                 case 10:
2851                                         nic->mac_control.stats_info->sw_stat.
2852                                                         tx_link_loss_cnt++;
2853                                 break;
2854
2855                                 case 15:
2856                                         nic->mac_control.stats_info->sw_stat.
2857                                                         tx_list_proc_err_cnt++;
2858                                 break;
2859                         }
2860                 }
2861
2862                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2863                 if (skb == NULL) {
2864                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2865                         __FUNCTION__);
2866                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2867                         return;
2868                 }
2869
2870                 /* Updating the statistics block */
2871                 nic->stats.tx_bytes += skb->len;
2872                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2873                 dev_kfree_skb_irq(skb);
2874
2875                 get_info.offset++;
2876                 if (get_info.offset == get_info.fifo_len + 1)
2877                         get_info.offset = 0;
2878                 txdlp = (struct TxD *) fifo_data->list_info
2879                     [get_info.offset].list_virt_addr;
2880                 fifo_data->tx_curr_get_info.offset =
2881                     get_info.offset;
2882         }
2883
2884         spin_lock(&nic->tx_lock);
2885         if (netif_queue_stopped(dev))
2886                 netif_wake_queue(dev);
2887         spin_unlock(&nic->tx_lock);
2888 }
2889
2890 /**
2891  *  s2io_mdio_write - Function to write in to MDIO registers
2892  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2893  *  @addr     : address value
2894  *  @value    : data value
2895  *  @dev      : pointer to net_device structure
2896  *  Description:
2897  *  This function is used to write values to the MDIO registers
2898  *  NONE
2899  */
2900 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2901 {
2902         u64 val64 = 0x0;
2903         struct s2io_nic *sp = dev->priv;
2904         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2905
2906         //address transaction
2907         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2908                         | MDIO_MMD_DEV_ADDR(mmd_type)
2909                         | MDIO_MMS_PRT_ADDR(0x0);
2910         writeq(val64, &bar0->mdio_control);
2911         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2912         writeq(val64, &bar0->mdio_control);
2913         udelay(100);
2914
2915         //Data transaction
2916         val64 = 0x0;
2917         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2918                         | MDIO_MMD_DEV_ADDR(mmd_type)
2919                         | MDIO_MMS_PRT_ADDR(0x0)
2920                         | MDIO_MDIO_DATA(value)
2921                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2922         writeq(val64, &bar0->mdio_control);
2923         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2924         writeq(val64, &bar0->mdio_control);
2925         udelay(100);
2926
2927         val64 = 0x0;
2928         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2929         | MDIO_MMD_DEV_ADDR(mmd_type)
2930         | MDIO_MMS_PRT_ADDR(0x0)
2931         | MDIO_OP(MDIO_OP_READ_TRANS);
2932         writeq(val64, &bar0->mdio_control);
2933         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2934         writeq(val64, &bar0->mdio_control);
2935         udelay(100);
2936
2937 }
2938
2939 /**
2940  *  s2io_mdio_read - Function to write in to MDIO registers
2941  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2942  *  @addr     : address value
2943  *  @dev      : pointer to net_device structure
2944  *  Description:
2945  *  This function is used to read values to the MDIO registers
2946  *  NONE
2947  */
2948 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2949 {
2950         u64 val64 = 0x0;
2951         u64 rval64 = 0x0;
2952         struct s2io_nic *sp = dev->priv;
2953         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2954
2955         /* address transaction */
2956         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2957                         | MDIO_MMD_DEV_ADDR(mmd_type)
2958                         | MDIO_MMS_PRT_ADDR(0x0);
2959         writeq(val64, &bar0->mdio_control);
2960         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2961         writeq(val64, &bar0->mdio_control);
2962         udelay(100);
2963
2964         /* Data transaction */
2965         val64 = 0x0;
2966         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2967                         | MDIO_MMD_DEV_ADDR(mmd_type)
2968                         | MDIO_MMS_PRT_ADDR(0x0)
2969                         | MDIO_OP(MDIO_OP_READ_TRANS);
2970         writeq(val64, &bar0->mdio_control);
2971         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2972         writeq(val64, &bar0->mdio_control);
2973         udelay(100);
2974
2975         /* Read the value from regs */
2976         rval64 = readq(&bar0->mdio_control);
2977         rval64 = rval64 & 0xFFFF0000;
2978         rval64 = rval64 >> 16;
2979         return rval64;
2980 }
2981 /**
2982  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2983  *  @counter      : couter value to be updated
2984  *  @flag         : flag to indicate the status
2985  *  @type         : counter type
2986  *  Description:
2987  *  This function is to check the status of the xpak counters value
2988  *  NONE
2989  */
2990
2991 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2992 {
2993         u64 mask = 0x3;
2994         u64 val64;
2995         int i;
2996         for(i = 0; i <index; i++)
2997                 mask = mask << 0x2;
2998
2999         if(flag > 0)
3000         {
3001                 *counter = *counter + 1;
3002                 val64 = *regs_stat & mask;
3003                 val64 = val64 >> (index * 0x2);
3004                 val64 = val64 + 1;
3005                 if(val64 == 3)
3006                 {
3007                         switch(type)
3008                         {
3009                         case 1:
3010                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3011                                           "service. Excessive temperatures may "
3012                                           "result in premature transceiver "
3013                                           "failure \n");
3014                         break;
3015                         case 2:
3016                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3017                                           "service Excessive bias currents may "
3018                                           "indicate imminent laser diode "
3019                                           "failure \n");
3020                         break;
3021                         case 3:
3022                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3023                                           "service Excessive laser output "
3024                                           "power may saturate far-end "
3025                                           "receiver\n");
3026                         break;
3027                         default:
3028                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3029                                           "type \n");
3030                         }
3031                         val64 = 0x0;
3032                 }
3033                 val64 = val64 << (index * 0x2);
3034                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3035
3036         } else {
3037                 *regs_stat = *regs_stat & (~mask);
3038         }
3039 }
3040
3041 /**
3042  *  s2io_updt_xpak_counter - Function to update the xpak counters
3043  *  @dev         : pointer to net_device struct
3044  *  Description:
3045  *  This function is to upate the status of the xpak counters value
3046  *  NONE
3047  */
3048 static void s2io_updt_xpak_counter(struct net_device *dev)
3049 {
3050         u16 flag  = 0x0;
3051         u16 type  = 0x0;
3052         u16 val16 = 0x0;
3053         u64 val64 = 0x0;
3054         u64 addr  = 0x0;
3055
3056         struct s2io_nic *sp = dev->priv;
3057         struct stat_block *stat_info = sp->mac_control.stats_info;
3058
3059         /* Check the communication with the MDIO slave */
3060         addr = 0x0000;
3061         val64 = 0x0;
3062         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3063         if((val64 == 0xFFFF) || (val64 == 0x0000))
3064         {
3065                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3066                           "Returned %llx\n", (unsigned long long)val64);
3067                 return;
3068         }
3069
3070         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3071         if(val64 != 0x2040)
3072         {
3073                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3074                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3075                           (unsigned long long)val64);
3076                 return;
3077         }
3078
3079         /* Loading the DOM register to MDIO register */
3080         addr = 0xA100;
3081         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3082         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3083
3084         /* Reading the Alarm flags */
3085         addr = 0xA070;
3086         val64 = 0x0;
3087         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3088
3089         flag = CHECKBIT(val64, 0x7);
3090         type = 1;
3091         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3092                                 &stat_info->xpak_stat.xpak_regs_stat,
3093                                 0x0, flag, type);
3094
3095         if(CHECKBIT(val64, 0x6))
3096                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3097
3098         flag = CHECKBIT(val64, 0x3);
3099         type = 2;
3100         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3101                                 &stat_info->xpak_stat.xpak_regs_stat,
3102                                 0x2, flag, type);
3103
3104         if(CHECKBIT(val64, 0x2))
3105                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3106
3107         flag = CHECKBIT(val64, 0x1);
3108         type = 3;
3109         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3110                                 &stat_info->xpak_stat.xpak_regs_stat,
3111                                 0x4, flag, type);
3112
3113         if(CHECKBIT(val64, 0x0))
3114                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3115
3116         /* Reading the Warning flags */
3117         addr = 0xA074;
3118         val64 = 0x0;
3119         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3120
3121         if(CHECKBIT(val64, 0x7))
3122                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3123
3124         if(CHECKBIT(val64, 0x6))
3125                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3126
3127         if(CHECKBIT(val64, 0x3))
3128                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3129
3130         if(CHECKBIT(val64, 0x2))
3131                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3132
3133         if(CHECKBIT(val64, 0x1))
3134                 stat_info->xpak_stat.warn_laser_output_power_high++;
3135
3136         if(CHECKBIT(val64, 0x0))
3137                 stat_info->xpak_stat.warn_laser_output_power_low++;
3138 }
3139
3140 /**
3141  *  alarm_intr_handler - Alarm Interrrupt handler
3142  *  @nic: device private variable
3143  *  Description: If the interrupt was neither because of Rx packet or Tx
3144  *  complete, this function is called. If the interrupt was to indicate
3145  *  a loss of link, the OSM link status handler is invoked for any other
3146  *  alarm interrupt the block that raised the interrupt is displayed
3147  *  and a H/W reset is issued.
3148  *  Return Value:
3149  *  NONE
3150 */
3151
3152 static void alarm_intr_handler(struct s2io_nic *nic)
3153 {
3154         struct net_device *dev = (struct net_device *) nic->dev;
3155         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3156         register u64 val64 = 0, err_reg = 0;
3157         u64 cnt;
3158         int i;
3159         if (atomic_read(&nic->card_state) == CARD_DOWN)
3160                 return;
3161         if (pci_channel_offline(nic->pdev))
3162                 return;
3163         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3164         /* Handling the XPAK counters update */
3165         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3166                 /* waiting for an hour */
3167                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3168         } else {
3169                 s2io_updt_xpak_counter(dev);
3170                 /* reset the count to zero */
3171                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3172         }
3173
3174         /* Handling link status change error Intr */
3175         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3176                 err_reg = readq(&bar0->mac_rmac_err_reg);
3177                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3178                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3179                         schedule_work(&nic->set_link_task);
3180                 }
3181         }
3182
3183         /* Handling Ecc errors */
3184         val64 = readq(&bar0->mc_err_reg);
3185         writeq(val64, &bar0->mc_err_reg);
3186         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3187                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3188                         nic->mac_control.stats_info->sw_stat.
3189                                 double_ecc_errs++;
3190                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3191                                   dev->name);
3192                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3193                         if (nic->device_type != XFRAME_II_DEVICE) {
3194                                 /* Reset XframeI only if critical error */
3195                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3196                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3197                                         netif_stop_queue(dev);
3198                                         schedule_work(&nic->rst_timer_task);
3199                                         nic->mac_control.stats_info->sw_stat.
3200                                                         soft_reset_cnt++;
3201                                 }
3202                         }
3203                 } else {
3204                         nic->mac_control.stats_info->sw_stat.
3205                                 single_ecc_errs++;
3206                 }
3207         }
3208
3209         /* In case of a serious error, the device will be Reset. */
3210         val64 = readq(&bar0->serr_source);
3211         if (val64 & SERR_SOURCE_ANY) {
3212                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3213                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3214                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3215                           (unsigned long long)val64);
3216                 netif_stop_queue(dev);
3217                 schedule_work(&nic->rst_timer_task);
3218                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3219         }
3220
3221         /*
3222          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3223          * Error occurs, the adapter will be recycled by disabling the
3224          * adapter enable bit and enabling it again after the device
3225          * becomes Quiescent.
3226          */
3227         val64 = readq(&bar0->pcc_err_reg);
3228         writeq(val64, &bar0->pcc_err_reg);
3229         if (val64 & PCC_FB_ECC_DB_ERR) {
3230                 u64 ac = readq(&bar0->adapter_control);
3231                 ac &= ~(ADAPTER_CNTL_EN);
3232                 writeq(ac, &bar0->adapter_control);
3233                 ac = readq(&bar0->adapter_control);
3234                 schedule_work(&nic->set_link_task);
3235         }
3236         /* Check for data parity error */
3237         val64 = readq(&bar0->pic_int_status);
3238         if (val64 & PIC_INT_GPIO) {
3239                 val64 = readq(&bar0->gpio_int_reg);
3240                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3241                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3242                         schedule_work(&nic->rst_timer_task);
3243                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3244                 }
3245         }
3246
3247         /* Check for ring full counter */
3248         if (nic->device_type & XFRAME_II_DEVICE) {
3249                 val64 = readq(&bar0->ring_bump_counter1);
3250                 for (i=0; i<4; i++) {
3251                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3252                         cnt >>= 64 - ((i+1)*16);
3253                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3254                                 += cnt;
3255                 }
3256
3257                 val64 = readq(&bar0->ring_bump_counter2);
3258                 for (i=0; i<4; i++) {
3259                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3260                         cnt >>= 64 - ((i+1)*16);
3261                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3262                                 += cnt;
3263                 }
3264         }
3265
3266         /* Other type of interrupts are not being handled now,  TODO */
3267 }
3268
3269 /**
3270  *  wait_for_cmd_complete - waits for a command to complete.
3271  *  @sp : private member of the device structure, which is a pointer to the
3272  *  s2io_nic structure.
3273  *  Description: Function that waits for a command to Write into RMAC
3274  *  ADDR DATA registers to be completed and returns either success or
3275  *  error depending on whether the command was complete or not.
3276  *  Return value:
3277  *   SUCCESS on success and FAILURE on failure.
3278  */
3279
3280 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3281                                 int bit_state)
3282 {
3283         int ret = FAILURE, cnt = 0, delay = 1;
3284         u64 val64;
3285
3286         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3287                 return FAILURE;
3288
3289         do {
3290                 val64 = readq(addr);
3291                 if (bit_state == S2IO_BIT_RESET) {
3292                         if (!(val64 & busy_bit)) {
3293                                 ret = SUCCESS;
3294                                 break;
3295                         }
3296                 } else {
3297                         if (!(val64 & busy_bit)) {
3298                                 ret = SUCCESS;
3299                                 break;
3300                         }
3301                 }
3302
3303                 if(in_interrupt())
3304                         mdelay(delay);
3305                 else
3306                         msleep(delay);
3307
3308                 if (++cnt >= 10)
3309                         delay = 50;
3310         } while (cnt < 20);
3311         return ret;
3312 }
3313 /*
3314  * check_pci_device_id - Checks if the device id is supported
3315  * @id : device id
3316  * Description: Function to check if the pci device id is supported by driver.
3317  * Return value: Actual device id if supported else PCI_ANY_ID
3318  */
3319 static u16 check_pci_device_id(u16 id)
3320 {
3321         switch (id) {
3322         case PCI_DEVICE_ID_HERC_WIN:
3323         case PCI_DEVICE_ID_HERC_UNI:
3324                 return XFRAME_II_DEVICE;
3325         case PCI_DEVICE_ID_S2IO_UNI:
3326         case PCI_DEVICE_ID_S2IO_WIN:
3327                 return XFRAME_I_DEVICE;
3328         default:
3329                 return PCI_ANY_ID;
3330         }
3331 }
3332
3333 /**
3334  *  s2io_reset - Resets the card.
3335  *  @sp : private member of the device structure.
3336  *  Description: Function to Reset the card. This function then also
3337  *  restores the previously saved PCI configuration space registers as
3338  *  the card reset also resets the configuration space.
3339  *  Return value:
3340  *  void.
3341  */
3342
3343 static void s2io_reset(struct s2io_nic * sp)
3344 {
3345         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3346         u64 val64;
3347         u16 subid, pci_cmd;
3348         int i;
3349         u16 val16;
3350         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3351         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3352
3353         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3354                         __FUNCTION__, sp->dev->name);
3355
3356         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3357         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3358
3359         if (sp->device_type == XFRAME_II_DEVICE) {
3360                 int ret;
3361                 ret = pci_set_power_state(sp->pdev, 3);
3362                 if (!ret)
3363                         ret = pci_set_power_state(sp->pdev, 0);
3364                 else {
3365                         DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3366                                         __FUNCTION__);
3367                         goto old_way;
3368                 }
3369                 msleep(20);
3370                 goto new_way;
3371         }
3372 old_way:
3373         val64 = SW_RESET_ALL;
3374         writeq(val64, &bar0->sw_reset);
3375 new_way:
3376         if (strstr(sp->product_name, "CX4")) {
3377                 msleep(750);
3378         }
3379         msleep(250);
3380         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3381
3382                 /* Restore the PCI state saved during initialization. */
3383                 pci_restore_state(sp->pdev);
3384                 pci_read_config_word(sp->pdev, 0x2, &val16);
3385                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3386                         break;
3387                 msleep(200);
3388         }
3389
3390         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3391                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3392         }
3393
3394         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3395
3396         s2io_init_pci(sp);
3397
3398         /* Set swapper to enable I/O register access */
3399         s2io_set_swapper(sp);
3400
3401         /* Restore the MSIX table entries from local variables */
3402         restore_xmsi_data(sp);
3403
3404         /* Clear certain PCI/PCI-X fields after reset */
3405         if (sp->device_type == XFRAME_II_DEVICE) {
3406                 /* Clear "detected parity error" bit */
3407                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3408
3409                 /* Clearing PCIX Ecc status register */
3410                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3411
3412                 /* Clearing PCI_STATUS error reflected here */
3413                 writeq(BIT(62), &bar0->txpic_int_reg);
3414         }
3415
3416         /* Reset device statistics maintained by OS */
3417         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3418
3419         up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3420         down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3421         up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3422         down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3423         reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3424         mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3425         mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3426         watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3427         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3428         memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3429         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3430         sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3431         sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3432         sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3433         sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3434         sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3435         sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3436         sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3437         sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3438
3439         /* SXE-002: Configure link and activity LED to turn it off */
3440         subid = sp->pdev->subsystem_device;
3441         if (((subid & 0xFF) >= 0x07) &&
3442             (sp->device_type == XFRAME_I_DEVICE)) {
3443                 val64 = readq(&bar0->gpio_control);
3444                 val64 |= 0x0000800000000000ULL;
3445                 writeq(val64, &bar0->gpio_control);
3446                 val64 = 0x0411040400000000ULL;
3447                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3448         }
3449
3450         /*
3451          * Clear spurious ECC interrupts that would have occured on
3452          * XFRAME II cards after reset.
3453          */
3454         if (sp->device_type == XFRAME_II_DEVICE) {
3455                 val64 = readq(&bar0->pcc_err_reg);
3456                 writeq(val64, &bar0->pcc_err_reg);
3457         }
3458
3459         /* restore the previously assigned mac address */
3460         s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3461
3462         sp->device_enabled_once = FALSE;
3463 }
3464
3465 /**
3466  *  s2io_set_swapper - to set the swapper controle on the card
3467  *  @sp : private member of the device structure,
3468  *  pointer to the s2io_nic structure.
3469  *  Description: Function to set the swapper control on the card
3470  *  correctly depending on the 'endianness' of the system.
3471  *  Return value:
3472  *  SUCCESS on success and FAILURE on failure.
3473  */
3474
3475 static int s2io_set_swapper(struct s2io_nic * sp)
3476 {
3477         struct net_device *dev = sp->dev;
3478         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3479         u64 val64, valt, valr;
3480
3481         /*
3482          * Set proper endian settings and verify the same by reading
3483          * the PIF Feed-back register.
3484          */
3485
3486         val64 = readq(&bar0->pif_rd_swapper_fb);
3487         if (val64 != 0x0123456789ABCDEFULL) {
3488                 int i = 0;
3489                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3490                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3491                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3492                                 0};                     /* FE=0, SE=0 */
3493
3494                 while(i<4) {
3495                         writeq(value[i], &bar0->swapper_ctrl);
3496                         val64 = readq(&bar0->pif_rd_swapper_fb);
3497                         if (val64 == 0x0123456789ABCDEFULL)
3498                                 break;
3499                         i++;
3500                 }
3501                 if (i == 4) {
3502                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3503                                 dev->name);
3504                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3505                                 (unsigned long long) val64);
3506                         return FAILURE;
3507                 }
3508                 valr = value[i];
3509         } else {
3510                 valr = readq(&bar0->swapper_ctrl);
3511         }
3512
3513         valt = 0x0123456789ABCDEFULL;
3514         writeq(valt, &bar0->xmsi_address);
3515         val64 = readq(&bar0->xmsi_address);
3516
3517         if(val64 != valt) {
3518                 int i = 0;
3519                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3520                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3521                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3522                                 0};                     /* FE=0, SE=0 */
3523
3524                 while(i<4) {
3525                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3526                         writeq(valt, &bar0->xmsi_address);
3527                         val64 = readq(&bar0->xmsi_address);
3528                         if(val64 == valt)
3529                                 break;
3530                         i++;
3531                 }
3532                 if(i == 4) {
3533                         unsigned long long x = val64;
3534                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3535                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3536                         return FAILURE;
3537                 }
3538         }
3539         val64 = readq(&bar0->swapper_ctrl);
3540         val64 &= 0xFFFF000000000000ULL;
3541
3542 #ifdef  __BIG_ENDIAN
3543         /*
3544          * The device by default set to a big endian format, so a
3545          * big endian driver need not set anything.
3546          */
3547         val64 |= (SWAPPER_CTRL_TXP_FE |
3548                  SWAPPER_CTRL_TXP_SE |
3549                  SWAPPER_CTRL_TXD_R_FE |
3550                  SWAPPER_CTRL_TXD_W_FE |
3551                  SWAPPER_CTRL_TXF_R_FE |
3552                  SWAPPER_CTRL_RXD_R_FE |
3553                  SWAPPER_CTRL_RXD_W_FE |
3554                  SWAPPER_CTRL_RXF_W_FE |
3555                  SWAPPER_CTRL_XMSI_FE |
3556                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3557         if (sp->intr_type == INTA)
3558                 val64 |= SWAPPER_CTRL_XMSI_SE;
3559         writeq(val64, &bar0->swapper_ctrl);
3560 #else
3561         /*
3562          * Initially we enable all bits to make it accessible by the
3563          * driver, then we selectively enable only those bits that
3564          * we want to set.
3565          */
3566         val64 |= (SWAPPER_CTRL_TXP_FE |
3567                  SWAPPER_CTRL_TXP_SE |
3568                  SWAPPER_CTRL_TXD_R_FE |
3569                  SWAPPER_CTRL_TXD_R_SE |
3570                  SWAPPER_CTRL_TXD_W_FE |
3571                  SWAPPER_CTRL_TXD_W_SE |
3572                  SWAPPER_CTRL_TXF_R_FE |
3573                  SWAPPER_CTRL_RXD_R_FE |
3574                  SWAPPER_CTRL_RXD_R_SE |
3575                  SWAPPER_CTRL_RXD_W_FE |
3576                  SWAPPER_CTRL_RXD_W_SE |
3577                  SWAPPER_CTRL_RXF_W_FE |
3578                  SWAPPER_CTRL_XMSI_FE |
3579                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3580         if (sp->intr_type == INTA)
3581                 val64 |= SWAPPER_CTRL_XMSI_SE;
3582         writeq(val64, &bar0->swapper_ctrl);
3583 #endif
3584         val64 = readq(&bar0->swapper_ctrl);
3585
3586         /*
3587          * Verifying if endian settings are accurate by reading a
3588          * feedback register.
3589          */
3590         val64 = readq(&bar0->pif_rd_swapper_fb);
3591         if (val64 != 0x0123456789ABCDEFULL) {
3592                 /* Endian settings are incorrect, calls for another dekko. */
3593                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3594                           dev->name);
3595                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3596                           (unsigned long long) val64);
3597                 return FAILURE;
3598         }
3599
3600         return SUCCESS;
3601 }
3602
3603 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3604 {
3605         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3606         u64 val64;
3607         int ret = 0, cnt = 0;
3608
3609         do {
3610                 val64 = readq(&bar0->xmsi_access);
3611                 if (!(val64 & BIT(15)))
3612                         break;
3613                 mdelay(1);
3614                 cnt++;
3615         } while(cnt < 5);
3616         if (cnt == 5) {
3617                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3618                 ret = 1;
3619         }
3620
3621         return ret;
3622 }
3623
3624 static void restore_xmsi_data(struct s2io_nic *nic)
3625 {
3626         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3627         u64 val64;
3628         int i;
3629
3630         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3631                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3632                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3633                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3634                 writeq(val64, &bar0->xmsi_access);
3635                 if (wait_for_msix_trans(nic, i)) {
3636                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3637                         continue;
3638                 }
3639         }
3640 }
3641
3642 static void store_xmsi_data(struct s2io_nic *nic)
3643 {
3644         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3645         u64 val64, addr, data;
3646         int i;
3647
3648         /* Store and display */
3649         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3650                 val64 = (BIT(15) | vBIT(i, 26, 6));
3651                 writeq(val64, &bar0->xmsi_access);
3652                 if (wait_for_msix_trans(nic, i)) {
3653                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3654                         continue;
3655                 }
3656                 addr = readq(&bar0->xmsi_address);
3657                 data = readq(&bar0->xmsi_data);
3658                 if (addr && data) {
3659                         nic->msix_info[i].addr = addr;
3660                         nic->msix_info[i].data = data;
3661                 }
3662         }
3663 }
3664
3665 static int s2io_enable_msi_x(struct s2io_nic *nic)
3666 {
3667         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3668         u64 tx_mat, rx_mat;
3669         u16 msi_control; /* Temp variable */
3670         int ret, i, j, msix_indx = 1;
3671
3672         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3673                                GFP_KERNEL);
3674         if (nic->entries == NULL) {
3675                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3676                         __FUNCTION__);
3677                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3678                 return -ENOMEM;
3679         }
3680         nic->mac_control.stats_info->sw_stat.mem_allocated
3681                 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3682         memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3683
3684         nic->s2io_entries =
3685                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3686                                    GFP_KERNEL);
3687         if (nic->s2io_entries == NULL) {
3688                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3689                         __FUNCTION__);
3690                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3691                 kfree(nic->entries);
3692                 nic->mac_control.stats_info->sw_stat.mem_freed
3693                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3694                 return -ENOMEM;
3695         }
3696          nic->mac_control.stats_info->sw_stat.mem_allocated
3697                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3698         memset(nic->s2io_entries, 0,
3699                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3700
3701         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3702                 nic->entries[i].entry = i;
3703                 nic->s2io_entries[i].entry = i;
3704                 nic->s2io_entries[i].arg = NULL;
3705                 nic->s2io_entries[i].in_use = 0;
3706         }
3707
3708         tx_mat = readq(&bar0->tx_mat0_n[0]);
3709         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3710                 tx_mat |= TX_MAT_SET(i, msix_indx);
3711                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3712                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3713                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3714         }
3715         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3716
3717         if (!nic->config.bimodal) {
3718                 rx_mat = readq(&bar0->rx_mat);
3719                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3720                         rx_mat |= RX_MAT_SET(j, msix_indx);
3721                         nic->s2io_entries[msix_indx].arg
3722                                 = &nic->mac_control.rings[j];
3723                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3724                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3725                 }
3726                 writeq(rx_mat, &bar0->rx_mat);
3727         } else {
3728                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3729                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3730                         tx_mat |= TX_MAT_SET(i, msix_indx);
3731                         nic->s2io_entries[msix_indx].arg
3732                                 = &nic->mac_control.rings[j];
3733                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3734                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3735                 }
3736                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3737         }
3738
3739         nic->avail_msix_vectors = 0;
3740         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3741         /* We fail init if error or we get less vectors than min required */
3742         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3743                 nic->avail_msix_vectors = ret;
3744                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3745         }
3746         if (ret) {
3747                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3748                 kfree(nic->entries);
3749                 nic->mac_control.stats_info->sw_stat.mem_freed
3750                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3751                 kfree(nic->s2io_entries);
3752                 nic->mac_control.stats_info->sw_stat.mem_freed
3753                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3754                 nic->entries = NULL;
3755                 nic->s2io_entries = NULL;
3756                 nic->avail_msix_vectors = 0;
3757                 return -ENOMEM;
3758         }
3759         if (!nic->avail_msix_vectors)
3760                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3761
3762         /*
3763          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3764          * in the herc NIC. (Temp change, needs to be removed later)
3765          */
3766         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3767         msi_control |= 0x1; /* Enable MSI */
3768         pci_write_config_word(nic->pdev, 0x42, msi_control);
3769
3770         return 0;
3771 }
3772
3773 /* ********************************************************* *
3774  * Functions defined below concern the OS part of the driver *
3775  * ********************************************************* */
3776
3777 /**
3778  *  s2io_open - open entry point of the driver
3779  *  @dev : pointer to the device structure.
3780  *  Description:
3781  *  This function is the open entry point of the driver. It mainly calls a
3782  *  function to allocate Rx buffers and inserts them into the buffer
3783  *  descriptors and then enables the Rx part of the NIC.
3784  *  Return value:
3785  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3786  *   file on failure.
3787  */
3788
3789 static int s2io_open(struct net_device *dev)
3790 {
3791         struct s2io_nic *sp = dev->priv;
3792         int err = 0;
3793
3794         /*
3795          * Make sure you have link off by default every time
3796          * Nic is initialized
3797          */
3798         netif_carrier_off(dev);
3799         sp->last_link_state = 0;
3800
3801         /* Initialize H/W and enable interrupts */
3802         err = s2io_card_up(sp);
3803         if (err) {
3804                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3805                           dev->name);
3806                 goto hw_init_failed;
3807         }
3808
3809         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3810                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3811                 s2io_card_down(sp);
3812                 err = -ENODEV;
3813                 goto hw_init_failed;
3814         }
3815
3816         netif_start_queue(dev);
3817         return 0;
3818
3819 hw_init_failed:
3820         if (sp->intr_type == MSI_X) {
3821                 if (sp->entries) {
3822                         kfree(sp->entries);
3823                         sp->mac_control.stats_info->sw_stat.mem_freed
3824                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3825                 }
3826                 if (sp->s2io_entries) {
3827                         kfree(sp->s2io_entries);
3828                         sp->mac_control.stats_info->sw_stat.mem_freed
3829                         += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3830                 }
3831         }
3832         return err;
3833 }
3834
3835 /**
3836  *  s2io_close -close entry point of the driver
3837  *  @dev : device pointer.
3838  *  Description:
3839  *  This is the stop entry point of the driver. It needs to undo exactly
3840  *  whatever was done by the open entry point,thus it's usually referred to
3841  *  as the close function.Among other things this function mainly stops the
3842  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3843  *  Return value:
3844  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3845  *  file on failure.
3846  */
3847
3848 static int s2io_close(struct net_device *dev)
3849 {
3850         struct s2io_nic *sp = dev->priv;
3851
3852         netif_stop_queue(dev);
3853         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3854         s2io_card_down(sp);
3855
3856         return 0;
3857 }
3858
3859 /**
3860  *  s2io_xmit - Tx entry point of te driver
3861  *  @skb : the socket buffer containing the Tx data.
3862  *  @dev : device pointer.
3863  *  Description :
3864  *  This function is the Tx entry point of the driver. S2IO NIC supports
3865  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3866  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3867  *  not be upadted.
3868  *  Return value:
3869  *  0 on success & 1 on failure.
3870  */
3871
3872 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3873 {
3874         struct s2io_nic *sp = dev->priv;
3875         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3876         register u64 val64;
3877         struct TxD *txdp;
3878         struct TxFIFO_element __iomem *tx_fifo;
3879         unsigned long flags;
3880         u16 vlan_tag = 0;
3881         int vlan_priority = 0;
3882         struct mac_info *mac_control;
3883         struct config_param *config;
3884         int offload_type;
3885
3886         mac_control = &sp->mac_control;
3887         config = &sp->config;
3888
3889         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3890
3891         if (unlikely(skb->len <= 0)) {
3892                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3893                 dev_kfree_skb_any(skb);
3894                 return 0;
3895 }
3896
3897         spin_lock_irqsave(&sp->tx_lock, flags);
3898         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3899                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3900                           dev->name);
3901                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3902                 dev_kfree_skb(skb);
3903                 return 0;
3904         }
3905
3906         queue = 0;
3907         /* Get Fifo number to Transmit based on vlan priority */
3908         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3909                 vlan_tag = vlan_tx_tag_get(skb);
3910                 vlan_priority = vlan_tag >> 13;
3911                 queue = config->fifo_mapping[vlan_priority];
3912         }
3913
3914         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3915         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3916         txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
3917                 list_virt_addr;
3918
3919         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3920         /* Avoid "put" pointer going beyond "get" pointer */
3921         if (txdp->Host_Control ||
3922                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3923                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3924                 netif_stop_queue(dev);
3925                 dev_kfree_skb(skb);
3926                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3927                 return 0;
3928         }
3929
3930         offload_type = s2io_offload_type(skb);
3931         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3932                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3933                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3934         }
3935         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3936                 txdp->Control_2 |=
3937                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3938                      TXD_TX_CKO_UDP_EN);
3939         }
3940         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3941         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3942         txdp->Control_2 |= config->tx_intr_type;
3943
3944         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3945                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3946                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3947         }
3948
3949         frg_len = skb->len - skb->data_len;
3950         if (offload_type == SKB_GSO_UDP) {
3951                 int ufo_size;
3952
3953                 ufo_size = s2io_udp_mss(skb);
3954                 ufo_size &= ~7;
3955                 txdp->Control_1 |= TXD_UFO_EN;
3956                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3957                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3958 #ifdef __BIG_ENDIAN
3959                 sp->ufo_in_band_v[put_off] =
3960                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3961 #else
3962                 sp->ufo_in_band_v[put_off] =
3963                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3964 #endif
3965                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3966                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3967                                         sp->ufo_in_band_v,
3968                                         sizeof(u64), PCI_DMA_TODEVICE);
3969                 txdp++;
3970         }
3971
3972         txdp->Buffer_Pointer = pci_map_single
3973             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3974         txdp->Host_Control = (unsigned long) skb;
3975         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3976         if (offload_type == SKB_GSO_UDP)
3977                 txdp->Control_1 |= TXD_UFO_EN;
3978
3979         frg_cnt = skb_shinfo(skb)->nr_frags;
3980         /* For fragmented SKB. */
3981         for (i = 0; i < frg_cnt; i++) {
3982                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3983                 /* A '0' length fragment will be ignored */
3984                 if (!frag->size)
3985                         continue;
3986                 txdp++;
3987                 txdp->Buffer_Pointer = (u64) pci_map_page
3988                     (sp->pdev, frag->page, frag->page_offset,
3989                      frag->size, PCI_DMA_TODEVICE);
3990                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3991                 if (offload_type == SKB_GSO_UDP)
3992                         txdp->Control_1 |= TXD_UFO_EN;
3993         }
3994         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3995
3996         if (offload_type == SKB_GSO_UDP)
3997                 frg_cnt++; /* as Txd0 was used for inband header */
3998
3999         tx_fifo = mac_control->tx_FIFO_start[queue];
4000         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4001         writeq(val64, &tx_fifo->TxDL_Pointer);
4002
4003         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4004                  TX_FIFO_LAST_LIST);
4005         if (offload_type)
4006                 val64 |= TX_FIFO_SPECIAL_FUNC;
4007
4008         writeq(val64, &tx_fifo->List_Control);
4009
4010         mmiowb();
4011
4012         put_off++;
4013         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4014                 put_off = 0;
4015         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4016
4017         /* Avoid "put" pointer going beyond "get" pointer */
4018         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4019                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4020                 DBG_PRINT(TX_DBG,
4021                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4022                           put_off, get_off);
4023                 netif_stop_queue(dev);
4024         }
4025         mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4026         dev->trans_start = jiffies;
4027         spin_unlock_irqrestore(&sp->tx_lock, flags);
4028
4029         return 0;
4030 }
4031
4032 static void
4033 s2io_alarm_handle(unsigned long data)
4034 {
4035         struct s2io_nic *sp = (struct s2io_nic *)data;
4036
4037         alarm_intr_handler(sp);
4038         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4039 }
4040
4041 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4042 {
4043         int rxb_size, level;
4044
4045         if (!sp->lro) {
4046                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4047                 level = rx_buffer_level(sp, rxb_size, rng_n);
4048
4049                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4050                         int ret;
4051                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4052                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4053                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4054                                 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4055                                           __FUNCTION__);
4056                                 clear_bit(0, (&sp->tasklet_status));
4057                                 return -1;
4058                         }
4059                         clear_bit(0, (&sp->tasklet_status));
4060                 } else if (level == LOW)
4061                         tasklet_schedule(&sp->task);
4062
4063         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4064                         DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4065                         DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4066         }
4067         return 0;
4068 }
4069
4070 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4071 {
4072         struct ring_info *ring = (struct ring_info *)dev_id;
4073         struct s2io_nic *sp = ring->nic;
4074
4075         atomic_inc(&sp->isr_cnt);
4076
4077         rx_intr_handler(ring);
4078         s2io_chk_rx_buffers(sp, ring->ring_no);
4079
4080         atomic_dec(&sp->isr_cnt);
4081         return IRQ_HANDLED;
4082 }
4083
4084 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4085 {
4086         struct fifo_info *fifo = (struct fifo_info *)dev_id;
4087         struct s2io_nic *sp = fifo->nic;
4088
4089         atomic_inc(&sp->isr_cnt);
4090         tx_intr_handler(fifo);
4091         atomic_dec(&sp->isr_cnt);
4092         return IRQ_HANDLED;
4093 }
4094 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4095 {
4096         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4097         u64 val64;
4098
4099         val64 = readq(&bar0->pic_int_status);
4100         if (val64 & PIC_INT_GPIO) {
4101                 val64 = readq(&bar0->gpio_int_reg);
4102                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4103                     (val64 & GPIO_INT_REG_LINK_UP)) {
4104                         /*
4105                          * This is unstable state so clear both up/down
4106                          * interrupt and adapter to re-evaluate the link state.
4107                          */
4108                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4109                         val64 |= GPIO_INT_REG_LINK_UP;
4110                         writeq(val64, &bar0->gpio_int_reg);
4111                         val64 = readq(&bar0->gpio_int_mask);
4112                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4113                                    GPIO_INT_MASK_LINK_DOWN);
4114                         writeq(val64, &bar0->gpio_int_mask);
4115                 }
4116                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4117                         val64 = readq(&bar0->adapter_status);
4118                                 /* Enable Adapter */
4119                         val64 = readq(&bar0->adapter_control);
4120                         val64 |= ADAPTER_CNTL_EN;
4121                         writeq(val64, &bar0->adapter_control);
4122                         val64 |= ADAPTER_LED_ON;
4123                         writeq(val64, &bar0->adapter_control);
4124                         if (!sp->device_enabled_once)
4125                                 sp->device_enabled_once = 1;
4126
4127                         s2io_link(sp, LINK_UP);
4128                         /*
4129                          * unmask link down interrupt and mask link-up
4130                          * intr
4131                          */
4132                         val64 = readq(&bar0->gpio_int_mask);
4133                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4134                         val64 |= GPIO_INT_MASK_LINK_UP;
4135                         writeq(val64, &bar0->gpio_int_mask);
4136
4137                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4138                         val64 = readq(&bar0->adapter_status);
4139                         s2io_link(sp, LINK_DOWN);
4140                         /* Link is down so unmaks link up interrupt */
4141                         val64 = readq(&bar0->gpio_int_mask);
4142                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4143                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4144                         writeq(val64, &bar0->gpio_int_mask);
4145
4146                         /* turn off LED */
4147                         val64 = readq(&bar0->adapter_control);
4148                         val64 = val64 &(~ADAPTER_LED_ON);
4149                         writeq(val64, &bar0->adapter_control);
4150                 }
4151         }
4152         val64 = readq(&bar0->gpio_int_mask);
4153 }
4154
4155 /**
4156  *  s2io_isr - ISR handler of the device .
4157  *  @irq: the irq of the device.
4158  *  @dev_id: a void pointer to the dev structure of the NIC.
4159  *  Description:  This function is the ISR handler of the device. It
4160  *  identifies the reason for the interrupt and calls the relevant
4161  *  service routines. As a contongency measure, this ISR allocates the
4162  *  recv buffers, if their numbers are below the panic value which is
4163  *  presently set to 25% of the original number of rcv buffers allocated.
4164  *  Return value:
4165  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4166  *   IRQ_NONE: will be returned if interrupt is not from our device
4167  */
4168 static irqreturn_t s2io_isr(int irq, void *dev_id)
4169 {
4170         struct net_device *dev = (struct net_device *) dev_id;
4171         struct s2io_nic *sp = dev->priv;
4172         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4173         int i;
4174         u64 reason = 0;
4175         struct mac_info *mac_control;
4176         struct config_param *config;
4177
4178         /* Pretend we handled any irq's from a disconnected card */
4179         if (pci_channel_offline(sp->pdev))
4180                 return IRQ_NONE;
4181
4182         atomic_inc(&sp->isr_cnt);
4183         mac_control = &sp->mac_control;
4184         config = &sp->config;
4185
4186         /*
4187          * Identify the cause for interrupt and call the appropriate
4188          * interrupt handler. Causes for the interrupt could be;
4189          * 1. Rx of packet.
4190          * 2. Tx complete.
4191          * 3. Link down.
4192          * 4. Error in any functional blocks of the NIC.
4193          */
4194         reason = readq(&bar0->general_int_status);
4195
4196         if (!reason) {
4197                 /* The interrupt was not raised by us. */
4198                 atomic_dec(&sp->isr_cnt);
4199                 return IRQ_NONE;
4200         }
4201         else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4202                 /* Disable device and get out */
4203                 atomic_dec(&sp->isr_cnt);
4204                 return IRQ_NONE;
4205         }
4206
4207         if (napi) {
4208                 if (reason & GEN_INTR_RXTRAFFIC) {
4209                         if ( likely ( netif_rx_schedule_prep(dev)) ) {
4210                                 __netif_rx_schedule(dev);
4211                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4212                         }
4213                         else
4214                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4215                 }
4216         } else {
4217                 /*
4218                  * Rx handler is called by default, without checking for the
4219                  * cause of interrupt.
4220                  * rx_traffic_int reg is an R1 register, writing all 1's
4221                  * will ensure that the actual interrupt causing bit get's
4222                  * cleared and hence a read can be avoided.
4223                  */
4224                 if (reason & GEN_INTR_RXTRAFFIC)
4225                         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4226
4227                 for (i = 0; i < config->rx_ring_num; i++) {
4228                         rx_intr_handler(&mac_control->rings[i]);
4229                 }
4230         }
4231
4232         /*
4233          * tx_traffic_int reg is an R1 register, writing all 1's
4234          * will ensure that the actual interrupt causing bit get's
4235          * cleared and hence a read can be avoided.
4236          */
4237         if (reason & GEN_INTR_TXTRAFFIC)
4238                 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4239
4240         for (i = 0; i < config->tx_fifo_num; i++)
4241                 tx_intr_handler(&mac_control->fifos[i]);
4242
4243         if (reason & GEN_INTR_TXPIC)
4244                 s2io_txpic_intr_handle(sp);
4245         /*
4246          * If the Rx buffer count is below the panic threshold then
4247          * reallocate the buffers from the interrupt handler itself,
4248          * else schedule a tasklet to reallocate the buffers.
4249          */
4250         if (!napi) {
4251                 for (i = 0; i < config->rx_ring_num; i++)
4252                         s2io_chk_rx_buffers(sp, i);
4253         }
4254
4255         writeq(0, &bar0->general_int_mask);
4256         readl(&bar0->general_int_status);
4257
4258         atomic_dec(&sp->isr_cnt);
4259         return IRQ_HANDLED;
4260 }
4261
4262 /**
4263  * s2io_updt_stats -
4264  */
4265 static void s2io_updt_stats(struct s2io_nic *sp)
4266 {
4267         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4268         u64 val64;
4269         int cnt = 0;
4270
4271         if (atomic_read(&sp->card_state) == CARD_UP) {
4272                 /* Apprx 30us on a 133 MHz bus */
4273                 val64 = SET_UPDT_CLICKS(10) |
4274                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4275                 writeq(val64, &bar0->stat_cfg);
4276                 do {
4277                         udelay(100);
4278                         val64 = readq(&bar0->stat_cfg);
4279                         if (!(val64 & BIT(0)))
4280                                 break;
4281                         cnt++;
4282                         if (cnt == 5)
4283                                 break; /* Updt failed */
4284                 } while(1);
4285         }
4286 }
4287
4288 /**
4289  *  s2io_get_stats - Updates the device statistics structure.
4290  *  @dev : pointer to the device structure.
4291  *  Description:
4292  *  This function updates the device statistics structure in the s2io_nic
4293  *  structure and returns a pointer to the same.
4294  *  Return value:
4295  *  pointer to the updated net_device_stats structure.
4296  */
4297
4298 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4299 {
4300         struct s2io_nic *sp = dev->priv;
4301         struct mac_info *mac_control;
4302         struct config_param *config;
4303
4304
4305         mac_control = &sp->mac_control;
4306         config = &sp->config;
4307
4308         /* Configure Stats for immediate updt */
4309         s2io_updt_stats(sp);
4310
4311         sp->stats.tx_packets =
4312                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4313         sp->stats.tx_errors =
4314                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4315         sp->stats.rx_errors =
4316                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4317         sp->stats.multicast =
4318                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4319         sp->stats.rx_length_errors =
4320                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4321
4322         return (&sp->stats);
4323 }
4324
4325 /**
4326  *  s2io_set_multicast - entry point for multicast address enable/disable.
4327  *  @dev : pointer to the device structure
4328  *  Description:
4329  *  This function is a driver entry point which gets called by the kernel
4330  *  whenever multicast addresses must be enabled/disabled. This also gets
4331  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4332  *  determine, if multicast address must be enabled or if promiscuous mode
4333  *  is to be disabled etc.
4334  *  Return value:
4335  *  void.
4336  */
4337
4338 static void s2io_set_multicast(struct net_device *dev)
4339 {
4340         int i, j, prev_cnt;
4341         struct dev_mc_list *mclist;
4342         struct s2io_nic *sp = dev->priv;
4343         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4344         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4345             0xfeffffffffffULL;
4346         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4347         void __iomem *add;
4348
4349         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4350                 /*  Enable all Multicast addresses */
4351                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4352                        &bar0->rmac_addr_data0_mem);
4353                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4354                        &bar0->rmac_addr_data1_mem);
4355                 val64 = RMAC_ADDR_CMD_MEM_WE |
4356                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4357                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4358                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4359                 /* Wait till command completes */
4360                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4361                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4362                                         S2IO_BIT_RESET);
4363
4364                 sp->m_cast_flg = 1;
4365                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4366         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4367                 /*  Disable all Multicast addresses */
4368                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4369                        &bar0->rmac_addr_data0_mem);
4370                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4371                        &bar0->rmac_addr_data1_mem);
4372                 val64 = RMAC_ADDR_CMD_MEM_WE |
4373                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4374                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4375                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4376                 /* Wait till command completes */
4377                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4378                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4379                                         S2IO_BIT_RESET);
4380
4381                 sp->m_cast_flg = 0;
4382                 sp->all_multi_pos = 0;
4383         }
4384
4385         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4386                 /*  Put the NIC into promiscuous mode */
4387                 add = &bar0->mac_cfg;
4388                 val64 = readq(&bar0->mac_cfg);
4389                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4390
4391                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4392                 writel((u32) val64, add);
4393                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4394                 writel((u32) (val64 >> 32), (add + 4));
4395
4396                 if (vlan_tag_strip != 1) {
4397                         val64 = readq(&bar0->rx_pa_cfg);
4398                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4399                         writeq(val64, &bar0->rx_pa_cfg);
4400                         vlan_strip_flag = 0;
4401                 }
4402
4403                 val64 = readq(&bar0->mac_cfg);
4404                 sp->promisc_flg = 1;
4405                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4406                           dev->name);
4407         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4408                 /*  Remove the NIC from promiscuous mode */
4409                 add = &bar0->mac_cfg;
4410                 val64 = readq(&bar0->mac_cfg);
4411                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4412
4413                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4414                 writel((u32) val64, add);
4415                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4416                 writel((u32) (val64 >> 32), (add + 4));
4417
4418                 if (vlan_tag_strip != 0) {
4419                         val64 = readq(&bar0->rx_pa_cfg);
4420                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4421                         writeq(val64, &bar0->rx_pa_cfg);
4422                         vlan_strip_flag = 1;
4423                 }
4424
4425                 val64 = readq(&bar0->mac_cfg);
4426                 sp->promisc_flg = 0;
4427                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4428                           dev->name);
4429         }
4430
4431         /*  Update individual M_CAST address list */
4432         if ((!sp->m_cast_flg) && dev->mc_count) {
4433                 if (dev->mc_count >
4434                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4435                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4436                                   dev->name);
4437                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4438                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4439                         return;
4440                 }
4441
4442                 prev_cnt = sp->mc_addr_count;
4443                 sp->mc_addr_count = dev->mc_count;
4444
4445                 /* Clear out the previous list of Mc in the H/W. */
4446                 for (i = 0; i < prev_cnt; i++) {
4447                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4448                                &bar0->rmac_addr_data0_mem);
4449                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4450                                 &bar0->rmac_addr_data1_mem);
4451                         val64 = RMAC_ADDR_CMD_MEM_WE |
4452                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4453                             RMAC_ADDR_CMD_MEM_OFFSET
4454                             (MAC_MC_ADDR_START_OFFSET + i);
4455                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4456
4457                         /* Wait for command completes */
4458                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4459                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4460                                         S2IO_BIT_RESET)) {
4461                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4462                                           dev->name);
4463                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4464                                 return;
4465                         }
4466                 }
4467
4468                 /* Create the new Rx filter list and update the same in H/W. */
4469                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4470                      i++, mclist = mclist->next) {
4471                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4472                                ETH_ALEN);
4473                         mac_addr = 0;
4474                         for (j = 0; j < ETH_ALEN; j++) {
4475                                 mac_addr |= mclist->dmi_addr[j];
4476                                 mac_addr <<= 8;
4477                         }
4478                         mac_addr >>= 8;
4479                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4480                                &bar0->rmac_addr_data0_mem);
4481                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4482                                 &bar0->rmac_addr_data1_mem);
4483                         val64 = RMAC_ADDR_CMD_MEM_WE |
4484                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4485                             RMAC_ADDR_CMD_MEM_OFFSET
4486                             (i + MAC_MC_ADDR_START_OFFSET);
4487                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4488
4489                         /* Wait for command completes */
4490                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4491                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4492                                         S2IO_BIT_RESET)) {
4493                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4494                                           dev->name);
4495                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4496                                 return;
4497                         }
4498                 }
4499         }
4500 }
4501
4502 /**
4503  *  s2io_set_mac_addr - Programs the Xframe mac address
4504  *  @dev : pointer to the device structure.
4505  *  @addr: a uchar pointer to the new mac address which is to be set.
4506  *  Description : This procedure will program the Xframe to receive
4507  *  frames with new Mac Address
4508  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4509  *  as defined in errno.h file on failure.
4510  */
4511
4512 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4513 {
4514         struct s2io_nic *sp = dev->priv;
4515         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4516         register u64 val64, mac_addr = 0;
4517         int i;
4518         u64 old_mac_addr = 0;
4519
4520         /*
4521          * Set the new MAC address as the new unicast filter and reflect this
4522          * change on the device address registered with the OS. It will be
4523          * at offset 0.
4524          */
4525         for (i = 0; i < ETH_ALEN; i++) {
4526                 mac_addr <<= 8;
4527                 mac_addr |= addr[i];
4528                 old_mac_addr <<= 8;
4529                 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4530         }
4531
4532         if(0 == mac_addr)
4533                 return SUCCESS;
4534
4535         /* Update the internal structure with this new mac address */
4536         if(mac_addr != old_mac_addr) {
4537                 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4538                 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4539                 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4540                 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4541                 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4542                 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4543                 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
4544         }
4545
4546         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4547                &bar0->rmac_addr_data0_mem);
4548
4549         val64 =
4550             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4551             RMAC_ADDR_CMD_MEM_OFFSET(0);
4552         writeq(val64, &bar0->rmac_addr_cmd_mem);
4553         /* Wait till command completes */
4554         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4555                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
4556                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4557                 return FAILURE;
4558         }
4559
4560         return SUCCESS;
4561 }
4562
4563 /**
4564  * s2io_ethtool_sset - Sets different link parameters.
4565  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4566  * @info: pointer to the structure with parameters given by ethtool to set
4567  * link information.
4568  * Description:
4569  * The function sets different link parameters provided by the user onto
4570  * the NIC.
4571  * Return value:
4572  * 0 on success.
4573 */
4574
4575 static int s2io_ethtool_sset(struct net_device *dev,
4576                              struct ethtool_cmd *info)
4577 {
4578         struct s2io_nic *sp = dev->priv;
4579         if ((info->autoneg == AUTONEG_ENABLE) ||
4580             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4581                 return -EINVAL;
4582         else {
4583                 s2io_close(sp->dev);
4584                 s2io_open(sp->dev);
4585         }
4586
4587         return 0;
4588 }
4589
4590 /**
4591  * s2io_ethtol_gset - Return link specific information.
4592  * @sp : private member of the device structure, pointer to the
4593  *      s2io_nic structure.
4594  * @info : pointer to the structure with parameters given by ethtool
4595  * to return link information.
4596  * Description:
4597  * Returns link specific information like speed, duplex etc.. to ethtool.
4598  * Return value :
4599  * return 0 on success.
4600  */
4601
4602 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4603 {
4604         struct s2io_nic *sp = dev->priv;
4605         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4606         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4607         info->port = PORT_FIBRE;
4608         /* info->transceiver?? TODO */
4609
4610         if (netif_carrier_ok(sp->dev)) {
4611                 info->speed = 10000;
4612                 info->duplex = DUPLEX_FULL;
4613         } else {
4614                 info->speed = -1;
4615                 info->duplex = -1;
4616         }
4617
4618         info->autoneg = AUTONEG_DISABLE;
4619         return 0;
4620 }
4621
4622 /**
4623  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4624  * @sp : private member of the device structure, which is a pointer to the
4625  * s2io_nic structure.
4626  * @info : pointer to the structure with parameters given by ethtool to
4627  * return driver information.
4628  * Description:
4629  * Returns driver specefic information like name, version etc.. to ethtool.
4630  * Return value:
4631  *  void
4632  */
4633
4634 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4635                                   struct ethtool_drvinfo *info)
4636 {
4637         struct s2io_nic *sp = dev->priv;
4638
4639         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4640         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4641         strncpy(info->fw_version, "", sizeof(info->fw_version));
4642         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4643         info->regdump_len = XENA_REG_SPACE;
4644         info->eedump_len = XENA_EEPROM_SPACE;
4645         info->testinfo_len = S2IO_TEST_LEN;
4646
4647         if (sp->device_type == XFRAME_I_DEVICE)
4648                 info->n_stats = XFRAME_I_STAT_LEN;
4649         else
4650                 info->n_stats = XFRAME_II_STAT_LEN;
4651 }
4652
4653 /**
4654  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4655  *  @sp: private member of the device structure, which is a pointer to the
4656  *  s2io_nic structure.
4657  *  @regs : pointer to the structure with parameters given by ethtool for
4658  *  dumping the registers.
4659  *  @reg_space: The input argumnet into which all the registers are dumped.
4660  *  Description:
4661  *  Dumps the entire register space of xFrame NIC into the user given
4662  *  buffer area.
4663  * Return value :
4664  * void .
4665 */
4666
4667 static void s2io_ethtool_gregs(struct net_device *dev,
4668                                struct ethtool_regs *regs, void *space)
4669 {
4670         int i;
4671         u64 reg;
4672         u8 *reg_space = (u8 *) space;
4673         struct s2io_nic *sp = dev->priv;
4674
4675         regs->len = XENA_REG_SPACE;
4676         regs->version = sp->pdev->subsystem_device;
4677
4678         for (i = 0; i < regs->len; i += 8) {
4679                 reg = readq(sp->bar0 + i);
4680                 memcpy((reg_space + i), &reg, 8);
4681         }
4682 }
4683
4684 /**
4685  *  s2io_phy_id  - timer function that alternates adapter LED.
4686  *  @data : address of the private member of the device structure, which
4687  *  is a pointer to the s2io_nic structure, provided as an u32.
4688  * Description: This is actually the timer function that alternates the
4689  * adapter LED bit of the adapter control bit to set/reset every time on
4690  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4691  *  once every second.
4692 */
4693 static void s2io_phy_id(unsigned long data)
4694 {
4695         struct s2io_nic *sp = (struct s2io_nic *) data;
4696         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4697         u64 val64 = 0;
4698         u16 subid;
4699
4700         subid = sp->pdev->subsystem_device;
4701         if ((sp->device_type == XFRAME_II_DEVICE) ||
4702                    ((subid & 0xFF) >= 0x07)) {
4703                 val64 = readq(&bar0->gpio_control);
4704                 val64 ^= GPIO_CTRL_GPIO_0;
4705                 writeq(val64, &bar0->gpio_control);
4706         } else {
4707                 val64 = readq(&bar0->adapter_control);
4708                 val64 ^= ADAPTER_LED_ON;
4709                 writeq(val64, &bar0->adapter_control);
4710         }
4711
4712         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4713 }
4714
4715 /**
4716  * s2io_ethtool_idnic - To physically identify the nic on the system.
4717  * @sp : private member of the device structure, which is a pointer to the
4718  * s2io_nic structure.
4719  * @id : pointer to the structure with identification parameters given by
4720  * ethtool.
4721  * Description: Used to physically identify the NIC on the system.
4722  * The Link LED will blink for a time specified by the user for
4723  * identification.
4724  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4725  * identification is possible only if it's link is up.
4726  * Return value:
4727  * int , returns 0 on success
4728  */
4729
4730 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4731 {
4732         u64 val64 = 0, last_gpio_ctrl_val;
4733         struct s2io_nic *sp = dev->priv;
4734         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4735         u16 subid;
4736
4737         subid = sp->pdev->subsystem_device;
4738         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4739         if ((sp->device_type == XFRAME_I_DEVICE) &&
4740                 ((subid & 0xFF) < 0x07)) {
4741                 val64 = readq(&bar0->adapter_control);
4742                 if (!(val64 & ADAPTER_CNTL_EN)) {
4743                         printk(KERN_ERR
4744                                "Adapter Link down, cannot blink LED\n");
4745                         return -EFAULT;
4746                 }
4747         }
4748         if (sp->id_timer.function == NULL) {
4749                 init_timer(&sp->id_timer);
4750                 sp->id_timer.function = s2io_phy_id;
4751                 sp->id_timer.data = (unsigned long) sp;
4752         }
4753         mod_timer(&sp->id_timer, jiffies);
4754         if (data)
4755                 msleep_interruptible(data * HZ);
4756         else
4757                 msleep_interruptible(MAX_FLICKER_TIME);
4758         del_timer_sync(&sp->id_timer);
4759
4760         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4761                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4762                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4763         }
4764
4765         return 0;
4766 }
4767
4768 static void s2io_ethtool_gringparam(struct net_device *dev,
4769                                     struct ethtool_ringparam *ering)
4770 {
4771         struct s2io_nic *sp = dev->priv;
4772         int i,tx_desc_count=0,rx_desc_count=0;
4773
4774         if (sp->rxd_mode == RXD_MODE_1)
4775                 ering->rx_max_pending = MAX_RX_DESC_1;
4776         else if (sp->rxd_mode == RXD_MODE_3B)
4777                 ering->rx_max_pending = MAX_RX_DESC_2;
4778
4779         ering->tx_max_pending = MAX_TX_DESC;
4780         for (i = 0 ; i < sp->config.tx_fifo_num ; i++) {
4781                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
4782         }
4783         DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
4784         ering->tx_pending = tx_desc_count;
4785         rx_desc_count = 0;
4786         for (i = 0 ; i < sp->config.rx_ring_num ; i++) {
4787                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
4788         }
4789         ering->rx_pending = rx_desc_count;
4790
4791         ering->rx_mini_max_pending = 0;
4792         ering->rx_mini_pending = 0;
4793         if(sp->rxd_mode == RXD_MODE_1)
4794                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
4795         else if (sp->rxd_mode == RXD_MODE_3B)
4796                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
4797         ering->rx_jumbo_pending = rx_desc_count;
4798 }
4799
4800 /**
4801  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4802  * @sp : private member of the device structure, which is a pointer to the
4803  *      s2io_nic structure.
4804  * @ep : pointer to the structure with pause parameters given by ethtool.
4805  * Description:
4806  * Returns the Pause frame generation and reception capability of the NIC.
4807  * Return value:
4808  *  void
4809  */
4810 static void s2io_ethtool_getpause_data(struct net_device *dev,
4811                                        struct ethtool_pauseparam *ep)
4812 {
4813         u64 val64;
4814         struct s2io_nic *sp = dev->priv;
4815         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4816
4817         val64 = readq(&bar0->rmac_pause_cfg);
4818         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4819                 ep->tx_pause = TRUE;
4820         if (val64 & RMAC_PAUSE_RX_ENABLE)
4821                 ep->rx_pause = TRUE;
4822         ep->autoneg = FALSE;
4823 }
4824
4825 /**
4826  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4827  * @sp : private member of the device structure, which is a pointer to the
4828  *      s2io_nic structure.
4829  * @ep : pointer to the structure with pause parameters given by ethtool.
4830  * Description:
4831  * It can be used to set or reset Pause frame generation or reception
4832  * support of the NIC.
4833  * Return value:
4834  * int, returns 0 on Success
4835  */
4836
4837 static int s2io_ethtool_setpause_data(struct net_device *dev,
4838                                struct ethtool_pauseparam *ep)
4839 {
4840         u64 val64;
4841         struct s2io_nic *sp = dev->priv;
4842         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4843
4844         val64 = readq(&bar0->rmac_pause_cfg);
4845         if (ep->tx_pause)
4846                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4847         else
4848                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4849         if (ep->rx_pause)
4850                 val64 |= RMAC_PAUSE_RX_ENABLE;
4851         else
4852                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4853         writeq(val64, &bar0->rmac_pause_cfg);
4854         return 0;
4855 }
4856
4857 /**
4858  * read_eeprom - reads 4 bytes of data from user given offset.
4859  * @sp : private member of the device structure, which is a pointer to the
4860  *      s2io_nic structure.
4861  * @off : offset at which the data must be written
4862  * @data : Its an output parameter where the data read at the given
4863  *      offset is stored.
4864  * Description:
4865  * Will read 4 bytes of data from the user given offset and return the
4866  * read data.
4867  * NOTE: Will allow to read only part of the EEPROM visible through the
4868  *   I2C bus.
4869  * Return value:
4870  *  -1 on failure and 0 on success.
4871  */
4872
4873 #define S2IO_DEV_ID             5
4874 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
4875 {
4876         int ret = -1;
4877         u32 exit_cnt = 0;
4878         u64 val64;
4879         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4880
4881         if (sp->device_type == XFRAME_I_DEVICE) {
4882                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4883                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4884                     I2C_CONTROL_CNTL_START;
4885                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4886
4887                 while (exit_cnt < 5) {
4888                         val64 = readq(&bar0->i2c_control);
4889                         if (I2C_CONTROL_CNTL_END(val64)) {
4890                                 *data = I2C_CONTROL_GET_DATA(val64);
4891                                 ret = 0;
4892                                 break;
4893                         }
4894                         msleep(50);
4895                         exit_cnt++;
4896                 }
4897         }
4898
4899         if (sp->device_type == XFRAME_II_DEVICE) {
4900                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4901                         SPI_CONTROL_BYTECNT(0x3) |
4902                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4903                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4904                 val64 |= SPI_CONTROL_REQ;
4905                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4906                 while (exit_cnt < 5) {
4907                         val64 = readq(&bar0->spi_control);
4908                         if (val64 & SPI_CONTROL_NACK) {
4909                                 ret = 1;
4910                                 break;
4911                         } else if (val64 & SPI_CONTROL_DONE) {
4912                                 *data = readq(&bar0->spi_data);
4913                                 *data &= 0xffffff;
4914                                 ret = 0;
4915                                 break;
4916                         }
4917                         msleep(50);
4918                         exit_cnt++;
4919                 }
4920         }
4921         return ret;
4922 }
4923
4924 /**
4925  *  write_eeprom - actually writes the relevant part of the data value.
4926  *  @sp : private member of the device structure, which is a pointer to the
4927  *       s2io_nic structure.
4928  *  @off : offset at which the data must be written
4929  *  @data : The data that is to be written
4930  *  @cnt : Number of bytes of the data that are actually to be written into
4931  *  the Eeprom. (max of 3)
4932  * Description:
4933  *  Actually writes the relevant part of the data value into the Eeprom
4934  *  through the I2C bus.
4935  * Return value:
4936  *  0 on success, -1 on failure.
4937  */
4938
4939 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
4940 {
4941         int exit_cnt = 0, ret = -1;
4942         u64 val64;
4943         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4944
4945         if (sp->device_type == XFRAME_I_DEVICE) {
4946                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4947                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4948                     I2C_CONTROL_CNTL_START;
4949                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4950
4951                 while (exit_cnt < 5) {
4952                         val64 = readq(&bar0->i2c_control);
4953                         if (I2C_CONTROL_CNTL_END(val64)) {
4954                                 if (!(val64 & I2C_CONTROL_NACK))
4955                                         ret = 0;
4956                                 break;
4957                         }
4958                         msleep(50);
4959                         exit_cnt++;
4960                 }
4961         }
4962
4963         if (sp->device_type == XFRAME_II_DEVICE) {
4964                 int write_cnt = (cnt == 8) ? 0 : cnt;
4965                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4966
4967                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4968                         SPI_CONTROL_BYTECNT(write_cnt) |
4969                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4970                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4971                 val64 |= SPI_CONTROL_REQ;
4972                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4973                 while (exit_cnt < 5) {
4974                         val64 = readq(&bar0->spi_control);
4975                         if (val64 & SPI_CONTROL_NACK) {
4976                                 ret = 1;
4977                                 break;
4978                         } else if (val64 & SPI_CONTROL_DONE) {
4979                                 ret = 0;
4980                                 break;
4981                         }
4982                         msleep(50);
4983                         exit_cnt++;
4984                 }
4985         }
4986         return ret;
4987 }
4988 static void s2io_vpd_read(struct s2io_nic *nic)
4989 {
4990         u8 *vpd_data;
4991         u8 data;
4992         int i=0, cnt, fail = 0;
4993         int vpd_addr = 0x80;
4994
4995         if (nic->device_type == XFRAME_II_DEVICE) {
4996                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4997                 vpd_addr = 0x80;
4998         }
4999         else {
5000                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5001                 vpd_addr = 0x50;
5002         }
5003         strcpy(nic->serial_num, "NOT AVAILABLE");
5004
5005         vpd_data = kmalloc(256, GFP_KERNEL);
5006         if (!vpd_data) {
5007                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5008                 return;
5009         }
5010         nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5011
5012         for (i = 0; i < 256; i +=4 ) {
5013                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5014                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5015                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5016                 for (cnt = 0; cnt <5; cnt++) {
5017                         msleep(2);
5018                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5019                         if (data == 0x80)
5020                                 break;
5021                 }
5022                 if (cnt >= 5) {
5023                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5024                         fail = 1;
5025                         break;
5026                 }
5027                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5028                                       (u32 *)&vpd_data[i]);
5029         }
5030
5031         if(!fail) {
5032                 /* read serial number of adapter */
5033                 for (cnt = 0; cnt < 256; cnt++) {
5034                 if ((vpd_data[cnt] == 'S') &&
5035                         (vpd_data[cnt+1] == 'N') &&
5036                         (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5037                                 memset(nic->serial_num, 0, VPD_STRING_LEN);
5038                                 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5039                                         vpd_data[cnt+2]);
5040                                 break;
5041                         }
5042                 }
5043         }
5044
5045         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5046                 memset(nic->product_name, 0, vpd_data[1]);
5047                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5048         }
5049         kfree(vpd_data);
5050         nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5051 }
5052
5053 /**
5054  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5055  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5056  *  @eeprom : pointer to the user level structure provided by ethtool,
5057  *  containing all relevant information.
5058  *  @data_buf : user defined value to be written into Eeprom.
5059  *  Description: Reads the values stored in the Eeprom at given offset
5060  *  for a given length. Stores these values int the input argument data
5061  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5062  *  Return value:
5063  *  int  0 on success
5064  */
5065
5066 static int s2io_ethtool_geeprom(struct net_device *dev,
5067                          struct ethtool_eeprom *eeprom, u8 * data_buf)
5068 {
5069         u32 i, valid;
5070         u64 data;
5071         struct s2io_nic *sp = dev->priv;
5072
5073         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5074
5075         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5076                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5077
5078         for (i = 0; i < eeprom->len; i += 4) {
5079                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5080                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5081                         return -EFAULT;
5082                 }
5083                 valid = INV(data);
5084                 memcpy((data_buf + i), &valid, 4);
5085         }
5086         return 0;
5087 }
5088
5089 /**
5090  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5091  *  @sp : private member of the device structure, which is a pointer to the
5092  *  s2io_nic structure.
5093  *  @eeprom : pointer to the user level structure provided by ethtool,
5094  *  containing all relevant information.
5095  *  @data_buf ; user defined value to be written into Eeprom.
5096  *  Description:
5097  *  Tries to write the user provided value in the Eeprom, at the offset
5098  *  given by the user.
5099  *  Return value:
5100  *  0 on success, -EFAULT on failure.
5101  */
5102
5103 static int s2io_ethtool_seeprom(struct net_device *dev,
5104                                 struct ethtool_eeprom *eeprom,
5105                                 u8 * data_buf)
5106 {
5107         int len = eeprom->len, cnt = 0;
5108         u64 valid = 0, data;
5109         struct s2io_nic *sp = dev->priv;
5110
5111         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5112                 DBG_PRINT(ERR_DBG,
5113                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5114                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5115                           eeprom->magic);
5116                 return -EFAULT;
5117         }
5118
5119         while (len) {
5120                 data = (u32) data_buf[cnt] & 0x000000FF;
5121                 if (data) {
5122                         valid = (u32) (data << 24);
5123                 } else
5124                         valid = data;
5125
5126                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5127                         DBG_PRINT(ERR_DBG,
5128                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5129                         DBG_PRINT(ERR_DBG,
5130                                   "write into the specified offset\n");
5131                         return -EFAULT;
5132                 }
5133                 cnt++;
5134                 len--;
5135         }
5136
5137         return 0;
5138 }
5139
5140 /**
5141  * s2io_register_test - reads and writes into all clock domains.
5142  * @sp : private member of the device structure, which is a pointer to the
5143  * s2io_nic structure.
5144  * @data : variable that returns the result of each of the test conducted b
5145  * by the driver.
5146  * Description:
5147  * Read and write into all clock domains. The NIC has 3 clock domains,
5148  * see that registers in all the three regions are accessible.
5149  * Return value:
5150  * 0 on success.
5151  */
5152
5153 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5154 {
5155         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5156         u64 val64 = 0, exp_val;
5157         int fail = 0;
5158
5159         val64 = readq(&bar0->pif_rd_swapper_fb);
5160         if (val64 != 0x123456789abcdefULL) {
5161                 fail = 1;
5162                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5163         }
5164
5165         val64 = readq(&bar0->rmac_pause_cfg);
5166         if (val64 != 0xc000ffff00000000ULL) {
5167                 fail = 1;
5168                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5169         }
5170
5171         val64 = readq(&bar0->rx_queue_cfg);
5172         if (sp->device_type == XFRAME_II_DEVICE)
5173                 exp_val = 0x0404040404040404ULL;
5174         else
5175                 exp_val = 0x0808080808080808ULL;
5176         if (val64 != exp_val) {
5177                 fail = 1;
5178                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5179         }
5180
5181         val64 = readq(&bar0->xgxs_efifo_cfg);
5182         if (val64 != 0x000000001923141EULL) {
5183                 fail = 1;
5184                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5185         }
5186
5187         val64 = 0x5A5A5A5A5A5A5A5AULL;
5188         writeq(val64, &bar0->xmsi_data);
5189         val64 = readq(&bar0->xmsi_data);
5190         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5191                 fail = 1;
5192                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5193         }
5194
5195         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5196         writeq(val64, &bar0->xmsi_data);
5197         val64 = readq(&bar0->xmsi_data);
5198         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5199                 fail = 1;
5200                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5201         }
5202
5203         *data = fail;
5204         return fail;
5205 }
5206
5207 /**
5208  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5209  * @sp : private member of the device structure, which is a pointer to the
5210  * s2io_nic structure.
5211  * @data:variable that returns the result of each of the test conducted by
5212  * the driver.
5213  * Description:
5214  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5215  * register.
5216  * Return value:
5217  * 0 on success.
5218  */
5219
5220 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5221 {
5222         int fail = 0;
5223         u64 ret_data, org_4F0, org_7F0;
5224         u8 saved_4F0 = 0, saved_7F0 = 0;
5225         struct net_device *dev = sp->dev;
5226
5227         /* Test Write Error at offset 0 */
5228         /* Note that SPI interface allows write access to all areas
5229          * of EEPROM. Hence doing all negative testing only for Xframe I.
5230          */
5231         if (sp->device_type == XFRAME_I_DEVICE)
5232                 if (!write_eeprom(sp, 0, 0, 3))
5233                         fail = 1;
5234
5235         /* Save current values at offsets 0x4F0 and 0x7F0 */
5236         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5237                 saved_4F0 = 1;
5238         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5239                 saved_7F0 = 1;
5240
5241         /* Test Write at offset 4f0 */
5242         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5243                 fail = 1;
5244         if (read_eeprom(sp, 0x4F0, &ret_data))
5245                 fail = 1;
5246
5247         if (ret_data != 0x012345) {
5248                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5249                         "Data written %llx Data read %llx\n",
5250                         dev->name, (unsigned long long)0x12345,
5251                         (unsigned long long)ret_data);
5252                 fail = 1;
5253         }
5254
5255         /* Reset the EEPROM data go FFFF */
5256         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5257
5258         /* Test Write Request Error at offset 0x7c */
5259         if (sp->device_type == XFRAME_I_DEVICE)
5260                 if (!write_eeprom(sp, 0x07C, 0, 3))
5261                         fail = 1;
5262
5263         /* Test Write Request at offset 0x7f0 */
5264         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5265                 fail = 1;
5266         if (read_eeprom(sp, 0x7F0, &ret_data))
5267                 fail = 1;
5268
5269         if (ret_data != 0x012345) {
5270                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5271                         "Data written %llx Data read %llx\n",
5272                         dev->name, (unsigned long long)0x12345,
5273                         (unsigned long long)ret_data);
5274                 fail = 1;
5275         }
5276
5277         /* Reset the EEPROM data go FFFF */
5278         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5279
5280         if (sp->device_type == XFRAME_I_DEVICE) {
5281                 /* Test Write Error at offset 0x80 */
5282                 if (!write_eeprom(sp, 0x080, 0, 3))
5283                         fail = 1;
5284
5285                 /* Test Write Error at offset 0xfc */
5286                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5287                         fail = 1;
5288
5289                 /* Test Write Error at offset 0x100 */
5290                 if (!write_eeprom(sp, 0x100, 0, 3))
5291                         fail = 1;
5292
5293                 /* Test Write Error at offset 4ec */
5294                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5295                         fail = 1;
5296         }
5297
5298         /* Restore values at offsets 0x4F0 and 0x7F0 */
5299         if (saved_4F0)
5300                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5301         if (saved_7F0)
5302                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5303
5304         *data = fail;
5305         return fail;
5306 }
5307
5308 /**
5309  * s2io_bist_test - invokes the MemBist test of the card .
5310  * @sp : private member of the device structure, which is a pointer to the
5311  * s2io_nic structure.
5312  * @data:variable that returns the result of each of the test conducted by
5313  * the driver.
5314  * Description:
5315  * This invokes the MemBist test of the card. We give around
5316  * 2 secs time for the Test to complete. If it's still not complete
5317  * within this peiod, we consider that the test failed.
5318  * Return value:
5319  * 0 on success and -1 on failure.
5320  */
5321
5322 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5323 {
5324         u8 bist = 0;
5325         int cnt = 0, ret = -1;
5326
5327         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5328         bist |= PCI_BIST_START;
5329         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5330
5331         while (cnt < 20) {
5332                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5333                 if (!(bist & PCI_BIST_START)) {
5334                         *data = (bist & PCI_BIST_CODE_MASK);
5335                         ret = 0;
5336                         break;
5337                 }
5338                 msleep(100);
5339                 cnt++;
5340         }
5341
5342         return ret;
5343 }
5344
5345 /**
5346  * s2io-link_test - verifies the link state of the nic
5347  * @sp ; private member of the device structure, which is a pointer to the
5348  * s2io_nic structure.
5349  * @data: variable that returns the result of each of the test conducted by
5350  * the driver.
5351  * Description:
5352  * The function verifies the link state of the NIC and updates the input
5353  * argument 'data' appropriately.
5354  * Return value:
5355  * 0 on success.
5356  */
5357
5358 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5359 {
5360         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5361         u64 val64;
5362
5363         val64 = readq(&bar0->adapter_status);
5364         if(!(LINK_IS_UP(val64)))
5365                 *data = 1;
5366         else
5367                 *data = 0;
5368
5369         return *data;
5370 }
5371
5372 /**
5373  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5374  * @sp - private member of the device structure, which is a pointer to the
5375  * s2io_nic structure.
5376  * @data - variable that returns the result of each of the test
5377  * conducted by the driver.
5378  * Description:
5379  *  This is one of the offline test that tests the read and write
5380  *  access to the RldRam chip on the NIC.
5381  * Return value:
5382  *  0 on success.
5383  */
5384
5385 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5386 {
5387         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5388         u64 val64;
5389         int cnt, iteration = 0, test_fail = 0;
5390
5391         val64 = readq(&bar0->adapter_control);
5392         val64 &= ~ADAPTER_ECC_EN;
5393         writeq(val64, &bar0->adapter_control);
5394
5395         val64 = readq(&bar0->mc_rldram_test_ctrl);
5396         val64 |= MC_RLDRAM_TEST_MODE;
5397         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5398
5399         val64 = readq(&bar0->mc_rldram_mrs);
5400         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5401         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5402
5403         val64 |= MC_RLDRAM_MRS_ENABLE;
5404         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5405
5406         while (iteration < 2) {
5407                 val64 = 0x55555555aaaa0000ULL;
5408                 if (iteration == 1) {
5409                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5410                 }
5411                 writeq(val64, &bar0->mc_rldram_test_d0);
5412
5413                 val64 = 0xaaaa5a5555550000ULL;
5414                 if (iteration == 1) {
5415                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5416                 }
5417                 writeq(val64, &bar0->mc_rldram_test_d1);
5418
5419                 val64 = 0x55aaaaaaaa5a0000ULL;
5420                 if (iteration == 1) {
5421                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5422                 }
5423                 writeq(val64, &bar0->mc_rldram_test_d2);
5424
5425                 val64 = (u64) (0x0000003ffffe0100ULL);
5426                 writeq(val64, &bar0->mc_rldram_test_add);
5427
5428                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5429                         MC_RLDRAM_TEST_GO;
5430                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5431
5432                 for (cnt = 0; cnt < 5; cnt++) {
5433                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5434                         if (val64 & MC_RLDRAM_TEST_DONE)
5435                                 break;
5436                         msleep(200);
5437                 }
5438
5439                 if (cnt == 5)
5440                         break;
5441
5442                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5443                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5444
5445                 for (cnt = 0; cnt < 5; cnt++) {
5446                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5447                         if (val64 & MC_RLDRAM_TEST_DONE)
5448                                 break;
5449                         msleep(500);
5450                 }
5451
5452                 if (cnt == 5)
5453                         break;
5454
5455                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5456                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5457                         test_fail = 1;
5458
5459                 iteration++;
5460         }
5461
5462         *data = test_fail;
5463
5464         /* Bring the adapter out of test mode */
5465         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5466
5467         return test_fail;
5468 }
5469
5470 /**
5471  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5472  *  @sp : private member of the device structure, which is a pointer to the
5473  *  s2io_nic structure.
5474  *  @ethtest : pointer to a ethtool command specific structure that will be
5475  *  returned to the user.
5476  *  @data : variable that returns the result of each of the test
5477  * conducted by the driver.
5478  * Description:
5479  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5480  *  the health of the card.
5481  * Return value:
5482  *  void
5483  */
5484
5485 static void s2io_ethtool_test(struct net_device *dev,
5486                               struct ethtool_test *ethtest,
5487                               uint64_t * data)
5488 {
5489         struct s2io_nic *sp = dev->priv;
5490         int orig_state = netif_running(sp->dev);
5491
5492         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5493                 /* Offline Tests. */
5494                 if (orig_state)
5495                         s2io_close(sp->dev);
5496
5497                 if (s2io_register_test(sp, &data[0]))
5498                         ethtest->flags |= ETH_TEST_FL_FAILED;
5499
5500                 s2io_reset(sp);
5501
5502                 if (s2io_rldram_test(sp, &data[3]))
5503                         ethtest->flags |= ETH_TEST_FL_FAILED;
5504
5505                 s2io_reset(sp);
5506
5507                 if (s2io_eeprom_test(sp, &data[1]))
5508                         ethtest->flags |= ETH_TEST_FL_FAILED;
5509
5510                 if (s2io_bist_test(sp, &data[4]))
5511                         ethtest->flags |= ETH_TEST_FL_FAILED;
5512
5513                 if (orig_state)
5514                         s2io_open(sp->dev);
5515
5516                 data[2] = 0;
5517         } else {
5518                 /* Online Tests. */
5519                 if (!orig_state) {
5520                         DBG_PRINT(ERR_DBG,
5521                                   "%s: is not up, cannot run test\n",
5522                                   dev->name);
5523                         data[0] = -1;
5524                         data[1] = -1;
5525                         data[2] = -1;
5526                         data[3] = -1;
5527                         data[4] = -1;
5528                 }
5529
5530                 if (s2io_link_test(sp, &data[2]))
5531                         ethtest->flags |= ETH_TEST_FL_FAILED;
5532
5533                 data[0] = 0;
5534                 data[1] = 0;
5535                 data[3] = 0;
5536                 data[4] = 0;
5537         }
5538 }
5539
5540 static void s2io_get_ethtool_stats(struct net_device *dev,
5541                                    struct ethtool_stats *estats,
5542                                    u64 * tmp_stats)
5543 {
5544         int i = 0;
5545         struct s2io_nic *sp = dev->priv;
5546         struct stat_block *stat_info = sp->mac_control.stats_info;
5547
5548         s2io_updt_stats(sp);
5549         tmp_stats[i++] =
5550                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5551                 le32_to_cpu(stat_info->tmac_frms);
5552         tmp_stats[i++] =
5553                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5554                 le32_to_cpu(stat_info->tmac_data_octets);
5555         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5556         tmp_stats[i++] =
5557                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5558                 le32_to_cpu(stat_info->tmac_mcst_frms);
5559         tmp_stats[i++] =
5560                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5561                 le32_to_cpu(stat_info->tmac_bcst_frms);
5562         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5563         tmp_stats[i++] =
5564                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5565                 le32_to_cpu(stat_info->tmac_ttl_octets);
5566         tmp_stats[i++] =
5567                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5568                 le32_to_cpu(stat_info->tmac_ucst_frms);
5569         tmp_stats[i++] =
5570                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5571                 le32_to_cpu(stat_info->tmac_nucst_frms);
5572         tmp_stats[i++] =
5573                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5574                 le32_to_cpu(stat_info->tmac_any_err_frms);
5575         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5576         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5577         tmp_stats[i++] =
5578                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5579                 le32_to_cpu(stat_info->tmac_vld_ip);
5580         tmp_stats[i++] =
5581                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5582                 le32_to_cpu(stat_info->tmac_drop_ip);
5583         tmp_stats[i++] =
5584                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5585                 le32_to_cpu(stat_info->tmac_icmp);
5586         tmp_stats[i++] =
5587                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5588                 le32_to_cpu(stat_info->tmac_rst_tcp);
5589         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5590         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5591                 le32_to_cpu(stat_info->tmac_udp);
5592         tmp_stats[i++] =
5593                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5594                 le32_to_cpu(stat_info->rmac_vld_frms);
5595         tmp_stats[i++] =
5596                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5597                 le32_to_cpu(stat_info->rmac_data_octets);
5598         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5599         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5600         tmp_stats[i++] =
5601                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5602                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5603         tmp_stats[i++] =
5604                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5605                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5606         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5607         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5608         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5609         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5610         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5611         tmp_stats[i++] =
5612                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5613                 le32_to_cpu(stat_info->rmac_ttl_octets);
5614         tmp_stats[i++] =
5615                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5616                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5617         tmp_stats[i++] =
5618                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5619                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5620         tmp_stats[i++] =
5621                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5622                 le32_to_cpu(stat_info->rmac_discarded_frms);
5623         tmp_stats[i++] =
5624                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5625                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5626         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5627         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5628         tmp_stats[i++] =
5629                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5630                 le32_to_cpu(stat_info->rmac_usized_frms);
5631         tmp_stats[i++] =
5632                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5633                 le32_to_cpu(stat_info->rmac_osized_frms);
5634         tmp_stats[i++] =
5635                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5636                 le32_to_cpu(stat_info->rmac_frag_frms);
5637         tmp_stats[i++] =
5638                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5639                 le32_to_cpu(stat_info->rmac_jabber_frms);
5640         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5641         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5642         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5643         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5644         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5645         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5646         tmp_stats[i++] =
5647                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5648                 le32_to_cpu(stat_info->rmac_ip);
5649         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5650         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5651         tmp_stats[i++] =
5652                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5653                 le32_to_cpu(stat_info->rmac_drop_ip);
5654         tmp_stats[i++] =
5655                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5656                 le32_to_cpu(stat_info->rmac_icmp);
5657         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5658         tmp_stats[i++] =
5659                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5660                 le32_to_cpu(stat_info->rmac_udp);
5661         tmp_stats[i++] =
5662                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5663                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5664         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5665         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5666         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5667         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5668         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5669         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5670         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5671         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5672         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5673         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5674         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5675         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5676         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5677         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5678         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5679         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5680         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5681         tmp_stats[i++] =
5682                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5683                 le32_to_cpu(stat_info->rmac_pause_cnt);
5684         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5685         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5686         tmp_stats[i++] =
5687                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5688                 le32_to_cpu(stat_info->rmac_accepted_ip);
5689         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5690         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5691         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5692         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5693         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5694         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5695         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5696         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5697         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5698         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5699         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5700         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5701         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5702         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5703         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5704         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5705         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5706         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5707         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5708
5709         /* Enhanced statistics exist only for Hercules */
5710         if(sp->device_type == XFRAME_II_DEVICE) {
5711                 tmp_stats[i++] =
5712                                 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5713                 tmp_stats[i++] =
5714                                 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5715                 tmp_stats[i++] =
5716                                 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5717                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5718                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5719                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5720                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5721                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5722                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5723                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5724                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5725                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5726                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5727                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5728                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5729                 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5730         }
5731
5732         tmp_stats[i++] = 0;
5733         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5734         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5735         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5736         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5737         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5738         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5739         tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5740         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5741         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5742         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5743         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5744         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5745         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5746         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5747         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5748         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5749         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5750         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5751         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5752         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5753         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5754         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5755         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5756         if (stat_info->sw_stat.num_aggregations) {
5757                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5758                 int count = 0;
5759                 /*
5760                  * Since 64-bit divide does not work on all platforms,
5761                  * do repeated subtraction.
5762                  */
5763                 while (tmp >= stat_info->sw_stat.num_aggregations) {
5764                         tmp -= stat_info->sw_stat.num_aggregations;
5765                         count++;
5766                 }
5767                 tmp_stats[i++] = count;
5768         }
5769         else
5770                 tmp_stats[i++] = 0;
5771         tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
5772         tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
5773         tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
5774         tmp_stats[i++] = stat_info->sw_stat.mem_freed;
5775         tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
5776         tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
5777         tmp_stats[i++] = stat_info->sw_stat.link_up_time;
5778         tmp_stats[i++] = stat_info->sw_stat.link_down_time;
5779
5780         tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
5781         tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
5782         tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
5783         tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
5784         tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
5785
5786         tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
5787         tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
5788         tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
5789         tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
5790         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
5791         tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
5792         tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
5793         tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
5794         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
5795 }
5796
5797 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5798 {
5799         return (XENA_REG_SPACE);
5800 }
5801
5802
5803 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5804 {
5805         struct s2io_nic *sp = dev->priv;
5806
5807         return (sp->rx_csum);
5808 }
5809
5810 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5811 {
5812         struct s2io_nic *sp = dev->priv;
5813
5814         if (data)
5815                 sp->rx_csum = 1;
5816         else
5817                 sp->rx_csum = 0;
5818
5819         return 0;
5820 }
5821
5822 static int s2io_get_eeprom_len(struct net_device *dev)
5823 {
5824         return (XENA_EEPROM_SPACE);
5825 }
5826
5827 static int s2io_ethtool_self_test_count(struct net_device *dev)
5828 {
5829         return (S2IO_TEST_LEN);
5830 }
5831
5832 static void s2io_ethtool_get_strings(struct net_device *dev,
5833                                      u32 stringset, u8 * data)
5834 {
5835         int stat_size = 0;
5836         struct s2io_nic *sp = dev->priv;
5837
5838         switch (stringset) {
5839         case ETH_SS_TEST:
5840                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5841                 break;
5842         case ETH_SS_STATS:
5843                 stat_size = sizeof(ethtool_xena_stats_keys);
5844                 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5845                 if(sp->device_type == XFRAME_II_DEVICE) {
5846                         memcpy(data + stat_size,
5847                                 &ethtool_enhanced_stats_keys,
5848                                 sizeof(ethtool_enhanced_stats_keys));
5849                         stat_size += sizeof(ethtool_enhanced_stats_keys);
5850                 }
5851
5852                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
5853                         sizeof(ethtool_driver_stats_keys));
5854         }
5855 }
5856 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5857 {
5858         struct s2io_nic *sp = dev->priv;
5859         int stat_count = 0;
5860         switch(sp->device_type) {
5861         case XFRAME_I_DEVICE:
5862                 stat_count = XFRAME_I_STAT_LEN;
5863         break;
5864
5865         case XFRAME_II_DEVICE:
5866                 stat_count = XFRAME_II_STAT_LEN;
5867         break;
5868         }
5869
5870         return stat_count;
5871 }
5872
5873 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5874 {
5875         if (data)
5876                 dev->features |= NETIF_F_IP_CSUM;
5877         else
5878                 dev->features &= ~NETIF_F_IP_CSUM;
5879
5880         return 0;
5881 }
5882
5883 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5884 {
5885         return (dev->features & NETIF_F_TSO) != 0;
5886 }
5887 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5888 {
5889         if (data)
5890                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5891         else
5892                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5893
5894         return 0;
5895 }
5896
5897 static const struct ethtool_ops netdev_ethtool_ops = {
5898         .get_settings = s2io_ethtool_gset,
5899         .set_settings = s2io_ethtool_sset,
5900         .get_drvinfo = s2io_ethtool_gdrvinfo,
5901         .get_regs_len = s2io_ethtool_get_regs_len,
5902         .get_regs = s2io_ethtool_gregs,
5903         .get_link = ethtool_op_get_link,
5904         .get_eeprom_len = s2io_get_eeprom_len,
5905         .get_eeprom = s2io_ethtool_geeprom,
5906         .set_eeprom = s2io_ethtool_seeprom,
5907         .get_ringparam = s2io_ethtool_gringparam,
5908         .get_pauseparam = s2io_ethtool_getpause_data,
5909         .set_pauseparam = s2io_ethtool_setpause_data,
5910         .get_rx_csum = s2io_ethtool_get_rx_csum,
5911         .set_rx_csum = s2io_ethtool_set_rx_csum,
5912         .get_tx_csum = ethtool_op_get_tx_csum,
5913         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5914         .get_sg = ethtool_op_get_sg,
5915         .set_sg = ethtool_op_set_sg,
5916         .get_tso = s2io_ethtool_op_get_tso,
5917         .set_tso = s2io_ethtool_op_set_tso,
5918         .get_ufo = ethtool_op_get_ufo,
5919         .set_ufo = ethtool_op_set_ufo,
5920         .self_test_count = s2io_ethtool_self_test_count,
5921         .self_test = s2io_ethtool_test,
5922         .get_strings = s2io_ethtool_get_strings,
5923         .phys_id = s2io_ethtool_idnic,
5924         .get_stats_count = s2io_ethtool_get_stats_count,
5925         .get_ethtool_stats = s2io_get_ethtool_stats
5926 };
5927
5928 /**
5929  *  s2io_ioctl - Entry point for the Ioctl
5930  *  @dev :  Device pointer.
5931  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5932  *  a proprietary structure used to pass information to the driver.
5933  *  @cmd :  This is used to distinguish between the different commands that
5934  *  can be passed to the IOCTL functions.
5935  *  Description:
5936  *  Currently there are no special functionality supported in IOCTL, hence
5937  *  function always return EOPNOTSUPPORTED
5938  */
5939
5940 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5941 {
5942         return -EOPNOTSUPP;
5943 }
5944
5945 /**
5946  *  s2io_change_mtu - entry point to change MTU size for the device.
5947  *   @dev : device pointer.
5948  *   @new_mtu : the new MTU size for the device.
5949  *   Description: A driver entry point to change MTU size for the device.
5950  *   Before changing the MTU the device must be stopped.
5951  *  Return value:
5952  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5953  *   file on failure.
5954  */
5955
5956 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5957 {
5958         struct s2io_nic *sp = dev->priv;
5959
5960         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5961                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5962                           dev->name);
5963                 return -EPERM;
5964         }
5965
5966         dev->mtu = new_mtu;
5967         if (netif_running(dev)) {
5968                 s2io_card_down(sp);
5969                 netif_stop_queue(dev);
5970                 if (s2io_card_up(sp)) {
5971                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5972                                   __FUNCTION__);
5973                 }
5974                 if (netif_queue_stopped(dev))
5975                         netif_wake_queue(dev);
5976         } else { /* Device is down */
5977                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5978                 u64 val64 = new_mtu;
5979
5980                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5981         }
5982
5983         return 0;
5984 }
5985
5986 /**
5987  *  s2io_tasklet - Bottom half of the ISR.
5988  *  @dev_adr : address of the device structure in dma_addr_t format.
5989  *  Description:
5990  *  This is the tasklet or the bottom half of the ISR. This is
5991  *  an extension of the ISR which is scheduled by the scheduler to be run
5992  *  when the load on the CPU is low. All low priority tasks of the ISR can
5993  *  be pushed into the tasklet. For now the tasklet is used only to
5994  *  replenish the Rx buffers in the Rx buffer descriptors.
5995  *  Return value:
5996  *  void.
5997  */
5998
5999 static void s2io_tasklet(unsigned long dev_addr)
6000 {
6001         struct net_device *dev = (struct net_device *) dev_addr;
6002         struct s2io_nic *sp = dev->priv;
6003         int i, ret;
6004         struct mac_info *mac_control;
6005         struct config_param *config;
6006
6007         mac_control = &sp->mac_control;
6008         config = &sp->config;
6009
6010         if (!TASKLET_IN_USE) {
6011                 for (i = 0; i < config->rx_ring_num; i++) {
6012                         ret = fill_rx_buffers(sp, i);
6013                         if (ret == -ENOMEM) {
6014                                 DBG_PRINT(INFO_DBG, "%s: Out of ",
6015                                           dev->name);
6016                                 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6017                                 break;
6018                         } else if (ret == -EFILL) {
6019                                 DBG_PRINT(INFO_DBG,
6020                                           "%s: Rx Ring %d is full\n",
6021                                           dev->name, i);
6022                                 break;
6023                         }
6024                 }
6025                 clear_bit(0, (&sp->tasklet_status));
6026         }
6027 }
6028
6029 /**
6030  * s2io_set_link - Set the LInk status
6031  * @data: long pointer to device private structue
6032  * Description: Sets the link status for the adapter
6033  */
6034
6035 static void s2io_set_link(struct work_struct *work)
6036 {
6037         struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6038         struct net_device *dev = nic->dev;
6039         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6040         register u64 val64;
6041         u16 subid;
6042
6043         rtnl_lock();
6044
6045         if (!netif_running(dev))
6046                 goto out_unlock;
6047
6048         if (test_and_set_bit(0, &(nic->link_state))) {
6049                 /* The card is being reset, no point doing anything */
6050                 goto out_unlock;
6051         }
6052
6053         subid = nic->pdev->subsystem_device;
6054         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6055                 /*
6056                  * Allow a small delay for the NICs self initiated
6057                  * cleanup to complete.
6058                  */
6059                 msleep(100);
6060         }
6061
6062         val64 = readq(&bar0->adapter_status);
6063         if (LINK_IS_UP(val64)) {
6064                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6065                         if (verify_xena_quiescence(nic)) {
6066                                 val64 = readq(&bar0->adapter_control);
6067                                 val64 |= ADAPTER_CNTL_EN;
6068                                 writeq(val64, &bar0->adapter_control);
6069                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6070                                         nic->device_type, subid)) {
6071                                         val64 = readq(&bar0->gpio_control);
6072                                         val64 |= GPIO_CTRL_GPIO_0;
6073                                         writeq(val64, &bar0->gpio_control);
6074                                         val64 = readq(&bar0->gpio_control);
6075                                 } else {
6076                                         val64 |= ADAPTER_LED_ON;
6077                                         writeq(val64, &bar0->adapter_control);
6078                                 }
6079                                 nic->device_enabled_once = TRUE;
6080                         } else {
6081                                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6082                                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6083                                 netif_stop_queue(dev);
6084                         }
6085                 }
6086                 val64 = readq(&bar0->adapter_status);
6087                 if (!LINK_IS_UP(val64)) {
6088                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
6089                         DBG_PRINT(ERR_DBG, " Link down after enabling ");
6090                         DBG_PRINT(ERR_DBG, "device \n");
6091                 } else
6092                         s2io_link(nic, LINK_UP);
6093         } else {
6094                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6095                                                       subid)) {
6096                         val64 = readq(&bar0->gpio_control);
6097                         val64 &= ~GPIO_CTRL_GPIO_0;
6098                         writeq(val64, &bar0->gpio_control);
6099                         val64 = readq(&bar0->gpio_control);
6100                 }
6101                 s2io_link(nic, LINK_DOWN);
6102         }
6103         clear_bit(0, &(nic->link_state));
6104
6105 out_unlock:
6106         rtnl_unlock();
6107 }
6108
6109 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6110                                 struct buffAdd *ba,
6111                                 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6112                                 u64 *temp2, int size)
6113 {
6114         struct net_device *dev = sp->dev;
6115
6116         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6117                 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6118                 /* allocate skb */
6119                 if (*skb) {
6120                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6121                         /*
6122                          * As Rx frame are not going to be processed,
6123                          * using same mapped address for the Rxd
6124                          * buffer pointer
6125                          */
6126                         rxdp1->Buffer0_ptr = *temp0;
6127                 } else {
6128                         *skb = dev_alloc_skb(size);
6129                         if (!(*skb)) {
6130                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6131                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6132                                 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6133                                 sp->mac_control.stats_info->sw_stat. \
6134                                         mem_alloc_fail_cnt++;
6135                                 return -ENOMEM ;
6136                         }
6137                         sp->mac_control.stats_info->sw_stat.mem_allocated
6138                                 += (*skb)->truesize;
6139                         /* storing the mapped addr in a temp variable
6140                          * such it will be used for next rxd whose
6141                          * Host Control is NULL
6142                          */
6143                         rxdp1->Buffer0_ptr = *temp0 =
6144                                 pci_map_single( sp->pdev, (*skb)->data,
6145                                         size - NET_IP_ALIGN,
6146                                         PCI_DMA_FROMDEVICE);
6147                         rxdp->Host_Control = (unsigned long) (*skb);
6148                 }
6149         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6150                 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6151                 /* Two buffer Mode */
6152                 if (*skb) {
6153                         rxdp3->Buffer2_ptr = *temp2;
6154                         rxdp3->Buffer0_ptr = *temp0;
6155                         rxdp3->Buffer1_ptr = *temp1;
6156                 } else {
6157                         *skb = dev_alloc_skb(size);
6158                         if (!(*skb)) {
6159                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6160                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6161                                 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6162                                 sp->mac_control.stats_info->sw_stat. \
6163                                         mem_alloc_fail_cnt++;
6164                                 return -ENOMEM;
6165                         }
6166                         sp->mac_control.stats_info->sw_stat.mem_allocated
6167                                 += (*skb)->truesize;
6168                         rxdp3->Buffer2_ptr = *temp2 =
6169                                 pci_map_single(sp->pdev, (*skb)->data,
6170                                                dev->mtu + 4,
6171                                                PCI_DMA_FROMDEVICE);
6172                         rxdp3->Buffer0_ptr = *temp0 =
6173                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6174                                                 PCI_DMA_FROMDEVICE);
6175                         rxdp->Host_Control = (unsigned long) (*skb);
6176
6177                         /* Buffer-1 will be dummy buffer not used */
6178                         rxdp3->Buffer1_ptr = *temp1 =
6179                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6180                                                 PCI_DMA_FROMDEVICE);
6181                 }
6182         }
6183         return 0;
6184 }
6185 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6186                                 int size)
6187 {
6188         struct net_device *dev = sp->dev;
6189         if (sp->rxd_mode == RXD_MODE_1) {
6190                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6191         } else if (sp->rxd_mode == RXD_MODE_3B) {
6192                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6193                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6194                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6195         }
6196 }
6197
6198 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6199 {
6200         int i, j, k, blk_cnt = 0, size;
6201         struct mac_info * mac_control = &sp->mac_control;
6202         struct config_param *config = &sp->config;
6203         struct net_device *dev = sp->dev;
6204         struct RxD_t *rxdp = NULL;
6205         struct sk_buff *skb = NULL;
6206         struct buffAdd *ba = NULL;
6207         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6208
6209         /* Calculate the size based on ring mode */
6210         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6211                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6212         if (sp->rxd_mode == RXD_MODE_1)
6213                 size += NET_IP_ALIGN;
6214         else if (sp->rxd_mode == RXD_MODE_3B)
6215                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6216
6217         for (i = 0; i < config->rx_ring_num; i++) {
6218                 blk_cnt = config->rx_cfg[i].num_rxd /
6219                         (rxd_count[sp->rxd_mode] +1);
6220
6221                 for (j = 0; j < blk_cnt; j++) {
6222                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6223                                 rxdp = mac_control->rings[i].
6224                                         rx_blocks[j].rxds[k].virt_addr;
6225                                 if(sp->rxd_mode == RXD_MODE_3B)
6226                                         ba = &mac_control->rings[i].ba[j][k];
6227                                 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6228                                                        &skb,(u64 *)&temp0_64,
6229                                                        (u64 *)&temp1_64,
6230                                                        (u64 *)&temp2_64,
6231                                                         size) == ENOMEM) {
6232                                         return 0;
6233                                 }
6234
6235                                 set_rxd_buffer_size(sp, rxdp, size);
6236                                 wmb();
6237                                 /* flip the Ownership bit to Hardware */
6238                                 rxdp->Control_1 |= RXD_OWN_XENA;
6239                         }
6240                 }
6241         }
6242         return 0;
6243
6244 }
6245
6246 static int s2io_add_isr(struct s2io_nic * sp)
6247 {
6248         int ret = 0;
6249         struct net_device *dev = sp->dev;
6250         int err = 0;
6251
6252         if (sp->intr_type == MSI_X)
6253                 ret = s2io_enable_msi_x(sp);
6254         if (ret) {
6255                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6256                 sp->intr_type = INTA;
6257         }
6258
6259         /* Store the values of the MSIX table in the struct s2io_nic structure */
6260         store_xmsi_data(sp);
6261
6262         /* After proper initialization of H/W, register ISR */
6263         if (sp->intr_type == MSI_X) {
6264                 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6265
6266                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6267                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6268                                 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6269                                         dev->name, i);
6270                                 err = request_irq(sp->entries[i].vector,
6271                                           s2io_msix_fifo_handle, 0, sp->desc[i],
6272                                                   sp->s2io_entries[i].arg);
6273                                 /* If either data or addr is zero print it */
6274                                 if(!(sp->msix_info[i].addr &&
6275                                         sp->msix_info[i].data)) {
6276                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6277                                                 "Data:0x%lx\n",sp->desc[i],
6278                                                 (unsigned long long)
6279                                                 sp->msix_info[i].addr,
6280                                                 (unsigned long)
6281                                                 ntohl(sp->msix_info[i].data));
6282                                 } else {
6283                                         msix_tx_cnt++;
6284                                 }
6285                         } else {
6286                                 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6287                                         dev->name, i);
6288                                 err = request_irq(sp->entries[i].vector,
6289                                           s2io_msix_ring_handle, 0, sp->desc[i],
6290                                                   sp->s2io_entries[i].arg);
6291                                 /* If either data or addr is zero print it */
6292                                 if(!(sp->msix_info[i].addr &&
6293                                         sp->msix_info[i].data)) {
6294                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6295                                                 "Data:0x%lx\n",sp->desc[i],
6296                                                 (unsigned long long)
6297                                                 sp->msix_info[i].addr,
6298                                                 (unsigned long)
6299                                                 ntohl(sp->msix_info[i].data));
6300                                 } else {
6301                                         msix_rx_cnt++;
6302                                 }
6303                         }
6304                         if (err) {
6305                                 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6306                                           "failed\n", dev->name, i);
6307                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6308                                 return -1;
6309                         }
6310                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6311                 }
6312                 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6313                 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
6314         }
6315         if (sp->intr_type == INTA) {
6316                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6317                                 sp->name, dev);
6318                 if (err) {
6319                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6320                                   dev->name);
6321                         return -1;
6322                 }
6323         }
6324         return 0;
6325 }
6326 static void s2io_rem_isr(struct s2io_nic * sp)
6327 {
6328         int cnt = 0;
6329         struct net_device *dev = sp->dev;
6330
6331         if (sp->intr_type == MSI_X) {
6332                 int i;
6333                 u16 msi_control;
6334
6335                 for (i=1; (sp->s2io_entries[i].in_use ==
6336                         MSIX_REGISTERED_SUCCESS); i++) {
6337                         int vector = sp->entries[i].vector;
6338                         void *arg = sp->s2io_entries[i].arg;
6339
6340                         free_irq(vector, arg);
6341                 }
6342                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6343                 msi_control &= 0xFFFE; /* Disable MSI */
6344                 pci_write_config_word(sp->pdev, 0x42, msi_control);
6345
6346                 pci_disable_msix(sp->pdev);
6347         } else {
6348                 free_irq(sp->pdev->irq, dev);
6349         }
6350         /* Waiting till all Interrupt handlers are complete */
6351         cnt = 0;
6352         do {
6353                 msleep(10);
6354                 if (!atomic_read(&sp->isr_cnt))
6355                         break;
6356                 cnt++;
6357         } while(cnt < 5);
6358 }
6359
6360 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
6361 {
6362         int cnt = 0;
6363         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6364         unsigned long flags;
6365         register u64 val64 = 0;
6366
6367         del_timer_sync(&sp->alarm_timer);
6368         /* If s2io_set_link task is executing, wait till it completes. */
6369         while (test_and_set_bit(0, &(sp->link_state))) {
6370                 msleep(50);
6371         }
6372         atomic_set(&sp->card_state, CARD_DOWN);
6373
6374         /* disable Tx and Rx traffic on the NIC */
6375         if (do_io)
6376                 stop_nic(sp);
6377
6378         s2io_rem_isr(sp);
6379
6380         /* Kill tasklet. */
6381         tasklet_kill(&sp->task);
6382
6383         /* Check if the device is Quiescent and then Reset the NIC */
6384         while(do_io) {
6385                 /* As per the HW requirement we need to replenish the
6386                  * receive buffer to avoid the ring bump. Since there is
6387                  * no intention of processing the Rx frame at this pointwe are
6388                  * just settting the ownership bit of rxd in Each Rx
6389                  * ring to HW and set the appropriate buffer size
6390                  * based on the ring mode
6391                  */
6392                 rxd_owner_bit_reset(sp);
6393
6394                 val64 = readq(&bar0->adapter_status);
6395                 if (verify_xena_quiescence(sp)) {
6396                         if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6397                         break;
6398                 }
6399
6400                 msleep(50);
6401                 cnt++;
6402                 if (cnt == 10) {
6403                         DBG_PRINT(ERR_DBG,
6404                                   "s2io_close:Device not Quiescent ");
6405                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6406                                   (unsigned long long) val64);
6407                         break;
6408                 }
6409         }
6410         if (do_io)
6411                 s2io_reset(sp);
6412
6413         spin_lock_irqsave(&sp->tx_lock, flags);
6414         /* Free all Tx buffers */
6415         free_tx_buffers(sp);
6416         spin_unlock_irqrestore(&sp->tx_lock, flags);
6417
6418         /* Free all Rx buffers */
6419         spin_lock_irqsave(&sp->rx_lock, flags);
6420         free_rx_buffers(sp);
6421         spin_unlock_irqrestore(&sp->rx_lock, flags);
6422
6423         clear_bit(0, &(sp->link_state));
6424 }
6425
6426 static void s2io_card_down(struct s2io_nic * sp)
6427 {
6428         do_s2io_card_down(sp, 1);
6429 }
6430
6431 static int s2io_card_up(struct s2io_nic * sp)
6432 {
6433         int i, ret = 0;
6434         struct mac_info *mac_control;
6435         struct config_param *config;
6436         struct net_device *dev = (struct net_device *) sp->dev;
6437         u16 interruptible;
6438
6439         /* Initialize the H/W I/O registers */
6440         if (init_nic(sp) != 0) {
6441                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6442                           dev->name);
6443                 s2io_reset(sp);
6444                 return -ENODEV;
6445         }
6446
6447         /*
6448          * Initializing the Rx buffers. For now we are considering only 1
6449          * Rx ring and initializing buffers into 30 Rx blocks
6450          */
6451         mac_control = &sp->mac_control;
6452         config = &sp->config;
6453
6454         for (i = 0; i < config->rx_ring_num; i++) {
6455                 if ((ret = fill_rx_buffers(sp, i))) {
6456                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6457                                   dev->name);
6458                         s2io_reset(sp);
6459                         free_rx_buffers(sp);
6460                         return -ENOMEM;
6461                 }
6462                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6463                           atomic_read(&sp->rx_bufs_left[i]));
6464         }
6465         /* Maintain the state prior to the open */
6466         if (sp->promisc_flg)
6467                 sp->promisc_flg = 0;
6468         if (sp->m_cast_flg) {
6469                 sp->m_cast_flg = 0;
6470                 sp->all_multi_pos= 0;
6471         }
6472
6473         /* Setting its receive mode */
6474         s2io_set_multicast(dev);
6475
6476         if (sp->lro) {
6477                 /* Initialize max aggregatable pkts per session based on MTU */
6478                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6479                 /* Check if we can use(if specified) user provided value */
6480                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6481                         sp->lro_max_aggr_per_sess = lro_max_pkts;
6482         }
6483
6484         /* Enable Rx Traffic and interrupts on the NIC */
6485         if (start_nic(sp)) {
6486                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6487                 s2io_reset(sp);
6488                 free_rx_buffers(sp);
6489                 return -ENODEV;
6490         }
6491
6492         /* Add interrupt service routine */
6493         if (s2io_add_isr(sp) != 0) {
6494                 if (sp->intr_type == MSI_X)
6495                         s2io_rem_isr(sp);
6496                 s2io_reset(sp);
6497                 free_rx_buffers(sp);
6498                 return -ENODEV;
6499         }
6500
6501         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6502
6503         /* Enable tasklet for the device */
6504         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6505
6506         /*  Enable select interrupts */
6507         if (sp->intr_type != INTA)
6508                 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6509         else {
6510                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6511                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6512                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6513                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6514         }
6515
6516
6517         atomic_set(&sp->card_state, CARD_UP);
6518         return 0;
6519 }
6520
6521 /**
6522  * s2io_restart_nic - Resets the NIC.
6523  * @data : long pointer to the device private structure
6524  * Description:
6525  * This function is scheduled to be run by the s2io_tx_watchdog
6526  * function after 0.5 secs to reset the NIC. The idea is to reduce
6527  * the run time of the watch dog routine which is run holding a
6528  * spin lock.
6529  */
6530
6531 static void s2io_restart_nic(struct work_struct *work)
6532 {
6533         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
6534         struct net_device *dev = sp->dev;
6535
6536         rtnl_lock();
6537
6538         if (!netif_running(dev))
6539                 goto out_unlock;
6540
6541         s2io_card_down(sp);
6542         if (s2io_card_up(sp)) {
6543                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6544                           dev->name);
6545         }
6546         netif_wake_queue(dev);
6547         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6548                   dev->name);
6549 out_unlock:
6550         rtnl_unlock();
6551 }
6552
6553 /**
6554  *  s2io_tx_watchdog - Watchdog for transmit side.
6555  *  @dev : Pointer to net device structure
6556  *  Description:
6557  *  This function is triggered if the Tx Queue is stopped
6558  *  for a pre-defined amount of time when the Interface is still up.
6559  *  If the Interface is jammed in such a situation, the hardware is
6560  *  reset (by s2io_close) and restarted again (by s2io_open) to
6561  *  overcome any problem that might have been caused in the hardware.
6562  *  Return value:
6563  *  void
6564  */
6565
6566 static void s2io_tx_watchdog(struct net_device *dev)
6567 {
6568         struct s2io_nic *sp = dev->priv;
6569
6570         if (netif_carrier_ok(dev)) {
6571                 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
6572                 schedule_work(&sp->rst_timer_task);
6573                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6574         }
6575 }
6576
6577 /**
6578  *   rx_osm_handler - To perform some OS related operations on SKB.
6579  *   @sp: private member of the device structure,pointer to s2io_nic structure.
6580  *   @skb : the socket buffer pointer.
6581  *   @len : length of the packet
6582  *   @cksum : FCS checksum of the frame.
6583  *   @ring_no : the ring from which this RxD was extracted.
6584  *   Description:
6585  *   This function is called by the Rx interrupt serivce routine to perform
6586  *   some OS related operations on the SKB before passing it to the upper
6587  *   layers. It mainly checks if the checksum is OK, if so adds it to the
6588  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
6589  *   to the upper layer. If the checksum is wrong, it increments the Rx
6590  *   packet error count, frees the SKB and returns error.
6591  *   Return value:
6592  *   SUCCESS on success and -1 on failure.
6593  */
6594 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
6595 {
6596         struct s2io_nic *sp = ring_data->nic;
6597         struct net_device *dev = (struct net_device *) sp->dev;
6598         struct sk_buff *skb = (struct sk_buff *)
6599                 ((unsigned long) rxdp->Host_Control);
6600         int ring_no = ring_data->ring_no;
6601         u16 l3_csum, l4_csum;
6602         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6603         struct lro *lro;
6604         u8 err_mask;
6605
6606         skb->dev = dev;
6607
6608         if (err) {
6609                 /* Check for parity error */
6610                 if (err & 0x1) {
6611                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6612                 }
6613                 err_mask = err >> 48;
6614                 switch(err_mask) {
6615                         case 1:
6616                                 sp->mac_control.stats_info->sw_stat.
6617                                 rx_parity_err_cnt++;
6618                         break;
6619
6620                         case 2:
6621                                 sp->mac_control.stats_info->sw_stat.
6622                                 rx_abort_cnt++;
6623                         break;
6624
6625                         case 3:
6626                                 sp->mac_control.stats_info->sw_stat.
6627                                 rx_parity_abort_cnt++;
6628                         break;
6629
6630                         case 4:
6631                                 sp->mac_control.stats_info->sw_stat.
6632                                 rx_rda_fail_cnt++;
6633                         break;
6634
6635                         case 5:
6636                                 sp->mac_control.stats_info->sw_stat.
6637                                 rx_unkn_prot_cnt++;
6638                         break;
6639
6640                         case 6:
6641                                 sp->mac_control.stats_info->sw_stat.
6642                                 rx_fcs_err_cnt++;
6643                         break;
6644
6645                         case 7:
6646                                 sp->mac_control.stats_info->sw_stat.
6647                                 rx_buf_size_err_cnt++;
6648                         break;
6649
6650                         case 8:
6651                                 sp->mac_control.stats_info->sw_stat.
6652                                 rx_rxd_corrupt_cnt++;
6653                         break;
6654
6655                         case 15:
6656                                 sp->mac_control.stats_info->sw_stat.
6657                                 rx_unkn_err_cnt++;
6658                         break;
6659                 }
6660                 /*
6661                 * Drop the packet if bad transfer code. Exception being
6662                 * 0x5, which could be due to unsupported IPv6 extension header.
6663                 * In this case, we let stack handle the packet.
6664                 * Note that in this case, since checksum will be incorrect,
6665                 * stack will validate the same.
6666                 */
6667                 if (err_mask != 0x5) {
6668                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
6669                                 dev->name, err_mask);
6670                         sp->stats.rx_crc_errors++;
6671                         sp->mac_control.stats_info->sw_stat.mem_freed
6672                                 += skb->truesize;
6673                         dev_kfree_skb(skb);
6674                         atomic_dec(&sp->rx_bufs_left[ring_no]);
6675                         rxdp->Host_Control = 0;
6676                         return 0;
6677                 }
6678         }
6679
6680         /* Updating statistics */
6681         rxdp->Host_Control = 0;
6682         if (sp->rxd_mode == RXD_MODE_1) {
6683                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6684
6685                 sp->stats.rx_bytes += len;
6686                 skb_put(skb, len);
6687
6688         } else if (sp->rxd_mode == RXD_MODE_3B) {
6689                 int get_block = ring_data->rx_curr_get_info.block_index;
6690                 int get_off = ring_data->rx_curr_get_info.offset;
6691                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6692                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6693                 unsigned char *buff = skb_push(skb, buf0_len);
6694
6695                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
6696                 sp->stats.rx_bytes += buf0_len + buf2_len;
6697                 memcpy(buff, ba->ba_0, buf0_len);
6698                 skb_put(skb, buf2_len);
6699         }
6700
6701         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6702             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6703             (sp->rx_csum)) {
6704                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6705                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6706                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6707                         /*
6708                          * NIC verifies if the Checksum of the received
6709                          * frame is Ok or not and accordingly returns
6710                          * a flag in the RxD.
6711                          */
6712                         skb->ip_summed = CHECKSUM_UNNECESSARY;
6713                         if (sp->lro) {
6714                                 u32 tcp_len;
6715                                 u8 *tcp;
6716                                 int ret = 0;
6717
6718                                 ret = s2io_club_tcp_session(skb->data, &tcp,
6719                                                 &tcp_len, &lro, rxdp, sp);
6720                                 switch (ret) {
6721                                         case 3: /* Begin anew */
6722                                                 lro->parent = skb;
6723                                                 goto aggregate;
6724                                         case 1: /* Aggregate */
6725                                         {
6726                                                 lro_append_pkt(sp, lro,
6727                                                         skb, tcp_len);
6728                                                 goto aggregate;
6729                                         }
6730                                         case 4: /* Flush session */
6731                                         {
6732                                                 lro_append_pkt(sp, lro,
6733                                                         skb, tcp_len);
6734                                                 queue_rx_frame(lro->parent);
6735                                                 clear_lro_session(lro);
6736                                                 sp->mac_control.stats_info->
6737                                                     sw_stat.flush_max_pkts++;
6738                                                 goto aggregate;
6739                                         }
6740                                         case 2: /* Flush both */
6741                                                 lro->parent->data_len =
6742                                                         lro->frags_len;
6743                                                 sp->mac_control.stats_info->
6744                                                      sw_stat.sending_both++;
6745                                                 queue_rx_frame(lro->parent);
6746                                                 clear_lro_session(lro);
6747                                                 goto send_up;
6748                                         case 0: /* sessions exceeded */
6749                                         case -1: /* non-TCP or not
6750                                                   * L2 aggregatable
6751                                                   */
6752                                         case 5: /*
6753                                                  * First pkt in session not
6754                                                  * L3/L4 aggregatable
6755                                                  */
6756                                                 break;
6757                                         default:
6758                                                 DBG_PRINT(ERR_DBG,
6759                                                         "%s: Samadhana!!\n",
6760                                                          __FUNCTION__);
6761                                                 BUG();
6762                                 }
6763                         }
6764                 } else {
6765                         /*
6766                          * Packet with erroneous checksum, let the
6767                          * upper layers deal with it.
6768                          */
6769                         skb->ip_summed = CHECKSUM_NONE;
6770                 }
6771         } else {
6772                 skb->ip_summed = CHECKSUM_NONE;
6773         }
6774         sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
6775         if (!sp->lro) {
6776                 skb->protocol = eth_type_trans(skb, dev);
6777                 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
6778                         vlan_strip_flag)) {
6779                         /* Queueing the vlan frame to the upper layer */
6780                         if (napi)
6781                                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6782                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
6783                         else
6784                                 vlan_hwaccel_rx(skb, sp->vlgrp,
6785                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
6786                 } else {
6787                         if (napi)
6788                                 netif_receive_skb(skb);
6789                         else
6790                                 netif_rx(skb);
6791                 }
6792         } else {
6793 send_up:
6794                 queue_rx_frame(skb);
6795         }
6796         dev->last_rx = jiffies;
6797 aggregate:
6798         atomic_dec(&sp->rx_bufs_left[ring_no]);
6799         return SUCCESS;
6800 }
6801
6802 /**
6803  *  s2io_link - stops/starts the Tx queue.
6804  *  @sp : private member of the device structure, which is a pointer to the
6805  *  s2io_nic structure.
6806  *  @link : inidicates whether link is UP/DOWN.
6807  *  Description:
6808  *  This function stops/starts the Tx queue depending on whether the link
6809  *  status of the NIC is is down or up. This is called by the Alarm
6810  *  interrupt handler whenever a link change interrupt comes up.
6811  *  Return value:
6812  *  void.
6813  */
6814
6815 static void s2io_link(struct s2io_nic * sp, int link)
6816 {
6817         struct net_device *dev = (struct net_device *) sp->dev;
6818
6819         if (link != sp->last_link_state) {
6820                 if (link == LINK_DOWN) {
6821                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6822                         netif_carrier_off(dev);
6823                         if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
6824                         sp->mac_control.stats_info->sw_stat.link_up_time =
6825                                 jiffies - sp->start_time;
6826                         sp->mac_control.stats_info->sw_stat.link_down_cnt++;
6827                 } else {
6828                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6829                         if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
6830                         sp->mac_control.stats_info->sw_stat.link_down_time =
6831                                 jiffies - sp->start_time;
6832                         sp->mac_control.stats_info->sw_stat.link_up_cnt++;
6833                         netif_carrier_on(dev);
6834                 }
6835         }
6836         sp->last_link_state = link;
6837         sp->start_time = jiffies;
6838 }
6839
6840 /**
6841  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6842  *  @sp : private member of the device structure, which is a pointer to the
6843  *  s2io_nic structure.
6844  *  Description:
6845  *  This function initializes a few of the PCI and PCI-X configuration registers
6846  *  with recommended values.
6847  *  Return value:
6848  *  void
6849  */
6850
6851 static void s2io_init_pci(struct s2io_nic * sp)
6852 {
6853         u16 pci_cmd = 0, pcix_cmd = 0;
6854
6855         /* Enable Data Parity Error Recovery in PCI-X command register. */
6856         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6857                              &(pcix_cmd));
6858         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6859                               (pcix_cmd | 1));
6860         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6861                              &(pcix_cmd));
6862
6863         /* Set the PErr Response bit in PCI command register. */
6864         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6865         pci_write_config_word(sp->pdev, PCI_COMMAND,
6866                               (pci_cmd | PCI_COMMAND_PARITY));
6867         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6868 }
6869
6870 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6871 {
6872         if ( tx_fifo_num > 8) {
6873                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6874                          "supported\n");
6875                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6876                 tx_fifo_num = 8;
6877         }
6878         if ( rx_ring_num > 8) {
6879                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6880                          "supported\n");
6881                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6882                 rx_ring_num = 8;
6883         }
6884         if (*dev_intr_type != INTA)
6885                 napi = 0;
6886
6887 #ifndef CONFIG_PCI_MSI
6888         if (*dev_intr_type != INTA) {
6889                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6890                           "MSI/MSI-X. Defaulting to INTA\n");
6891                 *dev_intr_type = INTA;
6892         }
6893 #else
6894         if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
6895                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6896                           "Defaulting to INTA\n");
6897                 *dev_intr_type = INTA;
6898         }
6899 #endif
6900         if ((*dev_intr_type == MSI_X) &&
6901                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6902                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6903                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
6904                                         "Defaulting to INTA\n");
6905                 *dev_intr_type = INTA;
6906         }
6907
6908         if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
6909                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6910                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
6911                 rx_ring_mode = 1;
6912         }
6913         return SUCCESS;
6914 }
6915
6916 /**
6917  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
6918  * or Traffic class respectively.
6919  * @nic: device peivate variable
6920  * Description: The function configures the receive steering to
6921  * desired receive ring.
6922  * Return Value:  SUCCESS on success and
6923  * '-1' on failure (endian settings incorrect).
6924  */
6925 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
6926 {
6927         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6928         register u64 val64 = 0;
6929
6930         if (ds_codepoint > 63)
6931                 return FAILURE;
6932
6933         val64 = RTS_DS_MEM_DATA(ring);
6934         writeq(val64, &bar0->rts_ds_mem_data);
6935
6936         val64 = RTS_DS_MEM_CTRL_WE |
6937                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
6938                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
6939
6940         writeq(val64, &bar0->rts_ds_mem_ctrl);
6941
6942         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
6943                                 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
6944                                 S2IO_BIT_RESET);
6945 }
6946
6947 /**
6948  *  s2io_init_nic - Initialization of the adapter .
6949  *  @pdev : structure containing the PCI related information of the device.
6950  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6951  *  Description:
6952  *  The function initializes an adapter identified by the pci_dec structure.
6953  *  All OS related initialization including memory and device structure and
6954  *  initlaization of the device private variable is done. Also the swapper
6955  *  control register is initialized to enable read and write into the I/O
6956  *  registers of the device.
6957  *  Return value:
6958  *  returns 0 on success and negative on failure.
6959  */
6960
6961 static int __devinit
6962 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6963 {
6964         struct s2io_nic *sp;
6965         struct net_device *dev;
6966         int i, j, ret;
6967         int dma_flag = FALSE;
6968         u32 mac_up, mac_down;
6969         u64 val64 = 0, tmp64 = 0;
6970         struct XENA_dev_config __iomem *bar0 = NULL;
6971         u16 subid;
6972         struct mac_info *mac_control;
6973         struct config_param *config;
6974         int mode;
6975         u8 dev_intr_type = intr_type;
6976
6977         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6978                 return ret;
6979
6980         if ((ret = pci_enable_device(pdev))) {
6981                 DBG_PRINT(ERR_DBG,
6982                           "s2io_init_nic: pci_enable_device failed\n");
6983                 return ret;
6984         }
6985
6986         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6987                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6988                 dma_flag = TRUE;
6989                 if (pci_set_consistent_dma_mask
6990                     (pdev, DMA_64BIT_MASK)) {
6991                         DBG_PRINT(ERR_DBG,
6992                                   "Unable to obtain 64bit DMA for \
6993                                         consistent allocations\n");
6994                         pci_disable_device(pdev);
6995                         return -ENOMEM;
6996                 }
6997         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6998                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6999         } else {
7000                 pci_disable_device(pdev);
7001                 return -ENOMEM;
7002         }
7003         if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7004                 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7005                 pci_disable_device(pdev);
7006                 return -ENODEV;
7007         }
7008
7009         dev = alloc_etherdev(sizeof(struct s2io_nic));
7010         if (dev == NULL) {
7011                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7012                 pci_disable_device(pdev);
7013                 pci_release_regions(pdev);
7014                 return -ENODEV;
7015         }
7016
7017         pci_set_master(pdev);
7018         pci_set_drvdata(pdev, dev);
7019         SET_MODULE_OWNER(dev);
7020         SET_NETDEV_DEV(dev, &pdev->dev);
7021
7022         /*  Private member variable initialized to s2io NIC structure */
7023         sp = dev->priv;
7024         memset(sp, 0, sizeof(struct s2io_nic));
7025         sp->dev = dev;
7026         sp->pdev = pdev;
7027         sp->high_dma_flag = dma_flag;
7028         sp->device_enabled_once = FALSE;
7029         if (rx_ring_mode == 1)
7030                 sp->rxd_mode = RXD_MODE_1;
7031         if (rx_ring_mode == 2)
7032                 sp->rxd_mode = RXD_MODE_3B;
7033
7034         sp->intr_type = dev_intr_type;
7035
7036         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7037                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7038                 sp->device_type = XFRAME_II_DEVICE;
7039         else
7040                 sp->device_type = XFRAME_I_DEVICE;
7041
7042         sp->lro = lro;
7043
7044         /* Initialize some PCI/PCI-X fields of the NIC. */
7045         s2io_init_pci(sp);
7046
7047         /*
7048          * Setting the device configuration parameters.
7049          * Most of these parameters can be specified by the user during
7050          * module insertion as they are module loadable parameters. If
7051          * these parameters are not not specified during load time, they
7052          * are initialized with default values.
7053          */
7054         mac_control = &sp->mac_control;
7055         config = &sp->config;
7056
7057         /* Tx side parameters. */
7058         config->tx_fifo_num = tx_fifo_num;
7059         for (i = 0; i < MAX_TX_FIFOS; i++) {
7060                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7061                 config->tx_cfg[i].fifo_priority = i;
7062         }
7063
7064         /* mapping the QoS priority to the configured fifos */
7065         for (i = 0; i < MAX_TX_FIFOS; i++)
7066                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7067
7068         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7069         for (i = 0; i < config->tx_fifo_num; i++) {
7070                 config->tx_cfg[i].f_no_snoop =
7071                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7072                 if (config->tx_cfg[i].fifo_len < 65) {
7073                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7074                         break;
7075                 }
7076         }
7077         /* + 2 because one Txd for skb->data and one Txd for UFO */
7078         config->max_txds = MAX_SKB_FRAGS + 2;
7079
7080         /* Rx side parameters. */
7081         config->rx_ring_num = rx_ring_num;
7082         for (i = 0; i < MAX_RX_RINGS; i++) {
7083                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7084                     (rxd_count[sp->rxd_mode] + 1);
7085                 config->rx_cfg[i].ring_priority = i;
7086         }
7087
7088         for (i = 0; i < rx_ring_num; i++) {
7089                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7090                 config->rx_cfg[i].f_no_snoop =
7091                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7092         }
7093
7094         /*  Setting Mac Control parameters */
7095         mac_control->rmac_pause_time = rmac_pause_time;
7096         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7097         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7098
7099
7100         /* Initialize Ring buffer parameters. */
7101         for (i = 0; i < config->rx_ring_num; i++)
7102                 atomic_set(&sp->rx_bufs_left[i], 0);
7103
7104         /* Initialize the number of ISRs currently running */
7105         atomic_set(&sp->isr_cnt, 0);
7106
7107         /*  initialize the shared memory used by the NIC and the host */
7108         if (init_shared_mem(sp)) {
7109                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7110                           dev->name);
7111                 ret = -ENOMEM;
7112                 goto mem_alloc_failed;
7113         }
7114
7115         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7116                                      pci_resource_len(pdev, 0));
7117         if (!sp->bar0) {
7118                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7119                           dev->name);
7120                 ret = -ENOMEM;
7121                 goto bar0_remap_failed;
7122         }
7123
7124         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7125                                      pci_resource_len(pdev, 2));
7126         if (!sp->bar1) {
7127                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7128                           dev->name);
7129                 ret = -ENOMEM;
7130                 goto bar1_remap_failed;
7131         }
7132
7133         dev->irq = pdev->irq;
7134         dev->base_addr = (unsigned long) sp->bar0;
7135
7136         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7137         for (j = 0; j < MAX_TX_FIFOS; j++) {
7138                 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7139                     (sp->bar1 + (j * 0x00020000));
7140         }
7141
7142         /*  Driver entry points */
7143         dev->open = &s2io_open;
7144         dev->stop = &s2io_close;
7145         dev->hard_start_xmit = &s2io_xmit;
7146         dev->get_stats = &s2io_get_stats;
7147         dev->set_multicast_list = &s2io_set_multicast;
7148         dev->do_ioctl = &s2io_ioctl;
7149         dev->change_mtu = &s2io_change_mtu;
7150         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7151         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7152         dev->vlan_rx_register = s2io_vlan_rx_register;
7153
7154         /*
7155          * will use eth_mac_addr() for  dev->set_mac_address
7156          * mac address will be set every time dev->open() is called
7157          */
7158         dev->poll = s2io_poll;
7159         dev->weight = 32;
7160
7161 #ifdef CONFIG_NET_POLL_CONTROLLER
7162         dev->poll_controller = s2io_netpoll;
7163 #endif
7164
7165         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7166         if (sp->high_dma_flag == TRUE)
7167                 dev->features |= NETIF_F_HIGHDMA;
7168         dev->features |= NETIF_F_TSO;
7169         dev->features |= NETIF_F_TSO6;
7170         if ((sp->device_type & XFRAME_II_DEVICE) && (ufo))  {
7171                 dev->features |= NETIF_F_UFO;
7172                 dev->features |= NETIF_F_HW_CSUM;
7173         }
7174
7175         dev->tx_timeout = &s2io_tx_watchdog;
7176         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7177         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7178         INIT_WORK(&sp->set_link_task, s2io_set_link);
7179
7180         pci_save_state(sp->pdev);
7181
7182         /* Setting swapper control on the NIC, for proper reset operation */
7183         if (s2io_set_swapper(sp)) {
7184                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7185                           dev->name);
7186                 ret = -EAGAIN;
7187                 goto set_swap_failed;
7188         }
7189
7190         /* Verify if the Herc works on the slot its placed into */
7191         if (sp->device_type & XFRAME_II_DEVICE) {
7192                 mode = s2io_verify_pci_mode(sp);
7193                 if (mode < 0) {
7194                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7195                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7196                         ret = -EBADSLT;
7197                         goto set_swap_failed;
7198                 }
7199         }
7200
7201         /* Not needed for Herc */
7202         if (sp->device_type & XFRAME_I_DEVICE) {
7203                 /*
7204                  * Fix for all "FFs" MAC address problems observed on
7205                  * Alpha platforms
7206                  */
7207                 fix_mac_address(sp);
7208                 s2io_reset(sp);
7209         }
7210
7211         /*
7212          * MAC address initialization.
7213          * For now only one mac address will be read and used.
7214          */
7215         bar0 = sp->bar0;
7216         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7217             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7218         writeq(val64, &bar0->rmac_addr_cmd_mem);
7219         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7220                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7221         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7222         mac_down = (u32) tmp64;
7223         mac_up = (u32) (tmp64 >> 32);
7224
7225         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7226         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7227         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7228         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7229         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7230         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7231
7232         /*  Set the factory defined MAC address initially   */
7233         dev->addr_len = ETH_ALEN;
7234         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7235
7236         /* reset Nic and bring it to known state */
7237         s2io_reset(sp);
7238
7239         /*
7240          * Initialize the tasklet status and link state flags
7241          * and the card state parameter
7242          */
7243         atomic_set(&(sp->card_state), 0);
7244         sp->tasklet_status = 0;
7245         sp->link_state = 0;
7246
7247         /* Initialize spinlocks */
7248         spin_lock_init(&sp->tx_lock);
7249
7250         if (!napi)
7251                 spin_lock_init(&sp->put_lock);
7252         spin_lock_init(&sp->rx_lock);
7253
7254         /*
7255          * SXE-002: Configure link and activity LED to init state
7256          * on driver load.
7257          */
7258         subid = sp->pdev->subsystem_device;
7259         if ((subid & 0xFF) >= 0x07) {
7260                 val64 = readq(&bar0->gpio_control);
7261                 val64 |= 0x0000800000000000ULL;
7262                 writeq(val64, &bar0->gpio_control);
7263                 val64 = 0x0411040400000000ULL;
7264                 writeq(val64, (void __iomem *) bar0 + 0x2700);
7265                 val64 = readq(&bar0->gpio_control);
7266         }
7267
7268         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
7269
7270         if (register_netdev(dev)) {
7271                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7272                 ret = -ENODEV;
7273                 goto register_failed;
7274         }
7275         s2io_vpd_read(sp);
7276         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7277         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7278                   sp->product_name, pdev->revision);
7279         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7280                   s2io_driver_version);
7281         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7282                           "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
7283                           sp->def_mac_addr[0].mac_addr[0],
7284                           sp->def_mac_addr[0].mac_addr[1],
7285                           sp->def_mac_addr[0].mac_addr[2],
7286                           sp->def_mac_addr[0].mac_addr[3],
7287                           sp->def_mac_addr[0].mac_addr[4],
7288                           sp->def_mac_addr[0].mac_addr[5]);
7289         DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7290         if (sp->device_type & XFRAME_II_DEVICE) {
7291                 mode = s2io_print_pci_mode(sp);
7292                 if (mode < 0) {
7293                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7294                         ret = -EBADSLT;
7295                         unregister_netdev(dev);
7296                         goto set_swap_failed;
7297                 }
7298         }
7299         switch(sp->rxd_mode) {
7300                 case RXD_MODE_1:
7301                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7302                                                 dev->name);
7303                     break;
7304                 case RXD_MODE_3B:
7305                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7306                                                 dev->name);
7307                     break;
7308         }
7309
7310         if (napi)
7311                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7312         switch(sp->intr_type) {
7313                 case INTA:
7314                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7315                     break;
7316                 case MSI_X:
7317                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7318                     break;
7319         }
7320         if (sp->lro)
7321                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7322                           dev->name);
7323         if (ufo)
7324                 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7325                                         " enabled\n", dev->name);
7326         /* Initialize device name */
7327         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7328
7329         /* Initialize bimodal Interrupts */
7330         sp->config.bimodal = bimodal;
7331         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7332                 sp->config.bimodal = 0;
7333                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7334                         dev->name);
7335         }
7336
7337         /*
7338          * Make Link state as off at this point, when the Link change
7339          * interrupt comes the state will be automatically changed to
7340          * the right state.
7341          */
7342         netif_carrier_off(dev);
7343
7344         return 0;
7345
7346       register_failed:
7347       set_swap_failed:
7348         iounmap(sp->bar1);
7349       bar1_remap_failed:
7350         iounmap(sp->bar0);
7351       bar0_remap_failed:
7352       mem_alloc_failed:
7353         free_shared_mem(sp);
7354         pci_disable_device(pdev);
7355         pci_release_regions(pdev);
7356         pci_set_drvdata(pdev, NULL);
7357         free_netdev(dev);
7358
7359         return ret;
7360 }
7361
7362 /**
7363  * s2io_rem_nic - Free the PCI device
7364  * @pdev: structure containing the PCI related information of the device.
7365  * Description: This function is called by the Pci subsystem to release a
7366  * PCI device and free up all resource held up by the device. This could
7367  * be in response to a Hot plug event or when the driver is to be removed
7368  * from memory.
7369  */
7370
7371 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7372 {
7373         struct net_device *dev =
7374             (struct net_device *) pci_get_drvdata(pdev);
7375         struct s2io_nic *sp;
7376
7377         if (dev == NULL) {
7378                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7379                 return;
7380         }
7381
7382         flush_scheduled_work();
7383
7384         sp = dev->priv;
7385         unregister_netdev(dev);
7386
7387         free_shared_mem(sp);
7388         iounmap(sp->bar0);
7389         iounmap(sp->bar1);
7390         pci_release_regions(pdev);
7391         pci_set_drvdata(pdev, NULL);
7392         free_netdev(dev);
7393         pci_disable_device(pdev);
7394 }
7395
7396 /**
7397  * s2io_starter - Entry point for the driver
7398  * Description: This function is the entry point for the driver. It verifies
7399  * the module loadable parameters and initializes PCI configuration space.
7400  */
7401
7402 int __init s2io_starter(void)
7403 {
7404         return pci_register_driver(&s2io_driver);
7405 }
7406
7407 /**
7408  * s2io_closer - Cleanup routine for the driver
7409  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7410  */
7411
7412 static __exit void s2io_closer(void)
7413 {
7414         pci_unregister_driver(&s2io_driver);
7415         DBG_PRINT(INIT_DBG, "cleanup done\n");
7416 }
7417
7418 module_init(s2io_starter);
7419 module_exit(s2io_closer);
7420
7421 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7422                 struct tcphdr **tcp, struct RxD_t *rxdp)
7423 {
7424         int ip_off;
7425         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7426
7427         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7428                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7429                           __FUNCTION__);
7430                 return -1;
7431         }
7432
7433         /* TODO:
7434          * By default the VLAN field in the MAC is stripped by the card, if this
7435          * feature is turned off in rx_pa_cfg register, then the ip_off field
7436          * has to be shifted by a further 2 bytes
7437          */
7438         switch (l2_type) {
7439                 case 0: /* DIX type */
7440                 case 4: /* DIX type with VLAN */
7441                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7442                         break;
7443                 /* LLC, SNAP etc are considered non-mergeable */
7444                 default:
7445                         return -1;
7446         }
7447
7448         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7449         ip_len = (u8)((*ip)->ihl);
7450         ip_len <<= 2;
7451         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7452
7453         return 0;
7454 }
7455
7456 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7457                                   struct tcphdr *tcp)
7458 {
7459         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7460         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7461            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7462                 return -1;
7463         return 0;
7464 }
7465
7466 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7467 {
7468         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7469 }
7470
7471 static void initiate_new_session(struct lro *lro, u8 *l2h,
7472                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7473 {
7474         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7475         lro->l2h = l2h;
7476         lro->iph = ip;
7477         lro->tcph = tcp;
7478         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7479         lro->tcp_ack = ntohl(tcp->ack_seq);
7480         lro->sg_num = 1;
7481         lro->total_len = ntohs(ip->tot_len);
7482         lro->frags_len = 0;
7483         /*
7484          * check if we saw TCP timestamp. Other consistency checks have
7485          * already been done.
7486          */
7487         if (tcp->doff == 8) {
7488                 u32 *ptr;
7489                 ptr = (u32 *)(tcp+1);
7490                 lro->saw_ts = 1;
7491                 lro->cur_tsval = *(ptr+1);
7492                 lro->cur_tsecr = *(ptr+2);
7493         }
7494         lro->in_use = 1;
7495 }
7496
7497 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7498 {
7499         struct iphdr *ip = lro->iph;
7500         struct tcphdr *tcp = lro->tcph;
7501         __sum16 nchk;
7502         struct stat_block *statinfo = sp->mac_control.stats_info;
7503         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7504
7505         /* Update L3 header */
7506         ip->tot_len = htons(lro->total_len);
7507         ip->check = 0;
7508         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7509         ip->check = nchk;
7510
7511         /* Update L4 header */
7512         tcp->ack_seq = lro->tcp_ack;
7513         tcp->window = lro->window;
7514
7515         /* Update tsecr field if this session has timestamps enabled */
7516         if (lro->saw_ts) {
7517                 u32 *ptr = (u32 *)(tcp + 1);
7518                 *(ptr+2) = lro->cur_tsecr;
7519         }
7520
7521         /* Update counters required for calculation of
7522          * average no. of packets aggregated.
7523          */
7524         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7525         statinfo->sw_stat.num_aggregations++;
7526 }
7527
7528 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7529                 struct tcphdr *tcp, u32 l4_pyld)
7530 {
7531         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7532         lro->total_len += l4_pyld;
7533         lro->frags_len += l4_pyld;
7534         lro->tcp_next_seq += l4_pyld;
7535         lro->sg_num++;
7536
7537         /* Update ack seq no. and window ad(from this pkt) in LRO object */
7538         lro->tcp_ack = tcp->ack_seq;
7539         lro->window = tcp->window;
7540
7541         if (lro->saw_ts) {
7542                 u32 *ptr;
7543                 /* Update tsecr and tsval from this packet */
7544                 ptr = (u32 *) (tcp + 1);
7545                 lro->cur_tsval = *(ptr + 1);
7546                 lro->cur_tsecr = *(ptr + 2);
7547         }
7548 }
7549
7550 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7551                                     struct tcphdr *tcp, u32 tcp_pyld_len)
7552 {
7553         u8 *ptr;
7554
7555         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7556
7557         if (!tcp_pyld_len) {
7558                 /* Runt frame or a pure ack */
7559                 return -1;
7560         }
7561
7562         if (ip->ihl != 5) /* IP has options */
7563                 return -1;
7564
7565         /* If we see CE codepoint in IP header, packet is not mergeable */
7566         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7567                 return -1;
7568
7569         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7570         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7571                                     tcp->ece || tcp->cwr || !tcp->ack) {
7572                 /*
7573                  * Currently recognize only the ack control word and
7574                  * any other control field being set would result in
7575                  * flushing the LRO session
7576                  */
7577                 return -1;
7578         }
7579
7580         /*
7581          * Allow only one TCP timestamp option. Don't aggregate if
7582          * any other options are detected.
7583          */
7584         if (tcp->doff != 5 && tcp->doff != 8)
7585                 return -1;
7586
7587         if (tcp->doff == 8) {
7588                 ptr = (u8 *)(tcp + 1);
7589                 while (*ptr == TCPOPT_NOP)
7590                         ptr++;
7591                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7592                         return -1;
7593
7594                 /* Ensure timestamp value increases monotonically */
7595                 if (l_lro)
7596                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7597                                 return -1;
7598
7599                 /* timestamp echo reply should be non-zero */
7600                 if (*((u32 *)(ptr+6)) == 0)
7601                         return -1;
7602         }
7603
7604         return 0;
7605 }
7606
7607 static int
7608 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7609                       struct RxD_t *rxdp, struct s2io_nic *sp)
7610 {
7611         struct iphdr *ip;
7612         struct tcphdr *tcph;
7613         int ret = 0, i;
7614
7615         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7616                                          rxdp))) {
7617                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7618                           ip->saddr, ip->daddr);
7619         } else {
7620                 return ret;
7621         }
7622
7623         tcph = (struct tcphdr *)*tcp;
7624         *tcp_len = get_l4_pyld_length(ip, tcph);
7625         for (i=0; i<MAX_LRO_SESSIONS; i++) {
7626                 struct lro *l_lro = &sp->lro0_n[i];
7627                 if (l_lro->in_use) {
7628                         if (check_for_socket_match(l_lro, ip, tcph))
7629                                 continue;
7630                         /* Sock pair matched */
7631                         *lro = l_lro;
7632
7633                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7634                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7635                                           "0x%x, actual 0x%x\n", __FUNCTION__,
7636                                           (*lro)->tcp_next_seq,
7637                                           ntohl(tcph->seq));
7638
7639                                 sp->mac_control.stats_info->
7640                                    sw_stat.outof_sequence_pkts++;
7641                                 ret = 2;
7642                                 break;
7643                         }
7644
7645                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7646                                 ret = 1; /* Aggregate */
7647                         else
7648                                 ret = 2; /* Flush both */
7649                         break;
7650                 }
7651         }
7652
7653         if (ret == 0) {
7654                 /* Before searching for available LRO objects,
7655                  * check if the pkt is L3/L4 aggregatable. If not
7656                  * don't create new LRO session. Just send this
7657                  * packet up.
7658                  */
7659                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7660                         return 5;
7661                 }
7662
7663                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7664                         struct lro *l_lro = &sp->lro0_n[i];
7665                         if (!(l_lro->in_use)) {
7666                                 *lro = l_lro;
7667                                 ret = 3; /* Begin anew */
7668                                 break;
7669                         }
7670                 }
7671         }
7672
7673         if (ret == 0) { /* sessions exceeded */
7674                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7675                           __FUNCTION__);
7676                 *lro = NULL;
7677                 return ret;
7678         }
7679
7680         switch (ret) {
7681                 case 3:
7682                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7683                         break;
7684                 case 2:
7685                         update_L3L4_header(sp, *lro);
7686                         break;
7687                 case 1:
7688                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7689                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7690                                 update_L3L4_header(sp, *lro);
7691                                 ret = 4; /* Flush the LRO */
7692                         }
7693                         break;
7694                 default:
7695                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7696                                 __FUNCTION__);
7697                         break;
7698         }
7699
7700         return ret;
7701 }
7702
7703 static void clear_lro_session(struct lro *lro)
7704 {
7705         static u16 lro_struct_size = sizeof(struct lro);
7706
7707         memset(lro, 0, lro_struct_size);
7708 }
7709
7710 static void queue_rx_frame(struct sk_buff *skb)
7711 {
7712         struct net_device *dev = skb->dev;
7713
7714         skb->protocol = eth_type_trans(skb, dev);
7715         if (napi)
7716                 netif_receive_skb(skb);
7717         else
7718                 netif_rx(skb);
7719 }
7720
7721 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7722                            struct sk_buff *skb,
7723                            u32 tcp_len)
7724 {
7725         struct sk_buff *first = lro->parent;
7726
7727         first->len += tcp_len;
7728         first->data_len = lro->frags_len;
7729         skb_pull(skb, (skb->len - tcp_len));
7730         if (skb_shinfo(first)->frag_list)
7731                 lro->last_frag->next = skb;
7732         else
7733                 skb_shinfo(first)->frag_list = skb;
7734         first->truesize += skb->truesize;
7735         lro->last_frag = skb;
7736         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7737         return;
7738 }
7739
7740 /**
7741  * s2io_io_error_detected - called when PCI error is detected
7742  * @pdev: Pointer to PCI device
7743  * @state: The current pci connection state
7744  *
7745  * This function is called after a PCI bus error affecting
7746  * this device has been detected.
7747  */
7748 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
7749                                                pci_channel_state_t state)
7750 {
7751         struct net_device *netdev = pci_get_drvdata(pdev);
7752         struct s2io_nic *sp = netdev->priv;
7753
7754         netif_device_detach(netdev);
7755
7756         if (netif_running(netdev)) {
7757                 /* Bring down the card, while avoiding PCI I/O */
7758                 do_s2io_card_down(sp, 0);
7759         }
7760         pci_disable_device(pdev);
7761
7762         return PCI_ERS_RESULT_NEED_RESET;
7763 }
7764
7765 /**
7766  * s2io_io_slot_reset - called after the pci bus has been reset.
7767  * @pdev: Pointer to PCI device
7768  *
7769  * Restart the card from scratch, as if from a cold-boot.
7770  * At this point, the card has exprienced a hard reset,
7771  * followed by fixups by BIOS, and has its config space
7772  * set up identically to what it was at cold boot.
7773  */
7774 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
7775 {
7776         struct net_device *netdev = pci_get_drvdata(pdev);
7777         struct s2io_nic *sp = netdev->priv;
7778
7779         if (pci_enable_device(pdev)) {
7780                 printk(KERN_ERR "s2io: "
7781                        "Cannot re-enable PCI device after reset.\n");
7782                 return PCI_ERS_RESULT_DISCONNECT;
7783         }
7784
7785         pci_set_master(pdev);
7786         s2io_reset(sp);
7787
7788         return PCI_ERS_RESULT_RECOVERED;
7789 }
7790
7791 /**
7792  * s2io_io_resume - called when traffic can start flowing again.
7793  * @pdev: Pointer to PCI device
7794  *
7795  * This callback is called when the error recovery driver tells
7796  * us that its OK to resume normal operation.
7797  */
7798 static void s2io_io_resume(struct pci_dev *pdev)
7799 {
7800         struct net_device *netdev = pci_get_drvdata(pdev);
7801         struct s2io_nic *sp = netdev->priv;
7802
7803         if (netif_running(netdev)) {
7804                 if (s2io_card_up(sp)) {
7805                         printk(KERN_ERR "s2io: "
7806                                "Can't bring device back up after reset.\n");
7807                         return;
7808                 }
7809
7810                 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
7811                         s2io_card_down(sp);
7812                         printk(KERN_ERR "s2io: "
7813                                "Can't resetore mac addr after reset.\n");
7814                         return;
7815                 }
7816         }
7817
7818         netif_device_attach(netdev);
7819         netif_wake_queue(netdev);
7820 }