1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
82 #include <asm/system.h>
83 #include <asm/div64.h>
88 #include "s2io-regs.h"
90 #define DRV_VERSION "2.0.26.25"
92 /* S2io Driver name & version. */
93 static char s2io_driver_name[] = "Neterion";
94 static char s2io_driver_version[] = DRV_VERSION;
96 static int rxd_size[2] = {32, 48};
97 static int rxd_count[2] = {127, 85};
99 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
103 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
104 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
114 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
119 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
122 static inline int is_s2io_card_up(const struct s2io_nic *sp)
124 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127 /* Ethtool related variables and Macros. */
128 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
136 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
138 {"tmac_data_octets"},
142 {"tmac_pause_ctrl_frms"},
146 {"tmac_any_err_frms"},
147 {"tmac_ttl_less_fb_octets"},
148 {"tmac_vld_ip_octets"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
162 {"rmac_out_rng_len_err_frms"},
164 {"rmac_pause_ctrl_frms"},
165 {"rmac_unsup_ctrl_frms"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
169 {"rmac_discarded_frms"},
170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
176 {"rmac_jabber_frms"},
177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
190 {"rmac_err_drp_udp"},
191 {"rmac_xgmii_err_sym"},
209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
211 {"rmac_accepted_ip"},
215 {"new_rd_req_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
220 {"new_wr_req_rtry_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
233 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
252 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
320 {"prc_pcix_err_cnt"},
327 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
331 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
332 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
334 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
335 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
337 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
338 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
340 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long)arg; \
344 mod_timer(&timer, (jiffies + exp)) \
346 /* copy mac addr to def_mac_addr array */
347 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
349 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
350 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
351 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
352 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
353 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
354 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
358 static void s2io_vlan_rx_register(struct net_device *dev,
359 struct vlan_group *grp)
362 struct s2io_nic *nic = netdev_priv(dev);
363 unsigned long flags[MAX_TX_FIFOS];
364 struct mac_info *mac_control = &nic->mac_control;
365 struct config_param *config = &nic->config;
367 for (i = 0; i < config->tx_fifo_num; i++) {
368 struct fifo_info *fifo = &mac_control->fifos[i];
370 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
375 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
376 struct fifo_info *fifo = &mac_control->fifos[i];
378 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
382 /* Unregister the vlan */
383 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
386 struct s2io_nic *nic = netdev_priv(dev);
387 unsigned long flags[MAX_TX_FIFOS];
388 struct mac_info *mac_control = &nic->mac_control;
389 struct config_param *config = &nic->config;
391 for (i = 0; i < config->tx_fifo_num; i++) {
392 struct fifo_info *fifo = &mac_control->fifos[i];
394 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
398 vlan_group_set_device(nic->vlgrp, vid, NULL);
400 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
401 struct fifo_info *fifo = &mac_control->fifos[i];
403 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
408 * Constants to be programmed into the Xena's registers, to configure
413 static const u64 herc_act_dtx_cfg[] = {
415 0x8000051536750000ULL, 0x80000515367500E0ULL,
417 0x8000051536750004ULL, 0x80000515367500E4ULL,
419 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
421 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
423 0x801205150D440000ULL, 0x801205150D4400E0ULL,
425 0x801205150D440004ULL, 0x801205150D4400E4ULL,
427 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
429 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
434 static const u64 xena_dtx_cfg[] = {
436 0x8000051500000000ULL, 0x80000515000000E0ULL,
438 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
440 0x8001051500000000ULL, 0x80010515000000E0ULL,
442 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
444 0x8002051500000000ULL, 0x80020515000000E0ULL,
446 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
451 * Constants for Fixing the MacAddress problem seen mostly on
454 static const u64 fix_mac[] = {
455 0x0060000000000000ULL, 0x0060600000000000ULL,
456 0x0040600000000000ULL, 0x0000600000000000ULL,
457 0x0020600000000000ULL, 0x0060600000000000ULL,
458 0x0020600000000000ULL, 0x0060600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0000600000000000ULL,
468 0x0040600000000000ULL, 0x0060600000000000ULL,
472 MODULE_LICENSE("GPL");
473 MODULE_VERSION(DRV_VERSION);
476 /* Module Loadable parameters. */
477 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
478 S2IO_PARM_INT(rx_ring_num, 1);
479 S2IO_PARM_INT(multiq, 0);
480 S2IO_PARM_INT(rx_ring_mode, 1);
481 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
482 S2IO_PARM_INT(rmac_pause_time, 0x100);
483 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
484 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
485 S2IO_PARM_INT(shared_splits, 0);
486 S2IO_PARM_INT(tmac_util_period, 5);
487 S2IO_PARM_INT(rmac_util_period, 5);
488 S2IO_PARM_INT(l3l4hdr_size, 128);
489 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
490 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
491 /* Frequency of Rx desc syncs expressed as power of 2 */
492 S2IO_PARM_INT(rxsync_frequency, 3);
493 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
494 S2IO_PARM_INT(intr_type, 2);
495 /* Large receive offload feature */
496 static unsigned int lro_enable;
497 module_param_named(lro, lro_enable, uint, 0);
499 /* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
502 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
503 S2IO_PARM_INT(indicate_max_pkts, 0);
505 S2IO_PARM_INT(napi, 1);
506 S2IO_PARM_INT(ufo, 0);
507 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
509 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
510 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
511 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
512 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
513 static unsigned int rts_frm_len[MAX_RX_RINGS] =
514 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
516 module_param_array(tx_fifo_len, uint, NULL, 0);
517 module_param_array(rx_ring_sz, uint, NULL, 0);
518 module_param_array(rts_frm_len, uint, NULL, 0);
522 * This table lists all the devices that this driver supports.
524 static struct pci_device_id s2io_tbl[] __devinitdata = {
525 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526 PCI_ANY_ID, PCI_ANY_ID},
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
536 MODULE_DEVICE_TABLE(pci, s2io_tbl);
538 static struct pci_error_handlers s2io_err_handler = {
539 .error_detected = s2io_io_error_detected,
540 .slot_reset = s2io_io_slot_reset,
541 .resume = s2io_io_resume,
544 static struct pci_driver s2io_driver = {
546 .id_table = s2io_tbl,
547 .probe = s2io_init_nic,
548 .remove = __devexit_p(s2io_rem_nic),
549 .err_handler = &s2io_err_handler,
552 /* A simplifier macro used both by init and free shared_mem Fns(). */
553 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
555 /* netqueue manipulation helper functions */
556 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
558 if (!sp->config.multiq) {
561 for (i = 0; i < sp->config.tx_fifo_num; i++)
562 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
564 netif_tx_stop_all_queues(sp->dev);
567 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
569 if (!sp->config.multiq)
570 sp->mac_control.fifos[fifo_no].queue_state =
573 netif_tx_stop_all_queues(sp->dev);
576 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
578 if (!sp->config.multiq) {
581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
584 netif_tx_start_all_queues(sp->dev);
587 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
589 if (!sp->config.multiq)
590 sp->mac_control.fifos[fifo_no].queue_state =
593 netif_tx_start_all_queues(sp->dev);
596 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
598 if (!sp->config.multiq) {
601 for (i = 0; i < sp->config.tx_fifo_num; i++)
602 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
604 netif_tx_wake_all_queues(sp->dev);
607 static inline void s2io_wake_tx_queue(
608 struct fifo_info *fifo, int cnt, u8 multiq)
612 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
614 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
615 if (netif_queue_stopped(fifo->dev)) {
616 fifo->queue_state = FIFO_QUEUE_START;
617 netif_wake_queue(fifo->dev);
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
627 * Rx descriptors and the statistics block.
630 static int init_shared_mem(struct s2io_nic *nic)
633 void *tmp_v_addr, *tmp_v_addr_next;
634 dma_addr_t tmp_p_addr, tmp_p_addr_next;
635 struct RxD_block *pre_rxd_blk = NULL;
637 int lst_size, lst_per_page;
638 struct net_device *dev = nic->dev;
642 struct mac_info *mac_control;
643 struct config_param *config;
644 unsigned long long mem_allocated = 0;
646 mac_control = &nic->mac_control;
647 config = &nic->config;
649 /* Allocation and initialization of TXDLs in FIFOs */
651 for (i = 0; i < config->tx_fifo_num; i++) {
652 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
654 size += tx_cfg->fifo_len;
656 if (size > MAX_AVAILABLE_TXDS) {
657 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
658 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n",
664 for (i = 0; i < config->tx_fifo_num; i++) {
665 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
667 size = tx_cfg->fifo_len;
669 * Legal values are from 2 to 8192
672 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
673 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
674 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
680 lst_size = (sizeof(struct TxD) * config->max_txds);
681 lst_per_page = PAGE_SIZE / lst_size;
683 for (i = 0; i < config->tx_fifo_num; i++) {
684 struct fifo_info *fifo = &mac_control->fifos[i];
685 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
686 int fifo_len = tx_cfg->fifo_len;
687 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
689 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
690 if (!fifo->list_info) {
691 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
694 mem_allocated += list_holder_size;
696 for (i = 0; i < config->tx_fifo_num; i++) {
697 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
699 struct fifo_info *fifo = &mac_control->fifos[i];
700 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
702 fifo->tx_curr_put_info.offset = 0;
703 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->tx_curr_get_info.offset = 0;
705 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
708 fifo->max_txds = MAX_SKB_FRAGS + 2;
711 for (j = 0; j < page_num; j++) {
715 tmp_v = pci_alloc_consistent(nic->pdev,
718 DBG_PRINT(INFO_DBG, "pci_alloc_consistent ");
719 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
722 /* If we got a zero DMA address(can happen on
723 * certain platforms like PPC), reallocate.
724 * Store virtual address of page we don't want,
728 mac_control->zerodma_virt_addr = tmp_v;
730 "%s: Zero DMA address for TxDL. ",
733 "Virtual address %p\n", tmp_v);
734 tmp_v = pci_alloc_consistent(nic->pdev,
738 "pci_alloc_consistent ");
740 "failed for TxDL\n");
743 mem_allocated += PAGE_SIZE;
745 while (k < lst_per_page) {
746 int l = (j * lst_per_page) + k;
747 if (l == tx_cfg->fifo_len)
749 fifo->list_info[l].list_virt_addr =
750 tmp_v + (k * lst_size);
751 fifo->list_info[l].list_phy_addr =
752 tmp_p + (k * lst_size);
758 for (i = 0; i < config->tx_fifo_num; i++) {
759 struct fifo_info *fifo = &mac_control->fifos[i];
760 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
762 size = tx_cfg->fifo_len;
763 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
764 if (!fifo->ufo_in_band_v)
766 mem_allocated += (size * sizeof(u64));
769 /* Allocation and initialization of RXDs in Rings */
771 for (i = 0; i < config->rx_ring_num; i++) {
772 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
773 struct ring_info *ring = &mac_control->rings[i];
775 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
776 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
777 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
778 DBG_PRINT(ERR_DBG, "RxDs per Block");
781 size += rx_cfg->num_rxd;
782 ring->block_count = rx_cfg->num_rxd /
783 (rxd_count[nic->rxd_mode] + 1);
784 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
786 if (nic->rxd_mode == RXD_MODE_1)
787 size = (size * (sizeof(struct RxD1)));
789 size = (size * (sizeof(struct RxD3)));
791 for (i = 0; i < config->rx_ring_num; i++) {
792 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
793 struct ring_info *ring = &mac_control->rings[i];
795 ring->rx_curr_get_info.block_index = 0;
796 ring->rx_curr_get_info.offset = 0;
797 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
798 ring->rx_curr_put_info.block_index = 0;
799 ring->rx_curr_put_info.offset = 0;
800 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
803 ring->lro = lro_enable;
805 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
806 /* Allocating all the Rx blocks */
807 for (j = 0; j < blk_cnt; j++) {
808 struct rx_block_info *rx_blocks;
811 rx_blocks = &ring->rx_blocks[j];
812 size = SIZE_OF_BLOCK; /* size is always page size */
813 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
815 if (tmp_v_addr == NULL) {
817 * In case of failure, free_shared_mem()
818 * is called, which should free any
819 * memory that was alloced till the
822 rx_blocks->block_virt_addr = tmp_v_addr;
825 mem_allocated += size;
826 memset(tmp_v_addr, 0, size);
828 size = sizeof(struct rxd_info) *
829 rxd_count[nic->rxd_mode];
830 rx_blocks->block_virt_addr = tmp_v_addr;
831 rx_blocks->block_dma_addr = tmp_p_addr;
832 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
833 if (!rx_blocks->rxds)
835 mem_allocated += size;
836 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
837 rx_blocks->rxds[l].virt_addr =
838 rx_blocks->block_virt_addr +
839 (rxd_size[nic->rxd_mode] * l);
840 rx_blocks->rxds[l].dma_addr =
841 rx_blocks->block_dma_addr +
842 (rxd_size[nic->rxd_mode] * l);
845 /* Interlinking all Rx Blocks */
846 for (j = 0; j < blk_cnt; j++) {
847 int next = (j + 1) % blk_cnt;
848 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
849 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
850 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
851 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
853 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
854 pre_rxd_blk->reserved_2_pNext_RxD_block =
855 (unsigned long)tmp_v_addr_next;
856 pre_rxd_blk->pNext_RxD_Blk_physical =
857 (u64)tmp_p_addr_next;
860 if (nic->rxd_mode == RXD_MODE_3B) {
862 * Allocation of Storages for buffer addresses in 2BUFF mode
863 * and the buffers as well.
865 for (i = 0; i < config->rx_ring_num; i++) {
866 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
867 struct ring_info *ring = &mac_control->rings[i];
869 blk_cnt = rx_cfg->num_rxd /
870 (rxd_count[nic->rxd_mode] + 1);
871 size = sizeof(struct buffAdd *) * blk_cnt;
872 ring->ba = kmalloc(size, GFP_KERNEL);
875 mem_allocated += size;
876 for (j = 0; j < blk_cnt; j++) {
879 size = sizeof(struct buffAdd) *
880 (rxd_count[nic->rxd_mode] + 1);
881 ring->ba[j] = kmalloc(size, GFP_KERNEL);
884 mem_allocated += size;
885 while (k != rxd_count[nic->rxd_mode]) {
886 ba = &ring->ba[j][k];
887 size = BUF0_LEN + ALIGN_SIZE;
888 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
891 mem_allocated += size;
892 tmp = (unsigned long)ba->ba_0_org;
894 tmp &= ~((unsigned long)ALIGN_SIZE);
895 ba->ba_0 = (void *)tmp;
897 size = BUF1_LEN + ALIGN_SIZE;
898 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
901 mem_allocated += size;
902 tmp = (unsigned long)ba->ba_1_org;
904 tmp &= ~((unsigned long)ALIGN_SIZE);
905 ba->ba_1 = (void *)tmp;
912 /* Allocation and initialization of Statistics block */
913 size = sizeof(struct stat_block);
914 mac_control->stats_mem =
915 pci_alloc_consistent(nic->pdev, size,
916 &mac_control->stats_mem_phy);
918 if (!mac_control->stats_mem) {
920 * In case of failure, free_shared_mem() is called, which
921 * should free any memory that was alloced till the
926 mem_allocated += size;
927 mac_control->stats_mem_sz = size;
929 tmp_v_addr = mac_control->stats_mem;
930 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
931 memset(tmp_v_addr, 0, size);
932 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
933 (unsigned long long)tmp_p_addr);
934 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
939 * free_shared_mem - Free the allocated Memory
940 * @nic: Device private variable.
941 * Description: This function is to free all memory locations allocated by
942 * the init_shared_mem() function and return it to the kernel.
945 static void free_shared_mem(struct s2io_nic *nic)
947 int i, j, blk_cnt, size;
949 dma_addr_t tmp_p_addr;
950 struct mac_info *mac_control;
951 struct config_param *config;
952 int lst_size, lst_per_page;
953 struct net_device *dev;
961 mac_control = &nic->mac_control;
962 config = &nic->config;
964 lst_size = sizeof(struct TxD) * config->max_txds;
965 lst_per_page = PAGE_SIZE / lst_size;
967 for (i = 0; i < config->tx_fifo_num; i++) {
968 struct fifo_info *fifo = &mac_control->fifos[i];
969 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
971 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
972 for (j = 0; j < page_num; j++) {
973 int mem_blks = (j * lst_per_page);
974 struct list_info_hold *fli;
976 if (!fifo->list_info)
979 fli = &fifo->list_info[mem_blks];
980 if (!fli->list_virt_addr)
982 pci_free_consistent(nic->pdev, PAGE_SIZE,
985 nic->mac_control.stats_info->sw_stat.mem_freed
988 /* If we got a zero DMA address during allocation,
991 if (mac_control->zerodma_virt_addr) {
992 pci_free_consistent(nic->pdev, PAGE_SIZE,
993 mac_control->zerodma_virt_addr,
996 "%s: Freeing TxDL with zero DMA addr. ",
998 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
999 mac_control->zerodma_virt_addr);
1000 nic->mac_control.stats_info->sw_stat.mem_freed
1003 kfree(fifo->list_info);
1004 nic->mac_control.stats_info->sw_stat.mem_freed +=
1005 nic->config.tx_cfg[i].fifo_len *
1006 sizeof(struct list_info_hold);
1009 size = SIZE_OF_BLOCK;
1010 for (i = 0; i < config->rx_ring_num; i++) {
1011 struct ring_info *ring = &mac_control->rings[i];
1013 blk_cnt = ring->block_count;
1014 for (j = 0; j < blk_cnt; j++) {
1015 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1016 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1017 if (tmp_v_addr == NULL)
1019 pci_free_consistent(nic->pdev, size,
1020 tmp_v_addr, tmp_p_addr);
1021 nic->mac_control.stats_info->sw_stat.mem_freed += size;
1022 kfree(ring->rx_blocks[j].rxds);
1023 nic->mac_control.stats_info->sw_stat.mem_freed +=
1024 sizeof(struct rxd_info) * rxd_count[nic->rxd_mode];
1028 if (nic->rxd_mode == RXD_MODE_3B) {
1029 /* Freeing buffer storage addresses in 2BUFF mode. */
1030 for (i = 0; i < config->rx_ring_num; i++) {
1031 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1032 struct ring_info *ring = &mac_control->rings[i];
1034 blk_cnt = rx_cfg->num_rxd /
1035 (rxd_count[nic->rxd_mode] + 1);
1036 for (j = 0; j < blk_cnt; j++) {
1040 while (k != rxd_count[nic->rxd_mode]) {
1041 struct buffAdd *ba = &ring->ba[j][k];
1042 kfree(ba->ba_0_org);
1043 nic->mac_control.stats_info->sw_stat.\
1044 mem_freed += (BUF0_LEN + ALIGN_SIZE);
1045 kfree(ba->ba_1_org);
1046 nic->mac_control.stats_info->sw_stat.\
1047 mem_freed += (BUF1_LEN + ALIGN_SIZE);
1051 nic->mac_control.stats_info->sw_stat.mem_freed +=
1052 (sizeof(struct buffAdd) *
1053 (rxd_count[nic->rxd_mode] + 1));
1056 nic->mac_control.stats_info->sw_stat.mem_freed +=
1057 (sizeof(struct buffAdd *) * blk_cnt);
1061 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1062 struct fifo_info *fifo = &mac_control->fifos[i];
1063 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1065 if (fifo->ufo_in_band_v) {
1066 nic->mac_control.stats_info->sw_stat.mem_freed
1067 += (tx_cfg->fifo_len * sizeof(u64));
1068 kfree(fifo->ufo_in_band_v);
1072 if (mac_control->stats_mem) {
1073 nic->mac_control.stats_info->sw_stat.mem_freed +=
1074 mac_control->stats_mem_sz;
1075 pci_free_consistent(nic->pdev,
1076 mac_control->stats_mem_sz,
1077 mac_control->stats_mem,
1078 mac_control->stats_mem_phy);
1083 * s2io_verify_pci_mode -
1086 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1088 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1089 register u64 val64 = 0;
1092 val64 = readq(&bar0->pci_mode);
1093 mode = (u8)GET_PCI_MODE(val64);
1095 if (val64 & PCI_MODE_UNKNOWN_MODE)
1096 return -1; /* Unknown PCI mode */
1100 #define NEC_VENID 0x1033
1101 #define NEC_DEVID 0x0125
1102 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1104 struct pci_dev *tdev = NULL;
1105 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1106 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1107 if (tdev->bus == s2io_pdev->bus->parent) {
1116 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1118 * s2io_print_pci_mode -
1120 static int s2io_print_pci_mode(struct s2io_nic *nic)
1122 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1123 register u64 val64 = 0;
1125 struct config_param *config = &nic->config;
1127 val64 = readq(&bar0->pci_mode);
1128 mode = (u8)GET_PCI_MODE(val64);
1130 if (val64 & PCI_MODE_UNKNOWN_MODE)
1131 return -1; /* Unknown PCI mode */
1133 config->bus_speed = bus_speed[mode];
1135 if (s2io_on_nec_bridge(nic->pdev)) {
1136 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1141 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit ",
1142 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64);
1145 case PCI_MODE_PCI_33:
1146 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1148 case PCI_MODE_PCI_66:
1149 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1151 case PCI_MODE_PCIX_M1_66:
1152 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1154 case PCI_MODE_PCIX_M1_100:
1155 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1157 case PCI_MODE_PCIX_M1_133:
1158 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1160 case PCI_MODE_PCIX_M2_66:
1161 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1163 case PCI_MODE_PCIX_M2_100:
1164 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1166 case PCI_MODE_PCIX_M2_133:
1167 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1170 return -1; /* Unsupported bus speed */
1177 * init_tti - Initialization transmit traffic interrupt scheme
1178 * @nic: device private variable
1179 * @link: link status (UP/DOWN) used to enable/disable continuous
1180 * transmit interrupts
1181 * Description: The function configures transmit traffic interrupts
1182 * Return Value: SUCCESS on success and
1186 static int init_tti(struct s2io_nic *nic, int link)
1188 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1189 register u64 val64 = 0;
1191 struct config_param *config;
1193 config = &nic->config;
1195 for (i = 0; i < config->tx_fifo_num; i++) {
1197 * TTI Initialization. Default Tx timer gets us about
1198 * 250 interrupts per sec. Continuous interrupts are enabled
1201 if (nic->device_type == XFRAME_II_DEVICE) {
1202 int count = (nic->config.bus_speed * 125)/2;
1203 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1205 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1207 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1208 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1209 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1210 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1212 if (use_continuous_tx_intrs && (link == LINK_UP))
1213 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1214 writeq(val64, &bar0->tti_data1_mem);
1216 if (nic->config.intr_type == MSI_X) {
1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x300);
1222 if ((nic->config.tx_steering_type ==
1223 TX_DEFAULT_STEERING) &&
1224 (config->tx_fifo_num > 1) &&
1225 (i >= nic->udp_fifo_idx) &&
1226 (i < (nic->udp_fifo_idx +
1227 nic->total_udp_fifos)))
1228 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1229 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1230 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1231 TTI_DATA2_MEM_TX_UFC_D(0x120);
1233 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1234 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1235 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1236 TTI_DATA2_MEM_TX_UFC_D(0x80);
1239 writeq(val64, &bar0->tti_data2_mem);
1241 val64 = TTI_CMD_MEM_WE |
1242 TTI_CMD_MEM_STROBE_NEW_CMD |
1243 TTI_CMD_MEM_OFFSET(i);
1244 writeq(val64, &bar0->tti_command_mem);
1246 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1247 TTI_CMD_MEM_STROBE_NEW_CMD,
1248 S2IO_BIT_RESET) != SUCCESS)
1256 * init_nic - Initialization of hardware
1257 * @nic: device private variable
1258 * Description: The function sequentially configures every block
1259 * of the H/W from their reset values.
1260 * Return Value: SUCCESS on success and
1261 * '-1' on failure (endian settings incorrect).
1264 static int init_nic(struct s2io_nic *nic)
1266 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1267 struct net_device *dev = nic->dev;
1268 register u64 val64 = 0;
1272 struct mac_info *mac_control;
1273 struct config_param *config;
1275 unsigned long long mem_share;
1278 mac_control = &nic->mac_control;
1279 config = &nic->config;
1281 /* to set the swapper controle on the card */
1282 if (s2io_set_swapper(nic)) {
1283 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1288 * Herc requires EOI to be removed from reset before XGXS, so..
1290 if (nic->device_type & XFRAME_II_DEVICE) {
1291 val64 = 0xA500000000ULL;
1292 writeq(val64, &bar0->sw_reset);
1294 val64 = readq(&bar0->sw_reset);
1297 /* Remove XGXS from reset state */
1299 writeq(val64, &bar0->sw_reset);
1301 val64 = readq(&bar0->sw_reset);
1303 /* Ensure that it's safe to access registers by checking
1304 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1306 if (nic->device_type == XFRAME_II_DEVICE) {
1307 for (i = 0; i < 50; i++) {
1308 val64 = readq(&bar0->adapter_status);
1309 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1317 /* Enable Receiving broadcasts */
1318 add = &bar0->mac_cfg;
1319 val64 = readq(&bar0->mac_cfg);
1320 val64 |= MAC_RMAC_BCAST_ENABLE;
1321 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1322 writel((u32)val64, add);
1323 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1324 writel((u32) (val64 >> 32), (add + 4));
1326 /* Read registers in all blocks */
1327 val64 = readq(&bar0->mac_int_mask);
1328 val64 = readq(&bar0->mc_int_mask);
1329 val64 = readq(&bar0->xgxs_int_mask);
1333 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1335 if (nic->device_type & XFRAME_II_DEVICE) {
1336 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1337 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1338 &bar0->dtx_control, UF);
1340 msleep(1); /* Necessary!! */
1344 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1345 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1346 &bar0->dtx_control, UF);
1347 val64 = readq(&bar0->dtx_control);
1352 /* Tx DMA Initialization */
1354 writeq(val64, &bar0->tx_fifo_partition_0);
1355 writeq(val64, &bar0->tx_fifo_partition_1);
1356 writeq(val64, &bar0->tx_fifo_partition_2);
1357 writeq(val64, &bar0->tx_fifo_partition_3);
1359 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1360 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1362 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1363 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1365 if (i == (config->tx_fifo_num - 1)) {
1372 writeq(val64, &bar0->tx_fifo_partition_0);
1377 writeq(val64, &bar0->tx_fifo_partition_1);
1382 writeq(val64, &bar0->tx_fifo_partition_2);
1387 writeq(val64, &bar0->tx_fifo_partition_3);
1398 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1399 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1401 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1402 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1404 val64 = readq(&bar0->tx_fifo_partition_0);
1405 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1406 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1409 * Initialization of Tx_PA_CONFIG register to ignore packet
1410 * integrity checking.
1412 val64 = readq(&bar0->tx_pa_cfg);
1413 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1414 TX_PA_CFG_IGNORE_SNAP_OUI |
1415 TX_PA_CFG_IGNORE_LLC_CTRL |
1416 TX_PA_CFG_IGNORE_L2_ERR;
1417 writeq(val64, &bar0->tx_pa_cfg);
1419 /* Rx DMA intialization. */
1421 for (i = 0; i < config->rx_ring_num; i++) {
1422 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1424 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1426 writeq(val64, &bar0->rx_queue_priority);
1429 * Allocating equal share of memory to all the
1433 if (nic->device_type & XFRAME_II_DEVICE)
1438 for (i = 0; i < config->rx_ring_num; i++) {
1441 mem_share = (mem_size / config->rx_ring_num +
1442 mem_size % config->rx_ring_num);
1443 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1446 mem_share = (mem_size / config->rx_ring_num);
1447 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1450 mem_share = (mem_size / config->rx_ring_num);
1451 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1454 mem_share = (mem_size / config->rx_ring_num);
1455 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1458 mem_share = (mem_size / config->rx_ring_num);
1459 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1462 mem_share = (mem_size / config->rx_ring_num);
1463 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1466 mem_share = (mem_size / config->rx_ring_num);
1467 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1470 mem_share = (mem_size / config->rx_ring_num);
1471 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1475 writeq(val64, &bar0->rx_queue_cfg);
1478 * Filling Tx round robin registers
1479 * as per the number of FIFOs for equal scheduling priority
1481 switch (config->tx_fifo_num) {
1484 writeq(val64, &bar0->tx_w_round_robin_0);
1485 writeq(val64, &bar0->tx_w_round_robin_1);
1486 writeq(val64, &bar0->tx_w_round_robin_2);
1487 writeq(val64, &bar0->tx_w_round_robin_3);
1488 writeq(val64, &bar0->tx_w_round_robin_4);
1491 val64 = 0x0001000100010001ULL;
1492 writeq(val64, &bar0->tx_w_round_robin_0);
1493 writeq(val64, &bar0->tx_w_round_robin_1);
1494 writeq(val64, &bar0->tx_w_round_robin_2);
1495 writeq(val64, &bar0->tx_w_round_robin_3);
1496 val64 = 0x0001000100000000ULL;
1497 writeq(val64, &bar0->tx_w_round_robin_4);
1500 val64 = 0x0001020001020001ULL;
1501 writeq(val64, &bar0->tx_w_round_robin_0);
1502 val64 = 0x0200010200010200ULL;
1503 writeq(val64, &bar0->tx_w_round_robin_1);
1504 val64 = 0x0102000102000102ULL;
1505 writeq(val64, &bar0->tx_w_round_robin_2);
1506 val64 = 0x0001020001020001ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_3);
1508 val64 = 0x0200010200000000ULL;
1509 writeq(val64, &bar0->tx_w_round_robin_4);
1512 val64 = 0x0001020300010203ULL;
1513 writeq(val64, &bar0->tx_w_round_robin_0);
1514 writeq(val64, &bar0->tx_w_round_robin_1);
1515 writeq(val64, &bar0->tx_w_round_robin_2);
1516 writeq(val64, &bar0->tx_w_round_robin_3);
1517 val64 = 0x0001020300000000ULL;
1518 writeq(val64, &bar0->tx_w_round_robin_4);
1521 val64 = 0x0001020304000102ULL;
1522 writeq(val64, &bar0->tx_w_round_robin_0);
1523 val64 = 0x0304000102030400ULL;
1524 writeq(val64, &bar0->tx_w_round_robin_1);
1525 val64 = 0x0102030400010203ULL;
1526 writeq(val64, &bar0->tx_w_round_robin_2);
1527 val64 = 0x0400010203040001ULL;
1528 writeq(val64, &bar0->tx_w_round_robin_3);
1529 val64 = 0x0203040000000000ULL;
1530 writeq(val64, &bar0->tx_w_round_robin_4);
1533 val64 = 0x0001020304050001ULL;
1534 writeq(val64, &bar0->tx_w_round_robin_0);
1535 val64 = 0x0203040500010203ULL;
1536 writeq(val64, &bar0->tx_w_round_robin_1);
1537 val64 = 0x0405000102030405ULL;
1538 writeq(val64, &bar0->tx_w_round_robin_2);
1539 val64 = 0x0001020304050001ULL;
1540 writeq(val64, &bar0->tx_w_round_robin_3);
1541 val64 = 0x0203040500000000ULL;
1542 writeq(val64, &bar0->tx_w_round_robin_4);
1545 val64 = 0x0001020304050600ULL;
1546 writeq(val64, &bar0->tx_w_round_robin_0);
1547 val64 = 0x0102030405060001ULL;
1548 writeq(val64, &bar0->tx_w_round_robin_1);
1549 val64 = 0x0203040506000102ULL;
1550 writeq(val64, &bar0->tx_w_round_robin_2);
1551 val64 = 0x0304050600010203ULL;
1552 writeq(val64, &bar0->tx_w_round_robin_3);
1553 val64 = 0x0405060000000000ULL;
1554 writeq(val64, &bar0->tx_w_round_robin_4);
1557 val64 = 0x0001020304050607ULL;
1558 writeq(val64, &bar0->tx_w_round_robin_0);
1559 writeq(val64, &bar0->tx_w_round_robin_1);
1560 writeq(val64, &bar0->tx_w_round_robin_2);
1561 writeq(val64, &bar0->tx_w_round_robin_3);
1562 val64 = 0x0001020300000000ULL;
1563 writeq(val64, &bar0->tx_w_round_robin_4);
1567 /* Enable all configured Tx FIFO partitions */
1568 val64 = readq(&bar0->tx_fifo_partition_0);
1569 val64 |= (TX_FIFO_PARTITION_EN);
1570 writeq(val64, &bar0->tx_fifo_partition_0);
1572 /* Filling the Rx round robin registers as per the
1573 * number of Rings and steering based on QoS with
1576 switch (config->rx_ring_num) {
1579 writeq(val64, &bar0->rx_w_round_robin_0);
1580 writeq(val64, &bar0->rx_w_round_robin_1);
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1582 writeq(val64, &bar0->rx_w_round_robin_3);
1583 writeq(val64, &bar0->rx_w_round_robin_4);
1585 val64 = 0x8080808080808080ULL;
1586 writeq(val64, &bar0->rts_qos_steering);
1589 val64 = 0x0001000100010001ULL;
1590 writeq(val64, &bar0->rx_w_round_robin_0);
1591 writeq(val64, &bar0->rx_w_round_robin_1);
1592 writeq(val64, &bar0->rx_w_round_robin_2);
1593 writeq(val64, &bar0->rx_w_round_robin_3);
1594 val64 = 0x0001000100000000ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_4);
1597 val64 = 0x8080808040404040ULL;
1598 writeq(val64, &bar0->rts_qos_steering);
1601 val64 = 0x0001020001020001ULL;
1602 writeq(val64, &bar0->rx_w_round_robin_0);
1603 val64 = 0x0200010200010200ULL;
1604 writeq(val64, &bar0->rx_w_round_robin_1);
1605 val64 = 0x0102000102000102ULL;
1606 writeq(val64, &bar0->rx_w_round_robin_2);
1607 val64 = 0x0001020001020001ULL;
1608 writeq(val64, &bar0->rx_w_round_robin_3);
1609 val64 = 0x0200010200000000ULL;
1610 writeq(val64, &bar0->rx_w_round_robin_4);
1612 val64 = 0x8080804040402020ULL;
1613 writeq(val64, &bar0->rts_qos_steering);
1616 val64 = 0x0001020300010203ULL;
1617 writeq(val64, &bar0->rx_w_round_robin_0);
1618 writeq(val64, &bar0->rx_w_round_robin_1);
1619 writeq(val64, &bar0->rx_w_round_robin_2);
1620 writeq(val64, &bar0->rx_w_round_robin_3);
1621 val64 = 0x0001020300000000ULL;
1622 writeq(val64, &bar0->rx_w_round_robin_4);
1624 val64 = 0x8080404020201010ULL;
1625 writeq(val64, &bar0->rts_qos_steering);
1628 val64 = 0x0001020304000102ULL;
1629 writeq(val64, &bar0->rx_w_round_robin_0);
1630 val64 = 0x0304000102030400ULL;
1631 writeq(val64, &bar0->rx_w_round_robin_1);
1632 val64 = 0x0102030400010203ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_2);
1634 val64 = 0x0400010203040001ULL;
1635 writeq(val64, &bar0->rx_w_round_robin_3);
1636 val64 = 0x0203040000000000ULL;
1637 writeq(val64, &bar0->rx_w_round_robin_4);
1639 val64 = 0x8080404020201008ULL;
1640 writeq(val64, &bar0->rts_qos_steering);
1643 val64 = 0x0001020304050001ULL;
1644 writeq(val64, &bar0->rx_w_round_robin_0);
1645 val64 = 0x0203040500010203ULL;
1646 writeq(val64, &bar0->rx_w_round_robin_1);
1647 val64 = 0x0405000102030405ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_2);
1649 val64 = 0x0001020304050001ULL;
1650 writeq(val64, &bar0->rx_w_round_robin_3);
1651 val64 = 0x0203040500000000ULL;
1652 writeq(val64, &bar0->rx_w_round_robin_4);
1654 val64 = 0x8080404020100804ULL;
1655 writeq(val64, &bar0->rts_qos_steering);
1658 val64 = 0x0001020304050600ULL;
1659 writeq(val64, &bar0->rx_w_round_robin_0);
1660 val64 = 0x0102030405060001ULL;
1661 writeq(val64, &bar0->rx_w_round_robin_1);
1662 val64 = 0x0203040506000102ULL;
1663 writeq(val64, &bar0->rx_w_round_robin_2);
1664 val64 = 0x0304050600010203ULL;
1665 writeq(val64, &bar0->rx_w_round_robin_3);
1666 val64 = 0x0405060000000000ULL;
1667 writeq(val64, &bar0->rx_w_round_robin_4);
1669 val64 = 0x8080402010080402ULL;
1670 writeq(val64, &bar0->rts_qos_steering);
1673 val64 = 0x0001020304050607ULL;
1674 writeq(val64, &bar0->rx_w_round_robin_0);
1675 writeq(val64, &bar0->rx_w_round_robin_1);
1676 writeq(val64, &bar0->rx_w_round_robin_2);
1677 writeq(val64, &bar0->rx_w_round_robin_3);
1678 val64 = 0x0001020300000000ULL;
1679 writeq(val64, &bar0->rx_w_round_robin_4);
1681 val64 = 0x8040201008040201ULL;
1682 writeq(val64, &bar0->rts_qos_steering);
1688 for (i = 0; i < 8; i++)
1689 writeq(val64, &bar0->rts_frm_len_n[i]);
1691 /* Set the default rts frame length for the rings configured */
1692 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1693 for (i = 0 ; i < config->rx_ring_num ; i++)
1694 writeq(val64, &bar0->rts_frm_len_n[i]);
1696 /* Set the frame length for the configured rings
1697 * desired by the user
1699 for (i = 0; i < config->rx_ring_num; i++) {
1700 /* If rts_frm_len[i] == 0 then it is assumed that user not
1701 * specified frame length steering.
1702 * If the user provides the frame length then program
1703 * the rts_frm_len register for those values or else
1704 * leave it as it is.
1706 if (rts_frm_len[i] != 0) {
1707 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1708 &bar0->rts_frm_len_n[i]);
1712 /* Disable differentiated services steering logic */
1713 for (i = 0; i < 64; i++) {
1714 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1715 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1717 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1722 /* Program statistics memory */
1723 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1725 if (nic->device_type == XFRAME_II_DEVICE) {
1726 val64 = STAT_BC(0x320);
1727 writeq(val64, &bar0->stat_byte_cnt);
1731 * Initializing the sampling rate for the device to calculate the
1732 * bandwidth utilization.
1734 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1735 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1736 writeq(val64, &bar0->mac_link_util);
1739 * Initializing the Transmit and Receive Traffic Interrupt
1743 /* Initialize TTI */
1744 if (SUCCESS != init_tti(nic, nic->last_link_state))
1747 /* RTI Initialization */
1748 if (nic->device_type == XFRAME_II_DEVICE) {
1750 * Programmed to generate Apprx 500 Intrs per
1753 int count = (nic->config.bus_speed * 125)/4;
1754 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1756 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1757 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1758 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1759 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1760 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1762 writeq(val64, &bar0->rti_data1_mem);
1764 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1765 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1766 if (nic->config.intr_type == MSI_X)
1767 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1768 RTI_DATA2_MEM_RX_UFC_D(0x40));
1770 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1771 RTI_DATA2_MEM_RX_UFC_D(0x80));
1772 writeq(val64, &bar0->rti_data2_mem);
1774 for (i = 0; i < config->rx_ring_num; i++) {
1775 val64 = RTI_CMD_MEM_WE |
1776 RTI_CMD_MEM_STROBE_NEW_CMD |
1777 RTI_CMD_MEM_OFFSET(i);
1778 writeq(val64, &bar0->rti_command_mem);
1781 * Once the operation completes, the Strobe bit of the
1782 * command register will be reset. We poll for this
1783 * particular condition. We wait for a maximum of 500ms
1784 * for the operation to complete, if it's not complete
1785 * by then we return error.
1789 val64 = readq(&bar0->rti_command_mem);
1790 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1794 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1804 * Initializing proper values as Pause threshold into all
1805 * the 8 Queues on Rx side.
1807 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1808 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1810 /* Disable RMAC PAD STRIPPING */
1811 add = &bar0->mac_cfg;
1812 val64 = readq(&bar0->mac_cfg);
1813 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1814 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1815 writel((u32) (val64), add);
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64 >> 32), (add + 4));
1818 val64 = readq(&bar0->mac_cfg);
1820 /* Enable FCS stripping by adapter */
1821 add = &bar0->mac_cfg;
1822 val64 = readq(&bar0->mac_cfg);
1823 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1824 if (nic->device_type == XFRAME_II_DEVICE)
1825 writeq(val64, &bar0->mac_cfg);
1827 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1828 writel((u32) (val64), add);
1829 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1830 writel((u32) (val64 >> 32), (add + 4));
1834 * Set the time value to be inserted in the pause frame
1835 * generated by xena.
1837 val64 = readq(&bar0->rmac_pause_cfg);
1838 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1839 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1840 writeq(val64, &bar0->rmac_pause_cfg);
1843 * Set the Threshold Limit for Generating the pause frame
1844 * If the amount of data in any Queue exceeds ratio of
1845 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1846 * pause frame is generated
1849 for (i = 0; i < 4; i++) {
1850 val64 |= (((u64)0xFF00 |
1851 nic->mac_control.mc_pause_threshold_q0q3)
1854 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1857 for (i = 0; i < 4; i++) {
1858 val64 |= (((u64)0xFF00 |
1859 nic->mac_control.mc_pause_threshold_q4q7)
1862 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1865 * TxDMA will stop Read request if the number of read split has
1866 * exceeded the limit pointed by shared_splits
1868 val64 = readq(&bar0->pic_control);
1869 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1870 writeq(val64, &bar0->pic_control);
1872 if (nic->config.bus_speed == 266) {
1873 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1874 writeq(0x0, &bar0->read_retry_delay);
1875 writeq(0x0, &bar0->write_retry_delay);
1879 * Programming the Herc to split every write transaction
1880 * that does not start on an ADB to reduce disconnects.
1882 if (nic->device_type == XFRAME_II_DEVICE) {
1883 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1884 MISC_LINK_STABILITY_PRD(3);
1885 writeq(val64, &bar0->misc_control);
1886 val64 = readq(&bar0->pic_control2);
1887 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1888 writeq(val64, &bar0->pic_control2);
1890 if (strstr(nic->product_name, "CX4")) {
1891 val64 = TMAC_AVG_IPG(0x17);
1892 writeq(val64, &bar0->tmac_avg_ipg);
1897 #define LINK_UP_DOWN_INTERRUPT 1
1898 #define MAC_RMAC_ERR_TIMER 2
1900 static int s2io_link_fault_indication(struct s2io_nic *nic)
1902 if (nic->device_type == XFRAME_II_DEVICE)
1903 return LINK_UP_DOWN_INTERRUPT;
1905 return MAC_RMAC_ERR_TIMER;
1909 * do_s2io_write_bits - update alarm bits in alarm register
1910 * @value: alarm bits
1911 * @flag: interrupt status
1912 * @addr: address value
1913 * Description: update alarm bits in alarm register
1917 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1921 temp64 = readq(addr);
1923 if (flag == ENABLE_INTRS)
1924 temp64 &= ~((u64)value);
1926 temp64 |= ((u64)value);
1927 writeq(temp64, addr);
1930 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1932 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1933 register u64 gen_int_mask = 0;
1936 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1937 if (mask & TX_DMA_INTR) {
1938 gen_int_mask |= TXDMA_INT_M;
1940 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1941 TXDMA_PCC_INT | TXDMA_TTI_INT |
1942 TXDMA_LSO_INT | TXDMA_TPA_INT |
1943 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1945 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1946 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1947 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1948 &bar0->pfc_err_mask);
1950 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1951 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1952 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1954 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1955 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1956 PCC_N_SERR | PCC_6_COF_OV_ERR |
1957 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1958 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1960 flag, &bar0->pcc_err_mask);
1962 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1963 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1965 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1966 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1967 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1968 flag, &bar0->lso_err_mask);
1970 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1971 flag, &bar0->tpa_err_mask);
1973 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1976 if (mask & TX_MAC_INTR) {
1977 gen_int_mask |= TXMAC_INT_M;
1978 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1979 &bar0->mac_int_mask);
1980 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1981 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1982 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1983 flag, &bar0->mac_tmac_err_mask);
1986 if (mask & TX_XGXS_INTR) {
1987 gen_int_mask |= TXXGXS_INT_M;
1988 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1989 &bar0->xgxs_int_mask);
1990 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1991 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1992 flag, &bar0->xgxs_txgxs_err_mask);
1995 if (mask & RX_DMA_INTR) {
1996 gen_int_mask |= RXDMA_INT_M;
1997 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1998 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1999 flag, &bar0->rxdma_int_mask);
2000 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2001 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2002 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2003 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2004 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2005 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2006 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2007 &bar0->prc_pcix_err_mask);
2008 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2009 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2010 &bar0->rpa_err_mask);
2011 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2012 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2013 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2014 RDA_FRM_ECC_SG_ERR |
2015 RDA_MISC_ERR|RDA_PCIX_ERR,
2016 flag, &bar0->rda_err_mask);
2017 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2018 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2019 flag, &bar0->rti_err_mask);
2022 if (mask & RX_MAC_INTR) {
2023 gen_int_mask |= RXMAC_INT_M;
2024 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2025 &bar0->mac_int_mask);
2026 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2027 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2028 RMAC_DOUBLE_ECC_ERR);
2029 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2030 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2031 do_s2io_write_bits(interruptible,
2032 flag, &bar0->mac_rmac_err_mask);
2035 if (mask & RX_XGXS_INTR) {
2036 gen_int_mask |= RXXGXS_INT_M;
2037 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2038 &bar0->xgxs_int_mask);
2039 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2040 &bar0->xgxs_rxgxs_err_mask);
2043 if (mask & MC_INTR) {
2044 gen_int_mask |= MC_INT_M;
2045 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2046 flag, &bar0->mc_int_mask);
2047 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2048 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2049 &bar0->mc_err_mask);
2051 nic->general_int_mask = gen_int_mask;
2053 /* Remove this line when alarm interrupts are enabled */
2054 nic->general_int_mask = 0;
2058 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2059 * @nic: device private variable,
2060 * @mask: A mask indicating which Intr block must be modified and,
2061 * @flag: A flag indicating whether to enable or disable the Intrs.
2062 * Description: This function will either disable or enable the interrupts
2063 * depending on the flag argument. The mask argument can be used to
2064 * enable/disable any Intr block.
2065 * Return Value: NONE.
2068 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2070 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2071 register u64 temp64 = 0, intr_mask = 0;
2073 intr_mask = nic->general_int_mask;
2075 /* Top level interrupt classification */
2076 /* PIC Interrupts */
2077 if (mask & TX_PIC_INTR) {
2078 /* Enable PIC Intrs in the general intr mask register */
2079 intr_mask |= TXPIC_INT_M;
2080 if (flag == ENABLE_INTRS) {
2082 * If Hercules adapter enable GPIO otherwise
2083 * disable all PCIX, Flash, MDIO, IIC and GPIO
2084 * interrupts for now.
2087 if (s2io_link_fault_indication(nic) ==
2088 LINK_UP_DOWN_INTERRUPT) {
2089 do_s2io_write_bits(PIC_INT_GPIO, flag,
2090 &bar0->pic_int_mask);
2091 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2092 &bar0->gpio_int_mask);
2094 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2095 } else if (flag == DISABLE_INTRS) {
2097 * Disable PIC Intrs in the general
2098 * intr mask register
2100 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2104 /* Tx traffic interrupts */
2105 if (mask & TX_TRAFFIC_INTR) {
2106 intr_mask |= TXTRAFFIC_INT_M;
2107 if (flag == ENABLE_INTRS) {
2109 * Enable all the Tx side interrupts
2110 * writing 0 Enables all 64 TX interrupt levels
2112 writeq(0x0, &bar0->tx_traffic_mask);
2113 } else if (flag == DISABLE_INTRS) {
2115 * Disable Tx Traffic Intrs in the general intr mask
2118 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2122 /* Rx traffic interrupts */
2123 if (mask & RX_TRAFFIC_INTR) {
2124 intr_mask |= RXTRAFFIC_INT_M;
2125 if (flag == ENABLE_INTRS) {
2126 /* writing 0 Enables all 8 RX interrupt levels */
2127 writeq(0x0, &bar0->rx_traffic_mask);
2128 } else if (flag == DISABLE_INTRS) {
2130 * Disable Rx Traffic Intrs in the general intr mask
2133 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2137 temp64 = readq(&bar0->general_int_mask);
2138 if (flag == ENABLE_INTRS)
2139 temp64 &= ~((u64)intr_mask);
2141 temp64 = DISABLE_ALL_INTRS;
2142 writeq(temp64, &bar0->general_int_mask);
2144 nic->general_int_mask = readq(&bar0->general_int_mask);
2148 * verify_pcc_quiescent- Checks for PCC quiescent state
2149 * Return: 1 If PCC is quiescence
2150 * 0 If PCC is not quiescence
2152 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2155 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2156 u64 val64 = readq(&bar0->adapter_status);
2158 herc = (sp->device_type == XFRAME_II_DEVICE);
2160 if (flag == false) {
2161 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2162 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2165 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2169 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2170 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2171 ADAPTER_STATUS_RMAC_PCC_IDLE))
2174 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2175 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2183 * verify_xena_quiescence - Checks whether the H/W is ready
2184 * Description: Returns whether the H/W is ready to go or not. Depending
2185 * on whether adapter enable bit was written or not the comparison
2186 * differs and the calling function passes the input argument flag to
2188 * Return: 1 If xena is quiescence
2189 * 0 If Xena is not quiescence
2192 static int verify_xena_quiescence(struct s2io_nic *sp)
2195 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2196 u64 val64 = readq(&bar0->adapter_status);
2197 mode = s2io_verify_pci_mode(sp);
2199 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2203 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2204 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2207 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2208 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2211 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2212 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2215 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2216 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2219 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2220 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2223 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2224 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2227 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2228 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2233 * In PCI 33 mode, the P_PLL is not used, and therefore,
2234 * the the P_PLL_LOCK bit in the adapter_status register will
2237 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2238 sp->device_type == XFRAME_II_DEVICE &&
2239 mode != PCI_MODE_PCI_33) {
2240 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2243 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2244 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2245 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2252 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2253 * @sp: Pointer to device specifc structure
2255 * New procedure to clear mac address reading problems on Alpha platforms
2259 static void fix_mac_address(struct s2io_nic *sp)
2261 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2265 while (fix_mac[i] != END_SIGN) {
2266 writeq(fix_mac[i++], &bar0->gpio_control);
2268 val64 = readq(&bar0->gpio_control);
2273 * start_nic - Turns the device on
2274 * @nic : device private variable.
2276 * This function actually turns the device on. Before this function is
2277 * called,all Registers are configured from their reset states
2278 * and shared memory is allocated but the NIC is still quiescent. On
2279 * calling this function, the device interrupts are cleared and the NIC is
2280 * literally switched on by writing into the adapter control register.
2282 * SUCCESS on success and -1 on failure.
2285 static int start_nic(struct s2io_nic *nic)
2287 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2288 struct net_device *dev = nic->dev;
2289 register u64 val64 = 0;
2291 struct mac_info *mac_control;
2292 struct config_param *config;
2294 mac_control = &nic->mac_control;
2295 config = &nic->config;
2297 /* PRC Initialization and configuration */
2298 for (i = 0; i < config->rx_ring_num; i++) {
2299 struct ring_info *ring = &mac_control->rings[i];
2301 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2302 &bar0->prc_rxd0_n[i]);
2304 val64 = readq(&bar0->prc_ctrl_n[i]);
2305 if (nic->rxd_mode == RXD_MODE_1)
2306 val64 |= PRC_CTRL_RC_ENABLED;
2308 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2309 if (nic->device_type == XFRAME_II_DEVICE)
2310 val64 |= PRC_CTRL_GROUP_READS;
2311 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2312 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2313 writeq(val64, &bar0->prc_ctrl_n[i]);
2316 if (nic->rxd_mode == RXD_MODE_3B) {
2317 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2318 val64 = readq(&bar0->rx_pa_cfg);
2319 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2320 writeq(val64, &bar0->rx_pa_cfg);
2323 if (vlan_tag_strip == 0) {
2324 val64 = readq(&bar0->rx_pa_cfg);
2325 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2326 writeq(val64, &bar0->rx_pa_cfg);
2327 nic->vlan_strip_flag = 0;
2331 * Enabling MC-RLDRAM. After enabling the device, we timeout
2332 * for around 100ms, which is approximately the time required
2333 * for the device to be ready for operation.
2335 val64 = readq(&bar0->mc_rldram_mrs);
2336 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2337 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2338 val64 = readq(&bar0->mc_rldram_mrs);
2340 msleep(100); /* Delay by around 100 ms. */
2342 /* Enabling ECC Protection. */
2343 val64 = readq(&bar0->adapter_control);
2344 val64 &= ~ADAPTER_ECC_EN;
2345 writeq(val64, &bar0->adapter_control);
2348 * Verify if the device is ready to be enabled, if so enable
2351 val64 = readq(&bar0->adapter_status);
2352 if (!verify_xena_quiescence(nic)) {
2353 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2354 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2355 (unsigned long long)val64);
2360 * With some switches, link might be already up at this point.
2361 * Because of this weird behavior, when we enable laser,
2362 * we may not get link. We need to handle this. We cannot
2363 * figure out which switch is misbehaving. So we are forced to
2364 * make a global change.
2367 /* Enabling Laser. */
2368 val64 = readq(&bar0->adapter_control);
2369 val64 |= ADAPTER_EOI_TX_ON;
2370 writeq(val64, &bar0->adapter_control);
2372 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2374 * Dont see link state interrupts initally on some switches,
2375 * so directly scheduling the link state task here.
2377 schedule_work(&nic->set_link_task);
2379 /* SXE-002: Initialize link and activity LED */
2380 subid = nic->pdev->subsystem_device;
2381 if (((subid & 0xFF) >= 0x07) &&
2382 (nic->device_type == XFRAME_I_DEVICE)) {
2383 val64 = readq(&bar0->gpio_control);
2384 val64 |= 0x0000800000000000ULL;
2385 writeq(val64, &bar0->gpio_control);
2386 val64 = 0x0411040400000000ULL;
2387 writeq(val64, (void __iomem *)bar0 + 0x2700);
2393 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2395 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2396 struct TxD *txdlp, int get_off)
2398 struct s2io_nic *nic = fifo_data->nic;
2399 struct sk_buff *skb;
2404 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2405 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2406 sizeof(u64), PCI_DMA_TODEVICE);
2410 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2412 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2415 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2416 skb->len - skb->data_len, PCI_DMA_TODEVICE);
2417 frg_cnt = skb_shinfo(skb)->nr_frags;
2420 for (j = 0; j < frg_cnt; j++, txds++) {
2421 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2422 if (!txds->Buffer_Pointer)
2424 pci_unmap_page(nic->pdev,
2425 (dma_addr_t)txds->Buffer_Pointer,
2426 frag->size, PCI_DMA_TODEVICE);
2429 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2434 * free_tx_buffers - Free all queued Tx buffers
2435 * @nic : device private variable.
2437 * Free all queued Tx buffers.
2438 * Return Value: void
2441 static void free_tx_buffers(struct s2io_nic *nic)
2443 struct net_device *dev = nic->dev;
2444 struct sk_buff *skb;
2447 struct mac_info *mac_control;
2448 struct config_param *config;
2451 mac_control = &nic->mac_control;
2452 config = &nic->config;
2454 for (i = 0; i < config->tx_fifo_num; i++) {
2455 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2456 struct fifo_info *fifo = &mac_control->fifos[i];
2457 unsigned long flags;
2459 spin_lock_irqsave(&fifo->tx_lock, flags);
2460 for (j = 0; j < tx_cfg->fifo_len; j++) {
2461 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2462 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2464 nic->mac_control.stats_info->sw_stat.mem_freed
2471 "%s:forcibly freeing %d skbs on FIFO%d\n",
2473 fifo->tx_curr_get_info.offset = 0;
2474 fifo->tx_curr_put_info.offset = 0;
2475 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2480 * stop_nic - To stop the nic
2481 * @nic ; device private variable.
2483 * This function does exactly the opposite of what the start_nic()
2484 * function does. This function is called to stop the device.
2489 static void stop_nic(struct s2io_nic *nic)
2491 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2492 register u64 val64 = 0;
2494 struct mac_info *mac_control;
2495 struct config_param *config;
2497 mac_control = &nic->mac_control;
2498 config = &nic->config;
2500 /* Disable all interrupts */
2501 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2502 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2503 interruptible |= TX_PIC_INTR;
2504 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2506 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2507 val64 = readq(&bar0->adapter_control);
2508 val64 &= ~(ADAPTER_CNTL_EN);
2509 writeq(val64, &bar0->adapter_control);
2513 * fill_rx_buffers - Allocates the Rx side skbs
2514 * @ring_info: per ring structure
2515 * @from_card_up: If this is true, we will map the buffer to get
2516 * the dma address for buf0 and buf1 to give it to the card.
2517 * Else we will sync the already mapped buffer to give it to the card.
2519 * The function allocates Rx side skbs and puts the physical
2520 * address of these buffers into the RxD buffer pointers, so that the NIC
2521 * can DMA the received frame into these locations.
2522 * The NIC supports 3 receive modes, viz
2524 * 2. three buffer and
2525 * 3. Five buffer modes.
2526 * Each mode defines how many fragments the received frame will be split
2527 * up into by the NIC. The frame is split into L3 header, L4 Header,
2528 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2529 * is split into 3 fragments. As of now only single buffer mode is
2532 * SUCCESS on success or an appropriate -ve value on failure.
2534 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2537 struct sk_buff *skb;
2539 int off, size, block_no, block_no1;
2544 struct RxD_t *first_rxdp = NULL;
2545 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2549 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
2551 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2553 block_no1 = ring->rx_curr_get_info.block_index;
2554 while (alloc_tab < alloc_cnt) {
2555 block_no = ring->rx_curr_put_info.block_index;
2557 off = ring->rx_curr_put_info.offset;
2559 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2561 rxd_index = off + 1;
2563 rxd_index += (block_no * ring->rxd_count);
2565 if ((block_no == block_no1) &&
2566 (off == ring->rx_curr_get_info.offset) &&
2567 (rxdp->Host_Control)) {
2568 DBG_PRINT(INTR_DBG, "%s: Get and Put", ring->dev->name);
2569 DBG_PRINT(INTR_DBG, " info equated\n");
2572 if (off && (off == ring->rxd_count)) {
2573 ring->rx_curr_put_info.block_index++;
2574 if (ring->rx_curr_put_info.block_index ==
2576 ring->rx_curr_put_info.block_index = 0;
2577 block_no = ring->rx_curr_put_info.block_index;
2579 ring->rx_curr_put_info.offset = off;
2580 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2581 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2582 ring->dev->name, rxdp);
2586 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2587 ((ring->rxd_mode == RXD_MODE_3B) &&
2588 (rxdp->Control_2 & s2BIT(0)))) {
2589 ring->rx_curr_put_info.offset = off;
2592 /* calculate size of skb based on ring mode */
2594 HEADER_ETHERNET_II_802_3_SIZE +
2595 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2596 if (ring->rxd_mode == RXD_MODE_1)
2597 size += NET_IP_ALIGN;
2599 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2602 skb = dev_alloc_skb(size);
2604 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2605 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2608 first_rxdp->Control_1 |= RXD_OWN_XENA;
2610 stats->mem_alloc_fail_cnt++;
2614 stats->mem_allocated += skb->truesize;
2616 if (ring->rxd_mode == RXD_MODE_1) {
2617 /* 1 buffer mode - normal operation mode */
2618 rxdp1 = (struct RxD1 *)rxdp;
2619 memset(rxdp, 0, sizeof(struct RxD1));
2620 skb_reserve(skb, NET_IP_ALIGN);
2621 rxdp1->Buffer0_ptr =
2622 pci_map_single(ring->pdev, skb->data,
2623 size - NET_IP_ALIGN,
2624 PCI_DMA_FROMDEVICE);
2625 if (pci_dma_mapping_error(nic->pdev,
2626 rxdp1->Buffer0_ptr))
2627 goto pci_map_failed;
2630 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2631 rxdp->Host_Control = (unsigned long)skb;
2632 } else if (ring->rxd_mode == RXD_MODE_3B) {
2635 * 2 buffer mode provides 128
2636 * byte aligned receive buffers.
2639 rxdp3 = (struct RxD3 *)rxdp;
2640 /* save buffer pointers to avoid frequent dma mapping */
2641 Buffer0_ptr = rxdp3->Buffer0_ptr;
2642 Buffer1_ptr = rxdp3->Buffer1_ptr;
2643 memset(rxdp, 0, sizeof(struct RxD3));
2644 /* restore the buffer pointers for dma sync*/
2645 rxdp3->Buffer0_ptr = Buffer0_ptr;
2646 rxdp3->Buffer1_ptr = Buffer1_ptr;
2648 ba = &ring->ba[block_no][off];
2649 skb_reserve(skb, BUF0_LEN);
2650 tmp = (u64)(unsigned long)skb->data;
2653 skb->data = (void *) (unsigned long)tmp;
2654 skb_reset_tail_pointer(skb);
2657 rxdp3->Buffer0_ptr =
2658 pci_map_single(ring->pdev, ba->ba_0,
2660 PCI_DMA_FROMDEVICE);
2661 if (pci_dma_mapping_error(nic->pdev,
2662 rxdp3->Buffer0_ptr))
2663 goto pci_map_failed;
2665 pci_dma_sync_single_for_device(ring->pdev,
2666 (dma_addr_t)rxdp3->Buffer0_ptr,
2668 PCI_DMA_FROMDEVICE);
2670 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2671 if (ring->rxd_mode == RXD_MODE_3B) {
2672 /* Two buffer mode */
2675 * Buffer2 will have L3/L4 header plus
2678 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2681 PCI_DMA_FROMDEVICE);
2683 if (pci_dma_mapping_error(nic->pdev,
2684 rxdp3->Buffer2_ptr))
2685 goto pci_map_failed;
2688 rxdp3->Buffer1_ptr =
2689 pci_map_single(ring->pdev,
2692 PCI_DMA_FROMDEVICE);
2694 if (pci_dma_mapping_error(nic->pdev,
2695 rxdp3->Buffer1_ptr)) {
2696 pci_unmap_single(ring->pdev,
2697 (dma_addr_t)(unsigned long)
2700 PCI_DMA_FROMDEVICE);
2701 goto pci_map_failed;
2704 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2705 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2708 rxdp->Control_2 |= s2BIT(0);
2709 rxdp->Host_Control = (unsigned long) (skb);
2711 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2712 rxdp->Control_1 |= RXD_OWN_XENA;
2714 if (off == (ring->rxd_count + 1))
2716 ring->rx_curr_put_info.offset = off;
2718 rxdp->Control_2 |= SET_RXD_MARKER;
2719 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2722 first_rxdp->Control_1 |= RXD_OWN_XENA;
2726 ring->rx_bufs_left += 1;
2731 /* Transfer ownership of first descriptor to adapter just before
2732 * exiting. Before that, use memory barrier so that ownership
2733 * and other fields are seen by adapter correctly.
2737 first_rxdp->Control_1 |= RXD_OWN_XENA;
2743 stats->pci_map_fail_cnt++;
2744 stats->mem_freed += skb->truesize;
2745 dev_kfree_skb_irq(skb);
2749 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2751 struct net_device *dev = sp->dev;
2753 struct sk_buff *skb;
2755 struct mac_info *mac_control;
2760 mac_control = &sp->mac_control;
2761 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2762 rxdp = mac_control->rings[ring_no].
2763 rx_blocks[blk].rxds[j].virt_addr;
2764 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2767 if (sp->rxd_mode == RXD_MODE_1) {
2768 rxdp1 = (struct RxD1 *)rxdp;
2769 pci_unmap_single(sp->pdev,
2770 (dma_addr_t)rxdp1->Buffer0_ptr,
2772 HEADER_ETHERNET_II_802_3_SIZE +
2773 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2774 PCI_DMA_FROMDEVICE);
2775 memset(rxdp, 0, sizeof(struct RxD1));
2776 } else if (sp->rxd_mode == RXD_MODE_3B) {
2777 rxdp3 = (struct RxD3 *)rxdp;
2778 ba = &mac_control->rings[ring_no].ba[blk][j];
2779 pci_unmap_single(sp->pdev,
2780 (dma_addr_t)rxdp3->Buffer0_ptr,
2782 PCI_DMA_FROMDEVICE);
2783 pci_unmap_single(sp->pdev,
2784 (dma_addr_t)rxdp3->Buffer1_ptr,
2786 PCI_DMA_FROMDEVICE);
2787 pci_unmap_single(sp->pdev,
2788 (dma_addr_t)rxdp3->Buffer2_ptr,
2790 PCI_DMA_FROMDEVICE);
2791 memset(rxdp, 0, sizeof(struct RxD3));
2793 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2795 mac_control->rings[ring_no].rx_bufs_left -= 1;
2800 * free_rx_buffers - Frees all Rx buffers
2801 * @sp: device private variable.
2803 * This function will free all Rx buffers allocated by host.
2808 static void free_rx_buffers(struct s2io_nic *sp)
2810 struct net_device *dev = sp->dev;
2811 int i, blk = 0, buf_cnt = 0;
2812 struct mac_info *mac_control;
2813 struct config_param *config;
2815 mac_control = &sp->mac_control;
2816 config = &sp->config;
2818 for (i = 0; i < config->rx_ring_num; i++) {
2819 struct ring_info *ring = &mac_control->rings[i];
2821 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2822 free_rxd_blk(sp, i, blk);
2824 ring->rx_curr_put_info.block_index = 0;
2825 ring->rx_curr_get_info.block_index = 0;
2826 ring->rx_curr_put_info.offset = 0;
2827 ring->rx_curr_get_info.offset = 0;
2828 ring->rx_bufs_left = 0;
2829 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2830 dev->name, buf_cnt, i);
2834 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2836 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2837 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2838 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2844 * s2io_poll - Rx interrupt handler for NAPI support
2845 * @napi : pointer to the napi structure.
2846 * @budget : The number of packets that were budgeted to be processed
2847 * during one pass through the 'Poll" function.
2849 * Comes into picture only if NAPI support has been incorporated. It does
2850 * the same thing that rx_intr_handler does, but not in a interrupt context
2851 * also It will process only a given number of packets.
2853 * 0 on success and 1 if there are No Rx packets to be processed.
2856 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2858 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2859 struct net_device *dev = ring->dev;
2860 struct config_param *config;
2861 struct mac_info *mac_control;
2862 int pkts_processed = 0;
2863 u8 __iomem *addr = NULL;
2865 struct s2io_nic *nic = netdev_priv(dev);
2866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2867 int budget_org = budget;
2869 config = &nic->config;
2870 mac_control = &nic->mac_control;
2872 if (unlikely(!is_s2io_card_up(nic)))
2875 pkts_processed = rx_intr_handler(ring, budget);
2876 s2io_chk_rx_buffers(nic, ring);
2878 if (pkts_processed < budget_org) {
2879 napi_complete(napi);
2880 /*Re Enable MSI-Rx Vector*/
2881 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2882 addr += 7 - ring->ring_no;
2883 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2887 return pkts_processed;
2890 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2892 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2893 struct config_param *config;
2894 struct mac_info *mac_control;
2895 int pkts_processed = 0;
2896 int ring_pkts_processed, i;
2897 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2898 int budget_org = budget;
2900 config = &nic->config;
2901 mac_control = &nic->mac_control;
2903 if (unlikely(!is_s2io_card_up(nic)))
2906 for (i = 0; i < config->rx_ring_num; i++) {
2907 struct ring_info *ring = &mac_control->rings[i];
2908 ring_pkts_processed = rx_intr_handler(ring, budget);
2909 s2io_chk_rx_buffers(nic, ring);
2910 pkts_processed += ring_pkts_processed;
2911 budget -= ring_pkts_processed;
2915 if (pkts_processed < budget_org) {
2916 napi_complete(napi);
2917 /* Re enable the Rx interrupts for the ring */
2918 writeq(0, &bar0->rx_traffic_mask);
2919 readl(&bar0->rx_traffic_mask);
2921 return pkts_processed;
2924 #ifdef CONFIG_NET_POLL_CONTROLLER
2926 * s2io_netpoll - netpoll event handler entry point
2927 * @dev : pointer to the device structure.
2929 * This function will be called by upper layer to check for events on the
2930 * interface in situations where interrupts are disabled. It is used for
2931 * specific in-kernel networking tasks, such as remote consoles and kernel
2932 * debugging over the network (example netdump in RedHat).
2934 static void s2io_netpoll(struct net_device *dev)
2936 struct s2io_nic *nic = netdev_priv(dev);
2937 struct mac_info *mac_control;
2938 struct config_param *config;
2939 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2940 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2943 if (pci_channel_offline(nic->pdev))
2946 disable_irq(dev->irq);
2948 mac_control = &nic->mac_control;
2949 config = &nic->config;
2951 writeq(val64, &bar0->rx_traffic_int);
2952 writeq(val64, &bar0->tx_traffic_int);
2954 /* we need to free up the transmitted skbufs or else netpoll will
2955 * run out of skbs and will fail and eventually netpoll application such
2956 * as netdump will fail.
2958 for (i = 0; i < config->tx_fifo_num; i++)
2959 tx_intr_handler(&mac_control->fifos[i]);
2961 /* check for received packet and indicate up to network */
2962 for (i = 0; i < config->rx_ring_num; i++) {
2963 struct ring_info *ring = &mac_control->rings[i];
2965 rx_intr_handler(ring, 0);
2968 for (i = 0; i < config->rx_ring_num; i++) {
2969 struct ring_info *ring = &mac_control->rings[i];
2971 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2972 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2973 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2977 enable_irq(dev->irq);
2983 * rx_intr_handler - Rx interrupt handler
2984 * @ring_info: per ring structure.
2985 * @budget: budget for napi processing.
2987 * If the interrupt is because of a received frame or if the
2988 * receive ring contains fresh as yet un-processed frames,this function is
2989 * called. It picks out the RxD at which place the last Rx processing had
2990 * stopped and sends the skb to the OSM's Rx handler and then increments
2993 * No. of napi packets processed.
2995 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2997 int get_block, put_block;
2998 struct rx_curr_get_info get_info, put_info;
3000 struct sk_buff *skb;
3001 int pkt_cnt = 0, napi_pkts = 0;
3006 get_info = ring_data->rx_curr_get_info;
3007 get_block = get_info.block_index;
3008 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
3009 put_block = put_info.block_index;
3010 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
3012 while (RXD_IS_UP2DT(rxdp)) {
3014 * If your are next to put index then it's
3015 * FIFO full condition
3017 if ((get_block == put_block) &&
3018 (get_info.offset + 1) == put_info.offset) {
3019 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
3020 ring_data->dev->name);
3023 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
3025 DBG_PRINT(ERR_DBG, "%s: The skb is ",
3026 ring_data->dev->name);
3027 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
3030 if (ring_data->rxd_mode == RXD_MODE_1) {
3031 rxdp1 = (struct RxD1 *)rxdp;
3032 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3035 HEADER_ETHERNET_II_802_3_SIZE +
3038 PCI_DMA_FROMDEVICE);
3039 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3040 rxdp3 = (struct RxD3 *)rxdp;
3041 pci_dma_sync_single_for_cpu(ring_data->pdev,
3042 (dma_addr_t)rxdp3->Buffer0_ptr,
3044 PCI_DMA_FROMDEVICE);
3045 pci_unmap_single(ring_data->pdev,
3046 (dma_addr_t)rxdp3->Buffer2_ptr,
3048 PCI_DMA_FROMDEVICE);
3050 prefetch(skb->data);
3051 rx_osm_handler(ring_data, rxdp);
3053 ring_data->rx_curr_get_info.offset = get_info.offset;
3054 rxdp = ring_data->rx_blocks[get_block].
3055 rxds[get_info.offset].virt_addr;
3056 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3057 get_info.offset = 0;
3058 ring_data->rx_curr_get_info.offset = get_info.offset;
3060 if (get_block == ring_data->block_count)
3062 ring_data->rx_curr_get_info.block_index = get_block;
3063 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3066 if (ring_data->nic->config.napi) {
3073 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3076 if (ring_data->lro) {
3077 /* Clear all LRO sessions before exiting */
3078 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3079 struct lro *lro = &ring_data->lro0_n[i];
3081 update_L3L4_header(ring_data->nic, lro);
3082 queue_rx_frame(lro->parent, lro->vlan_tag);
3083 clear_lro_session(lro);
3091 * tx_intr_handler - Transmit interrupt handler
3092 * @nic : device private variable
3094 * If an interrupt was raised to indicate DMA complete of the
3095 * Tx packet, this function is called. It identifies the last TxD
3096 * whose buffer was freed and frees all skbs whose data have already
3097 * DMA'ed into the NICs internal memory.
3102 static void tx_intr_handler(struct fifo_info *fifo_data)
3104 struct s2io_nic *nic = fifo_data->nic;
3105 struct tx_curr_get_info get_info, put_info;
3106 struct sk_buff *skb = NULL;
3109 unsigned long flags = 0;
3112 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3115 get_info = fifo_data->tx_curr_get_info;
3116 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3117 txdlp = (struct TxD *)
3118 fifo_data->list_info[get_info.offset].list_virt_addr;
3119 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3120 (get_info.offset != put_info.offset) &&
3121 (txdlp->Host_Control)) {
3122 /* Check for TxD errors */
3123 if (txdlp->Control_1 & TXD_T_CODE) {
3124 unsigned long long err;
3125 err = txdlp->Control_1 & TXD_T_CODE;
3127 nic->mac_control.stats_info->sw_stat.
3131 /* update t_code statistics */
3132 err_mask = err >> 48;
3135 nic->mac_control.stats_info->sw_stat.
3140 nic->mac_control.stats_info->sw_stat.
3141 tx_desc_abort_cnt++;
3145 nic->mac_control.stats_info->sw_stat.
3146 tx_parity_err_cnt++;
3150 nic->mac_control.stats_info->sw_stat.
3155 nic->mac_control.stats_info->sw_stat.
3156 tx_list_proc_err_cnt++;
3161 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3163 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3164 DBG_PRINT(ERR_DBG, "%s: Null skb ", __func__);
3165 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3170 /* Updating the statistics block */
3171 nic->dev->stats.tx_bytes += skb->len;
3172 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3173 dev_kfree_skb_irq(skb);
3176 if (get_info.offset == get_info.fifo_len + 1)
3177 get_info.offset = 0;
3178 txdlp = (struct TxD *)
3179 fifo_data->list_info[get_info.offset].list_virt_addr;
3180 fifo_data->tx_curr_get_info.offset = get_info.offset;
3183 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3185 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3189 * s2io_mdio_write - Function to write in to MDIO registers
3190 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3191 * @addr : address value
3192 * @value : data value
3193 * @dev : pointer to net_device structure
3195 * This function is used to write values to the MDIO registers
3198 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3199 struct net_device *dev)
3202 struct s2io_nic *sp = netdev_priv(dev);
3203 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3205 /* address transaction */
3206 val64 = MDIO_MMD_INDX_ADDR(addr) |
3207 MDIO_MMD_DEV_ADDR(mmd_type) |
3208 MDIO_MMS_PRT_ADDR(0x0);
3209 writeq(val64, &bar0->mdio_control);
3210 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3211 writeq(val64, &bar0->mdio_control);
3214 /* Data transaction */
3215 val64 = MDIO_MMD_INDX_ADDR(addr) |
3216 MDIO_MMD_DEV_ADDR(mmd_type) |
3217 MDIO_MMS_PRT_ADDR(0x0) |
3218 MDIO_MDIO_DATA(value) |
3219 MDIO_OP(MDIO_OP_WRITE_TRANS);
3220 writeq(val64, &bar0->mdio_control);
3221 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3222 writeq(val64, &bar0->mdio_control);
3225 val64 = MDIO_MMD_INDX_ADDR(addr) |
3226 MDIO_MMD_DEV_ADDR(mmd_type) |
3227 MDIO_MMS_PRT_ADDR(0x0) |
3228 MDIO_OP(MDIO_OP_READ_TRANS);
3229 writeq(val64, &bar0->mdio_control);
3230 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3231 writeq(val64, &bar0->mdio_control);
3236 * s2io_mdio_read - Function to write in to MDIO registers
3237 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3238 * @addr : address value
3239 * @dev : pointer to net_device structure
3241 * This function is used to read values to the MDIO registers
3244 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3248 struct s2io_nic *sp = netdev_priv(dev);
3249 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3251 /* address transaction */
3252 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3253 | MDIO_MMD_DEV_ADDR(mmd_type)
3254 | MDIO_MMS_PRT_ADDR(0x0));
3255 writeq(val64, &bar0->mdio_control);
3256 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3257 writeq(val64, &bar0->mdio_control);
3260 /* Data transaction */
3261 val64 = MDIO_MMD_INDX_ADDR(addr) |
3262 MDIO_MMD_DEV_ADDR(mmd_type) |
3263 MDIO_MMS_PRT_ADDR(0x0) |
3264 MDIO_OP(MDIO_OP_READ_TRANS);
3265 writeq(val64, &bar0->mdio_control);
3266 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3267 writeq(val64, &bar0->mdio_control);
3270 /* Read the value from regs */
3271 rval64 = readq(&bar0->mdio_control);
3272 rval64 = rval64 & 0xFFFF0000;
3273 rval64 = rval64 >> 16;
3278 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3279 * @counter : couter value to be updated
3280 * @flag : flag to indicate the status
3281 * @type : counter type
3283 * This function is to check the status of the xpak counters value
3287 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3293 for (i = 0; i < index; i++)
3297 *counter = *counter + 1;
3298 val64 = *regs_stat & mask;
3299 val64 = val64 >> (index * 0x2);
3304 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3305 "service. Excessive temperatures may "
3306 "result in premature transceiver "
3310 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3311 "service Excessive bias currents may "
3312 "indicate imminent laser diode "
3316 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3317 "service Excessive laser output "
3318 "power may saturate far-end "
3323 "Incorrect XPAK Alarm type\n");
3327 val64 = val64 << (index * 0x2);
3328 *regs_stat = (*regs_stat & (~mask)) | (val64);
3331 *regs_stat = *regs_stat & (~mask);
3336 * s2io_updt_xpak_counter - Function to update the xpak counters
3337 * @dev : pointer to net_device struct
3339 * This function is to upate the status of the xpak counters value
3342 static void s2io_updt_xpak_counter(struct net_device *dev)
3350 struct s2io_nic *sp = netdev_priv(dev);
3351 struct stat_block *stat_info = sp->mac_control.stats_info;
3353 /* Check the communication with the MDIO slave */
3356 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3357 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3358 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3359 "Returned %llx\n", (unsigned long long)val64);
3363 /* Check for the expected value of control reg 1 */
3364 if (val64 != MDIO_CTRL1_SPEED10G) {
3365 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3366 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3367 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3371 /* Loading the DOM register to MDIO register */
3373 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3374 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3376 /* Reading the Alarm flags */
3379 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3381 flag = CHECKBIT(val64, 0x7);
3383 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3384 &stat_info->xpak_stat.xpak_regs_stat,
3387 if (CHECKBIT(val64, 0x6))
3388 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3390 flag = CHECKBIT(val64, 0x3);
3392 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3393 &stat_info->xpak_stat.xpak_regs_stat,
3396 if (CHECKBIT(val64, 0x2))
3397 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3399 flag = CHECKBIT(val64, 0x1);
3401 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3402 &stat_info->xpak_stat.xpak_regs_stat,
3405 if (CHECKBIT(val64, 0x0))
3406 stat_info->xpak_stat.alarm_laser_output_power_low++;
3408 /* Reading the Warning flags */
3411 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3413 if (CHECKBIT(val64, 0x7))
3414 stat_info->xpak_stat.warn_transceiver_temp_high++;
3416 if (CHECKBIT(val64, 0x6))
3417 stat_info->xpak_stat.warn_transceiver_temp_low++;
3419 if (CHECKBIT(val64, 0x3))
3420 stat_info->xpak_stat.warn_laser_bias_current_high++;
3422 if (CHECKBIT(val64, 0x2))
3423 stat_info->xpak_stat.warn_laser_bias_current_low++;
3425 if (CHECKBIT(val64, 0x1))
3426 stat_info->xpak_stat.warn_laser_output_power_high++;
3428 if (CHECKBIT(val64, 0x0))
3429 stat_info->xpak_stat.warn_laser_output_power_low++;
3433 * wait_for_cmd_complete - waits for a command to complete.
3434 * @sp : private member of the device structure, which is a pointer to the
3435 * s2io_nic structure.
3436 * Description: Function that waits for a command to Write into RMAC
3437 * ADDR DATA registers to be completed and returns either success or
3438 * error depending on whether the command was complete or not.
3440 * SUCCESS on success and FAILURE on failure.
3443 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3446 int ret = FAILURE, cnt = 0, delay = 1;
3449 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3453 val64 = readq(addr);
3454 if (bit_state == S2IO_BIT_RESET) {
3455 if (!(val64 & busy_bit)) {
3460 if (!(val64 & busy_bit)) {
3477 * check_pci_device_id - Checks if the device id is supported
3479 * Description: Function to check if the pci device id is supported by driver.
3480 * Return value: Actual device id if supported else PCI_ANY_ID
3482 static u16 check_pci_device_id(u16 id)
3485 case PCI_DEVICE_ID_HERC_WIN:
3486 case PCI_DEVICE_ID_HERC_UNI:
3487 return XFRAME_II_DEVICE;
3488 case PCI_DEVICE_ID_S2IO_UNI:
3489 case PCI_DEVICE_ID_S2IO_WIN:
3490 return XFRAME_I_DEVICE;
3497 * s2io_reset - Resets the card.
3498 * @sp : private member of the device structure.
3499 * Description: Function to Reset the card. This function then also
3500 * restores the previously saved PCI configuration space registers as
3501 * the card reset also resets the configuration space.
3506 static void s2io_reset(struct s2io_nic *sp)
3508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3513 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3514 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3516 DBG_PRINT(INIT_DBG, "%s - Resetting XFrame card %s\n",
3517 __func__, sp->dev->name);
3519 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3520 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3522 val64 = SW_RESET_ALL;
3523 writeq(val64, &bar0->sw_reset);
3524 if (strstr(sp->product_name, "CX4"))
3527 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3529 /* Restore the PCI state saved during initialization. */
3530 pci_restore_state(sp->pdev);
3531 pci_read_config_word(sp->pdev, 0x2, &val16);
3532 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3537 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3538 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3540 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3544 /* Set swapper to enable I/O register access */
3545 s2io_set_swapper(sp);
3547 /* restore mac_addr entries */
3548 do_s2io_restore_unicast_mc(sp);
3550 /* Restore the MSIX table entries from local variables */
3551 restore_xmsi_data(sp);
3553 /* Clear certain PCI/PCI-X fields after reset */
3554 if (sp->device_type == XFRAME_II_DEVICE) {
3555 /* Clear "detected parity error" bit */
3556 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3558 /* Clearing PCIX Ecc status register */
3559 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3561 /* Clearing PCI_STATUS error reflected here */
3562 writeq(s2BIT(62), &bar0->txpic_int_reg);
3565 /* Reset device statistics maintained by OS */
3566 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3568 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3569 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3570 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3571 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3572 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3573 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3574 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3575 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3576 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3577 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3578 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3579 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3580 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3581 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3582 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3583 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3584 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3585 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3586 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3588 /* SXE-002: Configure link and activity LED to turn it off */
3589 subid = sp->pdev->subsystem_device;
3590 if (((subid & 0xFF) >= 0x07) &&
3591 (sp->device_type == XFRAME_I_DEVICE)) {
3592 val64 = readq(&bar0->gpio_control);
3593 val64 |= 0x0000800000000000ULL;
3594 writeq(val64, &bar0->gpio_control);
3595 val64 = 0x0411040400000000ULL;
3596 writeq(val64, (void __iomem *)bar0 + 0x2700);
3600 * Clear spurious ECC interrupts that would have occured on
3601 * XFRAME II cards after reset.
3603 if (sp->device_type == XFRAME_II_DEVICE) {
3604 val64 = readq(&bar0->pcc_err_reg);
3605 writeq(val64, &bar0->pcc_err_reg);
3608 sp->device_enabled_once = false;
3612 * s2io_set_swapper - to set the swapper controle on the card
3613 * @sp : private member of the device structure,
3614 * pointer to the s2io_nic structure.
3615 * Description: Function to set the swapper control on the card
3616 * correctly depending on the 'endianness' of the system.
3618 * SUCCESS on success and FAILURE on failure.
3621 static int s2io_set_swapper(struct s2io_nic *sp)
3623 struct net_device *dev = sp->dev;
3624 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3625 u64 val64, valt, valr;
3628 * Set proper endian settings and verify the same by reading
3629 * the PIF Feed-back register.
3632 val64 = readq(&bar0->pif_rd_swapper_fb);
3633 if (val64 != 0x0123456789ABCDEFULL) {
3635 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3636 0x8100008181000081ULL, /* FE=1, SE=0 */
3637 0x4200004242000042ULL, /* FE=0, SE=1 */
3638 0}; /* FE=0, SE=0 */
3641 writeq(value[i], &bar0->swapper_ctrl);
3642 val64 = readq(&bar0->pif_rd_swapper_fb);
3643 if (val64 == 0x0123456789ABCDEFULL)
3648 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3650 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3651 (unsigned long long)val64);
3656 valr = readq(&bar0->swapper_ctrl);
3659 valt = 0x0123456789ABCDEFULL;
3660 writeq(valt, &bar0->xmsi_address);
3661 val64 = readq(&bar0->xmsi_address);
3663 if (val64 != valt) {
3665 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3666 0x0081810000818100ULL, /* FE=1, SE=0 */
3667 0x0042420000424200ULL, /* FE=0, SE=1 */
3668 0}; /* FE=0, SE=0 */
3671 writeq((value[i] | valr), &bar0->swapper_ctrl);
3672 writeq(valt, &bar0->xmsi_address);
3673 val64 = readq(&bar0->xmsi_address);
3679 unsigned long long x = val64;
3680 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3681 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3685 val64 = readq(&bar0->swapper_ctrl);
3686 val64 &= 0xFFFF000000000000ULL;
3690 * The device by default set to a big endian format, so a
3691 * big endian driver need not set anything.
3693 val64 |= (SWAPPER_CTRL_TXP_FE |
3694 SWAPPER_CTRL_TXP_SE |
3695 SWAPPER_CTRL_TXD_R_FE |
3696 SWAPPER_CTRL_TXD_W_FE |
3697 SWAPPER_CTRL_TXF_R_FE |
3698 SWAPPER_CTRL_RXD_R_FE |
3699 SWAPPER_CTRL_RXD_W_FE |
3700 SWAPPER_CTRL_RXF_W_FE |
3701 SWAPPER_CTRL_XMSI_FE |
3702 SWAPPER_CTRL_STATS_FE |
3703 SWAPPER_CTRL_STATS_SE);
3704 if (sp->config.intr_type == INTA)
3705 val64 |= SWAPPER_CTRL_XMSI_SE;
3706 writeq(val64, &bar0->swapper_ctrl);
3709 * Initially we enable all bits to make it accessible by the
3710 * driver, then we selectively enable only those bits that
3713 val64 |= (SWAPPER_CTRL_TXP_FE |
3714 SWAPPER_CTRL_TXP_SE |
3715 SWAPPER_CTRL_TXD_R_FE |
3716 SWAPPER_CTRL_TXD_R_SE |
3717 SWAPPER_CTRL_TXD_W_FE |
3718 SWAPPER_CTRL_TXD_W_SE |
3719 SWAPPER_CTRL_TXF_R_FE |
3720 SWAPPER_CTRL_RXD_R_FE |
3721 SWAPPER_CTRL_RXD_R_SE |
3722 SWAPPER_CTRL_RXD_W_FE |
3723 SWAPPER_CTRL_RXD_W_SE |
3724 SWAPPER_CTRL_RXF_W_FE |
3725 SWAPPER_CTRL_XMSI_FE |
3726 SWAPPER_CTRL_STATS_FE |
3727 SWAPPER_CTRL_STATS_SE);
3728 if (sp->config.intr_type == INTA)
3729 val64 |= SWAPPER_CTRL_XMSI_SE;
3730 writeq(val64, &bar0->swapper_ctrl);
3732 val64 = readq(&bar0->swapper_ctrl);
3735 * Verifying if endian settings are accurate by reading a
3736 * feedback register.
3738 val64 = readq(&bar0->pif_rd_swapper_fb);
3739 if (val64 != 0x0123456789ABCDEFULL) {
3740 /* Endian settings are incorrect, calls for another dekko. */
3741 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3743 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3744 (unsigned long long)val64);
3751 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3753 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3755 int ret = 0, cnt = 0;
3758 val64 = readq(&bar0->xmsi_access);
3759 if (!(val64 & s2BIT(15)))
3765 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3772 static void restore_xmsi_data(struct s2io_nic *nic)
3774 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3778 if (nic->device_type == XFRAME_I_DEVICE)
3781 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3782 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3783 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3784 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3785 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3786 writeq(val64, &bar0->xmsi_access);
3787 if (wait_for_msix_trans(nic, msix_index)) {
3788 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3794 static void store_xmsi_data(struct s2io_nic *nic)
3796 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3797 u64 val64, addr, data;
3800 if (nic->device_type == XFRAME_I_DEVICE)
3803 /* Store and display */
3804 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3805 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3806 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3807 writeq(val64, &bar0->xmsi_access);
3808 if (wait_for_msix_trans(nic, msix_index)) {
3809 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3812 addr = readq(&bar0->xmsi_address);
3813 data = readq(&bar0->xmsi_data);
3815 nic->msix_info[i].addr = addr;
3816 nic->msix_info[i].data = data;
3821 static int s2io_enable_msi_x(struct s2io_nic *nic)
3823 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3825 u16 msi_control; /* Temp variable */
3826 int ret, i, j, msix_indx = 1;
3829 size = nic->num_entries * sizeof(struct msix_entry);
3830 nic->entries = kzalloc(size, GFP_KERNEL);
3831 if (!nic->entries) {
3832 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3834 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3837 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
3839 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3840 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3841 if (!nic->s2io_entries) {
3842 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3844 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3845 kfree(nic->entries);
3846 nic->mac_control.stats_info->sw_stat.mem_freed
3847 += (nic->num_entries * sizeof(struct msix_entry));
3850 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
3852 nic->entries[0].entry = 0;
3853 nic->s2io_entries[0].entry = 0;
3854 nic->s2io_entries[0].in_use = MSIX_FLG;
3855 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3856 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3858 for (i = 1; i < nic->num_entries; i++) {
3859 nic->entries[i].entry = ((i - 1) * 8) + 1;
3860 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3861 nic->s2io_entries[i].arg = NULL;
3862 nic->s2io_entries[i].in_use = 0;
3865 rx_mat = readq(&bar0->rx_mat);
3866 for (j = 0; j < nic->config.rx_ring_num; j++) {
3867 rx_mat |= RX_MAT_SET(j, msix_indx);
3868 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3869 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3870 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3873 writeq(rx_mat, &bar0->rx_mat);
3874 readq(&bar0->rx_mat);
3876 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3877 /* We fail init if error or we get less vectors than min required */
3879 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
3880 kfree(nic->entries);
3881 nic->mac_control.stats_info->sw_stat.mem_freed
3882 += (nic->num_entries * sizeof(struct msix_entry));
3883 kfree(nic->s2io_entries);
3884 nic->mac_control.stats_info->sw_stat.mem_freed
3885 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3886 nic->entries = NULL;
3887 nic->s2io_entries = NULL;
3892 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3893 * in the herc NIC. (Temp change, needs to be removed later)
3895 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3896 msi_control |= 0x1; /* Enable MSI */
3897 pci_write_config_word(nic->pdev, 0x42, msi_control);
3902 /* Handle software interrupt used during MSI(X) test */
3903 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3905 struct s2io_nic *sp = dev_id;
3907 sp->msi_detected = 1;
3908 wake_up(&sp->msi_wait);
3913 /* Test interrupt path by forcing a a software IRQ */
3914 static int s2io_test_msi(struct s2io_nic *sp)
3916 struct pci_dev *pdev = sp->pdev;
3917 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3921 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3924 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3925 sp->dev->name, pci_name(pdev), pdev->irq);
3929 init_waitqueue_head(&sp->msi_wait);
3930 sp->msi_detected = 0;
3932 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3933 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3934 val64 |= SCHED_INT_CTRL_TIMER_EN;
3935 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3936 writeq(val64, &bar0->scheduled_int_ctrl);
3938 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3940 if (!sp->msi_detected) {
3941 /* MSI(X) test failed, go back to INTx mode */
3942 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3943 "using MSI(X) during test\n", sp->dev->name,
3949 free_irq(sp->entries[1].vector, sp);
3951 writeq(saved64, &bar0->scheduled_int_ctrl);
3956 static void remove_msix_isr(struct s2io_nic *sp)
3961 for (i = 0; i < sp->num_entries; i++) {
3962 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3963 int vector = sp->entries[i].vector;
3964 void *arg = sp->s2io_entries[i].arg;
3965 free_irq(vector, arg);
3970 kfree(sp->s2io_entries);
3972 sp->s2io_entries = NULL;
3974 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3975 msi_control &= 0xFFFE; /* Disable MSI */
3976 pci_write_config_word(sp->pdev, 0x42, msi_control);
3978 pci_disable_msix(sp->pdev);
3981 static void remove_inta_isr(struct s2io_nic *sp)
3983 struct net_device *dev = sp->dev;
3985 free_irq(sp->pdev->irq, dev);
3988 /* ********************************************************* *
3989 * Functions defined below concern the OS part of the driver *
3990 * ********************************************************* */
3993 * s2io_open - open entry point of the driver
3994 * @dev : pointer to the device structure.
3996 * This function is the open entry point of the driver. It mainly calls a
3997 * function to allocate Rx buffers and inserts them into the buffer
3998 * descriptors and then enables the Rx part of the NIC.
4000 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4004 static int s2io_open(struct net_device *dev)
4006 struct s2io_nic *sp = netdev_priv(dev);
4010 * Make sure you have link off by default every time
4011 * Nic is initialized
4013 netif_carrier_off(dev);
4014 sp->last_link_state = 0;
4016 /* Initialize H/W and enable interrupts */
4017 err = s2io_card_up(sp);
4019 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4021 goto hw_init_failed;
4024 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4025 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4028 goto hw_init_failed;
4030 s2io_start_all_tx_queue(sp);
4034 if (sp->config.intr_type == MSI_X) {
4037 sp->mac_control.stats_info->sw_stat.mem_freed
4038 += (sp->num_entries * sizeof(struct msix_entry));
4040 if (sp->s2io_entries) {
4041 kfree(sp->s2io_entries);
4042 sp->mac_control.stats_info->sw_stat.mem_freed
4043 += (sp->num_entries * sizeof(struct s2io_msix_entry));
4050 * s2io_close -close entry point of the driver
4051 * @dev : device pointer.
4053 * This is the stop entry point of the driver. It needs to undo exactly
4054 * whatever was done by the open entry point,thus it's usually referred to
4055 * as the close function.Among other things this function mainly stops the
4056 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4058 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4062 static int s2io_close(struct net_device *dev)
4064 struct s2io_nic *sp = netdev_priv(dev);
4065 struct config_param *config = &sp->config;
4069 /* Return if the device is already closed *
4070 * Can happen when s2io_card_up failed in change_mtu *
4072 if (!is_s2io_card_up(sp))
4075 s2io_stop_all_tx_queue(sp);
4076 /* delete all populated mac entries */
4077 for (offset = 1; offset < config->max_mc_addr; offset++) {
4078 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4079 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4080 do_s2io_delete_unicast_mc(sp, tmp64);
4089 * s2io_xmit - Tx entry point of te driver
4090 * @skb : the socket buffer containing the Tx data.
4091 * @dev : device pointer.
4093 * This function is the Tx entry point of the driver. S2IO NIC supports
4094 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4095 * NOTE: when device cant queue the pkt,just the trans_start variable will
4098 * 0 on success & 1 on failure.
4101 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4103 struct s2io_nic *sp = netdev_priv(dev);
4104 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4107 struct TxFIFO_element __iomem *tx_fifo;
4108 unsigned long flags = 0;
4110 struct fifo_info *fifo = NULL;
4111 struct mac_info *mac_control;
4112 struct config_param *config;
4113 int do_spin_lock = 1;
4115 int enable_per_list_interrupt = 0;
4116 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4118 mac_control = &sp->mac_control;
4119 config = &sp->config;
4121 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4123 if (unlikely(skb->len <= 0)) {
4124 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4125 dev_kfree_skb_any(skb);
4126 return NETDEV_TX_OK;
4129 if (!is_s2io_card_up(sp)) {
4130 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4133 return NETDEV_TX_OK;
4137 if (sp->vlgrp && vlan_tx_tag_present(skb))
4138 vlan_tag = vlan_tx_tag_get(skb);
4139 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4140 if (skb->protocol == htons(ETH_P_IP)) {
4145 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4146 th = (struct tcphdr *)(((unsigned char *)ip) +
4149 if (ip->protocol == IPPROTO_TCP) {
4150 queue_len = sp->total_tcp_fifos;
4151 queue = (ntohs(th->source) +
4153 sp->fifo_selector[queue_len - 1];
4154 if (queue >= queue_len)
4155 queue = queue_len - 1;
4156 } else if (ip->protocol == IPPROTO_UDP) {
4157 queue_len = sp->total_udp_fifos;
4158 queue = (ntohs(th->source) +
4160 sp->fifo_selector[queue_len - 1];
4161 if (queue >= queue_len)
4162 queue = queue_len - 1;
4163 queue += sp->udp_fifo_idx;
4164 if (skb->len > 1024)
4165 enable_per_list_interrupt = 1;
4170 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4171 /* get fifo number based on skb->priority value */
4172 queue = config->fifo_mapping
4173 [skb->priority & (MAX_TX_FIFOS - 1)];
4174 fifo = &mac_control->fifos[queue];
4177 spin_lock_irqsave(&fifo->tx_lock, flags);
4179 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4180 return NETDEV_TX_LOCKED;
4183 if (sp->config.multiq) {
4184 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4185 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4186 return NETDEV_TX_BUSY;
4188 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4189 if (netif_queue_stopped(dev)) {
4190 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4191 return NETDEV_TX_BUSY;
4195 put_off = (u16)fifo->tx_curr_put_info.offset;
4196 get_off = (u16)fifo->tx_curr_get_info.offset;
4197 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4199 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4200 /* Avoid "put" pointer going beyond "get" pointer */
4201 if (txdp->Host_Control ||
4202 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4203 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4204 s2io_stop_tx_queue(sp, fifo->fifo_no);
4206 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4207 return NETDEV_TX_OK;
4210 offload_type = s2io_offload_type(skb);
4211 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4212 txdp->Control_1 |= TXD_TCP_LSO_EN;
4213 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4215 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4216 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4220 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4221 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4222 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4223 if (enable_per_list_interrupt)
4224 if (put_off & (queue_len >> 5))
4225 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4227 txdp->Control_2 |= TXD_VLAN_ENABLE;
4228 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4231 frg_len = skb->len - skb->data_len;
4232 if (offload_type == SKB_GSO_UDP) {
4235 ufo_size = s2io_udp_mss(skb);
4237 txdp->Control_1 |= TXD_UFO_EN;
4238 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4239 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4241 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4242 fifo->ufo_in_band_v[put_off] =
4243 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4245 fifo->ufo_in_band_v[put_off] =
4246 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4248 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4249 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4250 fifo->ufo_in_band_v,
4253 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4254 goto pci_map_failed;
4258 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4259 frg_len, PCI_DMA_TODEVICE);
4260 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4261 goto pci_map_failed;
4263 txdp->Host_Control = (unsigned long)skb;
4264 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4265 if (offload_type == SKB_GSO_UDP)
4266 txdp->Control_1 |= TXD_UFO_EN;
4268 frg_cnt = skb_shinfo(skb)->nr_frags;
4269 /* For fragmented SKB. */
4270 for (i = 0; i < frg_cnt; i++) {
4271 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4272 /* A '0' length fragment will be ignored */
4276 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4280 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4281 if (offload_type == SKB_GSO_UDP)
4282 txdp->Control_1 |= TXD_UFO_EN;
4284 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4286 if (offload_type == SKB_GSO_UDP)
4287 frg_cnt++; /* as Txd0 was used for inband header */
4289 tx_fifo = mac_control->tx_FIFO_start[queue];
4290 val64 = fifo->list_info[put_off].list_phy_addr;
4291 writeq(val64, &tx_fifo->TxDL_Pointer);
4293 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4296 val64 |= TX_FIFO_SPECIAL_FUNC;
4298 writeq(val64, &tx_fifo->List_Control);
4303 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4305 fifo->tx_curr_put_info.offset = put_off;
4307 /* Avoid "put" pointer going beyond "get" pointer */
4308 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4309 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4311 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4313 s2io_stop_tx_queue(sp, fifo->fifo_no);
4315 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4316 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4318 if (sp->config.intr_type == MSI_X)
4319 tx_intr_handler(fifo);
4321 return NETDEV_TX_OK;
4323 stats->pci_map_fail_cnt++;
4324 s2io_stop_tx_queue(sp, fifo->fifo_no);
4325 stats->mem_freed += skb->truesize;
4327 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4328 return NETDEV_TX_OK;
4332 s2io_alarm_handle(unsigned long data)
4334 struct s2io_nic *sp = (struct s2io_nic *)data;
4335 struct net_device *dev = sp->dev;
4337 s2io_handle_errors(dev);
4338 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4341 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4343 struct ring_info *ring = (struct ring_info *)dev_id;
4344 struct s2io_nic *sp = ring->nic;
4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4347 if (unlikely(!is_s2io_card_up(sp)))
4350 if (sp->config.napi) {
4351 u8 __iomem *addr = NULL;
4354 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4355 addr += (7 - ring->ring_no);
4356 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4359 napi_schedule(&ring->napi);
4361 rx_intr_handler(ring, 0);
4362 s2io_chk_rx_buffers(sp, ring);
4368 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4371 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4372 struct s2io_nic *sp = fifos->nic;
4373 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4374 struct config_param *config = &sp->config;
4377 if (unlikely(!is_s2io_card_up(sp)))
4380 reason = readq(&bar0->general_int_status);
4381 if (unlikely(reason == S2IO_MINUS_ONE))
4382 /* Nothing much can be done. Get out */
4385 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4386 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4388 if (reason & GEN_INTR_TXPIC)
4389 s2io_txpic_intr_handle(sp);
4391 if (reason & GEN_INTR_TXTRAFFIC)
4392 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4394 for (i = 0; i < config->tx_fifo_num; i++)
4395 tx_intr_handler(&fifos[i]);
4397 writeq(sp->general_int_mask, &bar0->general_int_mask);
4398 readl(&bar0->general_int_status);
4401 /* The interrupt was not raised by us */
4405 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4407 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4410 val64 = readq(&bar0->pic_int_status);
4411 if (val64 & PIC_INT_GPIO) {
4412 val64 = readq(&bar0->gpio_int_reg);
4413 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4414 (val64 & GPIO_INT_REG_LINK_UP)) {
4416 * This is unstable state so clear both up/down
4417 * interrupt and adapter to re-evaluate the link state.
4419 val64 |= GPIO_INT_REG_LINK_DOWN;
4420 val64 |= GPIO_INT_REG_LINK_UP;
4421 writeq(val64, &bar0->gpio_int_reg);
4422 val64 = readq(&bar0->gpio_int_mask);
4423 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4424 GPIO_INT_MASK_LINK_DOWN);
4425 writeq(val64, &bar0->gpio_int_mask);
4426 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4427 val64 = readq(&bar0->adapter_status);
4428 /* Enable Adapter */
4429 val64 = readq(&bar0->adapter_control);
4430 val64 |= ADAPTER_CNTL_EN;
4431 writeq(val64, &bar0->adapter_control);
4432 val64 |= ADAPTER_LED_ON;
4433 writeq(val64, &bar0->adapter_control);
4434 if (!sp->device_enabled_once)
4435 sp->device_enabled_once = 1;
4437 s2io_link(sp, LINK_UP);
4439 * unmask link down interrupt and mask link-up
4442 val64 = readq(&bar0->gpio_int_mask);
4443 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4444 val64 |= GPIO_INT_MASK_LINK_UP;
4445 writeq(val64, &bar0->gpio_int_mask);
4447 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4448 val64 = readq(&bar0->adapter_status);
4449 s2io_link(sp, LINK_DOWN);
4450 /* Link is down so unmaks link up interrupt */
4451 val64 = readq(&bar0->gpio_int_mask);
4452 val64 &= ~GPIO_INT_MASK_LINK_UP;
4453 val64 |= GPIO_INT_MASK_LINK_DOWN;
4454 writeq(val64, &bar0->gpio_int_mask);
4457 val64 = readq(&bar0->adapter_control);
4458 val64 = val64 & (~ADAPTER_LED_ON);
4459 writeq(val64, &bar0->adapter_control);
4462 val64 = readq(&bar0->gpio_int_mask);
4466 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4467 * @value: alarm bits
4468 * @addr: address value
4469 * @cnt: counter variable
4470 * Description: Check for alarm and increment the counter
4472 * 1 - if alarm bit set
4473 * 0 - if alarm bit is not set
4475 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4476 unsigned long long *cnt)
4479 val64 = readq(addr);
4480 if (val64 & value) {
4481 writeq(val64, addr);
4490 * s2io_handle_errors - Xframe error indication handler
4491 * @nic: device private variable
4492 * Description: Handle alarms such as loss of link, single or
4493 * double ECC errors, critical and serious errors.
4497 static void s2io_handle_errors(void *dev_id)
4499 struct net_device *dev = (struct net_device *)dev_id;
4500 struct s2io_nic *sp = netdev_priv(dev);
4501 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4502 u64 temp64 = 0, val64 = 0;
4505 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4506 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4508 if (!is_s2io_card_up(sp))
4511 if (pci_channel_offline(sp->pdev))
4514 memset(&sw_stat->ring_full_cnt, 0,
4515 sizeof(sw_stat->ring_full_cnt));
4517 /* Handling the XPAK counters update */
4518 if (stats->xpak_timer_count < 72000) {
4519 /* waiting for an hour */
4520 stats->xpak_timer_count++;
4522 s2io_updt_xpak_counter(dev);
4523 /* reset the count to zero */
4524 stats->xpak_timer_count = 0;
4527 /* Handling link status change error Intr */
4528 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4529 val64 = readq(&bar0->mac_rmac_err_reg);
4530 writeq(val64, &bar0->mac_rmac_err_reg);
4531 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4532 schedule_work(&sp->set_link_task);
4535 /* In case of a serious error, the device will be Reset. */
4536 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4537 &sw_stat->serious_err_cnt))
4540 /* Check for data parity error */
4541 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4542 &sw_stat->parity_err_cnt))
4545 /* Check for ring full counter */
4546 if (sp->device_type == XFRAME_II_DEVICE) {
4547 val64 = readq(&bar0->ring_bump_counter1);
4548 for (i = 0; i < 4; i++) {
4549 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4550 temp64 >>= 64 - ((i+1)*16);
4551 sw_stat->ring_full_cnt[i] += temp64;
4554 val64 = readq(&bar0->ring_bump_counter2);
4555 for (i = 0; i < 4; i++) {
4556 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4557 temp64 >>= 64 - ((i+1)*16);
4558 sw_stat->ring_full_cnt[i+4] += temp64;
4562 val64 = readq(&bar0->txdma_int_status);
4563 /*check for pfc_err*/
4564 if (val64 & TXDMA_PFC_INT) {
4565 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4566 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4569 &sw_stat->pfc_err_cnt))
4571 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4573 &sw_stat->pfc_err_cnt);
4576 /*check for tda_err*/
4577 if (val64 & TXDMA_TDA_INT) {
4578 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4582 &sw_stat->tda_err_cnt))
4584 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4586 &sw_stat->tda_err_cnt);
4588 /*check for pcc_err*/
4589 if (val64 & TXDMA_PCC_INT) {
4590 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4591 PCC_N_SERR | PCC_6_COF_OV_ERR |
4592 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4593 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4596 &sw_stat->pcc_err_cnt))
4598 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4600 &sw_stat->pcc_err_cnt);
4603 /*check for tti_err*/
4604 if (val64 & TXDMA_TTI_INT) {
4605 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4607 &sw_stat->tti_err_cnt))
4609 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4611 &sw_stat->tti_err_cnt);
4614 /*check for lso_err*/
4615 if (val64 & TXDMA_LSO_INT) {
4616 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4617 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4619 &sw_stat->lso_err_cnt))
4621 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4623 &sw_stat->lso_err_cnt);
4626 /*check for tpa_err*/
4627 if (val64 & TXDMA_TPA_INT) {
4628 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4630 &sw_stat->tpa_err_cnt))
4632 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4634 &sw_stat->tpa_err_cnt);
4637 /*check for sm_err*/
4638 if (val64 & TXDMA_SM_INT) {
4639 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4641 &sw_stat->sm_err_cnt))
4645 val64 = readq(&bar0->mac_int_status);
4646 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4647 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4648 &bar0->mac_tmac_err_reg,
4649 &sw_stat->mac_tmac_err_cnt))
4651 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4652 TMAC_DESC_ECC_SG_ERR |
4653 TMAC_DESC_ECC_DB_ERR,
4654 &bar0->mac_tmac_err_reg,
4655 &sw_stat->mac_tmac_err_cnt);
4658 val64 = readq(&bar0->xgxs_int_status);
4659 if (val64 & XGXS_INT_STATUS_TXGXS) {
4660 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4661 &bar0->xgxs_txgxs_err_reg,
4662 &sw_stat->xgxs_txgxs_err_cnt))
4664 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4665 &bar0->xgxs_txgxs_err_reg,
4666 &sw_stat->xgxs_txgxs_err_cnt);
4669 val64 = readq(&bar0->rxdma_int_status);
4670 if (val64 & RXDMA_INT_RC_INT_M) {
4671 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4673 RC_PRCn_SM_ERR_ALARM |
4674 RC_FTC_SM_ERR_ALARM,
4676 &sw_stat->rc_err_cnt))
4678 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4680 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4681 &sw_stat->rc_err_cnt);
4682 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4685 &bar0->prc_pcix_err_reg,
4686 &sw_stat->prc_pcix_err_cnt))
4688 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4691 &bar0->prc_pcix_err_reg,
4692 &sw_stat->prc_pcix_err_cnt);
4695 if (val64 & RXDMA_INT_RPA_INT_M) {
4696 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4698 &sw_stat->rpa_err_cnt))
4700 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4702 &sw_stat->rpa_err_cnt);
4705 if (val64 & RXDMA_INT_RDA_INT_M) {
4706 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4707 RDA_FRM_ECC_DB_N_AERR |
4710 RDA_RXD_ECC_DB_SERR,
4712 &sw_stat->rda_err_cnt))
4714 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4715 RDA_FRM_ECC_SG_ERR |
4719 &sw_stat->rda_err_cnt);
4722 if (val64 & RXDMA_INT_RTI_INT_M) {
4723 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4725 &sw_stat->rti_err_cnt))
4727 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4729 &sw_stat->rti_err_cnt);
4732 val64 = readq(&bar0->mac_int_status);
4733 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4734 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4735 &bar0->mac_rmac_err_reg,
4736 &sw_stat->mac_rmac_err_cnt))
4738 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4739 RMAC_SINGLE_ECC_ERR |
4740 RMAC_DOUBLE_ECC_ERR,
4741 &bar0->mac_rmac_err_reg,
4742 &sw_stat->mac_rmac_err_cnt);
4745 val64 = readq(&bar0->xgxs_int_status);
4746 if (val64 & XGXS_INT_STATUS_RXGXS) {
4747 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4748 &bar0->xgxs_rxgxs_err_reg,
4749 &sw_stat->xgxs_rxgxs_err_cnt))
4753 val64 = readq(&bar0->mc_int_status);
4754 if (val64 & MC_INT_STATUS_MC_INT) {
4755 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4757 &sw_stat->mc_err_cnt))
4760 /* Handling Ecc errors */
4761 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4762 writeq(val64, &bar0->mc_err_reg);
4763 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4764 sw_stat->double_ecc_errs++;
4765 if (sp->device_type != XFRAME_II_DEVICE) {
4767 * Reset XframeI only if critical error
4770 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4771 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4775 sw_stat->single_ecc_errs++;
4781 s2io_stop_all_tx_queue(sp);
4782 schedule_work(&sp->rst_timer_task);
4783 sw_stat->soft_reset_cnt++;
4788 * s2io_isr - ISR handler of the device .
4789 * @irq: the irq of the device.
4790 * @dev_id: a void pointer to the dev structure of the NIC.
4791 * Description: This function is the ISR handler of the device. It
4792 * identifies the reason for the interrupt and calls the relevant
4793 * service routines. As a contongency measure, this ISR allocates the
4794 * recv buffers, if their numbers are below the panic value which is
4795 * presently set to 25% of the original number of rcv buffers allocated.
4797 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4798 * IRQ_NONE: will be returned if interrupt is not from our device
4800 static irqreturn_t s2io_isr(int irq, void *dev_id)
4802 struct net_device *dev = (struct net_device *)dev_id;
4803 struct s2io_nic *sp = netdev_priv(dev);
4804 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4807 struct mac_info *mac_control;
4808 struct config_param *config;
4810 /* Pretend we handled any irq's from a disconnected card */
4811 if (pci_channel_offline(sp->pdev))
4814 if (!is_s2io_card_up(sp))
4817 mac_control = &sp->mac_control;
4818 config = &sp->config;
4821 * Identify the cause for interrupt and call the appropriate
4822 * interrupt handler. Causes for the interrupt could be;
4827 reason = readq(&bar0->general_int_status);
4829 if (unlikely(reason == S2IO_MINUS_ONE))
4830 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4833 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4834 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4837 if (reason & GEN_INTR_RXTRAFFIC) {
4838 napi_schedule(&sp->napi);
4839 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4840 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4841 readl(&bar0->rx_traffic_int);
4845 * rx_traffic_int reg is an R1 register, writing all 1's
4846 * will ensure that the actual interrupt causing bit
4847 * get's cleared and hence a read can be avoided.
4849 if (reason & GEN_INTR_RXTRAFFIC)
4850 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4852 for (i = 0; i < config->rx_ring_num; i++) {
4853 struct ring_info *ring = &mac_control->rings[i];
4855 rx_intr_handler(ring, 0);
4860 * tx_traffic_int reg is an R1 register, writing all 1's
4861 * will ensure that the actual interrupt causing bit get's
4862 * cleared and hence a read can be avoided.
4864 if (reason & GEN_INTR_TXTRAFFIC)
4865 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4867 for (i = 0; i < config->tx_fifo_num; i++)
4868 tx_intr_handler(&mac_control->fifos[i]);
4870 if (reason & GEN_INTR_TXPIC)
4871 s2io_txpic_intr_handle(sp);
4874 * Reallocate the buffers from the interrupt handler itself.
4876 if (!config->napi) {
4877 for (i = 0; i < config->rx_ring_num; i++) {
4878 struct ring_info *ring = &mac_control->rings[i];
4880 s2io_chk_rx_buffers(sp, ring);
4883 writeq(sp->general_int_mask, &bar0->general_int_mask);
4884 readl(&bar0->general_int_status);
4888 } else if (!reason) {
4889 /* The interrupt was not raised by us */
4899 static void s2io_updt_stats(struct s2io_nic *sp)
4901 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4905 if (is_s2io_card_up(sp)) {
4906 /* Apprx 30us on a 133 MHz bus */
4907 val64 = SET_UPDT_CLICKS(10) |
4908 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4909 writeq(val64, &bar0->stat_cfg);
4912 val64 = readq(&bar0->stat_cfg);
4913 if (!(val64 & s2BIT(0)))
4917 break; /* Updt failed */
4923 * s2io_get_stats - Updates the device statistics structure.
4924 * @dev : pointer to the device structure.
4926 * This function updates the device statistics structure in the s2io_nic
4927 * structure and returns a pointer to the same.
4929 * pointer to the updated net_device_stats structure.
4932 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4934 struct s2io_nic *sp = netdev_priv(dev);
4935 struct mac_info *mac_control;
4936 struct config_param *config;
4940 mac_control = &sp->mac_control;
4941 config = &sp->config;
4943 /* Configure Stats for immediate updt */
4944 s2io_updt_stats(sp);
4946 /* Using sp->stats as a staging area, because reset (due to mtu
4947 change, for example) will clear some hardware counters */
4948 dev->stats.tx_packets +=
4949 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4950 sp->stats.tx_packets;
4951 sp->stats.tx_packets =
4952 le32_to_cpu(mac_control->stats_info->tmac_frms);
4953 dev->stats.tx_errors +=
4954 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4955 sp->stats.tx_errors;
4956 sp->stats.tx_errors =
4957 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4958 dev->stats.rx_errors +=
4959 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4960 sp->stats.rx_errors;
4961 sp->stats.rx_errors =
4962 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4963 dev->stats.multicast =
4964 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4965 sp->stats.multicast;
4966 sp->stats.multicast =
4967 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4968 dev->stats.rx_length_errors =
4969 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4970 sp->stats.rx_length_errors;
4971 sp->stats.rx_length_errors =
4972 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4974 /* collect per-ring rx_packets and rx_bytes */
4975 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4976 for (i = 0; i < config->rx_ring_num; i++) {
4977 struct ring_info *ring = &mac_control->rings[i];
4979 dev->stats.rx_packets += ring->rx_packets;
4980 dev->stats.rx_bytes += ring->rx_bytes;
4987 * s2io_set_multicast - entry point for multicast address enable/disable.
4988 * @dev : pointer to the device structure
4990 * This function is a driver entry point which gets called by the kernel
4991 * whenever multicast addresses must be enabled/disabled. This also gets
4992 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4993 * determine, if multicast address must be enabled or if promiscuous mode
4994 * is to be disabled etc.
4999 static void s2io_set_multicast(struct net_device *dev)
5002 struct dev_mc_list *mclist;
5003 struct s2io_nic *sp = netdev_priv(dev);
5004 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5005 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
5007 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
5009 struct config_param *config = &sp->config;
5011 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5012 /* Enable all Multicast addresses */
5013 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5014 &bar0->rmac_addr_data0_mem);
5015 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5016 &bar0->rmac_addr_data1_mem);
5017 val64 = RMAC_ADDR_CMD_MEM_WE |
5018 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5019 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
5020 writeq(val64, &bar0->rmac_addr_cmd_mem);
5021 /* Wait till command completes */
5022 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5023 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5027 sp->all_multi_pos = config->max_mc_addr - 1;
5028 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5029 /* Disable all Multicast addresses */
5030 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5031 &bar0->rmac_addr_data0_mem);
5032 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5033 &bar0->rmac_addr_data1_mem);
5034 val64 = RMAC_ADDR_CMD_MEM_WE |
5035 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5036 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5037 writeq(val64, &bar0->rmac_addr_cmd_mem);
5038 /* Wait till command completes */
5039 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5040 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5044 sp->all_multi_pos = 0;
5047 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5048 /* Put the NIC into promiscuous mode */
5049 add = &bar0->mac_cfg;
5050 val64 = readq(&bar0->mac_cfg);
5051 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5053 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5054 writel((u32)val64, add);
5055 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5056 writel((u32) (val64 >> 32), (add + 4));
5058 if (vlan_tag_strip != 1) {
5059 val64 = readq(&bar0->rx_pa_cfg);
5060 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5061 writeq(val64, &bar0->rx_pa_cfg);
5062 sp->vlan_strip_flag = 0;
5065 val64 = readq(&bar0->mac_cfg);
5066 sp->promisc_flg = 1;
5067 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5069 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5070 /* Remove the NIC from promiscuous mode */
5071 add = &bar0->mac_cfg;
5072 val64 = readq(&bar0->mac_cfg);
5073 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5075 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5076 writel((u32)val64, add);
5077 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5078 writel((u32) (val64 >> 32), (add + 4));
5080 if (vlan_tag_strip != 0) {
5081 val64 = readq(&bar0->rx_pa_cfg);
5082 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5083 writeq(val64, &bar0->rx_pa_cfg);
5084 sp->vlan_strip_flag = 1;
5087 val64 = readq(&bar0->mac_cfg);
5088 sp->promisc_flg = 0;
5089 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5093 /* Update individual M_CAST address list */
5094 if ((!sp->m_cast_flg) && dev->mc_count) {
5096 (config->max_mc_addr - config->max_mac_addr)) {
5097 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5099 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5100 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5104 prev_cnt = sp->mc_addr_count;
5105 sp->mc_addr_count = dev->mc_count;
5107 /* Clear out the previous list of Mc in the H/W. */
5108 for (i = 0; i < prev_cnt; i++) {
5109 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5110 &bar0->rmac_addr_data0_mem);
5111 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5112 &bar0->rmac_addr_data1_mem);
5113 val64 = RMAC_ADDR_CMD_MEM_WE |
5114 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5115 RMAC_ADDR_CMD_MEM_OFFSET
5116 (config->mc_start_offset + i);
5117 writeq(val64, &bar0->rmac_addr_cmd_mem);
5119 /* Wait for command completes */
5120 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5121 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5123 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
5124 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5129 /* Create the new Rx filter list and update the same in H/W. */
5130 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5131 i++, mclist = mclist->next) {
5132 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5135 for (j = 0; j < ETH_ALEN; j++) {
5136 mac_addr |= mclist->dmi_addr[j];
5140 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5141 &bar0->rmac_addr_data0_mem);
5142 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5143 &bar0->rmac_addr_data1_mem);
5144 val64 = RMAC_ADDR_CMD_MEM_WE |
5145 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5146 RMAC_ADDR_CMD_MEM_OFFSET
5147 (i + config->mc_start_offset);
5148 writeq(val64, &bar0->rmac_addr_cmd_mem);
5150 /* Wait for command completes */
5151 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5152 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5154 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
5155 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5162 /* read from CAM unicast & multicast addresses and store it in
5163 * def_mac_addr structure
5165 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5169 struct config_param *config = &sp->config;
5171 /* store unicast & multicast mac addresses */
5172 for (offset = 0; offset < config->max_mc_addr; offset++) {
5173 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5174 /* if read fails disable the entry */
5175 if (mac_addr == FAILURE)
5176 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5177 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5181 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5182 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5185 struct config_param *config = &sp->config;
5186 /* restore unicast mac address */
5187 for (offset = 0; offset < config->max_mac_addr; offset++)
5188 do_s2io_prog_unicast(sp->dev,
5189 sp->def_mac_addr[offset].mac_addr);
5191 /* restore multicast mac address */
5192 for (offset = config->mc_start_offset;
5193 offset < config->max_mc_addr; offset++)
5194 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5197 /* add a multicast MAC address to CAM */
5198 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5202 struct config_param *config = &sp->config;
5204 for (i = 0; i < ETH_ALEN; i++) {
5206 mac_addr |= addr[i];
5208 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5211 /* check if the multicast mac already preset in CAM */
5212 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5214 tmp64 = do_s2io_read_unicast_mc(sp, i);
5215 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5218 if (tmp64 == mac_addr)
5221 if (i == config->max_mc_addr) {
5223 "CAM full no space left for multicast MAC\n");
5226 /* Update the internal structure with this new mac address */
5227 do_s2io_copy_mac_addr(sp, i, mac_addr);
5229 return do_s2io_add_mac(sp, mac_addr, i);
5232 /* add MAC address to CAM */
5233 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5236 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5238 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5239 &bar0->rmac_addr_data0_mem);
5241 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5242 RMAC_ADDR_CMD_MEM_OFFSET(off);
5243 writeq(val64, &bar0->rmac_addr_cmd_mem);
5245 /* Wait till command completes */
5246 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5247 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5249 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5254 /* deletes a specified unicast/multicast mac entry from CAM */
5255 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5258 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5259 struct config_param *config = &sp->config;
5262 offset < config->max_mc_addr; offset++) {
5263 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5264 if (tmp64 == addr) {
5265 /* disable the entry by writing 0xffffffffffffULL */
5266 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5268 /* store the new mac list from CAM */
5269 do_s2io_store_unicast_mc(sp);
5273 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5274 (unsigned long long)addr);
5278 /* read mac entries from CAM */
5279 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5281 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5282 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5285 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5286 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5287 writeq(val64, &bar0->rmac_addr_cmd_mem);
5289 /* Wait till command completes */
5290 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5291 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5293 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5296 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5302 * s2io_set_mac_addr driver entry point
5305 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5307 struct sockaddr *addr = p;
5309 if (!is_valid_ether_addr(addr->sa_data))
5312 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5314 /* store the MAC address in CAM */
5315 return do_s2io_prog_unicast(dev, dev->dev_addr);
5318 * do_s2io_prog_unicast - Programs the Xframe mac address
5319 * @dev : pointer to the device structure.
5320 * @addr: a uchar pointer to the new mac address which is to be set.
5321 * Description : This procedure will program the Xframe to receive
5322 * frames with new Mac Address
5323 * Return value: SUCCESS on success and an appropriate (-)ve integer
5324 * as defined in errno.h file on failure.
5327 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5329 struct s2io_nic *sp = netdev_priv(dev);
5330 register u64 mac_addr = 0, perm_addr = 0;
5333 struct config_param *config = &sp->config;
5336 * Set the new MAC address as the new unicast filter and reflect this
5337 * change on the device address registered with the OS. It will be
5340 for (i = 0; i < ETH_ALEN; i++) {
5342 mac_addr |= addr[i];
5344 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5347 /* check if the dev_addr is different than perm_addr */
5348 if (mac_addr == perm_addr)
5351 /* check if the mac already preset in CAM */
5352 for (i = 1; i < config->max_mac_addr; i++) {
5353 tmp64 = do_s2io_read_unicast_mc(sp, i);
5354 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5357 if (tmp64 == mac_addr) {
5359 "MAC addr:0x%llx already present in CAM\n",
5360 (unsigned long long)mac_addr);
5364 if (i == config->max_mac_addr) {
5365 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5368 /* Update the internal structure with this new mac address */
5369 do_s2io_copy_mac_addr(sp, i, mac_addr);
5371 return do_s2io_add_mac(sp, mac_addr, i);
5375 * s2io_ethtool_sset - Sets different link parameters.
5376 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5377 * @info: pointer to the structure with parameters given by ethtool to set
5380 * The function sets different link parameters provided by the user onto
5386 static int s2io_ethtool_sset(struct net_device *dev,
5387 struct ethtool_cmd *info)
5389 struct s2io_nic *sp = netdev_priv(dev);
5390 if ((info->autoneg == AUTONEG_ENABLE) ||
5391 (info->speed != SPEED_10000) ||
5392 (info->duplex != DUPLEX_FULL))
5395 s2io_close(sp->dev);
5403 * s2io_ethtol_gset - Return link specific information.
5404 * @sp : private member of the device structure, pointer to the
5405 * s2io_nic structure.
5406 * @info : pointer to the structure with parameters given by ethtool
5407 * to return link information.
5409 * Returns link specific information like speed, duplex etc.. to ethtool.
5411 * return 0 on success.
5414 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5416 struct s2io_nic *sp = netdev_priv(dev);
5417 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5418 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5419 info->port = PORT_FIBRE;
5421 /* info->transceiver */
5422 info->transceiver = XCVR_EXTERNAL;
5424 if (netif_carrier_ok(sp->dev)) {
5425 info->speed = 10000;
5426 info->duplex = DUPLEX_FULL;
5432 info->autoneg = AUTONEG_DISABLE;
5437 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5438 * @sp : private member of the device structure, which is a pointer to the
5439 * s2io_nic structure.
5440 * @info : pointer to the structure with parameters given by ethtool to
5441 * return driver information.
5443 * Returns driver specefic information like name, version etc.. to ethtool.
5448 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5449 struct ethtool_drvinfo *info)
5451 struct s2io_nic *sp = netdev_priv(dev);
5453 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5454 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5455 strncpy(info->fw_version, "", sizeof(info->fw_version));
5456 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5457 info->regdump_len = XENA_REG_SPACE;
5458 info->eedump_len = XENA_EEPROM_SPACE;
5462 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5463 * @sp: private member of the device structure, which is a pointer to the
5464 * s2io_nic structure.
5465 * @regs : pointer to the structure with parameters given by ethtool for
5466 * dumping the registers.
5467 * @reg_space: The input argumnet into which all the registers are dumped.
5469 * Dumps the entire register space of xFrame NIC into the user given
5475 static void s2io_ethtool_gregs(struct net_device *dev,
5476 struct ethtool_regs *regs, void *space)
5480 u8 *reg_space = (u8 *)space;
5481 struct s2io_nic *sp = netdev_priv(dev);
5483 regs->len = XENA_REG_SPACE;
5484 regs->version = sp->pdev->subsystem_device;
5486 for (i = 0; i < regs->len; i += 8) {
5487 reg = readq(sp->bar0 + i);
5488 memcpy((reg_space + i), ®, 8);
5493 * s2io_phy_id - timer function that alternates adapter LED.
5494 * @data : address of the private member of the device structure, which
5495 * is a pointer to the s2io_nic structure, provided as an u32.
5496 * Description: This is actually the timer function that alternates the
5497 * adapter LED bit of the adapter control bit to set/reset every time on
5498 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5499 * once every second.
5501 static void s2io_phy_id(unsigned long data)
5503 struct s2io_nic *sp = (struct s2io_nic *)data;
5504 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5508 subid = sp->pdev->subsystem_device;
5509 if ((sp->device_type == XFRAME_II_DEVICE) ||
5510 ((subid & 0xFF) >= 0x07)) {
5511 val64 = readq(&bar0->gpio_control);
5512 val64 ^= GPIO_CTRL_GPIO_0;
5513 writeq(val64, &bar0->gpio_control);
5515 val64 = readq(&bar0->adapter_control);
5516 val64 ^= ADAPTER_LED_ON;
5517 writeq(val64, &bar0->adapter_control);
5520 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5524 * s2io_ethtool_idnic - To physically identify the nic on the system.
5525 * @sp : private member of the device structure, which is a pointer to the
5526 * s2io_nic structure.
5527 * @id : pointer to the structure with identification parameters given by
5529 * Description: Used to physically identify the NIC on the system.
5530 * The Link LED will blink for a time specified by the user for
5532 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5533 * identification is possible only if it's link is up.
5535 * int , returns 0 on success
5538 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5540 u64 val64 = 0, last_gpio_ctrl_val;
5541 struct s2io_nic *sp = netdev_priv(dev);
5542 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5545 subid = sp->pdev->subsystem_device;
5546 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5547 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5548 val64 = readq(&bar0->adapter_control);
5549 if (!(val64 & ADAPTER_CNTL_EN)) {
5551 "Adapter Link down, cannot blink LED\n");
5555 if (sp->id_timer.function == NULL) {
5556 init_timer(&sp->id_timer);
5557 sp->id_timer.function = s2io_phy_id;
5558 sp->id_timer.data = (unsigned long)sp;
5560 mod_timer(&sp->id_timer, jiffies);
5562 msleep_interruptible(data * HZ);
5564 msleep_interruptible(MAX_FLICKER_TIME);
5565 del_timer_sync(&sp->id_timer);
5567 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5568 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5569 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5575 static void s2io_ethtool_gringparam(struct net_device *dev,
5576 struct ethtool_ringparam *ering)
5578 struct s2io_nic *sp = netdev_priv(dev);
5579 int i, tx_desc_count = 0, rx_desc_count = 0;
5581 if (sp->rxd_mode == RXD_MODE_1)
5582 ering->rx_max_pending = MAX_RX_DESC_1;
5583 else if (sp->rxd_mode == RXD_MODE_3B)
5584 ering->rx_max_pending = MAX_RX_DESC_2;
5586 ering->tx_max_pending = MAX_TX_DESC;
5587 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5588 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5590 DBG_PRINT(INFO_DBG, "\nmax txds : %d\n", sp->config.max_txds);
5591 ering->tx_pending = tx_desc_count;
5593 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5594 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5596 ering->rx_pending = rx_desc_count;
5598 ering->rx_mini_max_pending = 0;
5599 ering->rx_mini_pending = 0;
5600 if (sp->rxd_mode == RXD_MODE_1)
5601 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5602 else if (sp->rxd_mode == RXD_MODE_3B)
5603 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5604 ering->rx_jumbo_pending = rx_desc_count;
5608 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5609 * @sp : private member of the device structure, which is a pointer to the
5610 * s2io_nic structure.
5611 * @ep : pointer to the structure with pause parameters given by ethtool.
5613 * Returns the Pause frame generation and reception capability of the NIC.
5617 static void s2io_ethtool_getpause_data(struct net_device *dev,
5618 struct ethtool_pauseparam *ep)
5621 struct s2io_nic *sp = netdev_priv(dev);
5622 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5624 val64 = readq(&bar0->rmac_pause_cfg);
5625 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5626 ep->tx_pause = true;
5627 if (val64 & RMAC_PAUSE_RX_ENABLE)
5628 ep->rx_pause = true;
5629 ep->autoneg = false;
5633 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5634 * @sp : private member of the device structure, which is a pointer to the
5635 * s2io_nic structure.
5636 * @ep : pointer to the structure with pause parameters given by ethtool.
5638 * It can be used to set or reset Pause frame generation or reception
5639 * support of the NIC.
5641 * int, returns 0 on Success
5644 static int s2io_ethtool_setpause_data(struct net_device *dev,
5645 struct ethtool_pauseparam *ep)
5648 struct s2io_nic *sp = netdev_priv(dev);
5649 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5651 val64 = readq(&bar0->rmac_pause_cfg);
5653 val64 |= RMAC_PAUSE_GEN_ENABLE;
5655 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5657 val64 |= RMAC_PAUSE_RX_ENABLE;
5659 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5660 writeq(val64, &bar0->rmac_pause_cfg);
5665 * read_eeprom - reads 4 bytes of data from user given offset.
5666 * @sp : private member of the device structure, which is a pointer to the
5667 * s2io_nic structure.
5668 * @off : offset at which the data must be written
5669 * @data : Its an output parameter where the data read at the given
5672 * Will read 4 bytes of data from the user given offset and return the
5674 * NOTE: Will allow to read only part of the EEPROM visible through the
5677 * -1 on failure and 0 on success.
5680 #define S2IO_DEV_ID 5
5681 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5686 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5688 if (sp->device_type == XFRAME_I_DEVICE) {
5689 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5690 I2C_CONTROL_ADDR(off) |
5691 I2C_CONTROL_BYTE_CNT(0x3) |
5693 I2C_CONTROL_CNTL_START;
5694 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5696 while (exit_cnt < 5) {
5697 val64 = readq(&bar0->i2c_control);
5698 if (I2C_CONTROL_CNTL_END(val64)) {
5699 *data = I2C_CONTROL_GET_DATA(val64);
5708 if (sp->device_type == XFRAME_II_DEVICE) {
5709 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5710 SPI_CONTROL_BYTECNT(0x3) |
5711 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5712 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5713 val64 |= SPI_CONTROL_REQ;
5714 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5715 while (exit_cnt < 5) {
5716 val64 = readq(&bar0->spi_control);
5717 if (val64 & SPI_CONTROL_NACK) {
5720 } else if (val64 & SPI_CONTROL_DONE) {
5721 *data = readq(&bar0->spi_data);
5734 * write_eeprom - actually writes the relevant part of the data value.
5735 * @sp : private member of the device structure, which is a pointer to the
5736 * s2io_nic structure.
5737 * @off : offset at which the data must be written
5738 * @data : The data that is to be written
5739 * @cnt : Number of bytes of the data that are actually to be written into
5740 * the Eeprom. (max of 3)
5742 * Actually writes the relevant part of the data value into the Eeprom
5743 * through the I2C bus.
5745 * 0 on success, -1 on failure.
5748 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5750 int exit_cnt = 0, ret = -1;
5752 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5754 if (sp->device_type == XFRAME_I_DEVICE) {
5755 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5756 I2C_CONTROL_ADDR(off) |
5757 I2C_CONTROL_BYTE_CNT(cnt) |
5758 I2C_CONTROL_SET_DATA((u32)data) |
5759 I2C_CONTROL_CNTL_START;
5760 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5762 while (exit_cnt < 5) {
5763 val64 = readq(&bar0->i2c_control);
5764 if (I2C_CONTROL_CNTL_END(val64)) {
5765 if (!(val64 & I2C_CONTROL_NACK))
5774 if (sp->device_type == XFRAME_II_DEVICE) {
5775 int write_cnt = (cnt == 8) ? 0 : cnt;
5776 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5778 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5779 SPI_CONTROL_BYTECNT(write_cnt) |
5780 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5781 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5782 val64 |= SPI_CONTROL_REQ;
5783 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5784 while (exit_cnt < 5) {
5785 val64 = readq(&bar0->spi_control);
5786 if (val64 & SPI_CONTROL_NACK) {
5789 } else if (val64 & SPI_CONTROL_DONE) {
5799 static void s2io_vpd_read(struct s2io_nic *nic)
5803 int i = 0, cnt, fail = 0;
5804 int vpd_addr = 0x80;
5806 if (nic->device_type == XFRAME_II_DEVICE) {
5807 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5810 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5813 strcpy(nic->serial_num, "NOT AVAILABLE");
5815 vpd_data = kmalloc(256, GFP_KERNEL);
5817 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5820 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5822 for (i = 0; i < 256; i += 4) {
5823 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5824 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5825 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5826 for (cnt = 0; cnt < 5; cnt++) {
5828 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5833 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5837 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5838 (u32 *)&vpd_data[i]);
5842 /* read serial number of adapter */
5843 for (cnt = 0; cnt < 256; cnt++) {
5844 if ((vpd_data[cnt] == 'S') &&
5845 (vpd_data[cnt+1] == 'N') &&
5846 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5847 memset(nic->serial_num, 0, VPD_STRING_LEN);
5848 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5855 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5856 memset(nic->product_name, 0, vpd_data[1]);
5857 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5860 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5864 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5865 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5866 * @eeprom : pointer to the user level structure provided by ethtool,
5867 * containing all relevant information.
5868 * @data_buf : user defined value to be written into Eeprom.
5869 * Description: Reads the values stored in the Eeprom at given offset
5870 * for a given length. Stores these values int the input argument data
5871 * buffer 'data_buf' and returns these to the caller (ethtool.)
5876 static int s2io_ethtool_geeprom(struct net_device *dev,
5877 struct ethtool_eeprom *eeprom, u8 * data_buf)
5881 struct s2io_nic *sp = netdev_priv(dev);
5883 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5885 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5886 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5888 for (i = 0; i < eeprom->len; i += 4) {
5889 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5890 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5894 memcpy((data_buf + i), &valid, 4);
5900 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5901 * @sp : private member of the device structure, which is a pointer to the
5902 * s2io_nic structure.
5903 * @eeprom : pointer to the user level structure provided by ethtool,
5904 * containing all relevant information.
5905 * @data_buf ; user defined value to be written into Eeprom.
5907 * Tries to write the user provided value in the Eeprom, at the offset
5908 * given by the user.
5910 * 0 on success, -EFAULT on failure.
5913 static int s2io_ethtool_seeprom(struct net_device *dev,
5914 struct ethtool_eeprom *eeprom,
5917 int len = eeprom->len, cnt = 0;
5918 u64 valid = 0, data;
5919 struct s2io_nic *sp = netdev_priv(dev);
5921 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5923 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5924 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", eeprom->magic);
5929 data = (u32)data_buf[cnt] & 0x000000FF;
5931 valid = (u32)(data << 24);
5935 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5937 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5939 "write into the specified offset\n");
5950 * s2io_register_test - reads and writes into all clock domains.
5951 * @sp : private member of the device structure, which is a pointer to the
5952 * s2io_nic structure.
5953 * @data : variable that returns the result of each of the test conducted b
5956 * Read and write into all clock domains. The NIC has 3 clock domains,
5957 * see that registers in all the three regions are accessible.
5962 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5964 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5965 u64 val64 = 0, exp_val;
5968 val64 = readq(&bar0->pif_rd_swapper_fb);
5969 if (val64 != 0x123456789abcdefULL) {
5971 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5974 val64 = readq(&bar0->rmac_pause_cfg);
5975 if (val64 != 0xc000ffff00000000ULL) {
5977 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5980 val64 = readq(&bar0->rx_queue_cfg);
5981 if (sp->device_type == XFRAME_II_DEVICE)
5982 exp_val = 0x0404040404040404ULL;
5984 exp_val = 0x0808080808080808ULL;
5985 if (val64 != exp_val) {
5987 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5990 val64 = readq(&bar0->xgxs_efifo_cfg);
5991 if (val64 != 0x000000001923141EULL) {
5993 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5996 val64 = 0x5A5A5A5A5A5A5A5AULL;
5997 writeq(val64, &bar0->xmsi_data);
5998 val64 = readq(&bar0->xmsi_data);
5999 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
6001 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
6004 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6005 writeq(val64, &bar0->xmsi_data);
6006 val64 = readq(&bar0->xmsi_data);
6007 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6009 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
6017 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
6018 * @sp : private member of the device structure, which is a pointer to the
6019 * s2io_nic structure.
6020 * @data:variable that returns the result of each of the test conducted by
6023 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
6029 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
6032 u64 ret_data, org_4F0, org_7F0;
6033 u8 saved_4F0 = 0, saved_7F0 = 0;
6034 struct net_device *dev = sp->dev;
6036 /* Test Write Error at offset 0 */
6037 /* Note that SPI interface allows write access to all areas
6038 * of EEPROM. Hence doing all negative testing only for Xframe I.
6040 if (sp->device_type == XFRAME_I_DEVICE)
6041 if (!write_eeprom(sp, 0, 0, 3))
6044 /* Save current values at offsets 0x4F0 and 0x7F0 */
6045 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6047 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6050 /* Test Write at offset 4f0 */
6051 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6053 if (read_eeprom(sp, 0x4F0, &ret_data))
6056 if (ret_data != 0x012345) {
6057 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6058 "Data written %llx Data read %llx\n",
6059 dev->name, (unsigned long long)0x12345,
6060 (unsigned long long)ret_data);
6064 /* Reset the EEPROM data go FFFF */
6065 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6067 /* Test Write Request Error at offset 0x7c */
6068 if (sp->device_type == XFRAME_I_DEVICE)
6069 if (!write_eeprom(sp, 0x07C, 0, 3))
6072 /* Test Write Request at offset 0x7f0 */
6073 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6075 if (read_eeprom(sp, 0x7F0, &ret_data))
6078 if (ret_data != 0x012345) {
6079 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6080 "Data written %llx Data read %llx\n",
6081 dev->name, (unsigned long long)0x12345,
6082 (unsigned long long)ret_data);
6086 /* Reset the EEPROM data go FFFF */
6087 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6089 if (sp->device_type == XFRAME_I_DEVICE) {
6090 /* Test Write Error at offset 0x80 */
6091 if (!write_eeprom(sp, 0x080, 0, 3))
6094 /* Test Write Error at offset 0xfc */
6095 if (!write_eeprom(sp, 0x0FC, 0, 3))
6098 /* Test Write Error at offset 0x100 */
6099 if (!write_eeprom(sp, 0x100, 0, 3))
6102 /* Test Write Error at offset 4ec */
6103 if (!write_eeprom(sp, 0x4EC, 0, 3))
6107 /* Restore values at offsets 0x4F0 and 0x7F0 */
6109 write_eeprom(sp, 0x4F0, org_4F0, 3);
6111 write_eeprom(sp, 0x7F0, org_7F0, 3);
6118 * s2io_bist_test - invokes the MemBist test of the card .
6119 * @sp : private member of the device structure, which is a pointer to the
6120 * s2io_nic structure.
6121 * @data:variable that returns the result of each of the test conducted by
6124 * This invokes the MemBist test of the card. We give around
6125 * 2 secs time for the Test to complete. If it's still not complete
6126 * within this peiod, we consider that the test failed.
6128 * 0 on success and -1 on failure.
6131 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6134 int cnt = 0, ret = -1;
6136 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6137 bist |= PCI_BIST_START;
6138 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6141 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6142 if (!(bist & PCI_BIST_START)) {
6143 *data = (bist & PCI_BIST_CODE_MASK);
6155 * s2io-link_test - verifies the link state of the nic
6156 * @sp ; private member of the device structure, which is a pointer to the
6157 * s2io_nic structure.
6158 * @data: variable that returns the result of each of the test conducted by
6161 * The function verifies the link state of the NIC and updates the input
6162 * argument 'data' appropriately.
6167 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6169 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6172 val64 = readq(&bar0->adapter_status);
6173 if (!(LINK_IS_UP(val64)))
6182 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6183 * @sp - private member of the device structure, which is a pointer to the
6184 * s2io_nic structure.
6185 * @data - variable that returns the result of each of the test
6186 * conducted by the driver.
6188 * This is one of the offline test that tests the read and write
6189 * access to the RldRam chip on the NIC.
6194 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6196 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6198 int cnt, iteration = 0, test_fail = 0;
6200 val64 = readq(&bar0->adapter_control);
6201 val64 &= ~ADAPTER_ECC_EN;
6202 writeq(val64, &bar0->adapter_control);
6204 val64 = readq(&bar0->mc_rldram_test_ctrl);
6205 val64 |= MC_RLDRAM_TEST_MODE;
6206 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6208 val64 = readq(&bar0->mc_rldram_mrs);
6209 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6210 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6212 val64 |= MC_RLDRAM_MRS_ENABLE;
6213 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6215 while (iteration < 2) {
6216 val64 = 0x55555555aaaa0000ULL;
6218 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6219 writeq(val64, &bar0->mc_rldram_test_d0);
6221 val64 = 0xaaaa5a5555550000ULL;
6223 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6224 writeq(val64, &bar0->mc_rldram_test_d1);
6226 val64 = 0x55aaaaaaaa5a0000ULL;
6228 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6229 writeq(val64, &bar0->mc_rldram_test_d2);
6231 val64 = (u64) (0x0000003ffffe0100ULL);
6232 writeq(val64, &bar0->mc_rldram_test_add);
6234 val64 = MC_RLDRAM_TEST_MODE |
6235 MC_RLDRAM_TEST_WRITE |
6237 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6239 for (cnt = 0; cnt < 5; cnt++) {
6240 val64 = readq(&bar0->mc_rldram_test_ctrl);
6241 if (val64 & MC_RLDRAM_TEST_DONE)
6249 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6250 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6252 for (cnt = 0; cnt < 5; cnt++) {
6253 val64 = readq(&bar0->mc_rldram_test_ctrl);
6254 if (val64 & MC_RLDRAM_TEST_DONE)
6262 val64 = readq(&bar0->mc_rldram_test_ctrl);
6263 if (!(val64 & MC_RLDRAM_TEST_PASS))
6271 /* Bring the adapter out of test mode */
6272 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6278 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6279 * @sp : private member of the device structure, which is a pointer to the
6280 * s2io_nic structure.
6281 * @ethtest : pointer to a ethtool command specific structure that will be
6282 * returned to the user.
6283 * @data : variable that returns the result of each of the test
6284 * conducted by the driver.
6286 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6287 * the health of the card.
6292 static void s2io_ethtool_test(struct net_device *dev,
6293 struct ethtool_test *ethtest,
6296 struct s2io_nic *sp = netdev_priv(dev);
6297 int orig_state = netif_running(sp->dev);
6299 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6300 /* Offline Tests. */
6302 s2io_close(sp->dev);
6304 if (s2io_register_test(sp, &data[0]))
6305 ethtest->flags |= ETH_TEST_FL_FAILED;
6309 if (s2io_rldram_test(sp, &data[3]))
6310 ethtest->flags |= ETH_TEST_FL_FAILED;
6314 if (s2io_eeprom_test(sp, &data[1]))
6315 ethtest->flags |= ETH_TEST_FL_FAILED;
6317 if (s2io_bist_test(sp, &data[4]))
6318 ethtest->flags |= ETH_TEST_FL_FAILED;
6327 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6336 if (s2io_link_test(sp, &data[2]))
6337 ethtest->flags |= ETH_TEST_FL_FAILED;
6346 static void s2io_get_ethtool_stats(struct net_device *dev,
6347 struct ethtool_stats *estats,
6351 struct s2io_nic *sp = netdev_priv(dev);
6352 struct stat_block *stat_info = sp->mac_control.stats_info;
6354 s2io_updt_stats(sp);
6356 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6357 le32_to_cpu(stat_info->tmac_frms);
6359 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6360 le32_to_cpu(stat_info->tmac_data_octets);
6361 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
6363 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6364 le32_to_cpu(stat_info->tmac_mcst_frms);
6366 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6367 le32_to_cpu(stat_info->tmac_bcst_frms);
6368 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
6370 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6371 le32_to_cpu(stat_info->tmac_ttl_octets);
6373 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6374 le32_to_cpu(stat_info->tmac_ucst_frms);
6376 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6377 le32_to_cpu(stat_info->tmac_nucst_frms);
6379 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6380 le32_to_cpu(stat_info->tmac_any_err_frms);
6381 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
6382 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
6384 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6385 le32_to_cpu(stat_info->tmac_vld_ip);
6387 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6388 le32_to_cpu(stat_info->tmac_drop_ip);
6390 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6391 le32_to_cpu(stat_info->tmac_icmp);
6393 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6394 le32_to_cpu(stat_info->tmac_rst_tcp);
6395 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6396 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6397 le32_to_cpu(stat_info->tmac_udp);
6399 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6400 le32_to_cpu(stat_info->rmac_vld_frms);
6402 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6403 le32_to_cpu(stat_info->rmac_data_octets);
6404 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6405 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6407 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6408 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6410 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6411 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6412 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6413 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6414 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6415 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6416 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6418 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6419 le32_to_cpu(stat_info->rmac_ttl_octets);
6421 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow) << 32
6422 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6424 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6425 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6427 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6428 le32_to_cpu(stat_info->rmac_discarded_frms);
6430 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6431 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6432 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6433 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6435 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6436 le32_to_cpu(stat_info->rmac_usized_frms);
6438 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6439 le32_to_cpu(stat_info->rmac_osized_frms);
6441 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6442 le32_to_cpu(stat_info->rmac_frag_frms);
6444 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6445 le32_to_cpu(stat_info->rmac_jabber_frms);
6446 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6447 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6448 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6449 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6450 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6451 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6453 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6454 le32_to_cpu(stat_info->rmac_ip);
6455 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6456 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6458 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6459 le32_to_cpu(stat_info->rmac_drop_ip);
6461 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6462 le32_to_cpu(stat_info->rmac_icmp);
6463 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6465 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6466 le32_to_cpu(stat_info->rmac_udp);
6468 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6469 le32_to_cpu(stat_info->rmac_err_drp_udp);
6470 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6471 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6472 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6473 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6474 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6475 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6476 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6477 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6478 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6479 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6480 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6481 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6482 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6483 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6484 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6485 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6486 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6488 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6489 le32_to_cpu(stat_info->rmac_pause_cnt);
6490 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6491 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6493 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6494 le32_to_cpu(stat_info->rmac_accepted_ip);
6495 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6496 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6511 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6512 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6513 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6515 /* Enhanced statistics exist only for Hercules */
6516 if (sp->device_type == XFRAME_II_DEVICE) {
6518 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6520 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6522 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6523 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6524 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6525 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6526 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6527 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6528 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6529 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6530 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6531 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6532 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6533 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6534 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6535 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6539 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6540 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6541 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6543 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6544 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6545 for (k = 0; k < MAX_RX_RINGS; k++)
6546 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6547 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6548 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6549 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6550 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6551 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6552 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6553 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6554 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6555 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6556 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6557 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6558 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6559 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6561 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6562 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6563 if (stat_info->sw_stat.num_aggregations) {
6564 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6567 * Since 64-bit divide does not work on all platforms,
6568 * do repeated subtraction.
6570 while (tmp >= stat_info->sw_stat.num_aggregations) {
6571 tmp -= stat_info->sw_stat.num_aggregations;
6574 tmp_stats[i++] = count;
6577 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6578 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6579 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6580 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6581 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6582 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6583 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6584 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6585 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6587 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6588 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6589 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6590 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6591 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6593 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6594 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6595 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6596 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6597 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6598 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6599 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6600 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6601 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6602 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6603 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6604 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6605 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6606 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6607 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6608 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6609 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6610 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6611 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6612 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6613 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6614 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6615 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6616 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6617 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6618 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6621 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6623 return XENA_REG_SPACE;
6627 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6629 struct s2io_nic *sp = netdev_priv(dev);
6634 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6636 struct s2io_nic *sp = netdev_priv(dev);
6646 static int s2io_get_eeprom_len(struct net_device *dev)
6648 return XENA_EEPROM_SPACE;
6651 static int s2io_get_sset_count(struct net_device *dev, int sset)
6653 struct s2io_nic *sp = netdev_priv(dev);
6657 return S2IO_TEST_LEN;
6659 switch (sp->device_type) {
6660 case XFRAME_I_DEVICE:
6661 return XFRAME_I_STAT_LEN;
6662 case XFRAME_II_DEVICE:
6663 return XFRAME_II_STAT_LEN;
6672 static void s2io_ethtool_get_strings(struct net_device *dev,
6673 u32 stringset, u8 *data)
6676 struct s2io_nic *sp = netdev_priv(dev);
6678 switch (stringset) {
6680 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6683 stat_size = sizeof(ethtool_xena_stats_keys);
6684 memcpy(data, ðtool_xena_stats_keys, stat_size);
6685 if (sp->device_type == XFRAME_II_DEVICE) {
6686 memcpy(data + stat_size,
6687 ðtool_enhanced_stats_keys,
6688 sizeof(ethtool_enhanced_stats_keys));
6689 stat_size += sizeof(ethtool_enhanced_stats_keys);
6692 memcpy(data + stat_size, ðtool_driver_stats_keys,
6693 sizeof(ethtool_driver_stats_keys));
6697 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6700 dev->features |= NETIF_F_IP_CSUM;
6702 dev->features &= ~NETIF_F_IP_CSUM;
6707 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6709 return (dev->features & NETIF_F_TSO) != 0;
6711 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6714 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6716 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6721 static const struct ethtool_ops netdev_ethtool_ops = {
6722 .get_settings = s2io_ethtool_gset,
6723 .set_settings = s2io_ethtool_sset,
6724 .get_drvinfo = s2io_ethtool_gdrvinfo,
6725 .get_regs_len = s2io_ethtool_get_regs_len,
6726 .get_regs = s2io_ethtool_gregs,
6727 .get_link = ethtool_op_get_link,
6728 .get_eeprom_len = s2io_get_eeprom_len,
6729 .get_eeprom = s2io_ethtool_geeprom,
6730 .set_eeprom = s2io_ethtool_seeprom,
6731 .get_ringparam = s2io_ethtool_gringparam,
6732 .get_pauseparam = s2io_ethtool_getpause_data,
6733 .set_pauseparam = s2io_ethtool_setpause_data,
6734 .get_rx_csum = s2io_ethtool_get_rx_csum,
6735 .set_rx_csum = s2io_ethtool_set_rx_csum,
6736 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6737 .set_sg = ethtool_op_set_sg,
6738 .get_tso = s2io_ethtool_op_get_tso,
6739 .set_tso = s2io_ethtool_op_set_tso,
6740 .set_ufo = ethtool_op_set_ufo,
6741 .self_test = s2io_ethtool_test,
6742 .get_strings = s2io_ethtool_get_strings,
6743 .phys_id = s2io_ethtool_idnic,
6744 .get_ethtool_stats = s2io_get_ethtool_stats,
6745 .get_sset_count = s2io_get_sset_count,
6749 * s2io_ioctl - Entry point for the Ioctl
6750 * @dev : Device pointer.
6751 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6752 * a proprietary structure used to pass information to the driver.
6753 * @cmd : This is used to distinguish between the different commands that
6754 * can be passed to the IOCTL functions.
6756 * Currently there are no special functionality supported in IOCTL, hence
6757 * function always return EOPNOTSUPPORTED
6760 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6766 * s2io_change_mtu - entry point to change MTU size for the device.
6767 * @dev : device pointer.
6768 * @new_mtu : the new MTU size for the device.
6769 * Description: A driver entry point to change MTU size for the device.
6770 * Before changing the MTU the device must be stopped.
6772 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6776 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6778 struct s2io_nic *sp = netdev_priv(dev);
6781 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6782 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6787 if (netif_running(dev)) {
6788 s2io_stop_all_tx_queue(sp);
6790 ret = s2io_card_up(sp);
6792 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6796 s2io_wake_all_tx_queue(sp);
6797 } else { /* Device is down */
6798 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6799 u64 val64 = new_mtu;
6801 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6808 * s2io_set_link - Set the LInk status
6809 * @data: long pointer to device private structue
6810 * Description: Sets the link status for the adapter
6813 static void s2io_set_link(struct work_struct *work)
6815 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6817 struct net_device *dev = nic->dev;
6818 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6824 if (!netif_running(dev))
6827 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6828 /* The card is being reset, no point doing anything */
6832 subid = nic->pdev->subsystem_device;
6833 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6835 * Allow a small delay for the NICs self initiated
6836 * cleanup to complete.
6841 val64 = readq(&bar0->adapter_status);
6842 if (LINK_IS_UP(val64)) {
6843 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6844 if (verify_xena_quiescence(nic)) {
6845 val64 = readq(&bar0->adapter_control);
6846 val64 |= ADAPTER_CNTL_EN;
6847 writeq(val64, &bar0->adapter_control);
6848 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6849 nic->device_type, subid)) {
6850 val64 = readq(&bar0->gpio_control);
6851 val64 |= GPIO_CTRL_GPIO_0;
6852 writeq(val64, &bar0->gpio_control);
6853 val64 = readq(&bar0->gpio_control);
6855 val64 |= ADAPTER_LED_ON;
6856 writeq(val64, &bar0->adapter_control);
6858 nic->device_enabled_once = true;
6860 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6861 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6862 s2io_stop_all_tx_queue(nic);
6865 val64 = readq(&bar0->adapter_control);
6866 val64 |= ADAPTER_LED_ON;
6867 writeq(val64, &bar0->adapter_control);
6868 s2io_link(nic, LINK_UP);
6870 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6872 val64 = readq(&bar0->gpio_control);
6873 val64 &= ~GPIO_CTRL_GPIO_0;
6874 writeq(val64, &bar0->gpio_control);
6875 val64 = readq(&bar0->gpio_control);
6878 val64 = readq(&bar0->adapter_control);
6879 val64 = val64 & (~ADAPTER_LED_ON);
6880 writeq(val64, &bar0->adapter_control);
6881 s2io_link(nic, LINK_DOWN);
6883 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6889 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6891 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6892 u64 *temp2, int size)
6894 struct net_device *dev = sp->dev;
6895 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6897 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6898 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6901 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6903 * As Rx frame are not going to be processed,
6904 * using same mapped address for the Rxd
6907 rxdp1->Buffer0_ptr = *temp0;
6909 *skb = dev_alloc_skb(size);
6911 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6912 DBG_PRINT(INFO_DBG, "memory to allocate ");
6913 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6914 sp->mac_control.stats_info->sw_stat.
6915 mem_alloc_fail_cnt++;
6918 sp->mac_control.stats_info->sw_stat.mem_allocated
6919 += (*skb)->truesize;
6920 /* storing the mapped addr in a temp variable
6921 * such it will be used for next rxd whose
6922 * Host Control is NULL
6924 rxdp1->Buffer0_ptr = *temp0 =
6925 pci_map_single(sp->pdev, (*skb)->data,
6926 size - NET_IP_ALIGN,
6927 PCI_DMA_FROMDEVICE);
6928 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6929 goto memalloc_failed;
6930 rxdp->Host_Control = (unsigned long) (*skb);
6932 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6933 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6934 /* Two buffer Mode */
6936 rxdp3->Buffer2_ptr = *temp2;
6937 rxdp3->Buffer0_ptr = *temp0;
6938 rxdp3->Buffer1_ptr = *temp1;
6940 *skb = dev_alloc_skb(size);
6942 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6943 DBG_PRINT(INFO_DBG, "memory to allocate ");
6944 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6945 sp->mac_control.stats_info->sw_stat.
6946 mem_alloc_fail_cnt++;
6949 sp->mac_control.stats_info->sw_stat.mem_allocated
6950 += (*skb)->truesize;
6951 rxdp3->Buffer2_ptr = *temp2 =
6952 pci_map_single(sp->pdev, (*skb)->data,
6954 PCI_DMA_FROMDEVICE);
6955 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6956 goto memalloc_failed;
6957 rxdp3->Buffer0_ptr = *temp0 =
6958 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6959 PCI_DMA_FROMDEVICE);
6960 if (pci_dma_mapping_error(sp->pdev,
6961 rxdp3->Buffer0_ptr)) {
6962 pci_unmap_single(sp->pdev,
6963 (dma_addr_t)rxdp3->Buffer2_ptr,
6965 PCI_DMA_FROMDEVICE);
6966 goto memalloc_failed;
6968 rxdp->Host_Control = (unsigned long) (*skb);
6970 /* Buffer-1 will be dummy buffer not used */
6971 rxdp3->Buffer1_ptr = *temp1 =
6972 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6973 PCI_DMA_FROMDEVICE);
6974 if (pci_dma_mapping_error(sp->pdev,
6975 rxdp3->Buffer1_ptr)) {
6976 pci_unmap_single(sp->pdev,
6977 (dma_addr_t)rxdp3->Buffer0_ptr,
6978 BUF0_LEN, PCI_DMA_FROMDEVICE);
6979 pci_unmap_single(sp->pdev,
6980 (dma_addr_t)rxdp3->Buffer2_ptr,
6982 PCI_DMA_FROMDEVICE);
6983 goto memalloc_failed;
6990 stats->pci_map_fail_cnt++;
6991 stats->mem_freed += (*skb)->truesize;
6992 dev_kfree_skb(*skb);
6996 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6999 struct net_device *dev = sp->dev;
7000 if (sp->rxd_mode == RXD_MODE_1) {
7001 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
7002 } else if (sp->rxd_mode == RXD_MODE_3B) {
7003 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7004 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
7005 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
7009 static int rxd_owner_bit_reset(struct s2io_nic *sp)
7011 int i, j, k, blk_cnt = 0, size;
7012 struct mac_info *mac_control = &sp->mac_control;
7013 struct config_param *config = &sp->config;
7014 struct net_device *dev = sp->dev;
7015 struct RxD_t *rxdp = NULL;
7016 struct sk_buff *skb = NULL;
7017 struct buffAdd *ba = NULL;
7018 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7020 /* Calculate the size based on ring mode */
7021 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7022 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7023 if (sp->rxd_mode == RXD_MODE_1)
7024 size += NET_IP_ALIGN;
7025 else if (sp->rxd_mode == RXD_MODE_3B)
7026 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
7028 for (i = 0; i < config->rx_ring_num; i++) {
7029 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7030 struct ring_info *ring = &mac_control->rings[i];
7032 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
7034 for (j = 0; j < blk_cnt; j++) {
7035 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7036 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7037 if (sp->rxd_mode == RXD_MODE_3B)
7038 ba = &ring->ba[j][k];
7039 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7047 set_rxd_buffer_size(sp, rxdp, size);
7049 /* flip the Ownership bit to Hardware */
7050 rxdp->Control_1 |= RXD_OWN_XENA;
7058 static int s2io_add_isr(struct s2io_nic *sp)
7061 struct net_device *dev = sp->dev;
7064 if (sp->config.intr_type == MSI_X)
7065 ret = s2io_enable_msi_x(sp);
7067 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7068 sp->config.intr_type = INTA;
7072 * Store the values of the MSIX table in
7073 * the struct s2io_nic structure
7075 store_xmsi_data(sp);
7077 /* After proper initialization of H/W, register ISR */
7078 if (sp->config.intr_type == MSI_X) {
7079 int i, msix_rx_cnt = 0;
7081 for (i = 0; i < sp->num_entries; i++) {
7082 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7083 if (sp->s2io_entries[i].type ==
7085 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7087 err = request_irq(sp->entries[i].vector,
7088 s2io_msix_ring_handle,
7091 sp->s2io_entries[i].arg);
7092 } else if (sp->s2io_entries[i].type ==
7094 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7096 err = request_irq(sp->entries[i].vector,
7097 s2io_msix_fifo_handle,
7100 sp->s2io_entries[i].arg);
7103 /* if either data or addr is zero print it. */
7104 if (!(sp->msix_info[i].addr &&
7105 sp->msix_info[i].data)) {
7107 "%s @Addr:0x%llx Data:0x%llx\n",
7109 (unsigned long long)
7110 sp->msix_info[i].addr,
7111 (unsigned long long)
7112 ntohl(sp->msix_info[i].data));
7116 remove_msix_isr(sp);
7119 "%s:MSI-X-%d registration "
7120 "failed\n", dev->name, i);
7123 "%s: Defaulting to INTA\n",
7125 sp->config.intr_type = INTA;
7128 sp->s2io_entries[i].in_use =
7129 MSIX_REGISTERED_SUCCESS;
7133 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7135 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7136 " through alarm vector\n");
7139 if (sp->config.intr_type == INTA) {
7140 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7143 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7151 static void s2io_rem_isr(struct s2io_nic *sp)
7153 if (sp->config.intr_type == MSI_X)
7154 remove_msix_isr(sp);
7156 remove_inta_isr(sp);
7159 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7162 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7163 register u64 val64 = 0;
7164 struct config_param *config;
7165 config = &sp->config;
7167 if (!is_s2io_card_up(sp))
7170 del_timer_sync(&sp->alarm_timer);
7171 /* If s2io_set_link task is executing, wait till it completes. */
7172 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7174 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7177 if (sp->config.napi) {
7179 if (config->intr_type == MSI_X) {
7180 for (; off < sp->config.rx_ring_num; off++)
7181 napi_disable(&sp->mac_control.rings[off].napi);
7184 napi_disable(&sp->napi);
7187 /* disable Tx and Rx traffic on the NIC */
7193 /* stop the tx queue, indicate link down */
7194 s2io_link(sp, LINK_DOWN);
7196 /* Check if the device is Quiescent and then Reset the NIC */
7198 /* As per the HW requirement we need to replenish the
7199 * receive buffer to avoid the ring bump. Since there is
7200 * no intention of processing the Rx frame at this pointwe are
7201 * just settting the ownership bit of rxd in Each Rx
7202 * ring to HW and set the appropriate buffer size
7203 * based on the ring mode
7205 rxd_owner_bit_reset(sp);
7207 val64 = readq(&bar0->adapter_status);
7208 if (verify_xena_quiescence(sp)) {
7209 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7216 DBG_PRINT(ERR_DBG, "s2io_close:Device not Quiescent ");
7217 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7218 (unsigned long long)val64);
7225 /* Free all Tx buffers */
7226 free_tx_buffers(sp);
7228 /* Free all Rx buffers */
7229 free_rx_buffers(sp);
7231 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7234 static void s2io_card_down(struct s2io_nic *sp)
7236 do_s2io_card_down(sp, 1);
7239 static int s2io_card_up(struct s2io_nic *sp)
7242 struct mac_info *mac_control;
7243 struct config_param *config;
7244 struct net_device *dev = (struct net_device *)sp->dev;
7247 /* Initialize the H/W I/O registers */
7250 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7258 * Initializing the Rx buffers. For now we are considering only 1
7259 * Rx ring and initializing buffers into 30 Rx blocks
7261 mac_control = &sp->mac_control;
7262 config = &sp->config;
7264 for (i = 0; i < config->rx_ring_num; i++) {
7265 struct ring_info *ring = &mac_control->rings[i];
7267 ring->mtu = dev->mtu;
7268 ret = fill_rx_buffers(sp, ring, 1);
7270 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7273 free_rx_buffers(sp);
7276 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7277 ring->rx_bufs_left);
7280 /* Initialise napi */
7282 if (config->intr_type == MSI_X) {
7283 for (i = 0; i < sp->config.rx_ring_num; i++)
7284 napi_enable(&sp->mac_control.rings[i].napi);
7286 napi_enable(&sp->napi);
7290 /* Maintain the state prior to the open */
7291 if (sp->promisc_flg)
7292 sp->promisc_flg = 0;
7293 if (sp->m_cast_flg) {
7295 sp->all_multi_pos = 0;
7298 /* Setting its receive mode */
7299 s2io_set_multicast(dev);
7302 /* Initialize max aggregatable pkts per session based on MTU */
7303 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7304 /* Check if we can use (if specified) user provided value */
7305 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7306 sp->lro_max_aggr_per_sess = lro_max_pkts;
7309 /* Enable Rx Traffic and interrupts on the NIC */
7310 if (start_nic(sp)) {
7311 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7313 free_rx_buffers(sp);
7317 /* Add interrupt service routine */
7318 if (s2io_add_isr(sp) != 0) {
7319 if (sp->config.intr_type == MSI_X)
7322 free_rx_buffers(sp);
7326 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7328 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7330 /* Enable select interrupts */
7331 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7332 if (sp->config.intr_type != INTA) {
7333 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7334 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7336 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7337 interruptible |= TX_PIC_INTR;
7338 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7345 * s2io_restart_nic - Resets the NIC.
7346 * @data : long pointer to the device private structure
7348 * This function is scheduled to be run by the s2io_tx_watchdog
7349 * function after 0.5 secs to reset the NIC. The idea is to reduce
7350 * the run time of the watch dog routine which is run holding a
7354 static void s2io_restart_nic(struct work_struct *work)
7356 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7357 struct net_device *dev = sp->dev;
7361 if (!netif_running(dev))
7365 if (s2io_card_up(sp)) {
7366 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7368 s2io_wake_all_tx_queue(sp);
7369 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7375 * s2io_tx_watchdog - Watchdog for transmit side.
7376 * @dev : Pointer to net device structure
7378 * This function is triggered if the Tx Queue is stopped
7379 * for a pre-defined amount of time when the Interface is still up.
7380 * If the Interface is jammed in such a situation, the hardware is
7381 * reset (by s2io_close) and restarted again (by s2io_open) to
7382 * overcome any problem that might have been caused in the hardware.
7387 static void s2io_tx_watchdog(struct net_device *dev)
7389 struct s2io_nic *sp = netdev_priv(dev);
7391 if (netif_carrier_ok(dev)) {
7392 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7393 schedule_work(&sp->rst_timer_task);
7394 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7399 * rx_osm_handler - To perform some OS related operations on SKB.
7400 * @sp: private member of the device structure,pointer to s2io_nic structure.
7401 * @skb : the socket buffer pointer.
7402 * @len : length of the packet
7403 * @cksum : FCS checksum of the frame.
7404 * @ring_no : the ring from which this RxD was extracted.
7406 * This function is called by the Rx interrupt serivce routine to perform
7407 * some OS related operations on the SKB before passing it to the upper
7408 * layers. It mainly checks if the checksum is OK, if so adds it to the
7409 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7410 * to the upper layer. If the checksum is wrong, it increments the Rx
7411 * packet error count, frees the SKB and returns error.
7413 * SUCCESS on success and -1 on failure.
7415 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7417 struct s2io_nic *sp = ring_data->nic;
7418 struct net_device *dev = (struct net_device *)ring_data->dev;
7419 struct sk_buff *skb = (struct sk_buff *)
7420 ((unsigned long)rxdp->Host_Control);
7421 int ring_no = ring_data->ring_no;
7422 u16 l3_csum, l4_csum;
7423 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7424 struct lro *uninitialized_var(lro);
7430 /* Check for parity error */
7432 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7434 err_mask = err >> 48;
7437 sp->mac_control.stats_info->sw_stat.rx_parity_err_cnt++;
7441 sp->mac_control.stats_info->sw_stat.rx_abort_cnt++;
7445 sp->mac_control.stats_info->sw_stat.rx_parity_abort_cnt++;
7449 sp->mac_control.stats_info->sw_stat.rx_rda_fail_cnt++;
7453 sp->mac_control.stats_info->sw_stat.rx_unkn_prot_cnt++;
7457 sp->mac_control.stats_info->sw_stat.rx_fcs_err_cnt++;
7461 sp->mac_control.stats_info->sw_stat.rx_buf_size_err_cnt++;
7465 sp->mac_control.stats_info->sw_stat.rx_rxd_corrupt_cnt++;
7469 sp->mac_control.stats_info->sw_stat.rx_unkn_err_cnt++;
7473 * Drop the packet if bad transfer code. Exception being
7474 * 0x5, which could be due to unsupported IPv6 extension header.
7475 * In this case, we let stack handle the packet.
7476 * Note that in this case, since checksum will be incorrect,
7477 * stack will validate the same.
7479 if (err_mask != 0x5) {
7480 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7481 dev->name, err_mask);
7482 dev->stats.rx_crc_errors++;
7483 sp->mac_control.stats_info->sw_stat.mem_freed
7486 ring_data->rx_bufs_left -= 1;
7487 rxdp->Host_Control = 0;
7492 /* Updating statistics */
7493 ring_data->rx_packets++;
7494 rxdp->Host_Control = 0;
7495 if (sp->rxd_mode == RXD_MODE_1) {
7496 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7498 ring_data->rx_bytes += len;
7501 } else if (sp->rxd_mode == RXD_MODE_3B) {
7502 int get_block = ring_data->rx_curr_get_info.block_index;
7503 int get_off = ring_data->rx_curr_get_info.offset;
7504 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7505 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7506 unsigned char *buff = skb_push(skb, buf0_len);
7508 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7509 ring_data->rx_bytes += buf0_len + buf2_len;
7510 memcpy(buff, ba->ba_0, buf0_len);
7511 skb_put(skb, buf2_len);
7514 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7515 ((!ring_data->lro) ||
7516 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7518 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7519 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7520 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7522 * NIC verifies if the Checksum of the received
7523 * frame is Ok or not and accordingly returns
7524 * a flag in the RxD.
7526 skb->ip_summed = CHECKSUM_UNNECESSARY;
7527 if (ring_data->lro) {
7532 ret = s2io_club_tcp_session(ring_data,
7537 case 3: /* Begin anew */
7540 case 1: /* Aggregate */
7541 lro_append_pkt(sp, lro, skb, tcp_len);
7543 case 4: /* Flush session */
7544 lro_append_pkt(sp, lro, skb, tcp_len);
7545 queue_rx_frame(lro->parent,
7547 clear_lro_session(lro);
7548 sp->mac_control.stats_info->
7549 sw_stat.flush_max_pkts++;
7551 case 2: /* Flush both */
7552 lro->parent->data_len = lro->frags_len;
7553 sp->mac_control.stats_info->
7554 sw_stat.sending_both++;
7555 queue_rx_frame(lro->parent,
7557 clear_lro_session(lro);
7559 case 0: /* sessions exceeded */
7560 case -1: /* non-TCP or not L2 aggregatable */
7562 * First pkt in session not
7563 * L3/L4 aggregatable
7568 "%s: Samadhana!!\n",
7575 * Packet with erroneous checksum, let the
7576 * upper layers deal with it.
7578 skb->ip_summed = CHECKSUM_NONE;
7581 skb->ip_summed = CHECKSUM_NONE;
7583 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7585 skb_record_rx_queue(skb, ring_no);
7586 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7588 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7593 * s2io_link - stops/starts the Tx queue.
7594 * @sp : private member of the device structure, which is a pointer to the
7595 * s2io_nic structure.
7596 * @link : inidicates whether link is UP/DOWN.
7598 * This function stops/starts the Tx queue depending on whether the link
7599 * status of the NIC is is down or up. This is called by the Alarm
7600 * interrupt handler whenever a link change interrupt comes up.
7605 static void s2io_link(struct s2io_nic *sp, int link)
7607 struct net_device *dev = (struct net_device *)sp->dev;
7609 if (link != sp->last_link_state) {
7611 if (link == LINK_DOWN) {
7612 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7613 s2io_stop_all_tx_queue(sp);
7614 netif_carrier_off(dev);
7615 if (sp->mac_control.stats_info->sw_stat.link_up_cnt)
7616 sp->mac_control.stats_info->sw_stat.
7617 link_up_time = jiffies - sp->start_time;
7618 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7620 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7621 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7622 sp->mac_control.stats_info->
7623 sw_stat.link_down_time =
7624 jiffies - sp->start_time;
7625 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7626 netif_carrier_on(dev);
7627 s2io_wake_all_tx_queue(sp);
7630 sp->last_link_state = link;
7631 sp->start_time = jiffies;
7635 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7636 * @sp : private member of the device structure, which is a pointer to the
7637 * s2io_nic structure.
7639 * This function initializes a few of the PCI and PCI-X configuration registers
7640 * with recommended values.
7645 static void s2io_init_pci(struct s2io_nic *sp)
7647 u16 pci_cmd = 0, pcix_cmd = 0;
7649 /* Enable Data Parity Error Recovery in PCI-X command register. */
7650 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7652 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7654 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7657 /* Set the PErr Response bit in PCI command register. */
7658 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7659 pci_write_config_word(sp->pdev, PCI_COMMAND,
7660 (pci_cmd | PCI_COMMAND_PARITY));
7661 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7664 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7667 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7668 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7669 "(%d) not supported\n", tx_fifo_num);
7671 if (tx_fifo_num < 1)
7674 tx_fifo_num = MAX_TX_FIFOS;
7676 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7677 DBG_PRINT(ERR_DBG, "tx fifos\n");
7681 *dev_multiq = multiq;
7683 if (tx_steering_type && (1 == tx_fifo_num)) {
7684 if (tx_steering_type != TX_DEFAULT_STEERING)
7686 "s2io: Tx steering is not supported with "
7687 "one fifo. Disabling Tx steering.\n");
7688 tx_steering_type = NO_STEERING;
7691 if ((tx_steering_type < NO_STEERING) ||
7692 (tx_steering_type > TX_DEFAULT_STEERING)) {
7694 "s2io: Requested transmit steering not supported\n");
7695 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7696 tx_steering_type = NO_STEERING;
7699 if (rx_ring_num > MAX_RX_RINGS) {
7701 "s2io: Requested number of rx rings not supported\n");
7702 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7704 rx_ring_num = MAX_RX_RINGS;
7707 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7708 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7709 "Defaulting to INTA\n");
7710 *dev_intr_type = INTA;
7713 if ((*dev_intr_type == MSI_X) &&
7714 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7715 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7716 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7717 "Defaulting to INTA\n");
7718 *dev_intr_type = INTA;
7721 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7722 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7723 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7730 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7731 * or Traffic class respectively.
7732 * @nic: device private variable
7733 * Description: The function configures the receive steering to
7734 * desired receive ring.
7735 * Return Value: SUCCESS on success and
7736 * '-1' on failure (endian settings incorrect).
7738 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7740 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7741 register u64 val64 = 0;
7743 if (ds_codepoint > 63)
7746 val64 = RTS_DS_MEM_DATA(ring);
7747 writeq(val64, &bar0->rts_ds_mem_data);
7749 val64 = RTS_DS_MEM_CTRL_WE |
7750 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7751 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7753 writeq(val64, &bar0->rts_ds_mem_ctrl);
7755 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7756 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7760 static const struct net_device_ops s2io_netdev_ops = {
7761 .ndo_open = s2io_open,
7762 .ndo_stop = s2io_close,
7763 .ndo_get_stats = s2io_get_stats,
7764 .ndo_start_xmit = s2io_xmit,
7765 .ndo_validate_addr = eth_validate_addr,
7766 .ndo_set_multicast_list = s2io_set_multicast,
7767 .ndo_do_ioctl = s2io_ioctl,
7768 .ndo_set_mac_address = s2io_set_mac_addr,
7769 .ndo_change_mtu = s2io_change_mtu,
7770 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7771 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7772 .ndo_tx_timeout = s2io_tx_watchdog,
7773 #ifdef CONFIG_NET_POLL_CONTROLLER
7774 .ndo_poll_controller = s2io_netpoll,
7779 * s2io_init_nic - Initialization of the adapter .
7780 * @pdev : structure containing the PCI related information of the device.
7781 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7783 * The function initializes an adapter identified by the pci_dec structure.
7784 * All OS related initialization including memory and device structure and
7785 * initlaization of the device private variable is done. Also the swapper
7786 * control register is initialized to enable read and write into the I/O
7787 * registers of the device.
7789 * returns 0 on success and negative on failure.
7792 static int __devinit
7793 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7795 struct s2io_nic *sp;
7796 struct net_device *dev;
7798 int dma_flag = false;
7799 u32 mac_up, mac_down;
7800 u64 val64 = 0, tmp64 = 0;
7801 struct XENA_dev_config __iomem *bar0 = NULL;
7803 struct mac_info *mac_control;
7804 struct config_param *config;
7806 u8 dev_intr_type = intr_type;
7809 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7813 ret = pci_enable_device(pdev);
7816 "s2io_init_nic: pci_enable_device failed\n");
7820 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7821 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7823 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7825 "Unable to obtain 64bit DMA "
7826 "for consistent allocations\n");
7827 pci_disable_device(pdev);
7830 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7831 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7833 pci_disable_device(pdev);
7836 ret = pci_request_regions(pdev, s2io_driver_name);
7838 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n",
7840 pci_disable_device(pdev);
7844 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7846 dev = alloc_etherdev(sizeof(struct s2io_nic));
7848 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7849 pci_disable_device(pdev);
7850 pci_release_regions(pdev);
7854 pci_set_master(pdev);
7855 pci_set_drvdata(pdev, dev);
7856 SET_NETDEV_DEV(dev, &pdev->dev);
7858 /* Private member variable initialized to s2io NIC structure */
7859 sp = netdev_priv(dev);
7860 memset(sp, 0, sizeof(struct s2io_nic));
7863 sp->high_dma_flag = dma_flag;
7864 sp->device_enabled_once = false;
7865 if (rx_ring_mode == 1)
7866 sp->rxd_mode = RXD_MODE_1;
7867 if (rx_ring_mode == 2)
7868 sp->rxd_mode = RXD_MODE_3B;
7870 sp->config.intr_type = dev_intr_type;
7872 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7873 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7874 sp->device_type = XFRAME_II_DEVICE;
7876 sp->device_type = XFRAME_I_DEVICE;
7878 sp->lro = lro_enable;
7880 /* Initialize some PCI/PCI-X fields of the NIC. */
7884 * Setting the device configuration parameters.
7885 * Most of these parameters can be specified by the user during
7886 * module insertion as they are module loadable parameters. If
7887 * these parameters are not not specified during load time, they
7888 * are initialized with default values.
7890 mac_control = &sp->mac_control;
7891 config = &sp->config;
7893 config->napi = napi;
7894 config->tx_steering_type = tx_steering_type;
7896 /* Tx side parameters. */
7897 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7898 config->tx_fifo_num = MAX_TX_FIFOS;
7900 config->tx_fifo_num = tx_fifo_num;
7902 /* Initialize the fifos used for tx steering */
7903 if (config->tx_fifo_num < 5) {
7904 if (config->tx_fifo_num == 1)
7905 sp->total_tcp_fifos = 1;
7907 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7908 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7909 sp->total_udp_fifos = 1;
7910 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7912 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7913 FIFO_OTHER_MAX_NUM);
7914 sp->udp_fifo_idx = sp->total_tcp_fifos;
7915 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7916 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7919 config->multiq = dev_multiq;
7920 for (i = 0; i < config->tx_fifo_num; i++) {
7921 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7923 tx_cfg->fifo_len = tx_fifo_len[i];
7924 tx_cfg->fifo_priority = i;
7927 /* mapping the QoS priority to the configured fifos */
7928 for (i = 0; i < MAX_TX_FIFOS; i++)
7929 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7931 /* map the hashing selector table to the configured fifos */
7932 for (i = 0; i < config->tx_fifo_num; i++)
7933 sp->fifo_selector[i] = fifo_selector[i];
7936 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7937 for (i = 0; i < config->tx_fifo_num; i++) {
7938 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7940 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7941 if (tx_cfg->fifo_len < 65) {
7942 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7946 /* + 2 because one Txd for skb->data and one Txd for UFO */
7947 config->max_txds = MAX_SKB_FRAGS + 2;
7949 /* Rx side parameters. */
7950 config->rx_ring_num = rx_ring_num;
7951 for (i = 0; i < config->rx_ring_num; i++) {
7952 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7953 struct ring_info *ring = &mac_control->rings[i];
7955 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7956 rx_cfg->ring_priority = i;
7957 ring->rx_bufs_left = 0;
7958 ring->rxd_mode = sp->rxd_mode;
7959 ring->rxd_count = rxd_count[sp->rxd_mode];
7960 ring->pdev = sp->pdev;
7961 ring->dev = sp->dev;
7964 for (i = 0; i < rx_ring_num; i++) {
7965 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7967 rx_cfg->ring_org = RING_ORG_BUFF1;
7968 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7971 /* Setting Mac Control parameters */
7972 mac_control->rmac_pause_time = rmac_pause_time;
7973 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7974 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7977 /* initialize the shared memory used by the NIC and the host */
7978 if (init_shared_mem(sp)) {
7979 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7981 goto mem_alloc_failed;
7984 sp->bar0 = pci_ioremap_bar(pdev, 0);
7986 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7989 goto bar0_remap_failed;
7992 sp->bar1 = pci_ioremap_bar(pdev, 2);
7994 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7997 goto bar1_remap_failed;
8000 dev->irq = pdev->irq;
8001 dev->base_addr = (unsigned long)sp->bar0;
8003 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8004 for (j = 0; j < MAX_TX_FIFOS; j++) {
8005 mac_control->tx_FIFO_start[j] =
8006 (struct TxFIFO_element __iomem *)
8007 (sp->bar1 + (j * 0x00020000));
8010 /* Driver entry points */
8011 dev->netdev_ops = &s2io_netdev_ops;
8012 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
8013 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8015 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8016 if (sp->high_dma_flag == true)
8017 dev->features |= NETIF_F_HIGHDMA;
8018 dev->features |= NETIF_F_TSO;
8019 dev->features |= NETIF_F_TSO6;
8020 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
8021 dev->features |= NETIF_F_UFO;
8022 dev->features |= NETIF_F_HW_CSUM;
8024 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
8025 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8026 INIT_WORK(&sp->set_link_task, s2io_set_link);
8028 pci_save_state(sp->pdev);
8030 /* Setting swapper control on the NIC, for proper reset operation */
8031 if (s2io_set_swapper(sp)) {
8032 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
8035 goto set_swap_failed;
8038 /* Verify if the Herc works on the slot its placed into */
8039 if (sp->device_type & XFRAME_II_DEVICE) {
8040 mode = s2io_verify_pci_mode(sp);
8042 DBG_PRINT(ERR_DBG, "%s: ", __func__);
8043 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8045 goto set_swap_failed;
8049 if (sp->config.intr_type == MSI_X) {
8050 sp->num_entries = config->rx_ring_num + 1;
8051 ret = s2io_enable_msi_x(sp);
8054 ret = s2io_test_msi(sp);
8055 /* rollback MSI-X, will re-enable during add_isr() */
8056 remove_msix_isr(sp);
8061 "s2io: MSI-X requested but failed to enable\n");
8062 sp->config.intr_type = INTA;
8066 if (config->intr_type == MSI_X) {
8067 for (i = 0; i < config->rx_ring_num ; i++) {
8068 struct ring_info *ring = &mac_control->rings[i];
8070 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8073 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8076 /* Not needed for Herc */
8077 if (sp->device_type & XFRAME_I_DEVICE) {
8079 * Fix for all "FFs" MAC address problems observed on
8082 fix_mac_address(sp);
8087 * MAC address initialization.
8088 * For now only one mac address will be read and used.
8091 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8092 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8093 writeq(val64, &bar0->rmac_addr_cmd_mem);
8094 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8095 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8097 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8098 mac_down = (u32)tmp64;
8099 mac_up = (u32) (tmp64 >> 32);
8101 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8102 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8103 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8104 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8105 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8106 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8108 /* Set the factory defined MAC address initially */
8109 dev->addr_len = ETH_ALEN;
8110 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8111 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8113 /* initialize number of multicast & unicast MAC entries variables */
8114 if (sp->device_type == XFRAME_I_DEVICE) {
8115 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8116 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8117 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8118 } else if (sp->device_type == XFRAME_II_DEVICE) {
8119 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8120 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8121 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8124 /* store mac addresses from CAM to s2io_nic structure */
8125 do_s2io_store_unicast_mc(sp);
8127 /* Configure MSIX vector for number of rings configured plus one */
8128 if ((sp->device_type == XFRAME_II_DEVICE) &&
8129 (config->intr_type == MSI_X))
8130 sp->num_entries = config->rx_ring_num + 1;
8132 /* Store the values of the MSIX table in the s2io_nic structure */
8133 store_xmsi_data(sp);
8134 /* reset Nic and bring it to known state */
8138 * Initialize link state flags
8139 * and the card state parameter
8143 /* Initialize spinlocks */
8144 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8145 struct fifo_info *fifo = &mac_control->fifos[i];
8147 spin_lock_init(&fifo->tx_lock);
8151 * SXE-002: Configure link and activity LED to init state
8154 subid = sp->pdev->subsystem_device;
8155 if ((subid & 0xFF) >= 0x07) {
8156 val64 = readq(&bar0->gpio_control);
8157 val64 |= 0x0000800000000000ULL;
8158 writeq(val64, &bar0->gpio_control);
8159 val64 = 0x0411040400000000ULL;
8160 writeq(val64, (void __iomem *)bar0 + 0x2700);
8161 val64 = readq(&bar0->gpio_control);
8164 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8166 if (register_netdev(dev)) {
8167 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8169 goto register_failed;
8172 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8173 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8174 sp->product_name, pdev->revision);
8175 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8176 s2io_driver_version);
8177 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
8178 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
8179 if (sp->device_type & XFRAME_II_DEVICE) {
8180 mode = s2io_print_pci_mode(sp);
8182 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8184 unregister_netdev(dev);
8185 goto set_swap_failed;
8188 switch (sp->rxd_mode) {
8190 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8194 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8199 switch (sp->config.napi) {
8201 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8204 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8208 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8209 sp->config.tx_fifo_num);
8211 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8212 sp->config.rx_ring_num);
8214 switch (sp->config.intr_type) {
8216 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8219 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8222 if (sp->config.multiq) {
8223 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8224 struct fifo_info *fifo = &mac_control->fifos[i];
8226 fifo->multiq = config->multiq;
8228 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8231 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8234 switch (sp->config.tx_steering_type) {
8236 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8239 case TX_PRIORITY_STEERING:
8241 "%s: Priority steering enabled for transmit\n",
8244 case TX_DEFAULT_STEERING:
8246 "%s: Default steering enabled for transmit\n",
8251 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8255 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8257 /* Initialize device name */
8258 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8261 sp->vlan_strip_flag = 1;
8263 sp->vlan_strip_flag = 0;
8266 * Make Link state as off at this point, when the Link change
8267 * interrupt comes the state will be automatically changed to
8270 netif_carrier_off(dev);
8281 free_shared_mem(sp);
8282 pci_disable_device(pdev);
8283 pci_release_regions(pdev);
8284 pci_set_drvdata(pdev, NULL);
8291 * s2io_rem_nic - Free the PCI device
8292 * @pdev: structure containing the PCI related information of the device.
8293 * Description: This function is called by the Pci subsystem to release a
8294 * PCI device and free up all resource held up by the device. This could
8295 * be in response to a Hot plug event or when the driver is to be removed
8299 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8301 struct net_device *dev =
8302 (struct net_device *)pci_get_drvdata(pdev);
8303 struct s2io_nic *sp;
8306 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8310 flush_scheduled_work();
8312 sp = netdev_priv(dev);
8313 unregister_netdev(dev);
8315 free_shared_mem(sp);
8318 pci_release_regions(pdev);
8319 pci_set_drvdata(pdev, NULL);
8321 pci_disable_device(pdev);
8325 * s2io_starter - Entry point for the driver
8326 * Description: This function is the entry point for the driver. It verifies
8327 * the module loadable parameters and initializes PCI configuration space.
8330 static int __init s2io_starter(void)
8332 return pci_register_driver(&s2io_driver);
8336 * s2io_closer - Cleanup routine for the driver
8337 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8340 static __exit void s2io_closer(void)
8342 pci_unregister_driver(&s2io_driver);
8343 DBG_PRINT(INIT_DBG, "cleanup done\n");
8346 module_init(s2io_starter);
8347 module_exit(s2io_closer);
8349 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8350 struct tcphdr **tcp, struct RxD_t *rxdp,
8351 struct s2io_nic *sp)
8354 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8356 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8358 "%s: Non-TCP frames not supported for LRO\n",
8363 /* Checking for DIX type or DIX type with VLAN */
8364 if ((l2_type == 0) || (l2_type == 4)) {
8365 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8367 * If vlan stripping is disabled and the frame is VLAN tagged,
8368 * shift the offset by the VLAN header size bytes.
8370 if ((!sp->vlan_strip_flag) &&
8371 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8372 ip_off += HEADER_VLAN_SIZE;
8374 /* LLC, SNAP etc are considered non-mergeable */
8378 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8379 ip_len = (u8)((*ip)->ihl);
8381 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8386 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8389 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8390 if ((lro->iph->saddr != ip->saddr) ||
8391 (lro->iph->daddr != ip->daddr) ||
8392 (lro->tcph->source != tcp->source) ||
8393 (lro->tcph->dest != tcp->dest))
8398 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8400 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8403 static void initiate_new_session(struct lro *lro, u8 *l2h,
8404 struct iphdr *ip, struct tcphdr *tcp,
8405 u32 tcp_pyld_len, u16 vlan_tag)
8407 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8411 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8412 lro->tcp_ack = tcp->ack_seq;
8414 lro->total_len = ntohs(ip->tot_len);
8416 lro->vlan_tag = vlan_tag;
8418 * Check if we saw TCP timestamp.
8419 * Other consistency checks have already been done.
8421 if (tcp->doff == 8) {
8423 ptr = (__be32 *)(tcp+1);
8425 lro->cur_tsval = ntohl(*(ptr+1));
8426 lro->cur_tsecr = *(ptr+2);
8431 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8433 struct iphdr *ip = lro->iph;
8434 struct tcphdr *tcp = lro->tcph;
8436 struct stat_block *statinfo = sp->mac_control.stats_info;
8437 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8439 /* Update L3 header */
8440 ip->tot_len = htons(lro->total_len);
8442 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8445 /* Update L4 header */
8446 tcp->ack_seq = lro->tcp_ack;
8447 tcp->window = lro->window;
8449 /* Update tsecr field if this session has timestamps enabled */
8451 __be32 *ptr = (__be32 *)(tcp + 1);
8452 *(ptr+2) = lro->cur_tsecr;
8455 /* Update counters required for calculation of
8456 * average no. of packets aggregated.
8458 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8459 statinfo->sw_stat.num_aggregations++;
8462 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8463 struct tcphdr *tcp, u32 l4_pyld)
8465 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8466 lro->total_len += l4_pyld;
8467 lro->frags_len += l4_pyld;
8468 lro->tcp_next_seq += l4_pyld;
8471 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8472 lro->tcp_ack = tcp->ack_seq;
8473 lro->window = tcp->window;
8477 /* Update tsecr and tsval from this packet */
8478 ptr = (__be32 *)(tcp+1);
8479 lro->cur_tsval = ntohl(*(ptr+1));
8480 lro->cur_tsecr = *(ptr + 2);
8484 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8485 struct tcphdr *tcp, u32 tcp_pyld_len)
8489 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8491 if (!tcp_pyld_len) {
8492 /* Runt frame or a pure ack */
8496 if (ip->ihl != 5) /* IP has options */
8499 /* If we see CE codepoint in IP header, packet is not mergeable */
8500 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8503 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8504 if (tcp->urg || tcp->psh || tcp->rst ||
8505 tcp->syn || tcp->fin ||
8506 tcp->ece || tcp->cwr || !tcp->ack) {
8508 * Currently recognize only the ack control word and
8509 * any other control field being set would result in
8510 * flushing the LRO session
8516 * Allow only one TCP timestamp option. Don't aggregate if
8517 * any other options are detected.
8519 if (tcp->doff != 5 && tcp->doff != 8)
8522 if (tcp->doff == 8) {
8523 ptr = (u8 *)(tcp + 1);
8524 while (*ptr == TCPOPT_NOP)
8526 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8529 /* Ensure timestamp value increases monotonically */
8531 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8534 /* timestamp echo reply should be non-zero */
8535 if (*((__be32 *)(ptr+6)) == 0)
8542 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8543 u8 **tcp, u32 *tcp_len, struct lro **lro,
8544 struct RxD_t *rxdp, struct s2io_nic *sp)
8547 struct tcphdr *tcph;
8551 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8556 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8558 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8559 tcph = (struct tcphdr *)*tcp;
8560 *tcp_len = get_l4_pyld_length(ip, tcph);
8561 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8562 struct lro *l_lro = &ring_data->lro0_n[i];
8563 if (l_lro->in_use) {
8564 if (check_for_socket_match(l_lro, ip, tcph))
8566 /* Sock pair matched */
8569 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8570 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8571 "0x%x, actual 0x%x\n", __func__,
8572 (*lro)->tcp_next_seq,
8575 sp->mac_control.stats_info->
8576 sw_stat.outof_sequence_pkts++;
8581 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8583 ret = 1; /* Aggregate */
8585 ret = 2; /* Flush both */
8591 /* Before searching for available LRO objects,
8592 * check if the pkt is L3/L4 aggregatable. If not
8593 * don't create new LRO session. Just send this
8596 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8599 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8600 struct lro *l_lro = &ring_data->lro0_n[i];
8601 if (!(l_lro->in_use)) {
8603 ret = 3; /* Begin anew */
8609 if (ret == 0) { /* sessions exceeded */
8610 DBG_PRINT(INFO_DBG, "%s:All LRO sessions already in use\n",
8618 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8622 update_L3L4_header(sp, *lro);
8625 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8626 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8627 update_L3L4_header(sp, *lro);
8628 ret = 4; /* Flush the LRO */
8632 DBG_PRINT(ERR_DBG, "%s:Dont know, can't say!!\n", __func__);
8639 static void clear_lro_session(struct lro *lro)
8641 static u16 lro_struct_size = sizeof(struct lro);
8643 memset(lro, 0, lro_struct_size);
8646 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8648 struct net_device *dev = skb->dev;
8649 struct s2io_nic *sp = netdev_priv(dev);
8651 skb->protocol = eth_type_trans(skb, dev);
8652 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8653 /* Queueing the vlan frame to the upper layer */
8654 if (sp->config.napi)
8655 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8657 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8659 if (sp->config.napi)
8660 netif_receive_skb(skb);
8666 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8667 struct sk_buff *skb, u32 tcp_len)
8669 struct sk_buff *first = lro->parent;
8671 first->len += tcp_len;
8672 first->data_len = lro->frags_len;
8673 skb_pull(skb, (skb->len - tcp_len));
8674 if (skb_shinfo(first)->frag_list)
8675 lro->last_frag->next = skb;
8677 skb_shinfo(first)->frag_list = skb;
8678 first->truesize += skb->truesize;
8679 lro->last_frag = skb;
8680 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8685 * s2io_io_error_detected - called when PCI error is detected
8686 * @pdev: Pointer to PCI device
8687 * @state: The current pci connection state
8689 * This function is called after a PCI bus error affecting
8690 * this device has been detected.
8692 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8693 pci_channel_state_t state)
8695 struct net_device *netdev = pci_get_drvdata(pdev);
8696 struct s2io_nic *sp = netdev_priv(netdev);
8698 netif_device_detach(netdev);
8700 if (state == pci_channel_io_perm_failure)
8701 return PCI_ERS_RESULT_DISCONNECT;
8703 if (netif_running(netdev)) {
8704 /* Bring down the card, while avoiding PCI I/O */
8705 do_s2io_card_down(sp, 0);
8707 pci_disable_device(pdev);
8709 return PCI_ERS_RESULT_NEED_RESET;
8713 * s2io_io_slot_reset - called after the pci bus has been reset.
8714 * @pdev: Pointer to PCI device
8716 * Restart the card from scratch, as if from a cold-boot.
8717 * At this point, the card has exprienced a hard reset,
8718 * followed by fixups by BIOS, and has its config space
8719 * set up identically to what it was at cold boot.
8721 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8723 struct net_device *netdev = pci_get_drvdata(pdev);
8724 struct s2io_nic *sp = netdev_priv(netdev);
8726 if (pci_enable_device(pdev)) {
8727 printk(KERN_ERR "s2io: "
8728 "Cannot re-enable PCI device after reset.\n");
8729 return PCI_ERS_RESULT_DISCONNECT;
8732 pci_set_master(pdev);
8735 return PCI_ERS_RESULT_RECOVERED;
8739 * s2io_io_resume - called when traffic can start flowing again.
8740 * @pdev: Pointer to PCI device
8742 * This callback is called when the error recovery driver tells
8743 * us that its OK to resume normal operation.
8745 static void s2io_io_resume(struct pci_dev *pdev)
8747 struct net_device *netdev = pci_get_drvdata(pdev);
8748 struct s2io_nic *sp = netdev_priv(netdev);
8750 if (netif_running(netdev)) {
8751 if (s2io_card_up(sp)) {
8752 printk(KERN_ERR "s2io: "
8753 "Can't bring device back up after reset.\n");
8757 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8759 printk(KERN_ERR "s2io: "
8760 "Can't resetore mac addr after reset.\n");
8765 netif_device_attach(netdev);
8766 netif_tx_wake_all_queues(netdev);