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   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  * rx_ring_num : This can be used to program the number of receive rings used
  30  * in the driver.
  31  * rx_ring_sz: This defines the number of descriptors each ring can have. This
  32  * is also an array of size 8.
  33  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  34  *              values are 1, 2 and 3.
  35  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  36  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  37  * Tx descriptors that can be associated with each corresponding FIFO.
  38  ************************************************************************/
  39
  40 #include <linux/config.h>
  41 #include <linux/module.h>
  42 #include <linux/types.h>
  43 #include <linux/errno.h>
  44 #include <linux/ioport.h>
  45 #include <linux/pci.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/kernel.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/skbuff.h>
  51 #include <linux/init.h>
  52 #include <linux/delay.h>
  53 #include <linux/stddef.h>
  54 #include <linux/ioctl.h>
  55 #include <linux/timex.h>
  56 #include <linux/sched.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/workqueue.h>
  59 #include <linux/if_vlan.h>
  60 #include <linux/ip.h>
  61 #include <linux/tcp.h>
  62 #include <net/tcp.h>
  63
  64 #include <asm/system.h>
  65 #include <asm/uaccess.h>
  66 #include <asm/io.h>
  67 #include <asm/div64.h>
  68
  69 /* local include */
  70 #include "s2io.h"
  71 #include "s2io-regs.h"
  72
  73 #define DRV_VERSION "2.0.11.2"
  74
  75 /* S2io Driver name & version. */
  76 static char s2io_driver_name[] = "Neterion";
  77 static char s2io_driver_version[] = DRV_VERSION;
  78
  79 static int rxd_size[4] = {32,48,48,64};
  80 static int rxd_count[4] = {127,85,85,63};
  81
  82 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  83 {
  84         int ret;
  85
  86         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  87                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  88
  89         return ret;
  90 }
  91
  92 /*
  93  * Cards with following subsystem_id have a link state indication
  94  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  95  * macro below identifies these cards given the subsystem_id.
  96  */
  97 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  98         (dev_type == XFRAME_I_DEVICE) ?                 \
  99                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 100                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 101
 102 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 103                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 104 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 105 #define PANIC   1
 106 #define LOW     2
 107 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 108 {
 109         mac_info_t *mac_control;
 110
 111         mac_control = &sp->mac_control;
 112         if (rxb_size <= rxd_count[sp->rxd_mode])
 113                 return PANIC;
 114         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 115                 return  LOW;
 116         return 0;
 117 }
 118
 119 /* Ethtool related variables and Macros. */
 120 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 121         "Register test\t(offline)",
 122         "Eeprom test\t(offline)",
 123         "Link test\t(online)",
 124         "RLDRAM test\t(offline)",
 125         "BIST Test\t(offline)"
 126 };
 127
 128 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 129         {"tmac_frms"},
 130         {"tmac_data_octets"},
 131         {"tmac_drop_frms"},
 132         {"tmac_mcst_frms"},
 133         {"tmac_bcst_frms"},
 134         {"tmac_pause_ctrl_frms"},
 135         {"tmac_any_err_frms"},
 136         {"tmac_vld_ip_octets"},
 137         {"tmac_vld_ip"},
 138         {"tmac_drop_ip"},
 139         {"tmac_icmp"},
 140         {"tmac_rst_tcp"},
 141         {"tmac_tcp"},
 142         {"tmac_udp"},
 143         {"rmac_vld_frms"},
 144         {"rmac_data_octets"},
 145         {"rmac_fcs_err_frms"},
 146         {"rmac_drop_frms"},
 147         {"rmac_vld_mcst_frms"},
 148         {"rmac_vld_bcst_frms"},
 149         {"rmac_in_rng_len_err_frms"},
 150         {"rmac_long_frms"},
 151         {"rmac_pause_ctrl_frms"},
 152         {"rmac_discarded_frms"},
 153         {"rmac_usized_frms"},
 154         {"rmac_osized_frms"},
 155         {"rmac_frag_frms"},
 156         {"rmac_jabber_frms"},
 157         {"rmac_ip"},
 158         {"rmac_ip_octets"},
 159         {"rmac_hdr_err_ip"},
 160         {"rmac_drop_ip"},
 161         {"rmac_icmp"},
 162         {"rmac_tcp"},
 163         {"rmac_udp"},
 164         {"rmac_err_drp_udp"},
 165         {"rmac_pause_cnt"},
 166         {"rmac_accepted_ip"},
 167         {"rmac_err_tcp"},
 168         {"\n DRIVER STATISTICS"},
 169         {"single_bit_ecc_errs"},
 170         {"double_bit_ecc_errs"},
 171         ("lro_aggregated_pkts"),
 172         ("lro_flush_both_count"),
 173         ("lro_out_of_sequence_pkts"),
 174         ("lro_flush_due_to_max_pkts"),
 175         ("lro_avg_aggr_pkts"),
 176 };
 177
 178 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 179 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 180
 181 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 182 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 183
 184 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 185                         init_timer(&timer);                     \
 186                         timer.function = handle;                \
 187                         timer.data = (unsigned long) arg;       \
 188                         mod_timer(&timer, (jiffies + exp))      \
 189
 190 /* Add the vlan */
 191 static void s2io_vlan_rx_register(struct net_device *dev,
 192                                         struct vlan_group *grp)
 193 {
 194         nic_t *nic = dev->priv;
 195         unsigned long flags;
 196
 197         spin_lock_irqsave(&nic->tx_lock, flags);
 198         nic->vlgrp = grp;
 199         spin_unlock_irqrestore(&nic->tx_lock, flags);
 200 }
 201
 202 /* Unregister the vlan */
 203 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 204 {
 205         nic_t *nic = dev->priv;
 206         unsigned long flags;
 207
 208         spin_lock_irqsave(&nic->tx_lock, flags);
 209         if (nic->vlgrp)
 210                 nic->vlgrp->vlan_devices[vid] = NULL;
 211         spin_unlock_irqrestore(&nic->tx_lock, flags);
 212 }
 213
 214 /*
 215  * Constants to be programmed into the Xena's registers, to configure
 216  * the XAUI.
 217  */
 218
 219 #define SWITCH_SIGN     0xA5A5A5A5A5A5A5A5ULL
 220 #define END_SIGN        0x0
 221
 222 static const u64 herc_act_dtx_cfg[] = {
 223         /* Set address */
 224         0x8000051536750000ULL, 0x80000515367500E0ULL,
 225         /* Write data */
 226         0x8000051536750004ULL, 0x80000515367500E4ULL,
 227         /* Set address */
 228         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 229         /* Write data */
 230         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 231         /* Set address */
 232         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 233         /* Write data */
 234         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 235         /* Set address */
 236         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 237         /* Write data */
 238         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 239         /* Done */
 240         END_SIGN
 241 };
 242
 243 static const u64 xena_mdio_cfg[] = {
 244         /* Reset PMA PLL */
 245         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 246         0xC0010100008000E4ULL,
 247         /* Remove Reset from PMA PLL */
 248         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 249         0xC0010100000000E4ULL,
 250         END_SIGN
 251 };
 252
 253 static const u64 xena_dtx_cfg[] = {
 254         0x8000051500000000ULL, 0x80000515000000E0ULL,
 255         0x80000515D93500E4ULL, 0x8001051500000000ULL,
 256         0x80010515000000E0ULL, 0x80010515001E00E4ULL,
 257         0x8002051500000000ULL, 0x80020515000000E0ULL,
 258         0x80020515F21000E4ULL,
 259         /* Set PADLOOPBACKN */
 260         0x8002051500000000ULL, 0x80020515000000E0ULL,
 261         0x80020515B20000E4ULL, 0x8003051500000000ULL,
 262         0x80030515000000E0ULL, 0x80030515B20000E4ULL,
 263         0x8004051500000000ULL, 0x80040515000000E0ULL,
 264         0x80040515B20000E4ULL, 0x8005051500000000ULL,
 265         0x80050515000000E0ULL, 0x80050515B20000E4ULL,
 266         SWITCH_SIGN,
 267         /* Remove PADLOOPBACKN */
 268         0x8002051500000000ULL, 0x80020515000000E0ULL,
 269         0x80020515F20000E4ULL, 0x8003051500000000ULL,
 270         0x80030515000000E0ULL, 0x80030515F20000E4ULL,
 271         0x8004051500000000ULL, 0x80040515000000E0ULL,
 272         0x80040515F20000E4ULL, 0x8005051500000000ULL,
 273         0x80050515000000E0ULL, 0x80050515F20000E4ULL,
 274         END_SIGN
 275 };
 276
 277 /*
 278  * Constants for Fixing the MacAddress problem seen mostly on
 279  * Alpha machines.
 280  */
 281 static const u64 fix_mac[] = {
 282         0x0060000000000000ULL, 0x0060600000000000ULL,
 283         0x0040600000000000ULL, 0x0000600000000000ULL,
 284         0x0020600000000000ULL, 0x0060600000000000ULL,
 285         0x0020600000000000ULL, 0x0060600000000000ULL,
 286         0x0020600000000000ULL, 0x0060600000000000ULL,
 287         0x0020600000000000ULL, 0x0060600000000000ULL,
 288         0x0020600000000000ULL, 0x0060600000000000ULL,
 289         0x0020600000000000ULL, 0x0060600000000000ULL,
 290         0x0020600000000000ULL, 0x0060600000000000ULL,
 291         0x0020600000000000ULL, 0x0060600000000000ULL,
 292         0x0020600000000000ULL, 0x0060600000000000ULL,
 293         0x0020600000000000ULL, 0x0060600000000000ULL,
 294         0x0020600000000000ULL, 0x0000600000000000ULL,
 295         0x0040600000000000ULL, 0x0060600000000000ULL,
 296         END_SIGN
 297 };
 298
 299 /* Module Loadable parameters. */
 300 static unsigned int tx_fifo_num = 1;
 301 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 302     {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
 303 static unsigned int rx_ring_num = 1;
 304 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 305     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 306 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 307     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 308 static unsigned int rx_ring_mode = 1;
 309 static unsigned int use_continuous_tx_intrs = 1;
 310 static unsigned int rmac_pause_time = 0x100;
 311 static unsigned int mc_pause_threshold_q0q3 = 187;
 312 static unsigned int mc_pause_threshold_q4q7 = 187;
 313 static unsigned int shared_splits;
 314 static unsigned int tmac_util_period = 5;
 315 static unsigned int rmac_util_period = 5;
 316 static unsigned int bimodal = 0;
 317 static unsigned int l3l4hdr_size = 128;
 318 #ifndef CONFIG_S2IO_NAPI
 319 static unsigned int indicate_max_pkts;
 320 #endif
 321 /* Frequency of Rx desc syncs expressed as power of 2 */
 322 static unsigned int rxsync_frequency = 3;
 323 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 324 static unsigned int intr_type = 0;
 325 /* Large receive offload feature */
 326 static unsigned int lro = 0;
 327 /* Max pkts to be aggregated by LRO at one time. If not specified,
 328  * aggregation happens until we hit max IP pkt size(64K)
 329  */
 330 static unsigned int lro_max_pkts = 0xFFFF;
 331
 332 /*
 333  * S2IO device table.
 334  * This table lists all the devices that this driver supports.
 335  */
 336 static struct pci_device_id s2io_tbl[] __devinitdata = {
 337         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 338          PCI_ANY_ID, PCI_ANY_ID},
 339         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 340          PCI_ANY_ID, PCI_ANY_ID},
 341         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 342          PCI_ANY_ID, PCI_ANY_ID},
 343         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 344          PCI_ANY_ID, PCI_ANY_ID},
 345         {0,}
 346 };
 347
 348 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 349
 350 static struct pci_driver s2io_driver = {
 351       .name = "S2IO",
 352       .id_table = s2io_tbl,
 353       .probe = s2io_init_nic,
 354       .remove = __devexit_p(s2io_rem_nic),
 355 };
 356
 357 /* A simplifier macro used both by init and free shared_mem Fns(). */
 358 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 359
 360 /**
 361  * init_shared_mem - Allocation and Initialization of Memory
 362  * @nic: Device private variable.
 363  * Description: The function allocates all the memory areas shared
 364  * between the NIC and the driver. This includes Tx descriptors,
 365  * Rx descriptors and the statistics block.
 366  */
 367
 368 static int init_shared_mem(struct s2io_nic *nic)
 369 {
 370         u32 size;
 371         void *tmp_v_addr, *tmp_v_addr_next;
 372         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 373         RxD_block_t *pre_rxd_blk = NULL;
 374         int i, j, blk_cnt, rx_sz, tx_sz;
 375         int lst_size, lst_per_page;
 376         struct net_device *dev = nic->dev;
 377         unsigned long tmp;
 378         buffAdd_t *ba;
 379
 380         mac_info_t *mac_control;
 381         struct config_param *config;
 382
 383         mac_control = &nic->mac_control;
 384         config = &nic->config;
 385
 386
 387         /* Allocation and initialization of TXDLs in FIOFs */
 388         size = 0;
 389         for (i = 0; i < config->tx_fifo_num; i++) {
 390                 size += config->tx_cfg[i].fifo_len;
 391         }
 392         if (size > MAX_AVAILABLE_TXDS) {
 393                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
 394                           __FUNCTION__);
 395                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 396                 return FAILURE;
 397         }
 398
 399         lst_size = (sizeof(TxD_t) * config->max_txds);
 400         tx_sz = lst_size * size;
 401         lst_per_page = PAGE_SIZE / lst_size;
 402
 403         for (i = 0; i < config->tx_fifo_num; i++) {
 404                 int fifo_len = config->tx_cfg[i].fifo_len;
 405                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 406                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 407                                                           GFP_KERNEL);
 408                 if (!mac_control->fifos[i].list_info) {
 409                         DBG_PRINT(ERR_DBG,
 410                                   "Malloc failed for list_info\n");
 411                         return -ENOMEM;
 412                 }
 413                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 414         }
 415         for (i = 0; i < config->tx_fifo_num; i++) {
 416                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 417                                                 lst_per_page);
 418                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 419                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 420                     config->tx_cfg[i].fifo_len - 1;
 421                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 422                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 423                     config->tx_cfg[i].fifo_len - 1;
 424                 mac_control->fifos[i].fifo_no = i;
 425                 mac_control->fifos[i].nic = nic;
 426                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 427
 428                 for (j = 0; j < page_num; j++) {
 429                         int k = 0;
 430                         dma_addr_t tmp_p;
 431                         void *tmp_v;
 432                         tmp_v = pci_alloc_consistent(nic->pdev,
 433                                                      PAGE_SIZE, &tmp_p);
 434                         if (!tmp_v) {
 435                                 DBG_PRINT(ERR_DBG,
 436                                           "pci_alloc_consistent ");
 437                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 438                                 return -ENOMEM;
 439                         }
 440                         /* If we got a zero DMA address(can happen on
 441                          * certain platforms like PPC), reallocate.
 442                          * Store virtual address of page we don't want,
 443                          * to be freed later.
 444                          */
 445                         if (!tmp_p) {
 446                                 mac_control->zerodma_virt_addr = tmp_v;
 447                                 DBG_PRINT(INIT_DBG,
 448                                 "%s: Zero DMA address for TxDL. ", dev->name);
 449                                 DBG_PRINT(INIT_DBG,
 450                                 "Virtual address %p\n", tmp_v);
 451                                 tmp_v = pci_alloc_consistent(nic->pdev,
 452                                                      PAGE_SIZE, &tmp_p);
 453                                 if (!tmp_v) {
 454                                         DBG_PRINT(ERR_DBG,
 455                                           "pci_alloc_consistent ");
 456                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 457                                         return -ENOMEM;
 458                                 }
 459                         }
 460                         while (k < lst_per_page) {
 461                                 int l = (j * lst_per_page) + k;
 462                                 if (l == config->tx_cfg[i].fifo_len)
 463                                         break;
 464                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 465                                     tmp_v + (k * lst_size);
 466                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 467                                     tmp_p + (k * lst_size);
 468                                 k++;
 469                         }
 470                 }
 471         }
 472
 473         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
 474         if (!nic->ufo_in_band_v)
 475                 return -ENOMEM;
 476
 477         /* Allocation and initialization of RXDs in Rings */
 478         size = 0;
 479         for (i = 0; i < config->rx_ring_num; i++) {
 480                 if (config->rx_cfg[i].num_rxd %
 481                     (rxd_count[nic->rxd_mode] + 1)) {
 482                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 483                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 484                                   i);
 485                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 486                         return FAILURE;
 487                 }
 488                 size += config->rx_cfg[i].num_rxd;
 489                 mac_control->rings[i].block_count =
 490                         config->rx_cfg[i].num_rxd /
 491                         (rxd_count[nic->rxd_mode] + 1 );
 492                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 493                         mac_control->rings[i].block_count;
 494         }
 495         if (nic->rxd_mode == RXD_MODE_1)
 496                 size = (size * (sizeof(RxD1_t)));
 497         else
 498                 size = (size * (sizeof(RxD3_t)));
 499         rx_sz = size;
 500
 501         for (i = 0; i < config->rx_ring_num; i++) {
 502                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 503                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 504                 mac_control->rings[i].rx_curr_get_info.ring_len =
 505                     config->rx_cfg[i].num_rxd - 1;
 506                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 507                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 508                 mac_control->rings[i].rx_curr_put_info.ring_len =
 509                     config->rx_cfg[i].num_rxd - 1;
 510                 mac_control->rings[i].nic = nic;
 511                 mac_control->rings[i].ring_no = i;
 512
 513                 blk_cnt = config->rx_cfg[i].num_rxd /
 514                                 (rxd_count[nic->rxd_mode] + 1);
 515                 /*  Allocating all the Rx blocks */
 516                 for (j = 0; j < blk_cnt; j++) {
 517                         rx_block_info_t *rx_blocks;
 518                         int l;
 519
 520                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 521                         size = SIZE_OF_BLOCK; //size is always page size
 522                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 523                                                           &tmp_p_addr);
 524                         if (tmp_v_addr == NULL) {
 525                                 /*
 526                                  * In case of failure, free_shared_mem()
 527                                  * is called, which should free any
 528                                  * memory that was alloced till the
 529                                  * failure happened.
 530                                  */
 531                                 rx_blocks->block_virt_addr = tmp_v_addr;
 532                                 return -ENOMEM;
 533                         }
 534                         memset(tmp_v_addr, 0, size);
 535                         rx_blocks->block_virt_addr = tmp_v_addr;
 536                         rx_blocks->block_dma_addr = tmp_p_addr;
 537                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 538                                                   rxd_count[nic->rxd_mode],
 539                                                   GFP_KERNEL);
 540                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 541                                 rx_blocks->rxds[l].virt_addr =
 542                                         rx_blocks->block_virt_addr +
 543                                         (rxd_size[nic->rxd_mode] * l);
 544                                 rx_blocks->rxds[l].dma_addr =
 545                                         rx_blocks->block_dma_addr +
 546                                         (rxd_size[nic->rxd_mode] * l);
 547                         }
 548
 549                         mac_control->rings[i].rx_blocks[j].block_virt_addr =
 550                                 tmp_v_addr;
 551                         mac_control->rings[i].rx_blocks[j].block_dma_addr =
 552                                 tmp_p_addr;
 553                 }
 554                 /* Interlinking all Rx Blocks */
 555                 for (j = 0; j < blk_cnt; j++) {
 556                         tmp_v_addr =
 557                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 558                         tmp_v_addr_next =
 559                                 mac_control->rings[i].rx_blocks[(j + 1) %
 560                                               blk_cnt].block_virt_addr;
 561                         tmp_p_addr =
 562                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 563                         tmp_p_addr_next =
 564                                 mac_control->rings[i].rx_blocks[(j + 1) %
 565                                               blk_cnt].block_dma_addr;
 566
 567                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 568                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 569                             (unsigned long) tmp_v_addr_next;
 570                         pre_rxd_blk->pNext_RxD_Blk_physical =
 571                             (u64) tmp_p_addr_next;
 572                 }
 573         }
 574         if (nic->rxd_mode >= RXD_MODE_3A) {
 575                 /*
 576                  * Allocation of Storages for buffer addresses in 2BUFF mode
 577                  * and the buffers as well.
 578                  */
 579                 for (i = 0; i < config->rx_ring_num; i++) {
 580                         blk_cnt = config->rx_cfg[i].num_rxd /
 581                            (rxd_count[nic->rxd_mode]+ 1);
 582                         mac_control->rings[i].ba =
 583                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 584                                      GFP_KERNEL);
 585                         if (!mac_control->rings[i].ba)
 586                                 return -ENOMEM;
 587                         for (j = 0; j < blk_cnt; j++) {
 588                                 int k = 0;
 589                                 mac_control->rings[i].ba[j] =
 590                                         kmalloc((sizeof(buffAdd_t) *
 591                                                 (rxd_count[nic->rxd_mode] + 1)),
 592                                                 GFP_KERNEL);
 593                                 if (!mac_control->rings[i].ba[j])
 594                                         return -ENOMEM;
 595                                 while (k != rxd_count[nic->rxd_mode]) {
 596                                         ba = &mac_control->rings[i].ba[j][k];
 597
 598                                         ba->ba_0_org = (void *) kmalloc
 599                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 600                                         if (!ba->ba_0_org)
 601                                                 return -ENOMEM;
 602                                         tmp = (unsigned long)ba->ba_0_org;
 603                                         tmp += ALIGN_SIZE;
 604                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 605                                         ba->ba_0 = (void *) tmp;
 606
 607                                         ba->ba_1_org = (void *) kmalloc
 608                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 609                                         if (!ba->ba_1_org)
 610                                                 return -ENOMEM;
 611                                         tmp = (unsigned long) ba->ba_1_org;
 612                                         tmp += ALIGN_SIZE;
 613                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 614                                         ba->ba_1 = (void *) tmp;
 615                                         k++;
 616                                 }
 617                         }
 618                 }
 619         }
 620
 621         /* Allocation and initialization of Statistics block */
 622         size = sizeof(StatInfo_t);
 623         mac_control->stats_mem = pci_alloc_consistent
 624             (nic->pdev, size, &mac_control->stats_mem_phy);
 625
 626         if (!mac_control->stats_mem) {
 627                 /*
 628                  * In case of failure, free_shared_mem() is called, which
 629                  * should free any memory that was alloced till the
 630                  * failure happened.
 631                  */
 632                 return -ENOMEM;
 633         }
 634         mac_control->stats_mem_sz = size;
 635
 636         tmp_v_addr = mac_control->stats_mem;
 637         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 638         memset(tmp_v_addr, 0, size);
 639         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 640                   (unsigned long long) tmp_p_addr);
 641
 642         return SUCCESS;
 643 }
 644
 645 /**
 646  * free_shared_mem - Free the allocated Memory
 647  * @nic:  Device private variable.
 648  * Description: This function is to free all memory locations allocated by
 649  * the init_shared_mem() function and return it to the kernel.
 650  */
 651
 652 static void free_shared_mem(struct s2io_nic *nic)
 653 {
 654         int i, j, blk_cnt, size;
 655         void *tmp_v_addr;
 656         dma_addr_t tmp_p_addr;
 657         mac_info_t *mac_control;
 658         struct config_param *config;
 659         int lst_size, lst_per_page;
 660         struct net_device *dev = nic->dev;
 661
 662         if (!nic)
 663                 return;
 664
 665         mac_control = &nic->mac_control;
 666         config = &nic->config;
 667
 668         lst_size = (sizeof(TxD_t) * config->max_txds);
 669         lst_per_page = PAGE_SIZE / lst_size;
 670
 671         for (i = 0; i < config->tx_fifo_num; i++) {
 672                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 673                                                 lst_per_page);
 674                 for (j = 0; j < page_num; j++) {
 675                         int mem_blks = (j * lst_per_page);
 676                         if (!mac_control->fifos[i].list_info)
 677                                 return;
 678                         if (!mac_control->fifos[i].list_info[mem_blks].
 679                                  list_virt_addr)
 680                                 break;
 681                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 682                                             mac_control->fifos[i].
 683                                             list_info[mem_blks].
 684                                             list_virt_addr,
 685                                             mac_control->fifos[i].
 686                                             list_info[mem_blks].
 687                                             list_phy_addr);
 688                 }
 689                 /* If we got a zero DMA address during allocation,
 690                  * free the page now
 691                  */
 692                 if (mac_control->zerodma_virt_addr) {
 693                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 694                                             mac_control->zerodma_virt_addr,
 695                                             (dma_addr_t)0);
 696                         DBG_PRINT(INIT_DBG,
 697                                 "%s: Freeing TxDL with zero DMA addr. ",
 698                                 dev->name);
 699                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 700                                 mac_control->zerodma_virt_addr);
 701                 }
 702                 kfree(mac_control->fifos[i].list_info);
 703         }
 704
 705         size = SIZE_OF_BLOCK;
 706         for (i = 0; i < config->rx_ring_num; i++) {
 707                 blk_cnt = mac_control->rings[i].block_count;
 708                 for (j = 0; j < blk_cnt; j++) {
 709                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 710                                 block_virt_addr;
 711                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 712                                 block_dma_addr;
 713                         if (tmp_v_addr == NULL)
 714                                 break;
 715                         pci_free_consistent(nic->pdev, size,
 716                                             tmp_v_addr, tmp_p_addr);
 717                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 718                 }
 719         }
 720
 721         if (nic->rxd_mode >= RXD_MODE_3A) {
 722                 /* Freeing buffer storage addresses in 2BUFF mode. */
 723                 for (i = 0; i < config->rx_ring_num; i++) {
 724                         blk_cnt = config->rx_cfg[i].num_rxd /
 725                             (rxd_count[nic->rxd_mode] + 1);
 726                         for (j = 0; j < blk_cnt; j++) {
 727                                 int k = 0;
 728                                 if (!mac_control->rings[i].ba[j])
 729                                         continue;
 730                                 while (k != rxd_count[nic->rxd_mode]) {
 731                                         buffAdd_t *ba =
 732                                                 &mac_control->rings[i].ba[j][k];
 733                                         kfree(ba->ba_0_org);
 734                                         kfree(ba->ba_1_org);
 735                                         k++;
 736                                 }
 737                                 kfree(mac_control->rings[i].ba[j]);
 738                         }
 739                         kfree(mac_control->rings[i].ba);
 740                 }
 741         }
 742
 743         if (mac_control->stats_mem) {
 744                 pci_free_consistent(nic->pdev,
 745                                     mac_control->stats_mem_sz,
 746                                     mac_control->stats_mem,
 747                                     mac_control->stats_mem_phy);
 748         }
 749         if (nic->ufo_in_band_v)
 750                 kfree(nic->ufo_in_band_v);
 751 }
 752
 753 /**
 754  * s2io_verify_pci_mode -
 755  */
 756
 757 static int s2io_verify_pci_mode(nic_t *nic)
 758 {
 759         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 760         register u64 val64 = 0;
 761         int     mode;
 762
 763         val64 = readq(&bar0->pci_mode);
 764         mode = (u8)GET_PCI_MODE(val64);
 765
 766         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 767                 return -1;      /* Unknown PCI mode */
 768         return mode;
 769 }
 770
 771
 772 /**
 773  * s2io_print_pci_mode -
 774  */
 775 static int s2io_print_pci_mode(nic_t *nic)
 776 {
 777         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 778         register u64 val64 = 0;
 779         int     mode;
 780         struct config_param *config = &nic->config;
 781
 782         val64 = readq(&bar0->pci_mode);
 783         mode = (u8)GET_PCI_MODE(val64);
 784
 785         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 786                 return -1;      /* Unknown PCI mode */
 787
 788         if (val64 & PCI_MODE_32_BITS) {
 789                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 790         } else {
 791                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 792         }
 793
 794         switch(mode) {
 795                 case PCI_MODE_PCI_33:
 796                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 797                         config->bus_speed = 33;
 798                         break;
 799                 case PCI_MODE_PCI_66:
 800                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 801                         config->bus_speed = 133;
 802                         break;
 803                 case PCI_MODE_PCIX_M1_66:
 804                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 805                         config->bus_speed = 133; /* Herc doubles the clock rate */
 806                         break;
 807                 case PCI_MODE_PCIX_M1_100:
 808                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 809                         config->bus_speed = 200;
 810                         break;
 811                 case PCI_MODE_PCIX_M1_133:
 812                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 813                         config->bus_speed = 266;
 814                         break;
 815                 case PCI_MODE_PCIX_M2_66:
 816                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 817                         config->bus_speed = 133;
 818                         break;
 819                 case PCI_MODE_PCIX_M2_100:
 820                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 821                         config->bus_speed = 200;
 822                         break;
 823                 case PCI_MODE_PCIX_M2_133:
 824                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 825                         config->bus_speed = 266;
 826                         break;
 827                 default:
 828                         return -1;      /* Unsupported bus speed */
 829         }
 830
 831         return mode;
 832 }
 833
 834 /**
 835  *  init_nic - Initialization of hardware
 836  *  @nic: device peivate variable
 837  *  Description: The function sequentially configures every block
 838  *  of the H/W from their reset values.
 839  *  Return Value:  SUCCESS on success and
 840  *  '-1' on failure (endian settings incorrect).
 841  */
 842
 843 static int init_nic(struct s2io_nic *nic)
 844 {
 845         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 846         struct net_device *dev = nic->dev;
 847         register u64 val64 = 0;
 848         void __iomem *add;
 849         u32 time;
 850         int i, j;
 851         mac_info_t *mac_control;
 852         struct config_param *config;
 853         int mdio_cnt = 0, dtx_cnt = 0;
 854         unsigned long long mem_share;
 855         int mem_size;
 856
 857         mac_control = &nic->mac_control;
 858         config = &nic->config;
 859
 860         /* to set the swapper controle on the card */
 861         if(s2io_set_swapper(nic)) {
 862                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 863                 return -1;
 864         }
 865
 866         /*
 867          * Herc requires EOI to be removed from reset before XGXS, so..
 868          */
 869         if (nic->device_type & XFRAME_II_DEVICE) {
 870                 val64 = 0xA500000000ULL;
 871                 writeq(val64, &bar0->sw_reset);
 872                 msleep(500);
 873                 val64 = readq(&bar0->sw_reset);
 874         }
 875
 876         /* Remove XGXS from reset state */
 877         val64 = 0;
 878         writeq(val64, &bar0->sw_reset);
 879         msleep(500);
 880         val64 = readq(&bar0->sw_reset);
 881
 882         /*  Enable Receiving broadcasts */
 883         add = &bar0->mac_cfg;
 884         val64 = readq(&bar0->mac_cfg);
 885         val64 |= MAC_RMAC_BCAST_ENABLE;
 886         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 887         writel((u32) val64, add);
 888         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 889         writel((u32) (val64 >> 32), (add + 4));
 890
 891         /* Read registers in all blocks */
 892         val64 = readq(&bar0->mac_int_mask);
 893         val64 = readq(&bar0->mc_int_mask);
 894         val64 = readq(&bar0->xgxs_int_mask);
 895
 896         /*  Set MTU */
 897         val64 = dev->mtu;
 898         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 899
 900         /*
 901          * Configuring the XAUI Interface of Xena.
 902          * ***************************************
 903          * To Configure the Xena's XAUI, one has to write a series
 904          * of 64 bit values into two registers in a particular
 905          * sequence. Hence a macro 'SWITCH_SIGN' has been defined
 906          * which will be defined in the array of configuration values
 907          * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
 908          * to switch writing from one regsiter to another. We continue
 909          * writing these values until we encounter the 'END_SIGN' macro.
 910          * For example, After making a series of 21 writes into
 911          * dtx_control register the 'SWITCH_SIGN' appears and hence we
 912          * start writing into mdio_control until we encounter END_SIGN.
 913          */
 914         if (nic->device_type & XFRAME_II_DEVICE) {
 915                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 916                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 917                                           &bar0->dtx_control, UF);
 918                         if (dtx_cnt & 0x1)
 919                                 msleep(1); /* Necessary!! */
 920                         dtx_cnt++;
 921                 }
 922         } else {
 923                 while (1) {
 924                       dtx_cfg:
 925                         while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
 926                                 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
 927                                         dtx_cnt++;
 928                                         goto mdio_cfg;
 929                                 }
 930                                 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
 931                                                   &bar0->dtx_control, UF);
 932                                 val64 = readq(&bar0->dtx_control);
 933                                 dtx_cnt++;
 934                         }
 935                       mdio_cfg:
 936                         while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
 937                                 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
 938                                         mdio_cnt++;
 939                                         goto dtx_cfg;
 940                                 }
 941                                 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
 942                                                   &bar0->mdio_control, UF);
 943                                 val64 = readq(&bar0->mdio_control);
 944                                 mdio_cnt++;
 945                         }
 946                         if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
 947                             (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
 948                                 break;
 949                         } else {
 950                                 goto dtx_cfg;
 951                         }
 952                 }
 953         }
 954
 955         /*  Tx DMA Initialization */
 956         val64 = 0;
 957         writeq(val64, &bar0->tx_fifo_partition_0);
 958         writeq(val64, &bar0->tx_fifo_partition_1);
 959         writeq(val64, &bar0->tx_fifo_partition_2);
 960         writeq(val64, &bar0->tx_fifo_partition_3);
 961
 962
 963         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
 964                 val64 |=
 965                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
 966                          13) | vBIT(config->tx_cfg[i].fifo_priority,
 967                                     ((i * 32) + 5), 3);
 968
 969                 if (i == (config->tx_fifo_num - 1)) {
 970                         if (i % 2 == 0)
 971                                 i++;
 972                 }
 973
 974                 switch (i) {
 975                 case 1:
 976                         writeq(val64, &bar0->tx_fifo_partition_0);
 977                         val64 = 0;
 978                         break;
 979                 case 3:
 980                         writeq(val64, &bar0->tx_fifo_partition_1);
 981                         val64 = 0;
 982                         break;
 983                 case 5:
 984                         writeq(val64, &bar0->tx_fifo_partition_2);
 985                         val64 = 0;
 986                         break;
 987                 case 7:
 988                         writeq(val64, &bar0->tx_fifo_partition_3);
 989                         break;
 990                 }
 991         }
 992
 993         /* Enable Tx FIFO partition 0. */
 994         val64 = readq(&bar0->tx_fifo_partition_0);
 995         val64 |= BIT(0);        /* To enable the FIFO partition. */
 996         writeq(val64, &bar0->tx_fifo_partition_0);
 997
 998         /*
 999          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1000          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1001          */
1002         if ((nic->device_type == XFRAME_I_DEVICE) &&
1003                 (get_xena_rev_id(nic->pdev) < 4))
1004                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1005
1006         val64 = readq(&bar0->tx_fifo_partition_0);
1007         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1008                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1009
1010         /*
1011          * Initialization of Tx_PA_CONFIG register to ignore packet
1012          * integrity checking.
1013          */
1014         val64 = readq(&bar0->tx_pa_cfg);
1015         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1016             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1017         writeq(val64, &bar0->tx_pa_cfg);
1018
1019         /* Rx DMA intialization. */
1020         val64 = 0;
1021         for (i = 0; i < config->rx_ring_num; i++) {
1022                 val64 |=
1023                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1024                          3);
1025         }
1026         writeq(val64, &bar0->rx_queue_priority);
1027
1028         /*
1029          * Allocating equal share of memory to all the
1030          * configured Rings.
1031          */
1032         val64 = 0;
1033         if (nic->device_type & XFRAME_II_DEVICE)
1034                 mem_size = 32;
1035         else
1036                 mem_size = 64;
1037
1038         for (i = 0; i < config->rx_ring_num; i++) {
1039                 switch (i) {
1040                 case 0:
1041                         mem_share = (mem_size / config->rx_ring_num +
1042                                      mem_size % config->rx_ring_num);
1043                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1044                         continue;
1045                 case 1:
1046                         mem_share = (mem_size / config->rx_ring_num);
1047                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1048                         continue;
1049                 case 2:
1050                         mem_share = (mem_size / config->rx_ring_num);
1051                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1052                         continue;
1053                 case 3:
1054                         mem_share = (mem_size / config->rx_ring_num);
1055                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1056                         continue;
1057                 case 4:
1058                         mem_share = (mem_size / config->rx_ring_num);
1059                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1060                         continue;
1061                 case 5:
1062                         mem_share = (mem_size / config->rx_ring_num);
1063                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1064                         continue;
1065                 case 6:
1066                         mem_share = (mem_size / config->rx_ring_num);
1067                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1068                         continue;
1069                 case 7:
1070                         mem_share = (mem_size / config->rx_ring_num);
1071                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1072                         continue;
1073                 }
1074         }
1075         writeq(val64, &bar0->rx_queue_cfg);
1076
1077         /*
1078          * Filling Tx round robin registers
1079          * as per the number of FIFOs
1080          */
1081         switch (config->tx_fifo_num) {
1082         case 1:
1083                 val64 = 0x0000000000000000ULL;
1084                 writeq(val64, &bar0->tx_w_round_robin_0);
1085                 writeq(val64, &bar0->tx_w_round_robin_1);
1086                 writeq(val64, &bar0->tx_w_round_robin_2);
1087                 writeq(val64, &bar0->tx_w_round_robin_3);
1088                 writeq(val64, &bar0->tx_w_round_robin_4);
1089                 break;
1090         case 2:
1091                 val64 = 0x0000010000010000ULL;
1092                 writeq(val64, &bar0->tx_w_round_robin_0);
1093                 val64 = 0x0100000100000100ULL;
1094                 writeq(val64, &bar0->tx_w_round_robin_1);
1095                 val64 = 0x0001000001000001ULL;
1096                 writeq(val64, &bar0->tx_w_round_robin_2);
1097                 val64 = 0x0000010000010000ULL;
1098                 writeq(val64, &bar0->tx_w_round_robin_3);
1099                 val64 = 0x0100000000000000ULL;
1100                 writeq(val64, &bar0->tx_w_round_robin_4);
1101                 break;
1102         case 3:
1103                 val64 = 0x0001000102000001ULL;
1104                 writeq(val64, &bar0->tx_w_round_robin_0);
1105                 val64 = 0x0001020000010001ULL;
1106                 writeq(val64, &bar0->tx_w_round_robin_1);
1107                 val64 = 0x0200000100010200ULL;
1108                 writeq(val64, &bar0->tx_w_round_robin_2);
1109                 val64 = 0x0001000102000001ULL;
1110                 writeq(val64, &bar0->tx_w_round_robin_3);
1111                 val64 = 0x0001020000000000ULL;
1112                 writeq(val64, &bar0->tx_w_round_robin_4);
1113                 break;
1114         case 4:
1115                 val64 = 0x0001020300010200ULL;
1116                 writeq(val64, &bar0->tx_w_round_robin_0);
1117                 val64 = 0x0100000102030001ULL;
1118                 writeq(val64, &bar0->tx_w_round_robin_1);
1119                 val64 = 0x0200010000010203ULL;
1120                 writeq(val64, &bar0->tx_w_round_robin_2);
1121                 val64 = 0x0001020001000001ULL;
1122                 writeq(val64, &bar0->tx_w_round_robin_3);
1123                 val64 = 0x0203000100000000ULL;
1124                 writeq(val64, &bar0->tx_w_round_robin_4);
1125                 break;
1126         case 5:
1127                 val64 = 0x0001000203000102ULL;
1128                 writeq(val64, &bar0->tx_w_round_robin_0);
1129                 val64 = 0x0001020001030004ULL;
1130                 writeq(val64, &bar0->tx_w_round_robin_1);
1131                 val64 = 0x0001000203000102ULL;
1132                 writeq(val64, &bar0->tx_w_round_robin_2);
1133                 val64 = 0x0001020001030004ULL;
1134                 writeq(val64, &bar0->tx_w_round_robin_3);
1135                 val64 = 0x0001000000000000ULL;
1136                 writeq(val64, &bar0->tx_w_round_robin_4);
1137                 break;
1138         case 6:
1139                 val64 = 0x0001020304000102ULL;
1140                 writeq(val64, &bar0->tx_w_round_robin_0);
1141                 val64 = 0x0304050001020001ULL;
1142                 writeq(val64, &bar0->tx_w_round_robin_1);
1143                 val64 = 0x0203000100000102ULL;
1144                 writeq(val64, &bar0->tx_w_round_robin_2);
1145                 val64 = 0x0304000102030405ULL;
1146                 writeq(val64, &bar0->tx_w_round_robin_3);
1147                 val64 = 0x0001000200000000ULL;
1148                 writeq(val64, &bar0->tx_w_round_robin_4);
1149                 break;
1150         case 7:
1151                 val64 = 0x0001020001020300ULL;
1152                 writeq(val64, &bar0->tx_w_round_robin_0);
1153                 val64 = 0x0102030400010203ULL;
1154                 writeq(val64, &bar0->tx_w_round_robin_1);
1155                 val64 = 0x0405060001020001ULL;
1156                 writeq(val64, &bar0->tx_w_round_robin_2);
1157                 val64 = 0x0304050000010200ULL;
1158                 writeq(val64, &bar0->tx_w_round_robin_3);
1159                 val64 = 0x0102030000000000ULL;
1160                 writeq(val64, &bar0->tx_w_round_robin_4);
1161                 break;
1162         case 8:
1163                 val64 = 0x0001020300040105ULL;
1164                 writeq(val64, &bar0->tx_w_round_robin_0);
1165                 val64 = 0x0200030106000204ULL;
1166                 writeq(val64, &bar0->tx_w_round_robin_1);
1167                 val64 = 0x0103000502010007ULL;
1168                 writeq(val64, &bar0->tx_w_round_robin_2);
1169                 val64 = 0x0304010002060500ULL;
1170                 writeq(val64, &bar0->tx_w_round_robin_3);
1171                 val64 = 0x0103020400000000ULL;
1172                 writeq(val64, &bar0->tx_w_round_robin_4);
1173                 break;
1174         }
1175
1176         /* Filling the Rx round robin registers as per the
1177          * number of Rings and steering based on QoS.
1178          */
1179         switch (config->rx_ring_num) {
1180         case 1:
1181                 val64 = 0x8080808080808080ULL;
1182                 writeq(val64, &bar0->rts_qos_steering);
1183                 break;
1184         case 2:
1185                 val64 = 0x0000010000010000ULL;
1186                 writeq(val64, &bar0->rx_w_round_robin_0);
1187                 val64 = 0x0100000100000100ULL;
1188                 writeq(val64, &bar0->rx_w_round_robin_1);
1189                 val64 = 0x0001000001000001ULL;
1190                 writeq(val64, &bar0->rx_w_round_robin_2);
1191                 val64 = 0x0000010000010000ULL;
1192                 writeq(val64, &bar0->rx_w_round_robin_3);
1193                 val64 = 0x0100000000000000ULL;
1194                 writeq(val64, &bar0->rx_w_round_robin_4);
1195
1196                 val64 = 0x8080808040404040ULL;
1197                 writeq(val64, &bar0->rts_qos_steering);
1198                 break;
1199         case 3:
1200                 val64 = 0x0001000102000001ULL;
1201                 writeq(val64, &bar0->rx_w_round_robin_0);
1202                 val64 = 0x0001020000010001ULL;
1203                 writeq(val64, &bar0->rx_w_round_robin_1);
1204                 val64 = 0x0200000100010200ULL;
1205                 writeq(val64, &bar0->rx_w_round_robin_2);
1206                 val64 = 0x0001000102000001ULL;
1207                 writeq(val64, &bar0->rx_w_round_robin_3);
1208                 val64 = 0x0001020000000000ULL;
1209                 writeq(val64, &bar0->rx_w_round_robin_4);
1210
1211                 val64 = 0x8080804040402020ULL;
1212                 writeq(val64, &bar0->rts_qos_steering);
1213                 break;
1214         case 4:
1215                 val64 = 0x0001020300010200ULL;
1216                 writeq(val64, &bar0->rx_w_round_robin_0);
1217                 val64 = 0x0100000102030001ULL;
1218                 writeq(val64, &bar0->rx_w_round_robin_1);
1219                 val64 = 0x0200010000010203ULL;
1220                 writeq(val64, &bar0->rx_w_round_robin_2);
1221                 val64 = 0x0001020001000001ULL;
1222                 writeq(val64, &bar0->rx_w_round_robin_3);
1223                 val64 = 0x0203000100000000ULL;
1224                 writeq(val64, &bar0->rx_w_round_robin_4);
1225
1226                 val64 = 0x8080404020201010ULL;
1227                 writeq(val64, &bar0->rts_qos_steering);
1228                 break;
1229         case 5:
1230                 val64 = 0x0001000203000102ULL;
1231                 writeq(val64, &bar0->rx_w_round_robin_0);
1232                 val64 = 0x0001020001030004ULL;
1233                 writeq(val64, &bar0->rx_w_round_robin_1);
1234                 val64 = 0x0001000203000102ULL;
1235                 writeq(val64, &bar0->rx_w_round_robin_2);
1236                 val64 = 0x0001020001030004ULL;
1237                 writeq(val64, &bar0->rx_w_round_robin_3);
1238                 val64 = 0x0001000000000000ULL;
1239                 writeq(val64, &bar0->rx_w_round_robin_4);
1240
1241                 val64 = 0x8080404020201008ULL;
1242                 writeq(val64, &bar0->rts_qos_steering);
1243                 break;
1244         case 6:
1245                 val64 = 0x0001020304000102ULL;
1246                 writeq(val64, &bar0->rx_w_round_robin_0);
1247                 val64 = 0x0304050001020001ULL;
1248                 writeq(val64, &bar0->rx_w_round_robin_1);
1249                 val64 = 0x0203000100000102ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_2);
1251                 val64 = 0x0304000102030405ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_3);
1253                 val64 = 0x0001000200000000ULL;
1254                 writeq(val64, &bar0->rx_w_round_robin_4);
1255
1256                 val64 = 0x8080404020100804ULL;
1257                 writeq(val64, &bar0->rts_qos_steering);
1258                 break;
1259         case 7:
1260                 val64 = 0x0001020001020300ULL;
1261                 writeq(val64, &bar0->rx_w_round_robin_0);
1262                 val64 = 0x0102030400010203ULL;
1263                 writeq(val64, &bar0->rx_w_round_robin_1);
1264                 val64 = 0x0405060001020001ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_2);
1266                 val64 = 0x0304050000010200ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_3);
1268                 val64 = 0x0102030000000000ULL;
1269                 writeq(val64, &bar0->rx_w_round_robin_4);
1270
1271                 val64 = 0x8080402010080402ULL;
1272                 writeq(val64, &bar0->rts_qos_steering);
1273                 break;
1274         case 8:
1275                 val64 = 0x0001020300040105ULL;
1276                 writeq(val64, &bar0->rx_w_round_robin_0);
1277                 val64 = 0x0200030106000204ULL;
1278                 writeq(val64, &bar0->rx_w_round_robin_1);
1279                 val64 = 0x0103000502010007ULL;
1280                 writeq(val64, &bar0->rx_w_round_robin_2);
1281                 val64 = 0x0304010002060500ULL;
1282                 writeq(val64, &bar0->rx_w_round_robin_3);
1283                 val64 = 0x0103020400000000ULL;
1284                 writeq(val64, &bar0->rx_w_round_robin_4);
1285
1286                 val64 = 0x8040201008040201ULL;
1287                 writeq(val64, &bar0->rts_qos_steering);
1288                 break;
1289         }
1290
1291         /* UDP Fix */
1292         val64 = 0;
1293         for (i = 0; i < 8; i++)
1294                 writeq(val64, &bar0->rts_frm_len_n[i]);
1295
1296         /* Set the default rts frame length for the rings configured */
1297         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1298         for (i = 0 ; i < config->rx_ring_num ; i++)
1299                 writeq(val64, &bar0->rts_frm_len_n[i]);
1300
1301         /* Set the frame length for the configured rings
1302          * desired by the user
1303          */
1304         for (i = 0; i < config->rx_ring_num; i++) {
1305                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1306                  * specified frame length steering.
1307                  * If the user provides the frame length then program
1308                  * the rts_frm_len register for those values or else
1309                  * leave it as it is.
1310                  */
1311                 if (rts_frm_len[i] != 0) {
1312                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1313                                 &bar0->rts_frm_len_n[i]);
1314                 }
1315         }
1316
1317         /* Program statistics memory */
1318         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1319
1320         if (nic->device_type == XFRAME_II_DEVICE) {
1321                 val64 = STAT_BC(0x320);
1322                 writeq(val64, &bar0->stat_byte_cnt);
1323         }
1324
1325         /*
1326          * Initializing the sampling rate for the device to calculate the
1327          * bandwidth utilization.
1328          */
1329         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1330             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1331         writeq(val64, &bar0->mac_link_util);
1332
1333
1334         /*
1335          * Initializing the Transmit and Receive Traffic Interrupt
1336          * Scheme.
1337          */
1338         /*
1339          * TTI Initialization. Default Tx timer gets us about
1340          * 250 interrupts per sec. Continuous interrupts are enabled
1341          * by default.
1342          */
1343         if (nic->device_type == XFRAME_II_DEVICE) {
1344                 int count = (nic->config.bus_speed * 125)/2;
1345                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1346         } else {
1347
1348                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1349         }
1350         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1351             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1352             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1353                 if (use_continuous_tx_intrs)
1354                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1355         writeq(val64, &bar0->tti_data1_mem);
1356
1357         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1358             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1359             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1360         writeq(val64, &bar0->tti_data2_mem);
1361
1362         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1363         writeq(val64, &bar0->tti_command_mem);
1364
1365         /*
1366          * Once the operation completes, the Strobe bit of the command
1367          * register will be reset. We poll for this particular condition
1368          * We wait for a maximum of 500ms for the operation to complete,
1369          * if it's not complete by then we return error.
1370          */
1371         time = 0;
1372         while (TRUE) {
1373                 val64 = readq(&bar0->tti_command_mem);
1374                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1375                         break;
1376                 }
1377                 if (time > 10) {
1378                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1379                                   dev->name);
1380                         return -1;
1381                 }
1382                 msleep(50);
1383                 time++;
1384         }
1385
1386         if (nic->config.bimodal) {
1387                 int k = 0;
1388                 for (k = 0; k < config->rx_ring_num; k++) {
1389                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1390                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1391                         writeq(val64, &bar0->tti_command_mem);
1392
1393                 /*
1394                  * Once the operation completes, the Strobe bit of the command
1395                  * register will be reset. We poll for this particular condition
1396                  * We wait for a maximum of 500ms for the operation to complete,
1397                  * if it's not complete by then we return error.
1398                 */
1399                         time = 0;
1400                         while (TRUE) {
1401                                 val64 = readq(&bar0->tti_command_mem);
1402                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1403                                         break;
1404                                 }
1405                                 if (time > 10) {
1406                                         DBG_PRINT(ERR_DBG,
1407                                                 "%s: TTI init Failed\n",
1408                                         dev->name);
1409                                         return -1;
1410                                 }
1411                                 time++;
1412                                 msleep(50);
1413                         }
1414                 }
1415         } else {
1416
1417                 /* RTI Initialization */
1418                 if (nic->device_type == XFRAME_II_DEVICE) {
1419                         /*
1420                          * Programmed to generate Apprx 500 Intrs per
1421                          * second
1422                          */
1423                         int count = (nic->config.bus_speed * 125)/4;
1424                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1425                 } else {
1426                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1427                 }
1428                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1429                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1430                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1431
1432                 writeq(val64, &bar0->rti_data1_mem);
1433
1434                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1435                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1436                 if (nic->intr_type == MSI_X)
1437                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1438                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1439                 else
1440                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1441                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1442                 writeq(val64, &bar0->rti_data2_mem);
1443
1444                 for (i = 0; i < config->rx_ring_num; i++) {
1445                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1446                                         | RTI_CMD_MEM_OFFSET(i);
1447                         writeq(val64, &bar0->rti_command_mem);
1448
1449                         /*
1450                          * Once the operation completes, the Strobe bit of the
1451                          * command register will be reset. We poll for this
1452                          * particular condition. We wait for a maximum of 500ms
1453                          * for the operation to complete, if it's not complete
1454                          * by then we return error.
1455                          */
1456                         time = 0;
1457                         while (TRUE) {
1458                                 val64 = readq(&bar0->rti_command_mem);
1459                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1460                                         break;
1461                                 }
1462                                 if (time > 10) {
1463                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1464                                                   dev->name);
1465                                         return -1;
1466                                 }
1467                                 time++;
1468                                 msleep(50);
1469                         }
1470                 }
1471         }
1472
1473         /*
1474          * Initializing proper values as Pause threshold into all
1475          * the 8 Queues on Rx side.
1476          */
1477         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1478         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1479
1480         /* Disable RMAC PAD STRIPPING */
1481         add = &bar0->mac_cfg;
1482         val64 = readq(&bar0->mac_cfg);
1483         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1484         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1485         writel((u32) (val64), add);
1486         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1487         writel((u32) (val64 >> 32), (add + 4));
1488         val64 = readq(&bar0->mac_cfg);
1489
1490         /* Enable FCS stripping by adapter */
1491         add = &bar0->mac_cfg;
1492         val64 = readq(&bar0->mac_cfg);
1493         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1494         if (nic->device_type == XFRAME_II_DEVICE)
1495                 writeq(val64, &bar0->mac_cfg);
1496         else {
1497                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1498                 writel((u32) (val64), add);
1499                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1500                 writel((u32) (val64 >> 32), (add + 4));
1501         }
1502
1503         /*
1504          * Set the time value to be inserted in the pause frame
1505          * generated by xena.
1506          */
1507         val64 = readq(&bar0->rmac_pause_cfg);
1508         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1509         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1510         writeq(val64, &bar0->rmac_pause_cfg);
1511
1512         /*
1513          * Set the Threshold Limit for Generating the pause frame
1514          * If the amount of data in any Queue exceeds ratio of
1515          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1516          * pause frame is generated
1517          */
1518         val64 = 0;
1519         for (i = 0; i < 4; i++) {
1520                 val64 |=
1521                     (((u64) 0xFF00 | nic->mac_control.
1522                       mc_pause_threshold_q0q3)
1523                      << (i * 2 * 8));
1524         }
1525         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1526
1527         val64 = 0;
1528         for (i = 0; i < 4; i++) {
1529                 val64 |=
1530                     (((u64) 0xFF00 | nic->mac_control.
1531                       mc_pause_threshold_q4q7)
1532                      << (i * 2 * 8));
1533         }
1534         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1535
1536         /*
1537          * TxDMA will stop Read request if the number of read split has
1538          * exceeded the limit pointed by shared_splits
1539          */
1540         val64 = readq(&bar0->pic_control);
1541         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1542         writeq(val64, &bar0->pic_control);
1543
1544         if (nic->config.bus_speed == 266) {
1545                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1546                 writeq(0x0, &bar0->read_retry_delay);
1547                 writeq(0x0, &bar0->write_retry_delay);
1548         }
1549
1550         /*
1551          * Programming the Herc to split every write transaction
1552          * that does not start on an ADB to reduce disconnects.
1553          */
1554         if (nic->device_type == XFRAME_II_DEVICE) {
1555                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1556                 writeq(val64, &bar0->misc_control);
1557                 val64 = readq(&bar0->pic_control2);
1558                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1559                 writeq(val64, &bar0->pic_control2);
1560         }
1561
1562         /* Setting Link stability period to 64 ms */
1563         if (nic->device_type == XFRAME_II_DEVICE) {
1564                 val64 = MISC_LINK_STABILITY_PRD(3);
1565                 writeq(val64, &bar0->misc_control);
1566         }
1567
1568         return SUCCESS;
1569 }
1570 #define LINK_UP_DOWN_INTERRUPT          1
1571 #define MAC_RMAC_ERR_TIMER              2
1572
1573 static int s2io_link_fault_indication(nic_t *nic)
1574 {
1575         if (nic->intr_type != INTA)
1576                 return MAC_RMAC_ERR_TIMER;
1577         if (nic->device_type == XFRAME_II_DEVICE)
1578                 return LINK_UP_DOWN_INTERRUPT;
1579         else
1580                 return MAC_RMAC_ERR_TIMER;
1581 }
1582
1583 /**
1584  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1585  *  @nic: device private variable,
1586  *  @mask: A mask indicating which Intr block must be modified and,
1587  *  @flag: A flag indicating whether to enable or disable the Intrs.
1588  *  Description: This function will either disable or enable the interrupts
1589  *  depending on the flag argument. The mask argument can be used to
1590  *  enable/disable any Intr block.
1591  *  Return Value: NONE.
1592  */
1593
1594 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1595 {
1596         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1597         register u64 val64 = 0, temp64 = 0;
1598
1599         /*  Top level interrupt classification */
1600         /*  PIC Interrupts */
1601         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1602                 /*  Enable PIC Intrs in the general intr mask register */
1603                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1604                 if (flag == ENABLE_INTRS) {
1605                         temp64 = readq(&bar0->general_int_mask);
1606                         temp64 &= ~((u64) val64);
1607                         writeq(temp64, &bar0->general_int_mask);
1608                         /*
1609                          * If Hercules adapter enable GPIO otherwise
1610                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1611                          * interrupts for now.
1612                          * TODO
1613                          */
1614                         if (s2io_link_fault_indication(nic) ==
1615                                         LINK_UP_DOWN_INTERRUPT ) {
1616                                 temp64 = readq(&bar0->pic_int_mask);
1617                                 temp64 &= ~((u64) PIC_INT_GPIO);
1618                                 writeq(temp64, &bar0->pic_int_mask);
1619                                 temp64 = readq(&bar0->gpio_int_mask);
1620                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1621                                 writeq(temp64, &bar0->gpio_int_mask);
1622                         } else {
1623                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1624                         }
1625                         /*
1626                          * No MSI Support is available presently, so TTI and
1627                          * RTI interrupts are also disabled.
1628                          */
1629                 } else if (flag == DISABLE_INTRS) {
1630                         /*
1631                          * Disable PIC Intrs in the general
1632                          * intr mask register
1633                          */
1634                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1635                         temp64 = readq(&bar0->general_int_mask);
1636                         val64 |= temp64;
1637                         writeq(val64, &bar0->general_int_mask);
1638                 }
1639         }
1640
1641         /*  DMA Interrupts */
1642         /*  Enabling/Disabling Tx DMA interrupts */
1643         if (mask & TX_DMA_INTR) {
1644                 /* Enable TxDMA Intrs in the general intr mask register */
1645                 val64 = TXDMA_INT_M;
1646                 if (flag == ENABLE_INTRS) {
1647                         temp64 = readq(&bar0->general_int_mask);
1648                         temp64 &= ~((u64) val64);
1649                         writeq(temp64, &bar0->general_int_mask);
1650                         /*
1651                          * Keep all interrupts other than PFC interrupt
1652                          * and PCC interrupt disabled in DMA level.
1653                          */
1654                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1655                                                       TXDMA_PCC_INT_M);
1656                         writeq(val64, &bar0->txdma_int_mask);
1657                         /*
1658                          * Enable only the MISC error 1 interrupt in PFC block
1659                          */
1660                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1661                         writeq(val64, &bar0->pfc_err_mask);
1662                         /*
1663                          * Enable only the FB_ECC error interrupt in PCC block
1664                          */
1665                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1666                         writeq(val64, &bar0->pcc_err_mask);
1667                 } else if (flag == DISABLE_INTRS) {
1668                         /*
1669                          * Disable TxDMA Intrs in the general intr mask
1670                          * register
1671                          */
1672                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1673                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1674                         temp64 = readq(&bar0->general_int_mask);
1675                         val64 |= temp64;
1676                         writeq(val64, &bar0->general_int_mask);
1677                 }
1678         }
1679
1680         /*  Enabling/Disabling Rx DMA interrupts */
1681         if (mask & RX_DMA_INTR) {
1682                 /*  Enable RxDMA Intrs in the general intr mask register */
1683                 val64 = RXDMA_INT_M;
1684                 if (flag == ENABLE_INTRS) {
1685                         temp64 = readq(&bar0->general_int_mask);
1686                         temp64 &= ~((u64) val64);
1687                         writeq(temp64, &bar0->general_int_mask);
1688                         /*
1689                          * All RxDMA block interrupts are disabled for now
1690                          * TODO
1691                          */
1692                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1693                 } else if (flag == DISABLE_INTRS) {
1694                         /*
1695                          * Disable RxDMA Intrs in the general intr mask
1696                          * register
1697                          */
1698                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1699                         temp64 = readq(&bar0->general_int_mask);
1700                         val64 |= temp64;
1701                         writeq(val64, &bar0->general_int_mask);
1702                 }
1703         }
1704
1705         /*  MAC Interrupts */
1706         /*  Enabling/Disabling MAC interrupts */
1707         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1708                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1709                 if (flag == ENABLE_INTRS) {
1710                         temp64 = readq(&bar0->general_int_mask);
1711                         temp64 &= ~((u64) val64);
1712                         writeq(temp64, &bar0->general_int_mask);
1713                         /*
1714                          * All MAC block error interrupts are disabled for now
1715                          * TODO
1716                          */
1717                 } else if (flag == DISABLE_INTRS) {
1718                         /*
1719                          * Disable MAC Intrs in the general intr mask register
1720                          */
1721                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1722                         writeq(DISABLE_ALL_INTRS,
1723                                &bar0->mac_rmac_err_mask);
1724
1725                         temp64 = readq(&bar0->general_int_mask);
1726                         val64 |= temp64;
1727                         writeq(val64, &bar0->general_int_mask);
1728                 }
1729         }
1730
1731         /*  XGXS Interrupts */
1732         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1733                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1734                 if (flag == ENABLE_INTRS) {
1735                         temp64 = readq(&bar0->general_int_mask);
1736                         temp64 &= ~((u64) val64);
1737                         writeq(temp64, &bar0->general_int_mask);
1738                         /*
1739                          * All XGXS block error interrupts are disabled for now
1740                          * TODO
1741                          */
1742                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1743                 } else if (flag == DISABLE_INTRS) {
1744                         /*
1745                          * Disable MC Intrs in the general intr mask register
1746                          */
1747                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1748                         temp64 = readq(&bar0->general_int_mask);
1749                         val64 |= temp64;
1750                         writeq(val64, &bar0->general_int_mask);
1751                 }
1752         }
1753
1754         /*  Memory Controller(MC) interrupts */
1755         if (mask & MC_INTR) {
1756                 val64 = MC_INT_M;
1757                 if (flag == ENABLE_INTRS) {
1758                         temp64 = readq(&bar0->general_int_mask);
1759                         temp64 &= ~((u64) val64);
1760                         writeq(temp64, &bar0->general_int_mask);
1761                         /*
1762                          * Enable all MC Intrs.
1763                          */
1764                         writeq(0x0, &bar0->mc_int_mask);
1765                         writeq(0x0, &bar0->mc_err_mask);
1766                 } else if (flag == DISABLE_INTRS) {
1767                         /*
1768                          * Disable MC Intrs in the general intr mask register
1769                          */
1770                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1771                         temp64 = readq(&bar0->general_int_mask);
1772                         val64 |= temp64;
1773                         writeq(val64, &bar0->general_int_mask);
1774                 }
1775         }
1776
1777
1778         /*  Tx traffic interrupts */
1779         if (mask & TX_TRAFFIC_INTR) {
1780                 val64 = TXTRAFFIC_INT_M;
1781                 if (flag == ENABLE_INTRS) {
1782                         temp64 = readq(&bar0->general_int_mask);
1783                         temp64 &= ~((u64) val64);
1784                         writeq(temp64, &bar0->general_int_mask);
1785                         /*
1786                          * Enable all the Tx side interrupts
1787                          * writing 0 Enables all 64 TX interrupt levels
1788                          */
1789                         writeq(0x0, &bar0->tx_traffic_mask);
1790                 } else if (flag == DISABLE_INTRS) {
1791                         /*
1792                          * Disable Tx Traffic Intrs in the general intr mask
1793                          * register.
1794                          */
1795                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1796                         temp64 = readq(&bar0->general_int_mask);
1797                         val64 |= temp64;
1798                         writeq(val64, &bar0->general_int_mask);
1799                 }
1800         }
1801
1802         /*  Rx traffic interrupts */
1803         if (mask & RX_TRAFFIC_INTR) {
1804                 val64 = RXTRAFFIC_INT_M;
1805                 if (flag == ENABLE_INTRS) {
1806                         temp64 = readq(&bar0->general_int_mask);
1807                         temp64 &= ~((u64) val64);
1808                         writeq(temp64, &bar0->general_int_mask);
1809                         /* writing 0 Enables all 8 RX interrupt levels */
1810                         writeq(0x0, &bar0->rx_traffic_mask);
1811                 } else if (flag == DISABLE_INTRS) {
1812                         /*
1813                          * Disable Rx Traffic Intrs in the general intr mask
1814                          * register.
1815                          */
1816                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1817                         temp64 = readq(&bar0->general_int_mask);
1818                         val64 |= temp64;
1819                         writeq(val64, &bar0->general_int_mask);
1820                 }
1821         }
1822 }
1823
1824 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1825 {
1826         int ret = 0;
1827
1828         if (flag == FALSE) {
1829                 if ((!herc && (rev_id >= 4)) || herc) {
1830                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1831                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1832                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1833                                 ret = 1;
1834                         }
1835                 }else {
1836                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1837                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1838                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1839                                 ret = 1;
1840                         }
1841                 }
1842         } else {
1843                 if ((!herc && (rev_id >= 4)) || herc) {
1844                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1845                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1846                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1847                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1848                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1849                                 ret = 1;
1850                         }
1851                 } else {
1852                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1853                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1854                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1855                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1856                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1857                                 ret = 1;
1858                         }
1859                 }
1860         }
1861
1862         return ret;
1863 }
1864 /**
1865  *  verify_xena_quiescence - Checks whether the H/W is ready
1866  *  @val64 :  Value read from adapter status register.
1867  *  @flag : indicates if the adapter enable bit was ever written once
1868  *  before.
1869  *  Description: Returns whether the H/W is ready to go or not. Depending
1870  *  on whether adapter enable bit was written or not the comparison
1871  *  differs and the calling function passes the input argument flag to
1872  *  indicate this.
1873  *  Return: 1 If xena is quiescence
1874  *          0 If Xena is not quiescence
1875  */
1876
1877 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1878 {
1879         int ret = 0, herc;
1880         u64 tmp64 = ~((u64) val64);
1881         int rev_id = get_xena_rev_id(sp->pdev);
1882
1883         herc = (sp->device_type == XFRAME_II_DEVICE);
1884         if (!
1885             (tmp64 &
1886              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1887               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1888               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1889               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1890               ADAPTER_STATUS_P_PLL_LOCK))) {
1891                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1892         }
1893
1894         return ret;
1895 }
1896
1897 /**
1898  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1899  * @sp: Pointer to device specifc structure
1900  * Description :
1901  * New procedure to clear mac address reading  problems on Alpha platforms
1902  *
1903  */
1904
1905 static void fix_mac_address(nic_t * sp)
1906 {
1907         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1908         u64 val64;
1909         int i = 0;
1910
1911         while (fix_mac[i] != END_SIGN) {
1912                 writeq(fix_mac[i++], &bar0->gpio_control);
1913                 udelay(10);
1914                 val64 = readq(&bar0->gpio_control);
1915         }
1916 }
1917
1918 /**
1919  *  start_nic - Turns the device on
1920  *  @nic : device private variable.
1921  *  Description:
1922  *  This function actually turns the device on. Before this  function is
1923  *  called,all Registers are configured from their reset states
1924  *  and shared memory is allocated but the NIC is still quiescent. On
1925  *  calling this function, the device interrupts are cleared and the NIC is
1926  *  literally switched on by writing into the adapter control register.
1927  *  Return Value:
1928  *  SUCCESS on success and -1 on failure.
1929  */
1930
1931 static int start_nic(struct s2io_nic *nic)
1932 {
1933         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1934         struct net_device *dev = nic->dev;
1935         register u64 val64 = 0;
1936         u16 interruptible;
1937         u16 subid, i;
1938         mac_info_t *mac_control;
1939         struct config_param *config;
1940
1941         mac_control = &nic->mac_control;
1942         config = &nic->config;
1943
1944         /*  PRC Initialization and configuration */
1945         for (i = 0; i < config->rx_ring_num; i++) {
1946                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1947                        &bar0->prc_rxd0_n[i]);
1948
1949                 val64 = readq(&bar0->prc_ctrl_n[i]);
1950                 if (nic->config.bimodal)
1951                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1952                 if (nic->rxd_mode == RXD_MODE_1)
1953                         val64 |= PRC_CTRL_RC_ENABLED;
1954                 else
1955                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1956                 if (nic->device_type == XFRAME_II_DEVICE)
1957                         val64 |= PRC_CTRL_GROUP_READS;
1958                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1959                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1960                 writeq(val64, &bar0->prc_ctrl_n[i]);
1961         }
1962
1963         if (nic->rxd_mode == RXD_MODE_3B) {
1964                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1965                 val64 = readq(&bar0->rx_pa_cfg);
1966                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1967                 writeq(val64, &bar0->rx_pa_cfg);
1968         }
1969
1970         /*
1971          * Enabling MC-RLDRAM. After enabling the device, we timeout
1972          * for around 100ms, which is approximately the time required
1973          * for the device to be ready for operation.
1974          */
1975         val64 = readq(&bar0->mc_rldram_mrs);
1976         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1977         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1978         val64 = readq(&bar0->mc_rldram_mrs);
1979
1980         msleep(100);    /* Delay by around 100 ms. */
1981
1982         /* Enabling ECC Protection. */
1983         val64 = readq(&bar0->adapter_control);
1984         val64 &= ~ADAPTER_ECC_EN;
1985         writeq(val64, &bar0->adapter_control);
1986
1987         /*
1988          * Clearing any possible Link state change interrupts that
1989          * could have popped up just before Enabling the card.
1990          */
1991         val64 = readq(&bar0->mac_rmac_err_reg);
1992         if (val64)
1993                 writeq(val64, &bar0->mac_rmac_err_reg);
1994
1995         /*
1996          * Verify if the device is ready to be enabled, if so enable
1997          * it.
1998          */
1999         val64 = readq(&bar0->adapter_status);
2000         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2001                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2002                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2003                           (unsigned long long) val64);
2004                 return FAILURE;
2005         }
2006
2007         /*  Enable select interrupts */
2008         if (nic->intr_type != INTA)
2009                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2010         else {
2011                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2012                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2013                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2014                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
2015         }
2016
2017         /*
2018          * With some switches, link might be already up at this point.
2019          * Because of this weird behavior, when we enable laser,
2020          * we may not get link. We need to handle this. We cannot
2021          * figure out which switch is misbehaving. So we are forced to
2022          * make a global change.
2023          */
2024
2025         /* Enabling Laser. */
2026         val64 = readq(&bar0->adapter_control);
2027         val64 |= ADAPTER_EOI_TX_ON;
2028         writeq(val64, &bar0->adapter_control);
2029
2030         /* SXE-002: Initialize link and activity LED */
2031         subid = nic->pdev->subsystem_device;
2032         if (((subid & 0xFF) >= 0x07) &&
2033             (nic->device_type == XFRAME_I_DEVICE)) {
2034                 val64 = readq(&bar0->gpio_control);
2035                 val64 |= 0x0000800000000000ULL;
2036                 writeq(val64, &bar0->gpio_control);
2037                 val64 = 0x0411040400000000ULL;
2038                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2039         }
2040
2041         /*
2042          * Don't see link state interrupts on certain switches, so
2043          * directly scheduling a link state task from here.
2044          */
2045         schedule_work(&nic->set_link_task);
2046
2047         return SUCCESS;
2048 }
2049 /**
2050  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2051  */
2052 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2053 {
2054         nic_t *nic = fifo_data->nic;
2055         struct sk_buff *skb;
2056         TxD_t *txds;
2057         u16 j, frg_cnt;
2058
2059         txds = txdlp;
2060         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2061                 pci_unmap_single(nic->pdev, (dma_addr_t)
2062                         txds->Buffer_Pointer, sizeof(u64),
2063                         PCI_DMA_TODEVICE);
2064                 txds++;
2065         }
2066
2067         skb = (struct sk_buff *) ((unsigned long)
2068                         txds->Host_Control);
2069         if (!skb) {
2070                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2071                 return NULL;
2072         }
2073         pci_unmap_single(nic->pdev, (dma_addr_t)
2074                          txds->Buffer_Pointer,
2075                          skb->len - skb->data_len,
2076                          PCI_DMA_TODEVICE);
2077         frg_cnt = skb_shinfo(skb)->nr_frags;
2078         if (frg_cnt) {
2079                 txds++;
2080                 for (j = 0; j < frg_cnt; j++, txds++) {
2081                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2082                         if (!txds->Buffer_Pointer)
2083                                 break;
2084                         pci_unmap_page(nic->pdev, (dma_addr_t)
2085                                         txds->Buffer_Pointer,
2086                                        frag->size, PCI_DMA_TODEVICE);
2087                 }
2088         }
2089         txdlp->Host_Control = 0;
2090         return(skb);
2091 }
2092
2093 /**
2094  *  free_tx_buffers - Free all queued Tx buffers
2095  *  @nic : device private variable.
2096  *  Description:
2097  *  Free all queued Tx buffers.
2098  *  Return Value: void
2099 */
2100
2101 static void free_tx_buffers(struct s2io_nic *nic)
2102 {
2103         struct net_device *dev = nic->dev;
2104         struct sk_buff *skb;
2105         TxD_t *txdp;
2106         int i, j;
2107         mac_info_t *mac_control;
2108         struct config_param *config;
2109         int cnt = 0;
2110
2111         mac_control = &nic->mac_control;
2112         config = &nic->config;
2113
2114         for (i = 0; i < config->tx_fifo_num; i++) {
2115                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2116                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2117                             list_virt_addr;
2118                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2119                         if (skb) {
2120                                 dev_kfree_skb(skb);
2121                                 cnt++;
2122                         }
2123                 }
2124                 DBG_PRINT(INTR_DBG,
2125                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2126                           dev->name, cnt, i);
2127                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2128                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2129         }
2130 }
2131
2132 /**
2133  *   stop_nic -  To stop the nic
2134  *   @nic ; device private variable.
2135  *   Description:
2136  *   This function does exactly the opposite of what the start_nic()
2137  *   function does. This function is called to stop the device.
2138  *   Return Value:
2139  *   void.
2140  */
2141
2142 static void stop_nic(struct s2io_nic *nic)
2143 {
2144         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2145         register u64 val64 = 0;
2146         u16 interruptible, i;
2147         mac_info_t *mac_control;
2148         struct config_param *config;
2149
2150         mac_control = &nic->mac_control;
2151         config = &nic->config;
2152
2153         /*  Disable all interrupts */
2154         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2155         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2156         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2157         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2158
2159         /*  Disable PRCs */
2160         for (i = 0; i < config->rx_ring_num; i++) {
2161                 val64 = readq(&bar0->prc_ctrl_n[i]);
2162                 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
2163                 writeq(val64, &bar0->prc_ctrl_n[i]);
2164         }
2165 }
2166
2167 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2168 {
2169         struct net_device *dev = nic->dev;
2170         struct sk_buff *frag_list;
2171         void *tmp;
2172
2173         /* Buffer-1 receives L3/L4 headers */
2174         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2175                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2176                         PCI_DMA_FROMDEVICE);
2177
2178         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2179         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2180         if (skb_shinfo(skb)->frag_list == NULL) {
2181                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2182                 return -ENOMEM ;
2183         }
2184         frag_list = skb_shinfo(skb)->frag_list;
2185         frag_list->next = NULL;
2186         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2187         frag_list->data = tmp;
2188         frag_list->tail = tmp;
2189
2190         /* Buffer-2 receives L4 data payload */
2191         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2192                                 frag_list->data, dev->mtu,
2193                                 PCI_DMA_FROMDEVICE);
2194         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2195         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2196
2197         return SUCCESS;
2198 }
2199
2200 /**
2201  *  fill_rx_buffers - Allocates the Rx side skbs
2202  *  @nic:  device private variable
2203  *  @ring_no: ring number
2204  *  Description:
2205  *  The function allocates Rx side skbs and puts the physical
2206  *  address of these buffers into the RxD buffer pointers, so that the NIC
2207  *  can DMA the received frame into these locations.
2208  *  The NIC supports 3 receive modes, viz
2209  *  1. single buffer,
2210  *  2. three buffer and
2211  *  3. Five buffer modes.
2212  *  Each mode defines how many fragments the received frame will be split
2213  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2214  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2215  *  is split into 3 fragments. As of now only single buffer mode is
2216  *  supported.
2217  *   Return Value:
2218  *  SUCCESS on success or an appropriate -ve value on failure.
2219  */
2220
2221 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2222 {
2223         struct net_device *dev = nic->dev;
2224         struct sk_buff *skb;
2225         RxD_t *rxdp;
2226         int off, off1, size, block_no, block_no1;
2227         u32 alloc_tab = 0;
2228         u32 alloc_cnt;
2229         mac_info_t *mac_control;
2230         struct config_param *config;
2231         u64 tmp;
2232         buffAdd_t *ba;
2233 #ifndef CONFIG_S2IO_NAPI
2234         unsigned long flags;
2235 #endif
2236         RxD_t *first_rxdp = NULL;
2237
2238         mac_control = &nic->mac_control;
2239         config = &nic->config;
2240         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2241             atomic_read(&nic->rx_bufs_left[ring_no]);
2242
2243         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2244         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2245         while (alloc_tab < alloc_cnt) {
2246                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2247                     block_index;
2248                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2249
2250                 rxdp = mac_control->rings[ring_no].
2251                                 rx_blocks[block_no].rxds[off].virt_addr;
2252
2253                 if ((block_no == block_no1) && (off == off1) &&
2254                                         (rxdp->Host_Control)) {
2255                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2256                                   dev->name);
2257                         DBG_PRINT(INTR_DBG, " info equated\n");
2258                         goto end;
2259                 }
2260                 if (off && (off == rxd_count[nic->rxd_mode])) {
2261                         mac_control->rings[ring_no].rx_curr_put_info.
2262                             block_index++;
2263                         if (mac_control->rings[ring_no].rx_curr_put_info.
2264                             block_index == mac_control->rings[ring_no].
2265                                         block_count)
2266                                 mac_control->rings[ring_no].rx_curr_put_info.
2267                                         block_index = 0;
2268                         block_no = mac_control->rings[ring_no].
2269                                         rx_curr_put_info.block_index;
2270                         if (off == rxd_count[nic->rxd_mode])
2271                                 off = 0;
2272                         mac_control->rings[ring_no].rx_curr_put_info.
2273                                 offset = off;
2274                         rxdp = mac_control->rings[ring_no].
2275                                 rx_blocks[block_no].block_virt_addr;
2276                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2277                                   dev->name, rxdp);
2278                 }
2279 #ifndef CONFIG_S2IO_NAPI
2280                 spin_lock_irqsave(&nic->put_lock, flags);
2281                 mac_control->rings[ring_no].put_pos =
2282                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2283                 spin_unlock_irqrestore(&nic->put_lock, flags);
2284 #endif
2285                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2286                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2287                                 (rxdp->Control_2 & BIT(0)))) {
2288                         mac_control->rings[ring_no].rx_curr_put_info.
2289                                         offset = off;
2290                         goto end;
2291                 }
2292                 /* calculate size of skb based on ring mode */
2293                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2294                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2295                 if (nic->rxd_mode == RXD_MODE_1)
2296                         size += NET_IP_ALIGN;
2297                 else if (nic->rxd_mode == RXD_MODE_3B)
2298                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2299                 else
2300                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2301
2302                 /* allocate skb */
2303                 skb = dev_alloc_skb(size);
2304                 if(!skb) {
2305                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2306                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2307                         if (first_rxdp) {
2308                                 wmb();
2309                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2310                         }
2311                         return -ENOMEM ;
2312                 }
2313                 if (nic->rxd_mode == RXD_MODE_1) {
2314                         /* 1 buffer mode - normal operation mode */
2315                         memset(rxdp, 0, sizeof(RxD1_t));
2316                         skb_reserve(skb, NET_IP_ALIGN);
2317                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2318                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2319                                 PCI_DMA_FROMDEVICE);
2320                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2321
2322                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2323                         /*
2324                          * 2 or 3 buffer mode -
2325                          * Both 2 buffer mode and 3 buffer mode provides 128
2326                          * byte aligned receive buffers.
2327                          *
2328                          * 3 buffer mode provides header separation where in
2329                          * skb->data will have L3/L4 headers where as
2330                          * skb_shinfo(skb)->frag_list will have the L4 data
2331                          * payload
2332                          */
2333
2334                         memset(rxdp, 0, sizeof(RxD3_t));
2335                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2336                         skb_reserve(skb, BUF0_LEN);
2337                         tmp = (u64)(unsigned long) skb->data;
2338                         tmp += ALIGN_SIZE;
2339                         tmp &= ~ALIGN_SIZE;
2340                         skb->data = (void *) (unsigned long)tmp;
2341                         skb->tail = (void *) (unsigned long)tmp;
2342
2343                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2344                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2345                                            PCI_DMA_FROMDEVICE);
2346                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2347                         if (nic->rxd_mode == RXD_MODE_3B) {
2348                                 /* Two buffer mode */
2349
2350                                 /*
2351                                  * Buffer2 will have L3/L4 header plus
2352                                  * L4 payload
2353                                  */
2354                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2355                                 (nic->pdev, skb->data, dev->mtu + 4,
2356                                                 PCI_DMA_FROMDEVICE);
2357
2358                                 /* Buffer-1 will be dummy buffer not used */
2359                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2360                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2361                                         PCI_DMA_FROMDEVICE);
2362                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2363                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2364                                                                 (dev->mtu + 4);
2365                         } else {
2366                                 /* 3 buffer mode */
2367                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2368                                         dev_kfree_skb_irq(skb);
2369                                         if (first_rxdp) {
2370                                                 wmb();
2371                                                 first_rxdp->Control_1 |=
2372                                                         RXD_OWN_XENA;
2373                                         }
2374                                         return -ENOMEM ;
2375                                 }
2376                         }
2377                         rxdp->Control_2 |= BIT(0);
2378                 }
2379                 rxdp->Host_Control = (unsigned long) (skb);
2380                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2381                         rxdp->Control_1 |= RXD_OWN_XENA;
2382                 off++;
2383                 if (off == (rxd_count[nic->rxd_mode] + 1))
2384                         off = 0;
2385                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2386
2387                 rxdp->Control_2 |= SET_RXD_MARKER;
2388                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2389                         if (first_rxdp) {
2390                                 wmb();
2391                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2392                         }
2393                         first_rxdp = rxdp;
2394                 }
2395                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2396                 alloc_tab++;
2397         }
2398
2399       end:
2400         /* Transfer ownership of first descriptor to adapter just before
2401          * exiting. Before that, use memory barrier so that ownership
2402          * and other fields are seen by adapter correctly.
2403          */
2404         if (first_rxdp) {
2405                 wmb();
2406                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2407         }
2408
2409         return SUCCESS;
2410 }
2411
2412 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2413 {
2414         struct net_device *dev = sp->dev;
2415         int j;
2416         struct sk_buff *skb;
2417         RxD_t *rxdp;
2418         mac_info_t *mac_control;
2419         buffAdd_t *ba;
2420
2421         mac_control = &sp->mac_control;
2422         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2423                 rxdp = mac_control->rings[ring_no].
2424                                 rx_blocks[blk].rxds[j].virt_addr;
2425                 skb = (struct sk_buff *)
2426                         ((unsigned long) rxdp->Host_Control);
2427                 if (!skb) {
2428                         continue;
2429                 }
2430                 if (sp->rxd_mode == RXD_MODE_1) {
2431                         pci_unmap_single(sp->pdev, (dma_addr_t)
2432                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2433                                  dev->mtu +
2434                                  HEADER_ETHERNET_II_802_3_SIZE
2435                                  + HEADER_802_2_SIZE +
2436                                  HEADER_SNAP_SIZE,
2437                                  PCI_DMA_FROMDEVICE);
2438                         memset(rxdp, 0, sizeof(RxD1_t));
2439                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2440                         ba = &mac_control->rings[ring_no].
2441                                 ba[blk][j];
2442                         pci_unmap_single(sp->pdev, (dma_addr_t)
2443                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2444                                  BUF0_LEN,
2445                                  PCI_DMA_FROMDEVICE);
2446                         pci_unmap_single(sp->pdev, (dma_addr_t)
2447                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2448                                  BUF1_LEN,
2449                                  PCI_DMA_FROMDEVICE);
2450                         pci_unmap_single(sp->pdev, (dma_addr_t)
2451                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2452                                  dev->mtu + 4,
2453                                  PCI_DMA_FROMDEVICE);
2454                         memset(rxdp, 0, sizeof(RxD3_t));
2455                 } else {
2456                         pci_unmap_single(sp->pdev, (dma_addr_t)
2457                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2458                                 PCI_DMA_FROMDEVICE);
2459                         pci_unmap_single(sp->pdev, (dma_addr_t)
2460                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2461                                 l3l4hdr_size + 4,
2462                                 PCI_DMA_FROMDEVICE);
2463                         pci_unmap_single(sp->pdev, (dma_addr_t)
2464                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2465                                 PCI_DMA_FROMDEVICE);
2466                         memset(rxdp, 0, sizeof(RxD3_t));
2467                 }
2468                 dev_kfree_skb(skb);
2469                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2470         }
2471 }
2472
2473 /**
2474  *  free_rx_buffers - Frees all Rx buffers
2475  *  @sp: device private variable.
2476  *  Description:
2477  *  This function will free all Rx buffers allocated by host.
2478  *  Return Value:
2479  *  NONE.
2480  */
2481
2482 static void free_rx_buffers(struct s2io_nic *sp)
2483 {
2484         struct net_device *dev = sp->dev;
2485         int i, blk = 0, buf_cnt = 0;
2486         mac_info_t *mac_control;
2487         struct config_param *config;
2488
2489         mac_control = &sp->mac_control;
2490         config = &sp->config;
2491
2492         for (i = 0; i < config->rx_ring_num; i++) {
2493                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2494                         free_rxd_blk(sp,i,blk);
2495
2496                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2497                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2498                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2499                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2500                 atomic_set(&sp->rx_bufs_left[i], 0);
2501                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2502                           dev->name, buf_cnt, i);
2503         }
2504 }
2505
2506 /**
2507  * s2io_poll - Rx interrupt handler for NAPI support
2508  * @dev : pointer to the device structure.
2509  * @budget : The number of packets that were budgeted to be processed
2510  * during  one pass through the 'Poll" function.
2511  * Description:
2512  * Comes into picture only if NAPI support has been incorporated. It does
2513  * the same thing that rx_intr_handler does, but not in a interrupt context
2514  * also It will process only a given number of packets.
2515  * Return value:
2516  * 0 on success and 1 if there are No Rx packets to be processed.
2517  */
2518
2519 #if defined(CONFIG_S2IO_NAPI)
2520 static int s2io_poll(struct net_device *dev, int *budget)
2521 {
2522         nic_t *nic = dev->priv;
2523         int pkt_cnt = 0, org_pkts_to_process;
2524         mac_info_t *mac_control;
2525         struct config_param *config;
2526         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2527         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2528         int i;
2529
2530         atomic_inc(&nic->isr_cnt);
2531         mac_control = &nic->mac_control;
2532         config = &nic->config;
2533
2534         nic->pkts_to_process = *budget;
2535         if (nic->pkts_to_process > dev->quota)
2536                 nic->pkts_to_process = dev->quota;
2537         org_pkts_to_process = nic->pkts_to_process;
2538
2539         writeq(val64, &bar0->rx_traffic_int);
2540         val64 = readl(&bar0->rx_traffic_int);
2541
2542         for (i = 0; i < config->rx_ring_num; i++) {
2543                 rx_intr_handler(&mac_control->rings[i]);
2544                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2545                 if (!nic->pkts_to_process) {
2546                         /* Quota for the current iteration has been met */
2547                         goto no_rx;
2548                 }
2549         }
2550         if (!pkt_cnt)
2551                 pkt_cnt = 1;
2552
2553         dev->quota -= pkt_cnt;
2554         *budget -= pkt_cnt;
2555         netif_rx_complete(dev);
2556
2557         for (i = 0; i < config->rx_ring_num; i++) {
2558                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2559                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2560                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2561                         break;
2562                 }
2563         }
2564         /* Re enable the Rx interrupts. */
2565         en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2566         atomic_dec(&nic->isr_cnt);
2567         return 0;
2568
2569 no_rx:
2570         dev->quota -= pkt_cnt;
2571         *budget -= pkt_cnt;
2572
2573         for (i = 0; i < config->rx_ring_num; i++) {
2574                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2575                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2576                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2577                         break;
2578                 }
2579         }
2580         atomic_dec(&nic->isr_cnt);
2581         return 1;
2582 }
2583 #endif
2584
2585 /**
2586  *  rx_intr_handler - Rx interrupt handler
2587  *  @nic: device private variable.
2588  *  Description:
2589  *  If the interrupt is because of a received frame or if the
2590  *  receive ring contains fresh as yet un-processed frames,this function is
2591  *  called. It picks out the RxD at which place the last Rx processing had
2592  *  stopped and sends the skb to the OSM's Rx handler and then increments
2593  *  the offset.
2594  *  Return Value:
2595  *  NONE.
2596  */
2597 static void rx_intr_handler(ring_info_t *ring_data)
2598 {
2599         nic_t *nic = ring_data->nic;
2600         struct net_device *dev = (struct net_device *) nic->dev;
2601         int get_block, put_block, put_offset;
2602         rx_curr_get_info_t get_info, put_info;
2603         RxD_t *rxdp;
2604         struct sk_buff *skb;
2605 #ifndef CONFIG_S2IO_NAPI
2606         int pkt_cnt = 0;
2607 #endif
2608         int i;
2609
2610         spin_lock(&nic->rx_lock);
2611         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2612                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2613                           __FUNCTION__, dev->name);
2614                 spin_unlock(&nic->rx_lock);
2615                 return;
2616         }
2617
2618         get_info = ring_data->rx_curr_get_info;
2619         get_block = get_info.block_index;
2620         put_info = ring_data->rx_curr_put_info;
2621         put_block = put_info.block_index;
2622         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2623 #ifndef CONFIG_S2IO_NAPI
2624         spin_lock(&nic->put_lock);
2625         put_offset = ring_data->put_pos;
2626         spin_unlock(&nic->put_lock);
2627 #else
2628         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2629                 put_info.offset;
2630 #endif
2631         while (RXD_IS_UP2DT(rxdp)) {
2632                 /* If your are next to put index then it's FIFO full condition */
2633                 if ((get_block == put_block) &&
2634                     (get_info.offset + 1) == put_info.offset) {
2635                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2636                         break;
2637                 }
2638                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2639                 if (skb == NULL) {
2640                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2641                                   dev->name);
2642                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2643                         spin_unlock(&nic->rx_lock);
2644                         return;
2645                 }
2646                 if (nic->rxd_mode == RXD_MODE_1) {
2647                         pci_unmap_single(nic->pdev, (dma_addr_t)
2648                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2649                                  dev->mtu +
2650                                  HEADER_ETHERNET_II_802_3_SIZE +
2651                                  HEADER_802_2_SIZE +
2652                                  HEADER_SNAP_SIZE,
2653                                  PCI_DMA_FROMDEVICE);
2654                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2655                         pci_unmap_single(nic->pdev, (dma_addr_t)
2656                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2657                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2658                         pci_unmap_single(nic->pdev, (dma_addr_t)
2659                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2660                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2661                         pci_unmap_single(nic->pdev, (dma_addr_t)
2662                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2663                                  dev->mtu + 4,
2664                                  PCI_DMA_FROMDEVICE);
2665                 } else {
2666                         pci_unmap_single(nic->pdev, (dma_addr_t)
2667                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2668                                          PCI_DMA_FROMDEVICE);
2669                         pci_unmap_single(nic->pdev, (dma_addr_t)
2670                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2671                                          l3l4hdr_size + 4,
2672                                          PCI_DMA_FROMDEVICE);
2673                         pci_unmap_single(nic->pdev, (dma_addr_t)
2674                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2675                                          dev->mtu, PCI_DMA_FROMDEVICE);
2676                 }
2677                 prefetch(skb->data);
2678                 rx_osm_handler(ring_data, rxdp);
2679                 get_info.offset++;
2680                 ring_data->rx_curr_get_info.offset = get_info.offset;
2681                 rxdp = ring_data->rx_blocks[get_block].
2682                                 rxds[get_info.offset].virt_addr;
2683                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2684                         get_info.offset = 0;
2685                         ring_data->rx_curr_get_info.offset = get_info.offset;
2686                         get_block++;
2687                         if (get_block == ring_data->block_count)
2688                                 get_block = 0;
2689                         ring_data->rx_curr_get_info.block_index = get_block;
2690                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2691                 }
2692
2693 #ifdef CONFIG_S2IO_NAPI
2694                 nic->pkts_to_process -= 1;
2695                 if (!nic->pkts_to_process)
2696                         break;
2697 #else
2698                 pkt_cnt++;
2699                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2700                         break;
2701 #endif
2702         }
2703         if (nic->lro) {
2704                 /* Clear all LRO sessions before exiting */
2705                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2706                         lro_t *lro = &nic->lro0_n[i];
2707                         if (lro->in_use) {
2708                                 update_L3L4_header(nic, lro);
2709                                 queue_rx_frame(lro->parent);
2710                                 clear_lro_session(lro);
2711                         }
2712                 }
2713         }
2714
2715         spin_unlock(&nic->rx_lock);
2716 }
2717
2718 /**
2719  *  tx_intr_handler - Transmit interrupt handler
2720  *  @nic : device private variable
2721  *  Description:
2722  *  If an interrupt was raised to indicate DMA complete of the
2723  *  Tx packet, this function is called. It identifies the last TxD
2724  *  whose buffer was freed and frees all skbs whose data have already
2725  *  DMA'ed into the NICs internal memory.
2726  *  Return Value:
2727  *  NONE
2728  */
2729
2730 static void tx_intr_handler(fifo_info_t *fifo_data)
2731 {
2732         nic_t *nic = fifo_data->nic;
2733         struct net_device *dev = (struct net_device *) nic->dev;
2734         tx_curr_get_info_t get_info, put_info;
2735         struct sk_buff *skb;
2736         TxD_t *txdlp;
2737
2738         get_info = fifo_data->tx_curr_get_info;
2739         put_info = fifo_data->tx_curr_put_info;
2740         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2741             list_virt_addr;
2742         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2743                (get_info.offset != put_info.offset) &&
2744                (txdlp->Host_Control)) {
2745                 /* Check for TxD errors */
2746                 if (txdlp->Control_1 & TXD_T_CODE) {
2747                         unsigned long long err;
2748                         err = txdlp->Control_1 & TXD_T_CODE;
2749                         if ((err >> 48) == 0xA) {
2750                                 DBG_PRINT(TX_DBG, "TxD returned due \
2751 to loss of link\n");
2752                         }
2753                         else {
2754                                 DBG_PRINT(ERR_DBG, "***TxD error \
2755 %llx\n", err);
2756                         }
2757                 }
2758
2759                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2760                 if (skb == NULL) {
2761                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2762                         __FUNCTION__);
2763                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2764                         return;
2765                 }
2766
2767                 /* Updating the statistics block */
2768                 nic->stats.tx_bytes += skb->len;
2769                 dev_kfree_skb_irq(skb);
2770
2771                 get_info.offset++;
2772                 if (get_info.offset == get_info.fifo_len + 1)
2773                         get_info.offset = 0;
2774                 txdlp = (TxD_t *) fifo_data->list_info
2775                     [get_info.offset].list_virt_addr;
2776                 fifo_data->tx_curr_get_info.offset =
2777                     get_info.offset;
2778         }
2779
2780         spin_lock(&nic->tx_lock);
2781         if (netif_queue_stopped(dev))
2782                 netif_wake_queue(dev);
2783         spin_unlock(&nic->tx_lock);
2784 }
2785
2786 /**
2787  *  alarm_intr_handler - Alarm Interrrupt handler
2788  *  @nic: device private variable
2789  *  Description: If the interrupt was neither because of Rx packet or Tx
2790  *  complete, this function is called. If the interrupt was to indicate
2791  *  a loss of link, the OSM link status handler is invoked for any other
2792  *  alarm interrupt the block that raised the interrupt is displayed
2793  *  and a H/W reset is issued.
2794  *  Return Value:
2795  *  NONE
2796 */
2797
2798 static void alarm_intr_handler(struct s2io_nic *nic)
2799 {
2800         struct net_device *dev = (struct net_device *) nic->dev;
2801         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2802         register u64 val64 = 0, err_reg = 0;
2803
2804         /* Handling link status change error Intr */
2805         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2806                 err_reg = readq(&bar0->mac_rmac_err_reg);
2807                 writeq(err_reg, &bar0->mac_rmac_err_reg);
2808                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2809                         schedule_work(&nic->set_link_task);
2810                 }
2811         }
2812
2813         /* Handling Ecc errors */
2814         val64 = readq(&bar0->mc_err_reg);
2815         writeq(val64, &bar0->mc_err_reg);
2816         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2817                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2818                         nic->mac_control.stats_info->sw_stat.
2819                                 double_ecc_errs++;
2820                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
2821                                   dev->name);
2822                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
2823                         if (nic->device_type != XFRAME_II_DEVICE) {
2824                                 /* Reset XframeI only if critical error */
2825                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
2826                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
2827                                         netif_stop_queue(dev);
2828                                         schedule_work(&nic->rst_timer_task);
2829                                 }
2830                         }
2831                 } else {
2832                         nic->mac_control.stats_info->sw_stat.
2833                                 single_ecc_errs++;
2834                 }
2835         }
2836
2837         /* In case of a serious error, the device will be Reset. */
2838         val64 = readq(&bar0->serr_source);
2839         if (val64 & SERR_SOURCE_ANY) {
2840                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2841                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
2842                           (unsigned long long)val64);
2843                 netif_stop_queue(dev);
2844                 schedule_work(&nic->rst_timer_task);
2845         }
2846
2847         /*
2848          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2849          * Error occurs, the adapter will be recycled by disabling the
2850          * adapter enable bit and enabling it again after the device
2851          * becomes Quiescent.
2852          */
2853         val64 = readq(&bar0->pcc_err_reg);
2854         writeq(val64, &bar0->pcc_err_reg);
2855         if (val64 & PCC_FB_ECC_DB_ERR) {
2856                 u64 ac = readq(&bar0->adapter_control);
2857                 ac &= ~(ADAPTER_CNTL_EN);
2858                 writeq(ac, &bar0->adapter_control);
2859                 ac = readq(&bar0->adapter_control);
2860                 schedule_work(&nic->set_link_task);
2861         }
2862
2863         /* Other type of interrupts are not being handled now,  TODO */
2864 }
2865
2866 /**
2867  *  wait_for_cmd_complete - waits for a command to complete.
2868  *  @sp : private member of the device structure, which is a pointer to the
2869  *  s2io_nic structure.
2870  *  Description: Function that waits for a command to Write into RMAC
2871  *  ADDR DATA registers to be completed and returns either success or
2872  *  error depending on whether the command was complete or not.
2873  *  Return value:
2874  *   SUCCESS on success and FAILURE on failure.
2875  */
2876
2877 static int wait_for_cmd_complete(nic_t * sp)
2878 {
2879         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2880         int ret = FAILURE, cnt = 0;
2881         u64 val64;
2882
2883         while (TRUE) {
2884                 val64 = readq(&bar0->rmac_addr_cmd_mem);
2885                 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
2886                         ret = SUCCESS;
2887                         break;
2888                 }
2889                 msleep(50);
2890                 if (cnt++ > 10)
2891                         break;
2892         }
2893
2894         return ret;
2895 }
2896
2897 /**
2898  *  s2io_reset - Resets the card.
2899  *  @sp : private member of the device structure.
2900  *  Description: Function to Reset the card. This function then also
2901  *  restores the previously saved PCI configuration space registers as
2902  *  the card reset also resets the configuration space.
2903  *  Return value:
2904  *  void.
2905  */
2906
2907 static void s2io_reset(nic_t * sp)
2908 {
2909         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2910         u64 val64;
2911         u16 subid, pci_cmd;
2912
2913         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2914         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2915
2916         val64 = SW_RESET_ALL;
2917         writeq(val64, &bar0->sw_reset);
2918
2919         /*
2920          * At this stage, if the PCI write is indeed completed, the
2921          * card is reset and so is the PCI Config space of the device.
2922          * So a read cannot be issued at this stage on any of the
2923          * registers to ensure the write into "sw_reset" register
2924          * has gone through.
2925          * Question: Is there any system call that will explicitly force
2926          * all the write commands still pending on the bus to be pushed
2927          * through?
2928          * As of now I'am just giving a 250ms delay and hoping that the
2929          * PCI write to sw_reset register is done by this time.
2930          */
2931         msleep(250);
2932
2933         /* Restore the PCI state saved during initialization. */
2934         pci_restore_state(sp->pdev);
2935         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2936                                      pci_cmd);
2937         s2io_init_pci(sp);
2938
2939         msleep(250);
2940
2941         /* Set swapper to enable I/O register access */
2942         s2io_set_swapper(sp);
2943
2944         /* Restore the MSIX table entries from local variables */
2945         restore_xmsi_data(sp);
2946
2947         /* Clear certain PCI/PCI-X fields after reset */
2948         if (sp->device_type == XFRAME_II_DEVICE) {
2949                 /* Clear parity err detect bit */
2950                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2951
2952                 /* Clearing PCIX Ecc status register */
2953                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2954
2955                 /* Clearing PCI_STATUS error reflected here */
2956                 writeq(BIT(62), &bar0->txpic_int_reg);
2957         }
2958
2959         /* Reset device statistics maintained by OS */
2960         memset(&sp->stats, 0, sizeof (struct net_device_stats));
2961
2962         /* SXE-002: Configure link and activity LED to turn it off */
2963         subid = sp->pdev->subsystem_device;
2964         if (((subid & 0xFF) >= 0x07) &&
2965             (sp->device_type == XFRAME_I_DEVICE)) {
2966                 val64 = readq(&bar0->gpio_control);
2967                 val64 |= 0x0000800000000000ULL;
2968                 writeq(val64, &bar0->gpio_control);
2969                 val64 = 0x0411040400000000ULL;
2970                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2971         }
2972
2973         /*
2974          * Clear spurious ECC interrupts that would have occured on
2975          * XFRAME II cards after reset.
2976          */
2977         if (sp->device_type == XFRAME_II_DEVICE) {
2978                 val64 = readq(&bar0->pcc_err_reg);
2979                 writeq(val64, &bar0->pcc_err_reg);
2980         }
2981
2982         sp->device_enabled_once = FALSE;
2983 }
2984
2985 /**
2986  *  s2io_set_swapper - to set the swapper controle on the card
2987  *  @sp : private member of the device structure,
2988  *  pointer to the s2io_nic structure.
2989  *  Description: Function to set the swapper control on the card
2990  *  correctly depending on the 'endianness' of the system.
2991  *  Return value:
2992  *  SUCCESS on success and FAILURE on failure.
2993  */
2994
2995 static int s2io_set_swapper(nic_t * sp)
2996 {
2997         struct net_device *dev = sp->dev;
2998         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2999         u64 val64, valt, valr;
3000
3001         /*
3002          * Set proper endian settings and verify the same by reading
3003          * the PIF Feed-back register.
3004          */
3005
3006         val64 = readq(&bar0->pif_rd_swapper_fb);
3007         if (val64 != 0x0123456789ABCDEFULL) {
3008                 int i = 0;
3009                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3010                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3011                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3012                                 0};                     /* FE=0, SE=0 */
3013
3014                 while(i<4) {
3015                         writeq(value[i], &bar0->swapper_ctrl);
3016                         val64 = readq(&bar0->pif_rd_swapper_fb);
3017                         if (val64 == 0x0123456789ABCDEFULL)
3018                                 break;
3019                         i++;
3020                 }
3021                 if (i == 4) {
3022                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3023                                 dev->name);
3024                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3025                                 (unsigned long long) val64);
3026                         return FAILURE;
3027                 }
3028                 valr = value[i];
3029         } else {
3030                 valr = readq(&bar0->swapper_ctrl);
3031         }
3032
3033         valt = 0x0123456789ABCDEFULL;
3034         writeq(valt, &bar0->xmsi_address);
3035         val64 = readq(&bar0->xmsi_address);
3036
3037         if(val64 != valt) {
3038                 int i = 0;
3039                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3040                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3041                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3042                                 0};                     /* FE=0, SE=0 */
3043
3044                 while(i<4) {
3045                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3046                         writeq(valt, &bar0->xmsi_address);
3047                         val64 = readq(&bar0->xmsi_address);
3048                         if(val64 == valt)
3049                                 break;
3050                         i++;
3051                 }
3052                 if(i == 4) {
3053                         unsigned long long x = val64;
3054                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3055                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3056                         return FAILURE;
3057                 }
3058         }
3059         val64 = readq(&bar0->swapper_ctrl);
3060         val64 &= 0xFFFF000000000000ULL;
3061
3062 #ifdef  __BIG_ENDIAN
3063         /*
3064          * The device by default set to a big endian format, so a
3065          * big endian driver need not set anything.
3066          */
3067         val64 |= (SWAPPER_CTRL_TXP_FE |
3068                  SWAPPER_CTRL_TXP_SE |
3069                  SWAPPER_CTRL_TXD_R_FE |
3070                  SWAPPER_CTRL_TXD_W_FE |
3071                  SWAPPER_CTRL_TXF_R_FE |
3072                  SWAPPER_CTRL_RXD_R_FE |
3073                  SWAPPER_CTRL_RXD_W_FE |
3074                  SWAPPER_CTRL_RXF_W_FE |
3075                  SWAPPER_CTRL_XMSI_FE |
3076                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3077         if (sp->intr_type == INTA)
3078                 val64 |= SWAPPER_CTRL_XMSI_SE;
3079         writeq(val64, &bar0->swapper_ctrl);
3080 #else
3081         /*
3082          * Initially we enable all bits to make it accessible by the
3083          * driver, then we selectively enable only those bits that
3084          * we want to set.
3085          */
3086         val64 |= (SWAPPER_CTRL_TXP_FE |
3087                  SWAPPER_CTRL_TXP_SE |
3088                  SWAPPER_CTRL_TXD_R_FE |
3089                  SWAPPER_CTRL_TXD_R_SE |
3090                  SWAPPER_CTRL_TXD_W_FE |
3091                  SWAPPER_CTRL_TXD_W_SE |
3092                  SWAPPER_CTRL_TXF_R_FE |
3093                  SWAPPER_CTRL_RXD_R_FE |
3094                  SWAPPER_CTRL_RXD_R_SE |
3095                  SWAPPER_CTRL_RXD_W_FE |
3096                  SWAPPER_CTRL_RXD_W_SE |
3097                  SWAPPER_CTRL_RXF_W_FE |
3098                  SWAPPER_CTRL_XMSI_FE |
3099                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3100         if (sp->intr_type == INTA)
3101                 val64 |= SWAPPER_CTRL_XMSI_SE;
3102         writeq(val64, &bar0->swapper_ctrl);
3103 #endif
3104         val64 = readq(&bar0->swapper_ctrl);
3105
3106         /*
3107          * Verifying if endian settings are accurate by reading a
3108          * feedback register.
3109          */
3110         val64 = readq(&bar0->pif_rd_swapper_fb);
3111         if (val64 != 0x0123456789ABCDEFULL) {
3112                 /* Endian settings are incorrect, calls for another dekko. */
3113                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3114                           dev->name);
3115                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3116                           (unsigned long long) val64);
3117                 return FAILURE;
3118         }
3119
3120         return SUCCESS;
3121 }
3122
3123 static int wait_for_msix_trans(nic_t *nic, int i)
3124 {
3125         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3126         u64 val64;
3127         int ret = 0, cnt = 0;
3128
3129         do {
3130                 val64 = readq(&bar0->xmsi_access);
3131                 if (!(val64 & BIT(15)))
3132                         break;
3133                 mdelay(1);
3134                 cnt++;
3135         } while(cnt < 5);
3136         if (cnt == 5) {
3137                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3138                 ret = 1;
3139         }
3140
3141         return ret;
3142 }
3143
3144 static void restore_xmsi_data(nic_t *nic)
3145 {
3146         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3147         u64 val64;
3148         int i;
3149
3150         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3151                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3152                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3153                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3154                 writeq(val64, &bar0->xmsi_access);
3155                 if (wait_for_msix_trans(nic, i)) {
3156                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3157                         continue;
3158                 }
3159         }
3160 }
3161
3162 static void store_xmsi_data(nic_t *nic)
3163 {
3164         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3165         u64 val64, addr, data;
3166         int i;
3167
3168         /* Store and display */
3169         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3170                 val64 = (BIT(15) | vBIT(i, 26, 6));
3171                 writeq(val64, &bar0->xmsi_access);
3172                 if (wait_for_msix_trans(nic, i)) {
3173                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3174                         continue;
3175                 }
3176                 addr = readq(&bar0->xmsi_address);
3177                 data = readq(&bar0->xmsi_data);
3178                 if (addr && data) {
3179                         nic->msix_info[i].addr = addr;
3180                         nic->msix_info[i].data = data;
3181                 }
3182         }
3183 }
3184
3185 int s2io_enable_msi(nic_t *nic)
3186 {
3187         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3188         u16 msi_ctrl, msg_val;
3189         struct config_param *config = &nic->config;
3190         struct net_device *dev = nic->dev;
3191         u64 val64, tx_mat, rx_mat;
3192         int i, err;
3193
3194         val64 = readq(&bar0->pic_control);
3195         val64 &= ~BIT(1);
3196         writeq(val64, &bar0->pic_control);
3197
3198         err = pci_enable_msi(nic->pdev);
3199         if (err) {
3200                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3201                           nic->dev->name);
3202                 return err;
3203         }
3204
3205         /*
3206          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3207          * for interrupt handling.
3208          */
3209         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3210         msg_val ^= 0x1;
3211         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3212         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3213
3214         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3215         msi_ctrl |= 0x10;
3216         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3217
3218         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3219         tx_mat = readq(&bar0->tx_mat0_n[0]);
3220         for (i=0; i<config->tx_fifo_num; i++) {
3221                 tx_mat |= TX_MAT_SET(i, 1);
3222         }
3223         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3224
3225         rx_mat = readq(&bar0->rx_mat);
3226         for (i=0; i<config->rx_ring_num; i++) {
3227                 rx_mat |= RX_MAT_SET(i, 1);
3228         }
3229         writeq(rx_mat, &bar0->rx_mat);
3230
3231         dev->irq = nic->pdev->irq;
3232         return 0;
3233 }
3234
3235 static int s2io_enable_msi_x(nic_t *nic)
3236 {
3237         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3238         u64 tx_mat, rx_mat;
3239         u16 msi_control; /* Temp variable */
3240         int ret, i, j, msix_indx = 1;
3241
3242         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3243                                GFP_KERNEL);
3244         if (nic->entries == NULL) {
3245                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3246                 return -ENOMEM;
3247         }
3248         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3249
3250         nic->s2io_entries =
3251                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3252                                    GFP_KERNEL);
3253         if (nic->s2io_entries == NULL) {
3254                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3255                 kfree(nic->entries);
3256                 return -ENOMEM;
3257         }
3258         memset(nic->s2io_entries, 0,
3259                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3260
3261         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3262                 nic->entries[i].entry = i;
3263                 nic->s2io_entries[i].entry = i;
3264                 nic->s2io_entries[i].arg = NULL;
3265                 nic->s2io_entries[i].in_use = 0;
3266         }
3267
3268         tx_mat = readq(&bar0->tx_mat0_n[0]);
3269         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3270                 tx_mat |= TX_MAT_SET(i, msix_indx);
3271                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3272                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3273                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3274         }
3275         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3276
3277         if (!nic->config.bimodal) {
3278                 rx_mat = readq(&bar0->rx_mat);
3279                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3280                         rx_mat |= RX_MAT_SET(j, msix_indx);
3281                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3282                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3283                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3284                 }
3285                 writeq(rx_mat, &bar0->rx_mat);
3286         } else {
3287                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3288                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3289                         tx_mat |= TX_MAT_SET(i, msix_indx);
3290                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3291                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3292                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3293                 }
3294                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3295         }
3296
3297         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3298         if (ret) {
3299                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3300                 kfree(nic->entries);
3301                 kfree(nic->s2io_entries);
3302                 nic->entries = NULL;
3303                 nic->s2io_entries = NULL;
3304                 return -ENOMEM;
3305         }
3306
3307         /*
3308          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3309          * in the herc NIC. (Temp change, needs to be removed later)
3310          */
3311         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3312         msi_control |= 0x1; /* Enable MSI */
3313         pci_write_config_word(nic->pdev, 0x42, msi_control);
3314
3315         return 0;
3316 }
3317
3318 /* ********************************************************* *
3319  * Functions defined below concern the OS part of the driver *
3320  * ********************************************************* */
3321
3322 /**
3323  *  s2io_open - open entry point of the driver
3324  *  @dev : pointer to the device structure.
3325  *  Description:
3326  *  This function is the open entry point of the driver. It mainly calls a
3327  *  function to allocate Rx buffers and inserts them into the buffer
3328  *  descriptors and then enables the Rx part of the NIC.
3329  *  Return value:
3330  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3331  *   file on failure.
3332  */
3333
3334 static int s2io_open(struct net_device *dev)
3335 {
3336         nic_t *sp = dev->priv;
3337         int err = 0;
3338         int i;
3339         u16 msi_control; /* Temp variable */
3340
3341         /*
3342          * Make sure you have link off by default every time
3343          * Nic is initialized
3344          */
3345         netif_carrier_off(dev);
3346         sp->last_link_state = 0;
3347
3348         /* Initialize H/W and enable interrupts */
3349         if (s2io_card_up(sp)) {
3350                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3351                           dev->name);
3352                 err = -ENODEV;
3353                 goto hw_init_failed;
3354         }
3355
3356         /* Store the values of the MSIX table in the nic_t structure */
3357         store_xmsi_data(sp);
3358
3359         /* After proper initialization of H/W, register ISR */
3360         if (sp->intr_type == MSI) {
3361                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
3362                         SA_SHIRQ, sp->name, dev);
3363                 if (err) {
3364                         DBG_PRINT(ERR_DBG, "%s: MSI registration \
3365 failed\n", dev->name);
3366                         goto isr_registration_failed;
3367                 }
3368         }
3369         if (sp->intr_type == MSI_X) {
3370                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3371                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3372                                 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3373                                         dev->name, i);
3374                                 err = request_irq(sp->entries[i].vector,
3375                                           s2io_msix_fifo_handle, 0, sp->desc1,
3376                                           sp->s2io_entries[i].arg);
3377                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
3378                                     (unsigned long long)sp->msix_info[i].addr);
3379                         } else {
3380                                 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3381                                         dev->name, i);
3382                                 err = request_irq(sp->entries[i].vector,
3383                                           s2io_msix_ring_handle, 0, sp->desc2,
3384                                           sp->s2io_entries[i].arg);
3385                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
3386                                      (unsigned long long)sp->msix_info[i].addr);
3387                         }
3388                         if (err) {
3389                                 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3390 failed\n", dev->name, i);
3391                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3392                                 goto isr_registration_failed;
3393                         }
3394                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3395                 }
3396         }
3397         if (sp->intr_type == INTA) {
3398                 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
3399                                 sp->name, dev);
3400                 if (err) {
3401                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3402                                   dev->name);
3403                         goto isr_registration_failed;
3404                 }
3405         }
3406
3407         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3408                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3409                 err = -ENODEV;
3410                 goto setting_mac_address_failed;
3411         }
3412
3413         netif_start_queue(dev);
3414         return 0;
3415
3416 setting_mac_address_failed:
3417         if (sp->intr_type != MSI_X)
3418                 free_irq(sp->pdev->irq, dev);
3419 isr_registration_failed:
3420         del_timer_sync(&sp->alarm_timer);
3421         if (sp->intr_type == MSI_X) {
3422                 if (sp->device_type == XFRAME_II_DEVICE) {
3423                         for (i=1; (sp->s2io_entries[i].in_use ==
3424                                 MSIX_REGISTERED_SUCCESS); i++) {
3425                                 int vector = sp->entries[i].vector;
3426                                 void *arg = sp->s2io_entries[i].arg;
3427
3428                                 free_irq(vector, arg);
3429                         }
3430                         pci_disable_msix(sp->pdev);
3431
3432                         /* Temp */
3433                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3434                         msi_control &= 0xFFFE; /* Disable MSI */
3435                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3436                 }
3437         }
3438         else if (sp->intr_type == MSI)
3439                 pci_disable_msi(sp->pdev);
3440         s2io_reset(sp);
3441 hw_init_failed:
3442         if (sp->intr_type == MSI_X) {
3443                 if (sp->entries)
3444                         kfree(sp->entries);
3445                 if (sp->s2io_entries)
3446                         kfree(sp->s2io_entries);
3447         }
3448         return err;
3449 }
3450
3451 /**
3452  *  s2io_close -close entry point of the driver
3453  *  @dev : device pointer.
3454  *  Description:
3455  *  This is the stop entry point of the driver. It needs to undo exactly
3456  *  whatever was done by the open entry point,thus it's usually referred to
3457  *  as the close function.Among other things this function mainly stops the
3458  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3459  *  Return value:
3460  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3461  *  file on failure.
3462  */
3463
3464 static int s2io_close(struct net_device *dev)
3465 {
3466         nic_t *sp = dev->priv;
3467         int i;
3468         u16 msi_control;
3469
3470         flush_scheduled_work();
3471         netif_stop_queue(dev);
3472         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3473         s2io_card_down(sp);
3474
3475         if (sp->intr_type == MSI_X) {
3476                 if (sp->device_type == XFRAME_II_DEVICE) {
3477                         for (i=1; (sp->s2io_entries[i].in_use ==
3478                                         MSIX_REGISTERED_SUCCESS); i++) {
3479                                 int vector = sp->entries[i].vector;
3480                                 void *arg = sp->s2io_entries[i].arg;
3481
3482                                 free_irq(vector, arg);
3483                         }
3484                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3485                         msi_control &= 0xFFFE; /* Disable MSI */
3486                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3487
3488                         pci_disable_msix(sp->pdev);
3489                 }
3490         }
3491         else {
3492                 free_irq(sp->pdev->irq, dev);
3493                 if (sp->intr_type == MSI)
3494                         pci_disable_msi(sp->pdev);
3495         }
3496         sp->device_close_flag = TRUE;   /* Device is shut down. */
3497         return 0;
3498 }
3499
3500 /**
3501  *  s2io_xmit - Tx entry point of te driver
3502  *  @skb : the socket buffer containing the Tx data.
3503  *  @dev : device pointer.
3504  *  Description :
3505  *  This function is the Tx entry point of the driver. S2IO NIC supports
3506  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3507  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3508  *  not be upadted.
3509  *  Return value:
3510  *  0 on success & 1 on failure.
3511  */
3512
3513 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3514 {
3515         nic_t *sp = dev->priv;
3516         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3517         register u64 val64;
3518         TxD_t *txdp;
3519         TxFIFO_element_t __iomem *tx_fifo;
3520         unsigned long flags;
3521 #ifdef NETIF_F_TSO
3522         int mss;
3523 #endif
3524         u16 vlan_tag = 0;
3525         int vlan_priority = 0;
3526         mac_info_t *mac_control;
3527         struct config_param *config;
3528
3529         mac_control = &sp->mac_control;
3530         config = &sp->config;
3531
3532         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3533         spin_lock_irqsave(&sp->tx_lock, flags);
3534         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3535                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3536                           dev->name);
3537                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3538                 dev_kfree_skb(skb);
3539                 return 0;
3540         }
3541
3542         queue = 0;
3543
3544         /* Get Fifo number to Transmit based on vlan priority */
3545         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3546                 vlan_tag = vlan_tx_tag_get(skb);
3547                 vlan_priority = vlan_tag >> 13;
3548                 queue = config->fifo_mapping[vlan_priority];
3549         }
3550
3551         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3552         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3553         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3554                 list_virt_addr;
3555
3556         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3557         /* Avoid "put" pointer going beyond "get" pointer */
3558         if (txdp->Host_Control ||
3559                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3560                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3561                 netif_stop_queue(dev);
3562                 dev_kfree_skb(skb);
3563                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3564                 return 0;
3565         }
3566
3567         /* A buffer with no data will be dropped */
3568         if (!skb->len) {
3569                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3570                 dev_kfree_skb(skb);
3571                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3572                 return 0;
3573         }
3574
3575         txdp->Control_1 = 0;
3576         txdp->Control_2 = 0;
3577 #ifdef NETIF_F_TSO
3578         mss = skb_shinfo(skb)->tso_size;
3579         if (mss) {
3580                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3581                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3582         }
3583 #endif
3584         if (skb->ip_summed == CHECKSUM_HW) {
3585                 txdp->Control_2 |=
3586                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3587                      TXD_TX_CKO_UDP_EN);
3588         }
3589         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3590         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3591         txdp->Control_2 |= config->tx_intr_type;
3592
3593         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3594                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3595                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3596         }
3597
3598         frg_len = skb->len - skb->data_len;
3599         if (skb_shinfo(skb)->ufo_size) {
3600                 int ufo_size;
3601
3602                 ufo_size = skb_shinfo(skb)->ufo_size;
3603                 ufo_size &= ~7;
3604                 txdp->Control_1 |= TXD_UFO_EN;
3605                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3606                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3607 #ifdef __BIG_ENDIAN
3608                 sp->ufo_in_band_v[put_off] =
3609                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3610 #else
3611                 sp->ufo_in_band_v[put_off] =
3612                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3613 #endif
3614                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3615                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3616                                         sp->ufo_in_band_v,
3617                                         sizeof(u64), PCI_DMA_TODEVICE);
3618                 txdp++;
3619                 txdp->Control_1 = 0;
3620                 txdp->Control_2 = 0;
3621         }
3622
3623         txdp->Buffer_Pointer = pci_map_single
3624             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3625         txdp->Host_Control = (unsigned long) skb;
3626         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3627
3628         if (skb_shinfo(skb)->ufo_size)
3629                 txdp->Control_1 |= TXD_UFO_EN;
3630
3631         frg_cnt = skb_shinfo(skb)->nr_frags;
3632         /* For fragmented SKB. */
3633         for (i = 0; i < frg_cnt; i++) {
3634                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3635                 /* A '0' length fragment will be ignored */
3636                 if (!frag->size)
3637                         continue;
3638                 txdp++;
3639                 txdp->Buffer_Pointer = (u64) pci_map_page
3640                     (sp->pdev, frag->page, frag->page_offset,
3641                      frag->size, PCI_DMA_TODEVICE);
3642                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3643                 if (skb_shinfo(skb)->ufo_size)
3644                         txdp->Control_1 |= TXD_UFO_EN;
3645         }
3646         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3647
3648         if (skb_shinfo(skb)->ufo_size)
3649                 frg_cnt++; /* as Txd0 was used for inband header */
3650
3651         tx_fifo = mac_control->tx_FIFO_start[queue];
3652         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3653         writeq(val64, &tx_fifo->TxDL_Pointer);
3654
3655         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3656                  TX_FIFO_LAST_LIST);
3657
3658 #ifdef NETIF_F_TSO
3659         if (mss)
3660                 val64 |= TX_FIFO_SPECIAL_FUNC;
3661 #endif
3662         if (skb_shinfo(skb)->ufo_size)
3663                 val64 |= TX_FIFO_SPECIAL_FUNC;
3664         writeq(val64, &tx_fifo->List_Control);
3665
3666         mmiowb();
3667
3668         put_off++;
3669         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3670                 put_off = 0;
3671         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3672
3673         /* Avoid "put" pointer going beyond "get" pointer */
3674         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3675                 DBG_PRINT(TX_DBG,
3676                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3677                           put_off, get_off);
3678                 netif_stop_queue(dev);
3679         }
3680
3681         dev->trans_start = jiffies;
3682         spin_unlock_irqrestore(&sp->tx_lock, flags);
3683
3684         return 0;
3685 }
3686
3687 static void
3688 s2io_alarm_handle(unsigned long data)
3689 {
3690         nic_t *sp = (nic_t *)data;
3691
3692         alarm_intr_handler(sp);
3693         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3694 }
3695
3696 static irqreturn_t
3697 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3698 {
3699         struct net_device *dev = (struct net_device *) dev_id;
3700         nic_t *sp = dev->priv;
3701         int i;
3702         int ret;
3703         mac_info_t *mac_control;
3704         struct config_param *config;
3705
3706         atomic_inc(&sp->isr_cnt);
3707         mac_control = &sp->mac_control;
3708         config = &sp->config;
3709         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3710
3711         /* If Intr is because of Rx Traffic */
3712         for (i = 0; i < config->rx_ring_num; i++)
3713                 rx_intr_handler(&mac_control->rings[i]);
3714
3715         /* If Intr is because of Tx Traffic */
3716         for (i = 0; i < config->tx_fifo_num; i++)
3717                 tx_intr_handler(&mac_control->fifos[i]);
3718
3719         /*
3720          * If the Rx buffer count is below the panic threshold then
3721          * reallocate the buffers from the interrupt handler itself,
3722          * else schedule a tasklet to reallocate the buffers.
3723          */
3724         for (i = 0; i < config->rx_ring_num; i++) {
3725                 if (!sp->lro) {
3726                         int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3727                         int level = rx_buffer_level(sp, rxb_size, i);
3728
3729                         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3730                                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
3731                                                         dev->name);
3732                                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3733                                 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3734                                         DBG_PRINT(ERR_DBG, "%s:Out of memory",
3735                                                   dev->name);
3736                                         DBG_PRINT(ERR_DBG, " in ISR!!\n");
3737                                         clear_bit(0, (&sp->tasklet_status));
3738                                         atomic_dec(&sp->isr_cnt);
3739                                         return IRQ_HANDLED;
3740                                 }
3741                                 clear_bit(0, (&sp->tasklet_status));
3742                         } else if (level == LOW) {
3743                                 tasklet_schedule(&sp->task);
3744                         }
3745                 }
3746                 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
3747                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3748                                                         dev->name);
3749                                 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
3750                                 break;
3751                 }
3752         }
3753
3754         atomic_dec(&sp->isr_cnt);
3755         return IRQ_HANDLED;
3756 }
3757
3758 static irqreturn_t
3759 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
3760 {
3761         ring_info_t *ring = (ring_info_t *)dev_id;
3762         nic_t *sp = ring->nic;
3763         struct net_device *dev = (struct net_device *) dev_id;
3764         int rxb_size, level, rng_n;
3765
3766         atomic_inc(&sp->isr_cnt);
3767         rx_intr_handler(ring);
3768
3769         rng_n = ring->ring_no;
3770         if (!sp->lro) {
3771                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3772                 level = rx_buffer_level(sp, rxb_size, rng_n);
3773
3774                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3775                         int ret;
3776                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3777                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3778                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3779                                 DBG_PRINT(ERR_DBG, "Out of memory in %s",
3780                                           __FUNCTION__);
3781                                 clear_bit(0, (&sp->tasklet_status));
3782                                 return IRQ_HANDLED;
3783                         }
3784                         clear_bit(0, (&sp->tasklet_status));
3785                 } else if (level == LOW) {
3786                         tasklet_schedule(&sp->task);
3787                 }
3788         }
3789         else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
3790                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
3791                         DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
3792         }
3793
3794         atomic_dec(&sp->isr_cnt);
3795
3796         return IRQ_HANDLED;
3797 }
3798
3799 static irqreturn_t
3800 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
3801 {
3802         fifo_info_t *fifo = (fifo_info_t *)dev_id;
3803         nic_t *sp = fifo->nic;
3804
3805         atomic_inc(&sp->isr_cnt);
3806         tx_intr_handler(fifo);
3807         atomic_dec(&sp->isr_cnt);
3808         return IRQ_HANDLED;
3809 }
3810
3811 static void s2io_txpic_intr_handle(nic_t *sp)
3812 {
3813         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3814         u64 val64;
3815
3816         val64 = readq(&bar0->pic_int_status);
3817         if (val64 & PIC_INT_GPIO) {
3818                 val64 = readq(&bar0->gpio_int_reg);
3819                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3820                     (val64 & GPIO_INT_REG_LINK_UP)) {
3821                         val64 |=  GPIO_INT_REG_LINK_DOWN;
3822                         val64 |= GPIO_INT_REG_LINK_UP;
3823                         writeq(val64, &bar0->gpio_int_reg);
3824                         goto masking;
3825                 }
3826
3827                 if (((sp->last_link_state == LINK_UP) &&
3828                         (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3829                 ((sp->last_link_state == LINK_DOWN) &&
3830                 (val64 & GPIO_INT_REG_LINK_UP))) {
3831                         val64 = readq(&bar0->gpio_int_mask);
3832                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3833                         val64 |= GPIO_INT_MASK_LINK_UP;
3834                         writeq(val64, &bar0->gpio_int_mask);
3835                         s2io_set_link((unsigned long)sp);
3836                 }
3837 masking:
3838                 if (sp->last_link_state == LINK_UP) {
3839                         /*enable down interrupt */
3840                         val64 = readq(&bar0->gpio_int_mask);
3841                         /* unmasks link down intr */
3842                         val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
3843                         /* masks link up intr */
3844                         val64 |= GPIO_INT_MASK_LINK_UP;
3845                         writeq(val64, &bar0->gpio_int_mask);
3846                 } else {
3847                         /*enable UP Interrupt */
3848                         val64 = readq(&bar0->gpio_int_mask);
3849                         /* unmasks link up interrupt */
3850                         val64 &= ~GPIO_INT_MASK_LINK_UP;
3851                         /* masks link down interrupt */
3852                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3853                         writeq(val64, &bar0->gpio_int_mask);
3854                 }
3855         }
3856 }
3857
3858 /**
3859  *  s2io_isr - ISR handler of the device .
3860  *  @irq: the irq of the device.
3861  *  @dev_id: a void pointer to the dev structure of the NIC.
3862  *  @pt_regs: pointer to the registers pushed on the stack.
3863  *  Description:  This function is the ISR handler of the device. It
3864  *  identifies the reason for the interrupt and calls the relevant
3865  *  service routines. As a contongency measure, this ISR allocates the
3866  *  recv buffers, if their numbers are below the panic value which is
3867  *  presently set to 25% of the original number of rcv buffers allocated.
3868  *  Return value:
3869  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
3870  *   IRQ_NONE: will be returned if interrupt is not from our device
3871  */
3872 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
3873 {
3874         struct net_device *dev = (struct net_device *) dev_id;
3875         nic_t *sp = dev->priv;
3876         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3877         int i;
3878         u64 reason = 0, val64;
3879         mac_info_t *mac_control;
3880         struct config_param *config;
3881
3882         atomic_inc(&sp->isr_cnt);
3883         mac_control = &sp->mac_control;
3884         config = &sp->config;
3885
3886         /*
3887          * Identify the cause for interrupt and call the appropriate
3888          * interrupt handler. Causes for the interrupt could be;
3889          * 1. Rx of packet.
3890          * 2. Tx complete.
3891          * 3. Link down.
3892          * 4. Error in any functional blocks of the NIC.
3893          */
3894         reason = readq(&bar0->general_int_status);
3895
3896         if (!reason) {
3897                 /* The interrupt was not raised by Xena. */
3898                 atomic_dec(&sp->isr_cnt);
3899                 return IRQ_NONE;
3900         }
3901
3902         val64 = 0xFFFFFFFFFFFFFFFFULL;
3903 #ifdef CONFIG_S2IO_NAPI
3904         if (reason & GEN_INTR_RXTRAFFIC) {
3905                 if (netif_rx_schedule_prep(dev)) {
3906                         writeq(val64, &bar0->rx_traffic_mask);
3907                         __netif_rx_schedule(dev);
3908                 }
3909         }
3910 #else
3911         /*
3912          * Rx handler is called by default, without checking for the
3913          * cause of interrupt.
3914          * rx_traffic_int reg is an R1 register, writing all 1's
3915          * will ensure that the actual interrupt causing bit get's
3916          * cleared and hence a read can be avoided.
3917          */
3918         writeq(val64, &bar0->rx_traffic_int);
3919         for (i = 0; i < config->rx_ring_num; i++) {
3920                 rx_intr_handler(&mac_control->rings[i]);
3921         }
3922 #endif
3923
3924         /*
3925          * tx_traffic_int reg is an R1 register, writing all 1's
3926          * will ensure that the actual interrupt causing bit get's
3927          * cleared and hence a read can be avoided.
3928          */
3929         writeq(val64, &bar0->tx_traffic_int);
3930
3931         for (i = 0; i < config->tx_fifo_num; i++)
3932                 tx_intr_handler(&mac_control->fifos[i]);
3933
3934         if (reason & GEN_INTR_TXPIC)
3935                 s2io_txpic_intr_handle(sp);
3936         /*
3937          * If the Rx buffer count is below the panic threshold then
3938          * reallocate the buffers from the interrupt handler itself,
3939          * else schedule a tasklet to reallocate the buffers.
3940          */
3941 #ifndef CONFIG_S2IO_NAPI
3942         for (i = 0; i < config->rx_ring_num; i++) {
3943                 if (!sp->lro) {
3944                         int ret;
3945                         int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3946                         int level = rx_buffer_level(sp, rxb_size, i);
3947
3948                         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3949                                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ",
3950                                                         dev->name);
3951                                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3952                                 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3953                                         DBG_PRINT(ERR_DBG, "%s:Out of memory",
3954                                                   dev->name);
3955                                         DBG_PRINT(ERR_DBG, " in ISR!!\n");
3956                                         clear_bit(0, (&sp->tasklet_status));
3957                                         atomic_dec(&sp->isr_cnt);
3958                                         return IRQ_HANDLED;
3959                                 }
3960                                 clear_bit(0, (&sp->tasklet_status));
3961                         } else if (level == LOW) {
3962                                 tasklet_schedule(&sp->task);
3963                         }
3964                 }
3965                 else if (fill_rx_buffers(sp, i) == -ENOMEM) {
3966                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3967                                                         dev->name);
3968                                 DBG_PRINT(ERR_DBG, " in Rx intr!!\n");
3969                                 break;
3970                 }
3971         }
3972 #endif
3973
3974         atomic_dec(&sp->isr_cnt);
3975         return IRQ_HANDLED;
3976 }
3977
3978 /**
3979  * s2io_updt_stats -
3980  */
3981 static void s2io_updt_stats(nic_t *sp)
3982 {
3983         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3984         u64 val64;
3985         int cnt = 0;
3986
3987         if (atomic_read(&sp->card_state) == CARD_UP) {
3988                 /* Apprx 30us on a 133 MHz bus */
3989                 val64 = SET_UPDT_CLICKS(10) |
3990                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3991                 writeq(val64, &bar0->stat_cfg);
3992                 do {
3993                         udelay(100);
3994                         val64 = readq(&bar0->stat_cfg);
3995                         if (!(val64 & BIT(0)))
3996                                 break;
3997                         cnt++;
3998                         if (cnt == 5)
3999                                 break; /* Updt failed */
4000                 } while(1);
4001         }
4002 }
4003
4004 /**
4005  *  s2io_get_stats - Updates the device statistics structure.
4006  *  @dev : pointer to the device structure.
4007  *  Description:
4008  *  This function updates the device statistics structure in the s2io_nic
4009  *  structure and returns a pointer to the same.
4010  *  Return value:
4011  *  pointer to the updated net_device_stats structure.
4012  */
4013
4014 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4015 {
4016         nic_t *sp = dev->priv;
4017         mac_info_t *mac_control;
4018         struct config_param *config;
4019
4020
4021         mac_control = &sp->mac_control;
4022         config = &sp->config;
4023
4024         /* Configure Stats for immediate updt */
4025         s2io_updt_stats(sp);
4026
4027         sp->stats.tx_packets =
4028                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4029         sp->stats.tx_errors =
4030                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4031         sp->stats.rx_errors =
4032                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
4033         sp->stats.multicast =
4034                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4035         sp->stats.rx_length_errors =
4036                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
4037
4038         return (&sp->stats);
4039 }
4040
4041 /**
4042  *  s2io_set_multicast - entry point for multicast address enable/disable.
4043  *  @dev : pointer to the device structure
4044  *  Description:
4045  *  This function is a driver entry point which gets called by the kernel
4046  *  whenever multicast addresses must be enabled/disabled. This also gets
4047  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4048  *  determine, if multicast address must be enabled or if promiscuous mode
4049  *  is to be disabled etc.
4050  *  Return value:
4051  *  void.
4052  */
4053
4054 static void s2io_set_multicast(struct net_device *dev)
4055 {
4056         int i, j, prev_cnt;
4057         struct dev_mc_list *mclist;
4058         nic_t *sp = dev->priv;
4059         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4060         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4061             0xfeffffffffffULL;
4062         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4063         void __iomem *add;
4064
4065         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4066                 /*  Enable all Multicast addresses */
4067                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4068                        &bar0->rmac_addr_data0_mem);
4069                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4070                        &bar0->rmac_addr_data1_mem);
4071                 val64 = RMAC_ADDR_CMD_MEM_WE |
4072                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4073                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4074                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4075                 /* Wait till command completes */
4076                 wait_for_cmd_complete(sp);
4077
4078                 sp->m_cast_flg = 1;
4079                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4080         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4081                 /*  Disable all Multicast addresses */
4082                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4083                        &bar0->rmac_addr_data0_mem);
4084                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4085                        &bar0->rmac_addr_data1_mem);
4086                 val64 = RMAC_ADDR_CMD_MEM_WE |
4087                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4088                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4089                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4090                 /* Wait till command completes */
4091                 wait_for_cmd_complete(sp);
4092
4093                 sp->m_cast_flg = 0;
4094                 sp->all_multi_pos = 0;
4095         }
4096
4097         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4098                 /*  Put the NIC into promiscuous mode */
4099                 add = &bar0->mac_cfg;
4100                 val64 = readq(&bar0->mac_cfg);
4101                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4102
4103                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4104                 writel((u32) val64, add);
4105                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4106                 writel((u32) (val64 >> 32), (add + 4));
4107
4108                 val64 = readq(&bar0->mac_cfg);
4109                 sp->promisc_flg = 1;
4110                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4111                           dev->name);
4112         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4113                 /*  Remove the NIC from promiscuous mode */
4114                 add = &bar0->mac_cfg;
4115                 val64 = readq(&bar0->mac_cfg);
4116                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4117
4118                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4119                 writel((u32) val64, add);
4120                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4121                 writel((u32) (val64 >> 32), (add + 4));
4122
4123                 val64 = readq(&bar0->mac_cfg);
4124                 sp->promisc_flg = 0;
4125                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4126                           dev->name);
4127         }
4128
4129         /*  Update individual M_CAST address list */
4130         if ((!sp->m_cast_flg) && dev->mc_count) {
4131                 if (dev->mc_count >
4132                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4133                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4134                                   dev->name);
4135                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4136                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4137                         return;
4138                 }
4139
4140                 prev_cnt = sp->mc_addr_count;
4141                 sp->mc_addr_count = dev->mc_count;
4142
4143                 /* Clear out the previous list of Mc in the H/W. */
4144                 for (i = 0; i < prev_cnt; i++) {
4145                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4146                                &bar0->rmac_addr_data0_mem);
4147                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4148                                 &bar0->rmac_addr_data1_mem);
4149                         val64 = RMAC_ADDR_CMD_MEM_WE |
4150                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4151                             RMAC_ADDR_CMD_MEM_OFFSET
4152                             (MAC_MC_ADDR_START_OFFSET + i);
4153                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4154
4155                         /* Wait for command completes */
4156                         if (wait_for_cmd_complete(sp)) {
4157                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4158                                           dev->name);
4159                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4160                                 return;
4161                         }
4162                 }
4163
4164                 /* Create the new Rx filter list and update the same in H/W. */
4165                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4166                      i++, mclist = mclist->next) {
4167                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4168                                ETH_ALEN);
4169                         mac_addr = 0;
4170                         for (j = 0; j < ETH_ALEN; j++) {
4171                                 mac_addr |= mclist->dmi_addr[j];
4172                                 mac_addr <<= 8;
4173                         }
4174                         mac_addr >>= 8;
4175                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4176                                &bar0->rmac_addr_data0_mem);
4177                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4178                                 &bar0->rmac_addr_data1_mem);
4179                         val64 = RMAC_ADDR_CMD_MEM_WE |
4180                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4181                             RMAC_ADDR_CMD_MEM_OFFSET
4182                             (i + MAC_MC_ADDR_START_OFFSET);
4183                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4184
4185                         /* Wait for command completes */
4186                         if (wait_for_cmd_complete(sp)) {
4187                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4188                                           dev->name);
4189                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4190                                 return;
4191                         }
4192                 }
4193         }
4194 }
4195
4196 /**
4197  *  s2io_set_mac_addr - Programs the Xframe mac address
4198  *  @dev : pointer to the device structure.
4199  *  @addr: a uchar pointer to the new mac address which is to be set.
4200  *  Description : This procedure will program the Xframe to receive
4201  *  frames with new Mac Address
4202  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4203  *  as defined in errno.h file on failure.
4204  */
4205
4206 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4207 {
4208         nic_t *sp = dev->priv;
4209         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4210         register u64 val64, mac_addr = 0;
4211         int i;
4212
4213         /*
4214          * Set the new MAC address as the new unicast filter and reflect this
4215          * change on the device address registered with the OS. It will be
4216          * at offset 0.
4217          */
4218         for (i = 0; i < ETH_ALEN; i++) {
4219                 mac_addr <<= 8;
4220                 mac_addr |= addr[i];
4221         }
4222
4223         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4224                &bar0->rmac_addr_data0_mem);
4225
4226         val64 =
4227             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4228             RMAC_ADDR_CMD_MEM_OFFSET(0);
4229         writeq(val64, &bar0->rmac_addr_cmd_mem);
4230         /* Wait till command completes */
4231         if (wait_for_cmd_complete(sp)) {
4232                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4233                 return FAILURE;
4234         }
4235
4236         return SUCCESS;
4237 }
4238
4239 /**
4240  * s2io_ethtool_sset - Sets different link parameters.
4241  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4242  * @info: pointer to the structure with parameters given by ethtool to set
4243  * link information.
4244  * Description:
4245  * The function sets different link parameters provided by the user onto
4246  * the NIC.
4247  * Return value:
4248  * 0 on success.
4249 */
4250
4251 static int s2io_ethtool_sset(struct net_device *dev,
4252                              struct ethtool_cmd *info)
4253 {
4254         nic_t *sp = dev->priv;
4255         if ((info->autoneg == AUTONEG_ENABLE) ||
4256             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4257                 return -EINVAL;
4258         else {
4259                 s2io_close(sp->dev);
4260                 s2io_open(sp->dev);
4261         }
4262
4263         return 0;
4264 }
4265
4266 /**
4267  * s2io_ethtol_gset - Return link specific information.
4268  * @sp : private member of the device structure, pointer to the
4269  *      s2io_nic structure.
4270  * @info : pointer to the structure with parameters given by ethtool
4271  * to return link information.
4272  * Description:
4273  * Returns link specific information like speed, duplex etc.. to ethtool.
4274  * Return value :
4275  * return 0 on success.
4276  */
4277
4278 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4279 {
4280         nic_t *sp = dev->priv;
4281         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4282         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4283         info->port = PORT_FIBRE;
4284         /* info->transceiver?? TODO */
4285
4286         if (netif_carrier_ok(sp->dev)) {
4287                 info->speed = 10000;
4288                 info->duplex = DUPLEX_FULL;
4289         } else {
4290                 info->speed = -1;
4291                 info->duplex = -1;
4292         }
4293
4294         info->autoneg = AUTONEG_DISABLE;
4295         return 0;
4296 }
4297
4298 /**
4299  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4300  * @sp : private member of the device structure, which is a pointer to the
4301  * s2io_nic structure.
4302  * @info : pointer to the structure with parameters given by ethtool to
4303  * return driver information.
4304  * Description:
4305  * Returns driver specefic information like name, version etc.. to ethtool.
4306  * Return value:
4307  *  void
4308  */
4309
4310 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4311                                   struct ethtool_drvinfo *info)
4312 {
4313         nic_t *sp = dev->priv;
4314
4315         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4316         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4317         strncpy(info->fw_version, "", sizeof(info->fw_version));
4318         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4319         info->regdump_len = XENA_REG_SPACE;
4320         info->eedump_len = XENA_EEPROM_SPACE;
4321         info->testinfo_len = S2IO_TEST_LEN;
4322         info->n_stats = S2IO_STAT_LEN;
4323 }
4324
4325 /**
4326  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4327  *  @sp: private member of the device structure, which is a pointer to the
4328  *  s2io_nic structure.
4329  *  @regs : pointer to the structure with parameters given by ethtool for
4330  *  dumping the registers.
4331  *  @reg_space: The input argumnet into which all the registers are dumped.
4332  *  Description:
4333  *  Dumps the entire register space of xFrame NIC into the user given
4334  *  buffer area.
4335  * Return value :
4336  * void .
4337 */
4338
4339 static void s2io_ethtool_gregs(struct net_device *dev,
4340                                struct ethtool_regs *regs, void *space)
4341 {
4342         int i;
4343         u64 reg;
4344         u8 *reg_space = (u8 *) space;
4345         nic_t *sp = dev->priv;
4346
4347         regs->len = XENA_REG_SPACE;
4348         regs->version = sp->pdev->subsystem_device;
4349
4350         for (i = 0; i < regs->len; i += 8) {
4351                 reg = readq(sp->bar0 + i);
4352                 memcpy((reg_space + i), &reg, 8);
4353         }
4354 }
4355
4356 /**
4357  *  s2io_phy_id  - timer function that alternates adapter LED.
4358  *  @data : address of the private member of the device structure, which
4359  *  is a pointer to the s2io_nic structure, provided as an u32.
4360  * Description: This is actually the timer function that alternates the
4361  * adapter LED bit of the adapter control bit to set/reset every time on
4362  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4363  *  once every second.
4364 */
4365 static void s2io_phy_id(unsigned long data)
4366 {
4367         nic_t *sp = (nic_t *) data;
4368         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4369         u64 val64 = 0;
4370         u16 subid;
4371
4372         subid = sp->pdev->subsystem_device;
4373         if ((sp->device_type == XFRAME_II_DEVICE) ||
4374                    ((subid & 0xFF) >= 0x07)) {
4375                 val64 = readq(&bar0->gpio_control);
4376                 val64 ^= GPIO_CTRL_GPIO_0;
4377                 writeq(val64, &bar0->gpio_control);
4378         } else {
4379                 val64 = readq(&bar0->adapter_control);
4380                 val64 ^= ADAPTER_LED_ON;
4381                 writeq(val64, &bar0->adapter_control);
4382         }
4383
4384         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4385 }
4386
4387 /**
4388  * s2io_ethtool_idnic - To physically identify the nic on the system.
4389  * @sp : private member of the device structure, which is a pointer to the
4390  * s2io_nic structure.
4391  * @id : pointer to the structure with identification parameters given by
4392  * ethtool.
4393  * Description: Used to physically identify the NIC on the system.
4394  * The Link LED will blink for a time specified by the user for
4395  * identification.
4396  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4397  * identification is possible only if it's link is up.
4398  * Return value:
4399  * int , returns 0 on success
4400  */
4401
4402 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4403 {
4404         u64 val64 = 0, last_gpio_ctrl_val;
4405         nic_t *sp = dev->priv;
4406         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4407         u16 subid;
4408
4409         subid = sp->pdev->subsystem_device;
4410         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4411         if ((sp->device_type == XFRAME_I_DEVICE) &&
4412                 ((subid & 0xFF) < 0x07)) {
4413                 val64 = readq(&bar0->adapter_control);
4414                 if (!(val64 & ADAPTER_CNTL_EN)) {
4415                         printk(KERN_ERR
4416                                "Adapter Link down, cannot blink LED\n");
4417                         return -EFAULT;
4418                 }
4419         }
4420         if (sp->id_timer.function == NULL) {
4421                 init_timer(&sp->id_timer);
4422                 sp->id_timer.function = s2io_phy_id;
4423                 sp->id_timer.data = (unsigned long) sp;
4424         }
4425         mod_timer(&sp->id_timer, jiffies);
4426         if (data)
4427                 msleep_interruptible(data * HZ);
4428         else
4429                 msleep_interruptible(MAX_FLICKER_TIME);
4430         del_timer_sync(&sp->id_timer);
4431
4432         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4433                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4434                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4435         }
4436
4437         return 0;
4438 }
4439
4440 /**
4441  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4442  * @sp : private member of the device structure, which is a pointer to the
4443  *      s2io_nic structure.
4444  * @ep : pointer to the structure with pause parameters given by ethtool.
4445  * Description:
4446  * Returns the Pause frame generation and reception capability of the NIC.
4447  * Return value:
4448  *  void
4449  */
4450 static void s2io_ethtool_getpause_data(struct net_device *dev,
4451                                        struct ethtool_pauseparam *ep)
4452 {
4453         u64 val64;
4454         nic_t *sp = dev->priv;
4455         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4456
4457         val64 = readq(&bar0->rmac_pause_cfg);
4458         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4459                 ep->tx_pause = TRUE;
4460         if (val64 & RMAC_PAUSE_RX_ENABLE)
4461                 ep->rx_pause = TRUE;
4462         ep->autoneg = FALSE;
4463 }
4464
4465 /**
4466  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4467  * @sp : private member of the device structure, which is a pointer to the
4468  *      s2io_nic structure.
4469  * @ep : pointer to the structure with pause parameters given by ethtool.
4470  * Description:
4471  * It can be used to set or reset Pause frame generation or reception
4472  * support of the NIC.
4473  * Return value:
4474  * int, returns 0 on Success
4475  */
4476
4477 static int s2io_ethtool_setpause_data(struct net_device *dev,
4478                                struct ethtool_pauseparam *ep)
4479 {
4480         u64 val64;
4481         nic_t *sp = dev->priv;
4482         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4483
4484         val64 = readq(&bar0->rmac_pause_cfg);
4485         if (ep->tx_pause)
4486                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4487         else
4488                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4489         if (ep->rx_pause)
4490                 val64 |= RMAC_PAUSE_RX_ENABLE;
4491         else
4492                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4493         writeq(val64, &bar0->rmac_pause_cfg);
4494         return 0;
4495 }
4496
4497 /**
4498  * read_eeprom - reads 4 bytes of data from user given offset.
4499  * @sp : private member of the device structure, which is a pointer to the
4500  *      s2io_nic structure.
4501  * @off : offset at which the data must be written
4502  * @data : Its an output parameter where the data read at the given
4503  *      offset is stored.
4504  * Description:
4505  * Will read 4 bytes of data from the user given offset and return the
4506  * read data.
4507  * NOTE: Will allow to read only part of the EEPROM visible through the
4508  *   I2C bus.
4509  * Return value:
4510  *  -1 on failure and 0 on success.
4511  */
4512
4513 #define S2IO_DEV_ID             5
4514 static int read_eeprom(nic_t * sp, int off, u64 * data)
4515 {
4516         int ret = -1;
4517         u32 exit_cnt = 0;
4518         u64 val64;
4519         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4520
4521         if (sp->device_type == XFRAME_I_DEVICE) {
4522                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4523                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4524                     I2C_CONTROL_CNTL_START;
4525                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4526
4527                 while (exit_cnt < 5) {
4528                         val64 = readq(&bar0->i2c_control);
4529                         if (I2C_CONTROL_CNTL_END(val64)) {
4530                                 *data = I2C_CONTROL_GET_DATA(val64);
4531                                 ret = 0;
4532                                 break;
4533                         }
4534                         msleep(50);
4535                         exit_cnt++;
4536                 }
4537         }
4538
4539         if (sp->device_type == XFRAME_II_DEVICE) {
4540                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4541                         SPI_CONTROL_BYTECNT(0x3) |
4542                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4543                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4544                 val64 |= SPI_CONTROL_REQ;
4545                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4546                 while (exit_cnt < 5) {
4547                         val64 = readq(&bar0->spi_control);
4548                         if (val64 & SPI_CONTROL_NACK) {
4549                                 ret = 1;
4550                                 break;
4551                         } else if (val64 & SPI_CONTROL_DONE) {
4552                                 *data = readq(&bar0->spi_data);
4553                                 *data &= 0xffffff;
4554                                 ret = 0;
4555                                 break;
4556                         }
4557                         msleep(50);
4558                         exit_cnt++;
4559                 }
4560         }
4561         return ret;
4562 }
4563
4564 /**
4565  *  write_eeprom - actually writes the relevant part of the data value.
4566  *  @sp : private member of the device structure, which is a pointer to the
4567  *       s2io_nic structure.
4568  *  @off : offset at which the data must be written
4569  *  @data : The data that is to be written
4570  *  @cnt : Number of bytes of the data that are actually to be written into
4571  *  the Eeprom. (max of 3)
4572  * Description:
4573  *  Actually writes the relevant part of the data value into the Eeprom
4574  *  through the I2C bus.
4575  * Return value:
4576  *  0 on success, -1 on failure.
4577  */
4578
4579 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4580 {
4581         int exit_cnt = 0, ret = -1;
4582         u64 val64;
4583         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4584
4585         if (sp->device_type == XFRAME_I_DEVICE) {
4586                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4587                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4588                     I2C_CONTROL_CNTL_START;
4589                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4590
4591                 while (exit_cnt < 5) {
4592                         val64 = readq(&bar0->i2c_control);
4593                         if (I2C_CONTROL_CNTL_END(val64)) {
4594                                 if (!(val64 & I2C_CONTROL_NACK))
4595                                         ret = 0;
4596                                 break;
4597                         }
4598                         msleep(50);
4599                         exit_cnt++;
4600                 }
4601         }
4602
4603         if (sp->device_type == XFRAME_II_DEVICE) {
4604                 int write_cnt = (cnt == 8) ? 0 : cnt;
4605                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4606
4607                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4608                         SPI_CONTROL_BYTECNT(write_cnt) |
4609                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4610                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4611                 val64 |= SPI_CONTROL_REQ;
4612                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4613                 while (exit_cnt < 5) {
4614                         val64 = readq(&bar0->spi_control);
4615                         if (val64 & SPI_CONTROL_NACK) {
4616                                 ret = 1;
4617                                 break;
4618                         } else if (val64 & SPI_CONTROL_DONE) {
4619                                 ret = 0;
4620                                 break;
4621                         }
4622                         msleep(50);
4623                         exit_cnt++;
4624                 }
4625         }
4626         return ret;
4627 }
4628
4629 /**
4630  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4631  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4632  *  @eeprom : pointer to the user level structure provided by ethtool,
4633  *  containing all relevant information.
4634  *  @data_buf : user defined value to be written into Eeprom.
4635  *  Description: Reads the values stored in the Eeprom at given offset
4636  *  for a given length. Stores these values int the input argument data
4637  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4638  *  Return value:
4639  *  int  0 on success
4640  */
4641
4642 static int s2io_ethtool_geeprom(struct net_device *dev,
4643                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4644 {
4645         u32 i, valid;
4646         u64 data;
4647         nic_t *sp = dev->priv;
4648
4649         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4650
4651         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4652                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4653
4654         for (i = 0; i < eeprom->len; i += 4) {
4655                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4656                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4657                         return -EFAULT;
4658                 }
4659                 valid = INV(data);
4660                 memcpy((data_buf + i), &valid, 4);
4661         }
4662         return 0;
4663 }
4664
4665 /**
4666  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4667  *  @sp : private member of the device structure, which is a pointer to the
4668  *  s2io_nic structure.
4669  *  @eeprom : pointer to the user level structure provided by ethtool,
4670  *  containing all relevant information.
4671  *  @data_buf ; user defined value to be written into Eeprom.
4672  *  Description:
4673  *  Tries to write the user provided value in the Eeprom, at the offset
4674  *  given by the user.
4675  *  Return value:
4676  *  0 on success, -EFAULT on failure.
4677  */
4678
4679 static int s2io_ethtool_seeprom(struct net_device *dev,
4680                                 struct ethtool_eeprom *eeprom,
4681                                 u8 * data_buf)
4682 {
4683         int len = eeprom->len, cnt = 0;
4684         u64 valid = 0, data;
4685         nic_t *sp = dev->priv;
4686
4687         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4688                 DBG_PRINT(ERR_DBG,
4689                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4690                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4691                           eeprom->magic);
4692                 return -EFAULT;
4693         }
4694
4695         while (len) {
4696                 data = (u32) data_buf[cnt] & 0x000000FF;
4697                 if (data) {
4698                         valid = (u32) (data << 24);
4699                 } else
4700                         valid = data;
4701
4702                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4703                         DBG_PRINT(ERR_DBG,
4704                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4705                         DBG_PRINT(ERR_DBG,
4706                                   "write into the specified offset\n");
4707                         return -EFAULT;
4708                 }
4709                 cnt++;
4710                 len--;
4711         }
4712
4713         return 0;
4714 }
4715
4716 /**
4717  * s2io_register_test - reads and writes into all clock domains.
4718  * @sp : private member of the device structure, which is a pointer to the
4719  * s2io_nic structure.
4720  * @data : variable that returns the result of each of the test conducted b
4721  * by the driver.
4722  * Description:
4723  * Read and write into all clock domains. The NIC has 3 clock domains,
4724  * see that registers in all the three regions are accessible.
4725  * Return value:
4726  * 0 on success.
4727  */
4728
4729 static int s2io_register_test(nic_t * sp, uint64_t * data)
4730 {
4731         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4732         u64 val64 = 0, exp_val;
4733         int fail = 0;
4734
4735         val64 = readq(&bar0->pif_rd_swapper_fb);
4736         if (val64 != 0x123456789abcdefULL) {
4737                 fail = 1;
4738                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
4739         }
4740
4741         val64 = readq(&bar0->rmac_pause_cfg);
4742         if (val64 != 0xc000ffff00000000ULL) {
4743                 fail = 1;
4744                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
4745         }
4746
4747         val64 = readq(&bar0->rx_queue_cfg);
4748         if (sp->device_type == XFRAME_II_DEVICE)
4749                 exp_val = 0x0404040404040404ULL;
4750         else
4751                 exp_val = 0x0808080808080808ULL;
4752         if (val64 != exp_val) {
4753                 fail = 1;
4754                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4755         }
4756
4757         val64 = readq(&bar0->xgxs_efifo_cfg);
4758         if (val64 != 0x000000001923141EULL) {
4759                 fail = 1;
4760                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
4761         }
4762
4763         val64 = 0x5A5A5A5A5A5A5A5AULL;
4764         writeq(val64, &bar0->xmsi_data);
4765         val64 = readq(&bar0->xmsi_data);
4766         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
4767                 fail = 1;
4768                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
4769         }
4770
4771         val64 = 0xA5A5A5A5A5A5A5A5ULL;
4772         writeq(val64, &bar0->xmsi_data);
4773         val64 = readq(&bar0->xmsi_data);
4774         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
4775                 fail = 1;
4776                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
4777         }
4778
4779         *data = fail;
4780         return fail;
4781 }
4782
4783 /**
4784  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4785  * @sp : private member of the device structure, which is a pointer to the
4786  * s2io_nic structure.
4787  * @data:variable that returns the result of each of the test conducted by
4788  * the driver.
4789  * Description:
4790  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4791  * register.
4792  * Return value:
4793  * 0 on success.
4794  */
4795
4796 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4797 {
4798         int fail = 0;
4799         u64 ret_data, org_4F0, org_7F0;
4800         u8 saved_4F0 = 0, saved_7F0 = 0;
4801         struct net_device *dev = sp->dev;
4802
4803         /* Test Write Error at offset 0 */
4804         /* Note that SPI interface allows write access to all areas
4805          * of EEPROM. Hence doing all negative testing only for Xframe I.
4806          */
4807         if (sp->device_type == XFRAME_I_DEVICE)
4808                 if (!write_eeprom(sp, 0, 0, 3))
4809                         fail = 1;
4810
4811         /* Save current values at offsets 0x4F0 and 0x7F0 */
4812         if (!read_eeprom(sp, 0x4F0, &org_4F0))
4813                 saved_4F0 = 1;
4814         if (!read_eeprom(sp, 0x7F0, &org_7F0))
4815                 saved_7F0 = 1;
4816
4817         /* Test Write at offset 4f0 */
4818         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4819                 fail = 1;
4820         if (read_eeprom(sp, 0x4F0, &ret_data))
4821                 fail = 1;
4822
4823         if (ret_data != 0x012345) {
4824                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
4825                         "Data written %llx Data read %llx\n",
4826                         dev->name, (unsigned long long)0x12345,
4827                         (unsigned long long)ret_data);
4828                 fail = 1;
4829         }
4830
4831         /* Reset the EEPROM data go FFFF */
4832         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4833
4834         /* Test Write Request Error at offset 0x7c */
4835         if (sp->device_type == XFRAME_I_DEVICE)
4836                 if (!write_eeprom(sp, 0x07C, 0, 3))
4837                         fail = 1;
4838
4839         /* Test Write Request at offset 0x7f0 */
4840         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4841                 fail = 1;
4842         if (read_eeprom(sp, 0x7F0, &ret_data))
4843                 fail = 1;
4844
4845         if (ret_data != 0x012345) {
4846                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
4847                         "Data written %llx Data read %llx\n",
4848                         dev->name, (unsigned long long)0x12345,
4849                         (unsigned long long)ret_data);
4850                 fail = 1;
4851         }
4852
4853         /* Reset the EEPROM data go FFFF */
4854         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4855
4856         if (sp->device_type == XFRAME_I_DEVICE) {
4857                 /* Test Write Error at offset 0x80 */
4858                 if (!write_eeprom(sp, 0x080, 0, 3))
4859                         fail = 1;
4860
4861                 /* Test Write Error at offset 0xfc */
4862                 if (!write_eeprom(sp, 0x0FC, 0, 3))
4863                         fail = 1;
4864
4865                 /* Test Write Error at offset 0x100 */
4866                 if (!write_eeprom(sp, 0x100, 0, 3))
4867                         fail = 1;
4868
4869                 /* Test Write Error at offset 4ec */
4870                 if (!write_eeprom(sp, 0x4EC, 0, 3))
4871                         fail = 1;
4872         }
4873
4874         /* Restore values at offsets 0x4F0 and 0x7F0 */
4875         if (saved_4F0)
4876                 write_eeprom(sp, 0x4F0, org_4F0, 3);
4877         if (saved_7F0)
4878                 write_eeprom(sp, 0x7F0, org_7F0, 3);
4879
4880         *data = fail;
4881         return fail;
4882 }
4883
4884 /**
4885  * s2io_bist_test - invokes the MemBist test of the card .
4886  * @sp : private member of the device structure, which is a pointer to the
4887  * s2io_nic structure.
4888  * @data:variable that returns the result of each of the test conducted by
4889  * the driver.
4890  * Description:
4891  * This invokes the MemBist test of the card. We give around
4892  * 2 secs time for the Test to complete. If it's still not complete
4893  * within this peiod, we consider that the test failed.
4894  * Return value:
4895  * 0 on success and -1 on failure.
4896  */
4897
4898 static int s2io_bist_test(nic_t * sp, uint64_t * data)
4899 {
4900         u8 bist = 0;
4901         int cnt = 0, ret = -1;
4902
4903         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4904         bist |= PCI_BIST_START;
4905         pci_write_config_word(sp->pdev, PCI_BIST, bist);
4906
4907         while (cnt < 20) {
4908                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4909                 if (!(bist & PCI_BIST_START)) {
4910                         *data = (bist & PCI_BIST_CODE_MASK);
4911                         ret = 0;
4912                         break;
4913                 }
4914                 msleep(100);
4915                 cnt++;
4916         }
4917
4918         return ret;
4919 }
4920
4921 /**
4922  * s2io-link_test - verifies the link state of the nic
4923  * @sp ; private member of the device structure, which is a pointer to the
4924  * s2io_nic structure.
4925  * @data: variable that returns the result of each of the test conducted by
4926  * the driver.
4927  * Description:
4928  * The function verifies the link state of the NIC and updates the input
4929  * argument 'data' appropriately.
4930  * Return value:
4931  * 0 on success.
4932  */
4933
4934 static int s2io_link_test(nic_t * sp, uint64_t * data)
4935 {
4936         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4937         u64 val64;
4938
4939         val64 = readq(&bar0->adapter_status);
4940         if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
4941                 *data = 1;
4942
4943         return 0;
4944 }
4945
4946 /**
4947  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4948  * @sp - private member of the device structure, which is a pointer to the
4949  * s2io_nic structure.
4950  * @data - variable that returns the result of each of the test
4951  * conducted by the driver.
4952  * Description:
4953  *  This is one of the offline test that tests the read and write
4954  *  access to the RldRam chip on the NIC.
4955  * Return value:
4956  *  0 on success.
4957  */
4958
4959 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4960 {
4961         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4962         u64 val64;
4963         int cnt, iteration = 0, test_fail = 0;
4964
4965         val64 = readq(&bar0->adapter_control);
4966         val64 &= ~ADAPTER_ECC_EN;
4967         writeq(val64, &bar0->adapter_control);
4968
4969         val64 = readq(&bar0->mc_rldram_test_ctrl);
4970         val64 |= MC_RLDRAM_TEST_MODE;
4971         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4972
4973         val64 = readq(&bar0->mc_rldram_mrs);
4974         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
4975         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4976
4977         val64 |= MC_RLDRAM_MRS_ENABLE;
4978         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4979
4980         while (iteration < 2) {
4981                 val64 = 0x55555555aaaa0000ULL;
4982                 if (iteration == 1) {
4983                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4984                 }
4985                 writeq(val64, &bar0->mc_rldram_test_d0);
4986
4987                 val64 = 0xaaaa5a5555550000ULL;
4988                 if (iteration == 1) {
4989                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4990                 }
4991                 writeq(val64, &bar0->mc_rldram_test_d1);
4992
4993                 val64 = 0x55aaaaaaaa5a0000ULL;
4994                 if (iteration == 1) {
4995                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4996                 }
4997                 writeq(val64, &bar0->mc_rldram_test_d2);
4998
4999                 val64 = (u64) (0x0000003ffffe0100ULL);
5000                 writeq(val64, &bar0->mc_rldram_test_add);
5001
5002                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5003                         MC_RLDRAM_TEST_GO;
5004                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5005
5006                 for (cnt = 0; cnt < 5; cnt++) {
5007                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5008                         if (val64 & MC_RLDRAM_TEST_DONE)
5009                                 break;
5010                         msleep(200);
5011                 }
5012
5013                 if (cnt == 5)
5014                         break;
5015
5016                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5017                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5018
5019                 for (cnt = 0; cnt < 5; cnt++) {
5020                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5021                         if (val64 & MC_RLDRAM_TEST_DONE)
5022                                 break;
5023                         msleep(500);
5024                 }
5025
5026                 if (cnt == 5)
5027                         break;
5028
5029                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5030                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5031                         test_fail = 1;
5032
5033                 iteration++;
5034         }
5035
5036         *data = test_fail;
5037
5038         /* Bring the adapter out of test mode */
5039         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5040
5041         return test_fail;
5042 }
5043
5044 /**
5045  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5046  *  @sp : private member of the device structure, which is a pointer to the
5047  *  s2io_nic structure.
5048  *  @ethtest : pointer to a ethtool command specific structure that will be
5049  *  returned to the user.
5050  *  @data : variable that returns the result of each of the test
5051  * conducted by the driver.
5052  * Description:
5053  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5054  *  the health of the card.
5055  * Return value:
5056  *  void
5057  */
5058
5059 static void s2io_ethtool_test(struct net_device *dev,
5060                               struct ethtool_test *ethtest,
5061                               uint64_t * data)
5062 {
5063         nic_t *sp = dev->priv;
5064         int orig_state = netif_running(sp->dev);
5065
5066         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5067                 /* Offline Tests. */
5068                 if (orig_state)
5069                         s2io_close(sp->dev);
5070
5071                 if (s2io_register_test(sp, &data[0]))
5072                         ethtest->flags |= ETH_TEST_FL_FAILED;
5073
5074                 s2io_reset(sp);
5075
5076                 if (s2io_rldram_test(sp, &data[3]))
5077                         ethtest->flags |= ETH_TEST_FL_FAILED;
5078
5079                 s2io_reset(sp);
5080
5081                 if (s2io_eeprom_test(sp, &data[1]))
5082                         ethtest->flags |= ETH_TEST_FL_FAILED;
5083
5084                 if (s2io_bist_test(sp, &data[4]))
5085                         ethtest->flags |= ETH_TEST_FL_FAILED;
5086
5087                 if (orig_state)
5088                         s2io_open(sp->dev);
5089
5090                 data[2] = 0;
5091         } else {
5092                 /* Online Tests. */
5093                 if (!orig_state) {
5094                         DBG_PRINT(ERR_DBG,
5095                                   "%s: is not up, cannot run test\n",
5096                                   dev->name);
5097                         data[0] = -1;
5098                         data[1] = -1;
5099                         data[2] = -1;
5100                         data[3] = -1;
5101                         data[4] = -1;
5102                 }
5103
5104                 if (s2io_link_test(sp, &data[2]))
5105                         ethtest->flags |= ETH_TEST_FL_FAILED;
5106
5107                 data[0] = 0;
5108                 data[1] = 0;
5109                 data[3] = 0;
5110                 data[4] = 0;
5111         }
5112 }
5113
5114 static void s2io_get_ethtool_stats(struct net_device *dev,
5115                                    struct ethtool_stats *estats,
5116                                    u64 * tmp_stats)
5117 {
5118         int i = 0;
5119         nic_t *sp = dev->priv;
5120         StatInfo_t *stat_info = sp->mac_control.stats_info;
5121         u64 tmp;
5122
5123         s2io_updt_stats(sp);
5124         tmp_stats[i++] =
5125                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5126                 le32_to_cpu(stat_info->tmac_frms);
5127         tmp_stats[i++] =
5128                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5129                 le32_to_cpu(stat_info->tmac_data_octets);
5130         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5131         tmp_stats[i++] =
5132                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5133                 le32_to_cpu(stat_info->tmac_mcst_frms);
5134         tmp_stats[i++] =
5135                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5136                 le32_to_cpu(stat_info->tmac_bcst_frms);
5137         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5138         tmp_stats[i++] =
5139                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5140                 le32_to_cpu(stat_info->tmac_any_err_frms);
5141         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5142         tmp_stats[i++] =
5143                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5144                 le32_to_cpu(stat_info->tmac_vld_ip);
5145         tmp_stats[i++] =
5146                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5147                 le32_to_cpu(stat_info->tmac_drop_ip);
5148         tmp_stats[i++] =
5149                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5150                 le32_to_cpu(stat_info->tmac_icmp);
5151         tmp_stats[i++] =
5152                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5153                 le32_to_cpu(stat_info->tmac_rst_tcp);
5154         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5155         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5156                 le32_to_cpu(stat_info->tmac_udp);
5157         tmp_stats[i++] =
5158                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5159                 le32_to_cpu(stat_info->rmac_vld_frms);
5160         tmp_stats[i++] =
5161                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5162                 le32_to_cpu(stat_info->rmac_data_octets);
5163         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5164         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5165         tmp_stats[i++] =
5166                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5167                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5168         tmp_stats[i++] =
5169                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5170                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5171         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5172         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5173         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5174         tmp_stats[i++] =
5175                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5176                 le32_to_cpu(stat_info->rmac_discarded_frms);
5177         tmp_stats[i++] =
5178                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5179                 le32_to_cpu(stat_info->rmac_usized_frms);
5180         tmp_stats[i++] =
5181                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5182                 le32_to_cpu(stat_info->rmac_osized_frms);
5183         tmp_stats[i++] =
5184                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5185                 le32_to_cpu(stat_info->rmac_frag_frms);
5186         tmp_stats[i++] =
5187                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5188                 le32_to_cpu(stat_info->rmac_jabber_frms);
5189         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5190                 le32_to_cpu(stat_info->rmac_ip);
5191         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5192         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5193         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5194                 le32_to_cpu(stat_info->rmac_drop_ip);
5195         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5196                 le32_to_cpu(stat_info->rmac_icmp);
5197         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5198         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5199                 le32_to_cpu(stat_info->rmac_udp);
5200         tmp_stats[i++] =
5201                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5202                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5203         tmp_stats[i++] =
5204                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5205                 le32_to_cpu(stat_info->rmac_pause_cnt);
5206         tmp_stats[i++] =
5207                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5208                 le32_to_cpu(stat_info->rmac_accepted_ip);
5209         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5210         tmp_stats[i++] = 0;
5211         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5212         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5213         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5214         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5215         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5216         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5217         tmp = 0;
5218         if (stat_info->sw_stat.num_aggregations) {
5219                 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5220                 do_div(tmp, stat_info->sw_stat.num_aggregations);
5221         }
5222         tmp_stats[i++] = tmp;
5223 }
5224
5225 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5226 {
5227         return (XENA_REG_SPACE);
5228 }
5229
5230
5231 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5232 {
5233         nic_t *sp = dev->priv;
5234
5235         return (sp->rx_csum);
5236 }
5237
5238 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5239 {
5240         nic_t *sp = dev->priv;
5241
5242         if (data)
5243                 sp->rx_csum = 1;
5244         else
5245                 sp->rx_csum = 0;
5246
5247         return 0;
5248 }
5249
5250 static int s2io_get_eeprom_len(struct net_device *dev)
5251 {
5252         return (XENA_EEPROM_SPACE);
5253 }
5254
5255 static int s2io_ethtool_self_test_count(struct net_device *dev)
5256 {
5257         return (S2IO_TEST_LEN);
5258 }
5259
5260 static void s2io_ethtool_get_strings(struct net_device *dev,
5261                                      u32 stringset, u8 * data)
5262 {
5263         switch (stringset) {
5264         case ETH_SS_TEST:
5265                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5266                 break;
5267         case ETH_SS_STATS:
5268                 memcpy(data, &ethtool_stats_keys,
5269                        sizeof(ethtool_stats_keys));
5270         }
5271 }
5272 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5273 {
5274         return (S2IO_STAT_LEN);
5275 }
5276
5277 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5278 {
5279         if (data)
5280                 dev->features |= NETIF_F_IP_CSUM;
5281         else
5282                 dev->features &= ~NETIF_F_IP_CSUM;
5283
5284         return 0;
5285 }
5286
5287
5288 static struct ethtool_ops netdev_ethtool_ops = {
5289         .get_settings = s2io_ethtool_gset,
5290         .set_settings = s2io_ethtool_sset,
5291         .get_drvinfo = s2io_ethtool_gdrvinfo,
5292         .get_regs_len = s2io_ethtool_get_regs_len,
5293         .get_regs = s2io_ethtool_gregs,
5294         .get_link = ethtool_op_get_link,
5295         .get_eeprom_len = s2io_get_eeprom_len,
5296         .get_eeprom = s2io_ethtool_geeprom,
5297         .set_eeprom = s2io_ethtool_seeprom,
5298         .get_pauseparam = s2io_ethtool_getpause_data,
5299         .set_pauseparam = s2io_ethtool_setpause_data,
5300         .get_rx_csum = s2io_ethtool_get_rx_csum,
5301         .set_rx_csum = s2io_ethtool_set_rx_csum,
5302         .get_tx_csum = ethtool_op_get_tx_csum,
5303         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5304         .get_sg = ethtool_op_get_sg,
5305         .set_sg = ethtool_op_set_sg,
5306 #ifdef NETIF_F_TSO
5307         .get_tso = ethtool_op_get_tso,
5308         .set_tso = ethtool_op_set_tso,
5309 #endif
5310         .get_ufo = ethtool_op_get_ufo,
5311         .set_ufo = ethtool_op_set_ufo,
5312         .self_test_count = s2io_ethtool_self_test_count,
5313         .self_test = s2io_ethtool_test,
5314         .get_strings = s2io_ethtool_get_strings,
5315         .phys_id = s2io_ethtool_idnic,
5316         .get_stats_count = s2io_ethtool_get_stats_count,
5317         .get_ethtool_stats = s2io_get_ethtool_stats
5318 };
5319
5320 /**
5321  *  s2io_ioctl - Entry point for the Ioctl
5322  *  @dev :  Device pointer.
5323  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5324  *  a proprietary structure used to pass information to the driver.
5325  *  @cmd :  This is used to distinguish between the different commands that
5326  *  can be passed to the IOCTL functions.
5327  *  Description:
5328  *  Currently there are no special functionality supported in IOCTL, hence
5329  *  function always return EOPNOTSUPPORTED
5330  */
5331
5332 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5333 {
5334         return -EOPNOTSUPP;
5335 }
5336
5337 /**
5338  *  s2io_change_mtu - entry point to change MTU size for the device.
5339  *   @dev : device pointer.
5340  *   @new_mtu : the new MTU size for the device.
5341  *   Description: A driver entry point to change MTU size for the device.
5342  *   Before changing the MTU the device must be stopped.
5343  *  Return value:
5344  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5345  *   file on failure.
5346  */
5347
5348 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5349 {
5350         nic_t *sp = dev->priv;
5351
5352         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5353                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5354                           dev->name);
5355                 return -EPERM;
5356         }
5357
5358         dev->mtu = new_mtu;
5359         if (netif_running(dev)) {
5360                 s2io_card_down(sp);
5361                 netif_stop_queue(dev);
5362                 if (s2io_card_up(sp)) {
5363                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5364                                   __FUNCTION__);
5365                 }
5366                 if (netif_queue_stopped(dev))
5367                         netif_wake_queue(dev);
5368         } else { /* Device is down */
5369                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5370                 u64 val64 = new_mtu;
5371
5372                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5373         }
5374
5375         return 0;
5376 }
5377
5378 /**
5379  *  s2io_tasklet - Bottom half of the ISR.
5380  *  @dev_adr : address of the device structure in dma_addr_t format.
5381  *  Description:
5382  *  This is the tasklet or the bottom half of the ISR. This is
5383  *  an extension of the ISR which is scheduled by the scheduler to be run
5384  *  when the load on the CPU is low. All low priority tasks of the ISR can
5385  *  be pushed into the tasklet. For now the tasklet is used only to
5386  *  replenish the Rx buffers in the Rx buffer descriptors.
5387  *  Return value:
5388  *  void.
5389  */
5390
5391 static void s2io_tasklet(unsigned long dev_addr)
5392 {
5393         struct net_device *dev = (struct net_device *) dev_addr;
5394         nic_t *sp = dev->priv;
5395         int i, ret;
5396         mac_info_t *mac_control;
5397         struct config_param *config;
5398
5399         mac_control = &sp->mac_control;
5400         config = &sp->config;
5401
5402         if (!TASKLET_IN_USE) {
5403                 for (i = 0; i < config->rx_ring_num; i++) {
5404                         ret = fill_rx_buffers(sp, i);
5405                         if (ret == -ENOMEM) {
5406                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5407                                           dev->name);
5408                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5409                                 break;
5410                         } else if (ret == -EFILL) {
5411                                 DBG_PRINT(ERR_DBG,
5412                                           "%s: Rx Ring %d is full\n",
5413                                           dev->name, i);
5414                                 break;
5415                         }
5416                 }
5417                 clear_bit(0, (&sp->tasklet_status));
5418         }
5419 }
5420
5421 /**
5422  * s2io_set_link - Set the LInk status
5423  * @data: long pointer to device private structue
5424  * Description: Sets the link status for the adapter
5425  */
5426
5427 static void s2io_set_link(unsigned long data)
5428 {
5429         nic_t *nic = (nic_t *) data;
5430         struct net_device *dev = nic->dev;
5431         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5432         register u64 val64;
5433         u16 subid;
5434
5435         if (test_and_set_bit(0, &(nic->link_state))) {
5436                 /* The card is being reset, no point doing anything */
5437                 return;
5438         }
5439
5440         subid = nic->pdev->subsystem_device;
5441         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5442                 /*
5443                  * Allow a small delay for the NICs self initiated
5444                  * cleanup to complete.
5445                  */
5446                 msleep(100);
5447         }
5448
5449         val64 = readq(&bar0->adapter_status);
5450         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5451                 if (LINK_IS_UP(val64)) {
5452                         val64 = readq(&bar0->adapter_control);
5453                         val64 |= ADAPTER_CNTL_EN;
5454                         writeq(val64, &bar0->adapter_control);
5455                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5456                                                              subid)) {
5457                                 val64 = readq(&bar0->gpio_control);
5458                                 val64 |= GPIO_CTRL_GPIO_0;
5459                                 writeq(val64, &bar0->gpio_control);
5460                                 val64 = readq(&bar0->gpio_control);
5461                         } else {
5462                                 val64 |= ADAPTER_LED_ON;
5463                                 writeq(val64, &bar0->adapter_control);
5464                         }
5465                         if (s2io_link_fault_indication(nic) ==
5466                                                 MAC_RMAC_ERR_TIMER) {
5467                                 val64 = readq(&bar0->adapter_status);
5468                                 if (!LINK_IS_UP(val64)) {
5469                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5470                                         DBG_PRINT(ERR_DBG, " Link down");
5471                                         DBG_PRINT(ERR_DBG, "after ");
5472                                         DBG_PRINT(ERR_DBG, "enabling ");
5473                                         DBG_PRINT(ERR_DBG, "device \n");
5474                                 }
5475                         }
5476                         if (nic->device_enabled_once == FALSE) {
5477                                 nic->device_enabled_once = TRUE;
5478                         }
5479                         s2io_link(nic, LINK_UP);
5480                 } else {
5481                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5482                                                               subid)) {
5483                                 val64 = readq(&bar0->gpio_control);
5484                                 val64 &= ~GPIO_CTRL_GPIO_0;
5485                                 writeq(val64, &bar0->gpio_control);
5486                                 val64 = readq(&bar0->gpio_control);
5487                         }
5488                         s2io_link(nic, LINK_DOWN);
5489                 }
5490         } else {                /* NIC is not Quiescent. */
5491                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5492                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5493                 netif_stop_queue(dev);
5494         }
5495         clear_bit(0, &(nic->link_state));
5496 }
5497
5498 static void s2io_card_down(nic_t * sp)
5499 {
5500         int cnt = 0;
5501         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5502         unsigned long flags;
5503         register u64 val64 = 0;
5504
5505         del_timer_sync(&sp->alarm_timer);
5506         /* If s2io_set_link task is executing, wait till it completes. */
5507         while (test_and_set_bit(0, &(sp->link_state))) {
5508                 msleep(50);
5509         }
5510         atomic_set(&sp->card_state, CARD_DOWN);
5511
5512         /* disable Tx and Rx traffic on the NIC */
5513         stop_nic(sp);
5514
5515         /* Kill tasklet. */
5516         tasklet_kill(&sp->task);
5517
5518         /* Check if the device is Quiescent and then Reset the NIC */
5519         do {
5520                 val64 = readq(&bar0->adapter_status);
5521                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
5522                         break;
5523                 }
5524
5525                 msleep(50);
5526                 cnt++;
5527                 if (cnt == 10) {
5528                         DBG_PRINT(ERR_DBG,
5529                                   "s2io_close:Device not Quiescent ");
5530                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
5531                                   (unsigned long long) val64);
5532                         break;
5533                 }
5534         } while (1);
5535         s2io_reset(sp);
5536
5537         /* Waiting till all Interrupt handlers are complete */
5538         cnt = 0;
5539         do {
5540                 msleep(10);
5541                 if (!atomic_read(&sp->isr_cnt))
5542                         break;
5543                 cnt++;
5544         } while(cnt < 5);
5545
5546         spin_lock_irqsave(&sp->tx_lock, flags);
5547         /* Free all Tx buffers */
5548         free_tx_buffers(sp);
5549         spin_unlock_irqrestore(&sp->tx_lock, flags);
5550
5551         /* Free all Rx buffers */
5552         spin_lock_irqsave(&sp->rx_lock, flags);
5553         free_rx_buffers(sp);
5554         spin_unlock_irqrestore(&sp->rx_lock, flags);
5555
5556         clear_bit(0, &(sp->link_state));
5557 }
5558
5559 static int s2io_card_up(nic_t * sp)
5560 {
5561         int i, ret = 0;
5562         mac_info_t *mac_control;
5563         struct config_param *config;
5564         struct net_device *dev = (struct net_device *) sp->dev;
5565
5566         /* Initialize the H/W I/O registers */
5567         if (init_nic(sp) != 0) {
5568                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
5569                           dev->name);
5570                 return -ENODEV;
5571         }
5572
5573         if (sp->intr_type == MSI)
5574                 ret = s2io_enable_msi(sp);
5575         else if (sp->intr_type == MSI_X)
5576                 ret = s2io_enable_msi_x(sp);
5577         if (ret) {
5578                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
5579                 sp->intr_type = INTA;
5580         }
5581
5582         /*
5583          * Initializing the Rx buffers. For now we are considering only 1
5584          * Rx ring and initializing buffers into 30 Rx blocks
5585          */
5586         mac_control = &sp->mac_control;
5587         config = &sp->config;
5588
5589         for (i = 0; i < config->rx_ring_num; i++) {
5590                 if ((ret = fill_rx_buffers(sp, i))) {
5591                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
5592                                   dev->name);
5593                         s2io_reset(sp);
5594                         free_rx_buffers(sp);
5595                         return -ENOMEM;
5596                 }
5597                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
5598                           atomic_read(&sp->rx_bufs_left[i]));
5599         }
5600
5601         /* Setting its receive mode */
5602         s2io_set_multicast(dev);
5603
5604         if (sp->lro) {
5605                 /* Initialize max aggregatable pkts based on MTU */
5606                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
5607                 /* Check if we can use(if specified) user provided value */
5608                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
5609                         sp->lro_max_aggr_per_sess = lro_max_pkts;
5610         }
5611
5612         /* Enable tasklet for the device */
5613         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
5614
5615         /* Enable Rx Traffic and interrupts on the NIC */
5616         if (start_nic(sp)) {
5617                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
5618                 tasklet_kill(&sp->task);
5619                 s2io_reset(sp);
5620                 free_irq(dev->irq, dev);
5621                 free_rx_buffers(sp);
5622                 return -ENODEV;
5623         }
5624
5625         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
5626
5627         atomic_set(&sp->card_state, CARD_UP);
5628         return 0;
5629 }
5630
5631 /**
5632  * s2io_restart_nic - Resets the NIC.
5633  * @data : long pointer to the device private structure
5634  * Description:
5635  * This function is scheduled to be run by the s2io_tx_watchdog
5636  * function after 0.5 secs to reset the NIC. The idea is to reduce
5637  * the run time of the watch dog routine which is run holding a
5638  * spin lock.
5639  */
5640
5641 static void s2io_restart_nic(unsigned long data)
5642 {
5643         struct net_device *dev = (struct net_device *) data;
5644         nic_t *sp = dev->priv;
5645
5646         s2io_card_down(sp);
5647         if (s2io_card_up(sp)) {
5648                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5649                           dev->name);
5650         }
5651         netif_wake_queue(dev);
5652         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
5653                   dev->name);
5654
5655 }
5656
5657 /**
5658  *  s2io_tx_watchdog - Watchdog for transmit side.
5659  *  @dev : Pointer to net device structure
5660  *  Description:
5661  *  This function is triggered if the Tx Queue is stopped
5662  *  for a pre-defined amount of time when the Interface is still up.
5663  *  If the Interface is jammed in such a situation, the hardware is
5664  *  reset (by s2io_close) and restarted again (by s2io_open) to
5665  *  overcome any problem that might have been caused in the hardware.
5666  *  Return value:
5667  *  void
5668  */
5669
5670 static void s2io_tx_watchdog(struct net_device *dev)
5671 {
5672         nic_t *sp = dev->priv;
5673
5674         if (netif_carrier_ok(dev)) {
5675                 schedule_work(&sp->rst_timer_task);
5676         }
5677 }
5678
5679 /**
5680  *   rx_osm_handler - To perform some OS related operations on SKB.
5681  *   @sp: private member of the device structure,pointer to s2io_nic structure.
5682  *   @skb : the socket buffer pointer.
5683  *   @len : length of the packet
5684  *   @cksum : FCS checksum of the frame.
5685  *   @ring_no : the ring from which this RxD was extracted.
5686  *   Description:
5687  *   This function is called by the Tx interrupt serivce routine to perform
5688  *   some OS related operations on the SKB before passing it to the upper
5689  *   layers. It mainly checks if the checksum is OK, if so adds it to the
5690  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
5691  *   to the upper layer. If the checksum is wrong, it increments the Rx
5692  *   packet error count, frees the SKB and returns error.
5693  *   Return value:
5694  *   SUCCESS on success and -1 on failure.
5695  */
5696 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5697 {
5698         nic_t *sp = ring_data->nic;
5699         struct net_device *dev = (struct net_device *) sp->dev;
5700         struct sk_buff *skb = (struct sk_buff *)
5701                 ((unsigned long) rxdp->Host_Control);
5702         int ring_no = ring_data->ring_no;
5703         u16 l3_csum, l4_csum;
5704         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5705         lro_t *lro;
5706
5707         skb->dev = dev;
5708         if (err) {
5709                 /*
5710                 * Drop the packet if bad transfer code. Exception being
5711                 * 0x5, which could be due to unsupported IPv6 extension header.
5712                 * In this case, we let stack handle the packet.
5713                 * Note that in this case, since checksum will be incorrect,
5714                 * stack will validate the same.
5715                 */
5716                 if (err && ((err >> 48) != 0x5)) {
5717                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5718                                 dev->name, err);
5719                         sp->stats.rx_crc_errors++;
5720                         dev_kfree_skb(skb);
5721                         atomic_dec(&sp->rx_bufs_left[ring_no]);
5722                         rxdp->Host_Control = 0;
5723                         return 0;
5724                 }
5725         }
5726
5727         /* Updating statistics */
5728         rxdp->Host_Control = 0;
5729         sp->rx_pkt_count++;
5730         sp->stats.rx_packets++;
5731         if (sp->rxd_mode == RXD_MODE_1) {
5732                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
5733
5734                 sp->stats.rx_bytes += len;
5735                 skb_put(skb, len);
5736
5737         } else if (sp->rxd_mode >= RXD_MODE_3A) {
5738                 int get_block = ring_data->rx_curr_get_info.block_index;
5739                 int get_off = ring_data->rx_curr_get_info.offset;
5740                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
5741                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
5742                 unsigned char *buff = skb_push(skb, buf0_len);
5743
5744                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
5745                 sp->stats.rx_bytes += buf0_len + buf2_len;
5746                 memcpy(buff, ba->ba_0, buf0_len);
5747
5748                 if (sp->rxd_mode == RXD_MODE_3A) {
5749                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
5750
5751                         skb_put(skb, buf1_len);
5752                         skb->len += buf2_len;
5753                         skb->data_len += buf2_len;
5754                         skb->truesize += buf2_len;
5755                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
5756                         sp->stats.rx_bytes += buf1_len;
5757
5758                 } else
5759                         skb_put(skb, buf2_len);
5760         }
5761
5762         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
5763             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
5764             (sp->rx_csum)) {
5765                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
5766                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
5767                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
5768                         /*
5769                          * NIC verifies if the Checksum of the received
5770                          * frame is Ok or not and accordingly returns
5771                          * a flag in the RxD.
5772                          */
5773                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5774                         if (sp->lro) {
5775                                 u32 tcp_len;
5776                                 u8 *tcp;
5777                                 int ret = 0;
5778
5779                                 ret = s2io_club_tcp_session(skb->data, &tcp,
5780                                                 &tcp_len, &lro, rxdp, sp);
5781                                 switch (ret) {
5782                                         case 3: /* Begin anew */
5783                                                 lro->parent = skb;
5784                                                 goto aggregate;
5785                                         case 1: /* Aggregate */
5786                                         {
5787                                                 lro_append_pkt(sp, lro,
5788                                                         skb, tcp_len);
5789                                                 goto aggregate;
5790                                         }
5791                                         case 4: /* Flush session */
5792                                         {
5793                                                 lro_append_pkt(sp, lro,
5794                                                         skb, tcp_len);
5795                                                 queue_rx_frame(lro->parent);
5796                                                 clear_lro_session(lro);
5797                                                 sp->mac_control.stats_info->
5798                                                     sw_stat.flush_max_pkts++;
5799                                                 goto aggregate;
5800                                         }
5801                                         case 2: /* Flush both */
5802                                                 lro->parent->data_len =
5803                                                         lro->frags_len;
5804                                                 sp->mac_control.stats_info->
5805                                                      sw_stat.sending_both++;
5806                                                 queue_rx_frame(lro->parent);
5807                                                 clear_lro_session(lro);
5808                                                 goto send_up;
5809                                         case 0: /* sessions exceeded */
5810                                         case 5: /*
5811                                                  * First pkt in session not
5812                                                  * L3/L4 aggregatable
5813                                                  */
5814                                                 break;
5815                                         default:
5816                                                 DBG_PRINT(ERR_DBG,
5817                                                         "%s: Samadhana!!\n",
5818                                                          __FUNCTION__);
5819                                                 BUG();
5820                                 }
5821                         }
5822                 } else {
5823                         /*
5824                          * Packet with erroneous checksum, let the
5825                          * upper layers deal with it.
5826                          */
5827                         skb->ip_summed = CHECKSUM_NONE;
5828                 }
5829         } else {
5830                 skb->ip_summed = CHECKSUM_NONE;
5831         }
5832
5833         if (!sp->lro) {
5834                 skb->protocol = eth_type_trans(skb, dev);
5835 #ifdef CONFIG_S2IO_NAPI
5836                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5837                         /* Queueing the vlan frame to the upper layer */
5838                         vlan_hwaccel_receive_skb(skb, sp->vlgrp,
5839                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
5840                 } else {
5841                         netif_receive_skb(skb);
5842                 }
5843 #else
5844                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5845                         /* Queueing the vlan frame to the upper layer */
5846                         vlan_hwaccel_rx(skb, sp->vlgrp,
5847                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
5848                 } else {
5849                         netif_rx(skb);
5850                 }
5851 #endif
5852         } else {
5853 send_up:
5854                 queue_rx_frame(skb);
5855         }
5856         dev->last_rx = jiffies;
5857 aggregate:
5858         atomic_dec(&sp->rx_bufs_left[ring_no]);
5859         return SUCCESS;
5860 }
5861
5862 /**
5863  *  s2io_link - stops/starts the Tx queue.
5864  *  @sp : private member of the device structure, which is a pointer to the
5865  *  s2io_nic structure.
5866  *  @link : inidicates whether link is UP/DOWN.
5867  *  Description:
5868  *  This function stops/starts the Tx queue depending on whether the link
5869  *  status of the NIC is is down or up. This is called by the Alarm
5870  *  interrupt handler whenever a link change interrupt comes up.
5871  *  Return value:
5872  *  void.
5873  */
5874
5875 static void s2io_link(nic_t * sp, int link)
5876 {
5877         struct net_device *dev = (struct net_device *) sp->dev;
5878
5879         if (link != sp->last_link_state) {
5880                 if (link == LINK_DOWN) {
5881                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
5882                         netif_carrier_off(dev);
5883                 } else {
5884                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
5885                         netif_carrier_on(dev);
5886                 }
5887         }
5888         sp->last_link_state = link;
5889 }
5890
5891 /**
5892  *  get_xena_rev_id - to identify revision ID of xena.
5893  *  @pdev : PCI Dev structure
5894  *  Description:
5895  *  Function to identify the Revision ID of xena.
5896  *  Return value:
5897  *  returns the revision ID of the device.
5898  */
5899
5900 static int get_xena_rev_id(struct pci_dev *pdev)
5901 {
5902         u8 id = 0;
5903         int ret;
5904         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
5905         return id;
5906 }
5907
5908 /**
5909  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5910  *  @sp : private member of the device structure, which is a pointer to the
5911  *  s2io_nic structure.
5912  *  Description:
5913  *  This function initializes a few of the PCI and PCI-X configuration registers
5914  *  with recommended values.
5915  *  Return value:
5916  *  void
5917  */
5918
5919 static void s2io_init_pci(nic_t * sp)
5920 {
5921         u16 pci_cmd = 0, pcix_cmd = 0;
5922
5923         /* Enable Data Parity Error Recovery in PCI-X command register. */
5924         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5925                              &(pcix_cmd));
5926         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5927                               (pcix_cmd | 1));
5928         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5929                              &(pcix_cmd));
5930
5931         /* Set the PErr Response bit in PCI command register. */
5932         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5933         pci_write_config_word(sp->pdev, PCI_COMMAND,
5934                               (pci_cmd | PCI_COMMAND_PARITY));
5935         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5936 }
5937
5938 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
5939 MODULE_LICENSE("GPL");
5940 MODULE_VERSION(DRV_VERSION);
5941
5942 module_param(tx_fifo_num, int, 0);
5943 module_param(rx_ring_num, int, 0);
5944 module_param(rx_ring_mode, int, 0);
5945 module_param_array(tx_fifo_len, uint, NULL, 0);
5946 module_param_array(rx_ring_sz, uint, NULL, 0);
5947 module_param_array(rts_frm_len, uint, NULL, 0);
5948 module_param(use_continuous_tx_intrs, int, 1);
5949 module_param(rmac_pause_time, int, 0);
5950 module_param(mc_pause_threshold_q0q3, int, 0);
5951 module_param(mc_pause_threshold_q4q7, int, 0);
5952 module_param(shared_splits, int, 0);
5953 module_param(tmac_util_period, int, 0);
5954 module_param(rmac_util_period, int, 0);
5955 module_param(bimodal, bool, 0);
5956 module_param(l3l4hdr_size, int , 0);
5957 #ifndef CONFIG_S2IO_NAPI
5958 module_param(indicate_max_pkts, int, 0);
5959 #endif
5960 module_param(rxsync_frequency, int, 0);
5961 module_param(intr_type, int, 0);
5962 module_param(lro, int, 0);
5963 module_param(lro_max_pkts, int, 0);
5964
5965 /**
5966  *  s2io_init_nic - Initialization of the adapter .
5967  *  @pdev : structure containing the PCI related information of the device.
5968  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
5969  *  Description:
5970  *  The function initializes an adapter identified by the pci_dec structure.
5971  *  All OS related initialization including memory and device structure and
5972  *  initlaization of the device private variable is done. Also the swapper
5973  *  control register is initialized to enable read and write into the I/O
5974  *  registers of the device.
5975  *  Return value:
5976  *  returns 0 on success and negative on failure.
5977  */
5978
5979 static int __devinit
5980 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
5981 {
5982         nic_t *sp;
5983         struct net_device *dev;
5984         int i, j, ret;
5985         int dma_flag = FALSE;
5986         u32 mac_up, mac_down;
5987         u64 val64 = 0, tmp64 = 0;
5988         XENA_dev_config_t __iomem *bar0 = NULL;
5989         u16 subid;
5990         mac_info_t *mac_control;
5991         struct config_param *config;
5992         int mode;
5993         u8 dev_intr_type = intr_type;
5994
5995 #ifdef CONFIG_S2IO_NAPI
5996         if (dev_intr_type != INTA) {
5997                 DBG_PRINT(ERR_DBG, "NAPI cannot be enabled when MSI/MSI-X \
5998 is enabled. Defaulting to INTA\n");
5999                 dev_intr_type = INTA;
6000         }
6001         else
6002                 DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
6003 #endif
6004
6005         if ((ret = pci_enable_device(pdev))) {
6006                 DBG_PRINT(ERR_DBG,
6007                           "s2io_init_nic: pci_enable_device failed\n");
6008                 return ret;
6009         }
6010
6011         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6012                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6013                 dma_flag = TRUE;
6014                 if (pci_set_consistent_dma_mask
6015                     (pdev, DMA_64BIT_MASK)) {
6016                         DBG_PRINT(ERR_DBG,
6017                                   "Unable to obtain 64bit DMA for \
6018                                         consistent allocations\n");
6019                         pci_disable_device(pdev);
6020                         return -ENOMEM;
6021                 }
6022         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6023                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6024         } else {
6025                 pci_disable_device(pdev);
6026                 return -ENOMEM;
6027         }
6028
6029         if ((dev_intr_type == MSI_X) &&
6030                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6031                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6032                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. \
6033 Defaulting to INTA\n");
6034                 dev_intr_type = INTA;
6035         }
6036         if (dev_intr_type != MSI_X) {
6037                 if (pci_request_regions(pdev, s2io_driver_name)) {
6038                         DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
6039                             pci_disable_device(pdev);
6040                         return -ENODEV;
6041                 }
6042         }
6043         else {
6044                 if (!(request_mem_region(pci_resource_start(pdev, 0),
6045                          pci_resource_len(pdev, 0), s2io_driver_name))) {
6046                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6047                         pci_disable_device(pdev);
6048                         return -ENODEV;
6049                 }
6050                 if (!(request_mem_region(pci_resource_start(pdev, 2),
6051                          pci_resource_len(pdev, 2), s2io_driver_name))) {
6052                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6053                         release_mem_region(pci_resource_start(pdev, 0),
6054                                    pci_resource_len(pdev, 0));
6055                         pci_disable_device(pdev);
6056                         return -ENODEV;
6057                 }
6058         }
6059
6060         dev = alloc_etherdev(sizeof(nic_t));
6061         if (dev == NULL) {
6062                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6063                 pci_disable_device(pdev);
6064                 pci_release_regions(pdev);
6065                 return -ENODEV;
6066         }
6067
6068         pci_set_master(pdev);
6069         pci_set_drvdata(pdev, dev);
6070         SET_MODULE_OWNER(dev);
6071         SET_NETDEV_DEV(dev, &pdev->dev);
6072
6073         /*  Private member variable initialized to s2io NIC structure */
6074         sp = dev->priv;
6075         memset(sp, 0, sizeof(nic_t));
6076         sp->dev = dev;
6077         sp->pdev = pdev;
6078         sp->high_dma_flag = dma_flag;
6079         sp->device_enabled_once = FALSE;
6080         if (rx_ring_mode == 1)
6081                 sp->rxd_mode = RXD_MODE_1;
6082         if (rx_ring_mode == 2)
6083                 sp->rxd_mode = RXD_MODE_3B;
6084         if (rx_ring_mode == 3)
6085                 sp->rxd_mode = RXD_MODE_3A;
6086
6087         sp->intr_type = dev_intr_type;
6088
6089         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6090                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6091                 sp->device_type = XFRAME_II_DEVICE;
6092         else
6093                 sp->device_type = XFRAME_I_DEVICE;
6094
6095         sp->lro = lro;
6096
6097         /* Initialize some PCI/PCI-X fields of the NIC. */
6098         s2io_init_pci(sp);
6099
6100         /*
6101          * Setting the device configuration parameters.
6102          * Most of these parameters can be specified by the user during
6103          * module insertion as they are module loadable parameters. If
6104          * these parameters are not not specified during load time, they
6105          * are initialized with default values.
6106          */
6107         mac_control = &sp->mac_control;
6108         config = &sp->config;
6109
6110         /* Tx side parameters. */
6111         if (tx_fifo_len[0] == 0)
6112                 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
6113         config->tx_fifo_num = tx_fifo_num;
6114         for (i = 0; i < MAX_TX_FIFOS; i++) {
6115                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6116                 config->tx_cfg[i].fifo_priority = i;
6117         }
6118
6119         /* mapping the QoS priority to the configured fifos */
6120         for (i = 0; i < MAX_TX_FIFOS; i++)
6121                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6122
6123         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6124         for (i = 0; i < config->tx_fifo_num; i++) {
6125                 config->tx_cfg[i].f_no_snoop =
6126                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6127                 if (config->tx_cfg[i].fifo_len < 65) {
6128                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6129                         break;
6130                 }
6131         }
6132         /* + 2 because one Txd for skb->data and one Txd for UFO */
6133         config->max_txds = MAX_SKB_FRAGS + 2;
6134
6135         /* Rx side parameters. */
6136         if (rx_ring_sz[0] == 0)
6137                 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
6138         config->rx_ring_num = rx_ring_num;
6139         for (i = 0; i < MAX_RX_RINGS; i++) {
6140                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
6141                     (rxd_count[sp->rxd_mode] + 1);
6142                 config->rx_cfg[i].ring_priority = i;
6143         }
6144
6145         for (i = 0; i < rx_ring_num; i++) {
6146                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6147                 config->rx_cfg[i].f_no_snoop =
6148                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6149         }
6150
6151         /*  Setting Mac Control parameters */
6152         mac_control->rmac_pause_time = rmac_pause_time;
6153         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6154         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6155
6156
6157         /* Initialize Ring buffer parameters. */
6158         for (i = 0; i < config->rx_ring_num; i++)
6159                 atomic_set(&sp->rx_bufs_left[i], 0);
6160
6161         /* Initialize the number of ISRs currently running */
6162         atomic_set(&sp->isr_cnt, 0);
6163
6164         /*  initialize the shared memory used by the NIC and the host */
6165         if (init_shared_mem(sp)) {
6166                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6167                           __FUNCTION__);
6168                 ret = -ENOMEM;
6169                 goto mem_alloc_failed;
6170         }
6171
6172         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6173                                      pci_resource_len(pdev, 0));
6174         if (!sp->bar0) {
6175                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6176                           dev->name);
6177                 ret = -ENOMEM;
6178                 goto bar0_remap_failed;
6179         }
6180
6181         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6182                                      pci_resource_len(pdev, 2));
6183         if (!sp->bar1) {
6184                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6185                           dev->name);
6186                 ret = -ENOMEM;
6187                 goto bar1_remap_failed;
6188         }
6189
6190         dev->irq = pdev->irq;
6191         dev->base_addr = (unsigned long) sp->bar0;
6192
6193         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6194         for (j = 0; j < MAX_TX_FIFOS; j++) {
6195                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6196                     (sp->bar1 + (j * 0x00020000));
6197         }
6198
6199         /*  Driver entry points */
6200         dev->open = &s2io_open;
6201         dev->stop = &s2io_close;
6202         dev->hard_start_xmit = &s2io_xmit;
6203         dev->get_stats = &s2io_get_stats;
6204         dev->set_multicast_list = &s2io_set_multicast;
6205         dev->do_ioctl = &s2io_ioctl;
6206         dev->change_mtu = &s2io_change_mtu;
6207         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6208         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6209         dev->vlan_rx_register = s2io_vlan_rx_register;
6210         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6211
6212         /*
6213          * will use eth_mac_addr() for  dev->set_mac_address
6214          * mac address will be set every time dev->open() is called
6215          */
6216 #if defined(CONFIG_S2IO_NAPI)
6217         dev->poll = s2io_poll;
6218         dev->weight = 32;
6219 #endif
6220
6221         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6222         if (sp->high_dma_flag == TRUE)
6223                 dev->features |= NETIF_F_HIGHDMA;
6224 #ifdef NETIF_F_TSO
6225         dev->features |= NETIF_F_TSO;
6226 #endif
6227         if (sp->device_type & XFRAME_II_DEVICE) {
6228                 dev->features |= NETIF_F_UFO;
6229                 dev->features |= NETIF_F_HW_CSUM;
6230         }
6231
6232         dev->tx_timeout = &s2io_tx_watchdog;
6233         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6234         INIT_WORK(&sp->rst_timer_task,
6235                   (void (*)(void *)) s2io_restart_nic, dev);
6236         INIT_WORK(&sp->set_link_task,
6237                   (void (*)(void *)) s2io_set_link, sp);
6238
6239         pci_save_state(sp->pdev);
6240
6241         /* Setting swapper control on the NIC, for proper reset operation */
6242         if (s2io_set_swapper(sp)) {
6243                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6244                           dev->name);
6245                 ret = -EAGAIN;
6246                 goto set_swap_failed;
6247         }
6248
6249         /* Verify if the Herc works on the slot its placed into */
6250         if (sp->device_type & XFRAME_II_DEVICE) {
6251                 mode = s2io_verify_pci_mode(sp);
6252                 if (mode < 0) {
6253                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6254                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6255                         ret = -EBADSLT;
6256                         goto set_swap_failed;
6257                 }
6258         }
6259
6260         /* Not needed for Herc */
6261         if (sp->device_type & XFRAME_I_DEVICE) {
6262                 /*
6263                  * Fix for all "FFs" MAC address problems observed on
6264                  * Alpha platforms
6265                  */
6266                 fix_mac_address(sp);
6267                 s2io_reset(sp);
6268         }
6269
6270         /*
6271          * MAC address initialization.
6272          * For now only one mac address will be read and used.
6273          */
6274         bar0 = sp->bar0;
6275         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
6276             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
6277         writeq(val64, &bar0->rmac_addr_cmd_mem);
6278         wait_for_cmd_complete(sp);
6279
6280         tmp64 = readq(&bar0->rmac_addr_data0_mem);
6281         mac_down = (u32) tmp64;
6282         mac_up = (u32) (tmp64 >> 32);
6283
6284         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
6285
6286         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
6287         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
6288         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
6289         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
6290         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
6291         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
6292
6293         /*  Set the factory defined MAC address initially   */
6294         dev->addr_len = ETH_ALEN;
6295         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
6296
6297         /*
6298          * Initialize the tasklet status and link state flags
6299          * and the card state parameter
6300          */
6301         atomic_set(&(sp->card_state), 0);
6302         sp->tasklet_status = 0;
6303         sp->link_state = 0;
6304
6305         /* Initialize spinlocks */
6306         spin_lock_init(&sp->tx_lock);
6307 #ifndef CONFIG_S2IO_NAPI
6308         spin_lock_init(&sp->put_lock);
6309 #endif
6310         spin_lock_init(&sp->rx_lock);
6311
6312         /*
6313          * SXE-002: Configure link and activity LED to init state
6314          * on driver load.
6315          */
6316         subid = sp->pdev->subsystem_device;
6317         if ((subid & 0xFF) >= 0x07) {
6318                 val64 = readq(&bar0->gpio_control);
6319                 val64 |= 0x0000800000000000ULL;
6320                 writeq(val64, &bar0->gpio_control);
6321                 val64 = 0x0411040400000000ULL;
6322                 writeq(val64, (void __iomem *) bar0 + 0x2700);
6323                 val64 = readq(&bar0->gpio_control);
6324         }
6325
6326         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
6327
6328         if (register_netdev(dev)) {
6329                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
6330                 ret = -ENODEV;
6331                 goto register_failed;
6332         }
6333
6334         if (sp->device_type & XFRAME_II_DEVICE) {
6335                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
6336                           dev->name);
6337                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6338                                 get_xena_rev_id(sp->pdev),
6339                                 s2io_driver_version);
6340                 switch(sp->intr_type) {
6341                         case INTA:
6342                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6343                                 break;
6344                         case MSI:
6345                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6346                                 break;
6347                         case MSI_X:
6348                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6349                                 break;
6350                 }
6351
6352                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6353                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6354                           sp->def_mac_addr[0].mac_addr[0],
6355                           sp->def_mac_addr[0].mac_addr[1],
6356                           sp->def_mac_addr[0].mac_addr[2],
6357                           sp->def_mac_addr[0].mac_addr[3],
6358                           sp->def_mac_addr[0].mac_addr[4],
6359                           sp->def_mac_addr[0].mac_addr[5]);
6360                 mode = s2io_print_pci_mode(sp);
6361                 if (mode < 0) {
6362                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
6363                         ret = -EBADSLT;
6364                         goto set_swap_failed;
6365                 }
6366         } else {
6367                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
6368                           dev->name);
6369                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6370                                         get_xena_rev_id(sp->pdev),
6371                                         s2io_driver_version);
6372                 switch(sp->intr_type) {
6373                         case INTA:
6374                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6375                                 break;
6376                         case MSI:
6377                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6378                                 break;
6379                         case MSI_X:
6380                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6381                                 break;
6382                 }
6383                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6384                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6385                           sp->def_mac_addr[0].mac_addr[0],
6386                           sp->def_mac_addr[0].mac_addr[1],
6387                           sp->def_mac_addr[0].mac_addr[2],
6388                           sp->def_mac_addr[0].mac_addr[3],
6389                           sp->def_mac_addr[0].mac_addr[4],
6390                           sp->def_mac_addr[0].mac_addr[5]);
6391         }
6392         if (sp->rxd_mode == RXD_MODE_3B)
6393                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer mode support has been "
6394                           "enabled\n",dev->name);
6395         if (sp->rxd_mode == RXD_MODE_3A)
6396                 DBG_PRINT(ERR_DBG, "%s: 3-Buffer mode support has been "
6397                           "enabled\n",dev->name);
6398
6399         if (sp->lro)
6400                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
6401                         dev->name);
6402
6403         /* Initialize device name */
6404         strcpy(sp->name, dev->name);
6405         if (sp->device_type & XFRAME_II_DEVICE)
6406                 strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
6407         else
6408                 strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
6409
6410         /* Initialize bimodal Interrupts */
6411         sp->config.bimodal = bimodal;
6412         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
6413                 sp->config.bimodal = 0;
6414                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
6415                         dev->name);
6416         }
6417
6418         /*
6419          * Make Link state as off at this point, when the Link change
6420          * interrupt comes the state will be automatically changed to
6421          * the right state.
6422          */
6423         netif_carrier_off(dev);
6424
6425         return 0;
6426
6427       register_failed:
6428       set_swap_failed:
6429         iounmap(sp->bar1);
6430       bar1_remap_failed:
6431         iounmap(sp->bar0);
6432       bar0_remap_failed:
6433       mem_alloc_failed:
6434         free_shared_mem(sp);
6435         pci_disable_device(pdev);
6436         if (dev_intr_type != MSI_X)
6437                 pci_release_regions(pdev);
6438         else {
6439                 release_mem_region(pci_resource_start(pdev, 0),
6440                         pci_resource_len(pdev, 0));
6441                 release_mem_region(pci_resource_start(pdev, 2),
6442                         pci_resource_len(pdev, 2));
6443         }
6444         pci_set_drvdata(pdev, NULL);
6445         free_netdev(dev);
6446
6447         return ret;
6448 }
6449
6450 /**
6451  * s2io_rem_nic - Free the PCI device
6452  * @pdev: structure containing the PCI related information of the device.
6453  * Description: This function is called by the Pci subsystem to release a
6454  * PCI device and free up all resource held up by the device. This could
6455  * be in response to a Hot plug event or when the driver is to be removed
6456  * from memory.
6457  */
6458
6459 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
6460 {
6461         struct net_device *dev =
6462             (struct net_device *) pci_get_drvdata(pdev);
6463         nic_t *sp;
6464
6465         if (dev == NULL) {
6466                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
6467                 return;
6468         }
6469
6470         sp = dev->priv;
6471         unregister_netdev(dev);
6472
6473         free_shared_mem(sp);
6474         iounmap(sp->bar0);
6475         iounmap(sp->bar1);
6476         pci_disable_device(pdev);
6477         if (sp->intr_type != MSI_X)
6478                 pci_release_regions(pdev);
6479         else {
6480                 release_mem_region(pci_resource_start(pdev, 0),
6481                         pci_resource_len(pdev, 0));
6482                 release_mem_region(pci_resource_start(pdev, 2),
6483                         pci_resource_len(pdev, 2));
6484         }
6485         pci_set_drvdata(pdev, NULL);
6486         free_netdev(dev);
6487 }
6488
6489 /**
6490  * s2io_starter - Entry point for the driver
6491  * Description: This function is the entry point for the driver. It verifies
6492  * the module loadable parameters and initializes PCI configuration space.
6493  */
6494
6495 int __init s2io_starter(void)
6496 {
6497         return pci_module_init(&s2io_driver);
6498 }
6499
6500 /**
6501  * s2io_closer - Cleanup routine for the driver
6502  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
6503  */
6504
6505 static void s2io_closer(void)
6506 {
6507         pci_unregister_driver(&s2io_driver);
6508         DBG_PRINT(INIT_DBG, "cleanup done\n");
6509 }
6510
6511 module_init(s2io_starter);
6512 module_exit(s2io_closer);
6513
6514 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
6515                 struct tcphdr **tcp, RxD_t *rxdp)
6516 {
6517         int ip_off;
6518         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
6519
6520         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
6521                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
6522                           __FUNCTION__);
6523                 return -1;
6524         }
6525
6526         /* TODO:
6527          * By default the VLAN field in the MAC is stripped by the card, if this
6528          * feature is turned off in rx_pa_cfg register, then the ip_off field
6529          * has to be shifted by a further 2 bytes
6530          */
6531         switch (l2_type) {
6532                 case 0: /* DIX type */
6533                 case 4: /* DIX type with VLAN */
6534                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
6535                         break;
6536                 /* LLC, SNAP etc are considered non-mergeable */
6537                 default:
6538                         return -1;
6539         }
6540
6541         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
6542         ip_len = (u8)((*ip)->ihl);
6543         ip_len <<= 2;
6544         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
6545
6546         return 0;
6547 }
6548
6549 static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
6550                                   struct tcphdr *tcp)
6551 {
6552         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6553         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
6554            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
6555                 return -1;
6556         return 0;
6557 }
6558
6559 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
6560 {
6561         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
6562 }
6563
6564 static void initiate_new_session(lro_t *lro, u8 *l2h,
6565                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
6566 {
6567         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6568         lro->l2h = l2h;
6569         lro->iph = ip;
6570         lro->tcph = tcp;
6571         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
6572         lro->tcp_ack = ntohl(tcp->ack_seq);
6573         lro->sg_num = 1;
6574         lro->total_len = ntohs(ip->tot_len);
6575         lro->frags_len = 0;
6576         /*
6577          * check if we saw TCP timestamp. Other consistency checks have
6578          * already been done.
6579          */
6580         if (tcp->doff == 8) {
6581                 u32 *ptr;
6582                 ptr = (u32 *)(tcp+1);
6583                 lro->saw_ts = 1;
6584                 lro->cur_tsval = *(ptr+1);
6585                 lro->cur_tsecr = *(ptr+2);
6586         }
6587         lro->in_use = 1;
6588 }
6589
6590 static void update_L3L4_header(nic_t *sp, lro_t *lro)
6591 {
6592         struct iphdr *ip = lro->iph;
6593         struct tcphdr *tcp = lro->tcph;
6594         u16 nchk;
6595         StatInfo_t *statinfo = sp->mac_control.stats_info;
6596         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6597
6598         /* Update L3 header */
6599         ip->tot_len = htons(lro->total_len);
6600         ip->check = 0;
6601         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
6602         ip->check = nchk;
6603
6604         /* Update L4 header */
6605         tcp->ack_seq = lro->tcp_ack;
6606         tcp->window = lro->window;
6607
6608         /* Update tsecr field if this session has timestamps enabled */
6609         if (lro->saw_ts) {
6610                 u32 *ptr = (u32 *)(tcp + 1);
6611                 *(ptr+2) = lro->cur_tsecr;
6612         }
6613
6614         /* Update counters required for calculation of
6615          * average no. of packets aggregated.
6616          */
6617         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
6618         statinfo->sw_stat.num_aggregations++;
6619 }
6620
6621 static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
6622                 struct tcphdr *tcp, u32 l4_pyld)
6623 {
6624         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6625         lro->total_len += l4_pyld;
6626         lro->frags_len += l4_pyld;
6627         lro->tcp_next_seq += l4_pyld;
6628         lro->sg_num++;
6629
6630         /* Update ack seq no. and window ad(from this pkt) in LRO object */
6631         lro->tcp_ack = tcp->ack_seq;
6632         lro->window = tcp->window;
6633
6634         if (lro->saw_ts) {
6635                 u32 *ptr;
6636                 /* Update tsecr and tsval from this packet */
6637                 ptr = (u32 *) (tcp + 1);
6638                 lro->cur_tsval = *(ptr + 1);
6639                 lro->cur_tsecr = *(ptr + 2);
6640         }
6641 }
6642
6643 static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
6644                                     struct tcphdr *tcp, u32 tcp_pyld_len)
6645 {
6646         u8 *ptr;
6647
6648         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
6649
6650         if (!tcp_pyld_len) {
6651                 /* Runt frame or a pure ack */
6652                 return -1;
6653         }
6654
6655         if (ip->ihl != 5) /* IP has options */
6656                 return -1;
6657
6658         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
6659                                                                 !tcp->ack) {
6660                 /*
6661                  * Currently recognize only the ack control word and
6662                  * any other control field being set would result in
6663                  * flushing the LRO session
6664                  */
6665                 return -1;
6666         }
6667
6668         /*
6669          * Allow only one TCP timestamp option. Don't aggregate if
6670          * any other options are detected.
6671          */
6672         if (tcp->doff != 5 && tcp->doff != 8)
6673                 return -1;
6674
6675         if (tcp->doff == 8) {
6676                 ptr = (u8 *)(tcp + 1);
6677                 while (*ptr == TCPOPT_NOP)
6678                         ptr++;
6679                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
6680                         return -1;
6681
6682                 /* Ensure timestamp value increases monotonically */
6683                 if (l_lro)
6684                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
6685                                 return -1;
6686
6687                 /* timestamp echo reply should be non-zero */
6688                 if (*((u32 *)(ptr+6)) == 0)
6689                         return -1;
6690         }
6691
6692         return 0;
6693 }
6694
6695 static int
6696 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
6697                       RxD_t *rxdp, nic_t *sp)
6698 {
6699         struct iphdr *ip;
6700         struct tcphdr *tcph;
6701         int ret = 0, i;
6702
6703         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
6704                                          rxdp))) {
6705                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
6706                           ip->saddr, ip->daddr);
6707         } else {
6708                 return ret;
6709         }
6710
6711         tcph = (struct tcphdr *)*tcp;
6712         *tcp_len = get_l4_pyld_length(ip, tcph);
6713         for (i=0; i<MAX_LRO_SESSIONS; i++) {
6714                 lro_t *l_lro = &sp->lro0_n[i];
6715                 if (l_lro->in_use) {
6716                         if (check_for_socket_match(l_lro, ip, tcph))
6717                                 continue;
6718                         /* Sock pair matched */
6719                         *lro = l_lro;
6720
6721                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
6722                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
6723                                           "0x%x, actual 0x%x\n", __FUNCTION__,
6724                                           (*lro)->tcp_next_seq,
6725                                           ntohl(tcph->seq));
6726
6727                                 sp->mac_control.stats_info->
6728                                    sw_stat.outof_sequence_pkts++;
6729                                 ret = 2;
6730                                 break;
6731                         }
6732
6733                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
6734                                 ret = 1; /* Aggregate */
6735                         else
6736                                 ret = 2; /* Flush both */
6737                         break;
6738                 }
6739         }
6740
6741         if (ret == 0) {
6742                 /* Before searching for available LRO objects,
6743                  * check if the pkt is L3/L4 aggregatable. If not
6744                  * don't create new LRO session. Just send this
6745                  * packet up.
6746                  */
6747                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
6748                         return 5;
6749                 }
6750
6751                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
6752                         lro_t *l_lro = &sp->lro0_n[i];
6753                         if (!(l_lro->in_use)) {
6754                                 *lro = l_lro;
6755                                 ret = 3; /* Begin anew */
6756                                 break;
6757                         }
6758                 }
6759         }
6760
6761         if (ret == 0) { /* sessions exceeded */
6762                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
6763                           __FUNCTION__);
6764                 *lro = NULL;
6765                 return ret;
6766         }
6767
6768         switch (ret) {
6769                 case 3:
6770                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
6771                         break;
6772                 case 2:
6773                         update_L3L4_header(sp, *lro);
6774                         break;
6775                 case 1:
6776                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
6777                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
6778                                 update_L3L4_header(sp, *lro);
6779                                 ret = 4; /* Flush the LRO */
6780                         }
6781                         break;
6782                 default:
6783                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
6784                                 __FUNCTION__);
6785                         break;
6786         }
6787
6788         return ret;
6789 }
6790
6791 static void clear_lro_session(lro_t *lro)
6792 {
6793         static u16 lro_struct_size = sizeof(lro_t);
6794
6795         memset(lro, 0, lro_struct_size);
6796 }
6797
6798 static void queue_rx_frame(struct sk_buff *skb)
6799 {
6800         struct net_device *dev = skb->dev;
6801
6802         skb->protocol = eth_type_trans(skb, dev);
6803 #ifdef CONFIG_S2IO_NAPI
6804         netif_receive_skb(skb);
6805 #else
6806         netif_rx(skb);
6807 #endif
6808 }
6809
6810 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
6811                            u32 tcp_len)
6812 {
6813         struct sk_buff *tmp, *first = lro->parent;
6814
6815         first->len += tcp_len;
6816         first->data_len = lro->frags_len;
6817         skb_pull(skb, (skb->len - tcp_len));
6818         if ((tmp = skb_shinfo(first)->frag_list)) {
6819                 while (tmp->next)
6820                         tmp = tmp->next;
6821                 tmp->next = skb;
6822         }
6823         else
6824                 skb_shinfo(first)->frag_list = skb;
6825         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
6826         return;
6827 }