2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
28 #include <asm/system.h>
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
37 #define assert(expr) \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__func__,__LINE__); \
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
55 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
57 static const int multicast_filter_limit = 32;
59 /* MAC address length */
60 #define MAC_ADDR_LEN 6
62 #define MAX_READ_REQUEST_SHIFT 12
63 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
67 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70 #define R8169_REGS_SIZE 256
71 #define R8169_NAPI_WEIGHT 64
72 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
78 #define RTL8169_TX_TIMEOUT (6*HZ)
79 #define RTL8169_PHY_TIMEOUT (10*HZ)
81 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
83 #define RTL_EEPROM_SIG_ADDR 0x0000
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
94 RTL_GIGA_MAC_NONE = 0x00,
95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131 } rtl_chip_info[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
168 static void rtl_hw_start_8169(struct net_device *);
169 static void rtl_hw_start_8168(struct net_device *);
170 static void rtl_hw_start_8101(struct net_device *);
172 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
188 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
190 static int rx_copybreak = 200;
191 static int use_dac = -1;
197 MAC0 = 0, /* Ethernet hardware address. */
199 MAR0 = 8, /* Multicast filter. */
200 CounterAddrLow = 0x10,
201 CounterAddrHigh = 0x14,
202 TxDescStartAddrLow = 0x20,
203 TxDescStartAddrHigh = 0x24,
204 TxHDescStartAddrLow = 0x28,
205 TxHDescStartAddrHigh = 0x2c,
228 RxDescAddrLow = 0xe4,
229 RxDescAddrHigh = 0xe8,
232 FuncEventMask = 0xf4,
233 FuncPresetState = 0xf8,
234 FuncForceEvent = 0xfc,
237 enum rtl8110_registers {
243 enum rtl8168_8101_registers {
246 #define CSIAR_FLAG 0x80000000
247 #define CSIAR_WRITE_CMD 0x80000000
248 #define CSIAR_BYTE_ENABLE 0x0f
249 #define CSIAR_BYTE_ENABLE_SHIFT 12
250 #define CSIAR_ADDR_MASK 0x0fff
253 #define EPHYAR_FLAG 0x80000000
254 #define EPHYAR_WRITE_CMD 0x80000000
255 #define EPHYAR_REG_MASK 0x1f
256 #define EPHYAR_REG_SHIFT 16
257 #define EPHYAR_DATA_MASK 0xffff
259 #define FIX_NAK_1 (1 << 4)
260 #define FIX_NAK_2 (1 << 3)
262 #define EFUSEAR_FLAG 0x80000000
263 #define EFUSEAR_WRITE_CMD 0x80000000
264 #define EFUSEAR_READ_CMD 0x00000000
265 #define EFUSEAR_REG_MASK 0x03ff
266 #define EFUSEAR_REG_SHIFT 8
267 #define EFUSEAR_DATA_MASK 0xff
270 enum rtl_register_content {
271 /* InterruptStatusBits */
275 TxDescUnavail = 0x0080,
297 /* TXPoll register p.5 */
298 HPQ = 0x80, /* Poll cmd on the high prio queue */
299 NPQ = 0x40, /* Poll cmd on the low prio queue */
300 FSWInt = 0x01, /* Forced software interrupt */
304 Cfg9346_Unlock = 0xc0,
309 AcceptBroadcast = 0x08,
310 AcceptMulticast = 0x04,
312 AcceptAllPhys = 0x01,
319 TxInterFrameGapShift = 24,
320 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
322 /* Config1 register p.24 */
325 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
326 Speed_down = (1 << 4),
330 PMEnable = (1 << 0), /* Power Management Enable */
332 /* Config2 register p. 25 */
333 PCI_Clock_66MHz = 0x01,
334 PCI_Clock_33MHz = 0x00,
336 /* Config3 register p.25 */
337 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
338 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
339 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
341 /* Config5 register p.27 */
342 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF = (1 << 5), /* Accept Multicast wakeup frame */
344 UWF = (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake = (1 << 1), /* LanWake enable/disable */
346 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
349 TBIReset = 0x80000000,
350 TBILoopback = 0x40000000,
351 TBINwEnable = 0x20000000,
352 TBINwRestart = 0x10000000,
353 TBILinkOk = 0x02000000,
354 TBINwComplete = 0x01000000,
357 EnableBist = (1 << 15), // 8168 8101
358 Mac_dbgo_oe = (1 << 14), // 8168 8101
359 Normal_mode = (1 << 13), // unused
360 Force_half_dup = (1 << 12), // 8168 8101
361 Force_rxflow_en = (1 << 11), // 8168 8101
362 Force_txflow_en = (1 << 10), // 8168 8101
363 Cxpl_dbg_sel = (1 << 9), // 8168 8101
364 ASF = (1 << 8), // 8168 8101
365 PktCntrDisable = (1 << 7), // 8168 8101
366 Mac_dbgo_sel = 0x001c, // 8168
371 INTT_0 = 0x0000, // 8168
372 INTT_1 = 0x0001, // 8168
373 INTT_2 = 0x0002, // 8168
374 INTT_3 = 0x0003, // 8168
376 /* rtl8169_PHYstatus */
387 TBILinkOK = 0x02000000,
389 /* DumpCounterCommand */
393 enum desc_status_bit {
394 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
395 RingEnd = (1 << 30), /* End of descriptor ring */
396 FirstFrag = (1 << 29), /* First segment of a packet */
397 LastFrag = (1 << 28), /* Final segment of a packet */
400 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
401 MSSShift = 16, /* MSS value position */
402 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
403 IPCS = (1 << 18), /* Calculate IP checksum */
404 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
405 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
406 TxVlanTag = (1 << 17), /* Add VLAN tag */
409 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
410 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
412 #define RxProtoUDP (PID1)
413 #define RxProtoTCP (PID0)
414 #define RxProtoIP (PID1 | PID0)
415 #define RxProtoMask RxProtoIP
417 IPFail = (1 << 16), /* IP checksum failed */
418 UDPFail = (1 << 15), /* UDP/IP checksum failed */
419 TCPFail = (1 << 14), /* TCP/IP checksum failed */
420 RxVlanTag = (1 << 16), /* VLAN tag available */
423 #define RsvdMask 0x3fffc000
440 u8 __pad[sizeof(void *) - sizeof(u32)];
444 RTL_FEATURE_WOL = (1 << 0),
445 RTL_FEATURE_MSI = (1 << 1),
446 RTL_FEATURE_GMII = (1 << 2),
449 struct rtl8169_counters {
456 __le32 tx_one_collision;
457 __le32 tx_multi_collision;
465 struct rtl8169_private {
466 void __iomem *mmio_addr; /* memory map physical address */
467 struct pci_dev *pci_dev; /* Index of PCI device */
468 struct net_device *dev;
469 struct napi_struct napi;
470 spinlock_t lock; /* spin lock flag */
474 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
475 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
478 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
479 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
480 dma_addr_t TxPhyAddr;
481 dma_addr_t RxPhyAddr;
482 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
483 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
486 struct timer_list timer;
491 int phy_1000_ctrl_reg;
492 #ifdef CONFIG_R8169_VLAN
493 struct vlan_group *vlgrp;
495 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
496 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
497 void (*phy_reset_enable)(void __iomem *);
498 void (*hw_start)(struct net_device *);
499 unsigned int (*phy_reset_pending)(void __iomem *);
500 unsigned int (*link_ok)(void __iomem *);
501 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
503 struct delayed_work task;
506 struct mii_if_info mii;
507 struct rtl8169_counters counters;
511 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
512 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
513 module_param(rx_copybreak, int, 0);
514 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
515 module_param(use_dac, int, 0);
516 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. -1 defaults on for PCI Express only."
517 " Unsafe on 32 bit PCI slot.");
518 module_param_named(debug, debug.msg_enable, int, 0);
519 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
520 MODULE_LICENSE("GPL");
521 MODULE_VERSION(RTL8169_VERSION);
523 static int rtl8169_open(struct net_device *dev);
524 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
525 struct net_device *dev);
526 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
527 static int rtl8169_init_ring(struct net_device *dev);
528 static void rtl_hw_start(struct net_device *dev);
529 static int rtl8169_close(struct net_device *dev);
530 static void rtl_set_rx_mode(struct net_device *dev);
531 static void rtl8169_tx_timeout(struct net_device *dev);
532 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
533 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
534 void __iomem *, u32 budget);
535 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
536 static void rtl8169_down(struct net_device *dev);
537 static void rtl8169_rx_clear(struct rtl8169_private *tp);
538 static int rtl8169_poll(struct napi_struct *napi, int budget);
540 static const unsigned int rtl8169_rx_config =
541 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
543 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
547 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
549 for (i = 20; i > 0; i--) {
551 * Check if the RTL8169 has completed writing to the specified
554 if (!(RTL_R32(PHYAR) & 0x80000000))
560 static int mdio_read(void __iomem *ioaddr, int reg_addr)
564 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
566 for (i = 20; i > 0; i--) {
568 * Check if the RTL8169 has completed retrieving data from
569 * the specified MII register.
571 if (RTL_R32(PHYAR) & 0x80000000) {
572 value = RTL_R32(PHYAR) & 0xffff;
580 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
582 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
585 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
589 val = mdio_read(ioaddr, reg_addr);
590 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
593 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
596 struct rtl8169_private *tp = netdev_priv(dev);
597 void __iomem *ioaddr = tp->mmio_addr;
599 mdio_write(ioaddr, location, val);
602 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
604 struct rtl8169_private *tp = netdev_priv(dev);
605 void __iomem *ioaddr = tp->mmio_addr;
607 return mdio_read(ioaddr, location);
610 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
614 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
615 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
617 for (i = 0; i < 100; i++) {
618 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
624 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
629 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
631 for (i = 0; i < 100; i++) {
632 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
633 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
642 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
646 RTL_W32(CSIDR, value);
647 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
648 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
650 for (i = 0; i < 100; i++) {
651 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
657 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
662 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
663 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
665 for (i = 0; i < 100; i++) {
666 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
667 value = RTL_R32(CSIDR);
676 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
681 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
683 for (i = 0; i < 300; i++) {
684 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
685 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
694 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
696 RTL_W16(IntrMask, 0x0000);
698 RTL_W16(IntrStatus, 0xffff);
701 static void rtl8169_asic_down(void __iomem *ioaddr)
703 RTL_W8(ChipCmd, 0x00);
704 rtl8169_irq_mask_and_ack(ioaddr);
708 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
710 return RTL_R32(TBICSR) & TBIReset;
713 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
715 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
718 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
720 return RTL_R32(TBICSR) & TBILinkOk;
723 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
725 return RTL_R8(PHYstatus) & LinkStatus;
728 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
730 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
733 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
737 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
738 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
741 static void rtl8169_check_link_status(struct net_device *dev,
742 struct rtl8169_private *tp,
743 void __iomem *ioaddr)
747 spin_lock_irqsave(&tp->lock, flags);
748 if (tp->link_ok(ioaddr)) {
749 /* This is to cancel a scheduled suspend if there's one. */
750 pm_request_resume(&tp->pci_dev->dev);
751 netif_carrier_on(dev);
752 netif_info(tp, ifup, dev, "link up\n");
754 netif_carrier_off(dev);
755 netif_info(tp, ifdown, dev, "link down\n");
756 pm_schedule_suspend(&tp->pci_dev->dev, 100);
758 spin_unlock_irqrestore(&tp->lock, flags);
761 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
763 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
765 void __iomem *ioaddr = tp->mmio_addr;
769 options = RTL_R8(Config1);
770 if (!(options & PMEnable))
773 options = RTL_R8(Config3);
774 if (options & LinkUp)
776 if (options & MagicPacket)
777 wolopts |= WAKE_MAGIC;
779 options = RTL_R8(Config5);
781 wolopts |= WAKE_UCAST;
783 wolopts |= WAKE_BCAST;
785 wolopts |= WAKE_MCAST;
790 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
792 struct rtl8169_private *tp = netdev_priv(dev);
794 spin_lock_irq(&tp->lock);
796 wol->supported = WAKE_ANY;
797 wol->wolopts = __rtl8169_get_wol(tp);
799 spin_unlock_irq(&tp->lock);
802 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
804 void __iomem *ioaddr = tp->mmio_addr;
806 static const struct {
811 { WAKE_ANY, Config1, PMEnable },
812 { WAKE_PHY, Config3, LinkUp },
813 { WAKE_MAGIC, Config3, MagicPacket },
814 { WAKE_UCAST, Config5, UWF },
815 { WAKE_BCAST, Config5, BWF },
816 { WAKE_MCAST, Config5, MWF },
817 { WAKE_ANY, Config5, LanWake }
820 RTL_W8(Cfg9346, Cfg9346_Unlock);
822 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
823 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
824 if (wolopts & cfg[i].opt)
825 options |= cfg[i].mask;
826 RTL_W8(cfg[i].reg, options);
829 RTL_W8(Cfg9346, Cfg9346_Lock);
832 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
834 struct rtl8169_private *tp = netdev_priv(dev);
836 spin_lock_irq(&tp->lock);
839 tp->features |= RTL_FEATURE_WOL;
841 tp->features &= ~RTL_FEATURE_WOL;
842 __rtl8169_set_wol(tp, wol->wolopts);
843 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
845 spin_unlock_irq(&tp->lock);
850 static void rtl8169_get_drvinfo(struct net_device *dev,
851 struct ethtool_drvinfo *info)
853 struct rtl8169_private *tp = netdev_priv(dev);
855 strcpy(info->driver, MODULENAME);
856 strcpy(info->version, RTL8169_VERSION);
857 strcpy(info->bus_info, pci_name(tp->pci_dev));
860 static int rtl8169_get_regs_len(struct net_device *dev)
862 return R8169_REGS_SIZE;
865 static int rtl8169_set_speed_tbi(struct net_device *dev,
866 u8 autoneg, u16 speed, u8 duplex)
868 struct rtl8169_private *tp = netdev_priv(dev);
869 void __iomem *ioaddr = tp->mmio_addr;
873 reg = RTL_R32(TBICSR);
874 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
875 (duplex == DUPLEX_FULL)) {
876 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
877 } else if (autoneg == AUTONEG_ENABLE)
878 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
880 netif_warn(tp, link, dev,
881 "incorrect speed setting refused in TBI mode\n");
888 static int rtl8169_set_speed_xmii(struct net_device *dev,
889 u8 autoneg, u16 speed, u8 duplex)
891 struct rtl8169_private *tp = netdev_priv(dev);
892 void __iomem *ioaddr = tp->mmio_addr;
895 if (autoneg == AUTONEG_ENABLE) {
898 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
899 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
900 ADVERTISE_100HALF | ADVERTISE_100FULL);
901 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
903 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
904 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
906 /* The 8100e/8101e/8102e do Fast Ethernet only. */
907 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
908 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
909 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
910 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
911 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
912 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
913 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
914 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
915 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
917 netif_info(tp, link, dev,
918 "PHY does not support 1000Mbps\n");
921 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
923 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
924 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
925 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
928 * Vendor specific (0x1f) and reserved (0x0e) MII
931 mdio_write(ioaddr, 0x1f, 0x0000);
932 mdio_write(ioaddr, 0x0e, 0x0000);
935 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
936 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
940 if (speed == SPEED_10)
942 else if (speed == SPEED_100)
943 bmcr = BMCR_SPEED100;
947 if (duplex == DUPLEX_FULL)
948 bmcr |= BMCR_FULLDPLX;
950 mdio_write(ioaddr, 0x1f, 0x0000);
953 tp->phy_1000_ctrl_reg = giga_ctrl;
955 mdio_write(ioaddr, MII_BMCR, bmcr);
957 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
958 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
959 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
960 mdio_write(ioaddr, 0x17, 0x2138);
961 mdio_write(ioaddr, 0x0e, 0x0260);
963 mdio_write(ioaddr, 0x17, 0x2108);
964 mdio_write(ioaddr, 0x0e, 0x0000);
971 static int rtl8169_set_speed(struct net_device *dev,
972 u8 autoneg, u16 speed, u8 duplex)
974 struct rtl8169_private *tp = netdev_priv(dev);
977 ret = tp->set_speed(dev, autoneg, speed, duplex);
979 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
980 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
985 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
987 struct rtl8169_private *tp = netdev_priv(dev);
991 spin_lock_irqsave(&tp->lock, flags);
992 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
993 spin_unlock_irqrestore(&tp->lock, flags);
998 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1000 struct rtl8169_private *tp = netdev_priv(dev);
1002 return tp->cp_cmd & RxChkSum;
1005 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1007 struct rtl8169_private *tp = netdev_priv(dev);
1008 void __iomem *ioaddr = tp->mmio_addr;
1009 unsigned long flags;
1011 spin_lock_irqsave(&tp->lock, flags);
1014 tp->cp_cmd |= RxChkSum;
1016 tp->cp_cmd &= ~RxChkSum;
1018 RTL_W16(CPlusCmd, tp->cp_cmd);
1021 spin_unlock_irqrestore(&tp->lock, flags);
1026 #ifdef CONFIG_R8169_VLAN
1028 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1029 struct sk_buff *skb)
1031 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1032 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1035 static void rtl8169_vlan_rx_register(struct net_device *dev,
1036 struct vlan_group *grp)
1038 struct rtl8169_private *tp = netdev_priv(dev);
1039 void __iomem *ioaddr = tp->mmio_addr;
1040 unsigned long flags;
1042 spin_lock_irqsave(&tp->lock, flags);
1045 * Do not disable RxVlan on 8110SCd.
1047 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1048 tp->cp_cmd |= RxVlan;
1050 tp->cp_cmd &= ~RxVlan;
1051 RTL_W16(CPlusCmd, tp->cp_cmd);
1053 spin_unlock_irqrestore(&tp->lock, flags);
1056 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1057 struct sk_buff *skb)
1059 u32 opts2 = le32_to_cpu(desc->opts2);
1060 struct vlan_group *vlgrp = tp->vlgrp;
1063 if (vlgrp && (opts2 & RxVlanTag)) {
1064 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1072 #else /* !CONFIG_R8169_VLAN */
1074 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1075 struct sk_buff *skb)
1080 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1081 struct sk_buff *skb)
1088 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1090 struct rtl8169_private *tp = netdev_priv(dev);
1091 void __iomem *ioaddr = tp->mmio_addr;
1095 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1096 cmd->port = PORT_FIBRE;
1097 cmd->transceiver = XCVR_INTERNAL;
1099 status = RTL_R32(TBICSR);
1100 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1101 cmd->autoneg = !!(status & TBINwEnable);
1103 cmd->speed = SPEED_1000;
1104 cmd->duplex = DUPLEX_FULL; /* Always set */
1109 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1111 struct rtl8169_private *tp = netdev_priv(dev);
1113 return mii_ethtool_gset(&tp->mii, cmd);
1116 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1118 struct rtl8169_private *tp = netdev_priv(dev);
1119 unsigned long flags;
1122 spin_lock_irqsave(&tp->lock, flags);
1124 rc = tp->get_settings(dev, cmd);
1126 spin_unlock_irqrestore(&tp->lock, flags);
1130 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1133 struct rtl8169_private *tp = netdev_priv(dev);
1134 unsigned long flags;
1136 if (regs->len > R8169_REGS_SIZE)
1137 regs->len = R8169_REGS_SIZE;
1139 spin_lock_irqsave(&tp->lock, flags);
1140 memcpy_fromio(p, tp->mmio_addr, regs->len);
1141 spin_unlock_irqrestore(&tp->lock, flags);
1144 static u32 rtl8169_get_msglevel(struct net_device *dev)
1146 struct rtl8169_private *tp = netdev_priv(dev);
1148 return tp->msg_enable;
1151 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1153 struct rtl8169_private *tp = netdev_priv(dev);
1155 tp->msg_enable = value;
1158 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1165 "tx_single_collisions",
1166 "tx_multi_collisions",
1174 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1178 return ARRAY_SIZE(rtl8169_gstrings);
1184 static void rtl8169_update_counters(struct net_device *dev)
1186 struct rtl8169_private *tp = netdev_priv(dev);
1187 void __iomem *ioaddr = tp->mmio_addr;
1188 struct rtl8169_counters *counters;
1194 * Some chips are unable to dump tally counters when the receiver
1197 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1200 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1204 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1205 cmd = (u64)paddr & DMA_BIT_MASK(32);
1206 RTL_W32(CounterAddrLow, cmd);
1207 RTL_W32(CounterAddrLow, cmd | CounterDump);
1210 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1211 /* copy updated counters */
1212 memcpy(&tp->counters, counters, sizeof(*counters));
1218 RTL_W32(CounterAddrLow, 0);
1219 RTL_W32(CounterAddrHigh, 0);
1221 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1224 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1225 struct ethtool_stats *stats, u64 *data)
1227 struct rtl8169_private *tp = netdev_priv(dev);
1231 rtl8169_update_counters(dev);
1233 data[0] = le64_to_cpu(tp->counters.tx_packets);
1234 data[1] = le64_to_cpu(tp->counters.rx_packets);
1235 data[2] = le64_to_cpu(tp->counters.tx_errors);
1236 data[3] = le32_to_cpu(tp->counters.rx_errors);
1237 data[4] = le16_to_cpu(tp->counters.rx_missed);
1238 data[5] = le16_to_cpu(tp->counters.align_errors);
1239 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1240 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1241 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1242 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1243 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1244 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1245 data[12] = le16_to_cpu(tp->counters.tx_underun);
1248 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1252 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1257 static const struct ethtool_ops rtl8169_ethtool_ops = {
1258 .get_drvinfo = rtl8169_get_drvinfo,
1259 .get_regs_len = rtl8169_get_regs_len,
1260 .get_link = ethtool_op_get_link,
1261 .get_settings = rtl8169_get_settings,
1262 .set_settings = rtl8169_set_settings,
1263 .get_msglevel = rtl8169_get_msglevel,
1264 .set_msglevel = rtl8169_set_msglevel,
1265 .get_rx_csum = rtl8169_get_rx_csum,
1266 .set_rx_csum = rtl8169_set_rx_csum,
1267 .set_tx_csum = ethtool_op_set_tx_csum,
1268 .set_sg = ethtool_op_set_sg,
1269 .set_tso = ethtool_op_set_tso,
1270 .get_regs = rtl8169_get_regs,
1271 .get_wol = rtl8169_get_wol,
1272 .set_wol = rtl8169_set_wol,
1273 .get_strings = rtl8169_get_strings,
1274 .get_sset_count = rtl8169_get_sset_count,
1275 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1278 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1279 void __iomem *ioaddr)
1282 * The driver currently handles the 8168Bf and the 8168Be identically
1283 * but they can be identified more specifically through the test below
1286 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1288 * Same thing for the 8101Eb and the 8101Ec:
1290 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1292 static const struct {
1298 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1299 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1300 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1301 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1304 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1305 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1306 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1307 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1308 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1309 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1310 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1311 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1312 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1315 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1316 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1317 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1318 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1321 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1322 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1323 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1324 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1325 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1326 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1327 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1328 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1329 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1330 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1331 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1332 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1333 /* FIXME: where did these entries come from ? -- FR */
1334 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1335 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1338 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1339 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1340 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1341 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1342 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1343 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1346 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1350 reg = RTL_R32(TxConfig);
1351 while ((reg & p->mask) != p->val)
1353 tp->mac_version = p->mac_version;
1356 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1358 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1366 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1369 mdio_write(ioaddr, regs->reg, regs->val);
1374 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1376 static const struct phy_reg phy_reg_init[] = {
1438 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1441 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1443 static const struct phy_reg phy_reg_init[] = {
1449 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1452 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1453 void __iomem *ioaddr)
1455 struct pci_dev *pdev = tp->pci_dev;
1456 u16 vendor_id, device_id;
1458 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1459 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1461 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1464 mdio_write(ioaddr, 0x1f, 0x0001);
1465 mdio_write(ioaddr, 0x10, 0xf01b);
1466 mdio_write(ioaddr, 0x1f, 0x0000);
1469 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1470 void __iomem *ioaddr)
1472 static const struct phy_reg phy_reg_init[] = {
1512 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1514 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1517 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1519 static const struct phy_reg phy_reg_init[] = {
1567 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1570 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1572 static const struct phy_reg phy_reg_init[] = {
1577 mdio_write(ioaddr, 0x1f, 0x0001);
1578 mdio_patch(ioaddr, 0x16, 1 << 0);
1580 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1583 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1585 static const struct phy_reg phy_reg_init[] = {
1591 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1594 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1596 static const struct phy_reg phy_reg_init[] = {
1604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1607 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1609 static const struct phy_reg phy_reg_init[] = {
1615 mdio_write(ioaddr, 0x1f, 0x0000);
1616 mdio_patch(ioaddr, 0x14, 1 << 5);
1617 mdio_patch(ioaddr, 0x0d, 1 << 5);
1619 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1622 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1624 static const struct phy_reg phy_reg_init[] = {
1644 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1646 mdio_patch(ioaddr, 0x14, 1 << 5);
1647 mdio_patch(ioaddr, 0x0d, 1 << 5);
1648 mdio_write(ioaddr, 0x1f, 0x0000);
1651 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1653 static const struct phy_reg phy_reg_init[] = {
1671 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1673 mdio_patch(ioaddr, 0x16, 1 << 0);
1674 mdio_patch(ioaddr, 0x14, 1 << 5);
1675 mdio_patch(ioaddr, 0x0d, 1 << 5);
1676 mdio_write(ioaddr, 0x1f, 0x0000);
1679 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1681 static const struct phy_reg phy_reg_init[] = {
1693 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1695 mdio_patch(ioaddr, 0x16, 1 << 0);
1696 mdio_patch(ioaddr, 0x14, 1 << 5);
1697 mdio_patch(ioaddr, 0x0d, 1 << 5);
1698 mdio_write(ioaddr, 0x1f, 0x0000);
1701 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1703 rtl8168c_3_hw_phy_config(ioaddr);
1706 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1708 static const struct phy_reg phy_reg_init_0[] = {
1727 static const struct phy_reg phy_reg_init_1[] = {
1734 static const struct phy_reg phy_reg_init_2[] = {
2090 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2092 mdio_write(ioaddr, 0x1f, 0x0002);
2093 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2094 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2096 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2098 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2099 static const struct phy_reg phy_reg_init[] = {
2109 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2111 val = mdio_read(ioaddr, 0x0d);
2113 if ((val & 0x00ff) != 0x006c) {
2114 static const u32 set[] = {
2115 0x0065, 0x0066, 0x0067, 0x0068,
2116 0x0069, 0x006a, 0x006b, 0x006c
2120 mdio_write(ioaddr, 0x1f, 0x0002);
2123 for (i = 0; i < ARRAY_SIZE(set); i++)
2124 mdio_write(ioaddr, 0x0d, val | set[i]);
2127 static const struct phy_reg phy_reg_init[] = {
2135 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2138 mdio_write(ioaddr, 0x1f, 0x0002);
2139 mdio_patch(ioaddr, 0x0d, 0x0300);
2140 mdio_patch(ioaddr, 0x0f, 0x0010);
2142 mdio_write(ioaddr, 0x1f, 0x0002);
2143 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2144 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2146 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2149 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2151 static const struct phy_reg phy_reg_init_0[] = {
2176 static const struct phy_reg phy_reg_init_1[] = {
2489 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2491 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2492 static const struct phy_reg phy_reg_init[] = {
2503 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2505 val = mdio_read(ioaddr, 0x0d);
2506 if ((val & 0x00ff) != 0x006c) {
2508 0x0065, 0x0066, 0x0067, 0x0068,
2509 0x0069, 0x006a, 0x006b, 0x006c
2513 mdio_write(ioaddr, 0x1f, 0x0002);
2516 for (i = 0; i < ARRAY_SIZE(set); i++)
2517 mdio_write(ioaddr, 0x0d, val | set[i]);
2520 static const struct phy_reg phy_reg_init[] = {
2528 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2531 mdio_write(ioaddr, 0x1f, 0x0002);
2532 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2533 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2535 mdio_write(ioaddr, 0x1f, 0x0001);
2536 mdio_write(ioaddr, 0x17, 0x0cc0);
2538 mdio_write(ioaddr, 0x1f, 0x0002);
2539 mdio_patch(ioaddr, 0x0f, 0x0017);
2541 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2544 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2546 static const struct phy_reg phy_reg_init[] = {
2602 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2605 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2607 static const struct phy_reg phy_reg_init[] = {
2614 mdio_write(ioaddr, 0x1f, 0x0000);
2615 mdio_patch(ioaddr, 0x11, 1 << 12);
2616 mdio_patch(ioaddr, 0x19, 1 << 13);
2617 mdio_patch(ioaddr, 0x10, 1 << 15);
2619 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2622 static void rtl_hw_phy_config(struct net_device *dev)
2624 struct rtl8169_private *tp = netdev_priv(dev);
2625 void __iomem *ioaddr = tp->mmio_addr;
2627 rtl8169_print_mac_version(tp);
2629 switch (tp->mac_version) {
2630 case RTL_GIGA_MAC_VER_01:
2632 case RTL_GIGA_MAC_VER_02:
2633 case RTL_GIGA_MAC_VER_03:
2634 rtl8169s_hw_phy_config(ioaddr);
2636 case RTL_GIGA_MAC_VER_04:
2637 rtl8169sb_hw_phy_config(ioaddr);
2639 case RTL_GIGA_MAC_VER_05:
2640 rtl8169scd_hw_phy_config(tp, ioaddr);
2642 case RTL_GIGA_MAC_VER_06:
2643 rtl8169sce_hw_phy_config(ioaddr);
2645 case RTL_GIGA_MAC_VER_07:
2646 case RTL_GIGA_MAC_VER_08:
2647 case RTL_GIGA_MAC_VER_09:
2648 rtl8102e_hw_phy_config(ioaddr);
2650 case RTL_GIGA_MAC_VER_11:
2651 rtl8168bb_hw_phy_config(ioaddr);
2653 case RTL_GIGA_MAC_VER_12:
2654 rtl8168bef_hw_phy_config(ioaddr);
2656 case RTL_GIGA_MAC_VER_17:
2657 rtl8168bef_hw_phy_config(ioaddr);
2659 case RTL_GIGA_MAC_VER_18:
2660 rtl8168cp_1_hw_phy_config(ioaddr);
2662 case RTL_GIGA_MAC_VER_19:
2663 rtl8168c_1_hw_phy_config(ioaddr);
2665 case RTL_GIGA_MAC_VER_20:
2666 rtl8168c_2_hw_phy_config(ioaddr);
2668 case RTL_GIGA_MAC_VER_21:
2669 rtl8168c_3_hw_phy_config(ioaddr);
2671 case RTL_GIGA_MAC_VER_22:
2672 rtl8168c_4_hw_phy_config(ioaddr);
2674 case RTL_GIGA_MAC_VER_23:
2675 case RTL_GIGA_MAC_VER_24:
2676 rtl8168cp_2_hw_phy_config(ioaddr);
2678 case RTL_GIGA_MAC_VER_25:
2679 rtl8168d_1_hw_phy_config(ioaddr);
2681 case RTL_GIGA_MAC_VER_26:
2682 rtl8168d_2_hw_phy_config(ioaddr);
2684 case RTL_GIGA_MAC_VER_27:
2685 rtl8168d_3_hw_phy_config(ioaddr);
2693 static void rtl8169_phy_timer(unsigned long __opaque)
2695 struct net_device *dev = (struct net_device *)__opaque;
2696 struct rtl8169_private *tp = netdev_priv(dev);
2697 struct timer_list *timer = &tp->timer;
2698 void __iomem *ioaddr = tp->mmio_addr;
2699 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2701 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2703 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2706 spin_lock_irq(&tp->lock);
2708 if (tp->phy_reset_pending(ioaddr)) {
2710 * A busy loop could burn quite a few cycles on nowadays CPU.
2711 * Let's delay the execution of the timer for a few ticks.
2717 if (tp->link_ok(ioaddr))
2720 netif_warn(tp, link, dev, "PHY reset until link up\n");
2722 tp->phy_reset_enable(ioaddr);
2725 mod_timer(timer, jiffies + timeout);
2727 spin_unlock_irq(&tp->lock);
2730 static inline void rtl8169_delete_timer(struct net_device *dev)
2732 struct rtl8169_private *tp = netdev_priv(dev);
2733 struct timer_list *timer = &tp->timer;
2735 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2738 del_timer_sync(timer);
2741 static inline void rtl8169_request_timer(struct net_device *dev)
2743 struct rtl8169_private *tp = netdev_priv(dev);
2744 struct timer_list *timer = &tp->timer;
2746 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2749 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2752 #ifdef CONFIG_NET_POLL_CONTROLLER
2754 * Polling 'interrupt' - used by things like netconsole to send skbs
2755 * without having to re-enable interrupts. It's not called while
2756 * the interrupt routine is executing.
2758 static void rtl8169_netpoll(struct net_device *dev)
2760 struct rtl8169_private *tp = netdev_priv(dev);
2761 struct pci_dev *pdev = tp->pci_dev;
2763 disable_irq(pdev->irq);
2764 rtl8169_interrupt(pdev->irq, dev);
2765 enable_irq(pdev->irq);
2769 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2770 void __iomem *ioaddr)
2773 pci_release_regions(pdev);
2774 pci_disable_device(pdev);
2778 static void rtl8169_phy_reset(struct net_device *dev,
2779 struct rtl8169_private *tp)
2781 void __iomem *ioaddr = tp->mmio_addr;
2784 tp->phy_reset_enable(ioaddr);
2785 for (i = 0; i < 100; i++) {
2786 if (!tp->phy_reset_pending(ioaddr))
2790 netif_err(tp, link, dev, "PHY reset failed\n");
2793 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2795 void __iomem *ioaddr = tp->mmio_addr;
2797 rtl_hw_phy_config(dev);
2799 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2800 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2804 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2806 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2807 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2809 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2810 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2812 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2813 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2816 rtl8169_phy_reset(dev, tp);
2819 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2820 * only 8101. Don't panic.
2822 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2824 if (RTL_R8(PHYstatus) & TBI_Enable)
2825 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2828 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2830 void __iomem *ioaddr = tp->mmio_addr;
2834 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2835 high = addr[4] | (addr[5] << 8);
2837 spin_lock_irq(&tp->lock);
2839 RTL_W8(Cfg9346, Cfg9346_Unlock);
2841 RTL_W32(MAC4, high);
2842 RTL_W8(Cfg9346, Cfg9346_Lock);
2844 spin_unlock_irq(&tp->lock);
2847 static int rtl_set_mac_address(struct net_device *dev, void *p)
2849 struct rtl8169_private *tp = netdev_priv(dev);
2850 struct sockaddr *addr = p;
2852 if (!is_valid_ether_addr(addr->sa_data))
2853 return -EADDRNOTAVAIL;
2855 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2857 rtl_rar_set(tp, dev->dev_addr);
2862 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2864 struct rtl8169_private *tp = netdev_priv(dev);
2865 struct mii_ioctl_data *data = if_mii(ifr);
2867 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2870 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2874 data->phy_id = 32; /* Internal PHY */
2878 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2882 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2888 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2893 static const struct rtl_cfg_info {
2894 void (*hw_start)(struct net_device *);
2895 unsigned int region;
2901 } rtl_cfg_infos [] = {
2903 .hw_start = rtl_hw_start_8169,
2906 .intr_event = SYSErr | LinkChg | RxOverflow |
2907 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2908 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2909 .features = RTL_FEATURE_GMII,
2910 .default_ver = RTL_GIGA_MAC_VER_01,
2913 .hw_start = rtl_hw_start_8168,
2916 .intr_event = SYSErr | LinkChg | RxOverflow |
2917 TxErr | TxOK | RxOK | RxErr,
2918 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2919 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2920 .default_ver = RTL_GIGA_MAC_VER_11,
2923 .hw_start = rtl_hw_start_8101,
2926 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2927 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2928 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2929 .features = RTL_FEATURE_MSI,
2930 .default_ver = RTL_GIGA_MAC_VER_13,
2934 /* Cfg9346_Unlock assumed. */
2935 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2936 const struct rtl_cfg_info *cfg)
2941 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2942 if (cfg->features & RTL_FEATURE_MSI) {
2943 if (pci_enable_msi(pdev)) {
2944 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2947 msi = RTL_FEATURE_MSI;
2950 RTL_W8(Config2, cfg2);
2954 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2956 if (tp->features & RTL_FEATURE_MSI) {
2957 pci_disable_msi(pdev);
2958 tp->features &= ~RTL_FEATURE_MSI;
2962 static const struct net_device_ops rtl8169_netdev_ops = {
2963 .ndo_open = rtl8169_open,
2964 .ndo_stop = rtl8169_close,
2965 .ndo_get_stats = rtl8169_get_stats,
2966 .ndo_start_xmit = rtl8169_start_xmit,
2967 .ndo_tx_timeout = rtl8169_tx_timeout,
2968 .ndo_validate_addr = eth_validate_addr,
2969 .ndo_change_mtu = rtl8169_change_mtu,
2970 .ndo_set_mac_address = rtl_set_mac_address,
2971 .ndo_do_ioctl = rtl8169_ioctl,
2972 .ndo_set_multicast_list = rtl_set_rx_mode,
2973 #ifdef CONFIG_R8169_VLAN
2974 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2976 #ifdef CONFIG_NET_POLL_CONTROLLER
2977 .ndo_poll_controller = rtl8169_netpoll,
2982 static int __devinit
2983 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2985 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2986 const unsigned int region = cfg->region;
2987 struct rtl8169_private *tp;
2988 struct mii_if_info *mii;
2989 struct net_device *dev;
2990 void __iomem *ioaddr;
2993 int this_use_dac = use_dac;
2995 if (netif_msg_drv(&debug)) {
2996 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2997 MODULENAME, RTL8169_VERSION);
3000 dev = alloc_etherdev(sizeof (*tp));
3002 if (netif_msg_drv(&debug))
3003 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3008 SET_NETDEV_DEV(dev, &pdev->dev);
3009 dev->netdev_ops = &rtl8169_netdev_ops;
3010 tp = netdev_priv(dev);
3013 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3017 mii->mdio_read = rtl_mdio_read;
3018 mii->mdio_write = rtl_mdio_write;
3019 mii->phy_id_mask = 0x1f;
3020 mii->reg_num_mask = 0x1f;
3021 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3023 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3024 rc = pci_enable_device(pdev);
3026 netif_err(tp, probe, dev, "enable failure\n");
3027 goto err_out_free_dev_1;
3030 rc = pci_set_mwi(pdev);
3032 goto err_out_disable_2;
3034 /* make sure PCI base addr 1 is MMIO */
3035 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3036 netif_err(tp, probe, dev,
3037 "region #%d not an MMIO resource, aborting\n",
3043 /* check for weird/broken PCI region reporting */
3044 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3045 netif_err(tp, probe, dev,
3046 "Invalid PCI region size(s), aborting\n");
3051 rc = pci_request_regions(pdev, MODULENAME);
3053 netif_err(tp, probe, dev, "could not request regions\n");
3057 tp->cp_cmd = PCIMulRW | RxChkSum;
3059 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3061 netif_info(tp, probe, dev, "no PCI Express capability\n");
3063 if (this_use_dac < 0)
3064 this_use_dac = tp->pcie_cap != 0;
3066 if ((sizeof(dma_addr_t) > 4) &&
3068 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3069 netif_info(tp, probe, dev, "using 64-bit DMA\n");
3070 tp->cp_cmd |= PCIDAC;
3071 dev->features |= NETIF_F_HIGHDMA;
3073 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3075 netif_err(tp, probe, dev, "DMA configuration failed\n");
3076 goto err_out_free_res_4;
3080 /* ioremap MMIO region */
3081 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3083 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3085 goto err_out_free_res_4;
3088 RTL_W16(IntrMask, 0x0000);
3090 /* Soft reset the chip. */
3091 RTL_W8(ChipCmd, CmdReset);
3093 /* Check that the chip has finished the reset. */
3094 for (i = 0; i < 100; i++) {
3095 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3097 msleep_interruptible(1);
3100 RTL_W16(IntrStatus, 0xffff);
3102 pci_set_master(pdev);
3104 /* Identify chip attached to board */
3105 rtl8169_get_mac_version(tp, ioaddr);
3107 /* Use appropriate default if unknown */
3108 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3109 netif_notice(tp, probe, dev,
3110 "unknown MAC, using family default\n");
3111 tp->mac_version = cfg->default_ver;
3114 rtl8169_print_mac_version(tp);
3116 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3117 if (tp->mac_version == rtl_chip_info[i].mac_version)
3120 if (i == ARRAY_SIZE(rtl_chip_info)) {
3122 "driver bug, MAC version not found in rtl_chip_info\n");
3127 RTL_W8(Cfg9346, Cfg9346_Unlock);
3128 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3129 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3130 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3131 tp->features |= RTL_FEATURE_WOL;
3132 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3133 tp->features |= RTL_FEATURE_WOL;
3134 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3135 RTL_W8(Cfg9346, Cfg9346_Lock);
3137 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3138 (RTL_R8(PHYstatus) & TBI_Enable)) {
3139 tp->set_speed = rtl8169_set_speed_tbi;
3140 tp->get_settings = rtl8169_gset_tbi;
3141 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3142 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3143 tp->link_ok = rtl8169_tbi_link_ok;
3144 tp->do_ioctl = rtl_tbi_ioctl;
3146 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3148 tp->set_speed = rtl8169_set_speed_xmii;
3149 tp->get_settings = rtl8169_gset_xmii;
3150 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3151 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3152 tp->link_ok = rtl8169_xmii_link_ok;
3153 tp->do_ioctl = rtl_xmii_ioctl;
3156 spin_lock_init(&tp->lock);
3158 tp->mmio_addr = ioaddr;
3160 /* Get MAC address */
3161 for (i = 0; i < MAC_ADDR_LEN; i++)
3162 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3163 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3165 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3166 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3167 dev->irq = pdev->irq;
3168 dev->base_addr = (unsigned long) ioaddr;
3170 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3172 #ifdef CONFIG_R8169_VLAN
3173 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3176 tp->intr_mask = 0xffff;
3177 tp->align = cfg->align;
3178 tp->hw_start = cfg->hw_start;
3179 tp->intr_event = cfg->intr_event;
3180 tp->napi_event = cfg->napi_event;
3182 init_timer(&tp->timer);
3183 tp->timer.data = (unsigned long) dev;
3184 tp->timer.function = rtl8169_phy_timer;
3186 rc = register_netdev(dev);
3190 pci_set_drvdata(pdev, dev);
3192 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3193 rtl_chip_info[tp->chipset].name,
3194 dev->base_addr, dev->dev_addr,
3195 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3197 rtl8169_init_phy(dev, tp);
3200 * Pretend we are using VLANs; This bypasses a nasty bug where
3201 * Interrupts stop flowing on high load on 8110SCd controllers.
3203 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3204 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3206 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3208 if (pci_dev_run_wake(pdev)) {
3209 pm_runtime_set_active(&pdev->dev);
3210 pm_runtime_enable(&pdev->dev);
3212 pm_runtime_idle(&pdev->dev);
3218 rtl_disable_msi(pdev, tp);
3221 pci_release_regions(pdev);
3223 pci_clear_mwi(pdev);
3225 pci_disable_device(pdev);
3231 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3233 struct net_device *dev = pci_get_drvdata(pdev);
3234 struct rtl8169_private *tp = netdev_priv(dev);
3236 pm_runtime_get_sync(&pdev->dev);
3238 flush_scheduled_work();
3240 unregister_netdev(dev);
3242 if (pci_dev_run_wake(pdev)) {
3243 pm_runtime_disable(&pdev->dev);
3244 pm_runtime_set_suspended(&pdev->dev);
3246 pm_runtime_put_noidle(&pdev->dev);
3248 /* restore original MAC address */
3249 rtl_rar_set(tp, dev->perm_addr);
3251 rtl_disable_msi(pdev, tp);
3252 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3253 pci_set_drvdata(pdev, NULL);
3256 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3257 struct net_device *dev)
3259 unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3261 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3264 static int rtl8169_open(struct net_device *dev)
3266 struct rtl8169_private *tp = netdev_priv(dev);
3267 struct pci_dev *pdev = tp->pci_dev;
3268 int retval = -ENOMEM;
3270 pm_runtime_get_sync(&pdev->dev);
3272 rtl8169_set_rxbufsize(tp, dev);
3275 * Rx and Tx desscriptors needs 256 bytes alignment.
3276 * pci_alloc_consistent provides more.
3278 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3280 if (!tp->TxDescArray)
3281 goto err_pm_runtime_put;
3283 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3285 if (!tp->RxDescArray)
3288 retval = rtl8169_init_ring(dev);
3292 INIT_DELAYED_WORK(&tp->task, NULL);
3296 retval = request_irq(dev->irq, rtl8169_interrupt,
3297 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3300 goto err_release_ring_2;
3302 napi_enable(&tp->napi);
3306 rtl8169_request_timer(dev);
3308 tp->saved_wolopts = 0;
3309 pm_runtime_put_noidle(&pdev->dev);
3311 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3316 rtl8169_rx_clear(tp);
3318 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3320 tp->RxDescArray = NULL;
3322 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3324 tp->TxDescArray = NULL;
3326 pm_runtime_put_noidle(&pdev->dev);
3330 static void rtl8169_hw_reset(void __iomem *ioaddr)
3332 /* Disable interrupts */
3333 rtl8169_irq_mask_and_ack(ioaddr);
3335 /* Reset the chipset */
3336 RTL_W8(ChipCmd, CmdReset);
3342 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3344 void __iomem *ioaddr = tp->mmio_addr;
3345 u32 cfg = rtl8169_rx_config;
3347 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3348 RTL_W32(RxConfig, cfg);
3350 /* Set DMA burst size and Interframe Gap Time */
3351 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3352 (InterFrameGap << TxInterFrameGapShift));
3355 static void rtl_hw_start(struct net_device *dev)
3357 struct rtl8169_private *tp = netdev_priv(dev);
3358 void __iomem *ioaddr = tp->mmio_addr;
3361 /* Soft reset the chip. */
3362 RTL_W8(ChipCmd, CmdReset);
3364 /* Check that the chip has finished the reset. */
3365 for (i = 0; i < 100; i++) {
3366 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3368 msleep_interruptible(1);
3373 netif_start_queue(dev);
3377 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3378 void __iomem *ioaddr)
3381 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3382 * register to be written before TxDescAddrLow to work.
3383 * Switching from MMIO to I/O access fixes the issue as well.
3385 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3386 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3387 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3388 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3391 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3395 cmd = RTL_R16(CPlusCmd);
3396 RTL_W16(CPlusCmd, cmd);
3400 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3402 /* Low hurts. Let's disable the filtering. */
3403 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3406 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3408 static const struct {
3413 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3414 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3415 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3416 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3421 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3422 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3423 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3424 RTL_W32(0x7c, p->val);
3430 static void rtl_hw_start_8169(struct net_device *dev)
3432 struct rtl8169_private *tp = netdev_priv(dev);
3433 void __iomem *ioaddr = tp->mmio_addr;
3434 struct pci_dev *pdev = tp->pci_dev;
3436 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3437 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3438 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3441 RTL_W8(Cfg9346, Cfg9346_Unlock);
3442 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3443 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3444 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3445 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3446 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3448 RTL_W8(EarlyTxThres, EarlyTxThld);
3450 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3452 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3453 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3454 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3455 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3456 rtl_set_rx_tx_config_registers(tp);
3458 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3460 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3461 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3462 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3463 "Bit-3 and bit-14 MUST be 1\n");
3464 tp->cp_cmd |= (1 << 14);
3467 RTL_W16(CPlusCmd, tp->cp_cmd);
3469 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3472 * Undocumented corner. Supposedly:
3473 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3475 RTL_W16(IntrMitigate, 0x0000);
3477 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3479 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3480 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3481 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3482 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3483 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3484 rtl_set_rx_tx_config_registers(tp);
3487 RTL_W8(Cfg9346, Cfg9346_Lock);
3489 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3492 RTL_W32(RxMissed, 0);
3494 rtl_set_rx_mode(dev);
3496 /* no early-rx interrupts */
3497 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3499 /* Enable all known interrupts by setting the interrupt mask. */
3500 RTL_W16(IntrMask, tp->intr_event);
3503 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3505 struct net_device *dev = pci_get_drvdata(pdev);
3506 struct rtl8169_private *tp = netdev_priv(dev);
3507 int cap = tp->pcie_cap;
3512 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3513 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3514 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3518 static void rtl_csi_access_enable(void __iomem *ioaddr)
3522 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3523 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3527 unsigned int offset;
3532 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3537 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3538 rtl_ephy_write(ioaddr, e->offset, w);
3543 static void rtl_disable_clock_request(struct pci_dev *pdev)
3545 struct net_device *dev = pci_get_drvdata(pdev);
3546 struct rtl8169_private *tp = netdev_priv(dev);
3547 int cap = tp->pcie_cap;
3552 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3553 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3554 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3558 #define R8168_CPCMD_QUIRK_MASK (\
3569 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3571 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3573 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3575 rtl_tx_performance_tweak(pdev,
3576 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3579 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3581 rtl_hw_start_8168bb(ioaddr, pdev);
3583 RTL_W8(EarlyTxThres, EarlyTxThld);
3585 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3588 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3590 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3592 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3594 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3596 rtl_disable_clock_request(pdev);
3598 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3601 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3603 static const struct ephy_info e_info_8168cp[] = {
3604 { 0x01, 0, 0x0001 },
3605 { 0x02, 0x0800, 0x1000 },
3606 { 0x03, 0, 0x0042 },
3607 { 0x06, 0x0080, 0x0000 },
3611 rtl_csi_access_enable(ioaddr);
3613 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3615 __rtl_hw_start_8168cp(ioaddr, pdev);
3618 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3620 rtl_csi_access_enable(ioaddr);
3622 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3624 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3626 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3629 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3631 rtl_csi_access_enable(ioaddr);
3633 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3636 RTL_W8(DBG_REG, 0x20);
3638 RTL_W8(EarlyTxThres, EarlyTxThld);
3640 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3642 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3645 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3647 static const struct ephy_info e_info_8168c_1[] = {
3648 { 0x02, 0x0800, 0x1000 },
3649 { 0x03, 0, 0x0002 },
3650 { 0x06, 0x0080, 0x0000 }
3653 rtl_csi_access_enable(ioaddr);
3655 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3657 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3659 __rtl_hw_start_8168cp(ioaddr, pdev);
3662 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3664 static const struct ephy_info e_info_8168c_2[] = {
3665 { 0x01, 0, 0x0001 },
3666 { 0x03, 0x0400, 0x0220 }
3669 rtl_csi_access_enable(ioaddr);
3671 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3673 __rtl_hw_start_8168cp(ioaddr, pdev);
3676 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3678 rtl_hw_start_8168c_2(ioaddr, pdev);
3681 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3683 rtl_csi_access_enable(ioaddr);
3685 __rtl_hw_start_8168cp(ioaddr, pdev);
3688 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3690 rtl_csi_access_enable(ioaddr);
3692 rtl_disable_clock_request(pdev);
3694 RTL_W8(EarlyTxThres, EarlyTxThld);
3696 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3698 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3701 static void rtl_hw_start_8168(struct net_device *dev)
3703 struct rtl8169_private *tp = netdev_priv(dev);
3704 void __iomem *ioaddr = tp->mmio_addr;
3705 struct pci_dev *pdev = tp->pci_dev;
3707 RTL_W8(Cfg9346, Cfg9346_Unlock);
3709 RTL_W8(EarlyTxThres, EarlyTxThld);
3711 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3713 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3715 RTL_W16(CPlusCmd, tp->cp_cmd);
3717 RTL_W16(IntrMitigate, 0x5151);
3719 /* Work around for RxFIFO overflow. */
3720 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3721 tp->intr_event |= RxFIFOOver | PCSTimeout;
3722 tp->intr_event &= ~RxOverflow;
3725 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3727 rtl_set_rx_mode(dev);
3729 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3730 (InterFrameGap << TxInterFrameGapShift));
3734 switch (tp->mac_version) {
3735 case RTL_GIGA_MAC_VER_11:
3736 rtl_hw_start_8168bb(ioaddr, pdev);
3739 case RTL_GIGA_MAC_VER_12:
3740 case RTL_GIGA_MAC_VER_17:
3741 rtl_hw_start_8168bef(ioaddr, pdev);
3744 case RTL_GIGA_MAC_VER_18:
3745 rtl_hw_start_8168cp_1(ioaddr, pdev);
3748 case RTL_GIGA_MAC_VER_19:
3749 rtl_hw_start_8168c_1(ioaddr, pdev);
3752 case RTL_GIGA_MAC_VER_20:
3753 rtl_hw_start_8168c_2(ioaddr, pdev);
3756 case RTL_GIGA_MAC_VER_21:
3757 rtl_hw_start_8168c_3(ioaddr, pdev);
3760 case RTL_GIGA_MAC_VER_22:
3761 rtl_hw_start_8168c_4(ioaddr, pdev);
3764 case RTL_GIGA_MAC_VER_23:
3765 rtl_hw_start_8168cp_2(ioaddr, pdev);
3768 case RTL_GIGA_MAC_VER_24:
3769 rtl_hw_start_8168cp_3(ioaddr, pdev);
3772 case RTL_GIGA_MAC_VER_25:
3773 case RTL_GIGA_MAC_VER_26:
3774 case RTL_GIGA_MAC_VER_27:
3775 rtl_hw_start_8168d(ioaddr, pdev);
3779 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3780 dev->name, tp->mac_version);
3784 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3786 RTL_W8(Cfg9346, Cfg9346_Lock);
3788 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3790 RTL_W16(IntrMask, tp->intr_event);
3793 #define R810X_CPCMD_QUIRK_MASK (\
3805 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3807 static const struct ephy_info e_info_8102e_1[] = {
3808 { 0x01, 0, 0x6e65 },
3809 { 0x02, 0, 0x091f },
3810 { 0x03, 0, 0xc2f9 },
3811 { 0x06, 0, 0xafb5 },
3812 { 0x07, 0, 0x0e00 },
3813 { 0x19, 0, 0xec80 },
3814 { 0x01, 0, 0x2e65 },
3819 rtl_csi_access_enable(ioaddr);
3821 RTL_W8(DBG_REG, FIX_NAK_1);
3823 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3826 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3827 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3829 cfg1 = RTL_R8(Config1);
3830 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3831 RTL_W8(Config1, cfg1 & ~LEDS0);
3833 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3835 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3838 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3840 rtl_csi_access_enable(ioaddr);
3842 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3844 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3845 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3847 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3850 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3852 rtl_hw_start_8102e_2(ioaddr, pdev);
3854 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3857 static void rtl_hw_start_8101(struct net_device *dev)
3859 struct rtl8169_private *tp = netdev_priv(dev);
3860 void __iomem *ioaddr = tp->mmio_addr;
3861 struct pci_dev *pdev = tp->pci_dev;
3863 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3864 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3865 int cap = tp->pcie_cap;
3868 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3869 PCI_EXP_DEVCTL_NOSNOOP_EN);
3873 switch (tp->mac_version) {
3874 case RTL_GIGA_MAC_VER_07:
3875 rtl_hw_start_8102e_1(ioaddr, pdev);
3878 case RTL_GIGA_MAC_VER_08:
3879 rtl_hw_start_8102e_3(ioaddr, pdev);
3882 case RTL_GIGA_MAC_VER_09:
3883 rtl_hw_start_8102e_2(ioaddr, pdev);
3887 RTL_W8(Cfg9346, Cfg9346_Unlock);
3889 RTL_W8(EarlyTxThres, EarlyTxThld);
3891 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3893 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3895 RTL_W16(CPlusCmd, tp->cp_cmd);
3897 RTL_W16(IntrMitigate, 0x0000);
3899 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3901 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3902 rtl_set_rx_tx_config_registers(tp);
3904 RTL_W8(Cfg9346, Cfg9346_Lock);
3908 rtl_set_rx_mode(dev);
3910 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3912 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3914 RTL_W16(IntrMask, tp->intr_event);
3917 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3919 struct rtl8169_private *tp = netdev_priv(dev);
3922 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3927 if (!netif_running(dev))
3932 rtl8169_set_rxbufsize(tp, dev);
3934 ret = rtl8169_init_ring(dev);
3938 napi_enable(&tp->napi);
3942 rtl8169_request_timer(dev);
3948 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3950 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3951 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3954 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3955 struct sk_buff **sk_buff, struct RxDesc *desc)
3957 struct pci_dev *pdev = tp->pci_dev;
3959 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3960 PCI_DMA_FROMDEVICE);
3961 dev_kfree_skb(*sk_buff);
3963 rtl8169_make_unusable_by_asic(desc);
3966 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3968 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3970 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3973 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3976 desc->addr = cpu_to_le64(mapping);
3978 rtl8169_mark_to_asic(desc, rx_buf_sz);
3981 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3982 struct net_device *dev,
3983 struct RxDesc *desc, int rx_buf_sz,
3986 struct sk_buff *skb;
3990 pad = align ? align : NET_IP_ALIGN;
3992 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3996 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3998 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3999 PCI_DMA_FROMDEVICE);
4001 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4006 rtl8169_make_unusable_by_asic(desc);
4010 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4014 for (i = 0; i < NUM_RX_DESC; i++) {
4015 if (tp->Rx_skbuff[i]) {
4016 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4017 tp->RxDescArray + i);
4022 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4027 for (cur = start; end - cur != 0; cur++) {
4028 struct sk_buff *skb;
4029 unsigned int i = cur % NUM_RX_DESC;
4031 WARN_ON((s32)(end - cur) < 0);
4033 if (tp->Rx_skbuff[i])
4036 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4037 tp->RxDescArray + i,
4038 tp->rx_buf_sz, tp->align);
4042 tp->Rx_skbuff[i] = skb;
4047 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4049 desc->opts1 |= cpu_to_le32(RingEnd);
4052 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4054 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4057 static int rtl8169_init_ring(struct net_device *dev)
4059 struct rtl8169_private *tp = netdev_priv(dev);
4061 rtl8169_init_ring_indexes(tp);
4063 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4064 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4066 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4069 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4074 rtl8169_rx_clear(tp);
4078 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4079 struct TxDesc *desc)
4081 unsigned int len = tx_skb->len;
4083 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4090 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4094 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4095 unsigned int entry = i % NUM_TX_DESC;
4096 struct ring_info *tx_skb = tp->tx_skb + entry;
4097 unsigned int len = tx_skb->len;
4100 struct sk_buff *skb = tx_skb->skb;
4102 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4103 tp->TxDescArray + entry);
4108 tp->dev->stats.tx_dropped++;
4111 tp->cur_tx = tp->dirty_tx = 0;
4114 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4116 struct rtl8169_private *tp = netdev_priv(dev);
4118 PREPARE_DELAYED_WORK(&tp->task, task);
4119 schedule_delayed_work(&tp->task, 4);
4122 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4124 struct rtl8169_private *tp = netdev_priv(dev);
4125 void __iomem *ioaddr = tp->mmio_addr;
4127 synchronize_irq(dev->irq);
4129 /* Wait for any pending NAPI task to complete */
4130 napi_disable(&tp->napi);
4132 rtl8169_irq_mask_and_ack(ioaddr);
4134 tp->intr_mask = 0xffff;
4135 RTL_W16(IntrMask, tp->intr_event);
4136 napi_enable(&tp->napi);
4139 static void rtl8169_reinit_task(struct work_struct *work)
4141 struct rtl8169_private *tp =
4142 container_of(work, struct rtl8169_private, task.work);
4143 struct net_device *dev = tp->dev;
4148 if (!netif_running(dev))
4151 rtl8169_wait_for_quiescence(dev);
4154 ret = rtl8169_open(dev);
4155 if (unlikely(ret < 0)) {
4156 if (net_ratelimit())
4157 netif_err(tp, drv, dev,
4158 "reinit failure (status = %d). Rescheduling\n",
4160 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4167 static void rtl8169_reset_task(struct work_struct *work)
4169 struct rtl8169_private *tp =
4170 container_of(work, struct rtl8169_private, task.work);
4171 struct net_device *dev = tp->dev;
4175 if (!netif_running(dev))
4178 rtl8169_wait_for_quiescence(dev);
4180 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4181 rtl8169_tx_clear(tp);
4183 if (tp->dirty_rx == tp->cur_rx) {
4184 rtl8169_init_ring_indexes(tp);
4186 netif_wake_queue(dev);
4187 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4189 if (net_ratelimit())
4190 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4191 rtl8169_schedule_work(dev, rtl8169_reset_task);
4198 static void rtl8169_tx_timeout(struct net_device *dev)
4200 struct rtl8169_private *tp = netdev_priv(dev);
4202 rtl8169_hw_reset(tp->mmio_addr);
4204 /* Let's wait a bit while any (async) irq lands on */
4205 rtl8169_schedule_work(dev, rtl8169_reset_task);
4208 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4211 struct skb_shared_info *info = skb_shinfo(skb);
4212 unsigned int cur_frag, entry;
4213 struct TxDesc * uninitialized_var(txd);
4216 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4217 skb_frag_t *frag = info->frags + cur_frag;
4222 entry = (entry + 1) % NUM_TX_DESC;
4224 txd = tp->TxDescArray + entry;
4226 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4227 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4229 /* anti gcc 2.95.3 bugware (sic) */
4230 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4232 txd->opts1 = cpu_to_le32(status);
4233 txd->addr = cpu_to_le64(mapping);
4235 tp->tx_skb[entry].len = len;
4239 tp->tx_skb[entry].skb = skb;
4240 txd->opts1 |= cpu_to_le32(LastFrag);
4246 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4248 if (dev->features & NETIF_F_TSO) {
4249 u32 mss = skb_shinfo(skb)->gso_size;
4252 return LargeSend | ((mss & MSSMask) << MSSShift);
4254 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4255 const struct iphdr *ip = ip_hdr(skb);
4257 if (ip->protocol == IPPROTO_TCP)
4258 return IPCS | TCPCS;
4259 else if (ip->protocol == IPPROTO_UDP)
4260 return IPCS | UDPCS;
4261 WARN_ON(1); /* we need a WARN() */
4266 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4267 struct net_device *dev)
4269 struct rtl8169_private *tp = netdev_priv(dev);
4270 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4271 struct TxDesc *txd = tp->TxDescArray + entry;
4272 void __iomem *ioaddr = tp->mmio_addr;
4277 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4278 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4282 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4285 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4287 frags = rtl8169_xmit_frags(tp, skb, opts1);
4289 len = skb_headlen(skb);
4293 opts1 |= FirstFrag | LastFrag;
4294 tp->tx_skb[entry].skb = skb;
4297 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4299 tp->tx_skb[entry].len = len;
4300 txd->addr = cpu_to_le64(mapping);
4301 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4305 /* anti gcc 2.95.3 bugware (sic) */
4306 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4307 txd->opts1 = cpu_to_le32(status);
4309 tp->cur_tx += frags + 1;
4313 RTL_W8(TxPoll, NPQ); /* set polling bit */
4315 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4316 netif_stop_queue(dev);
4318 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4319 netif_wake_queue(dev);
4322 return NETDEV_TX_OK;
4325 netif_stop_queue(dev);
4326 dev->stats.tx_dropped++;
4327 return NETDEV_TX_BUSY;
4330 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4332 struct rtl8169_private *tp = netdev_priv(dev);
4333 struct pci_dev *pdev = tp->pci_dev;
4334 void __iomem *ioaddr = tp->mmio_addr;
4335 u16 pci_status, pci_cmd;
4337 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4338 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4340 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4341 pci_cmd, pci_status);
4344 * The recovery sequence below admits a very elaborated explanation:
4345 * - it seems to work;
4346 * - I did not see what else could be done;
4347 * - it makes iop3xx happy.
4349 * Feel free to adjust to your needs.
4351 if (pdev->broken_parity_status)
4352 pci_cmd &= ~PCI_COMMAND_PARITY;
4354 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4356 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4358 pci_write_config_word(pdev, PCI_STATUS,
4359 pci_status & (PCI_STATUS_DETECTED_PARITY |
4360 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4361 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4363 /* The infamous DAC f*ckup only happens at boot time */
4364 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4365 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4366 tp->cp_cmd &= ~PCIDAC;
4367 RTL_W16(CPlusCmd, tp->cp_cmd);
4368 dev->features &= ~NETIF_F_HIGHDMA;
4371 rtl8169_hw_reset(ioaddr);
4373 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4376 static void rtl8169_tx_interrupt(struct net_device *dev,
4377 struct rtl8169_private *tp,
4378 void __iomem *ioaddr)
4380 unsigned int dirty_tx, tx_left;
4382 dirty_tx = tp->dirty_tx;
4384 tx_left = tp->cur_tx - dirty_tx;
4386 while (tx_left > 0) {
4387 unsigned int entry = dirty_tx % NUM_TX_DESC;
4388 struct ring_info *tx_skb = tp->tx_skb + entry;
4389 u32 len = tx_skb->len;
4393 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4394 if (status & DescOwn)
4397 dev->stats.tx_bytes += len;
4398 dev->stats.tx_packets++;
4400 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4402 if (status & LastFrag) {
4403 dev_kfree_skb(tx_skb->skb);
4410 if (tp->dirty_tx != dirty_tx) {
4411 tp->dirty_tx = dirty_tx;
4413 if (netif_queue_stopped(dev) &&
4414 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4415 netif_wake_queue(dev);
4418 * 8168 hack: TxPoll requests are lost when the Tx packets are
4419 * too close. Let's kick an extra TxPoll request when a burst
4420 * of start_xmit activity is detected (if it is not detected,
4421 * it is slow enough). -- FR
4424 if (tp->cur_tx != dirty_tx)
4425 RTL_W8(TxPoll, NPQ);
4429 static inline int rtl8169_fragmented_frame(u32 status)
4431 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4434 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4436 u32 opts1 = le32_to_cpu(desc->opts1);
4437 u32 status = opts1 & RxProtoMask;
4439 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4440 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4441 ((status == RxProtoIP) && !(opts1 & IPFail)))
4442 skb->ip_summed = CHECKSUM_UNNECESSARY;
4444 skb->ip_summed = CHECKSUM_NONE;
4447 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4448 struct rtl8169_private *tp, int pkt_size,
4451 struct sk_buff *skb;
4454 if (pkt_size >= rx_copybreak)
4457 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4461 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4462 PCI_DMA_FROMDEVICE);
4463 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4470 static int rtl8169_rx_interrupt(struct net_device *dev,
4471 struct rtl8169_private *tp,
4472 void __iomem *ioaddr, u32 budget)
4474 unsigned int cur_rx, rx_left;
4475 unsigned int delta, count;
4477 cur_rx = tp->cur_rx;
4478 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4479 rx_left = min(rx_left, budget);
4481 for (; rx_left > 0; rx_left--, cur_rx++) {
4482 unsigned int entry = cur_rx % NUM_RX_DESC;
4483 struct RxDesc *desc = tp->RxDescArray + entry;
4487 status = le32_to_cpu(desc->opts1);
4489 if (status & DescOwn)
4491 if (unlikely(status & RxRES)) {
4492 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4494 dev->stats.rx_errors++;
4495 if (status & (RxRWT | RxRUNT))
4496 dev->stats.rx_length_errors++;
4498 dev->stats.rx_crc_errors++;
4499 if (status & RxFOVF) {
4500 rtl8169_schedule_work(dev, rtl8169_reset_task);
4501 dev->stats.rx_fifo_errors++;
4503 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4505 struct sk_buff *skb = tp->Rx_skbuff[entry];
4506 dma_addr_t addr = le64_to_cpu(desc->addr);
4507 int pkt_size = (status & 0x00001FFF) - 4;
4508 struct pci_dev *pdev = tp->pci_dev;
4511 * The driver does not support incoming fragmented
4512 * frames. They are seen as a symptom of over-mtu
4515 if (unlikely(rtl8169_fragmented_frame(status))) {
4516 dev->stats.rx_dropped++;
4517 dev->stats.rx_length_errors++;
4518 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4522 rtl8169_rx_csum(skb, desc);
4524 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4525 pci_dma_sync_single_for_device(pdev, addr,
4526 pkt_size, PCI_DMA_FROMDEVICE);
4527 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4529 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4530 PCI_DMA_FROMDEVICE);
4531 tp->Rx_skbuff[entry] = NULL;
4534 skb_put(skb, pkt_size);
4535 skb->protocol = eth_type_trans(skb, dev);
4537 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
4538 netif_receive_skb(skb);
4540 dev->stats.rx_bytes += pkt_size;
4541 dev->stats.rx_packets++;
4544 /* Work around for AMD plateform. */
4545 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4546 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4552 count = cur_rx - tp->cur_rx;
4553 tp->cur_rx = cur_rx;
4555 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4556 if (!delta && count)
4557 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4558 tp->dirty_rx += delta;
4561 * FIXME: until there is periodic timer to try and refill the ring,
4562 * a temporary shortage may definitely kill the Rx process.
4563 * - disable the asic to try and avoid an overflow and kick it again
4565 * - how do others driver handle this condition (Uh oh...).
4567 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4568 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4573 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4575 struct net_device *dev = dev_instance;
4576 struct rtl8169_private *tp = netdev_priv(dev);
4577 void __iomem *ioaddr = tp->mmio_addr;
4581 /* loop handling interrupts until we have no new ones or
4582 * we hit a invalid/hotplug case.
4584 status = RTL_R16(IntrStatus);
4585 while (status && status != 0xffff) {
4588 /* Handle all of the error cases first. These will reset
4589 * the chip, so just exit the loop.
4591 if (unlikely(!netif_running(dev))) {
4592 rtl8169_asic_down(ioaddr);
4596 /* Work around for rx fifo overflow */
4597 if (unlikely(status & RxFIFOOver) &&
4598 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4599 netif_stop_queue(dev);
4600 rtl8169_tx_timeout(dev);
4604 if (unlikely(status & SYSErr)) {
4605 rtl8169_pcierr_interrupt(dev);
4609 if (status & LinkChg)
4610 rtl8169_check_link_status(dev, tp, ioaddr);
4612 /* We need to see the lastest version of tp->intr_mask to
4613 * avoid ignoring an MSI interrupt and having to wait for
4614 * another event which may never come.
4617 if (status & tp->intr_mask & tp->napi_event) {
4618 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4619 tp->intr_mask = ~tp->napi_event;
4621 if (likely(napi_schedule_prep(&tp->napi)))
4622 __napi_schedule(&tp->napi);
4624 netif_info(tp, intr, dev,
4625 "interrupt %04x in poll\n", status);
4628 /* We only get a new MSI interrupt when all active irq
4629 * sources on the chip have been acknowledged. So, ack
4630 * everything we've seen and check if new sources have become
4631 * active to avoid blocking all interrupts from the chip.
4634 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4635 status = RTL_R16(IntrStatus);
4638 return IRQ_RETVAL(handled);
4641 static int rtl8169_poll(struct napi_struct *napi, int budget)
4643 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4644 struct net_device *dev = tp->dev;
4645 void __iomem *ioaddr = tp->mmio_addr;
4648 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4649 rtl8169_tx_interrupt(dev, tp, ioaddr);
4651 if (work_done < budget) {
4652 napi_complete(napi);
4654 /* We need for force the visibility of tp->intr_mask
4655 * for other CPUs, as we can loose an MSI interrupt
4656 * and potentially wait for a retransmit timeout if we don't.
4657 * The posted write to IntrMask is safe, as it will
4658 * eventually make it to the chip and we won't loose anything
4661 tp->intr_mask = 0xffff;
4663 RTL_W16(IntrMask, tp->intr_event);
4669 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4671 struct rtl8169_private *tp = netdev_priv(dev);
4673 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4676 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4677 RTL_W32(RxMissed, 0);
4680 static void rtl8169_down(struct net_device *dev)
4682 struct rtl8169_private *tp = netdev_priv(dev);
4683 void __iomem *ioaddr = tp->mmio_addr;
4684 unsigned int intrmask;
4686 rtl8169_delete_timer(dev);
4688 netif_stop_queue(dev);
4690 napi_disable(&tp->napi);
4693 spin_lock_irq(&tp->lock);
4695 rtl8169_asic_down(ioaddr);
4697 rtl8169_rx_missed(dev, ioaddr);
4699 spin_unlock_irq(&tp->lock);
4701 synchronize_irq(dev->irq);
4703 /* Give a racing hard_start_xmit a few cycles to complete. */
4704 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4707 * And now for the 50k$ question: are IRQ disabled or not ?
4709 * Two paths lead here:
4711 * -> netif_running() is available to sync the current code and the
4712 * IRQ handler. See rtl8169_interrupt for details.
4713 * 2) dev->change_mtu
4714 * -> rtl8169_poll can not be issued again and re-enable the
4715 * interruptions. Let's simply issue the IRQ down sequence again.
4717 * No loop if hotpluged or major error (0xffff).
4719 intrmask = RTL_R16(IntrMask);
4720 if (intrmask && (intrmask != 0xffff))
4723 rtl8169_tx_clear(tp);
4725 rtl8169_rx_clear(tp);
4728 static int rtl8169_close(struct net_device *dev)
4730 struct rtl8169_private *tp = netdev_priv(dev);
4731 struct pci_dev *pdev = tp->pci_dev;
4733 pm_runtime_get_sync(&pdev->dev);
4735 /* update counters before going down */
4736 rtl8169_update_counters(dev);
4740 free_irq(dev->irq, dev);
4742 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4744 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4746 tp->TxDescArray = NULL;
4747 tp->RxDescArray = NULL;
4749 pm_runtime_put_sync(&pdev->dev);
4754 static void rtl_set_rx_mode(struct net_device *dev)
4756 struct rtl8169_private *tp = netdev_priv(dev);
4757 void __iomem *ioaddr = tp->mmio_addr;
4758 unsigned long flags;
4759 u32 mc_filter[2]; /* Multicast hash filter */
4763 if (dev->flags & IFF_PROMISC) {
4764 /* Unconditionally log net taps. */
4765 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4767 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4769 mc_filter[1] = mc_filter[0] = 0xffffffff;
4770 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4771 (dev->flags & IFF_ALLMULTI)) {
4772 /* Too many to filter perfectly -- accept all multicasts. */
4773 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4774 mc_filter[1] = mc_filter[0] = 0xffffffff;
4776 struct dev_mc_list *mclist;
4778 rx_mode = AcceptBroadcast | AcceptMyPhys;
4779 mc_filter[1] = mc_filter[0] = 0;
4780 netdev_for_each_mc_addr(mclist, dev) {
4781 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4782 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4783 rx_mode |= AcceptMulticast;
4787 spin_lock_irqsave(&tp->lock, flags);
4789 tmp = rtl8169_rx_config | rx_mode |
4790 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4792 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4793 u32 data = mc_filter[0];
4795 mc_filter[0] = swab32(mc_filter[1]);
4796 mc_filter[1] = swab32(data);
4799 RTL_W32(MAR0 + 0, mc_filter[0]);
4800 RTL_W32(MAR0 + 4, mc_filter[1]);
4802 RTL_W32(RxConfig, tmp);
4804 spin_unlock_irqrestore(&tp->lock, flags);
4808 * rtl8169_get_stats - Get rtl8169 read/write statistics
4809 * @dev: The Ethernet Device to get statistics for
4811 * Get TX/RX statistics for rtl8169
4813 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4815 struct rtl8169_private *tp = netdev_priv(dev);
4816 void __iomem *ioaddr = tp->mmio_addr;
4817 unsigned long flags;
4819 if (netif_running(dev)) {
4820 spin_lock_irqsave(&tp->lock, flags);
4821 rtl8169_rx_missed(dev, ioaddr);
4822 spin_unlock_irqrestore(&tp->lock, flags);
4828 static void rtl8169_net_suspend(struct net_device *dev)
4830 if (!netif_running(dev))
4833 netif_device_detach(dev);
4834 netif_stop_queue(dev);
4839 static int rtl8169_suspend(struct device *device)
4841 struct pci_dev *pdev = to_pci_dev(device);
4842 struct net_device *dev = pci_get_drvdata(pdev);
4844 rtl8169_net_suspend(dev);
4849 static void __rtl8169_resume(struct net_device *dev)
4851 netif_device_attach(dev);
4852 rtl8169_schedule_work(dev, rtl8169_reset_task);
4855 static int rtl8169_resume(struct device *device)
4857 struct pci_dev *pdev = to_pci_dev(device);
4858 struct net_device *dev = pci_get_drvdata(pdev);
4860 if (netif_running(dev))
4861 __rtl8169_resume(dev);
4866 static int rtl8169_runtime_suspend(struct device *device)
4868 struct pci_dev *pdev = to_pci_dev(device);
4869 struct net_device *dev = pci_get_drvdata(pdev);
4870 struct rtl8169_private *tp = netdev_priv(dev);
4872 if (!tp->TxDescArray)
4875 spin_lock_irq(&tp->lock);
4876 tp->saved_wolopts = __rtl8169_get_wol(tp);
4877 __rtl8169_set_wol(tp, WAKE_ANY);
4878 spin_unlock_irq(&tp->lock);
4880 rtl8169_net_suspend(dev);
4885 static int rtl8169_runtime_resume(struct device *device)
4887 struct pci_dev *pdev = to_pci_dev(device);
4888 struct net_device *dev = pci_get_drvdata(pdev);
4889 struct rtl8169_private *tp = netdev_priv(dev);
4891 if (!tp->TxDescArray)
4894 spin_lock_irq(&tp->lock);
4895 __rtl8169_set_wol(tp, tp->saved_wolopts);
4896 tp->saved_wolopts = 0;
4897 spin_unlock_irq(&tp->lock);
4899 __rtl8169_resume(dev);
4904 static int rtl8169_runtime_idle(struct device *device)
4906 struct pci_dev *pdev = to_pci_dev(device);
4907 struct net_device *dev = pci_get_drvdata(pdev);
4908 struct rtl8169_private *tp = netdev_priv(dev);
4910 if (!tp->TxDescArray)
4913 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4917 static const struct dev_pm_ops rtl8169_pm_ops = {
4918 .suspend = rtl8169_suspend,
4919 .resume = rtl8169_resume,
4920 .freeze = rtl8169_suspend,
4921 .thaw = rtl8169_resume,
4922 .poweroff = rtl8169_suspend,
4923 .restore = rtl8169_resume,
4924 .runtime_suspend = rtl8169_runtime_suspend,
4925 .runtime_resume = rtl8169_runtime_resume,
4926 .runtime_idle = rtl8169_runtime_idle,
4929 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4931 #else /* !CONFIG_PM */
4933 #define RTL8169_PM_OPS NULL
4935 #endif /* !CONFIG_PM */
4937 static void rtl_shutdown(struct pci_dev *pdev)
4939 struct net_device *dev = pci_get_drvdata(pdev);
4940 struct rtl8169_private *tp = netdev_priv(dev);
4941 void __iomem *ioaddr = tp->mmio_addr;
4943 rtl8169_net_suspend(dev);
4945 /* restore original MAC address */
4946 rtl_rar_set(tp, dev->perm_addr);
4948 spin_lock_irq(&tp->lock);
4950 rtl8169_asic_down(ioaddr);
4952 spin_unlock_irq(&tp->lock);
4954 if (system_state == SYSTEM_POWER_OFF) {
4955 /* WoL fails with some 8168 when the receiver is disabled. */
4956 if (tp->features & RTL_FEATURE_WOL) {
4957 pci_clear_master(pdev);
4959 RTL_W8(ChipCmd, CmdRxEnb);
4964 pci_wake_from_d3(pdev, true);
4965 pci_set_power_state(pdev, PCI_D3hot);
4969 static struct pci_driver rtl8169_pci_driver = {
4971 .id_table = rtl8169_pci_tbl,
4972 .probe = rtl8169_init_one,
4973 .remove = __devexit_p(rtl8169_remove_one),
4974 .shutdown = rtl_shutdown,
4975 .driver.pm = RTL8169_PM_OPS,
4978 static int __init rtl8169_init_module(void)
4980 return pci_register_driver(&rtl8169_pci_driver);
4983 static void __exit rtl8169_cleanup_module(void)
4985 pci_unregister_driver(&rtl8169_pci_driver);
4988 module_init(rtl8169_init_module);
4989 module_exit(rtl8169_cleanup_module);