2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
34 #define NAPI_SUFFIX ""
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 #ifdef CONFIG_R8169_NAPI
60 #define rtl8169_rx_skb netif_receive_skb
61 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
62 #define rtl8169_rx_quota(count, quota) min(count, quota)
64 #define rtl8169_rx_skb netif_rx
65 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
66 #define rtl8169_rx_quota(count, quota) count
69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
70 static const int max_interrupt_work = 20;
72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
74 static const int multicast_filter_limit = 32;
76 /* MAC address length */
77 #define MAC_ADDR_LEN 6
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87 #define R8169_REGS_SIZE 256
88 #define R8169_NAPI_WEIGHT 64
89 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
92 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95 #define RTL8169_TX_TIMEOUT (6*HZ)
96 #define RTL8169_PHY_TIMEOUT (10*HZ)
98 /* write/read MMIO register */
99 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102 #define RTL_R8(reg) readb (ioaddr + (reg))
103 #define RTL_R16(reg) readw (ioaddr + (reg))
104 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
129 #define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
132 static const struct {
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136 } rtl_chip_info[] = {
137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
157 static void rtl_hw_start_8169(struct net_device *);
158 static void rtl_hw_start_8168(struct net_device *);
159 static void rtl_hw_start_8101(struct net_device *);
161 static struct pci_device_id rtl8169_pci_tbl[] = {
162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
177 static int rx_copybreak = 200;
184 MAC0 = 0, /* Ethernet hardware address. */
186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
227 enum rtl_register_content {
228 /* InterruptStatusBits */
232 TxDescUnavail = 0x0080,
254 /* TXPoll register p.5 */
255 HPQ = 0x80, /* Poll cmd on the high prio queue */
256 NPQ = 0x40, /* Poll cmd on the low prio queue */
257 FSWInt = 0x01, /* Forced software interrupt */
261 Cfg9346_Unlock = 0xc0,
266 AcceptBroadcast = 0x08,
267 AcceptMulticast = 0x04,
269 AcceptAllPhys = 0x01,
276 TxInterFrameGapShift = 24,
277 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
279 /* Config1 register p.24 */
280 PMEnable = (1 << 0), /* Power Management Enable */
282 /* Config2 register p. 25 */
283 PCI_Clock_66MHz = 0x01,
284 PCI_Clock_33MHz = 0x00,
286 /* Config3 register p.25 */
287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
290 /* Config5 register p.27 */
291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LanWake = (1 << 1), /* LanWake enable/disable */
295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
298 TBIReset = 0x80000000,
299 TBILoopback = 0x40000000,
300 TBINwEnable = 0x20000000,
301 TBINwRestart = 0x10000000,
302 TBILinkOk = 0x02000000,
303 TBINwComplete = 0x01000000,
306 PktCntrDisable = (1 << 7), // 8168
311 INTT_0 = 0x0000, // 8168
312 INTT_1 = 0x0001, // 8168
313 INTT_2 = 0x0002, // 8168
314 INTT_3 = 0x0003, // 8168
316 /* rtl8169_PHYstatus */
327 TBILinkOK = 0x02000000,
329 /* DumpCounterCommand */
333 enum desc_status_bit {
334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
335 RingEnd = (1 << 30), /* End of descriptor ring */
336 FirstFrag = (1 << 29), /* First segment of a packet */
337 LastFrag = (1 << 28), /* Final segment of a packet */
340 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
341 MSSShift = 16, /* MSS value position */
342 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
343 IPCS = (1 << 18), /* Calculate IP checksum */
344 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
345 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
346 TxVlanTag = (1 << 17), /* Add VLAN tag */
349 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
350 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
352 #define RxProtoUDP (PID1)
353 #define RxProtoTCP (PID0)
354 #define RxProtoIP (PID1 | PID0)
355 #define RxProtoMask RxProtoIP
357 IPFail = (1 << 16), /* IP checksum failed */
358 UDPFail = (1 << 15), /* UDP/IP checksum failed */
359 TCPFail = (1 << 14), /* TCP/IP checksum failed */
360 RxVlanTag = (1 << 16), /* VLAN tag available */
363 #define RsvdMask 0x3fffc000
380 u8 __pad[sizeof(void *) - sizeof(u32)];
383 struct rtl8169_private {
384 void __iomem *mmio_addr; /* memory map physical address */
385 struct pci_dev *pci_dev; /* Index of PCI device */
386 struct net_device *dev;
387 struct napi_struct napi;
388 struct net_device_stats stats; /* statistics of net device */
389 spinlock_t lock; /* spin lock flag */
394 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
395 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
398 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
399 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
400 dma_addr_t TxPhyAddr;
401 dma_addr_t RxPhyAddr;
402 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
403 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
406 struct timer_list timer;
411 int phy_auto_nego_reg;
412 int phy_1000_ctrl_reg;
413 #ifdef CONFIG_R8169_VLAN
414 struct vlan_group *vlgrp;
416 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
417 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
418 void (*phy_reset_enable)(void __iomem *);
419 void (*hw_start)(struct net_device *);
420 unsigned int (*phy_reset_pending)(void __iomem *);
421 unsigned int (*link_ok)(void __iomem *);
422 struct delayed_work task;
423 unsigned wol_enabled : 1;
426 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
427 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
428 module_param(rx_copybreak, int, 0);
429 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
430 module_param(use_dac, int, 0);
431 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
432 module_param_named(debug, debug.msg_enable, int, 0);
433 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
434 MODULE_LICENSE("GPL");
435 MODULE_VERSION(RTL8169_VERSION);
437 static int rtl8169_open(struct net_device *dev);
438 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
439 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
440 static int rtl8169_init_ring(struct net_device *dev);
441 static void rtl_hw_start(struct net_device *dev);
442 static int rtl8169_close(struct net_device *dev);
443 static void rtl_set_rx_mode(struct net_device *dev);
444 static void rtl8169_tx_timeout(struct net_device *dev);
445 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
446 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
447 void __iomem *, u32 budget);
448 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
449 static void rtl8169_down(struct net_device *dev);
450 static void rtl8169_rx_clear(struct rtl8169_private *tp);
452 #ifdef CONFIG_R8169_NAPI
453 static int rtl8169_poll(struct napi_struct *napi, int budget);
456 static const unsigned int rtl8169_rx_config =
457 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
459 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
463 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
465 for (i = 20; i > 0; i--) {
467 * Check if the RTL8169 has completed writing to the specified
470 if (!(RTL_R32(PHYAR) & 0x80000000))
476 static int mdio_read(void __iomem *ioaddr, int reg_addr)
480 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
482 for (i = 20; i > 0; i--) {
484 * Check if the RTL8169 has completed retrieving data from
485 * the specified MII register.
487 if (RTL_R32(PHYAR) & 0x80000000) {
488 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
496 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
498 RTL_W16(IntrMask, 0x0000);
500 RTL_W16(IntrStatus, 0xffff);
503 static void rtl8169_asic_down(void __iomem *ioaddr)
505 RTL_W8(ChipCmd, 0x00);
506 rtl8169_irq_mask_and_ack(ioaddr);
510 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
512 return RTL_R32(TBICSR) & TBIReset;
515 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
517 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
520 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
522 return RTL_R32(TBICSR) & TBILinkOk;
525 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
527 return RTL_R8(PHYstatus) & LinkStatus;
530 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
532 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
535 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
539 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
540 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
543 static void rtl8169_check_link_status(struct net_device *dev,
544 struct rtl8169_private *tp,
545 void __iomem *ioaddr)
549 spin_lock_irqsave(&tp->lock, flags);
550 if (tp->link_ok(ioaddr)) {
551 netif_carrier_on(dev);
552 if (netif_msg_ifup(tp))
553 printk(KERN_INFO PFX "%s: link up\n", dev->name);
555 if (netif_msg_ifdown(tp))
556 printk(KERN_INFO PFX "%s: link down\n", dev->name);
557 netif_carrier_off(dev);
559 spin_unlock_irqrestore(&tp->lock, flags);
562 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
564 struct rtl8169_private *tp = netdev_priv(dev);
565 void __iomem *ioaddr = tp->mmio_addr;
570 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
571 wol->supported = WAKE_ANY;
573 spin_lock_irq(&tp->lock);
575 options = RTL_R8(Config1);
576 if (!(options & PMEnable))
579 options = RTL_R8(Config3);
580 if (options & LinkUp)
581 wol->wolopts |= WAKE_PHY;
582 if (options & MagicPacket)
583 wol->wolopts |= WAKE_MAGIC;
585 options = RTL_R8(Config5);
587 wol->wolopts |= WAKE_UCAST;
589 wol->wolopts |= WAKE_BCAST;
591 wol->wolopts |= WAKE_MCAST;
594 spin_unlock_irq(&tp->lock);
597 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
599 struct rtl8169_private *tp = netdev_priv(dev);
600 void __iomem *ioaddr = tp->mmio_addr;
607 { WAKE_ANY, Config1, PMEnable },
608 { WAKE_PHY, Config3, LinkUp },
609 { WAKE_MAGIC, Config3, MagicPacket },
610 { WAKE_UCAST, Config5, UWF },
611 { WAKE_BCAST, Config5, BWF },
612 { WAKE_MCAST, Config5, MWF },
613 { WAKE_ANY, Config5, LanWake }
616 spin_lock_irq(&tp->lock);
618 RTL_W8(Cfg9346, Cfg9346_Unlock);
620 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
621 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
622 if (wol->wolopts & cfg[i].opt)
623 options |= cfg[i].mask;
624 RTL_W8(cfg[i].reg, options);
627 RTL_W8(Cfg9346, Cfg9346_Lock);
629 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
631 spin_unlock_irq(&tp->lock);
636 static void rtl8169_get_drvinfo(struct net_device *dev,
637 struct ethtool_drvinfo *info)
639 struct rtl8169_private *tp = netdev_priv(dev);
641 strcpy(info->driver, MODULENAME);
642 strcpy(info->version, RTL8169_VERSION);
643 strcpy(info->bus_info, pci_name(tp->pci_dev));
646 static int rtl8169_get_regs_len(struct net_device *dev)
648 return R8169_REGS_SIZE;
651 static int rtl8169_set_speed_tbi(struct net_device *dev,
652 u8 autoneg, u16 speed, u8 duplex)
654 struct rtl8169_private *tp = netdev_priv(dev);
655 void __iomem *ioaddr = tp->mmio_addr;
659 reg = RTL_R32(TBICSR);
660 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
661 (duplex == DUPLEX_FULL)) {
662 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
663 } else if (autoneg == AUTONEG_ENABLE)
664 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
666 if (netif_msg_link(tp)) {
667 printk(KERN_WARNING "%s: "
668 "incorrect speed setting refused in TBI mode\n",
677 static int rtl8169_set_speed_xmii(struct net_device *dev,
678 u8 autoneg, u16 speed, u8 duplex)
680 struct rtl8169_private *tp = netdev_priv(dev);
681 void __iomem *ioaddr = tp->mmio_addr;
682 int auto_nego, giga_ctrl;
684 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
685 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
686 ADVERTISE_100HALF | ADVERTISE_100FULL);
687 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
688 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
690 if (autoneg == AUTONEG_ENABLE) {
691 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
692 ADVERTISE_100HALF | ADVERTISE_100FULL);
693 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
695 if (speed == SPEED_10)
696 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
697 else if (speed == SPEED_100)
698 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
699 else if (speed == SPEED_1000)
700 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
702 if (duplex == DUPLEX_HALF)
703 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
705 if (duplex == DUPLEX_FULL)
706 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
708 /* This tweak comes straight from Realtek's driver. */
709 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
710 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
711 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
715 /* The 8100e/8101e do Fast Ethernet only. */
716 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
717 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
718 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
719 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
720 netif_msg_link(tp)) {
721 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
724 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
727 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
729 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
730 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
731 mdio_write(ioaddr, 0x1f, 0x0000);
732 mdio_write(ioaddr, 0x0e, 0x0000);
735 tp->phy_auto_nego_reg = auto_nego;
736 tp->phy_1000_ctrl_reg = giga_ctrl;
738 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
739 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
740 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
744 static int rtl8169_set_speed(struct net_device *dev,
745 u8 autoneg, u16 speed, u8 duplex)
747 struct rtl8169_private *tp = netdev_priv(dev);
750 ret = tp->set_speed(dev, autoneg, speed, duplex);
752 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
753 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
758 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
760 struct rtl8169_private *tp = netdev_priv(dev);
764 spin_lock_irqsave(&tp->lock, flags);
765 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
766 spin_unlock_irqrestore(&tp->lock, flags);
771 static u32 rtl8169_get_rx_csum(struct net_device *dev)
773 struct rtl8169_private *tp = netdev_priv(dev);
775 return tp->cp_cmd & RxChkSum;
778 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
780 struct rtl8169_private *tp = netdev_priv(dev);
781 void __iomem *ioaddr = tp->mmio_addr;
784 spin_lock_irqsave(&tp->lock, flags);
787 tp->cp_cmd |= RxChkSum;
789 tp->cp_cmd &= ~RxChkSum;
791 RTL_W16(CPlusCmd, tp->cp_cmd);
794 spin_unlock_irqrestore(&tp->lock, flags);
799 #ifdef CONFIG_R8169_VLAN
801 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
804 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
805 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
808 static void rtl8169_vlan_rx_register(struct net_device *dev,
809 struct vlan_group *grp)
811 struct rtl8169_private *tp = netdev_priv(dev);
812 void __iomem *ioaddr = tp->mmio_addr;
815 spin_lock_irqsave(&tp->lock, flags);
818 tp->cp_cmd |= RxVlan;
820 tp->cp_cmd &= ~RxVlan;
821 RTL_W16(CPlusCmd, tp->cp_cmd);
823 spin_unlock_irqrestore(&tp->lock, flags);
826 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
829 u32 opts2 = le32_to_cpu(desc->opts2);
832 if (tp->vlgrp && (opts2 & RxVlanTag)) {
833 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
841 #else /* !CONFIG_R8169_VLAN */
843 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
849 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
857 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
859 struct rtl8169_private *tp = netdev_priv(dev);
860 void __iomem *ioaddr = tp->mmio_addr;
864 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
865 cmd->port = PORT_FIBRE;
866 cmd->transceiver = XCVR_INTERNAL;
868 status = RTL_R32(TBICSR);
869 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
870 cmd->autoneg = !!(status & TBINwEnable);
872 cmd->speed = SPEED_1000;
873 cmd->duplex = DUPLEX_FULL; /* Always set */
876 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
878 struct rtl8169_private *tp = netdev_priv(dev);
879 void __iomem *ioaddr = tp->mmio_addr;
882 cmd->supported = SUPPORTED_10baseT_Half |
883 SUPPORTED_10baseT_Full |
884 SUPPORTED_100baseT_Half |
885 SUPPORTED_100baseT_Full |
886 SUPPORTED_1000baseT_Full |
891 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
893 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
894 cmd->advertising |= ADVERTISED_10baseT_Half;
895 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
896 cmd->advertising |= ADVERTISED_10baseT_Full;
897 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
898 cmd->advertising |= ADVERTISED_100baseT_Half;
899 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
900 cmd->advertising |= ADVERTISED_100baseT_Full;
901 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
902 cmd->advertising |= ADVERTISED_1000baseT_Full;
904 status = RTL_R8(PHYstatus);
906 if (status & _1000bpsF)
907 cmd->speed = SPEED_1000;
908 else if (status & _100bps)
909 cmd->speed = SPEED_100;
910 else if (status & _10bps)
911 cmd->speed = SPEED_10;
913 if (status & TxFlowCtrl)
914 cmd->advertising |= ADVERTISED_Asym_Pause;
915 if (status & RxFlowCtrl)
916 cmd->advertising |= ADVERTISED_Pause;
918 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
919 DUPLEX_FULL : DUPLEX_HALF;
922 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
924 struct rtl8169_private *tp = netdev_priv(dev);
927 spin_lock_irqsave(&tp->lock, flags);
929 tp->get_settings(dev, cmd);
931 spin_unlock_irqrestore(&tp->lock, flags);
935 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
938 struct rtl8169_private *tp = netdev_priv(dev);
941 if (regs->len > R8169_REGS_SIZE)
942 regs->len = R8169_REGS_SIZE;
944 spin_lock_irqsave(&tp->lock, flags);
945 memcpy_fromio(p, tp->mmio_addr, regs->len);
946 spin_unlock_irqrestore(&tp->lock, flags);
949 static u32 rtl8169_get_msglevel(struct net_device *dev)
951 struct rtl8169_private *tp = netdev_priv(dev);
953 return tp->msg_enable;
956 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
958 struct rtl8169_private *tp = netdev_priv(dev);
960 tp->msg_enable = value;
963 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
970 "tx_single_collisions",
971 "tx_multi_collisions",
979 struct rtl8169_counters {
986 u32 tx_one_collision;
987 u32 tx_multi_collision;
995 static int rtl8169_get_stats_count(struct net_device *dev)
997 return ARRAY_SIZE(rtl8169_gstrings);
1000 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1001 struct ethtool_stats *stats, u64 *data)
1003 struct rtl8169_private *tp = netdev_priv(dev);
1004 void __iomem *ioaddr = tp->mmio_addr;
1005 struct rtl8169_counters *counters;
1011 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1015 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1016 cmd = (u64)paddr & DMA_32BIT_MASK;
1017 RTL_W32(CounterAddrLow, cmd);
1018 RTL_W32(CounterAddrLow, cmd | CounterDump);
1020 while (RTL_R32(CounterAddrLow) & CounterDump) {
1021 if (msleep_interruptible(1))
1025 RTL_W32(CounterAddrLow, 0);
1026 RTL_W32(CounterAddrHigh, 0);
1028 data[0] = le64_to_cpu(counters->tx_packets);
1029 data[1] = le64_to_cpu(counters->rx_packets);
1030 data[2] = le64_to_cpu(counters->tx_errors);
1031 data[3] = le32_to_cpu(counters->rx_errors);
1032 data[4] = le16_to_cpu(counters->rx_missed);
1033 data[5] = le16_to_cpu(counters->align_errors);
1034 data[6] = le32_to_cpu(counters->tx_one_collision);
1035 data[7] = le32_to_cpu(counters->tx_multi_collision);
1036 data[8] = le64_to_cpu(counters->rx_unicast);
1037 data[9] = le64_to_cpu(counters->rx_broadcast);
1038 data[10] = le32_to_cpu(counters->rx_multicast);
1039 data[11] = le16_to_cpu(counters->tx_aborted);
1040 data[12] = le16_to_cpu(counters->tx_underun);
1042 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1045 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1049 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1054 static const struct ethtool_ops rtl8169_ethtool_ops = {
1055 .get_drvinfo = rtl8169_get_drvinfo,
1056 .get_regs_len = rtl8169_get_regs_len,
1057 .get_link = ethtool_op_get_link,
1058 .get_settings = rtl8169_get_settings,
1059 .set_settings = rtl8169_set_settings,
1060 .get_msglevel = rtl8169_get_msglevel,
1061 .set_msglevel = rtl8169_set_msglevel,
1062 .get_rx_csum = rtl8169_get_rx_csum,
1063 .set_rx_csum = rtl8169_set_rx_csum,
1064 .set_tx_csum = ethtool_op_set_tx_csum,
1065 .set_sg = ethtool_op_set_sg,
1066 .set_tso = ethtool_op_set_tso,
1067 .get_regs = rtl8169_get_regs,
1068 .get_wol = rtl8169_get_wol,
1069 .set_wol = rtl8169_set_wol,
1070 .get_strings = rtl8169_get_strings,
1071 .get_stats_count = rtl8169_get_stats_count,
1072 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1075 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1076 int bitnum, int bitval)
1080 val = mdio_read(ioaddr, reg);
1081 val = (bitval == 1) ?
1082 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1083 mdio_write(ioaddr, reg, val & 0xffff);
1086 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1087 void __iomem *ioaddr)
1090 * The driver currently handles the 8168Bf and the 8168Be identically
1091 * but they can be identified more specifically through the test below
1094 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1096 * Same thing for the 8101Eb and the 8101Ec:
1098 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1104 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1105 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1106 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1107 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1108 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1109 { 0x98000000, RTL_GIGA_MAC_VER_06 },
1110 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1111 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1112 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1113 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1114 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1118 reg = RTL_R32(TxConfig) & 0xfc800000;
1119 while ((reg & p->mask) != p->mask)
1121 tp->mac_version = p->mac_version;
1124 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1126 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1129 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1130 void __iomem *ioaddr)
1137 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1138 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1139 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1140 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1144 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1145 while ((reg & p->mask) != p->set)
1147 tp->phy_version = p->phy_version;
1150 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1157 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1158 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1159 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1160 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1164 for (p = phy_print; p->msg; p++) {
1165 if (tp->phy_version == p->version) {
1166 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1170 dprintk("phy_version == Unknown\n");
1173 static void rtl8169_hw_phy_config(struct net_device *dev)
1175 struct rtl8169_private *tp = netdev_priv(dev);
1176 void __iomem *ioaddr = tp->mmio_addr;
1178 u16 regs[5]; /* Beware of bit-sign propagation */
1179 } phy_magic[5] = { {
1180 { 0x0000, //w 4 15 12 0
1181 0x00a1, //w 3 15 0 00a1
1182 0x0008, //w 2 15 0 0008
1183 0x1020, //w 1 15 0 1020
1184 0x1000 } },{ //w 0 15 0 1000
1185 { 0x7000, //w 4 15 12 7
1186 0xff41, //w 3 15 0 ff41
1187 0xde60, //w 2 15 0 de60
1188 0x0140, //w 1 15 0 0140
1189 0x0077 } },{ //w 0 15 0 0077
1190 { 0xa000, //w 4 15 12 a
1191 0xdf01, //w 3 15 0 df01
1192 0xdf20, //w 2 15 0 df20
1193 0xff95, //w 1 15 0 ff95
1194 0xfa00 } },{ //w 0 15 0 fa00
1195 { 0xb000, //w 4 15 12 b
1196 0xff41, //w 3 15 0 ff41
1197 0xde20, //w 2 15 0 de20
1198 0x0140, //w 1 15 0 0140
1199 0x00bb } },{ //w 0 15 0 00bb
1200 { 0xf000, //w 4 15 12 f
1201 0xdf01, //w 3 15 0 df01
1202 0xdf20, //w 2 15 0 df20
1203 0xff95, //w 1 15 0 ff95
1204 0xbf00 } //w 0 15 0 bf00
1209 rtl8169_print_mac_version(tp);
1210 rtl8169_print_phy_version(tp);
1212 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1214 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1217 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1218 dprintk("Do final_reg2.cfg\n");
1222 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1223 mdio_write(ioaddr, 31, 0x0002);
1224 mdio_write(ioaddr, 1, 0x90d0);
1225 mdio_write(ioaddr, 31, 0x0000);
1229 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1230 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1233 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1234 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1235 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1236 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1238 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1241 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1242 mdio_write(ioaddr, pos, val);
1244 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1245 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1246 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1248 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1251 static void rtl8169_phy_timer(unsigned long __opaque)
1253 struct net_device *dev = (struct net_device *)__opaque;
1254 struct rtl8169_private *tp = netdev_priv(dev);
1255 struct timer_list *timer = &tp->timer;
1256 void __iomem *ioaddr = tp->mmio_addr;
1257 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1259 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1260 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1262 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1265 spin_lock_irq(&tp->lock);
1267 if (tp->phy_reset_pending(ioaddr)) {
1269 * A busy loop could burn quite a few cycles on nowadays CPU.
1270 * Let's delay the execution of the timer for a few ticks.
1276 if (tp->link_ok(ioaddr))
1279 if (netif_msg_link(tp))
1280 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1282 tp->phy_reset_enable(ioaddr);
1285 mod_timer(timer, jiffies + timeout);
1287 spin_unlock_irq(&tp->lock);
1290 static inline void rtl8169_delete_timer(struct net_device *dev)
1292 struct rtl8169_private *tp = netdev_priv(dev);
1293 struct timer_list *timer = &tp->timer;
1295 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1296 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1299 del_timer_sync(timer);
1302 static inline void rtl8169_request_timer(struct net_device *dev)
1304 struct rtl8169_private *tp = netdev_priv(dev);
1305 struct timer_list *timer = &tp->timer;
1307 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1308 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1311 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1314 #ifdef CONFIG_NET_POLL_CONTROLLER
1316 * Polling 'interrupt' - used by things like netconsole to send skbs
1317 * without having to re-enable interrupts. It's not called while
1318 * the interrupt routine is executing.
1320 static void rtl8169_netpoll(struct net_device *dev)
1322 struct rtl8169_private *tp = netdev_priv(dev);
1323 struct pci_dev *pdev = tp->pci_dev;
1325 disable_irq(pdev->irq);
1326 rtl8169_interrupt(pdev->irq, dev);
1327 enable_irq(pdev->irq);
1331 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1332 void __iomem *ioaddr)
1335 pci_release_regions(pdev);
1336 pci_disable_device(pdev);
1340 static void rtl8169_phy_reset(struct net_device *dev,
1341 struct rtl8169_private *tp)
1343 void __iomem *ioaddr = tp->mmio_addr;
1346 tp->phy_reset_enable(ioaddr);
1347 for (i = 0; i < 100; i++) {
1348 if (!tp->phy_reset_pending(ioaddr))
1352 if (netif_msg_link(tp))
1353 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1356 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1358 void __iomem *ioaddr = tp->mmio_addr;
1360 rtl8169_hw_phy_config(dev);
1362 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1365 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1367 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1368 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1370 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1371 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1373 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1374 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1377 rtl8169_phy_reset(dev, tp);
1380 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1381 * only 8101. Don't panic.
1383 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1385 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1386 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1389 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1391 void __iomem *ioaddr = tp->mmio_addr;
1395 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1396 high = addr[4] | (addr[5] << 8);
1398 spin_lock_irq(&tp->lock);
1400 RTL_W8(Cfg9346, Cfg9346_Unlock);
1402 RTL_W32(MAC4, high);
1403 RTL_W8(Cfg9346, Cfg9346_Lock);
1405 spin_unlock_irq(&tp->lock);
1408 static int rtl_set_mac_address(struct net_device *dev, void *p)
1410 struct rtl8169_private *tp = netdev_priv(dev);
1411 struct sockaddr *addr = p;
1413 if (!is_valid_ether_addr(addr->sa_data))
1414 return -EADDRNOTAVAIL;
1416 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1418 rtl_rar_set(tp, dev->dev_addr);
1423 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426 struct mii_ioctl_data *data = if_mii(ifr);
1428 if (!netif_running(dev))
1433 data->phy_id = 32; /* Internal PHY */
1437 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1441 if (!capable(CAP_NET_ADMIN))
1443 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1449 static const struct rtl_cfg_info {
1450 void (*hw_start)(struct net_device *);
1451 unsigned int region;
1455 } rtl_cfg_infos [] = {
1457 .hw_start = rtl_hw_start_8169,
1460 .intr_event = SYSErr | LinkChg | RxOverflow |
1461 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1462 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1465 .hw_start = rtl_hw_start_8168,
1468 .intr_event = SYSErr | LinkChg | RxOverflow |
1469 TxErr | TxOK | RxOK | RxErr,
1470 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1473 .hw_start = rtl_hw_start_8101,
1476 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1477 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1478 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1482 static int __devinit
1483 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1485 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1486 const unsigned int region = cfg->region;
1487 struct rtl8169_private *tp;
1488 struct net_device *dev;
1489 void __iomem *ioaddr;
1493 if (netif_msg_drv(&debug)) {
1494 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1495 MODULENAME, RTL8169_VERSION);
1498 dev = alloc_etherdev(sizeof (*tp));
1500 if (netif_msg_drv(&debug))
1501 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1506 SET_NETDEV_DEV(dev, &pdev->dev);
1507 tp = netdev_priv(dev);
1509 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1511 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1512 rc = pci_enable_device(pdev);
1514 if (netif_msg_probe(tp))
1515 dev_err(&pdev->dev, "enable failure\n");
1516 goto err_out_free_dev_1;
1519 rc = pci_set_mwi(pdev);
1521 goto err_out_disable_2;
1523 /* make sure PCI base addr 1 is MMIO */
1524 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1525 if (netif_msg_probe(tp)) {
1527 "region #%d not an MMIO resource, aborting\n",
1534 /* check for weird/broken PCI region reporting */
1535 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1536 if (netif_msg_probe(tp)) {
1538 "Invalid PCI region size(s), aborting\n");
1544 rc = pci_request_regions(pdev, MODULENAME);
1546 if (netif_msg_probe(tp))
1547 dev_err(&pdev->dev, "could not request regions.\n");
1551 tp->cp_cmd = PCIMulRW | RxChkSum;
1553 if ((sizeof(dma_addr_t) > 4) &&
1554 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1555 tp->cp_cmd |= PCIDAC;
1556 dev->features |= NETIF_F_HIGHDMA;
1558 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1560 if (netif_msg_probe(tp)) {
1562 "DMA configuration failed.\n");
1564 goto err_out_free_res_4;
1568 pci_set_master(pdev);
1570 /* ioremap MMIO region */
1571 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1573 if (netif_msg_probe(tp))
1574 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1576 goto err_out_free_res_4;
1579 /* Unneeded ? Don't mess with Mrs. Murphy. */
1580 rtl8169_irq_mask_and_ack(ioaddr);
1582 /* Soft reset the chip. */
1583 RTL_W8(ChipCmd, CmdReset);
1585 /* Check that the chip has finished the reset. */
1586 for (i = 0; i < 100; i++) {
1587 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1589 msleep_interruptible(1);
1592 /* Identify chip attached to board */
1593 rtl8169_get_mac_version(tp, ioaddr);
1594 rtl8169_get_phy_version(tp, ioaddr);
1596 rtl8169_print_mac_version(tp);
1597 rtl8169_print_phy_version(tp);
1599 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1600 if (tp->mac_version == rtl_chip_info[i].mac_version)
1604 /* Unknown chip: assume array element #0, original RTL-8169 */
1605 if (netif_msg_probe(tp)) {
1606 dev_printk(KERN_DEBUG, &pdev->dev,
1607 "unknown chip version, assuming %s\n",
1608 rtl_chip_info[0].name);
1614 RTL_W8(Cfg9346, Cfg9346_Unlock);
1615 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1616 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1617 RTL_W8(Cfg9346, Cfg9346_Lock);
1619 if (RTL_R8(PHYstatus) & TBI_Enable) {
1620 tp->set_speed = rtl8169_set_speed_tbi;
1621 tp->get_settings = rtl8169_gset_tbi;
1622 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1623 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1624 tp->link_ok = rtl8169_tbi_link_ok;
1626 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1628 tp->set_speed = rtl8169_set_speed_xmii;
1629 tp->get_settings = rtl8169_gset_xmii;
1630 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1631 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1632 tp->link_ok = rtl8169_xmii_link_ok;
1634 dev->do_ioctl = rtl8169_ioctl;
1637 /* Get MAC address. FIXME: read EEPROM */
1638 for (i = 0; i < MAC_ADDR_LEN; i++)
1639 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1640 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1642 dev->open = rtl8169_open;
1643 dev->hard_start_xmit = rtl8169_start_xmit;
1644 dev->get_stats = rtl8169_get_stats;
1645 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1646 dev->stop = rtl8169_close;
1647 dev->tx_timeout = rtl8169_tx_timeout;
1648 dev->set_multicast_list = rtl_set_rx_mode;
1649 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1650 dev->irq = pdev->irq;
1651 dev->base_addr = (unsigned long) ioaddr;
1652 dev->change_mtu = rtl8169_change_mtu;
1653 dev->set_mac_address = rtl_set_mac_address;
1655 #ifdef CONFIG_R8169_NAPI
1656 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1659 #ifdef CONFIG_R8169_VLAN
1660 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1661 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1664 #ifdef CONFIG_NET_POLL_CONTROLLER
1665 dev->poll_controller = rtl8169_netpoll;
1668 tp->intr_mask = 0xffff;
1670 tp->mmio_addr = ioaddr;
1671 tp->align = cfg->align;
1672 tp->hw_start = cfg->hw_start;
1673 tp->intr_event = cfg->intr_event;
1674 tp->napi_event = cfg->napi_event;
1676 init_timer(&tp->timer);
1677 tp->timer.data = (unsigned long) dev;
1678 tp->timer.function = rtl8169_phy_timer;
1680 spin_lock_init(&tp->lock);
1682 rc = register_netdev(dev);
1684 goto err_out_unmap_5;
1686 pci_set_drvdata(pdev, dev);
1688 if (netif_msg_probe(tp)) {
1689 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1691 printk(KERN_INFO "%s: %s at 0x%lx, "
1692 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1693 "XID %08x IRQ %d\n",
1695 rtl_chip_info[tp->chipset].name,
1697 dev->dev_addr[0], dev->dev_addr[1],
1698 dev->dev_addr[2], dev->dev_addr[3],
1699 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1702 rtl8169_init_phy(dev, tp);
1710 pci_release_regions(pdev);
1712 pci_clear_mwi(pdev);
1714 pci_disable_device(pdev);
1720 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1722 struct net_device *dev = pci_get_drvdata(pdev);
1723 struct rtl8169_private *tp = netdev_priv(dev);
1725 flush_scheduled_work();
1727 unregister_netdev(dev);
1728 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1729 pci_set_drvdata(pdev, NULL);
1732 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1733 struct net_device *dev)
1735 unsigned int mtu = dev->mtu;
1737 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1740 static int rtl8169_open(struct net_device *dev)
1742 struct rtl8169_private *tp = netdev_priv(dev);
1743 struct pci_dev *pdev = tp->pci_dev;
1744 int retval = -ENOMEM;
1747 rtl8169_set_rxbufsize(tp, dev);
1750 * Rx and Tx desscriptors needs 256 bytes alignment.
1751 * pci_alloc_consistent provides more.
1753 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1755 if (!tp->TxDescArray)
1758 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1760 if (!tp->RxDescArray)
1763 retval = rtl8169_init_ring(dev);
1767 INIT_DELAYED_WORK(&tp->task, NULL);
1771 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1774 goto err_release_ring_2;
1776 #ifdef CONFIG_R8169_NAPI
1777 napi_enable(&tp->napi);
1782 rtl8169_request_timer(dev);
1784 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1789 rtl8169_rx_clear(tp);
1791 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1794 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1799 static void rtl8169_hw_reset(void __iomem *ioaddr)
1801 /* Disable interrupts */
1802 rtl8169_irq_mask_and_ack(ioaddr);
1804 /* Reset the chipset */
1805 RTL_W8(ChipCmd, CmdReset);
1811 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1813 void __iomem *ioaddr = tp->mmio_addr;
1814 u32 cfg = rtl8169_rx_config;
1816 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1817 RTL_W32(RxConfig, cfg);
1819 /* Set DMA burst size and Interframe Gap Time */
1820 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1821 (InterFrameGap << TxInterFrameGapShift));
1824 static void rtl_hw_start(struct net_device *dev)
1826 struct rtl8169_private *tp = netdev_priv(dev);
1827 void __iomem *ioaddr = tp->mmio_addr;
1830 /* Soft reset the chip. */
1831 RTL_W8(ChipCmd, CmdReset);
1833 /* Check that the chip has finished the reset. */
1834 for (i = 0; i < 100; i++) {
1835 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1837 msleep_interruptible(1);
1842 netif_start_queue(dev);
1846 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1847 void __iomem *ioaddr)
1850 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1851 * register to be written before TxDescAddrLow to work.
1852 * Switching from MMIO to I/O access fixes the issue as well.
1854 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1855 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1856 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1857 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1860 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1864 cmd = RTL_R16(CPlusCmd);
1865 RTL_W16(CPlusCmd, cmd);
1869 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1871 /* Low hurts. Let's disable the filtering. */
1872 RTL_W16(RxMaxSize, 16383);
1875 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1882 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1883 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1884 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1885 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1890 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1891 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1892 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1893 RTL_W32(0x7c, p->val);
1899 static void rtl_hw_start_8169(struct net_device *dev)
1901 struct rtl8169_private *tp = netdev_priv(dev);
1902 void __iomem *ioaddr = tp->mmio_addr;
1903 struct pci_dev *pdev = tp->pci_dev;
1905 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1906 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1907 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1910 RTL_W8(Cfg9346, Cfg9346_Unlock);
1911 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1912 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1913 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1914 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1915 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1917 RTL_W8(EarlyTxThres, EarlyTxThld);
1919 rtl_set_rx_max_size(ioaddr);
1921 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1922 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1923 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1924 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1925 rtl_set_rx_tx_config_registers(tp);
1927 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1929 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1930 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1931 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1932 "Bit-3 and bit-14 MUST be 1\n");
1933 tp->cp_cmd |= (1 << 14);
1936 RTL_W16(CPlusCmd, tp->cp_cmd);
1938 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1941 * Undocumented corner. Supposedly:
1942 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1944 RTL_W16(IntrMitigate, 0x0000);
1946 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1948 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1949 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1950 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1951 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1952 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1953 rtl_set_rx_tx_config_registers(tp);
1956 RTL_W8(Cfg9346, Cfg9346_Lock);
1958 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1961 RTL_W32(RxMissed, 0);
1963 rtl_set_rx_mode(dev);
1965 /* no early-rx interrupts */
1966 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1968 /* Enable all known interrupts by setting the interrupt mask. */
1969 RTL_W16(IntrMask, tp->intr_event);
1972 static void rtl_hw_start_8168(struct net_device *dev)
1974 struct rtl8169_private *tp = netdev_priv(dev);
1975 void __iomem *ioaddr = tp->mmio_addr;
1976 struct pci_dev *pdev = tp->pci_dev;
1979 RTL_W8(Cfg9346, Cfg9346_Unlock);
1981 RTL_W8(EarlyTxThres, EarlyTxThld);
1983 rtl_set_rx_max_size(ioaddr);
1985 rtl_set_rx_tx_config_registers(tp);
1987 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1989 RTL_W16(CPlusCmd, tp->cp_cmd);
1991 /* Tx performance tweak. */
1992 pci_read_config_byte(pdev, 0x69, &ctl);
1993 ctl = (ctl & ~0x70) | 0x50;
1994 pci_write_config_byte(pdev, 0x69, ctl);
1996 RTL_W16(IntrMitigate, 0x5151);
1998 /* Work around for RxFIFO overflow. */
1999 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2000 tp->intr_event |= RxFIFOOver | PCSTimeout;
2001 tp->intr_event &= ~RxOverflow;
2004 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2006 RTL_W8(Cfg9346, Cfg9346_Lock);
2010 RTL_W32(RxMissed, 0);
2012 rtl_set_rx_mode(dev);
2014 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2016 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2018 RTL_W16(IntrMask, tp->intr_event);
2021 static void rtl_hw_start_8101(struct net_device *dev)
2023 struct rtl8169_private *tp = netdev_priv(dev);
2024 void __iomem *ioaddr = tp->mmio_addr;
2025 struct pci_dev *pdev = tp->pci_dev;
2027 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2028 pci_write_config_word(pdev, 0x68, 0x00);
2029 pci_write_config_word(pdev, 0x69, 0x08);
2032 RTL_W8(Cfg9346, Cfg9346_Unlock);
2034 RTL_W8(EarlyTxThres, EarlyTxThld);
2036 rtl_set_rx_max_size(ioaddr);
2038 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2040 RTL_W16(CPlusCmd, tp->cp_cmd);
2042 RTL_W16(IntrMitigate, 0x0000);
2044 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2046 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2047 rtl_set_rx_tx_config_registers(tp);
2049 RTL_W8(Cfg9346, Cfg9346_Lock);
2053 RTL_W32(RxMissed, 0);
2055 rtl_set_rx_mode(dev);
2057 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2059 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2061 RTL_W16(IntrMask, tp->intr_event);
2064 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2066 struct rtl8169_private *tp = netdev_priv(dev);
2069 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2074 if (!netif_running(dev))
2079 rtl8169_set_rxbufsize(tp, dev);
2081 ret = rtl8169_init_ring(dev);
2085 #ifdef CONFIG_R8169_NAPI
2086 napi_enable(&tp->napi);
2091 rtl8169_request_timer(dev);
2097 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2099 desc->addr = 0x0badbadbadbadbadull;
2100 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2103 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2104 struct sk_buff **sk_buff, struct RxDesc *desc)
2106 struct pci_dev *pdev = tp->pci_dev;
2108 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2109 PCI_DMA_FROMDEVICE);
2110 dev_kfree_skb(*sk_buff);
2112 rtl8169_make_unusable_by_asic(desc);
2115 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2117 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2119 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2122 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2125 desc->addr = cpu_to_le64(mapping);
2127 rtl8169_mark_to_asic(desc, rx_buf_sz);
2130 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2131 struct net_device *dev,
2132 struct RxDesc *desc, int rx_buf_sz,
2135 struct sk_buff *skb;
2139 pad = align ? align : NET_IP_ALIGN;
2141 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2145 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2147 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2148 PCI_DMA_FROMDEVICE);
2150 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2155 rtl8169_make_unusable_by_asic(desc);
2159 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2163 for (i = 0; i < NUM_RX_DESC; i++) {
2164 if (tp->Rx_skbuff[i]) {
2165 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2166 tp->RxDescArray + i);
2171 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2176 for (cur = start; end - cur != 0; cur++) {
2177 struct sk_buff *skb;
2178 unsigned int i = cur % NUM_RX_DESC;
2180 WARN_ON((s32)(end - cur) < 0);
2182 if (tp->Rx_skbuff[i])
2185 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2186 tp->RxDescArray + i,
2187 tp->rx_buf_sz, tp->align);
2191 tp->Rx_skbuff[i] = skb;
2196 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2198 desc->opts1 |= cpu_to_le32(RingEnd);
2201 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2203 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2206 static int rtl8169_init_ring(struct net_device *dev)
2208 struct rtl8169_private *tp = netdev_priv(dev);
2210 rtl8169_init_ring_indexes(tp);
2212 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2213 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2215 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2218 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2223 rtl8169_rx_clear(tp);
2227 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2228 struct TxDesc *desc)
2230 unsigned int len = tx_skb->len;
2232 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2239 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2243 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2244 unsigned int entry = i % NUM_TX_DESC;
2245 struct ring_info *tx_skb = tp->tx_skb + entry;
2246 unsigned int len = tx_skb->len;
2249 struct sk_buff *skb = tx_skb->skb;
2251 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2252 tp->TxDescArray + entry);
2257 tp->stats.tx_dropped++;
2260 tp->cur_tx = tp->dirty_tx = 0;
2263 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2265 struct rtl8169_private *tp = netdev_priv(dev);
2267 PREPARE_DELAYED_WORK(&tp->task, task);
2268 schedule_delayed_work(&tp->task, 4);
2271 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2273 struct rtl8169_private *tp = netdev_priv(dev);
2274 void __iomem *ioaddr = tp->mmio_addr;
2276 synchronize_irq(dev->irq);
2278 /* Wait for any pending NAPI task to complete */
2279 #ifdef CONFIG_R8169_NAPI
2280 napi_disable(&tp->napi);
2283 rtl8169_irq_mask_and_ack(ioaddr);
2285 #ifdef CONFIG_R8169_NAPI
2286 napi_enable(&tp->napi);
2290 static void rtl8169_reinit_task(struct work_struct *work)
2292 struct rtl8169_private *tp =
2293 container_of(work, struct rtl8169_private, task.work);
2294 struct net_device *dev = tp->dev;
2299 if (!netif_running(dev))
2302 rtl8169_wait_for_quiescence(dev);
2305 ret = rtl8169_open(dev);
2306 if (unlikely(ret < 0)) {
2307 if (net_ratelimit() && netif_msg_drv(tp)) {
2308 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2309 " Rescheduling.\n", dev->name, ret);
2311 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2318 static void rtl8169_reset_task(struct work_struct *work)
2320 struct rtl8169_private *tp =
2321 container_of(work, struct rtl8169_private, task.work);
2322 struct net_device *dev = tp->dev;
2326 if (!netif_running(dev))
2329 rtl8169_wait_for_quiescence(dev);
2331 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2332 rtl8169_tx_clear(tp);
2334 if (tp->dirty_rx == tp->cur_rx) {
2335 rtl8169_init_ring_indexes(tp);
2337 netif_wake_queue(dev);
2339 if (net_ratelimit() && netif_msg_intr(tp)) {
2340 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2343 rtl8169_schedule_work(dev, rtl8169_reset_task);
2350 static void rtl8169_tx_timeout(struct net_device *dev)
2352 struct rtl8169_private *tp = netdev_priv(dev);
2354 rtl8169_hw_reset(tp->mmio_addr);
2356 /* Let's wait a bit while any (async) irq lands on */
2357 rtl8169_schedule_work(dev, rtl8169_reset_task);
2360 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2363 struct skb_shared_info *info = skb_shinfo(skb);
2364 unsigned int cur_frag, entry;
2365 struct TxDesc * uninitialized_var(txd);
2368 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2369 skb_frag_t *frag = info->frags + cur_frag;
2374 entry = (entry + 1) % NUM_TX_DESC;
2376 txd = tp->TxDescArray + entry;
2378 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2379 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2381 /* anti gcc 2.95.3 bugware (sic) */
2382 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2384 txd->opts1 = cpu_to_le32(status);
2385 txd->addr = cpu_to_le64(mapping);
2387 tp->tx_skb[entry].len = len;
2391 tp->tx_skb[entry].skb = skb;
2392 txd->opts1 |= cpu_to_le32(LastFrag);
2398 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2400 if (dev->features & NETIF_F_TSO) {
2401 u32 mss = skb_shinfo(skb)->gso_size;
2404 return LargeSend | ((mss & MSSMask) << MSSShift);
2406 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2407 const struct iphdr *ip = ip_hdr(skb);
2409 if (ip->protocol == IPPROTO_TCP)
2410 return IPCS | TCPCS;
2411 else if (ip->protocol == IPPROTO_UDP)
2412 return IPCS | UDPCS;
2413 WARN_ON(1); /* we need a WARN() */
2418 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2420 struct rtl8169_private *tp = netdev_priv(dev);
2421 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2422 struct TxDesc *txd = tp->TxDescArray + entry;
2423 void __iomem *ioaddr = tp->mmio_addr;
2427 int ret = NETDEV_TX_OK;
2429 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2430 if (netif_msg_drv(tp)) {
2432 "%s: BUG! Tx Ring full when queue awake!\n",
2438 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2441 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2443 frags = rtl8169_xmit_frags(tp, skb, opts1);
2445 len = skb_headlen(skb);
2450 if (unlikely(len < ETH_ZLEN)) {
2451 if (skb_padto(skb, ETH_ZLEN))
2452 goto err_update_stats;
2456 opts1 |= FirstFrag | LastFrag;
2457 tp->tx_skb[entry].skb = skb;
2460 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2462 tp->tx_skb[entry].len = len;
2463 txd->addr = cpu_to_le64(mapping);
2464 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2468 /* anti gcc 2.95.3 bugware (sic) */
2469 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2470 txd->opts1 = cpu_to_le32(status);
2472 dev->trans_start = jiffies;
2474 tp->cur_tx += frags + 1;
2478 RTL_W8(TxPoll, NPQ); /* set polling bit */
2480 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2481 netif_stop_queue(dev);
2483 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2484 netif_wake_queue(dev);
2491 netif_stop_queue(dev);
2492 ret = NETDEV_TX_BUSY;
2494 tp->stats.tx_dropped++;
2498 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2500 struct rtl8169_private *tp = netdev_priv(dev);
2501 struct pci_dev *pdev = tp->pci_dev;
2502 void __iomem *ioaddr = tp->mmio_addr;
2503 u16 pci_status, pci_cmd;
2505 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2506 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2508 if (netif_msg_intr(tp)) {
2510 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2511 dev->name, pci_cmd, pci_status);
2515 * The recovery sequence below admits a very elaborated explanation:
2516 * - it seems to work;
2517 * - I did not see what else could be done;
2518 * - it makes iop3xx happy.
2520 * Feel free to adjust to your needs.
2522 if (pdev->broken_parity_status)
2523 pci_cmd &= ~PCI_COMMAND_PARITY;
2525 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2527 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2529 pci_write_config_word(pdev, PCI_STATUS,
2530 pci_status & (PCI_STATUS_DETECTED_PARITY |
2531 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2532 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2534 /* The infamous DAC f*ckup only happens at boot time */
2535 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2536 if (netif_msg_intr(tp))
2537 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2538 tp->cp_cmd &= ~PCIDAC;
2539 RTL_W16(CPlusCmd, tp->cp_cmd);
2540 dev->features &= ~NETIF_F_HIGHDMA;
2543 rtl8169_hw_reset(ioaddr);
2545 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2548 static void rtl8169_tx_interrupt(struct net_device *dev,
2549 struct rtl8169_private *tp,
2550 void __iomem *ioaddr)
2552 unsigned int dirty_tx, tx_left;
2554 dirty_tx = tp->dirty_tx;
2556 tx_left = tp->cur_tx - dirty_tx;
2558 while (tx_left > 0) {
2559 unsigned int entry = dirty_tx % NUM_TX_DESC;
2560 struct ring_info *tx_skb = tp->tx_skb + entry;
2561 u32 len = tx_skb->len;
2565 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2566 if (status & DescOwn)
2569 tp->stats.tx_bytes += len;
2570 tp->stats.tx_packets++;
2572 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2574 if (status & LastFrag) {
2575 dev_kfree_skb_irq(tx_skb->skb);
2582 if (tp->dirty_tx != dirty_tx) {
2583 tp->dirty_tx = dirty_tx;
2585 if (netif_queue_stopped(dev) &&
2586 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2587 netif_wake_queue(dev);
2590 * 8168 hack: TxPoll requests are lost when the Tx packets are
2591 * too close. Let's kick an extra TxPoll request when a burst
2592 * of start_xmit activity is detected (if it is not detected,
2593 * it is slow enough). -- FR
2596 if (tp->cur_tx != dirty_tx)
2597 RTL_W8(TxPoll, NPQ);
2601 static inline int rtl8169_fragmented_frame(u32 status)
2603 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2606 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2608 u32 opts1 = le32_to_cpu(desc->opts1);
2609 u32 status = opts1 & RxProtoMask;
2611 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2612 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2613 ((status == RxProtoIP) && !(opts1 & IPFail)))
2614 skb->ip_summed = CHECKSUM_UNNECESSARY;
2616 skb->ip_summed = CHECKSUM_NONE;
2619 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2620 struct rtl8169_private *tp, int pkt_size,
2623 struct sk_buff *skb;
2626 if (pkt_size >= rx_copybreak)
2629 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2633 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2634 PCI_DMA_FROMDEVICE);
2635 skb_reserve(skb, NET_IP_ALIGN);
2636 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2643 static int rtl8169_rx_interrupt(struct net_device *dev,
2644 struct rtl8169_private *tp,
2645 void __iomem *ioaddr, u32 budget)
2647 unsigned int cur_rx, rx_left;
2648 unsigned int delta, count;
2650 cur_rx = tp->cur_rx;
2651 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2652 rx_left = rtl8169_rx_quota(rx_left, budget);
2654 for (; rx_left > 0; rx_left--, cur_rx++) {
2655 unsigned int entry = cur_rx % NUM_RX_DESC;
2656 struct RxDesc *desc = tp->RxDescArray + entry;
2660 status = le32_to_cpu(desc->opts1);
2662 if (status & DescOwn)
2664 if (unlikely(status & RxRES)) {
2665 if (netif_msg_rx_err(tp)) {
2667 "%s: Rx ERROR. status = %08x\n",
2670 tp->stats.rx_errors++;
2671 if (status & (RxRWT | RxRUNT))
2672 tp->stats.rx_length_errors++;
2674 tp->stats.rx_crc_errors++;
2675 if (status & RxFOVF) {
2676 rtl8169_schedule_work(dev, rtl8169_reset_task);
2677 tp->stats.rx_fifo_errors++;
2679 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2681 struct sk_buff *skb = tp->Rx_skbuff[entry];
2682 dma_addr_t addr = le64_to_cpu(desc->addr);
2683 int pkt_size = (status & 0x00001FFF) - 4;
2684 struct pci_dev *pdev = tp->pci_dev;
2687 * The driver does not support incoming fragmented
2688 * frames. They are seen as a symptom of over-mtu
2691 if (unlikely(rtl8169_fragmented_frame(status))) {
2692 tp->stats.rx_dropped++;
2693 tp->stats.rx_length_errors++;
2694 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2698 rtl8169_rx_csum(skb, desc);
2700 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2701 pci_dma_sync_single_for_device(pdev, addr,
2702 pkt_size, PCI_DMA_FROMDEVICE);
2703 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2705 pci_unmap_single(pdev, addr, pkt_size,
2706 PCI_DMA_FROMDEVICE);
2707 tp->Rx_skbuff[entry] = NULL;
2710 skb_put(skb, pkt_size);
2711 skb->protocol = eth_type_trans(skb, dev);
2713 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2714 rtl8169_rx_skb(skb);
2716 dev->last_rx = jiffies;
2717 tp->stats.rx_bytes += pkt_size;
2718 tp->stats.rx_packets++;
2721 /* Work around for AMD plateform. */
2722 if ((desc->opts2 & 0xfffe000) &&
2723 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2729 count = cur_rx - tp->cur_rx;
2730 tp->cur_rx = cur_rx;
2732 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2733 if (!delta && count && netif_msg_intr(tp))
2734 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2735 tp->dirty_rx += delta;
2738 * FIXME: until there is periodic timer to try and refill the ring,
2739 * a temporary shortage may definitely kill the Rx process.
2740 * - disable the asic to try and avoid an overflow and kick it again
2742 * - how do others driver handle this condition (Uh oh...).
2744 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2745 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2750 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2752 struct net_device *dev = dev_instance;
2753 struct rtl8169_private *tp = netdev_priv(dev);
2754 int boguscnt = max_interrupt_work;
2755 void __iomem *ioaddr = tp->mmio_addr;
2760 status = RTL_R16(IntrStatus);
2762 /* hotplug/major error/no more work/shared irq */
2763 if ((status == 0xFFFF) || !status)
2768 if (unlikely(!netif_running(dev))) {
2769 rtl8169_asic_down(ioaddr);
2773 status &= tp->intr_mask;
2775 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2777 if (!(status & tp->intr_event))
2780 /* Work around for rx fifo overflow */
2781 if (unlikely(status & RxFIFOOver) &&
2782 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2783 netif_stop_queue(dev);
2784 rtl8169_tx_timeout(dev);
2788 if (unlikely(status & SYSErr)) {
2789 rtl8169_pcierr_interrupt(dev);
2793 if (status & LinkChg)
2794 rtl8169_check_link_status(dev, tp, ioaddr);
2796 #ifdef CONFIG_R8169_NAPI
2797 if (status & tp->napi_event) {
2798 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2799 tp->intr_mask = ~tp->napi_event;
2801 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2802 __netif_rx_schedule(dev, &tp->napi);
2803 else if (netif_msg_intr(tp)) {
2804 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2811 if (status & (RxOK | RxOverflow | RxFIFOOver))
2812 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2815 if (status & (TxOK | TxErr))
2816 rtl8169_tx_interrupt(dev, tp, ioaddr);
2820 } while (boguscnt > 0);
2822 if (boguscnt <= 0) {
2823 if (netif_msg_intr(tp) && net_ratelimit() ) {
2825 "%s: Too much work at interrupt!\n", dev->name);
2827 /* Clear all interrupt sources. */
2828 RTL_W16(IntrStatus, 0xffff);
2831 return IRQ_RETVAL(handled);
2834 #ifdef CONFIG_R8169_NAPI
2835 static int rtl8169_poll(struct napi_struct *napi, int budget)
2837 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2838 struct net_device *dev = tp->dev;
2839 void __iomem *ioaddr = tp->mmio_addr;
2842 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2843 rtl8169_tx_interrupt(dev, tp, ioaddr);
2845 if (work_done < budget) {
2846 netif_rx_complete(dev, napi);
2847 tp->intr_mask = 0xffff;
2849 * 20040426: the barrier is not strictly required but the
2850 * behavior of the irq handler could be less predictable
2851 * without it. Btw, the lack of flush for the posted pci
2852 * write is safe - FR
2855 RTL_W16(IntrMask, tp->intr_event);
2862 static void rtl8169_down(struct net_device *dev)
2864 struct rtl8169_private *tp = netdev_priv(dev);
2865 void __iomem *ioaddr = tp->mmio_addr;
2866 unsigned int poll_locked = 0;
2867 unsigned int intrmask;
2869 rtl8169_delete_timer(dev);
2871 netif_stop_queue(dev);
2874 spin_lock_irq(&tp->lock);
2876 rtl8169_asic_down(ioaddr);
2878 /* Update the error counts. */
2879 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2880 RTL_W32(RxMissed, 0);
2882 spin_unlock_irq(&tp->lock);
2884 synchronize_irq(dev->irq);
2887 napi_disable(&tp->napi);
2891 /* Give a racing hard_start_xmit a few cycles to complete. */
2892 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2895 * And now for the 50k$ question: are IRQ disabled or not ?
2897 * Two paths lead here:
2899 * -> netif_running() is available to sync the current code and the
2900 * IRQ handler. See rtl8169_interrupt for details.
2901 * 2) dev->change_mtu
2902 * -> rtl8169_poll can not be issued again and re-enable the
2903 * interruptions. Let's simply issue the IRQ down sequence again.
2905 * No loop if hotpluged or major error (0xffff).
2907 intrmask = RTL_R16(IntrMask);
2908 if (intrmask && (intrmask != 0xffff))
2911 rtl8169_tx_clear(tp);
2913 rtl8169_rx_clear(tp);
2916 static int rtl8169_close(struct net_device *dev)
2918 struct rtl8169_private *tp = netdev_priv(dev);
2919 struct pci_dev *pdev = tp->pci_dev;
2923 free_irq(dev->irq, dev);
2925 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2927 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2929 tp->TxDescArray = NULL;
2930 tp->RxDescArray = NULL;
2935 static void rtl_set_rx_mode(struct net_device *dev)
2937 struct rtl8169_private *tp = netdev_priv(dev);
2938 void __iomem *ioaddr = tp->mmio_addr;
2939 unsigned long flags;
2940 u32 mc_filter[2]; /* Multicast hash filter */
2944 if (dev->flags & IFF_PROMISC) {
2945 /* Unconditionally log net taps. */
2946 if (netif_msg_link(tp)) {
2947 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2951 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2953 mc_filter[1] = mc_filter[0] = 0xffffffff;
2954 } else if ((dev->mc_count > multicast_filter_limit)
2955 || (dev->flags & IFF_ALLMULTI)) {
2956 /* Too many to filter perfectly -- accept all multicasts. */
2957 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2958 mc_filter[1] = mc_filter[0] = 0xffffffff;
2960 struct dev_mc_list *mclist;
2963 rx_mode = AcceptBroadcast | AcceptMyPhys;
2964 mc_filter[1] = mc_filter[0] = 0;
2965 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2966 i++, mclist = mclist->next) {
2967 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2968 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2969 rx_mode |= AcceptMulticast;
2973 spin_lock_irqsave(&tp->lock, flags);
2975 tmp = rtl8169_rx_config | rx_mode |
2976 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2978 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2979 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2980 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2981 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2982 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2983 mc_filter[0] = 0xffffffff;
2984 mc_filter[1] = 0xffffffff;
2987 RTL_W32(MAR0 + 0, mc_filter[0]);
2988 RTL_W32(MAR0 + 4, mc_filter[1]);
2990 RTL_W32(RxConfig, tmp);
2992 spin_unlock_irqrestore(&tp->lock, flags);
2996 * rtl8169_get_stats - Get rtl8169 read/write statistics
2997 * @dev: The Ethernet Device to get statistics for
2999 * Get TX/RX statistics for rtl8169
3001 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3003 struct rtl8169_private *tp = netdev_priv(dev);
3004 void __iomem *ioaddr = tp->mmio_addr;
3005 unsigned long flags;
3007 if (netif_running(dev)) {
3008 spin_lock_irqsave(&tp->lock, flags);
3009 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3010 RTL_W32(RxMissed, 0);
3011 spin_unlock_irqrestore(&tp->lock, flags);
3019 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3021 struct net_device *dev = pci_get_drvdata(pdev);
3022 struct rtl8169_private *tp = netdev_priv(dev);
3023 void __iomem *ioaddr = tp->mmio_addr;
3025 if (!netif_running(dev))
3026 goto out_pci_suspend;
3028 netif_device_detach(dev);
3029 netif_stop_queue(dev);
3031 spin_lock_irq(&tp->lock);
3033 rtl8169_asic_down(ioaddr);
3035 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3036 RTL_W32(RxMissed, 0);
3038 spin_unlock_irq(&tp->lock);
3041 pci_save_state(pdev);
3042 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3043 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3048 static int rtl8169_resume(struct pci_dev *pdev)
3050 struct net_device *dev = pci_get_drvdata(pdev);
3052 pci_set_power_state(pdev, PCI_D0);
3053 pci_restore_state(pdev);
3054 pci_enable_wake(pdev, PCI_D0, 0);
3056 if (!netif_running(dev))
3059 netif_device_attach(dev);
3061 rtl8169_schedule_work(dev, rtl8169_reset_task);
3066 #endif /* CONFIG_PM */
3068 static struct pci_driver rtl8169_pci_driver = {
3070 .id_table = rtl8169_pci_tbl,
3071 .probe = rtl8169_init_one,
3072 .remove = __devexit_p(rtl8169_remove_one),
3074 .suspend = rtl8169_suspend,
3075 .resume = rtl8169_resume,
3079 static int __init rtl8169_init_module(void)
3081 return pci_register_driver(&rtl8169_pci_driver);
3084 static void __exit rtl8169_cleanup_module(void)
3086 pci_unregister_driver(&rtl8169_pci_driver);
3089 module_init(rtl8169_init_module);
3090 module_exit(rtl8169_cleanup_module);