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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...)   do { printk(PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 #ifdef CONFIG_R8169_NAPI
  60 #define rtl8169_rx_skb                  netif_receive_skb
  61 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  62 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  63 #else
  64 #define rtl8169_rx_skb                  netif_rx
  65 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  66 #define rtl8169_rx_quota(count, quota)  count
  67 #endif
  68
  69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  70 static const int max_interrupt_work = 20;
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  80 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  83 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  84 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  85 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  86
  87 #define R8169_REGS_SIZE         256
  88 #define R8169_NAPI_WEIGHT       64
  89 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  90 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  91 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  92 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  93 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  94
  95 #define RTL8169_TX_TIMEOUT      (6*HZ)
  96 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  97
  98 /* write/read MMIO register */
  99 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb (ioaddr + (reg))
 103 #define RTL_R16(reg)            readw (ioaddr + (reg))
 104 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 105
 106 enum mac_version {
 107         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 108         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 109         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 110         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 111         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 112         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 113         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 114         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 115         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 116         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 117         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 118 };
 119
 120 enum phy_version {
 121         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 122         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 123         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 124         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 125         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 126         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 127 };
 128
 129 #define _R(NAME,MAC,MASK) \
 130         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 131
 132 static const struct {
 133         const char *name;
 134         u8 mac_version;
 135         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 136 } rtl_chip_info[] = {
 137         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 138         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 139         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 140         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 148 };
 149 #undef _R
 150
 151 enum cfg_version {
 152         RTL_CFG_0 = 0x00,
 153         RTL_CFG_1,
 154         RTL_CFG_2
 155 };
 156
 157 static void rtl_hw_start_8169(struct net_device *);
 158 static void rtl_hw_start_8168(struct net_device *);
 159 static void rtl_hw_start_8101(struct net_device *);
 160
 161 static struct pci_device_id rtl8169_pci_tbl[] = {
 162         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 163         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 170         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 171                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 172         {0,},
 173 };
 174
 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 176
 177 static int rx_copybreak = 200;
 178 static int use_dac;
 179 static struct {
 180         u32 msg_enable;
 181 } debug = { -1 };
 182
 183 enum rtl_registers {
 184         MAC0            = 0,    /* Ethernet hardware address. */
 185         MAC4            = 4,
 186         MAR0            = 8,    /* Multicast filter. */
 187         CounterAddrLow          = 0x10,
 188         CounterAddrHigh         = 0x14,
 189         TxDescStartAddrLow      = 0x20,
 190         TxDescStartAddrHigh     = 0x24,
 191         TxHDescStartAddrLow     = 0x28,
 192         TxHDescStartAddrHigh    = 0x2c,
 193         FLASH           = 0x30,
 194         ERSR            = 0x36,
 195         ChipCmd         = 0x37,
 196         TxPoll          = 0x38,
 197         IntrMask        = 0x3c,
 198         IntrStatus      = 0x3e,
 199         TxConfig        = 0x40,
 200         RxConfig        = 0x44,
 201         RxMissed        = 0x4c,
 202         Cfg9346         = 0x50,
 203         Config0         = 0x51,
 204         Config1         = 0x52,
 205         Config2         = 0x53,
 206         Config3         = 0x54,
 207         Config4         = 0x55,
 208         Config5         = 0x56,
 209         MultiIntr       = 0x5c,
 210         PHYAR           = 0x60,
 211         TBICSR          = 0x64,
 212         TBI_ANAR        = 0x68,
 213         TBI_LPAR        = 0x6a,
 214         PHYstatus       = 0x6c,
 215         RxMaxSize       = 0xda,
 216         CPlusCmd        = 0xe0,
 217         IntrMitigate    = 0xe2,
 218         RxDescAddrLow   = 0xe4,
 219         RxDescAddrHigh  = 0xe8,
 220         EarlyTxThres    = 0xec,
 221         FuncEvent       = 0xf0,
 222         FuncEventMask   = 0xf4,
 223         FuncPresetState = 0xf8,
 224         FuncForceEvent  = 0xfc,
 225 };
 226
 227 enum rtl_register_content {
 228         /* InterruptStatusBits */
 229         SYSErr          = 0x8000,
 230         PCSTimeout      = 0x4000,
 231         SWInt           = 0x0100,
 232         TxDescUnavail   = 0x0080,
 233         RxFIFOOver      = 0x0040,
 234         LinkChg         = 0x0020,
 235         RxOverflow      = 0x0010,
 236         TxErr           = 0x0008,
 237         TxOK            = 0x0004,
 238         RxErr           = 0x0002,
 239         RxOK            = 0x0001,
 240
 241         /* RxStatusDesc */
 242         RxFOVF  = (1 << 23),
 243         RxRWT   = (1 << 22),
 244         RxRES   = (1 << 21),
 245         RxRUNT  = (1 << 20),
 246         RxCRC   = (1 << 19),
 247
 248         /* ChipCmdBits */
 249         CmdReset        = 0x10,
 250         CmdRxEnb        = 0x08,
 251         CmdTxEnb        = 0x04,
 252         RxBufEmpty      = 0x01,
 253
 254         /* TXPoll register p.5 */
 255         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 256         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 257         FSWInt          = 0x01,         /* Forced software interrupt */
 258
 259         /* Cfg9346Bits */
 260         Cfg9346_Lock    = 0x00,
 261         Cfg9346_Unlock  = 0xc0,
 262
 263         /* rx_mode_bits */
 264         AcceptErr       = 0x20,
 265         AcceptRunt      = 0x10,
 266         AcceptBroadcast = 0x08,
 267         AcceptMulticast = 0x04,
 268         AcceptMyPhys    = 0x02,
 269         AcceptAllPhys   = 0x01,
 270
 271         /* RxConfigBits */
 272         RxCfgFIFOShift  = 13,
 273         RxCfgDMAShift   =  8,
 274
 275         /* TxConfigBits */
 276         TxInterFrameGapShift = 24,
 277         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 278
 279         /* Config1 register p.24 */
 280         PMEnable        = (1 << 0),     /* Power Management Enable */
 281
 282         /* Config2 register p. 25 */
 283         PCI_Clock_66MHz = 0x01,
 284         PCI_Clock_33MHz = 0x00,
 285
 286         /* Config3 register p.25 */
 287         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 288         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 289
 290         /* Config5 register p.27 */
 291         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 292         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 293         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 294         LanWake         = (1 << 1),     /* LanWake enable/disable */
 295         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 296
 297         /* TBICSR p.28 */
 298         TBIReset        = 0x80000000,
 299         TBILoopback     = 0x40000000,
 300         TBINwEnable     = 0x20000000,
 301         TBINwRestart    = 0x10000000,
 302         TBILinkOk       = 0x02000000,
 303         TBINwComplete   = 0x01000000,
 304
 305         /* CPlusCmd p.31 */
 306         PktCntrDisable  = (1 << 7),     // 8168
 307         RxVlan          = (1 << 6),
 308         RxChkSum        = (1 << 5),
 309         PCIDAC          = (1 << 4),
 310         PCIMulRW        = (1 << 3),
 311         INTT_0          = 0x0000,       // 8168
 312         INTT_1          = 0x0001,       // 8168
 313         INTT_2          = 0x0002,       // 8168
 314         INTT_3          = 0x0003,       // 8168
 315
 316         /* rtl8169_PHYstatus */
 317         TBI_Enable      = 0x80,
 318         TxFlowCtrl      = 0x40,
 319         RxFlowCtrl      = 0x20,
 320         _1000bpsF       = 0x10,
 321         _100bps         = 0x08,
 322         _10bps          = 0x04,
 323         LinkStatus      = 0x02,
 324         FullDup         = 0x01,
 325
 326         /* _TBICSRBit */
 327         TBILinkOK       = 0x02000000,
 328
 329         /* DumpCounterCommand */
 330         CounterDump     = 0x8,
 331 };
 332
 333 enum desc_status_bit {
 334         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 335         RingEnd         = (1 << 30), /* End of descriptor ring */
 336         FirstFrag       = (1 << 29), /* First segment of a packet */
 337         LastFrag        = (1 << 28), /* Final segment of a packet */
 338
 339         /* Tx private */
 340         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 341         MSSShift        = 16,        /* MSS value position */
 342         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 343         IPCS            = (1 << 18), /* Calculate IP checksum */
 344         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 345         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 346         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 347
 348         /* Rx private */
 349         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 350         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 351
 352 #define RxProtoUDP      (PID1)
 353 #define RxProtoTCP      (PID0)
 354 #define RxProtoIP       (PID1 | PID0)
 355 #define RxProtoMask     RxProtoIP
 356
 357         IPFail          = (1 << 16), /* IP checksum failed */
 358         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 359         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 360         RxVlanTag       = (1 << 16), /* VLAN tag available */
 361 };
 362
 363 #define RsvdMask        0x3fffc000
 364
 365 struct TxDesc {
 366         __le32 opts1;
 367         __le32 opts2;
 368         __le64 addr;
 369 };
 370
 371 struct RxDesc {
 372         __le32 opts1;
 373         __le32 opts2;
 374         __le64 addr;
 375 };
 376
 377 struct ring_info {
 378         struct sk_buff  *skb;
 379         u32             len;
 380         u8              __pad[sizeof(void *) - sizeof(u32)];
 381 };
 382
 383 struct rtl8169_private {
 384         void __iomem *mmio_addr;        /* memory map physical address */
 385         struct pci_dev *pci_dev;        /* Index of PCI device */
 386         struct net_device *dev;
 387         struct net_device_stats stats;  /* statistics of net device */
 388         spinlock_t lock;                /* spin lock flag */
 389         u32 msg_enable;
 390         int chipset;
 391         int mac_version;
 392         int phy_version;
 393         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 394         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 395         u32 dirty_rx;
 396         u32 dirty_tx;
 397         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 398         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 399         dma_addr_t TxPhyAddr;
 400         dma_addr_t RxPhyAddr;
 401         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 402         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 403         unsigned align;
 404         unsigned rx_buf_sz;
 405         struct timer_list timer;
 406         u16 cp_cmd;
 407         u16 intr_event;
 408         u16 napi_event;
 409         u16 intr_mask;
 410         int phy_auto_nego_reg;
 411         int phy_1000_ctrl_reg;
 412 #ifdef CONFIG_R8169_VLAN
 413         struct vlan_group *vlgrp;
 414 #endif
 415         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 416         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 417         void (*phy_reset_enable)(void __iomem *);
 418         void (*hw_start)(struct net_device *);
 419         unsigned int (*phy_reset_pending)(void __iomem *);
 420         unsigned int (*link_ok)(void __iomem *);
 421         struct delayed_work task;
 422         unsigned wol_enabled : 1;
 423 };
 424
 425 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 426 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 427 module_param(rx_copybreak, int, 0);
 428 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 429 module_param(use_dac, int, 0);
 430 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 431 module_param_named(debug, debug.msg_enable, int, 0);
 432 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 433 MODULE_LICENSE("GPL");
 434 MODULE_VERSION(RTL8169_VERSION);
 435
 436 static int rtl8169_open(struct net_device *dev);
 437 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 438 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 439 static int rtl8169_init_ring(struct net_device *dev);
 440 static void rtl_hw_start(struct net_device *dev);
 441 static int rtl8169_close(struct net_device *dev);
 442 static void rtl_set_rx_mode(struct net_device *dev);
 443 static void rtl8169_tx_timeout(struct net_device *dev);
 444 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 445 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 446                                 void __iomem *);
 447 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 448 static void rtl8169_down(struct net_device *dev);
 449 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 450
 451 #ifdef CONFIG_R8169_NAPI
 452 static int rtl8169_poll(struct net_device *dev, int *budget);
 453 #endif
 454
 455 static const unsigned int rtl8169_rx_config =
 456         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 457
 458 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 459 {
 460         int i;
 461
 462         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 463
 464         for (i = 20; i > 0; i--) {
 465                 /*
 466                  * Check if the RTL8169 has completed writing to the specified
 467                  * MII register.
 468                  */
 469                 if (!(RTL_R32(PHYAR) & 0x80000000))
 470                         break;
 471                 udelay(25);
 472         }
 473 }
 474
 475 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 476 {
 477         int i, value = -1;
 478
 479         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 480
 481         for (i = 20; i > 0; i--) {
 482                 /*
 483                  * Check if the RTL8169 has completed retrieving data from
 484                  * the specified MII register.
 485                  */
 486                 if (RTL_R32(PHYAR) & 0x80000000) {
 487                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 488                         break;
 489                 }
 490                 udelay(25);
 491         }
 492         return value;
 493 }
 494
 495 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 496 {
 497         RTL_W16(IntrMask, 0x0000);
 498
 499         RTL_W16(IntrStatus, 0xffff);
 500 }
 501
 502 static void rtl8169_asic_down(void __iomem *ioaddr)
 503 {
 504         RTL_W8(ChipCmd, 0x00);
 505         rtl8169_irq_mask_and_ack(ioaddr);
 506         RTL_R16(CPlusCmd);
 507 }
 508
 509 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 510 {
 511         return RTL_R32(TBICSR) & TBIReset;
 512 }
 513
 514 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 515 {
 516         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 517 }
 518
 519 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 520 {
 521         return RTL_R32(TBICSR) & TBILinkOk;
 522 }
 523
 524 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 525 {
 526         return RTL_R8(PHYstatus) & LinkStatus;
 527 }
 528
 529 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 530 {
 531         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 532 }
 533
 534 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 535 {
 536         unsigned int val;
 537
 538         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 539         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 540 }
 541
 542 static void rtl8169_check_link_status(struct net_device *dev,
 543                                       struct rtl8169_private *tp,
 544                                       void __iomem *ioaddr)
 545 {
 546         unsigned long flags;
 547
 548         spin_lock_irqsave(&tp->lock, flags);
 549         if (tp->link_ok(ioaddr)) {
 550                 netif_carrier_on(dev);
 551                 if (netif_msg_ifup(tp))
 552                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 553         } else {
 554                 if (netif_msg_ifdown(tp))
 555                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 556                 netif_carrier_off(dev);
 557         }
 558         spin_unlock_irqrestore(&tp->lock, flags);
 559 }
 560
 561 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 562 {
 563         struct rtl8169_private *tp = netdev_priv(dev);
 564         void __iomem *ioaddr = tp->mmio_addr;
 565         u8 options;
 566
 567         wol->wolopts = 0;
 568
 569 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 570         wol->supported = WAKE_ANY;
 571
 572         spin_lock_irq(&tp->lock);
 573
 574         options = RTL_R8(Config1);
 575         if (!(options & PMEnable))
 576                 goto out_unlock;
 577
 578         options = RTL_R8(Config3);
 579         if (options & LinkUp)
 580                 wol->wolopts |= WAKE_PHY;
 581         if (options & MagicPacket)
 582                 wol->wolopts |= WAKE_MAGIC;
 583
 584         options = RTL_R8(Config5);
 585         if (options & UWF)
 586                 wol->wolopts |= WAKE_UCAST;
 587         if (options & BWF)
 588                 wol->wolopts |= WAKE_BCAST;
 589         if (options & MWF)
 590                 wol->wolopts |= WAKE_MCAST;
 591
 592 out_unlock:
 593         spin_unlock_irq(&tp->lock);
 594 }
 595
 596 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 597 {
 598         struct rtl8169_private *tp = netdev_priv(dev);
 599         void __iomem *ioaddr = tp->mmio_addr;
 600         unsigned int i;
 601         static struct {
 602                 u32 opt;
 603                 u16 reg;
 604                 u8  mask;
 605         } cfg[] = {
 606                 { WAKE_ANY,   Config1, PMEnable },
 607                 { WAKE_PHY,   Config3, LinkUp },
 608                 { WAKE_MAGIC, Config3, MagicPacket },
 609                 { WAKE_UCAST, Config5, UWF },
 610                 { WAKE_BCAST, Config5, BWF },
 611                 { WAKE_MCAST, Config5, MWF },
 612                 { WAKE_ANY,   Config5, LanWake }
 613         };
 614
 615         spin_lock_irq(&tp->lock);
 616
 617         RTL_W8(Cfg9346, Cfg9346_Unlock);
 618
 619         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 620                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 621                 if (wol->wolopts & cfg[i].opt)
 622                         options |= cfg[i].mask;
 623                 RTL_W8(cfg[i].reg, options);
 624         }
 625
 626         RTL_W8(Cfg9346, Cfg9346_Lock);
 627
 628         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 629
 630         spin_unlock_irq(&tp->lock);
 631
 632         return 0;
 633 }
 634
 635 static void rtl8169_get_drvinfo(struct net_device *dev,
 636                                 struct ethtool_drvinfo *info)
 637 {
 638         struct rtl8169_private *tp = netdev_priv(dev);
 639
 640         strcpy(info->driver, MODULENAME);
 641         strcpy(info->version, RTL8169_VERSION);
 642         strcpy(info->bus_info, pci_name(tp->pci_dev));
 643 }
 644
 645 static int rtl8169_get_regs_len(struct net_device *dev)
 646 {
 647         return R8169_REGS_SIZE;
 648 }
 649
 650 static int rtl8169_set_speed_tbi(struct net_device *dev,
 651                                  u8 autoneg, u16 speed, u8 duplex)
 652 {
 653         struct rtl8169_private *tp = netdev_priv(dev);
 654         void __iomem *ioaddr = tp->mmio_addr;
 655         int ret = 0;
 656         u32 reg;
 657
 658         reg = RTL_R32(TBICSR);
 659         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 660             (duplex == DUPLEX_FULL)) {
 661                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 662         } else if (autoneg == AUTONEG_ENABLE)
 663                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 664         else {
 665                 if (netif_msg_link(tp)) {
 666                         printk(KERN_WARNING "%s: "
 667                                "incorrect speed setting refused in TBI mode\n",
 668                                dev->name);
 669                 }
 670                 ret = -EOPNOTSUPP;
 671         }
 672
 673         return ret;
 674 }
 675
 676 static int rtl8169_set_speed_xmii(struct net_device *dev,
 677                                   u8 autoneg, u16 speed, u8 duplex)
 678 {
 679         struct rtl8169_private *tp = netdev_priv(dev);
 680         void __iomem *ioaddr = tp->mmio_addr;
 681         int auto_nego, giga_ctrl;
 682
 683         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 684         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 685                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 686         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 687         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 688
 689         if (autoneg == AUTONEG_ENABLE) {
 690                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 691                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 692                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 693         } else {
 694                 if (speed == SPEED_10)
 695                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 696                 else if (speed == SPEED_100)
 697                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 698                 else if (speed == SPEED_1000)
 699                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 700
 701                 if (duplex == DUPLEX_HALF)
 702                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 703
 704                 if (duplex == DUPLEX_FULL)
 705                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 706
 707                 /* This tweak comes straight from Realtek's driver. */
 708                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 709                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 710                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 711                 }
 712         }
 713
 714         /* The 8100e/8101e do Fast Ethernet only. */
 715         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 716             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 717             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 718                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 719                     netif_msg_link(tp)) {
 720                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 721                                dev->name);
 722                 }
 723                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 724         }
 725
 726         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 727
 728         if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
 729                 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
 730                 mdio_write(ioaddr, 0x1f, 0x0000);
 731                 mdio_write(ioaddr, 0x0e, 0x0000);
 732         }
 733
 734         tp->phy_auto_nego_reg = auto_nego;
 735         tp->phy_1000_ctrl_reg = giga_ctrl;
 736
 737         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 738         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 739         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 740         return 0;
 741 }
 742
 743 static int rtl8169_set_speed(struct net_device *dev,
 744                              u8 autoneg, u16 speed, u8 duplex)
 745 {
 746         struct rtl8169_private *tp = netdev_priv(dev);
 747         int ret;
 748
 749         ret = tp->set_speed(dev, autoneg, speed, duplex);
 750
 751         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 752                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 753
 754         return ret;
 755 }
 756
 757 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 758 {
 759         struct rtl8169_private *tp = netdev_priv(dev);
 760         unsigned long flags;
 761         int ret;
 762
 763         spin_lock_irqsave(&tp->lock, flags);
 764         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 765         spin_unlock_irqrestore(&tp->lock, flags);
 766
 767         return ret;
 768 }
 769
 770 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 771 {
 772         struct rtl8169_private *tp = netdev_priv(dev);
 773
 774         return tp->cp_cmd & RxChkSum;
 775 }
 776
 777 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 778 {
 779         struct rtl8169_private *tp = netdev_priv(dev);
 780         void __iomem *ioaddr = tp->mmio_addr;
 781         unsigned long flags;
 782
 783         spin_lock_irqsave(&tp->lock, flags);
 784
 785         if (data)
 786                 tp->cp_cmd |= RxChkSum;
 787         else
 788                 tp->cp_cmd &= ~RxChkSum;
 789
 790         RTL_W16(CPlusCmd, tp->cp_cmd);
 791         RTL_R16(CPlusCmd);
 792
 793         spin_unlock_irqrestore(&tp->lock, flags);
 794
 795         return 0;
 796 }
 797
 798 #ifdef CONFIG_R8169_VLAN
 799
 800 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 801                                       struct sk_buff *skb)
 802 {
 803         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 804                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 805 }
 806
 807 static void rtl8169_vlan_rx_register(struct net_device *dev,
 808                                      struct vlan_group *grp)
 809 {
 810         struct rtl8169_private *tp = netdev_priv(dev);
 811         void __iomem *ioaddr = tp->mmio_addr;
 812         unsigned long flags;
 813
 814         spin_lock_irqsave(&tp->lock, flags);
 815         tp->vlgrp = grp;
 816         if (tp->vlgrp)
 817                 tp->cp_cmd |= RxVlan;
 818         else
 819                 tp->cp_cmd &= ~RxVlan;
 820         RTL_W16(CPlusCmd, tp->cp_cmd);
 821         RTL_R16(CPlusCmd);
 822         spin_unlock_irqrestore(&tp->lock, flags);
 823 }
 824
 825 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 826                                struct sk_buff *skb)
 827 {
 828         u32 opts2 = le32_to_cpu(desc->opts2);
 829         int ret;
 830
 831         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 832                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 833                 ret = 0;
 834         } else
 835                 ret = -1;
 836         desc->opts2 = 0;
 837         return ret;
 838 }
 839
 840 #else /* !CONFIG_R8169_VLAN */
 841
 842 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 843                                       struct sk_buff *skb)
 844 {
 845         return 0;
 846 }
 847
 848 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 849                                struct sk_buff *skb)
 850 {
 851         return -1;
 852 }
 853
 854 #endif
 855
 856 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 857 {
 858         struct rtl8169_private *tp = netdev_priv(dev);
 859         void __iomem *ioaddr = tp->mmio_addr;
 860         u32 status;
 861
 862         cmd->supported =
 863                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 864         cmd->port = PORT_FIBRE;
 865         cmd->transceiver = XCVR_INTERNAL;
 866
 867         status = RTL_R32(TBICSR);
 868         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 869         cmd->autoneg = !!(status & TBINwEnable);
 870
 871         cmd->speed = SPEED_1000;
 872         cmd->duplex = DUPLEX_FULL; /* Always set */
 873 }
 874
 875 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 876 {
 877         struct rtl8169_private *tp = netdev_priv(dev);
 878         void __iomem *ioaddr = tp->mmio_addr;
 879         u8 status;
 880
 881         cmd->supported = SUPPORTED_10baseT_Half |
 882                          SUPPORTED_10baseT_Full |
 883                          SUPPORTED_100baseT_Half |
 884                          SUPPORTED_100baseT_Full |
 885                          SUPPORTED_1000baseT_Full |
 886                          SUPPORTED_Autoneg |
 887                          SUPPORTED_TP;
 888
 889         cmd->autoneg = 1;
 890         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 891
 892         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 893                 cmd->advertising |= ADVERTISED_10baseT_Half;
 894         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 895                 cmd->advertising |= ADVERTISED_10baseT_Full;
 896         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 897                 cmd->advertising |= ADVERTISED_100baseT_Half;
 898         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 899                 cmd->advertising |= ADVERTISED_100baseT_Full;
 900         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 901                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 902
 903         status = RTL_R8(PHYstatus);
 904
 905         if (status & _1000bpsF)
 906                 cmd->speed = SPEED_1000;
 907         else if (status & _100bps)
 908                 cmd->speed = SPEED_100;
 909         else if (status & _10bps)
 910                 cmd->speed = SPEED_10;
 911
 912         if (status & TxFlowCtrl)
 913                 cmd->advertising |= ADVERTISED_Asym_Pause;
 914         if (status & RxFlowCtrl)
 915                 cmd->advertising |= ADVERTISED_Pause;
 916
 917         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 918                       DUPLEX_FULL : DUPLEX_HALF;
 919 }
 920
 921 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 922 {
 923         struct rtl8169_private *tp = netdev_priv(dev);
 924         unsigned long flags;
 925
 926         spin_lock_irqsave(&tp->lock, flags);
 927
 928         tp->get_settings(dev, cmd);
 929
 930         spin_unlock_irqrestore(&tp->lock, flags);
 931         return 0;
 932 }
 933
 934 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 935                              void *p)
 936 {
 937         struct rtl8169_private *tp = netdev_priv(dev);
 938         unsigned long flags;
 939
 940         if (regs->len > R8169_REGS_SIZE)
 941                 regs->len = R8169_REGS_SIZE;
 942
 943         spin_lock_irqsave(&tp->lock, flags);
 944         memcpy_fromio(p, tp->mmio_addr, regs->len);
 945         spin_unlock_irqrestore(&tp->lock, flags);
 946 }
 947
 948 static u32 rtl8169_get_msglevel(struct net_device *dev)
 949 {
 950         struct rtl8169_private *tp = netdev_priv(dev);
 951
 952         return tp->msg_enable;
 953 }
 954
 955 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 956 {
 957         struct rtl8169_private *tp = netdev_priv(dev);
 958
 959         tp->msg_enable = value;
 960 }
 961
 962 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 963         "tx_packets",
 964         "rx_packets",
 965         "tx_errors",
 966         "rx_errors",
 967         "rx_missed",
 968         "align_errors",
 969         "tx_single_collisions",
 970         "tx_multi_collisions",
 971         "unicast",
 972         "broadcast",
 973         "multicast",
 974         "tx_aborted",
 975         "tx_underrun",
 976 };
 977
 978 struct rtl8169_counters {
 979         u64     tx_packets;
 980         u64     rx_packets;
 981         u64     tx_errors;
 982         u32     rx_errors;
 983         u16     rx_missed;
 984         u16     align_errors;
 985         u32     tx_one_collision;
 986         u32     tx_multi_collision;
 987         u64     rx_unicast;
 988         u64     rx_broadcast;
 989         u32     rx_multicast;
 990         u16     tx_aborted;
 991         u16     tx_underun;
 992 };
 993
 994 static int rtl8169_get_stats_count(struct net_device *dev)
 995 {
 996         return ARRAY_SIZE(rtl8169_gstrings);
 997 }
 998
 999 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1000                                       struct ethtool_stats *stats, u64 *data)
1001 {
1002         struct rtl8169_private *tp = netdev_priv(dev);
1003         void __iomem *ioaddr = tp->mmio_addr;
1004         struct rtl8169_counters *counters;
1005         dma_addr_t paddr;
1006         u32 cmd;
1007
1008         ASSERT_RTNL();
1009
1010         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1011         if (!counters)
1012                 return;
1013
1014         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1015         cmd = (u64)paddr & DMA_32BIT_MASK;
1016         RTL_W32(CounterAddrLow, cmd);
1017         RTL_W32(CounterAddrLow, cmd | CounterDump);
1018
1019         while (RTL_R32(CounterAddrLow) & CounterDump) {
1020                 if (msleep_interruptible(1))
1021                         break;
1022         }
1023
1024         RTL_W32(CounterAddrLow, 0);
1025         RTL_W32(CounterAddrHigh, 0);
1026
1027         data[0] = le64_to_cpu(counters->tx_packets);
1028         data[1] = le64_to_cpu(counters->rx_packets);
1029         data[2] = le64_to_cpu(counters->tx_errors);
1030         data[3] = le32_to_cpu(counters->rx_errors);
1031         data[4] = le16_to_cpu(counters->rx_missed);
1032         data[5] = le16_to_cpu(counters->align_errors);
1033         data[6] = le32_to_cpu(counters->tx_one_collision);
1034         data[7] = le32_to_cpu(counters->tx_multi_collision);
1035         data[8] = le64_to_cpu(counters->rx_unicast);
1036         data[9] = le64_to_cpu(counters->rx_broadcast);
1037         data[10] = le32_to_cpu(counters->rx_multicast);
1038         data[11] = le16_to_cpu(counters->tx_aborted);
1039         data[12] = le16_to_cpu(counters->tx_underun);
1040
1041         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1042 }
1043
1044 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1045 {
1046         switch(stringset) {
1047         case ETH_SS_STATS:
1048                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1049                 break;
1050         }
1051 }
1052
1053 static const struct ethtool_ops rtl8169_ethtool_ops = {
1054         .get_drvinfo            = rtl8169_get_drvinfo,
1055         .get_regs_len           = rtl8169_get_regs_len,
1056         .get_link               = ethtool_op_get_link,
1057         .get_settings           = rtl8169_get_settings,
1058         .set_settings           = rtl8169_set_settings,
1059         .get_msglevel           = rtl8169_get_msglevel,
1060         .set_msglevel           = rtl8169_set_msglevel,
1061         .get_rx_csum            = rtl8169_get_rx_csum,
1062         .set_rx_csum            = rtl8169_set_rx_csum,
1063         .get_tx_csum            = ethtool_op_get_tx_csum,
1064         .set_tx_csum            = ethtool_op_set_tx_csum,
1065         .get_sg                 = ethtool_op_get_sg,
1066         .set_sg                 = ethtool_op_set_sg,
1067         .get_tso                = ethtool_op_get_tso,
1068         .set_tso                = ethtool_op_set_tso,
1069         .get_regs               = rtl8169_get_regs,
1070         .get_wol                = rtl8169_get_wol,
1071         .set_wol                = rtl8169_set_wol,
1072         .get_strings            = rtl8169_get_strings,
1073         .get_stats_count        = rtl8169_get_stats_count,
1074         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1075         .get_perm_addr          = ethtool_op_get_perm_addr,
1076 };
1077
1078 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1079                                        int bitnum, int bitval)
1080 {
1081         int val;
1082
1083         val = mdio_read(ioaddr, reg);
1084         val = (bitval == 1) ?
1085                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1086         mdio_write(ioaddr, reg, val & 0xffff);
1087 }
1088
1089 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1090                                     void __iomem *ioaddr)
1091 {
1092         /*
1093          * The driver currently handles the 8168Bf and the 8168Be identically
1094          * but they can be identified more specifically through the test below
1095          * if needed:
1096          *
1097          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1098          *
1099          * Same thing for the 8101Eb and the 8101Ec:
1100          *
1101          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1102          */
1103         const struct {
1104                 u32 mask;
1105                 int mac_version;
1106         } mac_info[] = {
1107                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1108                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1109                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1110                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1111                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1112                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1113                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1114                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1115                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1116                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1117                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1118         }, *p = mac_info;
1119         u32 reg;
1120
1121         reg = RTL_R32(TxConfig) & 0xfc800000;
1122         while ((reg & p->mask) != p->mask)
1123                 p++;
1124         tp->mac_version = p->mac_version;
1125 }
1126
1127 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1128 {
1129         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1130 }
1131
1132 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1133                                     void __iomem *ioaddr)
1134 {
1135         const struct {
1136                 u16 mask;
1137                 u16 set;
1138                 int phy_version;
1139         } phy_info[] = {
1140                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1141                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1142                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1143                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1144         }, *p = phy_info;
1145         u16 reg;
1146
1147         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1148         while ((reg & p->mask) != p->set)
1149                 p++;
1150         tp->phy_version = p->phy_version;
1151 }
1152
1153 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1154 {
1155         struct {
1156                 int version;
1157                 char *msg;
1158                 u32 reg;
1159         } phy_print[] = {
1160                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1161                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1162                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1163                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1164                 { 0, NULL, 0x0000 }
1165         }, *p;
1166
1167         for (p = phy_print; p->msg; p++) {
1168                 if (tp->phy_version == p->version) {
1169                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1170                         return;
1171                 }
1172         }
1173         dprintk("phy_version == Unknown\n");
1174 }
1175
1176 static void rtl8169_hw_phy_config(struct net_device *dev)
1177 {
1178         struct rtl8169_private *tp = netdev_priv(dev);
1179         void __iomem *ioaddr = tp->mmio_addr;
1180         struct {
1181                 u16 regs[5]; /* Beware of bit-sign propagation */
1182         } phy_magic[5] = { {
1183                 { 0x0000,       //w 4 15 12 0
1184                   0x00a1,       //w 3 15 0 00a1
1185                   0x0008,       //w 2 15 0 0008
1186                   0x1020,       //w 1 15 0 1020
1187                   0x1000 } },{  //w 0 15 0 1000
1188                 { 0x7000,       //w 4 15 12 7
1189                   0xff41,       //w 3 15 0 ff41
1190                   0xde60,       //w 2 15 0 de60
1191                   0x0140,       //w 1 15 0 0140
1192                   0x0077 } },{  //w 0 15 0 0077
1193                 { 0xa000,       //w 4 15 12 a
1194                   0xdf01,       //w 3 15 0 df01
1195                   0xdf20,       //w 2 15 0 df20
1196                   0xff95,       //w 1 15 0 ff95
1197                   0xfa00 } },{  //w 0 15 0 fa00
1198                 { 0xb000,       //w 4 15 12 b
1199                   0xff41,       //w 3 15 0 ff41
1200                   0xde20,       //w 2 15 0 de20
1201                   0x0140,       //w 1 15 0 0140
1202                   0x00bb } },{  //w 0 15 0 00bb
1203                 { 0xf000,       //w 4 15 12 f
1204                   0xdf01,       //w 3 15 0 df01
1205                   0xdf20,       //w 2 15 0 df20
1206                   0xff95,       //w 1 15 0 ff95
1207                   0xbf00 }      //w 0 15 0 bf00
1208                 }
1209         }, *p = phy_magic;
1210         unsigned int i;
1211
1212         rtl8169_print_mac_version(tp);
1213         rtl8169_print_phy_version(tp);
1214
1215         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1216                 return;
1217         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1218                 return;
1219
1220         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1221         dprintk("Do final_reg2.cfg\n");
1222
1223         /* Shazam ! */
1224
1225         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1226                 mdio_write(ioaddr, 31, 0x0002);
1227                 mdio_write(ioaddr,  1, 0x90d0);
1228                 mdio_write(ioaddr, 31, 0x0000);
1229                 return;
1230         }
1231
1232         /* phy config for RTL8169s mac_version C chip */
1233         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1234         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1235         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1236         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1237
1238         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1239                 int val, pos = 4;
1240
1241                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1242                 mdio_write(ioaddr, pos, val);
1243                 while (--pos >= 0)
1244                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1245                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1246                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1247         }
1248         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1249 }
1250
1251 static void rtl8169_phy_timer(unsigned long __opaque)
1252 {
1253         struct net_device *dev = (struct net_device *)__opaque;
1254         struct rtl8169_private *tp = netdev_priv(dev);
1255         struct timer_list *timer = &tp->timer;
1256         void __iomem *ioaddr = tp->mmio_addr;
1257         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1258
1259         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1260         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1261
1262         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1263                 return;
1264
1265         spin_lock_irq(&tp->lock);
1266
1267         if (tp->phy_reset_pending(ioaddr)) {
1268                 /*
1269                  * A busy loop could burn quite a few cycles on nowadays CPU.
1270                  * Let's delay the execution of the timer for a few ticks.
1271                  */
1272                 timeout = HZ/10;
1273                 goto out_mod_timer;
1274         }
1275
1276         if (tp->link_ok(ioaddr))
1277                 goto out_unlock;
1278
1279         if (netif_msg_link(tp))
1280                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1281
1282         tp->phy_reset_enable(ioaddr);
1283
1284 out_mod_timer:
1285         mod_timer(timer, jiffies + timeout);
1286 out_unlock:
1287         spin_unlock_irq(&tp->lock);
1288 }
1289
1290 static inline void rtl8169_delete_timer(struct net_device *dev)
1291 {
1292         struct rtl8169_private *tp = netdev_priv(dev);
1293         struct timer_list *timer = &tp->timer;
1294
1295         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1296             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1297                 return;
1298
1299         del_timer_sync(timer);
1300 }
1301
1302 static inline void rtl8169_request_timer(struct net_device *dev)
1303 {
1304         struct rtl8169_private *tp = netdev_priv(dev);
1305         struct timer_list *timer = &tp->timer;
1306
1307         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1308             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1309                 return;
1310
1311         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1312 }
1313
1314 #ifdef CONFIG_NET_POLL_CONTROLLER
1315 /*
1316  * Polling 'interrupt' - used by things like netconsole to send skbs
1317  * without having to re-enable interrupts. It's not called while
1318  * the interrupt routine is executing.
1319  */
1320 static void rtl8169_netpoll(struct net_device *dev)
1321 {
1322         struct rtl8169_private *tp = netdev_priv(dev);
1323         struct pci_dev *pdev = tp->pci_dev;
1324
1325         disable_irq(pdev->irq);
1326         rtl8169_interrupt(pdev->irq, dev);
1327         enable_irq(pdev->irq);
1328 }
1329 #endif
1330
1331 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1332                                   void __iomem *ioaddr)
1333 {
1334         iounmap(ioaddr);
1335         pci_release_regions(pdev);
1336         pci_disable_device(pdev);
1337         free_netdev(dev);
1338 }
1339
1340 static void rtl8169_phy_reset(struct net_device *dev,
1341                               struct rtl8169_private *tp)
1342 {
1343         void __iomem *ioaddr = tp->mmio_addr;
1344         unsigned int i;
1345
1346         tp->phy_reset_enable(ioaddr);
1347         for (i = 0; i < 100; i++) {
1348                 if (!tp->phy_reset_pending(ioaddr))
1349                         return;
1350                 msleep(1);
1351         }
1352         if (netif_msg_link(tp))
1353                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1354 }
1355
1356 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1357 {
1358         void __iomem *ioaddr = tp->mmio_addr;
1359
1360         rtl8169_hw_phy_config(dev);
1361
1362         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1363         RTL_W8(0x82, 0x01);
1364
1365         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1366
1367         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1368                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1369
1370         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1371                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1372                 RTL_W8(0x82, 0x01);
1373                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1374                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1375         }
1376
1377         rtl8169_phy_reset(dev, tp);
1378
1379         /*
1380          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1381          * only 8101. Don't panic.
1382          */
1383         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1384
1385         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1386                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1387 }
1388
1389 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1390 {
1391         void __iomem *ioaddr = tp->mmio_addr;
1392         u32 high;
1393         u32 low;
1394
1395         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1396         high = addr[4] | (addr[5] << 8);
1397
1398         spin_lock_irq(&tp->lock);
1399
1400         RTL_W8(Cfg9346, Cfg9346_Unlock);
1401         RTL_W32(MAC0, low);
1402         RTL_W32(MAC4, high);
1403         RTL_W8(Cfg9346, Cfg9346_Lock);
1404
1405         spin_unlock_irq(&tp->lock);
1406 }
1407
1408 static int rtl_set_mac_address(struct net_device *dev, void *p)
1409 {
1410         struct rtl8169_private *tp = netdev_priv(dev);
1411         struct sockaddr *addr = p;
1412
1413         if (!is_valid_ether_addr(addr->sa_data))
1414                 return -EADDRNOTAVAIL;
1415
1416         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1417
1418         rtl_rar_set(tp, dev->dev_addr);
1419
1420         return 0;
1421 }
1422
1423 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1424 {
1425         struct rtl8169_private *tp = netdev_priv(dev);
1426         struct mii_ioctl_data *data = if_mii(ifr);
1427
1428         if (!netif_running(dev))
1429                 return -ENODEV;
1430
1431         switch (cmd) {
1432         case SIOCGMIIPHY:
1433                 data->phy_id = 32; /* Internal PHY */
1434                 return 0;
1435
1436         case SIOCGMIIREG:
1437                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1438                 return 0;
1439
1440         case SIOCSMIIREG:
1441                 if (!capable(CAP_NET_ADMIN))
1442                         return -EPERM;
1443                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1444                 return 0;
1445         }
1446         return -EOPNOTSUPP;
1447 }
1448
1449 static const struct rtl_cfg_info {
1450         void (*hw_start)(struct net_device *);
1451         unsigned int region;
1452         unsigned int align;
1453         u16 intr_event;
1454         u16 napi_event;
1455 } rtl_cfg_infos [] = {
1456         [RTL_CFG_0] = {
1457                 .hw_start       = rtl_hw_start_8169,
1458                 .region         = 1,
1459                 .align          = 0,
1460                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1461                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1462                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1463         },
1464         [RTL_CFG_1] = {
1465                 .hw_start       = rtl_hw_start_8168,
1466                 .region         = 2,
1467                 .align          = 8,
1468                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1469                                   TxErr | TxOK | RxOK | RxErr,
1470                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1471         },
1472         [RTL_CFG_2] = {
1473                 .hw_start       = rtl_hw_start_8101,
1474                 .region         = 2,
1475                 .align          = 8,
1476                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1477                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1478                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1479         }
1480 };
1481
1482 static int __devinit
1483 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1484 {
1485         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1486         const unsigned int region = cfg->region;
1487         struct rtl8169_private *tp;
1488         struct net_device *dev;
1489         void __iomem *ioaddr;
1490         unsigned int i;
1491         int rc;
1492
1493         if (netif_msg_drv(&debug)) {
1494                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1495                        MODULENAME, RTL8169_VERSION);
1496         }
1497
1498         dev = alloc_etherdev(sizeof (*tp));
1499         if (!dev) {
1500                 if (netif_msg_drv(&debug))
1501                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1502                 rc = -ENOMEM;
1503                 goto out;
1504         }
1505
1506         SET_MODULE_OWNER(dev);
1507         SET_NETDEV_DEV(dev, &pdev->dev);
1508         tp = netdev_priv(dev);
1509         tp->dev = dev;
1510         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1511
1512         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1513         rc = pci_enable_device(pdev);
1514         if (rc < 0) {
1515                 if (netif_msg_probe(tp))
1516                         dev_err(&pdev->dev, "enable failure\n");
1517                 goto err_out_free_dev_1;
1518         }
1519
1520         rc = pci_set_mwi(pdev);
1521         if (rc < 0)
1522                 goto err_out_disable_2;
1523
1524         /* make sure PCI base addr 1 is MMIO */
1525         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1526                 if (netif_msg_probe(tp)) {
1527                         dev_err(&pdev->dev,
1528                                 "region #%d not an MMIO resource, aborting\n",
1529                                 region);
1530                 }
1531                 rc = -ENODEV;
1532                 goto err_out_mwi_3;
1533         }
1534
1535         /* check for weird/broken PCI region reporting */
1536         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1537                 if (netif_msg_probe(tp)) {
1538                         dev_err(&pdev->dev,
1539                                 "Invalid PCI region size(s), aborting\n");
1540                 }
1541                 rc = -ENODEV;
1542                 goto err_out_mwi_3;
1543         }
1544
1545         rc = pci_request_regions(pdev, MODULENAME);
1546         if (rc < 0) {
1547                 if (netif_msg_probe(tp))
1548                         dev_err(&pdev->dev, "could not request regions.\n");
1549                 goto err_out_mwi_3;
1550         }
1551
1552         tp->cp_cmd = PCIMulRW | RxChkSum;
1553
1554         if ((sizeof(dma_addr_t) > 4) &&
1555             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1556                 tp->cp_cmd |= PCIDAC;
1557                 dev->features |= NETIF_F_HIGHDMA;
1558         } else {
1559                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1560                 if (rc < 0) {
1561                         if (netif_msg_probe(tp)) {
1562                                 dev_err(&pdev->dev,
1563                                         "DMA configuration failed.\n");
1564                         }
1565                         goto err_out_free_res_4;
1566                 }
1567         }
1568
1569         pci_set_master(pdev);
1570
1571         /* ioremap MMIO region */
1572         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1573         if (!ioaddr) {
1574                 if (netif_msg_probe(tp))
1575                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1576                 rc = -EIO;
1577                 goto err_out_free_res_4;
1578         }
1579
1580         /* Unneeded ? Don't mess with Mrs. Murphy. */
1581         rtl8169_irq_mask_and_ack(ioaddr);
1582
1583         /* Soft reset the chip. */
1584         RTL_W8(ChipCmd, CmdReset);
1585
1586         /* Check that the chip has finished the reset. */
1587         for (i = 0; i < 100; i++) {
1588                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1589                         break;
1590                 msleep_interruptible(1);
1591         }
1592
1593         /* Identify chip attached to board */
1594         rtl8169_get_mac_version(tp, ioaddr);
1595         rtl8169_get_phy_version(tp, ioaddr);
1596
1597         rtl8169_print_mac_version(tp);
1598         rtl8169_print_phy_version(tp);
1599
1600         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1601                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1602                         break;
1603         }
1604         if (i < 0) {
1605                 /* Unknown chip: assume array element #0, original RTL-8169 */
1606                 if (netif_msg_probe(tp)) {
1607                         dev_printk(KERN_DEBUG, &pdev->dev,
1608                                 "unknown chip version, assuming %s\n",
1609                                 rtl_chip_info[0].name);
1610                 }
1611                 i++;
1612         }
1613         tp->chipset = i;
1614
1615         RTL_W8(Cfg9346, Cfg9346_Unlock);
1616         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1617         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1618         RTL_W8(Cfg9346, Cfg9346_Lock);
1619
1620         if (RTL_R8(PHYstatus) & TBI_Enable) {
1621                 tp->set_speed = rtl8169_set_speed_tbi;
1622                 tp->get_settings = rtl8169_gset_tbi;
1623                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1624                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1625                 tp->link_ok = rtl8169_tbi_link_ok;
1626
1627                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1628         } else {
1629                 tp->set_speed = rtl8169_set_speed_xmii;
1630                 tp->get_settings = rtl8169_gset_xmii;
1631                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1632                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1633                 tp->link_ok = rtl8169_xmii_link_ok;
1634
1635                 dev->do_ioctl = rtl8169_ioctl;
1636         }
1637
1638         /* Get MAC address.  FIXME: read EEPROM */
1639         for (i = 0; i < MAC_ADDR_LEN; i++)
1640                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1641         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1642
1643         dev->open = rtl8169_open;
1644         dev->hard_start_xmit = rtl8169_start_xmit;
1645         dev->get_stats = rtl8169_get_stats;
1646         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1647         dev->stop = rtl8169_close;
1648         dev->tx_timeout = rtl8169_tx_timeout;
1649         dev->set_multicast_list = rtl_set_rx_mode;
1650         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1651         dev->irq = pdev->irq;
1652         dev->base_addr = (unsigned long) ioaddr;
1653         dev->change_mtu = rtl8169_change_mtu;
1654         dev->set_mac_address = rtl_set_mac_address;
1655
1656 #ifdef CONFIG_R8169_NAPI
1657         dev->poll = rtl8169_poll;
1658         dev->weight = R8169_NAPI_WEIGHT;
1659 #endif
1660
1661 #ifdef CONFIG_R8169_VLAN
1662         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1663         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1664 #endif
1665
1666 #ifdef CONFIG_NET_POLL_CONTROLLER
1667         dev->poll_controller = rtl8169_netpoll;
1668 #endif
1669
1670         tp->intr_mask = 0xffff;
1671         tp->pci_dev = pdev;
1672         tp->mmio_addr = ioaddr;
1673         tp->align = cfg->align;
1674         tp->hw_start = cfg->hw_start;
1675         tp->intr_event = cfg->intr_event;
1676         tp->napi_event = cfg->napi_event;
1677
1678         init_timer(&tp->timer);
1679         tp->timer.data = (unsigned long) dev;
1680         tp->timer.function = rtl8169_phy_timer;
1681
1682         spin_lock_init(&tp->lock);
1683
1684         rc = register_netdev(dev);
1685         if (rc < 0)
1686                 goto err_out_unmap_5;
1687
1688         pci_set_drvdata(pdev, dev);
1689
1690         if (netif_msg_probe(tp)) {
1691                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1692
1693                 printk(KERN_INFO "%s: %s at 0x%lx, "
1694                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1695                        "XID %08x IRQ %d\n",
1696                        dev->name,
1697                        rtl_chip_info[tp->chipset].name,
1698                        dev->base_addr,
1699                        dev->dev_addr[0], dev->dev_addr[1],
1700                        dev->dev_addr[2], dev->dev_addr[3],
1701                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1702         }
1703
1704         rtl8169_init_phy(dev, tp);
1705
1706 out:
1707         return rc;
1708
1709 err_out_unmap_5:
1710         iounmap(ioaddr);
1711 err_out_free_res_4:
1712         pci_release_regions(pdev);
1713 err_out_mwi_3:
1714         pci_clear_mwi(pdev);
1715 err_out_disable_2:
1716         pci_disable_device(pdev);
1717 err_out_free_dev_1:
1718         free_netdev(dev);
1719         goto out;
1720 }
1721
1722 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1723 {
1724         struct net_device *dev = pci_get_drvdata(pdev);
1725         struct rtl8169_private *tp = netdev_priv(dev);
1726
1727         flush_scheduled_work();
1728
1729         unregister_netdev(dev);
1730         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1731         pci_set_drvdata(pdev, NULL);
1732 }
1733
1734 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1735                                   struct net_device *dev)
1736 {
1737         unsigned int mtu = dev->mtu;
1738
1739         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1740 }
1741
1742 static int rtl8169_open(struct net_device *dev)
1743 {
1744         struct rtl8169_private *tp = netdev_priv(dev);
1745         struct pci_dev *pdev = tp->pci_dev;
1746         int retval = -ENOMEM;
1747
1748
1749         rtl8169_set_rxbufsize(tp, dev);
1750
1751         /*
1752          * Rx and Tx desscriptors needs 256 bytes alignment.
1753          * pci_alloc_consistent provides more.
1754          */
1755         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1756                                                &tp->TxPhyAddr);
1757         if (!tp->TxDescArray)
1758                 goto out;
1759
1760         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1761                                                &tp->RxPhyAddr);
1762         if (!tp->RxDescArray)
1763                 goto err_free_tx_0;
1764
1765         retval = rtl8169_init_ring(dev);
1766         if (retval < 0)
1767                 goto err_free_rx_1;
1768
1769         INIT_DELAYED_WORK(&tp->task, NULL);
1770
1771         smp_mb();
1772
1773         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1774                              dev->name, dev);
1775         if (retval < 0)
1776                 goto err_release_ring_2;
1777
1778         rtl_hw_start(dev);
1779
1780         rtl8169_request_timer(dev);
1781
1782         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1783 out:
1784         return retval;
1785
1786 err_release_ring_2:
1787         rtl8169_rx_clear(tp);
1788 err_free_rx_1:
1789         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1790                             tp->RxPhyAddr);
1791 err_free_tx_0:
1792         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1793                             tp->TxPhyAddr);
1794         goto out;
1795 }
1796
1797 static void rtl8169_hw_reset(void __iomem *ioaddr)
1798 {
1799         /* Disable interrupts */
1800         rtl8169_irq_mask_and_ack(ioaddr);
1801
1802         /* Reset the chipset */
1803         RTL_W8(ChipCmd, CmdReset);
1804
1805         /* PCI commit */
1806         RTL_R8(ChipCmd);
1807 }
1808
1809 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1810 {
1811         void __iomem *ioaddr = tp->mmio_addr;
1812         u32 cfg = rtl8169_rx_config;
1813
1814         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1815         RTL_W32(RxConfig, cfg);
1816
1817         /* Set DMA burst size and Interframe Gap Time */
1818         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1819                 (InterFrameGap << TxInterFrameGapShift));
1820 }
1821
1822 static void rtl_hw_start(struct net_device *dev)
1823 {
1824         struct rtl8169_private *tp = netdev_priv(dev);
1825         void __iomem *ioaddr = tp->mmio_addr;
1826         unsigned int i;
1827
1828         /* Soft reset the chip. */
1829         RTL_W8(ChipCmd, CmdReset);
1830
1831         /* Check that the chip has finished the reset. */
1832         for (i = 0; i < 100; i++) {
1833                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1834                         break;
1835                 msleep_interruptible(1);
1836         }
1837
1838         tp->hw_start(dev);
1839
1840         netif_start_queue(dev);
1841 }
1842
1843
1844 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1845                                          void __iomem *ioaddr)
1846 {
1847         /*
1848          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1849          * register to be written before TxDescAddrLow to work.
1850          * Switching from MMIO to I/O access fixes the issue as well.
1851          */
1852         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1853         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1854         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1855         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1856 }
1857
1858 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1859 {
1860         u16 cmd;
1861
1862         cmd = RTL_R16(CPlusCmd);
1863         RTL_W16(CPlusCmd, cmd);
1864         return cmd;
1865 }
1866
1867 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1868 {
1869         /* Low hurts. Let's disable the filtering. */
1870         RTL_W16(RxMaxSize, 16383);
1871 }
1872
1873 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1874 {
1875         struct {
1876                 u32 mac_version;
1877                 u32 clk;
1878                 u32 val;
1879         } cfg2_info [] = {
1880                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1881                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1882                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1883                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1884         }, *p = cfg2_info;
1885         unsigned int i;
1886         u32 clk;
1887
1888         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1889         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1890                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1891                         RTL_W32(0x7c, p->val);
1892                         break;
1893                 }
1894         }
1895 }
1896
1897 static void rtl_hw_start_8169(struct net_device *dev)
1898 {
1899         struct rtl8169_private *tp = netdev_priv(dev);
1900         void __iomem *ioaddr = tp->mmio_addr;
1901         struct pci_dev *pdev = tp->pci_dev;
1902
1903         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1904                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1905                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1906         }
1907
1908         RTL_W8(Cfg9346, Cfg9346_Unlock);
1909         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1910             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1911             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1912             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1913                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1914
1915         RTL_W8(EarlyTxThres, EarlyTxThld);
1916
1917         rtl_set_rx_max_size(ioaddr);
1918
1919         rtl_set_rx_tx_config_registers(tp);
1920
1921         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1922
1923         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1924             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1925                 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1926                         "Bit-3 and bit-14 MUST be 1\n");
1927                 tp->cp_cmd |= (1 << 14);
1928         }
1929
1930         RTL_W16(CPlusCmd, tp->cp_cmd);
1931
1932         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1933
1934         /*
1935          * Undocumented corner. Supposedly:
1936          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1937          */
1938         RTL_W16(IntrMitigate, 0x0000);
1939
1940         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1941
1942         RTL_W8(Cfg9346, Cfg9346_Lock);
1943
1944         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1945         RTL_R8(IntrMask);
1946
1947         RTL_W32(RxMissed, 0);
1948
1949         rtl_set_rx_mode(dev);
1950
1951         /* no early-rx interrupts */
1952         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1953
1954         /* Enable all known interrupts by setting the interrupt mask. */
1955         RTL_W16(IntrMask, tp->intr_event);
1956
1957         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1958 }
1959
1960 static void rtl_hw_start_8168(struct net_device *dev)
1961 {
1962         struct rtl8169_private *tp = netdev_priv(dev);
1963         void __iomem *ioaddr = tp->mmio_addr;
1964         struct pci_dev *pdev = tp->pci_dev;
1965         u8 ctl;
1966
1967         RTL_W8(Cfg9346, Cfg9346_Unlock);
1968
1969         RTL_W8(EarlyTxThres, EarlyTxThld);
1970
1971         rtl_set_rx_max_size(ioaddr);
1972
1973         rtl_set_rx_tx_config_registers(tp);
1974
1975         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1976
1977         RTL_W16(CPlusCmd, tp->cp_cmd);
1978
1979         /* Tx performance tweak. */
1980         pci_read_config_byte(pdev, 0x69, &ctl);
1981         ctl = (ctl & ~0x70) | 0x50;
1982         pci_write_config_byte(pdev, 0x69, ctl);
1983
1984         RTL_W16(IntrMitigate, 0x5151);
1985
1986         /* Work around for RxFIFO overflow. */
1987         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1988                 tp->intr_event |= RxFIFOOver | PCSTimeout;
1989                 tp->intr_event &= ~RxOverflow;
1990         }
1991
1992         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1993
1994         RTL_W8(Cfg9346, Cfg9346_Lock);
1995
1996         RTL_R8(IntrMask);
1997
1998         RTL_W32(RxMissed, 0);
1999
2000         rtl_set_rx_mode(dev);
2001
2002         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2003
2004         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2005
2006         RTL_W16(IntrMask, tp->intr_event);
2007 }
2008
2009 static void rtl_hw_start_8101(struct net_device *dev)
2010 {
2011         struct rtl8169_private *tp = netdev_priv(dev);
2012         void __iomem *ioaddr = tp->mmio_addr;
2013         struct pci_dev *pdev = tp->pci_dev;
2014
2015         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2016                 pci_write_config_word(pdev, 0x68, 0x00);
2017                 pci_write_config_word(pdev, 0x69, 0x08);
2018         }
2019
2020         RTL_W8(Cfg9346, Cfg9346_Unlock);
2021
2022         RTL_W8(EarlyTxThres, EarlyTxThld);
2023
2024         rtl_set_rx_max_size(ioaddr);
2025
2026         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2027
2028         RTL_W16(CPlusCmd, tp->cp_cmd);
2029
2030         RTL_W16(IntrMitigate, 0x0000);
2031
2032         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2033
2034         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2035         rtl_set_rx_tx_config_registers(tp);
2036
2037         RTL_W8(Cfg9346, Cfg9346_Lock);
2038
2039         RTL_R8(IntrMask);
2040
2041         RTL_W32(RxMissed, 0);
2042
2043         rtl_set_rx_mode(dev);
2044
2045         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2046
2047         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2048
2049         RTL_W16(IntrMask, tp->intr_event);
2050 }
2051
2052 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2053 {
2054         struct rtl8169_private *tp = netdev_priv(dev);
2055         int ret = 0;
2056
2057         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2058                 return -EINVAL;
2059
2060         dev->mtu = new_mtu;
2061
2062         if (!netif_running(dev))
2063                 goto out;
2064
2065         rtl8169_down(dev);
2066
2067         rtl8169_set_rxbufsize(tp, dev);
2068
2069         ret = rtl8169_init_ring(dev);
2070         if (ret < 0)
2071                 goto out;
2072
2073         netif_poll_enable(dev);
2074
2075         rtl_hw_start(dev);
2076
2077         rtl8169_request_timer(dev);
2078
2079 out:
2080         return ret;
2081 }
2082
2083 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2084 {
2085         desc->addr = 0x0badbadbadbadbadull;
2086         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2087 }
2088
2089 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2090                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2091 {
2092         struct pci_dev *pdev = tp->pci_dev;
2093
2094         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2095                          PCI_DMA_FROMDEVICE);
2096         dev_kfree_skb(*sk_buff);
2097         *sk_buff = NULL;
2098         rtl8169_make_unusable_by_asic(desc);
2099 }
2100
2101 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2102 {
2103         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2104
2105         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2106 }
2107
2108 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2109                                        u32 rx_buf_sz)
2110 {
2111         desc->addr = cpu_to_le64(mapping);
2112         wmb();
2113         rtl8169_mark_to_asic(desc, rx_buf_sz);
2114 }
2115
2116 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2117                                             struct net_device *dev,
2118                                             struct RxDesc *desc, int rx_buf_sz,
2119                                             unsigned int align)
2120 {
2121         struct sk_buff *skb;
2122         dma_addr_t mapping;
2123         unsigned int pad;
2124
2125         pad = align ? align : NET_IP_ALIGN;
2126
2127         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2128         if (!skb)
2129                 goto err_out;
2130
2131         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2132
2133         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2134                                  PCI_DMA_FROMDEVICE);
2135
2136         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2137 out:
2138         return skb;
2139
2140 err_out:
2141         rtl8169_make_unusable_by_asic(desc);
2142         goto out;
2143 }
2144
2145 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2146 {
2147         unsigned int i;
2148
2149         for (i = 0; i < NUM_RX_DESC; i++) {
2150                 if (tp->Rx_skbuff[i]) {
2151                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2152                                             tp->RxDescArray + i);
2153                 }
2154         }
2155 }
2156
2157 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2158                            u32 start, u32 end)
2159 {
2160         u32 cur;
2161
2162         for (cur = start; end - cur != 0; cur++) {
2163                 struct sk_buff *skb;
2164                 unsigned int i = cur % NUM_RX_DESC;
2165
2166                 WARN_ON((s32)(end - cur) < 0);
2167
2168                 if (tp->Rx_skbuff[i])
2169                         continue;
2170
2171                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2172                                            tp->RxDescArray + i,
2173                                            tp->rx_buf_sz, tp->align);
2174                 if (!skb)
2175                         break;
2176
2177                 tp->Rx_skbuff[i] = skb;
2178         }
2179         return cur - start;
2180 }
2181
2182 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2183 {
2184         desc->opts1 |= cpu_to_le32(RingEnd);
2185 }
2186
2187 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2188 {
2189         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2190 }
2191
2192 static int rtl8169_init_ring(struct net_device *dev)
2193 {
2194         struct rtl8169_private *tp = netdev_priv(dev);
2195
2196         rtl8169_init_ring_indexes(tp);
2197
2198         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2199         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2200
2201         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2202                 goto err_out;
2203
2204         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2205
2206         return 0;
2207
2208 err_out:
2209         rtl8169_rx_clear(tp);
2210         return -ENOMEM;
2211 }
2212
2213 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2214                                  struct TxDesc *desc)
2215 {
2216         unsigned int len = tx_skb->len;
2217
2218         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2219         desc->opts1 = 0x00;
2220         desc->opts2 = 0x00;
2221         desc->addr = 0x00;
2222         tx_skb->len = 0;
2223 }
2224
2225 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2226 {
2227         unsigned int i;
2228
2229         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2230                 unsigned int entry = i % NUM_TX_DESC;
2231                 struct ring_info *tx_skb = tp->tx_skb + entry;
2232                 unsigned int len = tx_skb->len;
2233
2234                 if (len) {
2235                         struct sk_buff *skb = tx_skb->skb;
2236
2237                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2238                                              tp->TxDescArray + entry);
2239                         if (skb) {
2240                                 dev_kfree_skb(skb);
2241                                 tx_skb->skb = NULL;
2242                         }
2243                         tp->stats.tx_dropped++;
2244                 }
2245         }
2246         tp->cur_tx = tp->dirty_tx = 0;
2247 }
2248
2249 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2250 {
2251         struct rtl8169_private *tp = netdev_priv(dev);
2252
2253         PREPARE_DELAYED_WORK(&tp->task, task);
2254         schedule_delayed_work(&tp->task, 4);
2255 }
2256
2257 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2258 {
2259         struct rtl8169_private *tp = netdev_priv(dev);
2260         void __iomem *ioaddr = tp->mmio_addr;
2261
2262         synchronize_irq(dev->irq);
2263
2264         /* Wait for any pending NAPI task to complete */
2265         netif_poll_disable(dev);
2266
2267         rtl8169_irq_mask_and_ack(ioaddr);
2268
2269         netif_poll_enable(dev);
2270 }
2271
2272 static void rtl8169_reinit_task(struct work_struct *work)
2273 {
2274         struct rtl8169_private *tp =
2275                 container_of(work, struct rtl8169_private, task.work);
2276         struct net_device *dev = tp->dev;
2277         int ret;
2278
2279         rtnl_lock();
2280
2281         if (!netif_running(dev))
2282                 goto out_unlock;
2283
2284         rtl8169_wait_for_quiescence(dev);
2285         rtl8169_close(dev);
2286
2287         ret = rtl8169_open(dev);
2288         if (unlikely(ret < 0)) {
2289                 if (net_ratelimit() && netif_msg_drv(tp)) {
2290                         printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2291                                " Rescheduling.\n", dev->name, ret);
2292                 }
2293                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2294         }
2295
2296 out_unlock:
2297         rtnl_unlock();
2298 }
2299
2300 static void rtl8169_reset_task(struct work_struct *work)
2301 {
2302         struct rtl8169_private *tp =
2303                 container_of(work, struct rtl8169_private, task.work);
2304         struct net_device *dev = tp->dev;
2305
2306         rtnl_lock();
2307
2308         if (!netif_running(dev))
2309                 goto out_unlock;
2310
2311         rtl8169_wait_for_quiescence(dev);
2312
2313         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2314         rtl8169_tx_clear(tp);
2315
2316         if (tp->dirty_rx == tp->cur_rx) {
2317                 rtl8169_init_ring_indexes(tp);
2318                 rtl_hw_start(dev);
2319                 netif_wake_queue(dev);
2320         } else {
2321                 if (net_ratelimit() && netif_msg_intr(tp)) {
2322                         printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2323                                dev->name);
2324                 }
2325                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2326         }
2327
2328 out_unlock:
2329         rtnl_unlock();
2330 }
2331
2332 static void rtl8169_tx_timeout(struct net_device *dev)
2333 {
2334         struct rtl8169_private *tp = netdev_priv(dev);
2335
2336         rtl8169_hw_reset(tp->mmio_addr);
2337
2338         /* Let's wait a bit while any (async) irq lands on */
2339         rtl8169_schedule_work(dev, rtl8169_reset_task);
2340 }
2341
2342 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2343                               u32 opts1)
2344 {
2345         struct skb_shared_info *info = skb_shinfo(skb);
2346         unsigned int cur_frag, entry;
2347         struct TxDesc * uninitialized_var(txd);
2348
2349         entry = tp->cur_tx;
2350         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2351                 skb_frag_t *frag = info->frags + cur_frag;
2352                 dma_addr_t mapping;
2353                 u32 status, len;
2354                 void *addr;
2355
2356                 entry = (entry + 1) % NUM_TX_DESC;
2357
2358                 txd = tp->TxDescArray + entry;
2359                 len = frag->size;
2360                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2361                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2362
2363                 /* anti gcc 2.95.3 bugware (sic) */
2364                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2365
2366                 txd->opts1 = cpu_to_le32(status);
2367                 txd->addr = cpu_to_le64(mapping);
2368
2369                 tp->tx_skb[entry].len = len;
2370         }
2371
2372         if (cur_frag) {
2373                 tp->tx_skb[entry].skb = skb;
2374                 txd->opts1 |= cpu_to_le32(LastFrag);
2375         }
2376
2377         return cur_frag;
2378 }
2379
2380 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2381 {
2382         if (dev->features & NETIF_F_TSO) {
2383                 u32 mss = skb_shinfo(skb)->gso_size;
2384
2385                 if (mss)
2386                         return LargeSend | ((mss & MSSMask) << MSSShift);
2387         }
2388         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2389                 const struct iphdr *ip = ip_hdr(skb);
2390
2391                 if (ip->protocol == IPPROTO_TCP)
2392                         return IPCS | TCPCS;
2393                 else if (ip->protocol == IPPROTO_UDP)
2394                         return IPCS | UDPCS;
2395                 WARN_ON(1);     /* we need a WARN() */
2396         }
2397         return 0;
2398 }
2399
2400 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2401 {
2402         struct rtl8169_private *tp = netdev_priv(dev);
2403         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2404         struct TxDesc *txd = tp->TxDescArray + entry;
2405         void __iomem *ioaddr = tp->mmio_addr;
2406         dma_addr_t mapping;
2407         u32 status, len;
2408         u32 opts1;
2409         int ret = NETDEV_TX_OK;
2410
2411         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2412                 if (netif_msg_drv(tp)) {
2413                         printk(KERN_ERR
2414                                "%s: BUG! Tx Ring full when queue awake!\n",
2415                                dev->name);
2416                 }
2417                 goto err_stop;
2418         }
2419
2420         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2421                 goto err_stop;
2422
2423         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2424
2425         frags = rtl8169_xmit_frags(tp, skb, opts1);
2426         if (frags) {
2427                 len = skb_headlen(skb);
2428                 opts1 |= FirstFrag;
2429         } else {
2430                 len = skb->len;
2431
2432                 if (unlikely(len < ETH_ZLEN)) {
2433                         if (skb_padto(skb, ETH_ZLEN))
2434                                 goto err_update_stats;
2435                         len = ETH_ZLEN;
2436                 }
2437
2438                 opts1 |= FirstFrag | LastFrag;
2439                 tp->tx_skb[entry].skb = skb;
2440         }
2441
2442         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2443
2444         tp->tx_skb[entry].len = len;
2445         txd->addr = cpu_to_le64(mapping);
2446         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2447
2448         wmb();
2449
2450         /* anti gcc 2.95.3 bugware (sic) */
2451         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2452         txd->opts1 = cpu_to_le32(status);
2453
2454         dev->trans_start = jiffies;
2455
2456         tp->cur_tx += frags + 1;
2457
2458         smp_wmb();
2459
2460         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2461
2462         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2463                 netif_stop_queue(dev);
2464                 smp_rmb();
2465                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2466                         netif_wake_queue(dev);
2467         }
2468
2469 out:
2470         return ret;
2471
2472 err_stop:
2473         netif_stop_queue(dev);
2474         ret = NETDEV_TX_BUSY;
2475 err_update_stats:
2476         tp->stats.tx_dropped++;
2477         goto out;
2478 }
2479
2480 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2481 {
2482         struct rtl8169_private *tp = netdev_priv(dev);
2483         struct pci_dev *pdev = tp->pci_dev;
2484         void __iomem *ioaddr = tp->mmio_addr;
2485         u16 pci_status, pci_cmd;
2486
2487         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2488         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2489
2490         if (netif_msg_intr(tp)) {
2491                 printk(KERN_ERR
2492                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2493                        dev->name, pci_cmd, pci_status);
2494         }
2495
2496         /*
2497          * The recovery sequence below admits a very elaborated explanation:
2498          * - it seems to work;
2499          * - I did not see what else could be done;
2500          * - it makes iop3xx happy.
2501          *
2502          * Feel free to adjust to your needs.
2503          */
2504         if (pdev->broken_parity_status)
2505                 pci_cmd &= ~PCI_COMMAND_PARITY;
2506         else
2507                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2508
2509         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2510
2511         pci_write_config_word(pdev, PCI_STATUS,
2512                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2513                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2514                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2515
2516         /* The infamous DAC f*ckup only happens at boot time */
2517         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2518                 if (netif_msg_intr(tp))
2519                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2520                 tp->cp_cmd &= ~PCIDAC;
2521                 RTL_W16(CPlusCmd, tp->cp_cmd);
2522                 dev->features &= ~NETIF_F_HIGHDMA;
2523         }
2524
2525         rtl8169_hw_reset(ioaddr);
2526
2527         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2528 }
2529
2530 static void rtl8169_tx_interrupt(struct net_device *dev,
2531                                  struct rtl8169_private *tp,
2532                                  void __iomem *ioaddr)
2533 {
2534         unsigned int dirty_tx, tx_left;
2535
2536         dirty_tx = tp->dirty_tx;
2537         smp_rmb();
2538         tx_left = tp->cur_tx - dirty_tx;
2539
2540         while (tx_left > 0) {
2541                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2542                 struct ring_info *tx_skb = tp->tx_skb + entry;
2543                 u32 len = tx_skb->len;
2544                 u32 status;
2545
2546                 rmb();
2547                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2548                 if (status & DescOwn)
2549                         break;
2550
2551                 tp->stats.tx_bytes += len;
2552                 tp->stats.tx_packets++;
2553
2554                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2555
2556                 if (status & LastFrag) {
2557                         dev_kfree_skb_irq(tx_skb->skb);
2558                         tx_skb->skb = NULL;
2559                 }
2560                 dirty_tx++;
2561                 tx_left--;
2562         }
2563
2564         if (tp->dirty_tx != dirty_tx) {
2565                 tp->dirty_tx = dirty_tx;
2566                 smp_wmb();
2567                 if (netif_queue_stopped(dev) &&
2568                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2569                         netif_wake_queue(dev);
2570                 }
2571         }
2572 }
2573
2574 static inline int rtl8169_fragmented_frame(u32 status)
2575 {
2576         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2577 }
2578
2579 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2580 {
2581         u32 opts1 = le32_to_cpu(desc->opts1);
2582         u32 status = opts1 & RxProtoMask;
2583
2584         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2585             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2586             ((status == RxProtoIP) && !(opts1 & IPFail)))
2587                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2588         else
2589                 skb->ip_summed = CHECKSUM_NONE;
2590 }
2591
2592 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2593                                        struct rtl8169_private *tp, int pkt_size,
2594                                        dma_addr_t addr)
2595 {
2596         struct sk_buff *skb;
2597         bool done = false;
2598
2599         if (pkt_size >= rx_copybreak)
2600                 goto out;
2601
2602         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2603         if (!skb)
2604                 goto out;
2605
2606         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2607                                     PCI_DMA_FROMDEVICE);
2608         skb_reserve(skb, NET_IP_ALIGN);
2609         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2610         *sk_buff = skb;
2611         done = true;
2612 out:
2613         return done;
2614 }
2615
2616 static int rtl8169_rx_interrupt(struct net_device *dev,
2617                                 struct rtl8169_private *tp,
2618                                 void __iomem *ioaddr)
2619 {
2620         unsigned int cur_rx, rx_left;
2621         unsigned int delta, count;
2622
2623         cur_rx = tp->cur_rx;
2624         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2625         rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2626
2627         for (; rx_left > 0; rx_left--, cur_rx++) {
2628                 unsigned int entry = cur_rx % NUM_RX_DESC;
2629                 struct RxDesc *desc = tp->RxDescArray + entry;
2630                 u32 status;
2631
2632                 rmb();
2633                 status = le32_to_cpu(desc->opts1);
2634
2635                 if (status & DescOwn)
2636                         break;
2637                 if (unlikely(status & RxRES)) {
2638                         if (netif_msg_rx_err(tp)) {
2639                                 printk(KERN_INFO
2640                                        "%s: Rx ERROR. status = %08x\n",
2641                                        dev->name, status);
2642                         }
2643                         tp->stats.rx_errors++;
2644                         if (status & (RxRWT | RxRUNT))
2645                                 tp->stats.rx_length_errors++;
2646                         if (status & RxCRC)
2647                                 tp->stats.rx_crc_errors++;
2648                         if (status & RxFOVF) {
2649                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2650                                 tp->stats.rx_fifo_errors++;
2651                         }
2652                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2653                 } else {
2654                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2655                         dma_addr_t addr = le64_to_cpu(desc->addr);
2656                         int pkt_size = (status & 0x00001FFF) - 4;
2657                         struct pci_dev *pdev = tp->pci_dev;
2658
2659                         /*
2660                          * The driver does not support incoming fragmented
2661                          * frames. They are seen as a symptom of over-mtu
2662                          * sized frames.
2663                          */
2664                         if (unlikely(rtl8169_fragmented_frame(status))) {
2665                                 tp->stats.rx_dropped++;
2666                                 tp->stats.rx_length_errors++;
2667                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2668                                 continue;
2669                         }
2670
2671                         rtl8169_rx_csum(skb, desc);
2672
2673                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2674                                 pci_dma_sync_single_for_device(pdev, addr,
2675                                         pkt_size, PCI_DMA_FROMDEVICE);
2676                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2677                         } else {
2678                                 pci_unmap_single(pdev, addr, pkt_size,
2679                                                  PCI_DMA_FROMDEVICE);
2680                                 tp->Rx_skbuff[entry] = NULL;
2681                         }
2682
2683                         skb_put(skb, pkt_size);
2684                         skb->protocol = eth_type_trans(skb, dev);
2685
2686                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2687                                 rtl8169_rx_skb(skb);
2688
2689                         dev->last_rx = jiffies;
2690                         tp->stats.rx_bytes += pkt_size;
2691                         tp->stats.rx_packets++;
2692                 }
2693
2694                 /* Work around for AMD plateform. */
2695                 if ((desc->opts2 & 0xfffe000) &&
2696                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2697                         desc->opts2 = 0;
2698                         cur_rx++;
2699                 }
2700         }
2701
2702         count = cur_rx - tp->cur_rx;
2703         tp->cur_rx = cur_rx;
2704
2705         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2706         if (!delta && count && netif_msg_intr(tp))
2707                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2708         tp->dirty_rx += delta;
2709
2710         /*
2711          * FIXME: until there is periodic timer to try and refill the ring,
2712          * a temporary shortage may definitely kill the Rx process.
2713          * - disable the asic to try and avoid an overflow and kick it again
2714          *   after refill ?
2715          * - how do others driver handle this condition (Uh oh...).
2716          */
2717         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2718                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2719
2720         return count;
2721 }
2722
2723 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2724 {
2725         struct net_device *dev = dev_instance;
2726         struct rtl8169_private *tp = netdev_priv(dev);
2727         int boguscnt = max_interrupt_work;
2728         void __iomem *ioaddr = tp->mmio_addr;
2729         int status;
2730         int handled = 0;
2731
2732         do {
2733                 status = RTL_R16(IntrStatus);
2734
2735                 /* hotplug/major error/no more work/shared irq */
2736                 if ((status == 0xFFFF) || !status)
2737                         break;
2738
2739                 handled = 1;
2740
2741                 if (unlikely(!netif_running(dev))) {
2742                         rtl8169_asic_down(ioaddr);
2743                         goto out;
2744                 }
2745
2746                 status &= tp->intr_mask;
2747                 RTL_W16(IntrStatus,
2748                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2749
2750                 if (!(status & tp->intr_event))
2751                         break;
2752
2753                 /* Work around for rx fifo overflow */
2754                 if (unlikely(status & RxFIFOOver) &&
2755                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2756                         netif_stop_queue(dev);
2757                         rtl8169_tx_timeout(dev);
2758                         break;
2759                 }
2760
2761                 if (unlikely(status & SYSErr)) {
2762                         rtl8169_pcierr_interrupt(dev);
2763                         break;
2764                 }
2765
2766                 if (status & LinkChg)
2767                         rtl8169_check_link_status(dev, tp, ioaddr);
2768
2769 #ifdef CONFIG_R8169_NAPI
2770                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2771                 tp->intr_mask = ~tp->napi_event;
2772
2773                 if (likely(netif_rx_schedule_prep(dev)))
2774                         __netif_rx_schedule(dev);
2775                 else if (netif_msg_intr(tp)) {
2776                         printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2777                                dev->name, status);
2778                 }
2779                 break;
2780 #else
2781                 /* Rx interrupt */
2782                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2783                         rtl8169_rx_interrupt(dev, tp, ioaddr);
2784
2785                 /* Tx interrupt */
2786                 if (status & (TxOK | TxErr))
2787                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2788 #endif
2789
2790                 boguscnt--;
2791         } while (boguscnt > 0);
2792
2793         if (boguscnt <= 0) {
2794                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2795                         printk(KERN_WARNING
2796                                "%s: Too much work at interrupt!\n", dev->name);
2797                 }
2798                 /* Clear all interrupt sources. */
2799                 RTL_W16(IntrStatus, 0xffff);
2800         }
2801 out:
2802         return IRQ_RETVAL(handled);
2803 }
2804
2805 #ifdef CONFIG_R8169_NAPI
2806 static int rtl8169_poll(struct net_device *dev, int *budget)
2807 {
2808         unsigned int work_done, work_to_do = min(*budget, dev->quota);
2809         struct rtl8169_private *tp = netdev_priv(dev);
2810         void __iomem *ioaddr = tp->mmio_addr;
2811
2812         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2813         rtl8169_tx_interrupt(dev, tp, ioaddr);
2814
2815         *budget -= work_done;
2816         dev->quota -= work_done;
2817
2818         if (work_done < work_to_do) {
2819                 netif_rx_complete(dev);
2820                 tp->intr_mask = 0xffff;
2821                 /*
2822                  * 20040426: the barrier is not strictly required but the
2823                  * behavior of the irq handler could be less predictable
2824                  * without it. Btw, the lack of flush for the posted pci
2825                  * write is safe - FR
2826                  */
2827                 smp_wmb();
2828                 RTL_W16(IntrMask, tp->intr_event);
2829         }
2830
2831         return (work_done >= work_to_do);
2832 }
2833 #endif
2834
2835 static void rtl8169_down(struct net_device *dev)
2836 {
2837         struct rtl8169_private *tp = netdev_priv(dev);
2838         void __iomem *ioaddr = tp->mmio_addr;
2839         unsigned int poll_locked = 0;
2840         unsigned int intrmask;
2841
2842         rtl8169_delete_timer(dev);
2843
2844         netif_stop_queue(dev);
2845
2846 core_down:
2847         spin_lock_irq(&tp->lock);
2848
2849         rtl8169_asic_down(ioaddr);
2850
2851         /* Update the error counts. */
2852         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2853         RTL_W32(RxMissed, 0);
2854
2855         spin_unlock_irq(&tp->lock);
2856
2857         synchronize_irq(dev->irq);
2858
2859         if (!poll_locked) {
2860                 netif_poll_disable(dev);
2861                 poll_locked++;
2862         }
2863
2864         /* Give a racing hard_start_xmit a few cycles to complete. */
2865         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2866
2867         /*
2868          * And now for the 50k$ question: are IRQ disabled or not ?
2869          *
2870          * Two paths lead here:
2871          * 1) dev->close
2872          *    -> netif_running() is available to sync the current code and the
2873          *       IRQ handler. See rtl8169_interrupt for details.
2874          * 2) dev->change_mtu
2875          *    -> rtl8169_poll can not be issued again and re-enable the
2876          *       interruptions. Let's simply issue the IRQ down sequence again.
2877          *
2878          * No loop if hotpluged or major error (0xffff).
2879          */
2880         intrmask = RTL_R16(IntrMask);
2881         if (intrmask && (intrmask != 0xffff))
2882                 goto core_down;
2883
2884         rtl8169_tx_clear(tp);
2885
2886         rtl8169_rx_clear(tp);
2887 }
2888
2889 static int rtl8169_close(struct net_device *dev)
2890 {
2891         struct rtl8169_private *tp = netdev_priv(dev);
2892         struct pci_dev *pdev = tp->pci_dev;
2893
2894         rtl8169_down(dev);
2895
2896         free_irq(dev->irq, dev);
2897
2898         netif_poll_enable(dev);
2899
2900         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2901                             tp->RxPhyAddr);
2902         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2903                             tp->TxPhyAddr);
2904         tp->TxDescArray = NULL;
2905         tp->RxDescArray = NULL;
2906
2907         return 0;
2908 }
2909
2910 static void rtl_set_rx_mode(struct net_device *dev)
2911 {
2912         struct rtl8169_private *tp = netdev_priv(dev);
2913         void __iomem *ioaddr = tp->mmio_addr;
2914         unsigned long flags;
2915         u32 mc_filter[2];       /* Multicast hash filter */
2916         int rx_mode;
2917         u32 tmp = 0;
2918
2919         if (dev->flags & IFF_PROMISC) {
2920                 /* Unconditionally log net taps. */
2921                 if (netif_msg_link(tp)) {
2922                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2923                                dev->name);
2924                 }
2925                 rx_mode =
2926                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2927                     AcceptAllPhys;
2928                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2929         } else if ((dev->mc_count > multicast_filter_limit)
2930                    || (dev->flags & IFF_ALLMULTI)) {
2931                 /* Too many to filter perfectly -- accept all multicasts. */
2932                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2933                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2934         } else {
2935                 struct dev_mc_list *mclist;
2936                 unsigned int i;
2937
2938                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2939                 mc_filter[1] = mc_filter[0] = 0;
2940                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2941                      i++, mclist = mclist->next) {
2942                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2943                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2944                         rx_mode |= AcceptMulticast;
2945                 }
2946         }
2947
2948         spin_lock_irqsave(&tp->lock, flags);
2949
2950         tmp = rtl8169_rx_config | rx_mode |
2951               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2952
2953         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2954             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2955             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2956             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2957             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2958                 mc_filter[0] = 0xffffffff;
2959                 mc_filter[1] = 0xffffffff;
2960         }
2961
2962         RTL_W32(MAR0 + 0, mc_filter[0]);
2963         RTL_W32(MAR0 + 4, mc_filter[1]);
2964
2965         RTL_W32(RxConfig, tmp);
2966
2967         spin_unlock_irqrestore(&tp->lock, flags);
2968 }
2969
2970 /**
2971  *  rtl8169_get_stats - Get rtl8169 read/write statistics
2972  *  @dev: The Ethernet Device to get statistics for
2973  *
2974  *  Get TX/RX statistics for rtl8169
2975  */
2976 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2977 {
2978         struct rtl8169_private *tp = netdev_priv(dev);
2979         void __iomem *ioaddr = tp->mmio_addr;
2980         unsigned long flags;
2981
2982         if (netif_running(dev)) {
2983                 spin_lock_irqsave(&tp->lock, flags);
2984                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2985                 RTL_W32(RxMissed, 0);
2986                 spin_unlock_irqrestore(&tp->lock, flags);
2987         }
2988
2989         return &tp->stats;
2990 }
2991
2992 #ifdef CONFIG_PM
2993
2994 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2995 {
2996         struct net_device *dev = pci_get_drvdata(pdev);
2997         struct rtl8169_private *tp = netdev_priv(dev);
2998         void __iomem *ioaddr = tp->mmio_addr;
2999
3000         if (!netif_running(dev))
3001                 goto out_pci_suspend;
3002
3003         netif_device_detach(dev);
3004         netif_stop_queue(dev);
3005
3006         spin_lock_irq(&tp->lock);
3007
3008         rtl8169_asic_down(ioaddr);
3009
3010         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3011         RTL_W32(RxMissed, 0);
3012
3013         spin_unlock_irq(&tp->lock);
3014
3015 out_pci_suspend:
3016         pci_save_state(pdev);
3017         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3018         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3019
3020         return 0;
3021 }
3022
3023 static int rtl8169_resume(struct pci_dev *pdev)
3024 {
3025         struct net_device *dev = pci_get_drvdata(pdev);
3026
3027         pci_set_power_state(pdev, PCI_D0);
3028         pci_restore_state(pdev);
3029         pci_enable_wake(pdev, PCI_D0, 0);
3030
3031         if (!netif_running(dev))
3032                 goto out;
3033
3034         netif_device_attach(dev);
3035
3036         rtl8169_schedule_work(dev, rtl8169_reset_task);
3037 out:
3038         return 0;
3039 }
3040
3041 #endif /* CONFIG_PM */
3042
3043 static struct pci_driver rtl8169_pci_driver = {
3044         .name           = MODULENAME,
3045         .id_table       = rtl8169_pci_tbl,
3046         .probe          = rtl8169_init_one,
3047         .remove         = __devexit_p(rtl8169_remove_one),
3048 #ifdef CONFIG_PM
3049         .suspend        = rtl8169_suspend,
3050         .resume         = rtl8169_resume,
3051 #endif
3052 };
3053
3054 static int __init rtl8169_init_module(void)
3055 {
3056         return pci_register_driver(&rtl8169_pci_driver);
3057 }
3058
3059 static void __exit rtl8169_cleanup_module(void)
3060 {
3061         pci_unregister_driver(&rtl8169_pci_driver);
3062 }
3063
3064 module_init(rtl8169_init_module);
3065 module_exit(rtl8169_cleanup_module);