2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
50 #include <asm/processor.h>
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
65 /* RDC MAC I/O Size */
66 #define R6040_IO_SIZE 256
72 #define MCR0 0x00 /* Control register 0 */
73 #define MCR1 0x04 /* Control register 1 */
74 #define MAC_RST 0x0001 /* Reset the MAC */
75 #define MBCR 0x08 /* Bus control */
76 #define MT_ICR 0x0C /* TX interrupt control */
77 #define MR_ICR 0x10 /* RX interrupt control */
78 #define MTPR 0x14 /* TX poll command register */
79 #define MR_BSR 0x18 /* RX buffer size */
80 #define MR_DCR 0x1A /* RX descriptor control */
81 #define MLSR 0x1C /* Last status */
82 #define MMDIO 0x20 /* MDIO control register */
83 #define MDIO_WRITE 0x4000 /* MDIO write */
84 #define MDIO_READ 0x2000 /* MDIO read */
85 #define MMRD 0x24 /* MDIO read data register */
86 #define MMWD 0x28 /* MDIO write data register */
87 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
88 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
89 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
90 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
91 #define MISR 0x3C /* Status register */
92 #define MIER 0x40 /* INT enable register */
93 #define MSK_INT 0x0000 /* Mask off interrupts */
94 #define RX_FINISH 0x0001 /* RX finished */
95 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
96 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
97 #define RX_EARLY 0x0008 /* RX early */
98 #define TX_FINISH 0x0010 /* TX finished */
99 #define TX_EARLY 0x0080 /* TX early */
100 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
101 #define LINK_CHANGED 0x0200 /* PHY link changed */
102 #define ME_CISR 0x44 /* Event counter INT status */
103 #define ME_CIER 0x48 /* Event counter INT enable */
104 #define MR_CNT 0x50 /* Successfully received packet counter */
105 #define ME_CNT0 0x52 /* Event counter 0 */
106 #define ME_CNT1 0x54 /* Event counter 1 */
107 #define ME_CNT2 0x56 /* Event counter 2 */
108 #define ME_CNT3 0x58 /* Event counter 3 */
109 #define MT_CNT 0x5A /* Successfully transmit packet counter */
110 #define ME_CNT4 0x5C /* Event counter 4 */
111 #define MP_CNT 0x5E /* Pause frame counter register */
112 #define MAR0 0x60 /* Hash table 0 */
113 #define MAR1 0x62 /* Hash table 1 */
114 #define MAR2 0x64 /* Hash table 2 */
115 #define MAR3 0x66 /* Hash table 3 */
116 #define MID_0L 0x68 /* Multicast address MID0 Low */
117 #define MID_0M 0x6A /* Multicast address MID0 Medium */
118 #define MID_0H 0x6C /* Multicast address MID0 High */
119 #define MID_1L 0x70 /* MID1 Low */
120 #define MID_1M 0x72 /* MID1 Medium */
121 #define MID_1H 0x74 /* MID1 High */
122 #define MID_2L 0x78 /* MID2 Low */
123 #define MID_2M 0x7A /* MID2 Medium */
124 #define MID_2H 0x7C /* MID2 High */
125 #define MID_3L 0x80 /* MID3 Low */
126 #define MID_3M 0x82 /* MID3 Medium */
127 #define MID_3H 0x84 /* MID3 High */
128 #define PHY_CC 0x88 /* PHY status change configuration register */
129 #define PHY_ST 0x8A /* PHY status register */
130 #define MAC_SM 0xAC /* MAC status machine */
131 #define MAC_ID 0xBE /* Identifier register */
133 #define TX_DCNT 0x80 /* TX descriptor count */
134 #define RX_DCNT 0x80 /* RX descriptor count */
135 #define MAX_BUF_SIZE 0x600
136 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
137 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
138 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
142 #define ICPLUS_PHY_ID 0x0243
144 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
145 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
146 "Florian Fainelli <florian@openwrt.org>");
147 MODULE_LICENSE("GPL");
148 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
150 /* RX and TX interrupts that we handle */
151 #define RX_INT (RX_FINISH)
152 #define TX_INT (TX_FINISH)
153 #define INT_MASK (RX_INT | TX_INT)
155 struct r6040_descriptor {
156 u16 status, len; /* 0-3 */
157 __le32 buf; /* 4-7 */
158 __le32 ndesc; /* 8-B */
160 char *vbufp; /* 10-13 */
161 struct r6040_descriptor *vndescp; /* 14-17 */
162 struct sk_buff *skb_ptr; /* 18-1B */
163 u32 rev2; /* 1C-1F */
164 } __attribute__((aligned(32)));
166 struct r6040_private {
167 spinlock_t lock; /* driver lock */
168 struct timer_list timer;
169 struct pci_dev *pdev;
170 struct r6040_descriptor *rx_insert_ptr;
171 struct r6040_descriptor *rx_remove_ptr;
172 struct r6040_descriptor *tx_insert_ptr;
173 struct r6040_descriptor *tx_remove_ptr;
174 struct r6040_descriptor *rx_ring;
175 struct r6040_descriptor *tx_ring;
176 dma_addr_t rx_ring_dma;
177 dma_addr_t tx_ring_dma;
178 u16 tx_free_desc, phy_addr, phy_mode;
181 struct net_device *dev;
182 struct mii_if_info mii_if;
183 struct napi_struct napi;
187 static char version[] __devinitdata = KERN_INFO DRV_NAME
188 ": RDC R6040 NAPI net driver,"
189 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
191 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
193 /* Read a word data from PHY Chip */
194 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
199 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
200 /* Wait for the read bit to be cleared */
202 cmd = ioread16(ioaddr + MMDIO);
207 return ioread16(ioaddr + MMRD);
210 /* Write a word data from PHY Chip */
211 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
216 iowrite16(val, ioaddr + MMWD);
217 /* Write the command to the MDIO bus */
218 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
219 /* Wait for the write bit to be cleared */
221 cmd = ioread16(ioaddr + MMDIO);
222 if (cmd & MDIO_WRITE)
227 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
229 struct r6040_private *lp = netdev_priv(dev);
230 void __iomem *ioaddr = lp->base;
232 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
235 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
237 struct r6040_private *lp = netdev_priv(dev);
238 void __iomem *ioaddr = lp->base;
240 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
243 static void r6040_free_txbufs(struct net_device *dev)
245 struct r6040_private *lp = netdev_priv(dev);
248 for (i = 0; i < TX_DCNT; i++) {
249 if (lp->tx_insert_ptr->skb_ptr) {
250 pci_unmap_single(lp->pdev,
251 le32_to_cpu(lp->tx_insert_ptr->buf),
252 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
253 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
254 lp->rx_insert_ptr->skb_ptr = NULL;
256 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
260 static void r6040_free_rxbufs(struct net_device *dev)
262 struct r6040_private *lp = netdev_priv(dev);
265 for (i = 0; i < RX_DCNT; i++) {
266 if (lp->rx_insert_ptr->skb_ptr) {
267 pci_unmap_single(lp->pdev,
268 le32_to_cpu(lp->rx_insert_ptr->buf),
269 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
270 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
271 lp->rx_insert_ptr->skb_ptr = NULL;
273 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
277 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
278 dma_addr_t desc_dma, int size)
280 struct r6040_descriptor *desc = desc_ring;
281 dma_addr_t mapping = desc_dma;
284 mapping += sizeof(*desc);
285 desc->ndesc = cpu_to_le32(mapping);
286 desc->vndescp = desc + 1;
290 desc->ndesc = cpu_to_le32(desc_dma);
291 desc->vndescp = desc_ring;
294 static void r6040_init_txbufs(struct net_device *dev)
296 struct r6040_private *lp = netdev_priv(dev);
298 lp->tx_free_desc = TX_DCNT;
300 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
301 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
304 static int r6040_alloc_rxbufs(struct net_device *dev)
306 struct r6040_private *lp = netdev_priv(dev);
307 struct r6040_descriptor *desc;
311 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
312 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
314 /* Allocate skbs for the rx descriptors */
317 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
319 printk(KERN_ERR "%s: failed to alloc skb for rx\n", dev->name);
324 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
326 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
327 desc->status = 0x8000;
328 desc = desc->vndescp;
329 } while (desc != lp->rx_ring);
334 /* Deallocate all previously allocated skbs */
335 r6040_free_rxbufs(dev);
339 static void r6040_init_mac_regs(struct net_device *dev)
341 struct r6040_private *lp = netdev_priv(dev);
342 void __iomem *ioaddr = lp->base;
346 /* Mask Off Interrupt */
347 iowrite16(MSK_INT, ioaddr + MIER);
350 iowrite16(MAC_RST, ioaddr + MCR1);
352 cmd = ioread16(ioaddr + MCR1);
356 /* Reset internal state machine */
357 iowrite16(2, ioaddr + MAC_SM);
358 iowrite16(0, ioaddr + MAC_SM);
361 /* MAC Bus Control Register */
362 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
364 /* Buffer Size Register */
365 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
367 /* Write TX ring start address */
368 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
369 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
371 /* Write RX ring start address */
372 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
373 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
375 /* Set interrupt waiting time and packet numbers */
376 iowrite16(0x0F06, ioaddr + MT_ICR);
377 iowrite16(0x0F06, ioaddr + MR_ICR);
379 /* Enable interrupts */
380 iowrite16(INT_MASK, ioaddr + MIER);
382 /* Enable TX and RX */
383 iowrite16(lp->mcr0 | 0x0002, ioaddr);
385 /* Let TX poll the descriptors
386 * we may got called by r6040_tx_timeout which has left
387 * some unsent tx buffers */
388 iowrite16(0x01, ioaddr + MTPR);
391 static void r6040_tx_timeout(struct net_device *dev)
393 struct r6040_private *priv = netdev_priv(dev);
394 void __iomem *ioaddr = priv->base;
396 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
397 "status %4.4x, PHY status %4.4x\n",
398 dev->name, ioread16(ioaddr + MIER),
399 ioread16(ioaddr + MISR),
400 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
402 dev->stats.tx_errors++;
404 /* Reset MAC and re-init all registers */
405 r6040_init_mac_regs(dev);
408 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
410 struct r6040_private *priv = netdev_priv(dev);
411 void __iomem *ioaddr = priv->base;
414 spin_lock_irqsave(&priv->lock, flags);
415 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
416 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
417 spin_unlock_irqrestore(&priv->lock, flags);
422 /* Stop RDC MAC and Free the allocated resource */
423 static void r6040_down(struct net_device *dev)
425 struct r6040_private *lp = netdev_priv(dev);
426 void __iomem *ioaddr = lp->base;
427 struct pci_dev *pdev = lp->pdev;
433 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
434 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
436 cmd = ioread16(ioaddr + MCR1);
441 /* Restore MAC Address to MIDx */
442 adrp = (u16 *) dev->dev_addr;
443 iowrite16(adrp[0], ioaddr + MID_0L);
444 iowrite16(adrp[1], ioaddr + MID_0M);
445 iowrite16(adrp[2], ioaddr + MID_0H);
446 free_irq(dev->irq, dev);
449 r6040_free_rxbufs(dev);
452 r6040_free_txbufs(dev);
454 /* Free Descriptor memory */
455 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
456 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
459 static int r6040_close(struct net_device *dev)
461 struct r6040_private *lp = netdev_priv(dev);
464 del_timer_sync(&lp->timer);
466 spin_lock_irq(&lp->lock);
467 napi_disable(&lp->napi);
468 netif_stop_queue(dev);
470 spin_unlock_irq(&lp->lock);
475 /* Status of PHY CHIP */
476 static int r6040_phy_mode_chk(struct net_device *dev)
478 struct r6040_private *lp = netdev_priv(dev);
479 void __iomem *ioaddr = lp->base;
482 /* PHY Link Status Check */
483 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
484 if (!(phy_dat & 0x4))
485 phy_dat = 0x8000; /* Link Failed, full duplex */
487 /* PHY Chip Auto-Negotiation Status */
488 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
489 if (phy_dat & 0x0020) {
490 /* Auto Negotiation Mode */
491 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
492 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
494 /* Force full duplex */
500 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
510 static void r6040_set_carrier(struct mii_if_info *mii)
512 if (r6040_phy_mode_chk(mii->dev)) {
513 /* autoneg is off: Link is always assumed to be up */
514 if (!netif_carrier_ok(mii->dev))
515 netif_carrier_on(mii->dev);
517 r6040_phy_mode_chk(mii->dev);
520 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
522 struct r6040_private *lp = netdev_priv(dev);
523 struct mii_ioctl_data *data = if_mii(rq);
526 if (!netif_running(dev))
528 spin_lock_irq(&lp->lock);
529 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
530 spin_unlock_irq(&lp->lock);
531 r6040_set_carrier(&lp->mii_if);
535 static int r6040_rx(struct net_device *dev, int limit)
537 struct r6040_private *priv = netdev_priv(dev);
538 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
539 struct sk_buff *skb_ptr, *new_skb;
543 /* Limit not reached and the descriptor belongs to the CPU */
544 while (count < limit && !(descptr->status & 0x8000)) {
545 /* Read the descriptor status */
546 err = descptr->status;
547 /* Global error status set */
551 dev->stats.rx_frame_errors++;
552 /* Buffer lenght exceeded */
554 dev->stats.rx_length_errors++;
555 /* Packet too long */
557 dev->stats.rx_length_errors++;
558 /* Packet < 64 bytes */
560 dev->stats.rx_length_errors++;
563 spin_lock(&priv->lock);
564 dev->stats.rx_crc_errors++;
565 spin_unlock(&priv->lock);
570 /* Packet successfully received */
571 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
573 dev->stats.rx_dropped++;
576 skb_ptr = descptr->skb_ptr;
577 skb_ptr->dev = priv->dev;
579 /* Do not count the CRC */
580 skb_put(skb_ptr, descptr->len - 4);
581 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
582 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
583 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
585 /* Send to upper layer */
586 netif_receive_skb(skb_ptr);
587 dev->last_rx = jiffies;
588 dev->stats.rx_packets++;
589 dev->stats.rx_bytes += descptr->len - 4;
591 /* put new skb into descriptor */
592 descptr->skb_ptr = new_skb;
593 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
594 descptr->skb_ptr->data,
595 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
598 /* put the descriptor back to the MAC */
599 descptr->status = 0x8000;
600 descptr = descptr->vndescp;
603 priv->rx_remove_ptr = descptr;
608 static void r6040_tx(struct net_device *dev)
610 struct r6040_private *priv = netdev_priv(dev);
611 struct r6040_descriptor *descptr;
612 void __iomem *ioaddr = priv->base;
613 struct sk_buff *skb_ptr;
616 spin_lock(&priv->lock);
617 descptr = priv->tx_remove_ptr;
618 while (priv->tx_free_desc < TX_DCNT) {
619 /* Check for errors */
620 err = ioread16(ioaddr + MLSR);
623 dev->stats.rx_fifo_errors++;
624 if (err & (0x2000 | 0x4000))
625 dev->stats.tx_carrier_errors++;
627 if (descptr->status & 0x8000)
628 break; /* Not complete */
629 skb_ptr = descptr->skb_ptr;
630 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
631 skb_ptr->len, PCI_DMA_TODEVICE);
633 dev_kfree_skb_irq(skb_ptr);
634 descptr->skb_ptr = NULL;
635 /* To next descriptor */
636 descptr = descptr->vndescp;
637 priv->tx_free_desc++;
639 priv->tx_remove_ptr = descptr;
641 if (priv->tx_free_desc)
642 netif_wake_queue(dev);
643 spin_unlock(&priv->lock);
646 static int r6040_poll(struct napi_struct *napi, int budget)
648 struct r6040_private *priv =
649 container_of(napi, struct r6040_private, napi);
650 struct net_device *dev = priv->dev;
651 void __iomem *ioaddr = priv->base;
654 work_done = r6040_rx(dev, budget);
656 if (work_done < budget) {
657 netif_rx_complete(dev, napi);
658 /* Enable RX interrupt */
659 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
664 /* The RDC interrupt handler. */
665 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
667 struct net_device *dev = dev_id;
668 struct r6040_private *lp = netdev_priv(dev);
669 void __iomem *ioaddr = lp->base;
672 /* Mask off RDC MAC interrupt */
673 iowrite16(MSK_INT, ioaddr + MIER);
674 /* Read MISR status and clear */
675 status = ioread16(ioaddr + MISR);
677 if (status == 0x0000 || status == 0xffff)
680 /* RX interrupt request */
682 /* Mask off RX interrupt */
683 iowrite16(ioread16(ioaddr + MIER) & ~RX_INT, ioaddr + MIER);
684 netif_rx_schedule(dev, &lp->napi);
687 /* TX interrupt request */
694 #ifdef CONFIG_NET_POLL_CONTROLLER
695 static void r6040_poll_controller(struct net_device *dev)
697 disable_irq(dev->irq);
698 r6040_interrupt(dev->irq, dev);
699 enable_irq(dev->irq);
704 static int r6040_up(struct net_device *dev)
706 struct r6040_private *lp = netdev_priv(dev);
707 void __iomem *ioaddr = lp->base;
710 /* Initialise and alloc RX/TX buffers */
711 r6040_init_txbufs(dev);
712 ret = r6040_alloc_rxbufs(dev);
716 /* Read the PHY ID */
717 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
719 if (lp->switch_sig == ICPLUS_PHY_ID) {
720 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
721 lp->phy_mode = 0x8000;
724 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
725 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
727 if (PHY_MODE == 0x3100)
728 lp->phy_mode = r6040_phy_mode_chk(dev);
730 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
733 /* Set duplex mode */
734 lp->mcr0 |= lp->phy_mode;
736 /* improve performance (by RDC guys) */
737 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
738 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
739 r6040_phy_write(ioaddr, 0, 19, 0x0000);
740 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
742 /* Initialize all MAC registers */
743 r6040_init_mac_regs(dev);
749 A periodic timer routine
750 Polling PHY Chip Link Status
752 static void r6040_timer(unsigned long data)
754 struct net_device *dev = (struct net_device *)data;
755 struct r6040_private *lp = netdev_priv(dev);
756 void __iomem *ioaddr = lp->base;
759 /* Polling PHY Chip Status */
760 if (PHY_MODE == 0x3100)
761 phy_mode = r6040_phy_mode_chk(dev);
763 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
765 if (phy_mode != lp->phy_mode) {
766 lp->phy_mode = phy_mode;
767 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
768 iowrite16(lp->mcr0, ioaddr);
769 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
772 /* Timer active again */
773 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
776 /* Read/set MAC address routines */
777 static void r6040_mac_address(struct net_device *dev)
779 struct r6040_private *lp = netdev_priv(dev);
780 void __iomem *ioaddr = lp->base;
783 /* MAC operation register */
784 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
785 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
786 iowrite16(0, ioaddr + MAC_SM);
789 /* Restore MAC Address */
790 adrp = (u16 *) dev->dev_addr;
791 iowrite16(adrp[0], ioaddr + MID_0L);
792 iowrite16(adrp[1], ioaddr + MID_0M);
793 iowrite16(adrp[2], ioaddr + MID_0H);
796 static int r6040_open(struct net_device *dev)
798 struct r6040_private *lp = netdev_priv(dev);
801 /* Request IRQ and Register interrupt handler */
802 ret = request_irq(dev->irq, &r6040_interrupt,
803 IRQF_SHARED, dev->name, dev);
807 /* Set MAC address */
808 r6040_mac_address(dev);
810 /* Allocate Descriptor memory */
812 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
817 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
819 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
826 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
828 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
833 napi_enable(&lp->napi);
834 netif_start_queue(dev);
836 /* set and active a timer process */
837 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
838 if (lp->switch_sig != ICPLUS_PHY_ID)
839 mod_timer(&lp->timer, jiffies + HZ);
843 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
845 struct r6040_private *lp = netdev_priv(dev);
846 struct r6040_descriptor *descptr;
847 void __iomem *ioaddr = lp->base;
849 int ret = NETDEV_TX_OK;
851 /* Critical Section */
852 spin_lock_irqsave(&lp->lock, flags);
854 /* TX resource check */
855 if (!lp->tx_free_desc) {
856 spin_unlock_irqrestore(&lp->lock, flags);
857 netif_stop_queue(dev);
858 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
859 ret = NETDEV_TX_BUSY;
863 /* Statistic Counter */
864 dev->stats.tx_packets++;
865 dev->stats.tx_bytes += skb->len;
866 /* Set TX descriptor & Transmit it */
868 descptr = lp->tx_insert_ptr;
872 descptr->len = skb->len;
874 descptr->skb_ptr = skb;
875 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
876 skb->data, skb->len, PCI_DMA_TODEVICE));
877 descptr->status = 0x8000;
878 /* Trigger the MAC to check the TX descriptor */
879 iowrite16(0x01, ioaddr + MTPR);
880 lp->tx_insert_ptr = descptr->vndescp;
882 /* If no tx resource, stop */
883 if (!lp->tx_free_desc)
884 netif_stop_queue(dev);
886 dev->trans_start = jiffies;
887 spin_unlock_irqrestore(&lp->lock, flags);
891 static void r6040_multicast_list(struct net_device *dev)
893 struct r6040_private *lp = netdev_priv(dev);
894 void __iomem *ioaddr = lp->base;
898 struct dev_mc_list *dmi = dev->mc_list;
902 adrp = (u16 *)dev->dev_addr;
903 iowrite16(adrp[0], ioaddr + MID_0L);
904 iowrite16(adrp[1], ioaddr + MID_0M);
905 iowrite16(adrp[2], ioaddr + MID_0H);
907 /* Promiscous Mode */
908 spin_lock_irqsave(&lp->lock, flags);
910 /* Clear AMCP & PROM bits */
911 reg = ioread16(ioaddr) & ~0x0120;
912 if (dev->flags & IFF_PROMISC) {
916 /* Too many multicast addresses
917 * accept all traffic */
918 else if ((dev->mc_count > MCAST_MAX)
919 || (dev->flags & IFF_ALLMULTI))
922 iowrite16(reg, ioaddr);
923 spin_unlock_irqrestore(&lp->lock, flags);
925 /* Build the hash table */
926 if (dev->mc_count > MCAST_MAX) {
930 for (i = 0; i < 4; i++)
933 for (i = 0; i < dev->mc_count; i++) {
934 char *addrs = dmi->dmi_addr;
941 crc = ether_crc_le(6, addrs);
943 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
945 /* Write the index of the hash table */
946 for (i = 0; i < 4; i++)
947 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
948 /* Fill the MAC hash tables with their values */
949 iowrite16(hash_table[0], ioaddr + MAR0);
950 iowrite16(hash_table[1], ioaddr + MAR1);
951 iowrite16(hash_table[2], ioaddr + MAR2);
952 iowrite16(hash_table[3], ioaddr + MAR3);
954 /* Multicast Address 1~4 case */
955 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
956 adrp = (u16 *)dmi->dmi_addr;
957 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
958 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
959 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
962 for (i = dev->mc_count; i < MCAST_MAX; i++) {
963 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
964 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
965 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
969 static void netdev_get_drvinfo(struct net_device *dev,
970 struct ethtool_drvinfo *info)
972 struct r6040_private *rp = netdev_priv(dev);
974 strcpy(info->driver, DRV_NAME);
975 strcpy(info->version, DRV_VERSION);
976 strcpy(info->bus_info, pci_name(rp->pdev));
979 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
981 struct r6040_private *rp = netdev_priv(dev);
984 spin_lock_irq(&rp->lock);
985 rc = mii_ethtool_gset(&rp->mii_if, cmd);
986 spin_unlock_irq(&rp->lock);
991 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
993 struct r6040_private *rp = netdev_priv(dev);
996 spin_lock_irq(&rp->lock);
997 rc = mii_ethtool_sset(&rp->mii_if, cmd);
998 spin_unlock_irq(&rp->lock);
999 r6040_set_carrier(&rp->mii_if);
1004 static u32 netdev_get_link(struct net_device *dev)
1006 struct r6040_private *rp = netdev_priv(dev);
1008 return mii_link_ok(&rp->mii_if);
1011 static struct ethtool_ops netdev_ethtool_ops = {
1012 .get_drvinfo = netdev_get_drvinfo,
1013 .get_settings = netdev_get_settings,
1014 .set_settings = netdev_set_settings,
1015 .get_link = netdev_get_link,
1018 static int __devinit r6040_init_one(struct pci_dev *pdev,
1019 const struct pci_device_id *ent)
1021 struct net_device *dev;
1022 struct r6040_private *lp;
1023 void __iomem *ioaddr;
1024 int err, io_size = R6040_IO_SIZE;
1025 static int card_idx = -1;
1030 printk(KERN_INFO "%s\n", version);
1032 err = pci_enable_device(pdev);
1036 /* this should always be supported */
1037 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1038 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1039 "not supported by the card\n");
1042 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1043 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1044 "not supported by the card\n");
1049 if (pci_resource_len(pdev, 0) < io_size) {
1050 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1054 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1055 pci_set_master(pdev);
1057 dev = alloc_etherdev(sizeof(struct r6040_private));
1059 printk(KERN_ERR "Failed to allocate etherdev\n");
1062 SET_NETDEV_DEV(dev, &pdev->dev);
1063 lp = netdev_priv(dev);
1065 if (pci_request_regions(pdev, DRV_NAME)) {
1066 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1068 goto err_out_disable;
1071 ioaddr = pci_iomap(pdev, bar, io_size);
1073 printk(KERN_ERR "ioremap failed for device %s\n",
1078 /* Init system & device */
1080 dev->irq = pdev->irq;
1082 spin_lock_init(&lp->lock);
1083 pci_set_drvdata(pdev, dev);
1085 /* Set MAC address */
1088 adrp = (u16 *)dev->dev_addr;
1089 adrp[0] = ioread16(ioaddr + MID_0L);
1090 adrp[1] = ioread16(ioaddr + MID_0M);
1091 adrp[2] = ioread16(ioaddr + MID_0H);
1093 /* Link new device into r6040_root_dev */
1097 /* Init RDC private data */
1099 lp->phy_addr = phy_table[card_idx];
1102 /* The RDC-specific entries in the device structure. */
1103 dev->open = &r6040_open;
1104 dev->hard_start_xmit = &r6040_start_xmit;
1105 dev->stop = &r6040_close;
1106 dev->get_stats = r6040_get_stats;
1107 dev->set_multicast_list = &r6040_multicast_list;
1108 dev->do_ioctl = &r6040_ioctl;
1109 dev->ethtool_ops = &netdev_ethtool_ops;
1110 dev->tx_timeout = &r6040_tx_timeout;
1111 dev->watchdog_timeo = TX_TIMEOUT;
1112 #ifdef CONFIG_NET_POLL_CONTROLLER
1113 dev->poll_controller = r6040_poll_controller;
1115 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1116 lp->mii_if.dev = dev;
1117 lp->mii_if.mdio_read = r6040_mdio_read;
1118 lp->mii_if.mdio_write = r6040_mdio_write;
1119 lp->mii_if.phy_id = lp->phy_addr;
1120 lp->mii_if.phy_id_mask = 0x1f;
1121 lp->mii_if.reg_num_mask = 0x1f;
1123 /* Register net device. After this dev->name assign */
1124 err = register_netdev(dev);
1126 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1132 pci_release_regions(pdev);
1134 pci_disable_device(pdev);
1135 pci_set_drvdata(pdev, NULL);
1141 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1143 struct net_device *dev = pci_get_drvdata(pdev);
1145 unregister_netdev(dev);
1146 pci_release_regions(pdev);
1148 pci_disable_device(pdev);
1149 pci_set_drvdata(pdev, NULL);
1153 static struct pci_device_id r6040_pci_tbl[] = {
1154 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1157 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1159 static struct pci_driver r6040_driver = {
1161 .id_table = r6040_pci_tbl,
1162 .probe = r6040_init_one,
1163 .remove = __devexit_p(r6040_remove_one),
1167 static int __init r6040_init(void)
1169 return pci_register_driver(&r6040_driver);
1173 static void __exit r6040_cleanup(void)
1175 pci_unregister_driver(&r6040_driver);
1178 module_init(r6040_init);
1179 module_exit(r6040_cleanup);