2 * RDC R6040 Fast Ethernet MAC support
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
50 #include <asm/processor.h>
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
65 /* RDC MAC I/O Size */
66 #define R6040_IO_SIZE 256
72 #define MCR0 0x00 /* Control register 0 */
73 #define MCR1 0x04 /* Control register 1 */
74 #define MAC_RST 0x0001 /* Reset the MAC */
75 #define MBCR 0x08 /* Bus control */
76 #define MT_ICR 0x0C /* TX interrupt control */
77 #define MR_ICR 0x10 /* RX interrupt control */
78 #define MTPR 0x14 /* TX poll command register */
79 #define MR_BSR 0x18 /* RX buffer size */
80 #define MR_DCR 0x1A /* RX descriptor control */
81 #define MLSR 0x1C /* Last status */
82 #define MMDIO 0x20 /* MDIO control register */
83 #define MDIO_WRITE 0x4000 /* MDIO write */
84 #define MDIO_READ 0x2000 /* MDIO read */
85 #define MMRD 0x24 /* MDIO read data register */
86 #define MMWD 0x28 /* MDIO write data register */
87 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
88 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
89 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
90 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
91 #define MISR 0x3C /* Status register */
92 #define MIER 0x40 /* INT enable register */
93 #define MSK_INT 0x0000 /* Mask off interrupts */
94 #define RX_FINISH 0x0001 /* RX finished */
95 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
96 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
97 #define RX_EARLY 0x0008 /* RX early */
98 #define TX_FINISH 0x0010 /* TX finished */
99 #define TX_EARLY 0x0080 /* TX early */
100 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
101 #define LINK_CHANGED 0x0200 /* PHY link changed */
102 #define ME_CISR 0x44 /* Event counter INT status */
103 #define ME_CIER 0x48 /* Event counter INT enable */
104 #define MR_CNT 0x50 /* Successfully received packet counter */
105 #define ME_CNT0 0x52 /* Event counter 0 */
106 #define ME_CNT1 0x54 /* Event counter 1 */
107 #define ME_CNT2 0x56 /* Event counter 2 */
108 #define ME_CNT3 0x58 /* Event counter 3 */
109 #define MT_CNT 0x5A /* Successfully transmit packet counter */
110 #define ME_CNT4 0x5C /* Event counter 4 */
111 #define MP_CNT 0x5E /* Pause frame counter register */
112 #define MAR0 0x60 /* Hash table 0 */
113 #define MAR1 0x62 /* Hash table 1 */
114 #define MAR2 0x64 /* Hash table 2 */
115 #define MAR3 0x66 /* Hash table 3 */
116 #define MID_0L 0x68 /* Multicast address MID0 Low */
117 #define MID_0M 0x6A /* Multicast address MID0 Medium */
118 #define MID_0H 0x6C /* Multicast address MID0 High */
119 #define MID_1L 0x70 /* MID1 Low */
120 #define MID_1M 0x72 /* MID1 Medium */
121 #define MID_1H 0x74 /* MID1 High */
122 #define MID_2L 0x78 /* MID2 Low */
123 #define MID_2M 0x7A /* MID2 Medium */
124 #define MID_2H 0x7C /* MID2 High */
125 #define MID_3L 0x80 /* MID3 Low */
126 #define MID_3M 0x82 /* MID3 Medium */
127 #define MID_3H 0x84 /* MID3 High */
128 #define PHY_CC 0x88 /* PHY status change configuration register */
129 #define PHY_ST 0x8A /* PHY status register */
130 #define MAC_SM 0xAC /* MAC status machine */
131 #define MAC_ID 0xBE /* Identifier register */
133 #define TX_DCNT 0x80 /* TX descriptor count */
134 #define RX_DCNT 0x80 /* RX descriptor count */
135 #define MAX_BUF_SIZE 0x600
136 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
137 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
138 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
139 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
142 #define ICPLUS_PHY_ID 0x0243
144 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
145 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
146 "Florian Fainelli <florian@openwrt.org>");
147 MODULE_LICENSE("GPL");
148 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
150 /* RX and TX interrupts that we handle */
151 #define RX_INT (RX_FINISH)
152 #define TX_INT (TX_FINISH)
153 #define INT_MASK (RX_INT | TX_INT)
155 struct r6040_descriptor {
156 u16 status, len; /* 0-3 */
157 __le32 buf; /* 4-7 */
158 __le32 ndesc; /* 8-B */
160 char *vbufp; /* 10-13 */
161 struct r6040_descriptor *vndescp; /* 14-17 */
162 struct sk_buff *skb_ptr; /* 18-1B */
163 u32 rev2; /* 1C-1F */
164 } __attribute__((aligned(32)));
166 struct r6040_private {
167 spinlock_t lock; /* driver lock */
168 struct timer_list timer;
169 struct pci_dev *pdev;
170 struct r6040_descriptor *rx_insert_ptr;
171 struct r6040_descriptor *rx_remove_ptr;
172 struct r6040_descriptor *tx_insert_ptr;
173 struct r6040_descriptor *tx_remove_ptr;
174 struct r6040_descriptor *rx_ring;
175 struct r6040_descriptor *tx_ring;
176 dma_addr_t rx_ring_dma;
177 dma_addr_t tx_ring_dma;
178 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
181 struct net_device *dev;
182 struct mii_if_info mii_if;
183 struct napi_struct napi;
187 static char version[] __devinitdata = KERN_INFO DRV_NAME
188 ": RDC R6040 NAPI net driver,"
189 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
191 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
193 /* Read a word data from PHY Chip */
194 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
199 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
200 /* Wait for the read bit to be cleared */
202 cmd = ioread16(ioaddr + MMDIO);
207 return ioread16(ioaddr + MMRD);
210 /* Write a word data from PHY Chip */
211 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
216 iowrite16(val, ioaddr + MMWD);
217 /* Write the command to the MDIO bus */
218 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
219 /* Wait for the write bit to be cleared */
221 cmd = ioread16(ioaddr + MMDIO);
222 if (cmd & MDIO_WRITE)
227 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
229 struct r6040_private *lp = netdev_priv(dev);
230 void __iomem *ioaddr = lp->base;
232 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
235 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
237 struct r6040_private *lp = netdev_priv(dev);
238 void __iomem *ioaddr = lp->base;
240 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
243 static void r6040_free_txbufs(struct net_device *dev)
245 struct r6040_private *lp = netdev_priv(dev);
248 for (i = 0; i < TX_DCNT; i++) {
249 if (lp->tx_insert_ptr->skb_ptr) {
250 pci_unmap_single(lp->pdev,
251 le32_to_cpu(lp->tx_insert_ptr->buf),
252 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
253 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
254 lp->rx_insert_ptr->skb_ptr = NULL;
256 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
260 static void r6040_free_rxbufs(struct net_device *dev)
262 struct r6040_private *lp = netdev_priv(dev);
265 for (i = 0; i < RX_DCNT; i++) {
266 if (lp->rx_insert_ptr->skb_ptr) {
267 pci_unmap_single(lp->pdev,
268 le32_to_cpu(lp->rx_insert_ptr->buf),
269 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
270 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
271 lp->rx_insert_ptr->skb_ptr = NULL;
273 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
277 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
278 dma_addr_t desc_dma, int size)
280 struct r6040_descriptor *desc = desc_ring;
281 dma_addr_t mapping = desc_dma;
284 mapping += sizeof(*desc);
285 desc->ndesc = cpu_to_le32(mapping);
286 desc->vndescp = desc + 1;
290 desc->ndesc = cpu_to_le32(desc_dma);
291 desc->vndescp = desc_ring;
294 /* Allocate skb buffer for rx descriptor */
295 static void r6040_rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
297 struct r6040_descriptor *descptr;
298 void __iomem *ioaddr = lp->base;
300 descptr = lp->rx_insert_ptr;
301 while (lp->rx_free_desc < RX_DCNT) {
302 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
304 if (!descptr->skb_ptr)
306 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
307 descptr->skb_ptr->data,
308 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
309 descptr->status = 0x8000;
310 descptr = descptr->vndescp;
313 iowrite16(lp->mcr0 | 0x0002, ioaddr);
315 lp->rx_insert_ptr = descptr;
318 static void r6040_alloc_txbufs(struct net_device *dev)
320 struct r6040_private *lp = netdev_priv(dev);
321 void __iomem *ioaddr = lp->base;
323 lp->tx_free_desc = TX_DCNT;
325 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
326 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
328 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
329 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
332 static void r6040_alloc_rxbufs(struct net_device *dev)
334 struct r6040_private *lp = netdev_priv(dev);
335 void __iomem *ioaddr = lp->base;
337 lp->rx_free_desc = 0;
339 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
340 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
342 r6040_rx_buf_alloc(lp, dev);
344 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
345 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
348 static void r6040_tx_timeout(struct net_device *dev)
350 struct r6040_private *priv = netdev_priv(dev);
351 void __iomem *ioaddr = priv->base;
353 printk(KERN_WARNING "%s: transmit timed out, status %4.4x, PHY status "
355 dev->name, ioread16(ioaddr + MIER),
356 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
358 disable_irq(dev->irq);
359 napi_disable(&priv->napi);
360 spin_lock(&priv->lock);
361 /* Clear all descriptors */
362 r6040_free_txbufs(dev);
363 r6040_free_rxbufs(dev);
364 r6040_alloc_txbufs(dev);
365 r6040_alloc_rxbufs(dev);
368 iowrite16(MAC_RST, ioaddr + MCR1);
369 spin_unlock(&priv->lock);
370 enable_irq(dev->irq);
372 dev->stats.tx_errors++;
373 netif_wake_queue(dev);
376 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
378 struct r6040_private *priv = netdev_priv(dev);
379 void __iomem *ioaddr = priv->base;
382 spin_lock_irqsave(&priv->lock, flags);
383 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
384 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
385 spin_unlock_irqrestore(&priv->lock, flags);
390 /* Stop RDC MAC and Free the allocated resource */
391 static void r6040_down(struct net_device *dev)
393 struct r6040_private *lp = netdev_priv(dev);
394 void __iomem *ioaddr = lp->base;
395 struct pci_dev *pdev = lp->pdev;
401 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
402 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
404 cmd = ioread16(ioaddr + MCR1);
409 /* Restore MAC Address to MIDx */
410 adrp = (u16 *) dev->dev_addr;
411 iowrite16(adrp[0], ioaddr + MID_0L);
412 iowrite16(adrp[1], ioaddr + MID_0M);
413 iowrite16(adrp[2], ioaddr + MID_0H);
414 free_irq(dev->irq, dev);
417 r6040_free_rxbufs(dev);
420 r6040_free_txbufs(dev);
422 /* Free Descriptor memory */
423 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
424 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
427 static int r6040_close(struct net_device *dev)
429 struct r6040_private *lp = netdev_priv(dev);
432 del_timer_sync(&lp->timer);
434 spin_lock_irq(&lp->lock);
435 netif_stop_queue(dev);
437 spin_unlock_irq(&lp->lock);
442 /* Status of PHY CHIP */
443 static int r6040_phy_mode_chk(struct net_device *dev)
445 struct r6040_private *lp = netdev_priv(dev);
446 void __iomem *ioaddr = lp->base;
449 /* PHY Link Status Check */
450 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
451 if (!(phy_dat & 0x4))
452 phy_dat = 0x8000; /* Link Failed, full duplex */
454 /* PHY Chip Auto-Negotiation Status */
455 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
456 if (phy_dat & 0x0020) {
457 /* Auto Negotiation Mode */
458 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
459 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
461 /* Force full duplex */
467 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
477 static void r6040_set_carrier(struct mii_if_info *mii)
479 if (r6040_phy_mode_chk(mii->dev)) {
480 /* autoneg is off: Link is always assumed to be up */
481 if (!netif_carrier_ok(mii->dev))
482 netif_carrier_on(mii->dev);
484 r6040_phy_mode_chk(mii->dev);
487 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
489 struct r6040_private *lp = netdev_priv(dev);
490 struct mii_ioctl_data *data = if_mii(rq);
493 if (!netif_running(dev))
495 spin_lock_irq(&lp->lock);
496 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
497 spin_unlock_irq(&lp->lock);
498 r6040_set_carrier(&lp->mii_if);
502 static int r6040_rx(struct net_device *dev, int limit)
504 struct r6040_private *priv = netdev_priv(dev);
506 void __iomem *ioaddr = priv->base;
509 for (count = 0; count < limit; ++count) {
510 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
511 struct sk_buff *skb_ptr;
513 descptr = priv->rx_remove_ptr;
515 /* Check for errors */
516 err = ioread16(ioaddr + MLSR);
518 dev->stats.rx_errors++;
519 /* RX FIFO over-run */
521 dev->stats.rx_fifo_errors++;
522 /* RX descriptor unavailable */
524 dev->stats.rx_frame_errors++;
525 /* Received packet with length over buffer lenght */
527 dev->stats.rx_over_errors++;
528 /* Received packet with too long or short */
529 if (err & (0x0010 | 0x0008))
530 dev->stats.rx_length_errors++;
531 /* Received packet with CRC errors */
533 spin_lock(&priv->lock);
534 dev->stats.rx_crc_errors++;
535 spin_unlock(&priv->lock);
538 while (priv->rx_free_desc) {
540 if (descptr->status & 0x8000)
542 skb_ptr = descptr->skb_ptr;
544 printk(KERN_ERR "%s: Inconsistent RX"
545 "descriptor chain\n",
549 descptr->skb_ptr = NULL;
550 skb_ptr->dev = priv->dev;
551 /* Do not count the CRC */
552 skb_put(skb_ptr, descptr->len - 4);
553 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
554 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
555 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
556 /* Send to upper layer */
557 netif_receive_skb(skb_ptr);
558 dev->last_rx = jiffies;
559 dev->stats.rx_packets++;
560 dev->stats.rx_bytes += descptr->len;
561 /* To next descriptor */
562 descptr = descptr->vndescp;
563 priv->rx_free_desc--;
565 priv->rx_remove_ptr = descptr;
567 /* Allocate new RX buffer */
568 if (priv->rx_free_desc < RX_DCNT)
569 r6040_rx_buf_alloc(priv, priv->dev);
574 static void r6040_tx(struct net_device *dev)
576 struct r6040_private *priv = netdev_priv(dev);
577 struct r6040_descriptor *descptr;
578 void __iomem *ioaddr = priv->base;
579 struct sk_buff *skb_ptr;
582 spin_lock(&priv->lock);
583 descptr = priv->tx_remove_ptr;
584 while (priv->tx_free_desc < TX_DCNT) {
585 /* Check for errors */
586 err = ioread16(ioaddr + MLSR);
589 dev->stats.rx_fifo_errors++;
590 if (err & (0x2000 | 0x4000))
591 dev->stats.tx_carrier_errors++;
593 if (descptr->status & 0x8000)
594 break; /* Not complete */
595 skb_ptr = descptr->skb_ptr;
596 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
597 skb_ptr->len, PCI_DMA_TODEVICE);
599 dev_kfree_skb_irq(skb_ptr);
600 descptr->skb_ptr = NULL;
601 /* To next descriptor */
602 descptr = descptr->vndescp;
603 priv->tx_free_desc++;
605 priv->tx_remove_ptr = descptr;
607 if (priv->tx_free_desc)
608 netif_wake_queue(dev);
609 spin_unlock(&priv->lock);
612 static int r6040_poll(struct napi_struct *napi, int budget)
614 struct r6040_private *priv =
615 container_of(napi, struct r6040_private, napi);
616 struct net_device *dev = priv->dev;
617 void __iomem *ioaddr = priv->base;
620 work_done = r6040_rx(dev, budget);
622 if (work_done < budget) {
623 netif_rx_complete(dev, napi);
624 /* Enable RX interrupt */
625 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
630 /* The RDC interrupt handler. */
631 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
633 struct net_device *dev = dev_id;
634 struct r6040_private *lp = netdev_priv(dev);
635 void __iomem *ioaddr = lp->base;
638 /* Mask off RDC MAC interrupt */
639 iowrite16(MSK_INT, ioaddr + MIER);
640 /* Read MISR status and clear */
641 status = ioread16(ioaddr + MISR);
643 if (status == 0x0000 || status == 0xffff)
646 /* RX interrupt request */
648 /* Mask off RX interrupt */
649 iowrite16(ioread16(ioaddr + MIER) & ~RX_INT, ioaddr + MIER);
650 netif_rx_schedule(dev, &lp->napi);
653 /* TX interrupt request */
660 #ifdef CONFIG_NET_POLL_CONTROLLER
661 static void r6040_poll_controller(struct net_device *dev)
663 disable_irq(dev->irq);
664 r6040_interrupt(dev->irq, dev);
665 enable_irq(dev->irq);
670 static void r6040_up(struct net_device *dev)
672 struct r6040_private *lp = netdev_priv(dev);
673 void __iomem *ioaddr = lp->base;
675 /* Initialise and alloc RX/TX buffers */
676 r6040_alloc_txbufs(dev);
677 r6040_alloc_rxbufs(dev);
679 /* Buffer Size Register */
680 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
681 /* Read the PHY ID */
682 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
684 if (lp->switch_sig == ICPLUS_PHY_ID) {
685 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
686 lp->phy_mode = 0x8000;
689 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
690 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
692 if (PHY_MODE == 0x3100)
693 lp->phy_mode = r6040_phy_mode_chk(dev);
695 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
697 /* MAC Bus Control Register :
698 * - wait 1 host clock SDRAM bus request
699 * - RX FIFO : 32 bytes
700 * - TX FIFO : 64 bytes
701 * - FIFO transfer lenght : 16 bytes */
702 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
704 /* MAC TX/RX Enable */
705 lp->mcr0 |= lp->phy_mode;
706 iowrite16(lp->mcr0, ioaddr);
708 /* set interrupt waiting time and packet numbers */
709 iowrite16(0x0F06, ioaddr + MT_ICR);
710 iowrite16(0x0F06, ioaddr + MR_ICR);
712 /* improve performance (by RDC guys) */
713 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
714 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
715 r6040_phy_write(ioaddr, 0, 19, 0x0000);
716 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
718 /* Interrupt Mask Register */
719 iowrite16(INT_MASK, ioaddr + MIER);
723 A periodic timer routine
724 Polling PHY Chip Link Status
726 static void r6040_timer(unsigned long data)
728 struct net_device *dev = (struct net_device *)data;
729 struct r6040_private *lp = netdev_priv(dev);
730 void __iomem *ioaddr = lp->base;
733 /* Polling PHY Chip Status */
734 if (PHY_MODE == 0x3100)
735 phy_mode = r6040_phy_mode_chk(dev);
737 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
739 if (phy_mode != lp->phy_mode) {
740 lp->phy_mode = phy_mode;
741 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
742 iowrite16(lp->mcr0, ioaddr);
743 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
746 /* Timer active again */
747 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
750 /* Read/set MAC address routines */
751 static void r6040_mac_address(struct net_device *dev)
753 struct r6040_private *lp = netdev_priv(dev);
754 void __iomem *ioaddr = lp->base;
757 /* MAC operation register */
758 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
759 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
760 iowrite16(0, ioaddr + MAC_SM);
763 /* Restore MAC Address */
764 adrp = (u16 *) dev->dev_addr;
765 iowrite16(adrp[0], ioaddr + MID_0L);
766 iowrite16(adrp[1], ioaddr + MID_0M);
767 iowrite16(adrp[2], ioaddr + MID_0H);
770 static int r6040_open(struct net_device *dev)
772 struct r6040_private *lp = netdev_priv(dev);
775 /* Request IRQ and Register interrupt handler */
776 ret = request_irq(dev->irq, &r6040_interrupt,
777 IRQF_SHARED, dev->name, dev);
781 /* Set MAC address */
782 r6040_mac_address(dev);
784 /* Allocate Descriptor memory */
786 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
791 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
793 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
800 napi_enable(&lp->napi);
801 netif_start_queue(dev);
803 /* set and active a timer process */
804 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
805 if (lp->switch_sig != ICPLUS_PHY_ID)
806 mod_timer(&lp->timer, jiffies + HZ);
810 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
812 struct r6040_private *lp = netdev_priv(dev);
813 struct r6040_descriptor *descptr;
814 void __iomem *ioaddr = lp->base;
816 int ret = NETDEV_TX_OK;
818 /* Critical Section */
819 spin_lock_irqsave(&lp->lock, flags);
821 /* TX resource check */
822 if (!lp->tx_free_desc) {
823 spin_unlock_irqrestore(&lp->lock, flags);
824 netif_stop_queue(dev);
825 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
826 ret = NETDEV_TX_BUSY;
830 /* Statistic Counter */
831 dev->stats.tx_packets++;
832 dev->stats.tx_bytes += skb->len;
833 /* Set TX descriptor & Transmit it */
835 descptr = lp->tx_insert_ptr;
839 descptr->len = skb->len;
841 descptr->skb_ptr = skb;
842 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
843 skb->data, skb->len, PCI_DMA_TODEVICE));
844 descptr->status = 0x8000;
845 /* Trigger the MAC to check the TX descriptor */
846 iowrite16(0x01, ioaddr + MTPR);
847 lp->tx_insert_ptr = descptr->vndescp;
849 /* If no tx resource, stop */
850 if (!lp->tx_free_desc)
851 netif_stop_queue(dev);
853 dev->trans_start = jiffies;
854 spin_unlock_irqrestore(&lp->lock, flags);
858 static void r6040_multicast_list(struct net_device *dev)
860 struct r6040_private *lp = netdev_priv(dev);
861 void __iomem *ioaddr = lp->base;
865 struct dev_mc_list *dmi = dev->mc_list;
869 adrp = (u16 *)dev->dev_addr;
870 iowrite16(adrp[0], ioaddr + MID_0L);
871 iowrite16(adrp[1], ioaddr + MID_0M);
872 iowrite16(adrp[2], ioaddr + MID_0H);
874 /* Promiscous Mode */
875 spin_lock_irqsave(&lp->lock, flags);
877 /* Clear AMCP & PROM bits */
878 reg = ioread16(ioaddr) & ~0x0120;
879 if (dev->flags & IFF_PROMISC) {
883 /* Too many multicast addresses
884 * accept all traffic */
885 else if ((dev->mc_count > MCAST_MAX)
886 || (dev->flags & IFF_ALLMULTI))
889 iowrite16(reg, ioaddr);
890 spin_unlock_irqrestore(&lp->lock, flags);
892 /* Build the hash table */
893 if (dev->mc_count > MCAST_MAX) {
897 for (i = 0; i < 4; i++)
900 for (i = 0; i < dev->mc_count; i++) {
901 char *addrs = dmi->dmi_addr;
908 crc = ether_crc_le(6, addrs);
910 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
912 /* Write the index of the hash table */
913 for (i = 0; i < 4; i++)
914 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
915 /* Fill the MAC hash tables with their values */
916 iowrite16(hash_table[0], ioaddr + MAR0);
917 iowrite16(hash_table[1], ioaddr + MAR1);
918 iowrite16(hash_table[2], ioaddr + MAR2);
919 iowrite16(hash_table[3], ioaddr + MAR3);
921 /* Multicast Address 1~4 case */
922 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
923 adrp = (u16 *)dmi->dmi_addr;
924 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
925 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
926 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
929 for (i = dev->mc_count; i < MCAST_MAX; i++) {
930 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
931 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
932 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
936 static void netdev_get_drvinfo(struct net_device *dev,
937 struct ethtool_drvinfo *info)
939 struct r6040_private *rp = netdev_priv(dev);
941 strcpy(info->driver, DRV_NAME);
942 strcpy(info->version, DRV_VERSION);
943 strcpy(info->bus_info, pci_name(rp->pdev));
946 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
948 struct r6040_private *rp = netdev_priv(dev);
951 spin_lock_irq(&rp->lock);
952 rc = mii_ethtool_gset(&rp->mii_if, cmd);
953 spin_unlock_irq(&rp->lock);
958 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
960 struct r6040_private *rp = netdev_priv(dev);
963 spin_lock_irq(&rp->lock);
964 rc = mii_ethtool_sset(&rp->mii_if, cmd);
965 spin_unlock_irq(&rp->lock);
966 r6040_set_carrier(&rp->mii_if);
971 static u32 netdev_get_link(struct net_device *dev)
973 struct r6040_private *rp = netdev_priv(dev);
975 return mii_link_ok(&rp->mii_if);
978 static struct ethtool_ops netdev_ethtool_ops = {
979 .get_drvinfo = netdev_get_drvinfo,
980 .get_settings = netdev_get_settings,
981 .set_settings = netdev_set_settings,
982 .get_link = netdev_get_link,
985 static int __devinit r6040_init_one(struct pci_dev *pdev,
986 const struct pci_device_id *ent)
988 struct net_device *dev;
989 struct r6040_private *lp;
990 void __iomem *ioaddr;
991 int err, io_size = R6040_IO_SIZE;
992 static int card_idx = -1;
997 printk(KERN_INFO "%s\n", version);
999 err = pci_enable_device(pdev);
1003 /* this should always be supported */
1004 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1005 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1006 "not supported by the card\n");
1009 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1010 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1011 "not supported by the card\n");
1016 if (pci_resource_len(pdev, 0) < io_size) {
1017 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1021 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1022 pci_set_master(pdev);
1024 dev = alloc_etherdev(sizeof(struct r6040_private));
1026 printk(KERN_ERR "Failed to allocate etherdev\n");
1029 SET_NETDEV_DEV(dev, &pdev->dev);
1030 lp = netdev_priv(dev);
1034 if (pci_request_regions(pdev, DRV_NAME)) {
1035 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1037 goto err_out_disable;
1040 ioaddr = pci_iomap(pdev, bar, io_size);
1042 printk(KERN_ERR "ioremap failed for device %s\n",
1047 /* Init system & device */
1049 dev->irq = pdev->irq;
1051 spin_lock_init(&lp->lock);
1052 pci_set_drvdata(pdev, dev);
1054 /* Set MAC address */
1057 adrp = (u16 *)dev->dev_addr;
1058 adrp[0] = ioread16(ioaddr + MID_0L);
1059 adrp[1] = ioread16(ioaddr + MID_0M);
1060 adrp[2] = ioread16(ioaddr + MID_0H);
1062 /* Link new device into r6040_root_dev */
1065 /* Init RDC private data */
1067 lp->phy_addr = phy_table[card_idx];
1070 /* The RDC-specific entries in the device structure. */
1071 dev->open = &r6040_open;
1072 dev->hard_start_xmit = &r6040_start_xmit;
1073 dev->stop = &r6040_close;
1074 dev->get_stats = r6040_get_stats;
1075 dev->set_multicast_list = &r6040_multicast_list;
1076 dev->do_ioctl = &r6040_ioctl;
1077 dev->ethtool_ops = &netdev_ethtool_ops;
1078 dev->tx_timeout = &r6040_tx_timeout;
1079 dev->watchdog_timeo = TX_TIMEOUT;
1080 #ifdef CONFIG_NET_POLL_CONTROLLER
1081 dev->poll_controller = r6040_poll_controller;
1083 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1084 lp->mii_if.dev = dev;
1085 lp->mii_if.mdio_read = r6040_mdio_read;
1086 lp->mii_if.mdio_write = r6040_mdio_write;
1087 lp->mii_if.phy_id = lp->phy_addr;
1088 lp->mii_if.phy_id_mask = 0x1f;
1089 lp->mii_if.reg_num_mask = 0x1f;
1091 /* Register net device. After this dev->name assign */
1092 err = register_netdev(dev);
1094 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1100 pci_release_regions(pdev);
1102 pci_disable_device(pdev);
1103 pci_set_drvdata(pdev, NULL);
1109 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1111 struct net_device *dev = pci_get_drvdata(pdev);
1113 unregister_netdev(dev);
1114 pci_release_regions(pdev);
1116 pci_disable_device(pdev);
1117 pci_set_drvdata(pdev, NULL);
1121 static struct pci_device_id r6040_pci_tbl[] = {
1122 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1125 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1127 static struct pci_driver r6040_driver = {
1129 .id_table = r6040_pci_tbl,
1130 .probe = r6040_init_one,
1131 .remove = __devexit_p(r6040_remove_one),
1135 static int __init r6040_init(void)
1137 return pci_register_driver(&r6040_driver);
1141 static void __exit r6040_cleanup(void)
1143 pci_unregister_driver(&r6040_driver);
1146 module_init(r6040_init);
1147 module_exit(r6040_cleanup);