SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         /* required last entry */
  80         {0,}
  81 };
  82
  83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  84
  85 /* This hardware semaphore causes exclusive access to
  86  * resources shared between the NIC driver, MPI firmware,
  87  * FCOE firmware and the FC driver.
  88  */
  89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  90 {
  91         u32 sem_bits = 0;
  92
  93         switch (sem_mask) {
  94         case SEM_XGMAC0_MASK:
  95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  96                 break;
  97         case SEM_XGMAC1_MASK:
  98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  99                 break;
 100         case SEM_ICB_MASK:
 101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 102                 break;
 103         case SEM_MAC_ADDR_MASK:
 104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 105                 break;
 106         case SEM_FLASH_MASK:
 107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 108                 break;
 109         case SEM_PROBE_MASK:
 110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 111                 break;
 112         case SEM_RT_IDX_MASK:
 113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 114                 break;
 115         case SEM_PROC_REG_MASK:
 116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 117                 break;
 118         default:
 119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 120                 return -EINVAL;
 121         }
 122
 123         ql_write32(qdev, SEM, sem_bits | sem_mask);
 124         return !(ql_read32(qdev, SEM) & sem_bits);
 125 }
 126
 127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 128 {
 129         unsigned int wait_count = 30;
 130         do {
 131                 if (!ql_sem_trylock(qdev, sem_mask))
 132                         return 0;
 133                 udelay(100);
 134         } while (--wait_count);
 135         return -ETIMEDOUT;
 136 }
 137
 138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 139 {
 140         ql_write32(qdev, SEM, sem_mask);
 141         ql_read32(qdev, SEM);   /* flush */
 142 }
 143
 144 /* This function waits for a specific bit to come ready
 145  * in a given register.  It is used mostly by the initialize
 146  * process, but is also used in kernel thread API such as
 147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 148  */
 149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 150 {
 151         u32 temp;
 152         int count = UDELAY_COUNT;
 153
 154         while (count) {
 155                 temp = ql_read32(qdev, reg);
 156
 157                 /* check for errors */
 158                 if (temp & err_bit) {
 159                         QPRINTK(qdev, PROBE, ALERT,
 160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 161                                 reg, temp);
 162                         return -EIO;
 163                 } else if (temp & bit)
 164                         return 0;
 165                 udelay(UDELAY_DELAY);
 166                 count--;
 167         }
 168         QPRINTK(qdev, PROBE, ALERT,
 169                 "Timed out waiting for reg %x to come ready.\n", reg);
 170         return -ETIMEDOUT;
 171 }
 172
 173 /* The CFG register is used to download TX and RX control blocks
 174  * to the chip. This function waits for an operation to complete.
 175  */
 176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 177 {
 178         int count = UDELAY_COUNT;
 179         u32 temp;
 180
 181         while (count) {
 182                 temp = ql_read32(qdev, CFG);
 183                 if (temp & CFG_LE)
 184                         return -EIO;
 185                 if (!(temp & bit))
 186                         return 0;
 187                 udelay(UDELAY_DELAY);
 188                 count--;
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193
 194 /* Used to issue init control blocks to hw. Maps control block,
 195  * sets address, triggers download, waits for completion.
 196  */
 197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 198                  u16 q_id)
 199 {
 200         u64 map;
 201         int status = 0;
 202         int direction;
 203         u32 mask;
 204         u32 value;
 205
 206         direction =
 207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 208             PCI_DMA_FROMDEVICE;
 209
 210         map = pci_map_single(qdev->pdev, ptr, size, direction);
 211         if (pci_dma_mapping_error(qdev->pdev, map)) {
 212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 213                 return -ENOMEM;
 214         }
 215
 216         status = ql_wait_cfg(qdev, bit);
 217         if (status) {
 218                 QPRINTK(qdev, IFUP, ERR,
 219                         "Timed out waiting for CFG to come ready.\n");
 220                 goto exit;
 221         }
 222
 223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 224         if (status)
 225                 goto exit;
 226         ql_write32(qdev, ICB_L, (u32) map);
 227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 229
 230         mask = CFG_Q_MASK | (bit << 16);
 231         value = bit | (q_id << CFG_Q_SHIFT);
 232         ql_write32(qdev, CFG, (mask | value));
 233
 234         /*
 235          * Wait for the bit to clear after signaling hw.
 236          */
 237         status = ql_wait_cfg(qdev, bit);
 238 exit:
 239         pci_unmap_single(qdev->pdev, map, size, direction);
 240         return status;
 241 }
 242
 243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 245                         u32 *value)
 246 {
 247         u32 offset = 0;
 248         int status;
 249
 250         switch (type) {
 251         case MAC_ADDR_TYPE_MULTI_MAC:
 252         case MAC_ADDR_TYPE_CAM_MAC:
 253                 {
 254                         status =
 255                             ql_wait_reg_rdy(qdev,
 256                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 257                         if (status)
 258                                 goto exit;
 259                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 260                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 261                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 262                         status =
 263                             ql_wait_reg_rdy(qdev,
 264                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 265                         if (status)
 266                                 goto exit;
 267                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 268                         status =
 269                             ql_wait_reg_rdy(qdev,
 270                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 271                         if (status)
 272                                 goto exit;
 273                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 274                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 275                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 276                         status =
 277                             ql_wait_reg_rdy(qdev,
 278                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 279                         if (status)
 280                                 goto exit;
 281                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 282                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 283                                 status =
 284                                     ql_wait_reg_rdy(qdev,
 285                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 286                                 if (status)
 287                                         goto exit;
 288                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 289                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 290                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 291                                 status =
 292                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 293                                                     MAC_ADDR_MR, 0);
 294                                 if (status)
 295                                         goto exit;
 296                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 297                         }
 298                         break;
 299                 }
 300         case MAC_ADDR_TYPE_VLAN:
 301         case MAC_ADDR_TYPE_MULTI_FLTR:
 302         default:
 303                 QPRINTK(qdev, IFUP, CRIT,
 304                         "Address type %d not yet supported.\n", type);
 305                 status = -EPERM;
 306         }
 307 exit:
 308         return status;
 309 }
 310
 311 /* Set up a MAC, multicast or VLAN address for the
 312  * inbound frame matching.
 313  */
 314 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 315                                u16 index)
 316 {
 317         u32 offset = 0;
 318         int status = 0;
 319
 320         switch (type) {
 321         case MAC_ADDR_TYPE_MULTI_MAC:
 322         case MAC_ADDR_TYPE_CAM_MAC:
 323                 {
 324                         u32 cam_output;
 325                         u32 upper = (addr[0] << 8) | addr[1];
 326                         u32 lower =
 327                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 328                             (addr[5]);
 329
 330                         QPRINTK(qdev, IFUP, INFO,
 331                                 "Adding %s address %pM"
 332                                 " at index %d in the CAM.\n",
 333                                 ((type ==
 334                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 335                                  "UNICAST"), addr, index);
 336
 337                         status =
 338                             ql_wait_reg_rdy(qdev,
 339                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 340                         if (status)
 341                                 goto exit;
 342                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 343                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 344                                    type);       /* type */
 345                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 346                         status =
 347                             ql_wait_reg_rdy(qdev,
 348                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 349                         if (status)
 350                                 goto exit;
 351                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 352                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 353                                    type);       /* type */
 354                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 355                         status =
 356                             ql_wait_reg_rdy(qdev,
 357                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 358                         if (status)
 359                                 goto exit;
 360                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 361                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 362                                    type);       /* type */
 363                         /* This field should also include the queue id
 364                            and possibly the function id.  Right now we hardcode
 365                            the route field to NIC core.
 366                          */
 367                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 368                                 cam_output = (CAM_OUT_ROUTE_NIC |
 369                                               (qdev->
 370                                                func << CAM_OUT_FUNC_SHIFT) |
 371                                               (qdev->
 372                                                rss_ring_first_cq_id <<
 373                                                CAM_OUT_CQ_ID_SHIFT));
 374                                 if (qdev->vlgrp)
 375                                         cam_output |= CAM_OUT_RV;
 376                                 /* route to NIC core */
 377                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 378                         }
 379                         break;
 380                 }
 381         case MAC_ADDR_TYPE_VLAN:
 382                 {
 383                         u32 enable_bit = *((u32 *) &addr[0]);
 384                         /* For VLAN, the addr actually holds a bit that
 385                          * either enables or disables the vlan id we are
 386                          * addressing. It's either MAC_ADDR_E on or off.
 387                          * That's bit-27 we're talking about.
 388                          */
 389                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 390                                 (enable_bit ? "Adding" : "Removing"),
 391                                 index, (enable_bit ? "to" : "from"));
 392
 393                         status =
 394                             ql_wait_reg_rdy(qdev,
 395                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 396                         if (status)
 397                                 goto exit;
 398                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 399                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 400                                    type |       /* type */
 401                                    enable_bit); /* enable/disable */
 402                         break;
 403                 }
 404         case MAC_ADDR_TYPE_MULTI_FLTR:
 405         default:
 406                 QPRINTK(qdev, IFUP, CRIT,
 407                         "Address type %d not yet supported.\n", type);
 408                 status = -EPERM;
 409         }
 410 exit:
 411         return status;
 412 }
 413
 414 /* Get a specific frame routing value from the CAM.
 415  * Used for debug and reg dump.
 416  */
 417 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 418 {
 419         int status = 0;
 420
 421         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 422         if (status)
 423                 goto exit;
 424
 425         ql_write32(qdev, RT_IDX,
 426                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 427         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 428         if (status)
 429                 goto exit;
 430         *value = ql_read32(qdev, RT_DATA);
 431 exit:
 432         return status;
 433 }
 434
 435 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 436  * to route different frame types to various inbound queues.  We send broadcast/
 437  * multicast/error frames to the default queue for slow handling,
 438  * and CAM hit/RSS frames to the fast handling queues.
 439  */
 440 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 441                               int enable)
 442 {
 443         int status = -EINVAL; /* Return error if no mask match. */
 444         u32 value = 0;
 445
 446         QPRINTK(qdev, IFUP, DEBUG,
 447                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 448                 (enable ? "Adding" : "Removing"),
 449                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 450                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 451                 ((index ==
 452                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 453                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 454                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 455                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 456                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 457                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 458                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 459                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 460                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 461                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 462                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 463                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 464                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 465                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 466                 (enable ? "to" : "from"));
 467
 468         switch (mask) {
 469         case RT_IDX_CAM_HIT:
 470                 {
 471                         value = RT_IDX_DST_CAM_Q |      /* dest */
 472                             RT_IDX_TYPE_NICQ |  /* type */
 473                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 474                         break;
 475                 }
 476         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 477                 {
 478                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 479                             RT_IDX_TYPE_NICQ |  /* type */
 480                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 481                         break;
 482                 }
 483         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 484                 {
 485                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 486                             RT_IDX_TYPE_NICQ |  /* type */
 487                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 488                         break;
 489                 }
 490         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 491                 {
 492                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 493                             RT_IDX_TYPE_NICQ |  /* type */
 494                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 495                         break;
 496                 }
 497         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 498                 {
 499                         value = RT_IDX_DST_CAM_Q |      /* dest */
 500                             RT_IDX_TYPE_NICQ |  /* type */
 501                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 502                         break;
 503                 }
 504         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 505                 {
 506                         value = RT_IDX_DST_CAM_Q |      /* dest */
 507                             RT_IDX_TYPE_NICQ |  /* type */
 508                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 509                         break;
 510                 }
 511         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 512                 {
 513                         value = RT_IDX_DST_RSS |        /* dest */
 514                             RT_IDX_TYPE_NICQ |  /* type */
 515                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 516                         break;
 517                 }
 518         case 0:         /* Clear the E-bit on an entry. */
 519                 {
 520                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 521                             RT_IDX_TYPE_NICQ |  /* type */
 522                             (index << RT_IDX_IDX_SHIFT);/* index */
 523                         break;
 524                 }
 525         default:
 526                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 527                         mask);
 528                 status = -EPERM;
 529                 goto exit;
 530         }
 531
 532         if (value) {
 533                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 534                 if (status)
 535                         goto exit;
 536                 value |= (enable ? RT_IDX_E : 0);
 537                 ql_write32(qdev, RT_IDX, value);
 538                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 539         }
 540 exit:
 541         return status;
 542 }
 543
 544 static void ql_enable_interrupts(struct ql_adapter *qdev)
 545 {
 546         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 547 }
 548
 549 static void ql_disable_interrupts(struct ql_adapter *qdev)
 550 {
 551         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 552 }
 553
 554 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 555  * Otherwise, we may have multiple outstanding workers and don't want to
 556  * enable until the last one finishes. In this case, the irq_cnt gets
 557  * incremented everytime we queue a worker and decremented everytime
 558  * a worker finishes.  Once it hits zero we enable the interrupt.
 559  */
 560 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 561 {
 562         u32 var = 0;
 563         unsigned long hw_flags = 0;
 564         struct intr_context *ctx = qdev->intr_context + intr;
 565
 566         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 567                 /* Always enable if we're MSIX multi interrupts and
 568                  * it's not the default (zeroeth) interrupt.
 569                  */
 570                 ql_write32(qdev, INTR_EN,
 571                            ctx->intr_en_mask);
 572                 var = ql_read32(qdev, STS);
 573                 return var;
 574         }
 575
 576         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 577         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 578                 ql_write32(qdev, INTR_EN,
 579                            ctx->intr_en_mask);
 580                 var = ql_read32(qdev, STS);
 581         }
 582         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 583         return var;
 584 }
 585
 586 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 587 {
 588         u32 var = 0;
 589         unsigned long hw_flags;
 590         struct intr_context *ctx;
 591
 592         /* HW disables for us if we're MSIX multi interrupts and
 593          * it's not the default (zeroeth) interrupt.
 594          */
 595         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 596                 return 0;
 597
 598         ctx = qdev->intr_context + intr;
 599         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 600         if (!atomic_read(&ctx->irq_cnt)) {
 601                 ql_write32(qdev, INTR_EN,
 602                 ctx->intr_dis_mask);
 603                 var = ql_read32(qdev, STS);
 604         }
 605         atomic_inc(&ctx->irq_cnt);
 606         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 607         return var;
 608 }
 609
 610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 611 {
 612         int i;
 613         for (i = 0; i < qdev->intr_count; i++) {
 614                 /* The enable call does a atomic_dec_and_test
 615                  * and enables only if the result is zero.
 616                  * So we precharge it here.
 617                  */
 618                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 619                         i == 0))
 620                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 621                 ql_enable_completion_interrupt(qdev, i);
 622         }
 623
 624 }
 625
 626 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 627 {
 628         int status = 0;
 629         /* wait for reg to come ready */
 630         status = ql_wait_reg_rdy(qdev,
 631                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 632         if (status)
 633                 goto exit;
 634         /* set up for reg read */
 635         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 636         /* wait for reg to come ready */
 637         status = ql_wait_reg_rdy(qdev,
 638                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 639         if (status)
 640                 goto exit;
 641          /* This data is stored on flash as an array of
 642          * __le32.  Since ql_read32() returns cpu endian
 643          * we need to swap it back.
 644          */
 645         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 646 exit:
 647         return status;
 648 }
 649
 650 static int ql_get_flash_params(struct ql_adapter *qdev)
 651 {
 652         int i;
 653         int status;
 654         __le32 *p = (__le32 *)&qdev->flash;
 655         u32 offset = 0;
 656
 657         /* Second function's parameters follow the first
 658          * function's.
 659          */
 660         if (qdev->func)
 661                 offset = sizeof(qdev->flash) / sizeof(u32);
 662
 663         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 664                 return -ETIMEDOUT;
 665
 666         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 667                 status = ql_read_flash_word(qdev, i+offset, p);
 668                 if (status) {
 669                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 670                         goto exit;
 671                 }
 672
 673         }
 674 exit:
 675         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 676         return status;
 677 }
 678
 679 /* xgmac register are located behind the xgmac_addr and xgmac_data
 680  * register pair.  Each read/write requires us to wait for the ready
 681  * bit before reading/writing the data.
 682  */
 683 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 684 {
 685         int status;
 686         /* wait for reg to come ready */
 687         status = ql_wait_reg_rdy(qdev,
 688                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 689         if (status)
 690                 return status;
 691         /* write the data to the data reg */
 692         ql_write32(qdev, XGMAC_DATA, data);
 693         /* trigger the write */
 694         ql_write32(qdev, XGMAC_ADDR, reg);
 695         return status;
 696 }
 697
 698 /* xgmac register are located behind the xgmac_addr and xgmac_data
 699  * register pair.  Each read/write requires us to wait for the ready
 700  * bit before reading/writing the data.
 701  */
 702 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 703 {
 704         int status = 0;
 705         /* wait for reg to come ready */
 706         status = ql_wait_reg_rdy(qdev,
 707                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 708         if (status)
 709                 goto exit;
 710         /* set up for reg read */
 711         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 712         /* wait for reg to come ready */
 713         status = ql_wait_reg_rdy(qdev,
 714                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 715         if (status)
 716                 goto exit;
 717         /* get the data */
 718         *data = ql_read32(qdev, XGMAC_DATA);
 719 exit:
 720         return status;
 721 }
 722
 723 /* This is used for reading the 64-bit statistics regs. */
 724 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 725 {
 726         int status = 0;
 727         u32 hi = 0;
 728         u32 lo = 0;
 729
 730         status = ql_read_xgmac_reg(qdev, reg, &lo);
 731         if (status)
 732                 goto exit;
 733
 734         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 735         if (status)
 736                 goto exit;
 737
 738         *data = (u64) lo | ((u64) hi << 32);
 739
 740 exit:
 741         return status;
 742 }
 743
 744 /* Take the MAC Core out of reset.
 745  * Enable statistics counting.
 746  * Take the transmitter/receiver out of reset.
 747  * This functionality may be done in the MPI firmware at a
 748  * later date.
 749  */
 750 static int ql_port_initialize(struct ql_adapter *qdev)
 751 {
 752         int status = 0;
 753         u32 data;
 754
 755         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 756                 /* Another function has the semaphore, so
 757                  * wait for the port init bit to come ready.
 758                  */
 759                 QPRINTK(qdev, LINK, INFO,
 760                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 761                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 762                 if (status) {
 763                         QPRINTK(qdev, LINK, CRIT,
 764                                 "Port initialize timed out.\n");
 765                 }
 766                 return status;
 767         }
 768
 769         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 770         /* Set the core reset. */
 771         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 772         if (status)
 773                 goto end;
 774         data |= GLOBAL_CFG_RESET;
 775         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 776         if (status)
 777                 goto end;
 778
 779         /* Clear the core reset and turn on jumbo for receiver. */
 780         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 781         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 782         data |= GLOBAL_CFG_TX_STAT_EN;
 783         data |= GLOBAL_CFG_RX_STAT_EN;
 784         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 785         if (status)
 786                 goto end;
 787
 788         /* Enable transmitter, and clear it's reset. */
 789         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 790         if (status)
 791                 goto end;
 792         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 793         data |= TX_CFG_EN;      /* Enable the transmitter. */
 794         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 795         if (status)
 796                 goto end;
 797
 798         /* Enable receiver and clear it's reset. */
 799         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 800         if (status)
 801                 goto end;
 802         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 803         data |= RX_CFG_EN;      /* Enable the receiver. */
 804         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 805         if (status)
 806                 goto end;
 807
 808         /* Turn on jumbo. */
 809         status =
 810             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 811         if (status)
 812                 goto end;
 813         status =
 814             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 815         if (status)
 816                 goto end;
 817
 818         /* Signal to the world that the port is enabled.        */
 819         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 820 end:
 821         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 822         return status;
 823 }
 824
 825 /* Get the next large buffer. */
 826 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 827 {
 828         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 829         rx_ring->lbq_curr_idx++;
 830         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 831                 rx_ring->lbq_curr_idx = 0;
 832         rx_ring->lbq_free_cnt++;
 833         return lbq_desc;
 834 }
 835
 836 /* Get the next small buffer. */
 837 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 838 {
 839         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 840         rx_ring->sbq_curr_idx++;
 841         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 842                 rx_ring->sbq_curr_idx = 0;
 843         rx_ring->sbq_free_cnt++;
 844         return sbq_desc;
 845 }
 846
 847 /* Update an rx ring index. */
 848 static void ql_update_cq(struct rx_ring *rx_ring)
 849 {
 850         rx_ring->cnsmr_idx++;
 851         rx_ring->curr_entry++;
 852         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 853                 rx_ring->cnsmr_idx = 0;
 854                 rx_ring->curr_entry = rx_ring->cq_base;
 855         }
 856 }
 857
 858 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 859 {
 860         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 861 }
 862
 863 /* Process (refill) a large buffer queue. */
 864 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 865 {
 866         int clean_idx = rx_ring->lbq_clean_idx;
 867         struct bq_desc *lbq_desc;
 868         u64 map;
 869         int i;
 870
 871         while (rx_ring->lbq_free_cnt > 16) {
 872                 for (i = 0; i < 16; i++) {
 873                         QPRINTK(qdev, RX_STATUS, DEBUG,
 874                                 "lbq: try cleaning clean_idx = %d.\n",
 875                                 clean_idx);
 876                         lbq_desc = &rx_ring->lbq[clean_idx];
 877                         if (lbq_desc->p.lbq_page == NULL) {
 878                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 879                                         "lbq: getting new page for index %d.\n",
 880                                         lbq_desc->index);
 881                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 882                                 if (lbq_desc->p.lbq_page == NULL) {
 883                                         rx_ring->lbq_clean_idx = clean_idx;
 884                                         QPRINTK(qdev, RX_STATUS, ERR,
 885                                                 "Couldn't get a page.\n");
 886                                         return;
 887                                 }
 888                                 map = pci_map_page(qdev->pdev,
 889                                                    lbq_desc->p.lbq_page,
 890                                                    0, PAGE_SIZE,
 891                                                    PCI_DMA_FROMDEVICE);
 892                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 893                                         rx_ring->lbq_clean_idx = clean_idx;
 894                                         put_page(lbq_desc->p.lbq_page);
 895                                         lbq_desc->p.lbq_page = NULL;
 896                                         QPRINTK(qdev, RX_STATUS, ERR,
 897                                                 "PCI mapping failed.\n");
 898                                         return;
 899                                 }
 900                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 901                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 902                                 *lbq_desc->addr = cpu_to_le64(map);
 903                         }
 904                         clean_idx++;
 905                         if (clean_idx == rx_ring->lbq_len)
 906                                 clean_idx = 0;
 907                 }
 908
 909                 rx_ring->lbq_clean_idx = clean_idx;
 910                 rx_ring->lbq_prod_idx += 16;
 911                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 912                         rx_ring->lbq_prod_idx = 0;
 913                 QPRINTK(qdev, RX_STATUS, DEBUG,
 914                         "lbq: updating prod idx = %d.\n",
 915                         rx_ring->lbq_prod_idx);
 916                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 917                                 rx_ring->lbq_prod_idx_db_reg);
 918                 rx_ring->lbq_free_cnt -= 16;
 919         }
 920 }
 921
 922 /* Process (refill) a small buffer queue. */
 923 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 924 {
 925         int clean_idx = rx_ring->sbq_clean_idx;
 926         struct bq_desc *sbq_desc;
 927         u64 map;
 928         int i;
 929
 930         while (rx_ring->sbq_free_cnt > 16) {
 931                 for (i = 0; i < 16; i++) {
 932                         sbq_desc = &rx_ring->sbq[clean_idx];
 933                         QPRINTK(qdev, RX_STATUS, DEBUG,
 934                                 "sbq: try cleaning clean_idx = %d.\n",
 935                                 clean_idx);
 936                         if (sbq_desc->p.skb == NULL) {
 937                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 938                                         "sbq: getting new skb for index %d.\n",
 939                                         sbq_desc->index);
 940                                 sbq_desc->p.skb =
 941                                     netdev_alloc_skb(qdev->ndev,
 942                                                      rx_ring->sbq_buf_size);
 943                                 if (sbq_desc->p.skb == NULL) {
 944                                         QPRINTK(qdev, PROBE, ERR,
 945                                                 "Couldn't get an skb.\n");
 946                                         rx_ring->sbq_clean_idx = clean_idx;
 947                                         return;
 948                                 }
 949                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 950                                 map = pci_map_single(qdev->pdev,
 951                                                      sbq_desc->p.skb->data,
 952                                                      rx_ring->sbq_buf_size /
 953                                                      2, PCI_DMA_FROMDEVICE);
 954                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 955                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
 956                                         rx_ring->sbq_clean_idx = clean_idx;
 957                                         dev_kfree_skb_any(sbq_desc->p.skb);
 958                                         sbq_desc->p.skb = NULL;
 959                                         return;
 960                                 }
 961                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 962                                 pci_unmap_len_set(sbq_desc, maplen,
 963                                                   rx_ring->sbq_buf_size / 2);
 964                                 *sbq_desc->addr = cpu_to_le64(map);
 965                         }
 966
 967                         clean_idx++;
 968                         if (clean_idx == rx_ring->sbq_len)
 969                                 clean_idx = 0;
 970                 }
 971                 rx_ring->sbq_clean_idx = clean_idx;
 972                 rx_ring->sbq_prod_idx += 16;
 973                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 974                         rx_ring->sbq_prod_idx = 0;
 975                 QPRINTK(qdev, RX_STATUS, DEBUG,
 976                         "sbq: updating prod idx = %d.\n",
 977                         rx_ring->sbq_prod_idx);
 978                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 979                                 rx_ring->sbq_prod_idx_db_reg);
 980
 981                 rx_ring->sbq_free_cnt -= 16;
 982         }
 983 }
 984
 985 static void ql_update_buffer_queues(struct ql_adapter *qdev,
 986                                     struct rx_ring *rx_ring)
 987 {
 988         ql_update_sbq(qdev, rx_ring);
 989         ql_update_lbq(qdev, rx_ring);
 990 }
 991
 992 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
 993  * fails at some stage, or from the interrupt when a tx completes.
 994  */
 995 static void ql_unmap_send(struct ql_adapter *qdev,
 996                           struct tx_ring_desc *tx_ring_desc, int mapped)
 997 {
 998         int i;
 999         for (i = 0; i < mapped; i++) {
1000                 if (i == 0 || (i == 7 && mapped > 7)) {
1001                         /*
1002                          * Unmap the skb->data area, or the
1003                          * external sglist (AKA the Outbound
1004                          * Address List (OAL)).
1005                          * If its the zeroeth element, then it's
1006                          * the skb->data area.  If it's the 7th
1007                          * element and there is more than 6 frags,
1008                          * then its an OAL.
1009                          */
1010                         if (i == 7) {
1011                                 QPRINTK(qdev, TX_DONE, DEBUG,
1012                                         "unmapping OAL area.\n");
1013                         }
1014                         pci_unmap_single(qdev->pdev,
1015                                          pci_unmap_addr(&tx_ring_desc->map[i],
1016                                                         mapaddr),
1017                                          pci_unmap_len(&tx_ring_desc->map[i],
1018                                                        maplen),
1019                                          PCI_DMA_TODEVICE);
1020                 } else {
1021                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1022                                 i);
1023                         pci_unmap_page(qdev->pdev,
1024                                        pci_unmap_addr(&tx_ring_desc->map[i],
1025                                                       mapaddr),
1026                                        pci_unmap_len(&tx_ring_desc->map[i],
1027                                                      maplen), PCI_DMA_TODEVICE);
1028                 }
1029         }
1030
1031 }
1032
1033 /* Map the buffers for this transmit.  This will return
1034  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1035  */
1036 static int ql_map_send(struct ql_adapter *qdev,
1037                        struct ob_mac_iocb_req *mac_iocb_ptr,
1038                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1039 {
1040         int len = skb_headlen(skb);
1041         dma_addr_t map;
1042         int frag_idx, err, map_idx = 0;
1043         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1044         int frag_cnt = skb_shinfo(skb)->nr_frags;
1045
1046         if (frag_cnt) {
1047                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1048         }
1049         /*
1050          * Map the skb buffer first.
1051          */
1052         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1053
1054         err = pci_dma_mapping_error(qdev->pdev, map);
1055         if (err) {
1056                 QPRINTK(qdev, TX_QUEUED, ERR,
1057                         "PCI mapping failed with error: %d\n", err);
1058
1059                 return NETDEV_TX_BUSY;
1060         }
1061
1062         tbd->len = cpu_to_le32(len);
1063         tbd->addr = cpu_to_le64(map);
1064         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1065         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1066         map_idx++;
1067
1068         /*
1069          * This loop fills the remainder of the 8 address descriptors
1070          * in the IOCB.  If there are more than 7 fragments, then the
1071          * eighth address desc will point to an external list (OAL).
1072          * When this happens, the remainder of the frags will be stored
1073          * in this list.
1074          */
1075         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1076                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1077                 tbd++;
1078                 if (frag_idx == 6 && frag_cnt > 7) {
1079                         /* Let's tack on an sglist.
1080                          * Our control block will now
1081                          * look like this:
1082                          * iocb->seg[0] = skb->data
1083                          * iocb->seg[1] = frag[0]
1084                          * iocb->seg[2] = frag[1]
1085                          * iocb->seg[3] = frag[2]
1086                          * iocb->seg[4] = frag[3]
1087                          * iocb->seg[5] = frag[4]
1088                          * iocb->seg[6] = frag[5]
1089                          * iocb->seg[7] = ptr to OAL (external sglist)
1090                          * oal->seg[0] = frag[6]
1091                          * oal->seg[1] = frag[7]
1092                          * oal->seg[2] = frag[8]
1093                          * oal->seg[3] = frag[9]
1094                          * oal->seg[4] = frag[10]
1095                          *      etc...
1096                          */
1097                         /* Tack on the OAL in the eighth segment of IOCB. */
1098                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1099                                              sizeof(struct oal),
1100                                              PCI_DMA_TODEVICE);
1101                         err = pci_dma_mapping_error(qdev->pdev, map);
1102                         if (err) {
1103                                 QPRINTK(qdev, TX_QUEUED, ERR,
1104                                         "PCI mapping outbound address list with error: %d\n",
1105                                         err);
1106                                 goto map_error;
1107                         }
1108
1109                         tbd->addr = cpu_to_le64(map);
1110                         /*
1111                          * The length is the number of fragments
1112                          * that remain to be mapped times the length
1113                          * of our sglist (OAL).
1114                          */
1115                         tbd->len =
1116                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1117                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1118                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1119                                            map);
1120                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1121                                           sizeof(struct oal));
1122                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1123                         map_idx++;
1124                 }
1125
1126                 map =
1127                     pci_map_page(qdev->pdev, frag->page,
1128                                  frag->page_offset, frag->size,
1129                                  PCI_DMA_TODEVICE);
1130
1131                 err = pci_dma_mapping_error(qdev->pdev, map);
1132                 if (err) {
1133                         QPRINTK(qdev, TX_QUEUED, ERR,
1134                                 "PCI mapping frags failed with error: %d.\n",
1135                                 err);
1136                         goto map_error;
1137                 }
1138
1139                 tbd->addr = cpu_to_le64(map);
1140                 tbd->len = cpu_to_le32(frag->size);
1141                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1142                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1143                                   frag->size);
1144
1145         }
1146         /* Save the number of segments we've mapped. */
1147         tx_ring_desc->map_cnt = map_idx;
1148         /* Terminate the last segment. */
1149         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1150         return NETDEV_TX_OK;
1151
1152 map_error:
1153         /*
1154          * If the first frag mapping failed, then i will be zero.
1155          * This causes the unmap of the skb->data area.  Otherwise
1156          * we pass in the number of frags that mapped successfully
1157          * so they can be umapped.
1158          */
1159         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1160         return NETDEV_TX_BUSY;
1161 }
1162
1163 static void ql_realign_skb(struct sk_buff *skb, int len)
1164 {
1165         void *temp_addr = skb->data;
1166
1167         /* Undo the skb_reserve(skb,32) we did before
1168          * giving to hardware, and realign data on
1169          * a 2-byte boundary.
1170          */
1171         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1172         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1173         skb_copy_to_linear_data(skb, temp_addr,
1174                 (unsigned int)len);
1175 }
1176
1177 /*
1178  * This function builds an skb for the given inbound
1179  * completion.  It will be rewritten for readability in the near
1180  * future, but for not it works well.
1181  */
1182 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1183                                        struct rx_ring *rx_ring,
1184                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1185 {
1186         struct bq_desc *lbq_desc;
1187         struct bq_desc *sbq_desc;
1188         struct sk_buff *skb = NULL;
1189         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1190        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1191
1192         /*
1193          * Handle the header buffer if present.
1194          */
1195         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1196             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1197                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1198                 /*
1199                  * Headers fit nicely into a small buffer.
1200                  */
1201                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1202                 pci_unmap_single(qdev->pdev,
1203                                 pci_unmap_addr(sbq_desc, mapaddr),
1204                                 pci_unmap_len(sbq_desc, maplen),
1205                                 PCI_DMA_FROMDEVICE);
1206                 skb = sbq_desc->p.skb;
1207                 ql_realign_skb(skb, hdr_len);
1208                 skb_put(skb, hdr_len);
1209                 sbq_desc->p.skb = NULL;
1210         }
1211
1212         /*
1213          * Handle the data buffer(s).
1214          */
1215         if (unlikely(!length)) {        /* Is there data too? */
1216                 QPRINTK(qdev, RX_STATUS, DEBUG,
1217                         "No Data buffer in this packet.\n");
1218                 return skb;
1219         }
1220
1221         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1222                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1223                         QPRINTK(qdev, RX_STATUS, DEBUG,
1224                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1225                         /*
1226                          * Data is less than small buffer size so it's
1227                          * stuffed in a small buffer.
1228                          * For this case we append the data
1229                          * from the "data" small buffer to the "header" small
1230                          * buffer.
1231                          */
1232                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1233                         pci_dma_sync_single_for_cpu(qdev->pdev,
1234                                                     pci_unmap_addr
1235                                                     (sbq_desc, mapaddr),
1236                                                     pci_unmap_len
1237                                                     (sbq_desc, maplen),
1238                                                     PCI_DMA_FROMDEVICE);
1239                         memcpy(skb_put(skb, length),
1240                                sbq_desc->p.skb->data, length);
1241                         pci_dma_sync_single_for_device(qdev->pdev,
1242                                                        pci_unmap_addr
1243                                                        (sbq_desc,
1244                                                         mapaddr),
1245                                                        pci_unmap_len
1246                                                        (sbq_desc,
1247                                                         maplen),
1248                                                        PCI_DMA_FROMDEVICE);
1249                 } else {
1250                         QPRINTK(qdev, RX_STATUS, DEBUG,
1251                                 "%d bytes in a single small buffer.\n", length);
1252                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1253                         skb = sbq_desc->p.skb;
1254                         ql_realign_skb(skb, length);
1255                         skb_put(skb, length);
1256                         pci_unmap_single(qdev->pdev,
1257                                          pci_unmap_addr(sbq_desc,
1258                                                         mapaddr),
1259                                          pci_unmap_len(sbq_desc,
1260                                                        maplen),
1261                                          PCI_DMA_FROMDEVICE);
1262                         sbq_desc->p.skb = NULL;
1263                 }
1264         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1265                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1266                         QPRINTK(qdev, RX_STATUS, DEBUG,
1267                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1268                         /*
1269                          * The data is in a single large buffer.  We
1270                          * chain it to the header buffer's skb and let
1271                          * it rip.
1272                          */
1273                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1274                         pci_unmap_page(qdev->pdev,
1275                                        pci_unmap_addr(lbq_desc,
1276                                                       mapaddr),
1277                                        pci_unmap_len(lbq_desc, maplen),
1278                                        PCI_DMA_FROMDEVICE);
1279                         QPRINTK(qdev, RX_STATUS, DEBUG,
1280                                 "Chaining page to skb.\n");
1281                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1282                                            0, length);
1283                         skb->len += length;
1284                         skb->data_len += length;
1285                         skb->truesize += length;
1286                         lbq_desc->p.lbq_page = NULL;
1287                 } else {
1288                         /*
1289                          * The headers and data are in a single large buffer. We
1290                          * copy it to a new skb and let it go. This can happen with
1291                          * jumbo mtu on a non-TCP/UDP frame.
1292                          */
1293                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1294                         skb = netdev_alloc_skb(qdev->ndev, length);
1295                         if (skb == NULL) {
1296                                 QPRINTK(qdev, PROBE, DEBUG,
1297                                         "No skb available, drop the packet.\n");
1298                                 return NULL;
1299                         }
1300                         pci_unmap_page(qdev->pdev,
1301                                        pci_unmap_addr(lbq_desc,
1302                                                       mapaddr),
1303                                        pci_unmap_len(lbq_desc, maplen),
1304                                        PCI_DMA_FROMDEVICE);
1305                         skb_reserve(skb, NET_IP_ALIGN);
1306                         QPRINTK(qdev, RX_STATUS, DEBUG,
1307                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1308                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1309                                            0, length);
1310                         skb->len += length;
1311                         skb->data_len += length;
1312                         skb->truesize += length;
1313                         length -= length;
1314                         lbq_desc->p.lbq_page = NULL;
1315                         __pskb_pull_tail(skb,
1316                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1317                                 VLAN_ETH_HLEN : ETH_HLEN);
1318                 }
1319         } else {
1320                 /*
1321                  * The data is in a chain of large buffers
1322                  * pointed to by a small buffer.  We loop
1323                  * thru and chain them to the our small header
1324                  * buffer's skb.
1325                  * frags:  There are 18 max frags and our small
1326                  *         buffer will hold 32 of them. The thing is,
1327                  *         we'll use 3 max for our 9000 byte jumbo
1328                  *         frames.  If the MTU goes up we could
1329                  *          eventually be in trouble.
1330                  */
1331                 int size, offset, i = 0;
1332                 __le64 *bq, bq_array[8];
1333                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1334                 pci_unmap_single(qdev->pdev,
1335                                  pci_unmap_addr(sbq_desc, mapaddr),
1336                                  pci_unmap_len(sbq_desc, maplen),
1337                                  PCI_DMA_FROMDEVICE);
1338                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1339                         /*
1340                          * This is an non TCP/UDP IP frame, so
1341                          * the headers aren't split into a small
1342                          * buffer.  We have to use the small buffer
1343                          * that contains our sg list as our skb to
1344                          * send upstairs. Copy the sg list here to
1345                          * a local buffer and use it to find the
1346                          * pages to chain.
1347                          */
1348                         QPRINTK(qdev, RX_STATUS, DEBUG,
1349                                 "%d bytes of headers & data in chain of large.\n", length);
1350                         skb = sbq_desc->p.skb;
1351                         bq = &bq_array[0];
1352                         memcpy(bq, skb->data, sizeof(bq_array));
1353                         sbq_desc->p.skb = NULL;
1354                         skb_reserve(skb, NET_IP_ALIGN);
1355                 } else {
1356                         QPRINTK(qdev, RX_STATUS, DEBUG,
1357                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1358                         bq = (__le64 *)sbq_desc->p.skb->data;
1359                 }
1360                 while (length > 0) {
1361                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1362                         pci_unmap_page(qdev->pdev,
1363                                        pci_unmap_addr(lbq_desc,
1364                                                       mapaddr),
1365                                        pci_unmap_len(lbq_desc,
1366                                                      maplen),
1367                                        PCI_DMA_FROMDEVICE);
1368                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1369                         offset = 0;
1370
1371                         QPRINTK(qdev, RX_STATUS, DEBUG,
1372                                 "Adding page %d to skb for %d bytes.\n",
1373                                 i, size);
1374                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1375                                            offset, size);
1376                         skb->len += size;
1377                         skb->data_len += size;
1378                         skb->truesize += size;
1379                         length -= size;
1380                         lbq_desc->p.lbq_page = NULL;
1381                         bq++;
1382                         i++;
1383                 }
1384                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1385                                 VLAN_ETH_HLEN : ETH_HLEN);
1386         }
1387         return skb;
1388 }
1389
1390 /* Process an inbound completion from an rx ring. */
1391 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1392                                    struct rx_ring *rx_ring,
1393                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1394 {
1395         struct net_device *ndev = qdev->ndev;
1396         struct sk_buff *skb = NULL;
1397
1398         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1399
1400         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1401         if (unlikely(!skb)) {
1402                 QPRINTK(qdev, RX_STATUS, DEBUG,
1403                         "No skb available, drop packet.\n");
1404                 return;
1405         }
1406
1407         prefetch(skb->data);
1408         skb->dev = ndev;
1409         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1410                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1411                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1412                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1413                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1414                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1415                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1416                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1417         }
1418         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1419                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1420         }
1421         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1422                 QPRINTK(qdev, RX_STATUS, ERR,
1423                         "Bad checksum for this %s packet.\n",
1424                         ((ib_mac_rsp->
1425                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1426                 skb->ip_summed = CHECKSUM_NONE;
1427         } else if (qdev->rx_csum &&
1428                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1429                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1430                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1431                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1432                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1433         }
1434         qdev->stats.rx_packets++;
1435         qdev->stats.rx_bytes += skb->len;
1436         skb->protocol = eth_type_trans(skb, ndev);
1437         skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1438         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1439                 QPRINTK(qdev, RX_STATUS, DEBUG,
1440                         "Passing a VLAN packet upstream.\n");
1441                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1442                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1443         } else {
1444                 QPRINTK(qdev, RX_STATUS, DEBUG,
1445                         "Passing a normal packet upstream.\n");
1446                 netif_receive_skb(skb);
1447         }
1448 }
1449
1450 /* Process an outbound completion from an rx ring. */
1451 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1452                                    struct ob_mac_iocb_rsp *mac_rsp)
1453 {
1454         struct tx_ring *tx_ring;
1455         struct tx_ring_desc *tx_ring_desc;
1456
1457         QL_DUMP_OB_MAC_RSP(mac_rsp);
1458         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1459         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1460         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1461         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1462         qdev->stats.tx_packets++;
1463         dev_kfree_skb(tx_ring_desc->skb);
1464         tx_ring_desc->skb = NULL;
1465
1466         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1467                                         OB_MAC_IOCB_RSP_S |
1468                                         OB_MAC_IOCB_RSP_L |
1469                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1470                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1471                         QPRINTK(qdev, TX_DONE, WARNING,
1472                                 "Total descriptor length did not match transfer length.\n");
1473                 }
1474                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1475                         QPRINTK(qdev, TX_DONE, WARNING,
1476                                 "Frame too short to be legal, not sent.\n");
1477                 }
1478                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1479                         QPRINTK(qdev, TX_DONE, WARNING,
1480                                 "Frame too long, but sent anyway.\n");
1481                 }
1482                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1483                         QPRINTK(qdev, TX_DONE, WARNING,
1484                                 "PCI backplane error. Frame not sent.\n");
1485                 }
1486         }
1487         atomic_inc(&tx_ring->tx_count);
1488 }
1489
1490 /* Fire up a handler to reset the MPI processor. */
1491 void ql_queue_fw_error(struct ql_adapter *qdev)
1492 {
1493         netif_stop_queue(qdev->ndev);
1494         netif_carrier_off(qdev->ndev);
1495         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1496 }
1497
1498 void ql_queue_asic_error(struct ql_adapter *qdev)
1499 {
1500         netif_stop_queue(qdev->ndev);
1501         netif_carrier_off(qdev->ndev);
1502         ql_disable_interrupts(qdev);
1503         /* Clear adapter up bit to signal the recovery
1504          * process that it shouldn't kill the reset worker
1505          * thread
1506          */
1507         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1508         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1509 }
1510
1511 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1512                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1513 {
1514         switch (ib_ae_rsp->event) {
1515         case MGMT_ERR_EVENT:
1516                 QPRINTK(qdev, RX_ERR, ERR,
1517                         "Management Processor Fatal Error.\n");
1518                 ql_queue_fw_error(qdev);
1519                 return;
1520
1521         case CAM_LOOKUP_ERR_EVENT:
1522                 QPRINTK(qdev, LINK, ERR,
1523                         "Multiple CAM hits lookup occurred.\n");
1524                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1525                 ql_queue_asic_error(qdev);
1526                 return;
1527
1528         case SOFT_ECC_ERROR_EVENT:
1529                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1530                 ql_queue_asic_error(qdev);
1531                 break;
1532
1533         case PCI_ERR_ANON_BUF_RD:
1534                 QPRINTK(qdev, RX_ERR, ERR,
1535                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1536                         ib_ae_rsp->q_id);
1537                 ql_queue_asic_error(qdev);
1538                 break;
1539
1540         default:
1541                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1542                         ib_ae_rsp->event);
1543                 ql_queue_asic_error(qdev);
1544                 break;
1545         }
1546 }
1547
1548 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1549 {
1550         struct ql_adapter *qdev = rx_ring->qdev;
1551         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1552         struct ob_mac_iocb_rsp *net_rsp = NULL;
1553         int count = 0;
1554
1555         /* While there are entries in the completion queue. */
1556         while (prod != rx_ring->cnsmr_idx) {
1557
1558                 QPRINTK(qdev, RX_STATUS, DEBUG,
1559                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1560                         prod, rx_ring->cnsmr_idx);
1561
1562                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1563                 rmb();
1564                 switch (net_rsp->opcode) {
1565
1566                 case OPCODE_OB_MAC_TSO_IOCB:
1567                 case OPCODE_OB_MAC_IOCB:
1568                         ql_process_mac_tx_intr(qdev, net_rsp);
1569                         break;
1570                 default:
1571                         QPRINTK(qdev, RX_STATUS, DEBUG,
1572                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1573                                 net_rsp->opcode);
1574                 }
1575                 count++;
1576                 ql_update_cq(rx_ring);
1577                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1578         }
1579         ql_write_cq_idx(rx_ring);
1580         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1581                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1582                 if (atomic_read(&tx_ring->queue_stopped) &&
1583                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1584                         /*
1585                          * The queue got stopped because the tx_ring was full.
1586                          * Wake it up, because it's now at least 25% empty.
1587                          */
1588                         netif_wake_queue(qdev->ndev);
1589         }
1590
1591         return count;
1592 }
1593
1594 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1595 {
1596         struct ql_adapter *qdev = rx_ring->qdev;
1597         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1598         struct ql_net_rsp_iocb *net_rsp;
1599         int count = 0;
1600
1601         /* While there are entries in the completion queue. */
1602         while (prod != rx_ring->cnsmr_idx) {
1603
1604                 QPRINTK(qdev, RX_STATUS, DEBUG,
1605                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1606                         prod, rx_ring->cnsmr_idx);
1607
1608                 net_rsp = rx_ring->curr_entry;
1609                 rmb();
1610                 switch (net_rsp->opcode) {
1611                 case OPCODE_IB_MAC_IOCB:
1612                         ql_process_mac_rx_intr(qdev, rx_ring,
1613                                                (struct ib_mac_iocb_rsp *)
1614                                                net_rsp);
1615                         break;
1616
1617                 case OPCODE_IB_AE_IOCB:
1618                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1619                                                 net_rsp);
1620                         break;
1621                 default:
1622                         {
1623                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1624                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1625                                         net_rsp->opcode);
1626                         }
1627                 }
1628                 count++;
1629                 ql_update_cq(rx_ring);
1630                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1631                 if (count == budget)
1632                         break;
1633         }
1634         ql_update_buffer_queues(qdev, rx_ring);
1635         ql_write_cq_idx(rx_ring);
1636         return count;
1637 }
1638
1639 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1640 {
1641         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1642         struct ql_adapter *qdev = rx_ring->qdev;
1643         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1644
1645         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1646                 rx_ring->cq_id);
1647
1648         if (work_done < budget) {
1649                 __napi_complete(napi);
1650                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1651         }
1652         return work_done;
1653 }
1654
1655 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1656 {
1657         struct ql_adapter *qdev = netdev_priv(ndev);
1658
1659         qdev->vlgrp = grp;
1660         if (grp) {
1661                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1662                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1663                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1664         } else {
1665                 QPRINTK(qdev, IFUP, DEBUG,
1666                         "Turning off VLAN in NIC_RCV_CFG.\n");
1667                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1668         }
1669 }
1670
1671 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1672 {
1673         struct ql_adapter *qdev = netdev_priv(ndev);
1674         u32 enable_bit = MAC_ADDR_E;
1675         int status;
1676
1677         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1678         if (status)
1679                 return;
1680         spin_lock(&qdev->hw_lock);
1681         if (ql_set_mac_addr_reg
1682             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1683                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1684         }
1685         spin_unlock(&qdev->hw_lock);
1686         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1687 }
1688
1689 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1690 {
1691         struct ql_adapter *qdev = netdev_priv(ndev);
1692         u32 enable_bit = 0;
1693         int status;
1694
1695         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1696         if (status)
1697                 return;
1698
1699         spin_lock(&qdev->hw_lock);
1700         if (ql_set_mac_addr_reg
1701             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1702                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1703         }
1704         spin_unlock(&qdev->hw_lock);
1705         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1706
1707 }
1708
1709 /* Worker thread to process a given rx_ring that is dedicated
1710  * to outbound completions.
1711  */
1712 static void ql_tx_clean(struct work_struct *work)
1713 {
1714         struct rx_ring *rx_ring =
1715             container_of(work, struct rx_ring, rx_work.work);
1716         ql_clean_outbound_rx_ring(rx_ring);
1717         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1718
1719 }
1720
1721 /* Worker thread to process a given rx_ring that is dedicated
1722  * to inbound completions.
1723  */
1724 static void ql_rx_clean(struct work_struct *work)
1725 {
1726         struct rx_ring *rx_ring =
1727             container_of(work, struct rx_ring, rx_work.work);
1728         ql_clean_inbound_rx_ring(rx_ring, 64);
1729         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1730 }
1731
1732 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1733 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1734 {
1735         struct rx_ring *rx_ring = dev_id;
1736         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1737                               &rx_ring->rx_work, 0);
1738         return IRQ_HANDLED;
1739 }
1740
1741 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1742 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1743 {
1744         struct rx_ring *rx_ring = dev_id;
1745         napi_schedule(&rx_ring->napi);
1746         return IRQ_HANDLED;
1747 }
1748
1749 /* This handles a fatal error, MPI activity, and the default
1750  * rx_ring in an MSI-X multiple vector environment.
1751  * In MSI/Legacy environment it also process the rest of
1752  * the rx_rings.
1753  */
1754 static irqreturn_t qlge_isr(int irq, void *dev_id)
1755 {
1756         struct rx_ring *rx_ring = dev_id;
1757         struct ql_adapter *qdev = rx_ring->qdev;
1758         struct intr_context *intr_context = &qdev->intr_context[0];
1759         u32 var;
1760         int i;
1761         int work_done = 0;
1762
1763         spin_lock(&qdev->hw_lock);
1764         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1765                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1766                 spin_unlock(&qdev->hw_lock);
1767                 return IRQ_NONE;
1768         }
1769         spin_unlock(&qdev->hw_lock);
1770
1771         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1772
1773         /*
1774          * Check for fatal error.
1775          */
1776         if (var & STS_FE) {
1777                 ql_queue_asic_error(qdev);
1778                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1779                 var = ql_read32(qdev, ERR_STS);
1780                 QPRINTK(qdev, INTR, ERR,
1781                         "Resetting chip. Error Status Register = 0x%x\n", var);
1782                 return IRQ_HANDLED;
1783         }
1784
1785         /*
1786          * Check MPI processor activity.
1787          */
1788         if (var & STS_PI) {
1789                 /*
1790                  * We've got an async event or mailbox completion.
1791                  * Handle it and clear the source of the interrupt.
1792                  */
1793                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1794                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1795                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1796                                       &qdev->mpi_work, 0);
1797                 work_done++;
1798         }
1799
1800         /*
1801          * Check the default queue and wake handler if active.
1802          */
1803         rx_ring = &qdev->rx_ring[0];
1804         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1805                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1806                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1807                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1808                                       &rx_ring->rx_work, 0);
1809                 work_done++;
1810         }
1811
1812         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1813                 /*
1814                  * Start the DPC for each active queue.
1815                  */
1816                 for (i = 1; i < qdev->rx_ring_count; i++) {
1817                         rx_ring = &qdev->rx_ring[i];
1818                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1819                             rx_ring->cnsmr_idx) {
1820                                 QPRINTK(qdev, INTR, INFO,
1821                                         "Waking handler for rx_ring[%d].\n", i);
1822                                 ql_disable_completion_interrupt(qdev,
1823                                                                 intr_context->
1824                                                                 intr);
1825                                 if (i < qdev->rss_ring_first_cq_id)
1826                                         queue_delayed_work_on(rx_ring->cpu,
1827                                                               qdev->q_workqueue,
1828                                                               &rx_ring->rx_work,
1829                                                               0);
1830                                 else
1831                                         napi_schedule(&rx_ring->napi);
1832                                 work_done++;
1833                         }
1834                 }
1835         }
1836         ql_enable_completion_interrupt(qdev, intr_context->intr);
1837         return work_done ? IRQ_HANDLED : IRQ_NONE;
1838 }
1839
1840 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1841 {
1842
1843         if (skb_is_gso(skb)) {
1844                 int err;
1845                 if (skb_header_cloned(skb)) {
1846                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1847                         if (err)
1848                                 return err;
1849                 }
1850
1851                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1852                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1853                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1854                 mac_iocb_ptr->total_hdrs_len =
1855                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1856                 mac_iocb_ptr->net_trans_offset =
1857                     cpu_to_le16(skb_network_offset(skb) |
1858                                 skb_transport_offset(skb)
1859                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1860                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1861                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1862                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1863                         struct iphdr *iph = ip_hdr(skb);
1864                         iph->check = 0;
1865                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1866                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1867                                                                  iph->daddr, 0,
1868                                                                  IPPROTO_TCP,
1869                                                                  0);
1870                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1871                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1872                         tcp_hdr(skb)->check =
1873                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1874                                              &ipv6_hdr(skb)->daddr,
1875                                              0, IPPROTO_TCP, 0);
1876                 }
1877                 return 1;
1878         }
1879         return 0;
1880 }
1881
1882 static void ql_hw_csum_setup(struct sk_buff *skb,
1883                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1884 {
1885         int len;
1886         struct iphdr *iph = ip_hdr(skb);
1887         __sum16 *check;
1888         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1889         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1890         mac_iocb_ptr->net_trans_offset =
1891                 cpu_to_le16(skb_network_offset(skb) |
1892                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1893
1894         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1895         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1896         if (likely(iph->protocol == IPPROTO_TCP)) {
1897                 check = &(tcp_hdr(skb)->check);
1898                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1899                 mac_iocb_ptr->total_hdrs_len =
1900                     cpu_to_le16(skb_transport_offset(skb) +
1901                                 (tcp_hdr(skb)->doff << 2));
1902         } else {
1903                 check = &(udp_hdr(skb)->check);
1904                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1905                 mac_iocb_ptr->total_hdrs_len =
1906                     cpu_to_le16(skb_transport_offset(skb) +
1907                                 sizeof(struct udphdr));
1908         }
1909         *check = ~csum_tcpudp_magic(iph->saddr,
1910                                     iph->daddr, len, iph->protocol, 0);
1911 }
1912
1913 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1914 {
1915         struct tx_ring_desc *tx_ring_desc;
1916         struct ob_mac_iocb_req *mac_iocb_ptr;
1917         struct ql_adapter *qdev = netdev_priv(ndev);
1918         int tso;
1919         struct tx_ring *tx_ring;
1920         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1921
1922         tx_ring = &qdev->tx_ring[tx_ring_idx];
1923
1924         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1925                 QPRINTK(qdev, TX_QUEUED, INFO,
1926                         "%s: shutting down tx queue %d du to lack of resources.\n",
1927                         __func__, tx_ring_idx);
1928                 netif_stop_queue(ndev);
1929                 atomic_inc(&tx_ring->queue_stopped);
1930                 return NETDEV_TX_BUSY;
1931         }
1932         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1933         mac_iocb_ptr = tx_ring_desc->queue_entry;
1934         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1935
1936         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1937         mac_iocb_ptr->tid = tx_ring_desc->index;
1938         /* We use the upper 32-bits to store the tx queue for this IO.
1939          * When we get the completion we can use it to establish the context.
1940          */
1941         mac_iocb_ptr->txq_idx = tx_ring_idx;
1942         tx_ring_desc->skb = skb;
1943
1944         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1945
1946         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1947                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1948                         vlan_tx_tag_get(skb));
1949                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1950                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1951         }
1952         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1953         if (tso < 0) {
1954                 dev_kfree_skb_any(skb);
1955                 return NETDEV_TX_OK;
1956         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1957                 ql_hw_csum_setup(skb,
1958                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1959         }
1960         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
1961                         NETDEV_TX_OK) {
1962                 QPRINTK(qdev, TX_QUEUED, ERR,
1963                                 "Could not map the segments.\n");
1964                 return NETDEV_TX_BUSY;
1965         }
1966         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1967         tx_ring->prod_idx++;
1968         if (tx_ring->prod_idx == tx_ring->wq_len)
1969                 tx_ring->prod_idx = 0;
1970         wmb();
1971
1972         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1973         ndev->trans_start = jiffies;
1974         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1975                 tx_ring->prod_idx, skb->len);
1976
1977         atomic_dec(&tx_ring->tx_count);
1978         return NETDEV_TX_OK;
1979 }
1980
1981 static void ql_free_shadow_space(struct ql_adapter *qdev)
1982 {
1983         if (qdev->rx_ring_shadow_reg_area) {
1984                 pci_free_consistent(qdev->pdev,
1985                                     PAGE_SIZE,
1986                                     qdev->rx_ring_shadow_reg_area,
1987                                     qdev->rx_ring_shadow_reg_dma);
1988                 qdev->rx_ring_shadow_reg_area = NULL;
1989         }
1990         if (qdev->tx_ring_shadow_reg_area) {
1991                 pci_free_consistent(qdev->pdev,
1992                                     PAGE_SIZE,
1993                                     qdev->tx_ring_shadow_reg_area,
1994                                     qdev->tx_ring_shadow_reg_dma);
1995                 qdev->tx_ring_shadow_reg_area = NULL;
1996         }
1997 }
1998
1999 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2000 {
2001         qdev->rx_ring_shadow_reg_area =
2002             pci_alloc_consistent(qdev->pdev,
2003                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2004         if (qdev->rx_ring_shadow_reg_area == NULL) {
2005                 QPRINTK(qdev, IFUP, ERR,
2006                         "Allocation of RX shadow space failed.\n");
2007                 return -ENOMEM;
2008         }
2009         qdev->tx_ring_shadow_reg_area =
2010             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2011                                  &qdev->tx_ring_shadow_reg_dma);
2012         if (qdev->tx_ring_shadow_reg_area == NULL) {
2013                 QPRINTK(qdev, IFUP, ERR,
2014                         "Allocation of TX shadow space failed.\n");
2015                 goto err_wqp_sh_area;
2016         }
2017         return 0;
2018
2019 err_wqp_sh_area:
2020         pci_free_consistent(qdev->pdev,
2021                             PAGE_SIZE,
2022                             qdev->rx_ring_shadow_reg_area,
2023                             qdev->rx_ring_shadow_reg_dma);
2024         return -ENOMEM;
2025 }
2026
2027 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2028 {
2029         struct tx_ring_desc *tx_ring_desc;
2030         int i;
2031         struct ob_mac_iocb_req *mac_iocb_ptr;
2032
2033         mac_iocb_ptr = tx_ring->wq_base;
2034         tx_ring_desc = tx_ring->q;
2035         for (i = 0; i < tx_ring->wq_len; i++) {
2036                 tx_ring_desc->index = i;
2037                 tx_ring_desc->skb = NULL;
2038                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2039                 mac_iocb_ptr++;
2040                 tx_ring_desc++;
2041         }
2042         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2043         atomic_set(&tx_ring->queue_stopped, 0);
2044 }
2045
2046 static void ql_free_tx_resources(struct ql_adapter *qdev,
2047                                  struct tx_ring *tx_ring)
2048 {
2049         if (tx_ring->wq_base) {
2050                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2051                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2052                 tx_ring->wq_base = NULL;
2053         }
2054         kfree(tx_ring->q);
2055         tx_ring->q = NULL;
2056 }
2057
2058 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2059                                  struct tx_ring *tx_ring)
2060 {
2061         tx_ring->wq_base =
2062             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2063                                  &tx_ring->wq_base_dma);
2064
2065         if ((tx_ring->wq_base == NULL)
2066             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2067                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2068                 return -ENOMEM;
2069         }
2070         tx_ring->q =
2071             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2072         if (tx_ring->q == NULL)
2073                 goto err;
2074
2075         return 0;
2076 err:
2077         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2078                             tx_ring->wq_base, tx_ring->wq_base_dma);
2079         return -ENOMEM;
2080 }
2081
2082 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2083 {
2084         int i;
2085         struct bq_desc *lbq_desc;
2086
2087         for (i = 0; i < rx_ring->lbq_len; i++) {
2088                 lbq_desc = &rx_ring->lbq[i];
2089                 if (lbq_desc->p.lbq_page) {
2090                         pci_unmap_page(qdev->pdev,
2091                                        pci_unmap_addr(lbq_desc, mapaddr),
2092                                        pci_unmap_len(lbq_desc, maplen),
2093                                        PCI_DMA_FROMDEVICE);
2094
2095                         put_page(lbq_desc->p.lbq_page);
2096                         lbq_desc->p.lbq_page = NULL;
2097                 }
2098         }
2099 }
2100
2101 /*
2102  * Allocate and map a page for each element of the lbq.
2103  */
2104 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2105                                 struct rx_ring *rx_ring)
2106 {
2107         int i;
2108         struct bq_desc *lbq_desc;
2109         u64 map;
2110         __le64 *bq = rx_ring->lbq_base;
2111
2112         for (i = 0; i < rx_ring->lbq_len; i++) {
2113                 lbq_desc = &rx_ring->lbq[i];
2114                 memset(lbq_desc, 0, sizeof(lbq_desc));
2115                 lbq_desc->addr = bq;
2116                 lbq_desc->index = i;
2117                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2118                 if (unlikely(!lbq_desc->p.lbq_page)) {
2119                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2120                         goto mem_error;
2121                 } else {
2122                         map = pci_map_page(qdev->pdev,
2123                                            lbq_desc->p.lbq_page,
2124                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2125                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2126                                 QPRINTK(qdev, IFUP, ERR,
2127                                         "PCI mapping failed.\n");
2128                                 goto mem_error;
2129                         }
2130                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2131                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2132                         *lbq_desc->addr = cpu_to_le64(map);
2133                 }
2134                 bq++;
2135         }
2136         return 0;
2137 mem_error:
2138         ql_free_lbq_buffers(qdev, rx_ring);
2139         return -ENOMEM;
2140 }
2141
2142 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2143 {
2144         int i;
2145         struct bq_desc *sbq_desc;
2146
2147         for (i = 0; i < rx_ring->sbq_len; i++) {
2148                 sbq_desc = &rx_ring->sbq[i];
2149                 if (sbq_desc == NULL) {
2150                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2151                         return;
2152                 }
2153                 if (sbq_desc->p.skb) {
2154                         pci_unmap_single(qdev->pdev,
2155                                          pci_unmap_addr(sbq_desc, mapaddr),
2156                                          pci_unmap_len(sbq_desc, maplen),
2157                                          PCI_DMA_FROMDEVICE);
2158                         dev_kfree_skb(sbq_desc->p.skb);
2159                         sbq_desc->p.skb = NULL;
2160                 }
2161         }
2162 }
2163
2164 /* Allocate and map an skb for each element of the sbq. */
2165 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2166                                 struct rx_ring *rx_ring)
2167 {
2168         int i;
2169         struct bq_desc *sbq_desc;
2170         struct sk_buff *skb;
2171         u64 map;
2172         __le64 *bq = rx_ring->sbq_base;
2173
2174         for (i = 0; i < rx_ring->sbq_len; i++) {
2175                 sbq_desc = &rx_ring->sbq[i];
2176                 memset(sbq_desc, 0, sizeof(sbq_desc));
2177                 sbq_desc->index = i;
2178                 sbq_desc->addr = bq;
2179                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2180                 if (unlikely(!skb)) {
2181                         /* Better luck next round */
2182                         QPRINTK(qdev, IFUP, ERR,
2183                                 "small buff alloc failed for %d bytes at index %d.\n",
2184                                 rx_ring->sbq_buf_size, i);
2185                         goto mem_err;
2186                 }
2187                 skb_reserve(skb, QLGE_SB_PAD);
2188                 sbq_desc->p.skb = skb;
2189                 /*
2190                  * Map only half the buffer. Because the
2191                  * other half may get some data copied to it
2192                  * when the completion arrives.
2193                  */
2194                 map = pci_map_single(qdev->pdev,
2195                                      skb->data,
2196                                      rx_ring->sbq_buf_size / 2,
2197                                      PCI_DMA_FROMDEVICE);
2198                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2199                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2200                         goto mem_err;
2201                 }
2202                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2203                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2204                 *sbq_desc->addr = cpu_to_le64(map);
2205                 bq++;
2206         }
2207         return 0;
2208 mem_err:
2209         ql_free_sbq_buffers(qdev, rx_ring);
2210         return -ENOMEM;
2211 }
2212
2213 static void ql_free_rx_resources(struct ql_adapter *qdev,
2214                                  struct rx_ring *rx_ring)
2215 {
2216         if (rx_ring->sbq_len)
2217                 ql_free_sbq_buffers(qdev, rx_ring);
2218         if (rx_ring->lbq_len)
2219                 ql_free_lbq_buffers(qdev, rx_ring);
2220
2221         /* Free the small buffer queue. */
2222         if (rx_ring->sbq_base) {
2223                 pci_free_consistent(qdev->pdev,
2224                                     rx_ring->sbq_size,
2225                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2226                 rx_ring->sbq_base = NULL;
2227         }
2228
2229         /* Free the small buffer queue control blocks. */
2230         kfree(rx_ring->sbq);
2231         rx_ring->sbq = NULL;
2232
2233         /* Free the large buffer queue. */
2234         if (rx_ring->lbq_base) {
2235                 pci_free_consistent(qdev->pdev,
2236                                     rx_ring->lbq_size,
2237                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2238                 rx_ring->lbq_base = NULL;
2239         }
2240
2241         /* Free the large buffer queue control blocks. */
2242         kfree(rx_ring->lbq);
2243         rx_ring->lbq = NULL;
2244
2245         /* Free the rx queue. */
2246         if (rx_ring->cq_base) {
2247                 pci_free_consistent(qdev->pdev,
2248                                     rx_ring->cq_size,
2249                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2250                 rx_ring->cq_base = NULL;
2251         }
2252 }
2253
2254 /* Allocate queues and buffers for this completions queue based
2255  * on the values in the parameter structure. */
2256 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2257                                  struct rx_ring *rx_ring)
2258 {
2259
2260         /*
2261          * Allocate the completion queue for this rx_ring.
2262          */
2263         rx_ring->cq_base =
2264             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2265                                  &rx_ring->cq_base_dma);
2266
2267         if (rx_ring->cq_base == NULL) {
2268                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2269                 return -ENOMEM;
2270         }
2271
2272         if (rx_ring->sbq_len) {
2273                 /*
2274                  * Allocate small buffer queue.
2275                  */
2276                 rx_ring->sbq_base =
2277                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2278                                          &rx_ring->sbq_base_dma);
2279
2280                 if (rx_ring->sbq_base == NULL) {
2281                         QPRINTK(qdev, IFUP, ERR,
2282                                 "Small buffer queue allocation failed.\n");
2283                         goto err_mem;
2284                 }
2285
2286                 /*
2287                  * Allocate small buffer queue control blocks.
2288                  */
2289                 rx_ring->sbq =
2290                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2291                             GFP_KERNEL);
2292                 if (rx_ring->sbq == NULL) {
2293                         QPRINTK(qdev, IFUP, ERR,
2294                                 "Small buffer queue control block allocation failed.\n");
2295                         goto err_mem;
2296                 }
2297
2298                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2299                         QPRINTK(qdev, IFUP, ERR,
2300                                 "Small buffer allocation failed.\n");
2301                         goto err_mem;
2302                 }
2303         }
2304
2305         if (rx_ring->lbq_len) {
2306                 /*
2307                  * Allocate large buffer queue.
2308                  */
2309                 rx_ring->lbq_base =
2310                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2311                                          &rx_ring->lbq_base_dma);
2312
2313                 if (rx_ring->lbq_base == NULL) {
2314                         QPRINTK(qdev, IFUP, ERR,
2315                                 "Large buffer queue allocation failed.\n");
2316                         goto err_mem;
2317                 }
2318                 /*
2319                  * Allocate large buffer queue control blocks.
2320                  */
2321                 rx_ring->lbq =
2322                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2323                             GFP_KERNEL);
2324                 if (rx_ring->lbq == NULL) {
2325                         QPRINTK(qdev, IFUP, ERR,
2326                                 "Large buffer queue control block allocation failed.\n");
2327                         goto err_mem;
2328                 }
2329
2330                 /*
2331                  * Allocate the buffers.
2332                  */
2333                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2334                         QPRINTK(qdev, IFUP, ERR,
2335                                 "Large buffer allocation failed.\n");
2336                         goto err_mem;
2337                 }
2338         }
2339
2340         return 0;
2341
2342 err_mem:
2343         ql_free_rx_resources(qdev, rx_ring);
2344         return -ENOMEM;
2345 }
2346
2347 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2348 {
2349         struct tx_ring *tx_ring;
2350         struct tx_ring_desc *tx_ring_desc;
2351         int i, j;
2352
2353         /*
2354          * Loop through all queues and free
2355          * any resources.
2356          */
2357         for (j = 0; j < qdev->tx_ring_count; j++) {
2358                 tx_ring = &qdev->tx_ring[j];
2359                 for (i = 0; i < tx_ring->wq_len; i++) {
2360                         tx_ring_desc = &tx_ring->q[i];
2361                         if (tx_ring_desc && tx_ring_desc->skb) {
2362                                 QPRINTK(qdev, IFDOWN, ERR,
2363                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2364                                         tx_ring_desc->skb, j,
2365                                         tx_ring_desc->index);
2366                                 ql_unmap_send(qdev, tx_ring_desc,
2367                                               tx_ring_desc->map_cnt);
2368                                 dev_kfree_skb(tx_ring_desc->skb);
2369                                 tx_ring_desc->skb = NULL;
2370                         }
2371                 }
2372         }
2373 }
2374
2375 static void ql_free_mem_resources(struct ql_adapter *qdev)
2376 {
2377         int i;
2378
2379         for (i = 0; i < qdev->tx_ring_count; i++)
2380                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2381         for (i = 0; i < qdev->rx_ring_count; i++)
2382                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2383         ql_free_shadow_space(qdev);
2384 }
2385
2386 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2387 {
2388         int i;
2389
2390         /* Allocate space for our shadow registers and such. */
2391         if (ql_alloc_shadow_space(qdev))
2392                 return -ENOMEM;
2393
2394         for (i = 0; i < qdev->rx_ring_count; i++) {
2395                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2396                         QPRINTK(qdev, IFUP, ERR,
2397                                 "RX resource allocation failed.\n");
2398                         goto err_mem;
2399                 }
2400         }
2401         /* Allocate tx queue resources */
2402         for (i = 0; i < qdev->tx_ring_count; i++) {
2403                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2404                         QPRINTK(qdev, IFUP, ERR,
2405                                 "TX resource allocation failed.\n");
2406                         goto err_mem;
2407                 }
2408         }
2409         return 0;
2410
2411 err_mem:
2412         ql_free_mem_resources(qdev);
2413         return -ENOMEM;
2414 }
2415
2416 /* Set up the rx ring control block and pass it to the chip.
2417  * The control block is defined as
2418  * "Completion Queue Initialization Control Block", or cqicb.
2419  */
2420 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2421 {
2422         struct cqicb *cqicb = &rx_ring->cqicb;
2423         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2424             (rx_ring->cq_id * sizeof(u64) * 4);
2425         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2426             (rx_ring->cq_id * sizeof(u64) * 4);
2427         void __iomem *doorbell_area =
2428             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2429         int err = 0;
2430         u16 bq_len;
2431
2432         /* Set up the shadow registers for this ring. */
2433         rx_ring->prod_idx_sh_reg = shadow_reg;
2434         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2435         shadow_reg += sizeof(u64);
2436         shadow_reg_dma += sizeof(u64);
2437         rx_ring->lbq_base_indirect = shadow_reg;
2438         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2439         shadow_reg += sizeof(u64);
2440         shadow_reg_dma += sizeof(u64);
2441         rx_ring->sbq_base_indirect = shadow_reg;
2442         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2443
2444         /* PCI doorbell mem area + 0x00 for consumer index register */
2445         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2446         rx_ring->cnsmr_idx = 0;
2447         rx_ring->curr_entry = rx_ring->cq_base;
2448
2449         /* PCI doorbell mem area + 0x04 for valid register */
2450         rx_ring->valid_db_reg = doorbell_area + 0x04;
2451
2452         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2453         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2454
2455         /* PCI doorbell mem area + 0x1c */
2456         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2457
2458         memset((void *)cqicb, 0, sizeof(struct cqicb));
2459         cqicb->msix_vect = rx_ring->irq;
2460
2461         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2462         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2463
2464         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2465
2466         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2467
2468         /*
2469          * Set up the control block load flags.
2470          */
2471         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2472             FLAGS_LV |          /* Load MSI-X vector */
2473             FLAGS_LI;           /* Load irq delay values */
2474         if (rx_ring->lbq_len) {
2475                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2476                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2477                 cqicb->lbq_addr =
2478                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2479                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2480                         (u16) rx_ring->lbq_buf_size;
2481                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2482                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2483                         (u16) rx_ring->lbq_len;
2484                 cqicb->lbq_len = cpu_to_le16(bq_len);
2485                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2486                 rx_ring->lbq_curr_idx = 0;
2487                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2488                 rx_ring->lbq_free_cnt = 16;
2489         }
2490         if (rx_ring->sbq_len) {
2491                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2492                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2493                 cqicb->sbq_addr =
2494                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2495                 cqicb->sbq_buf_size =
2496                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2497                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2498                         (u16) rx_ring->sbq_len;
2499                 cqicb->sbq_len = cpu_to_le16(bq_len);
2500                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2501                 rx_ring->sbq_curr_idx = 0;
2502                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2503                 rx_ring->sbq_free_cnt = 16;
2504         }
2505         switch (rx_ring->type) {
2506         case TX_Q:
2507                 /* If there's only one interrupt, then we use
2508                  * worker threads to process the outbound
2509                  * completion handling rx_rings. We do this so
2510                  * they can be run on multiple CPUs. There is
2511                  * room to play with this more where we would only
2512                  * run in a worker if there are more than x number
2513                  * of outbound completions on the queue and more
2514                  * than one queue active.  Some threshold that
2515                  * would indicate a benefit in spite of the cost
2516                  * of a context switch.
2517                  * If there's more than one interrupt, then the
2518                  * outbound completions are processed in the ISR.
2519                  */
2520                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2521                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2522                 else {
2523                         /* With all debug warnings on we see a WARN_ON message
2524                          * when we free the skb in the interrupt context.
2525                          */
2526                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2527                 }
2528                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2529                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2530                 break;
2531         case DEFAULT_Q:
2532                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2533                 cqicb->irq_delay = 0;
2534                 cqicb->pkt_delay = 0;
2535                 break;
2536         case RX_Q:
2537                 /* Inbound completion handling rx_rings run in
2538                  * separate NAPI contexts.
2539                  */
2540                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2541                                64);
2542                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2543                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2544                 break;
2545         default:
2546                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2547                         rx_ring->type);
2548         }
2549         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2550         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2551                            CFG_LCQ, rx_ring->cq_id);
2552         if (err) {
2553                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2554                 return err;
2555         }
2556         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2557         /*
2558          * Advance the producer index for the buffer queues.
2559          */
2560         wmb();
2561         if (rx_ring->lbq_len)
2562                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2563                                 rx_ring->lbq_prod_idx_db_reg);
2564         if (rx_ring->sbq_len)
2565                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2566                                 rx_ring->sbq_prod_idx_db_reg);
2567         return err;
2568 }
2569
2570 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2571 {
2572         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2573         void __iomem *doorbell_area =
2574             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2575         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2576             (tx_ring->wq_id * sizeof(u64));
2577         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2578             (tx_ring->wq_id * sizeof(u64));
2579         int err = 0;
2580
2581         /*
2582          * Assign doorbell registers for this tx_ring.
2583          */
2584         /* TX PCI doorbell mem area for tx producer index */
2585         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2586         tx_ring->prod_idx = 0;
2587         /* TX PCI doorbell mem area + 0x04 */
2588         tx_ring->valid_db_reg = doorbell_area + 0x04;
2589
2590         /*
2591          * Assign shadow registers for this tx_ring.
2592          */
2593         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2594         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2595
2596         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2597         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2598                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2599         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2600         wqicb->rid = 0;
2601         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2602
2603         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2604
2605         ql_init_tx_ring(qdev, tx_ring);
2606
2607         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2608                            (u16) tx_ring->wq_id);
2609         if (err) {
2610                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2611                 return err;
2612         }
2613         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2614         return err;
2615 }
2616
2617 static void ql_disable_msix(struct ql_adapter *qdev)
2618 {
2619         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2620                 pci_disable_msix(qdev->pdev);
2621                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2622                 kfree(qdev->msi_x_entry);
2623                 qdev->msi_x_entry = NULL;
2624         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2625                 pci_disable_msi(qdev->pdev);
2626                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2627         }
2628 }
2629
2630 static void ql_enable_msix(struct ql_adapter *qdev)
2631 {
2632         int i;
2633
2634         qdev->intr_count = 1;
2635         /* Get the MSIX vectors. */
2636         if (irq_type == MSIX_IRQ) {
2637                 /* Try to alloc space for the msix struct,
2638                  * if it fails then go to MSI/legacy.
2639                  */
2640                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2641                                             sizeof(struct msix_entry),
2642                                             GFP_KERNEL);
2643                 if (!qdev->msi_x_entry) {
2644                         irq_type = MSI_IRQ;
2645                         goto msi;
2646                 }
2647
2648                 for (i = 0; i < qdev->rx_ring_count; i++)
2649                         qdev->msi_x_entry[i].entry = i;
2650
2651                 if (!pci_enable_msix
2652                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2653                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2654                         qdev->intr_count = qdev->rx_ring_count;
2655                         QPRINTK(qdev, IFUP, INFO,
2656                                 "MSI-X Enabled, got %d vectors.\n",
2657                                 qdev->intr_count);
2658                         return;
2659                 } else {
2660                         kfree(qdev->msi_x_entry);
2661                         qdev->msi_x_entry = NULL;
2662                         QPRINTK(qdev, IFUP, WARNING,
2663                                 "MSI-X Enable failed, trying MSI.\n");
2664                         irq_type = MSI_IRQ;
2665                 }
2666         }
2667 msi:
2668         if (irq_type == MSI_IRQ) {
2669                 if (!pci_enable_msi(qdev->pdev)) {
2670                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2671                         QPRINTK(qdev, IFUP, INFO,
2672                                 "Running with MSI interrupts.\n");
2673                         return;
2674                 }
2675         }
2676         irq_type = LEG_IRQ;
2677         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2678 }
2679
2680 /*
2681  * Here we build the intr_context structures based on
2682  * our rx_ring count and intr vector count.
2683  * The intr_context structure is used to hook each vector
2684  * to possibly different handlers.
2685  */
2686 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2687 {
2688         int i = 0;
2689         struct intr_context *intr_context = &qdev->intr_context[0];
2690
2691         ql_enable_msix(qdev);
2692
2693         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2694                 /* Each rx_ring has it's
2695                  * own intr_context since we have separate
2696                  * vectors for each queue.
2697                  * This only true when MSI-X is enabled.
2698                  */
2699                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2700                         qdev->rx_ring[i].irq = i;
2701                         intr_context->intr = i;
2702                         intr_context->qdev = qdev;
2703                         /*
2704                          * We set up each vectors enable/disable/read bits so
2705                          * there's no bit/mask calculations in the critical path.
2706                          */
2707                         intr_context->intr_en_mask =
2708                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2709                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2710                             | i;
2711                         intr_context->intr_dis_mask =
2712                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2713                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2714                             INTR_EN_IHD | i;
2715                         intr_context->intr_read_mask =
2716                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2717                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2718                             i;
2719
2720                         if (i == 0) {
2721                                 /*
2722                                  * Default queue handles bcast/mcast plus
2723                                  * async events.  Needs buffers.
2724                                  */
2725                                 intr_context->handler = qlge_isr;
2726                                 sprintf(intr_context->name, "%s-default-queue",
2727                                         qdev->ndev->name);
2728                         } else if (i < qdev->rss_ring_first_cq_id) {
2729                                 /*
2730                                  * Outbound queue is for outbound completions only.
2731                                  */
2732                                 intr_context->handler = qlge_msix_tx_isr;
2733                                 sprintf(intr_context->name, "%s-tx-%d",
2734                                         qdev->ndev->name, i);
2735                         } else {
2736                                 /*
2737                                  * Inbound queues handle unicast frames only.
2738                                  */
2739                                 intr_context->handler = qlge_msix_rx_isr;
2740                                 sprintf(intr_context->name, "%s-rx-%d",
2741                                         qdev->ndev->name, i);
2742                         }
2743                 }
2744         } else {
2745                 /*
2746                  * All rx_rings use the same intr_context since
2747                  * there is only one vector.
2748                  */
2749                 intr_context->intr = 0;
2750                 intr_context->qdev = qdev;
2751                 /*
2752                  * We set up each vectors enable/disable/read bits so
2753                  * there's no bit/mask calculations in the critical path.
2754                  */
2755                 intr_context->intr_en_mask =
2756                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2757                 intr_context->intr_dis_mask =
2758                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2759                     INTR_EN_TYPE_DISABLE;
2760                 intr_context->intr_read_mask =
2761                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2762                 /*
2763                  * Single interrupt means one handler for all rings.
2764                  */
2765                 intr_context->handler = qlge_isr;
2766                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2767                 for (i = 0; i < qdev->rx_ring_count; i++)
2768                         qdev->rx_ring[i].irq = 0;
2769         }
2770 }
2771
2772 static void ql_free_irq(struct ql_adapter *qdev)
2773 {
2774         int i;
2775         struct intr_context *intr_context = &qdev->intr_context[0];
2776
2777         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2778                 if (intr_context->hooked) {
2779                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2780                                 free_irq(qdev->msi_x_entry[i].vector,
2781                                          &qdev->rx_ring[i]);
2782                                 QPRINTK(qdev, IFDOWN, ERR,
2783                                         "freeing msix interrupt %d.\n", i);
2784                         } else {
2785                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2786                                 QPRINTK(qdev, IFDOWN, ERR,
2787                                         "freeing msi interrupt %d.\n", i);
2788                         }
2789                 }
2790         }
2791         ql_disable_msix(qdev);
2792 }
2793
2794 static int ql_request_irq(struct ql_adapter *qdev)
2795 {
2796         int i;
2797         int status = 0;
2798         struct pci_dev *pdev = qdev->pdev;
2799         struct intr_context *intr_context = &qdev->intr_context[0];
2800
2801         ql_resolve_queues_to_irqs(qdev);
2802
2803         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2804                 atomic_set(&intr_context->irq_cnt, 0);
2805                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2806                         status = request_irq(qdev->msi_x_entry[i].vector,
2807                                              intr_context->handler,
2808                                              0,
2809                                              intr_context->name,
2810                                              &qdev->rx_ring[i]);
2811                         if (status) {
2812                                 QPRINTK(qdev, IFUP, ERR,
2813                                         "Failed request for MSIX interrupt %d.\n",
2814                                         i);
2815                                 goto err_irq;
2816                         } else {
2817                                 QPRINTK(qdev, IFUP, INFO,
2818                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2819                                         i,
2820                                         qdev->rx_ring[i].type ==
2821                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2822                                         qdev->rx_ring[i].type ==
2823                                         TX_Q ? "TX_Q" : "",
2824                                         qdev->rx_ring[i].type ==
2825                                         RX_Q ? "RX_Q" : "", intr_context->name);
2826                         }
2827                 } else {
2828                         QPRINTK(qdev, IFUP, DEBUG,
2829                                 "trying msi or legacy interrupts.\n");
2830                         QPRINTK(qdev, IFUP, DEBUG,
2831                                 "%s: irq = %d.\n", __func__, pdev->irq);
2832                         QPRINTK(qdev, IFUP, DEBUG,
2833                                 "%s: context->name = %s.\n", __func__,
2834                                intr_context->name);
2835                         QPRINTK(qdev, IFUP, DEBUG,
2836                                 "%s: dev_id = 0x%p.\n", __func__,
2837                                &qdev->rx_ring[0]);
2838                         status =
2839                             request_irq(pdev->irq, qlge_isr,
2840                                         test_bit(QL_MSI_ENABLED,
2841                                                  &qdev->
2842                                                  flags) ? 0 : IRQF_SHARED,
2843                                         intr_context->name, &qdev->rx_ring[0]);
2844                         if (status)
2845                                 goto err_irq;
2846
2847                         QPRINTK(qdev, IFUP, ERR,
2848                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2849                                 i,
2850                                 qdev->rx_ring[0].type ==
2851                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2852                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2853                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2854                                 intr_context->name);
2855                 }
2856                 intr_context->hooked = 1;
2857         }
2858         return status;
2859 err_irq:
2860         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2861         ql_free_irq(qdev);
2862         return status;
2863 }
2864
2865 static int ql_start_rss(struct ql_adapter *qdev)
2866 {
2867         struct ricb *ricb = &qdev->ricb;
2868         int status = 0;
2869         int i;
2870         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2871
2872         memset((void *)ricb, 0, sizeof(ricb));
2873
2874         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2875         ricb->flags =
2876             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2877              RSS_RT6);
2878         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2879
2880         /*
2881          * Fill out the Indirection Table.
2882          */
2883         for (i = 0; i < 256; i++)
2884                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2885
2886         /*
2887          * Random values for the IPv6 and IPv4 Hash Keys.
2888          */
2889         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2890         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2891
2892         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2893
2894         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2895         if (status) {
2896                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2897                 return status;
2898         }
2899         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2900         return status;
2901 }
2902
2903 /* Initialize the frame-to-queue routing. */
2904 static int ql_route_initialize(struct ql_adapter *qdev)
2905 {
2906         int status = 0;
2907         int i;
2908
2909         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2910         if (status)
2911                 return status;
2912
2913         /* Clear all the entries in the routing table. */
2914         for (i = 0; i < 16; i++) {
2915                 status = ql_set_routing_reg(qdev, i, 0, 0);
2916                 if (status) {
2917                         QPRINTK(qdev, IFUP, ERR,
2918                                 "Failed to init routing register for CAM packets.\n");
2919                         goto exit;
2920                 }
2921         }
2922
2923         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2924         if (status) {
2925                 QPRINTK(qdev, IFUP, ERR,
2926                         "Failed to init routing register for error packets.\n");
2927                 goto exit;
2928         }
2929         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2930         if (status) {
2931                 QPRINTK(qdev, IFUP, ERR,
2932                         "Failed to init routing register for broadcast packets.\n");
2933                 goto exit;
2934         }
2935         /* If we have more than one inbound queue, then turn on RSS in the
2936          * routing block.
2937          */
2938         if (qdev->rss_ring_count > 1) {
2939                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2940                                         RT_IDX_RSS_MATCH, 1);
2941                 if (status) {
2942                         QPRINTK(qdev, IFUP, ERR,
2943                                 "Failed to init routing register for MATCH RSS packets.\n");
2944                         goto exit;
2945                 }
2946         }
2947
2948         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2949                                     RT_IDX_CAM_HIT, 1);
2950         if (status)
2951                 QPRINTK(qdev, IFUP, ERR,
2952                         "Failed to init routing register for CAM packets.\n");
2953 exit:
2954         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
2955         return status;
2956 }
2957
2958 static int ql_cam_route_initialize(struct ql_adapter *qdev)
2959 {
2960         int status;
2961
2962         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
2963         if (status)
2964                 return status;
2965         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
2966                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
2967         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
2968         if (status) {
2969                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
2970                 return status;
2971         }
2972
2973         status = ql_route_initialize(qdev);
2974         if (status)
2975                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
2976
2977         return status;
2978 }
2979
2980 static int ql_adapter_initialize(struct ql_adapter *qdev)
2981 {
2982         u32 value, mask;
2983         int i;
2984         int status = 0;
2985
2986         /*
2987          * Set up the System register to halt on errors.
2988          */
2989         value = SYS_EFE | SYS_FAE;
2990         mask = value << 16;
2991         ql_write32(qdev, SYS, mask | value);
2992
2993         /* Set the default queue. */
2994         value = NIC_RCV_CFG_DFQ;
2995         mask = NIC_RCV_CFG_DFQ_MASK;
2996         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2997
2998         /* Set the MPI interrupt to enabled. */
2999         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3000
3001         /* Enable the function, set pagesize, enable error checking. */
3002         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3003             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3004
3005         /* Set/clear header splitting. */
3006         mask = FSC_VM_PAGESIZE_MASK |
3007             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3008         ql_write32(qdev, FSC, mask | value);
3009
3010         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3011                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3012
3013         /* Start up the rx queues. */
3014         for (i = 0; i < qdev->rx_ring_count; i++) {
3015                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3016                 if (status) {
3017                         QPRINTK(qdev, IFUP, ERR,
3018                                 "Failed to start rx ring[%d].\n", i);
3019                         return status;
3020                 }
3021         }
3022
3023         /* If there is more than one inbound completion queue
3024          * then download a RICB to configure RSS.
3025          */
3026         if (qdev->rss_ring_count > 1) {
3027                 status = ql_start_rss(qdev);
3028                 if (status) {
3029                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3030                         return status;
3031                 }
3032         }
3033
3034         /* Start up the tx queues. */
3035         for (i = 0; i < qdev->tx_ring_count; i++) {
3036                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3037                 if (status) {
3038                         QPRINTK(qdev, IFUP, ERR,
3039                                 "Failed to start tx ring[%d].\n", i);
3040                         return status;
3041                 }
3042         }
3043
3044         status = ql_port_initialize(qdev);
3045         if (status) {
3046                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3047                 return status;
3048         }
3049
3050         /* Set up the MAC address and frame routing filter. */
3051         status = ql_cam_route_initialize(qdev);
3052         if (status) {
3053                 QPRINTK(qdev, IFUP, ERR,
3054                                 "Failed to init CAM/Routing tables.\n");
3055                 return status;
3056         }
3057
3058         /* Start NAPI for the RSS queues. */
3059         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3060                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3061                         i);
3062                 napi_enable(&qdev->rx_ring[i].napi);
3063         }
3064
3065         return status;
3066 }
3067
3068 /* Issue soft reset to chip. */
3069 static int ql_adapter_reset(struct ql_adapter *qdev)
3070 {
3071         u32 value;
3072         int max_wait_time;
3073         int status = 0;
3074         int resetCnt = 0;
3075
3076 #define MAX_RESET_CNT   1
3077 issueReset:
3078         resetCnt++;
3079         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3080         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3081         /* Wait for reset to complete. */
3082         max_wait_time = 3;
3083         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3084                 max_wait_time);
3085         do {
3086                 value = ql_read32(qdev, RST_FO);
3087                 if ((value & RST_FO_FR) == 0)
3088                         break;
3089
3090                 ssleep(1);
3091         } while ((--max_wait_time));
3092         if (value & RST_FO_FR) {
3093                 QPRINTK(qdev, IFDOWN, ERR,
3094                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3095                 if (resetCnt < MAX_RESET_CNT)
3096                         goto issueReset;
3097         }
3098         if (max_wait_time == 0) {
3099                 status = -ETIMEDOUT;
3100                 QPRINTK(qdev, IFDOWN, ERR,
3101                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3102         }
3103
3104         return status;
3105 }
3106
3107 static void ql_display_dev_info(struct net_device *ndev)
3108 {
3109         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3110
3111         QPRINTK(qdev, PROBE, INFO,
3112                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3113                 "XG Roll = %d, XG Rev = %d.\n",
3114                 qdev->func,
3115                 qdev->chip_rev_id & 0x0000000f,
3116                 qdev->chip_rev_id >> 4 & 0x0000000f,
3117                 qdev->chip_rev_id >> 8 & 0x0000000f,
3118                 qdev->chip_rev_id >> 12 & 0x0000000f);
3119         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3120 }
3121
3122 static int ql_adapter_down(struct ql_adapter *qdev)
3123 {
3124         struct net_device *ndev = qdev->ndev;
3125         int i, status = 0;
3126         struct rx_ring *rx_ring;
3127
3128         netif_stop_queue(ndev);
3129         netif_carrier_off(ndev);
3130
3131         /* Don't kill the reset worker thread if we
3132          * are in the process of recovery.
3133          */
3134         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3135                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3136         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3137         cancel_delayed_work_sync(&qdev->mpi_work);
3138
3139         /* The default queue at index 0 is always processed in
3140          * a workqueue.
3141          */
3142         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3143
3144         /* The rest of the rx_rings are processed in
3145          * a workqueue only if it's a single interrupt
3146          * environment (MSI/Legacy).
3147          */
3148         for (i = 1; i < qdev->rx_ring_count; i++) {
3149                 rx_ring = &qdev->rx_ring[i];
3150                 /* Only the RSS rings use NAPI on multi irq
3151                  * environment.  Outbound completion processing
3152                  * is done in interrupt context.
3153                  */
3154                 if (i >= qdev->rss_ring_first_cq_id) {
3155                         napi_disable(&rx_ring->napi);
3156                 } else {
3157                         cancel_delayed_work_sync(&rx_ring->rx_work);
3158                 }
3159         }
3160
3161         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3162
3163         ql_disable_interrupts(qdev);
3164
3165         ql_tx_ring_clean(qdev);
3166
3167         spin_lock(&qdev->hw_lock);
3168         status = ql_adapter_reset(qdev);
3169         if (status)
3170                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3171                         qdev->func);
3172         spin_unlock(&qdev->hw_lock);
3173         return status;
3174 }
3175
3176 static int ql_adapter_up(struct ql_adapter *qdev)
3177 {
3178         int err = 0;
3179
3180         spin_lock(&qdev->hw_lock);
3181         err = ql_adapter_initialize(qdev);
3182         if (err) {
3183                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3184                 spin_unlock(&qdev->hw_lock);
3185                 goto err_init;
3186         }
3187         spin_unlock(&qdev->hw_lock);
3188         set_bit(QL_ADAPTER_UP, &qdev->flags);
3189         ql_enable_interrupts(qdev);
3190         ql_enable_all_completion_interrupts(qdev);
3191         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3192                 netif_carrier_on(qdev->ndev);
3193                 netif_start_queue(qdev->ndev);
3194         }
3195
3196         return 0;
3197 err_init:
3198         ql_adapter_reset(qdev);
3199         return err;
3200 }
3201
3202 static int ql_cycle_adapter(struct ql_adapter *qdev)
3203 {
3204         int status;
3205
3206         status = ql_adapter_down(qdev);
3207         if (status)
3208                 goto error;
3209
3210         status = ql_adapter_up(qdev);
3211         if (status)
3212                 goto error;
3213
3214         return status;
3215 error:
3216         QPRINTK(qdev, IFUP, ALERT,
3217                 "Driver up/down cycle failed, closing device\n");
3218         rtnl_lock();
3219         dev_close(qdev->ndev);
3220         rtnl_unlock();
3221         return status;
3222 }
3223
3224 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3225 {
3226         ql_free_mem_resources(qdev);
3227         ql_free_irq(qdev);
3228 }
3229
3230 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3231 {
3232         int status = 0;
3233
3234         if (ql_alloc_mem_resources(qdev)) {
3235                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3236                 return -ENOMEM;
3237         }
3238         status = ql_request_irq(qdev);
3239         if (status)
3240                 goto err_irq;
3241         return status;
3242 err_irq:
3243         ql_free_mem_resources(qdev);
3244         return status;
3245 }
3246
3247 static int qlge_close(struct net_device *ndev)
3248 {
3249         struct ql_adapter *qdev = netdev_priv(ndev);
3250
3251         /*
3252          * Wait for device to recover from a reset.
3253          * (Rarely happens, but possible.)
3254          */
3255         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3256                 msleep(1);
3257         ql_adapter_down(qdev);
3258         ql_release_adapter_resources(qdev);
3259         return 0;
3260 }
3261
3262 static int ql_configure_rings(struct ql_adapter *qdev)
3263 {
3264         int i;
3265         struct rx_ring *rx_ring;
3266         struct tx_ring *tx_ring;
3267         int cpu_cnt = num_online_cpus();
3268
3269         /*
3270          * For each processor present we allocate one
3271          * rx_ring for outbound completions, and one
3272          * rx_ring for inbound completions.  Plus there is
3273          * always the one default queue.  For the CPU
3274          * counts we end up with the following rx_rings:
3275          * rx_ring count =
3276          *  one default queue +
3277          *  (CPU count * outbound completion rx_ring) +
3278          *  (CPU count * inbound (RSS) completion rx_ring)
3279          * To keep it simple we limit the total number of
3280          * queues to < 32, so we truncate CPU to 8.
3281          * This limitation can be removed when requested.
3282          */
3283
3284         if (cpu_cnt > MAX_CPUS)
3285                 cpu_cnt = MAX_CPUS;
3286
3287         /*
3288          * rx_ring[0] is always the default queue.
3289          */
3290         /* Allocate outbound completion ring for each CPU. */
3291         qdev->tx_ring_count = cpu_cnt;
3292         /* Allocate inbound completion (RSS) ring for each CPU. */
3293         qdev->rss_ring_count = cpu_cnt;
3294         /* cq_id for the first inbound ring handler. */
3295         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3296         /*
3297          * qdev->rx_ring_count:
3298          * Total number of rx_rings.  This includes the one
3299          * default queue, a number of outbound completion
3300          * handler rx_rings, and the number of inbound
3301          * completion handler rx_rings.
3302          */
3303         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3304
3305         for (i = 0; i < qdev->tx_ring_count; i++) {
3306                 tx_ring = &qdev->tx_ring[i];
3307                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3308                 tx_ring->qdev = qdev;
3309                 tx_ring->wq_id = i;
3310                 tx_ring->wq_len = qdev->tx_ring_size;
3311                 tx_ring->wq_size =
3312                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3313
3314                 /*
3315                  * The completion queue ID for the tx rings start
3316                  * immediately after the default Q ID, which is zero.
3317                  */
3318                 tx_ring->cq_id = i + 1;
3319         }
3320
3321         for (i = 0; i < qdev->rx_ring_count; i++) {
3322                 rx_ring = &qdev->rx_ring[i];
3323                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3324                 rx_ring->qdev = qdev;
3325                 rx_ring->cq_id = i;
3326                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3327                 if (i == 0) {   /* Default queue at index 0. */
3328                         /*
3329                          * Default queue handles bcast/mcast plus
3330                          * async events.  Needs buffers.
3331                          */
3332                         rx_ring->cq_len = qdev->rx_ring_size;
3333                         rx_ring->cq_size =
3334                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3335                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3336                         rx_ring->lbq_size =
3337                             rx_ring->lbq_len * sizeof(__le64);
3338                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3339                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3340                         rx_ring->sbq_size =
3341                             rx_ring->sbq_len * sizeof(__le64);
3342                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3343                         rx_ring->type = DEFAULT_Q;
3344                 } else if (i < qdev->rss_ring_first_cq_id) {
3345                         /*
3346                          * Outbound queue handles outbound completions only.
3347                          */
3348                         /* outbound cq is same size as tx_ring it services. */
3349                         rx_ring->cq_len = qdev->tx_ring_size;
3350                         rx_ring->cq_size =
3351                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3352                         rx_ring->lbq_len = 0;
3353                         rx_ring->lbq_size = 0;
3354                         rx_ring->lbq_buf_size = 0;
3355                         rx_ring->sbq_len = 0;
3356                         rx_ring->sbq_size = 0;
3357                         rx_ring->sbq_buf_size = 0;
3358                         rx_ring->type = TX_Q;
3359                 } else {        /* Inbound completions (RSS) queues */
3360                         /*
3361                          * Inbound queues handle unicast frames only.
3362                          */
3363                         rx_ring->cq_len = qdev->rx_ring_size;
3364                         rx_ring->cq_size =
3365                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3366                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3367                         rx_ring->lbq_size =
3368                             rx_ring->lbq_len * sizeof(__le64);
3369                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3370                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3371                         rx_ring->sbq_size =
3372                             rx_ring->sbq_len * sizeof(__le64);
3373                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3374                         rx_ring->type = RX_Q;
3375                 }
3376         }
3377         return 0;
3378 }
3379
3380 static int qlge_open(struct net_device *ndev)
3381 {
3382         int err = 0;
3383         struct ql_adapter *qdev = netdev_priv(ndev);
3384
3385         err = ql_configure_rings(qdev);
3386         if (err)
3387                 return err;
3388
3389         err = ql_get_adapter_resources(qdev);
3390         if (err)
3391                 goto error_up;
3392
3393         err = ql_adapter_up(qdev);
3394         if (err)
3395                 goto error_up;
3396
3397         return err;
3398
3399 error_up:
3400         ql_release_adapter_resources(qdev);
3401         return err;
3402 }
3403
3404 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3405 {
3406         struct ql_adapter *qdev = netdev_priv(ndev);
3407
3408         if (ndev->mtu == 1500 && new_mtu == 9000) {
3409                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3410         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3411                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3412         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3413                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3414                 return 0;
3415         } else
3416                 return -EINVAL;
3417         ndev->mtu = new_mtu;
3418         return 0;
3419 }
3420
3421 static struct net_device_stats *qlge_get_stats(struct net_device
3422                                                *ndev)
3423 {
3424         struct ql_adapter *qdev = netdev_priv(ndev);
3425         return &qdev->stats;
3426 }
3427
3428 static void qlge_set_multicast_list(struct net_device *ndev)
3429 {
3430         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3431         struct dev_mc_list *mc_ptr;
3432         int i, status;
3433
3434         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3435         if (status)
3436                 return;
3437         spin_lock(&qdev->hw_lock);
3438         /*
3439          * Set or clear promiscuous mode if a
3440          * transition is taking place.
3441          */
3442         if (ndev->flags & IFF_PROMISC) {
3443                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3444                         if (ql_set_routing_reg
3445                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3446                                 QPRINTK(qdev, HW, ERR,
3447                                         "Failed to set promiscous mode.\n");
3448                         } else {
3449                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3450                         }
3451                 }
3452         } else {
3453                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3454                         if (ql_set_routing_reg
3455                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3456                                 QPRINTK(qdev, HW, ERR,
3457                                         "Failed to clear promiscous mode.\n");
3458                         } else {
3459                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3460                         }
3461                 }
3462         }
3463
3464         /*
3465          * Set or clear all multicast mode if a
3466          * transition is taking place.
3467          */
3468         if ((ndev->flags & IFF_ALLMULTI) ||
3469             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3470                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3471                         if (ql_set_routing_reg
3472                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3473                                 QPRINTK(qdev, HW, ERR,
3474                                         "Failed to set all-multi mode.\n");
3475                         } else {
3476                                 set_bit(QL_ALLMULTI, &qdev->flags);
3477                         }
3478                 }
3479         } else {
3480                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3481                         if (ql_set_routing_reg
3482                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3483                                 QPRINTK(qdev, HW, ERR,
3484                                         "Failed to clear all-multi mode.\n");
3485                         } else {
3486                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3487                         }
3488                 }
3489         }
3490
3491         if (ndev->mc_count) {
3492                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3493                 if (status)
3494                         goto exit;
3495                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3496                      i++, mc_ptr = mc_ptr->next)
3497                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3498                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3499                                 QPRINTK(qdev, HW, ERR,
3500                                         "Failed to loadmulticast address.\n");
3501                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3502                                 goto exit;
3503                         }
3504                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3505                 if (ql_set_routing_reg
3506                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3507                         QPRINTK(qdev, HW, ERR,
3508                                 "Failed to set multicast match mode.\n");
3509                 } else {
3510                         set_bit(QL_ALLMULTI, &qdev->flags);
3511                 }
3512         }
3513 exit:
3514         spin_unlock(&qdev->hw_lock);
3515         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3516 }
3517
3518 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3519 {
3520         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3521         struct sockaddr *addr = p;
3522         int status;
3523
3524         if (netif_running(ndev))
3525                 return -EBUSY;
3526
3527         if (!is_valid_ether_addr(addr->sa_data))
3528                 return -EADDRNOTAVAIL;
3529         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3530
3531         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3532         if (status)
3533                 return status;
3534         spin_lock(&qdev->hw_lock);
3535         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3536                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3537         spin_unlock(&qdev->hw_lock);
3538         if (status)
3539                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3540         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3541         return status;
3542 }
3543
3544 static void qlge_tx_timeout(struct net_device *ndev)
3545 {
3546         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3547         ql_queue_asic_error(qdev);
3548 }
3549
3550 static void ql_asic_reset_work(struct work_struct *work)
3551 {
3552         struct ql_adapter *qdev =
3553             container_of(work, struct ql_adapter, asic_reset_work.work);
3554         ql_cycle_adapter(qdev);
3555 }
3556
3557 static void ql_get_board_info(struct ql_adapter *qdev)
3558 {
3559         qdev->func =
3560             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3561         if (qdev->func) {
3562                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3563                 qdev->port_link_up = STS_PL1;
3564                 qdev->port_init = STS_PI1;
3565                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3566                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3567         } else {
3568                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3569                 qdev->port_link_up = STS_PL0;
3570                 qdev->port_init = STS_PI0;
3571                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3572                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3573         }
3574         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3575 }
3576
3577 static void ql_release_all(struct pci_dev *pdev)
3578 {
3579         struct net_device *ndev = pci_get_drvdata(pdev);
3580         struct ql_adapter *qdev = netdev_priv(ndev);
3581
3582         if (qdev->workqueue) {
3583                 destroy_workqueue(qdev->workqueue);
3584                 qdev->workqueue = NULL;
3585         }
3586         if (qdev->q_workqueue) {
3587                 destroy_workqueue(qdev->q_workqueue);
3588                 qdev->q_workqueue = NULL;
3589         }
3590         if (qdev->reg_base)
3591                 iounmap(qdev->reg_base);
3592         if (qdev->doorbell_area)
3593                 iounmap(qdev->doorbell_area);
3594         pci_release_regions(pdev);
3595         pci_set_drvdata(pdev, NULL);
3596 }
3597
3598 static int __devinit ql_init_device(struct pci_dev *pdev,
3599                                     struct net_device *ndev, int cards_found)
3600 {
3601         struct ql_adapter *qdev = netdev_priv(ndev);
3602         int pos, err = 0;
3603         u16 val16;
3604
3605         memset((void *)qdev, 0, sizeof(qdev));
3606         err = pci_enable_device(pdev);
3607         if (err) {
3608                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3609                 return err;
3610         }
3611
3612         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3613         if (pos <= 0) {
3614                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3615                         "aborting.\n");
3616                 goto err_out;
3617         } else {
3618                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3619                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3620                 val16 |= (PCI_EXP_DEVCTL_CERE |
3621                           PCI_EXP_DEVCTL_NFERE |
3622                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3623                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3624         }
3625
3626         err = pci_request_regions(pdev, DRV_NAME);
3627         if (err) {
3628                 dev_err(&pdev->dev, "PCI region request failed.\n");
3629                 goto err_out;
3630         }
3631
3632         pci_set_master(pdev);
3633         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3634                 set_bit(QL_DMA64, &qdev->flags);
3635                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3636         } else {
3637                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3638                 if (!err)
3639                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3640         }
3641
3642         if (err) {
3643                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3644                 goto err_out;
3645         }
3646
3647         pci_set_drvdata(pdev, ndev);
3648         qdev->reg_base =
3649             ioremap_nocache(pci_resource_start(pdev, 1),
3650                             pci_resource_len(pdev, 1));
3651         if (!qdev->reg_base) {
3652                 dev_err(&pdev->dev, "Register mapping failed.\n");
3653                 err = -ENOMEM;
3654                 goto err_out;
3655         }
3656
3657         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3658         qdev->doorbell_area =
3659             ioremap_nocache(pci_resource_start(pdev, 3),
3660                             pci_resource_len(pdev, 3));
3661         if (!qdev->doorbell_area) {
3662                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3663                 err = -ENOMEM;
3664                 goto err_out;
3665         }
3666
3667         ql_get_board_info(qdev);
3668         qdev->ndev = ndev;
3669         qdev->pdev = pdev;
3670         qdev->msg_enable = netif_msg_init(debug, default_msg);
3671         spin_lock_init(&qdev->hw_lock);
3672         spin_lock_init(&qdev->stats_lock);
3673
3674         /* make sure the EEPROM is good */
3675         err = ql_get_flash_params(qdev);
3676         if (err) {
3677                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3678                 goto err_out;
3679         }
3680
3681         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3682                 goto err_out;
3683
3684         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3685         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3686
3687         /* Set up the default ring sizes. */
3688         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3689         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3690
3691         /* Set up the coalescing parameters. */
3692         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3693         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3694         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3695         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3696
3697         /*
3698          * Set up the operating parameters.
3699          */
3700         qdev->rx_csum = 1;
3701
3702         qdev->q_workqueue = create_workqueue(ndev->name);
3703         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3704         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3705         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3706         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3707
3708         if (!cards_found) {
3709                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3710                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3711                          DRV_NAME, DRV_VERSION);
3712         }
3713         return 0;
3714 err_out:
3715         ql_release_all(pdev);
3716         pci_disable_device(pdev);
3717         return err;
3718 }
3719
3720
3721 static const struct net_device_ops qlge_netdev_ops = {
3722         .ndo_open               = qlge_open,
3723         .ndo_stop               = qlge_close,
3724         .ndo_start_xmit         = qlge_send,
3725         .ndo_change_mtu         = qlge_change_mtu,
3726         .ndo_get_stats          = qlge_get_stats,
3727         .ndo_set_multicast_list = qlge_set_multicast_list,
3728         .ndo_set_mac_address    = qlge_set_mac_address,
3729         .ndo_validate_addr      = eth_validate_addr,
3730         .ndo_tx_timeout         = qlge_tx_timeout,
3731         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3732         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3733         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3734 };
3735
3736 static int __devinit qlge_probe(struct pci_dev *pdev,
3737                                 const struct pci_device_id *pci_entry)
3738 {
3739         struct net_device *ndev = NULL;
3740         struct ql_adapter *qdev = NULL;
3741         static int cards_found = 0;
3742         int err = 0;
3743
3744         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3745         if (!ndev)
3746                 return -ENOMEM;
3747
3748         err = ql_init_device(pdev, ndev, cards_found);
3749         if (err < 0) {
3750                 free_netdev(ndev);
3751                 return err;
3752         }
3753
3754         qdev = netdev_priv(ndev);
3755         SET_NETDEV_DEV(ndev, &pdev->dev);
3756         ndev->features = (0
3757                           | NETIF_F_IP_CSUM
3758                           | NETIF_F_SG
3759                           | NETIF_F_TSO
3760                           | NETIF_F_TSO6
3761                           | NETIF_F_TSO_ECN
3762                           | NETIF_F_HW_VLAN_TX
3763                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3764
3765         if (test_bit(QL_DMA64, &qdev->flags))
3766                 ndev->features |= NETIF_F_HIGHDMA;
3767
3768         /*
3769          * Set up net_device structure.
3770          */
3771         ndev->tx_queue_len = qdev->tx_ring_size;
3772         ndev->irq = pdev->irq;
3773
3774         ndev->netdev_ops = &qlge_netdev_ops;
3775         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3776         ndev->watchdog_timeo = 10 * HZ;
3777
3778         err = register_netdev(ndev);
3779         if (err) {
3780                 dev_err(&pdev->dev, "net device registration failed.\n");
3781                 ql_release_all(pdev);
3782                 pci_disable_device(pdev);
3783                 return err;
3784         }
3785         netif_carrier_off(ndev);
3786         netif_stop_queue(ndev);
3787         ql_display_dev_info(ndev);
3788         cards_found++;
3789         return 0;
3790 }
3791
3792 static void __devexit qlge_remove(struct pci_dev *pdev)
3793 {
3794         struct net_device *ndev = pci_get_drvdata(pdev);
3795         unregister_netdev(ndev);
3796         ql_release_all(pdev);
3797         pci_disable_device(pdev);
3798         free_netdev(ndev);
3799 }
3800
3801 /*
3802  * This callback is called by the PCI subsystem whenever
3803  * a PCI bus error is detected.
3804  */
3805 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3806                                                enum pci_channel_state state)
3807 {
3808         struct net_device *ndev = pci_get_drvdata(pdev);
3809         struct ql_adapter *qdev = netdev_priv(ndev);
3810
3811         if (netif_running(ndev))
3812                 ql_adapter_down(qdev);
3813
3814         pci_disable_device(pdev);
3815
3816         /* Request a slot reset. */
3817         return PCI_ERS_RESULT_NEED_RESET;
3818 }
3819
3820 /*
3821  * This callback is called after the PCI buss has been reset.
3822  * Basically, this tries to restart the card from scratch.
3823  * This is a shortened version of the device probe/discovery code,
3824  * it resembles the first-half of the () routine.
3825  */
3826 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3827 {
3828         struct net_device *ndev = pci_get_drvdata(pdev);
3829         struct ql_adapter *qdev = netdev_priv(ndev);
3830
3831         if (pci_enable_device(pdev)) {
3832                 QPRINTK(qdev, IFUP, ERR,
3833                         "Cannot re-enable PCI device after reset.\n");
3834                 return PCI_ERS_RESULT_DISCONNECT;
3835         }
3836
3837         pci_set_master(pdev);
3838
3839         netif_carrier_off(ndev);
3840         netif_stop_queue(ndev);
3841         ql_adapter_reset(qdev);
3842
3843         /* Make sure the EEPROM is good */
3844         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3845
3846         if (!is_valid_ether_addr(ndev->perm_addr)) {
3847                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3848                 return PCI_ERS_RESULT_DISCONNECT;
3849         }
3850
3851         return PCI_ERS_RESULT_RECOVERED;
3852 }
3853
3854 static void qlge_io_resume(struct pci_dev *pdev)
3855 {
3856         struct net_device *ndev = pci_get_drvdata(pdev);
3857         struct ql_adapter *qdev = netdev_priv(ndev);
3858
3859         pci_set_master(pdev);
3860
3861         if (netif_running(ndev)) {
3862                 if (ql_adapter_up(qdev)) {
3863                         QPRINTK(qdev, IFUP, ERR,
3864                                 "Device initialization failed after reset.\n");
3865                         return;
3866                 }
3867         }
3868
3869         netif_device_attach(ndev);
3870 }
3871
3872 static struct pci_error_handlers qlge_err_handler = {
3873         .error_detected = qlge_io_error_detected,
3874         .slot_reset = qlge_io_slot_reset,
3875         .resume = qlge_io_resume,
3876 };
3877
3878 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3879 {
3880         struct net_device *ndev = pci_get_drvdata(pdev);
3881         struct ql_adapter *qdev = netdev_priv(ndev);
3882         int err, i;
3883
3884         netif_device_detach(ndev);
3885
3886         if (netif_running(ndev)) {
3887                 err = ql_adapter_down(qdev);
3888                 if (!err)
3889                         return err;
3890         }
3891
3892         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3893                 netif_napi_del(&qdev->rx_ring[i].napi);
3894
3895         err = pci_save_state(pdev);
3896         if (err)
3897                 return err;
3898
3899         pci_disable_device(pdev);
3900
3901         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3902
3903         return 0;
3904 }
3905
3906 #ifdef CONFIG_PM
3907 static int qlge_resume(struct pci_dev *pdev)
3908 {
3909         struct net_device *ndev = pci_get_drvdata(pdev);
3910         struct ql_adapter *qdev = netdev_priv(ndev);
3911         int err;
3912
3913         pci_set_power_state(pdev, PCI_D0);
3914         pci_restore_state(pdev);
3915         err = pci_enable_device(pdev);
3916         if (err) {
3917                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3918                 return err;
3919         }
3920         pci_set_master(pdev);
3921
3922         pci_enable_wake(pdev, PCI_D3hot, 0);
3923         pci_enable_wake(pdev, PCI_D3cold, 0);
3924
3925         if (netif_running(ndev)) {
3926                 err = ql_adapter_up(qdev);
3927                 if (err)
3928                         return err;
3929         }
3930
3931         netif_device_attach(ndev);
3932
3933         return 0;
3934 }
3935 #endif /* CONFIG_PM */
3936
3937 static void qlge_shutdown(struct pci_dev *pdev)
3938 {
3939         qlge_suspend(pdev, PMSG_SUSPEND);
3940 }
3941
3942 static struct pci_driver qlge_driver = {
3943         .name = DRV_NAME,
3944         .id_table = qlge_pci_tbl,
3945         .probe = qlge_probe,
3946         .remove = __devexit_p(qlge_remove),
3947 #ifdef CONFIG_PM
3948         .suspend = qlge_suspend,
3949         .resume = qlge_resume,
3950 #endif
3951         .shutdown = qlge_shutdown,
3952         .err_handler = &qlge_err_handler
3953 };
3954
3955 static int __init qlge_init_module(void)
3956 {
3957         return pci_register_driver(&qlge_driver);
3958 }
3959
3960 static void __exit qlge_exit(void)
3961 {
3962         pci_unregister_driver(&qlge_driver);
3963 }
3964
3965 module_init(qlge_init_module);
3966 module_exit(qlge_exit);