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   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int seconds = 3;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 ssleep(1);
 135         } while (--seconds);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_wait_cfg(qdev, bit);
 218         if (status) {
 219                 QPRINTK(qdev, IFUP, ERR,
 220                         "Timed out waiting for CFG to come ready.\n");
 221                 goto exit;
 222         }
 223
 224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 225         if (status)
 226                 goto exit;
 227         ql_write32(qdev, ICB_L, (u32) map);
 228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         pci_unmap_single(qdev->pdev, map, size, direction);
 241         return status;
 242 }
 243
 244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 246                         u32 *value)
 247 {
 248         u32 offset = 0;
 249         int status;
 250
 251         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 252         if (status)
 253                 return status;
 254         switch (type) {
 255         case MAC_ADDR_TYPE_MULTI_MAC:
 256         case MAC_ADDR_TYPE_CAM_MAC:
 257                 {
 258                         status =
 259                             ql_wait_reg_rdy(qdev,
 260                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 261                         if (status)
 262                                 goto exit;
 263                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 264                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 265                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 266                         status =
 267                             ql_wait_reg_rdy(qdev,
 268                                 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
 269                         if (status)
 270                                 goto exit;
 271                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 272                         status =
 273                             ql_wait_reg_rdy(qdev,
 274                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 275                         if (status)
 276                                 goto exit;
 277                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 278                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 279                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 280                         status =
 281                             ql_wait_reg_rdy(qdev,
 282                                 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
 283                         if (status)
 284                                 goto exit;
 285                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 286                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 287                                 status =
 288                                     ql_wait_reg_rdy(qdev,
 289                                         MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 290                                 if (status)
 291                                         goto exit;
 292                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 293                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 294                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 295                                 status =
 296                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 297                                                     MAC_ADDR_MR, MAC_ADDR_E);
 298                                 if (status)
 299                                         goto exit;
 300                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 301                         }
 302                         break;
 303                 }
 304         case MAC_ADDR_TYPE_VLAN:
 305         case MAC_ADDR_TYPE_MULTI_FLTR:
 306         default:
 307                 QPRINTK(qdev, IFUP, CRIT,
 308                         "Address type %d not yet supported.\n", type);
 309                 status = -EPERM;
 310         }
 311 exit:
 312         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 313         return status;
 314 }
 315
 316 /* Set up a MAC, multicast or VLAN address for the
 317  * inbound frame matching.
 318  */
 319 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 320                                u16 index)
 321 {
 322         u32 offset = 0;
 323         int status = 0;
 324
 325         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 326         if (status)
 327                 return status;
 328         switch (type) {
 329         case MAC_ADDR_TYPE_MULTI_MAC:
 330         case MAC_ADDR_TYPE_CAM_MAC:
 331                 {
 332                         u32 cam_output;
 333                         u32 upper = (addr[0] << 8) | addr[1];
 334                         u32 lower =
 335                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 336                             (addr[5]);
 337
 338                         QPRINTK(qdev, IFUP, INFO,
 339                                 "Adding %s address %pM"
 340                                 " at index %d in the CAM.\n",
 341                                 ((type ==
 342                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 343                                  "UNICAST"), addr, index);
 344
 345                         status =
 346                             ql_wait_reg_rdy(qdev,
 347                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 348                         if (status)
 349                                 goto exit;
 350                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 351                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 352                                    type);       /* type */
 353                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 354                         status =
 355                             ql_wait_reg_rdy(qdev,
 356                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 357                         if (status)
 358                                 goto exit;
 359                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 360                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 361                                    type);       /* type */
 362                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 363                         status =
 364                             ql_wait_reg_rdy(qdev,
 365                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 366                         if (status)
 367                                 goto exit;
 368                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 369                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 370                                    type);       /* type */
 371                         /* This field should also include the queue id
 372                            and possibly the function id.  Right now we hardcode
 373                            the route field to NIC core.
 374                          */
 375                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 376                                 cam_output = (CAM_OUT_ROUTE_NIC |
 377                                               (qdev->
 378                                                func << CAM_OUT_FUNC_SHIFT) |
 379                                               (qdev->
 380                                                rss_ring_first_cq_id <<
 381                                                CAM_OUT_CQ_ID_SHIFT));
 382                                 if (qdev->vlgrp)
 383                                         cam_output |= CAM_OUT_RV;
 384                                 /* route to NIC core */
 385                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 386                         }
 387                         break;
 388                 }
 389         case MAC_ADDR_TYPE_VLAN:
 390                 {
 391                         u32 enable_bit = *((u32 *) &addr[0]);
 392                         /* For VLAN, the addr actually holds a bit that
 393                          * either enables or disables the vlan id we are
 394                          * addressing. It's either MAC_ADDR_E on or off.
 395                          * That's bit-27 we're talking about.
 396                          */
 397                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 398                                 (enable_bit ? "Adding" : "Removing"),
 399                                 index, (enable_bit ? "to" : "from"));
 400
 401                         status =
 402                             ql_wait_reg_rdy(qdev,
 403                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 404                         if (status)
 405                                 goto exit;
 406                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 407                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 408                                    type |       /* type */
 409                                    enable_bit); /* enable/disable */
 410                         break;
 411                 }
 412         case MAC_ADDR_TYPE_MULTI_FLTR:
 413         default:
 414                 QPRINTK(qdev, IFUP, CRIT,
 415                         "Address type %d not yet supported.\n", type);
 416                 status = -EPERM;
 417         }
 418 exit:
 419         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 420         return status;
 421 }
 422
 423 /* Get a specific frame routing value from the CAM.
 424  * Used for debug and reg dump.
 425  */
 426 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 427 {
 428         int status = 0;
 429
 430         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 431         if (status)
 432                 goto exit;
 433
 434         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
 435         if (status)
 436                 goto exit;
 437
 438         ql_write32(qdev, RT_IDX,
 439                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 440         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
 441         if (status)
 442                 goto exit;
 443         *value = ql_read32(qdev, RT_DATA);
 444 exit:
 445         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 446         return status;
 447 }
 448
 449 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 450  * to route different frame types to various inbound queues.  We send broadcast/
 451  * multicast/error frames to the default queue for slow handling,
 452  * and CAM hit/RSS frames to the fast handling queues.
 453  */
 454 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 455                               int enable)
 456 {
 457         int status;
 458         u32 value = 0;
 459
 460         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 461         if (status)
 462                 return status;
 463
 464         QPRINTK(qdev, IFUP, DEBUG,
 465                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 466                 (enable ? "Adding" : "Removing"),
 467                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 468                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 469                 ((index ==
 470                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 471                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 472                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 474                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 475                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 476                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 477                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 478                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 479                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 480                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 481                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 482                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 483                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 484                 (enable ? "to" : "from"));
 485
 486         switch (mask) {
 487         case RT_IDX_CAM_HIT:
 488                 {
 489                         value = RT_IDX_DST_CAM_Q |      /* dest */
 490                             RT_IDX_TYPE_NICQ |  /* type */
 491                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 492                         break;
 493                 }
 494         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 495                 {
 496                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 497                             RT_IDX_TYPE_NICQ |  /* type */
 498                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 499                         break;
 500                 }
 501         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 502                 {
 503                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 504                             RT_IDX_TYPE_NICQ |  /* type */
 505                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 506                         break;
 507                 }
 508         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 509                 {
 510                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 511                             RT_IDX_TYPE_NICQ |  /* type */
 512                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 513                         break;
 514                 }
 515         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 516                 {
 517                         value = RT_IDX_DST_CAM_Q |      /* dest */
 518                             RT_IDX_TYPE_NICQ |  /* type */
 519                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 520                         break;
 521                 }
 522         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 523                 {
 524                         value = RT_IDX_DST_CAM_Q |      /* dest */
 525                             RT_IDX_TYPE_NICQ |  /* type */
 526                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 527                         break;
 528                 }
 529         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 530                 {
 531                         value = RT_IDX_DST_RSS |        /* dest */
 532                             RT_IDX_TYPE_NICQ |  /* type */
 533                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 534                         break;
 535                 }
 536         case 0:         /* Clear the E-bit on an entry. */
 537                 {
 538                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 539                             RT_IDX_TYPE_NICQ |  /* type */
 540                             (index << RT_IDX_IDX_SHIFT);/* index */
 541                         break;
 542                 }
 543         default:
 544                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 545                         mask);
 546                 status = -EPERM;
 547                 goto exit;
 548         }
 549
 550         if (value) {
 551                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 552                 if (status)
 553                         goto exit;
 554                 value |= (enable ? RT_IDX_E : 0);
 555                 ql_write32(qdev, RT_IDX, value);
 556                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 557         }
 558 exit:
 559         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 560         return status;
 561 }
 562
 563 static void ql_enable_interrupts(struct ql_adapter *qdev)
 564 {
 565         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 566 }
 567
 568 static void ql_disable_interrupts(struct ql_adapter *qdev)
 569 {
 570         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 571 }
 572
 573 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 574  * Otherwise, we may have multiple outstanding workers and don't want to
 575  * enable until the last one finishes. In this case, the irq_cnt gets
 576  * incremented everytime we queue a worker and decremented everytime
 577  * a worker finishes.  Once it hits zero we enable the interrupt.
 578  */
 579 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 580 {
 581         u32 var = 0;
 582         unsigned long hw_flags = 0;
 583         struct intr_context *ctx = qdev->intr_context + intr;
 584
 585         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 586                 /* Always enable if we're MSIX multi interrupts and
 587                  * it's not the default (zeroeth) interrupt.
 588                  */
 589                 ql_write32(qdev, INTR_EN,
 590                            ctx->intr_en_mask);
 591                 var = ql_read32(qdev, STS);
 592                 return var;
 593         }
 594
 595         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 596         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 597                 ql_write32(qdev, INTR_EN,
 598                            ctx->intr_en_mask);
 599                 var = ql_read32(qdev, STS);
 600         }
 601         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 602         return var;
 603 }
 604
 605 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 606 {
 607         u32 var = 0;
 608         unsigned long hw_flags;
 609         struct intr_context *ctx;
 610
 611         /* HW disables for us if we're MSIX multi interrupts and
 612          * it's not the default (zeroeth) interrupt.
 613          */
 614         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 615                 return 0;
 616
 617         ctx = qdev->intr_context + intr;
 618         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 619         if (!atomic_read(&ctx->irq_cnt)) {
 620                 ql_write32(qdev, INTR_EN,
 621                 ctx->intr_dis_mask);
 622                 var = ql_read32(qdev, STS);
 623         }
 624         atomic_inc(&ctx->irq_cnt);
 625         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 626         return var;
 627 }
 628
 629 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 630 {
 631         int i;
 632         for (i = 0; i < qdev->intr_count; i++) {
 633                 /* The enable call does a atomic_dec_and_test
 634                  * and enables only if the result is zero.
 635                  * So we precharge it here.
 636                  */
 637                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 638                         i == 0))
 639                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 640                 ql_enable_completion_interrupt(qdev, i);
 641         }
 642
 643 }
 644
 645 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
 646 {
 647         int status = 0;
 648         /* wait for reg to come ready */
 649         status = ql_wait_reg_rdy(qdev,
 650                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 651         if (status)
 652                 goto exit;
 653         /* set up for reg read */
 654         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 655         /* wait for reg to come ready */
 656         status = ql_wait_reg_rdy(qdev,
 657                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 658         if (status)
 659                 goto exit;
 660         /* get the data */
 661         *data = ql_read32(qdev, FLASH_DATA);
 662 exit:
 663         return status;
 664 }
 665
 666 static int ql_get_flash_params(struct ql_adapter *qdev)
 667 {
 668         int i;
 669         int status;
 670         u32 *p = (u32 *)&qdev->flash;
 671
 672         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 673                 return -ETIMEDOUT;
 674
 675         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 676                 status = ql_read_flash_word(qdev, i, p);
 677                 if (status) {
 678                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 679                         goto exit;
 680                 }
 681
 682         }
 683 exit:
 684         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 685         return status;
 686 }
 687
 688 /* xgmac register are located behind the xgmac_addr and xgmac_data
 689  * register pair.  Each read/write requires us to wait for the ready
 690  * bit before reading/writing the data.
 691  */
 692 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 693 {
 694         int status;
 695         /* wait for reg to come ready */
 696         status = ql_wait_reg_rdy(qdev,
 697                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 698         if (status)
 699                 return status;
 700         /* write the data to the data reg */
 701         ql_write32(qdev, XGMAC_DATA, data);
 702         /* trigger the write */
 703         ql_write32(qdev, XGMAC_ADDR, reg);
 704         return status;
 705 }
 706
 707 /* xgmac register are located behind the xgmac_addr and xgmac_data
 708  * register pair.  Each read/write requires us to wait for the ready
 709  * bit before reading/writing the data.
 710  */
 711 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 712 {
 713         int status = 0;
 714         /* wait for reg to come ready */
 715         status = ql_wait_reg_rdy(qdev,
 716                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 717         if (status)
 718                 goto exit;
 719         /* set up for reg read */
 720         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 721         /* wait for reg to come ready */
 722         status = ql_wait_reg_rdy(qdev,
 723                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 724         if (status)
 725                 goto exit;
 726         /* get the data */
 727         *data = ql_read32(qdev, XGMAC_DATA);
 728 exit:
 729         return status;
 730 }
 731
 732 /* This is used for reading the 64-bit statistics regs. */
 733 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 734 {
 735         int status = 0;
 736         u32 hi = 0;
 737         u32 lo = 0;
 738
 739         status = ql_read_xgmac_reg(qdev, reg, &lo);
 740         if (status)
 741                 goto exit;
 742
 743         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 744         if (status)
 745                 goto exit;
 746
 747         *data = (u64) lo | ((u64) hi << 32);
 748
 749 exit:
 750         return status;
 751 }
 752
 753 /* Take the MAC Core out of reset.
 754  * Enable statistics counting.
 755  * Take the transmitter/receiver out of reset.
 756  * This functionality may be done in the MPI firmware at a
 757  * later date.
 758  */
 759 static int ql_port_initialize(struct ql_adapter *qdev)
 760 {
 761         int status = 0;
 762         u32 data;
 763
 764         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 765                 /* Another function has the semaphore, so
 766                  * wait for the port init bit to come ready.
 767                  */
 768                 QPRINTK(qdev, LINK, INFO,
 769                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 770                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 771                 if (status) {
 772                         QPRINTK(qdev, LINK, CRIT,
 773                                 "Port initialize timed out.\n");
 774                 }
 775                 return status;
 776         }
 777
 778         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 779         /* Set the core reset. */
 780         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 781         if (status)
 782                 goto end;
 783         data |= GLOBAL_CFG_RESET;
 784         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 785         if (status)
 786                 goto end;
 787
 788         /* Clear the core reset and turn on jumbo for receiver. */
 789         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 790         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 791         data |= GLOBAL_CFG_TX_STAT_EN;
 792         data |= GLOBAL_CFG_RX_STAT_EN;
 793         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 794         if (status)
 795                 goto end;
 796
 797         /* Enable transmitter, and clear it's reset. */
 798         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 799         if (status)
 800                 goto end;
 801         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 802         data |= TX_CFG_EN;      /* Enable the transmitter. */
 803         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 804         if (status)
 805                 goto end;
 806
 807         /* Enable receiver and clear it's reset. */
 808         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 809         if (status)
 810                 goto end;
 811         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 812         data |= RX_CFG_EN;      /* Enable the receiver. */
 813         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 814         if (status)
 815                 goto end;
 816
 817         /* Turn on jumbo. */
 818         status =
 819             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 820         if (status)
 821                 goto end;
 822         status =
 823             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 824         if (status)
 825                 goto end;
 826
 827         /* Signal to the world that the port is enabled.        */
 828         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 829 end:
 830         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 831         return status;
 832 }
 833
 834 /* Get the next large buffer. */
 835 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 836 {
 837         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 838         rx_ring->lbq_curr_idx++;
 839         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 840                 rx_ring->lbq_curr_idx = 0;
 841         rx_ring->lbq_free_cnt++;
 842         return lbq_desc;
 843 }
 844
 845 /* Get the next small buffer. */
 846 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 847 {
 848         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 849         rx_ring->sbq_curr_idx++;
 850         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 851                 rx_ring->sbq_curr_idx = 0;
 852         rx_ring->sbq_free_cnt++;
 853         return sbq_desc;
 854 }
 855
 856 /* Update an rx ring index. */
 857 static void ql_update_cq(struct rx_ring *rx_ring)
 858 {
 859         rx_ring->cnsmr_idx++;
 860         rx_ring->curr_entry++;
 861         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 862                 rx_ring->cnsmr_idx = 0;
 863                 rx_ring->curr_entry = rx_ring->cq_base;
 864         }
 865 }
 866
 867 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 868 {
 869         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 870 }
 871
 872 /* Process (refill) a large buffer queue. */
 873 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 874 {
 875         int clean_idx = rx_ring->lbq_clean_idx;
 876         struct bq_desc *lbq_desc;
 877         struct bq_element *bq;
 878         u64 map;
 879         int i;
 880
 881         while (rx_ring->lbq_free_cnt > 16) {
 882                 for (i = 0; i < 16; i++) {
 883                         QPRINTK(qdev, RX_STATUS, DEBUG,
 884                                 "lbq: try cleaning clean_idx = %d.\n",
 885                                 clean_idx);
 886                         lbq_desc = &rx_ring->lbq[clean_idx];
 887                         bq = lbq_desc->bq;
 888                         if (lbq_desc->p.lbq_page == NULL) {
 889                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 890                                         "lbq: getting new page for index %d.\n",
 891                                         lbq_desc->index);
 892                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 893                                 if (lbq_desc->p.lbq_page == NULL) {
 894                                         QPRINTK(qdev, RX_STATUS, ERR,
 895                                                 "Couldn't get a page.\n");
 896                                         return;
 897                                 }
 898                                 map = pci_map_page(qdev->pdev,
 899                                                    lbq_desc->p.lbq_page,
 900                                                    0, PAGE_SIZE,
 901                                                    PCI_DMA_FROMDEVICE);
 902                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 903                                         QPRINTK(qdev, RX_STATUS, ERR,
 904                                                 "PCI mapping failed.\n");
 905                                         return;
 906                                 }
 907                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 908                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 909                                 bq->addr_lo =   /*lbq_desc->addr_lo = */
 910                                     cpu_to_le32(map);
 911                                 bq->addr_hi =   /*lbq_desc->addr_hi = */
 912                                     cpu_to_le32(map >> 32);
 913                         }
 914                         clean_idx++;
 915                         if (clean_idx == rx_ring->lbq_len)
 916                                 clean_idx = 0;
 917                 }
 918
 919                 rx_ring->lbq_clean_idx = clean_idx;
 920                 rx_ring->lbq_prod_idx += 16;
 921                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 922                         rx_ring->lbq_prod_idx = 0;
 923                 QPRINTK(qdev, RX_STATUS, DEBUG,
 924                         "lbq: updating prod idx = %d.\n",
 925                         rx_ring->lbq_prod_idx);
 926                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 927                                 rx_ring->lbq_prod_idx_db_reg);
 928                 rx_ring->lbq_free_cnt -= 16;
 929         }
 930 }
 931
 932 /* Process (refill) a small buffer queue. */
 933 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 934 {
 935         int clean_idx = rx_ring->sbq_clean_idx;
 936         struct bq_desc *sbq_desc;
 937         struct bq_element *bq;
 938         u64 map;
 939         int i;
 940
 941         while (rx_ring->sbq_free_cnt > 16) {
 942                 for (i = 0; i < 16; i++) {
 943                         sbq_desc = &rx_ring->sbq[clean_idx];
 944                         QPRINTK(qdev, RX_STATUS, DEBUG,
 945                                 "sbq: try cleaning clean_idx = %d.\n",
 946                                 clean_idx);
 947                         bq = sbq_desc->bq;
 948                         if (sbq_desc->p.skb == NULL) {
 949                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 950                                         "sbq: getting new skb for index %d.\n",
 951                                         sbq_desc->index);
 952                                 sbq_desc->p.skb =
 953                                     netdev_alloc_skb(qdev->ndev,
 954                                                      rx_ring->sbq_buf_size);
 955                                 if (sbq_desc->p.skb == NULL) {
 956                                         QPRINTK(qdev, PROBE, ERR,
 957                                                 "Couldn't get an skb.\n");
 958                                         rx_ring->sbq_clean_idx = clean_idx;
 959                                         return;
 960                                 }
 961                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 962                                 map = pci_map_single(qdev->pdev,
 963                                                      sbq_desc->p.skb->data,
 964                                                      rx_ring->sbq_buf_size /
 965                                                      2, PCI_DMA_FROMDEVICE);
 966                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 967                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
 968                                         rx_ring->sbq_clean_idx = clean_idx;
 969                                         return;
 970                                 }
 971                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 972                                 pci_unmap_len_set(sbq_desc, maplen,
 973                                                   rx_ring->sbq_buf_size / 2);
 974                                 bq->addr_lo = cpu_to_le32(map);
 975                                 bq->addr_hi = cpu_to_le32(map >> 32);
 976                         }
 977
 978                         clean_idx++;
 979                         if (clean_idx == rx_ring->sbq_len)
 980                                 clean_idx = 0;
 981                 }
 982                 rx_ring->sbq_clean_idx = clean_idx;
 983                 rx_ring->sbq_prod_idx += 16;
 984                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 985                         rx_ring->sbq_prod_idx = 0;
 986                 QPRINTK(qdev, RX_STATUS, DEBUG,
 987                         "sbq: updating prod idx = %d.\n",
 988                         rx_ring->sbq_prod_idx);
 989                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 990                                 rx_ring->sbq_prod_idx_db_reg);
 991
 992                 rx_ring->sbq_free_cnt -= 16;
 993         }
 994 }
 995
 996 static void ql_update_buffer_queues(struct ql_adapter *qdev,
 997                                     struct rx_ring *rx_ring)
 998 {
 999         ql_update_sbq(qdev, rx_ring);
1000         ql_update_lbq(qdev, rx_ring);
1001 }
1002
1003 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1004  * fails at some stage, or from the interrupt when a tx completes.
1005  */
1006 static void ql_unmap_send(struct ql_adapter *qdev,
1007                           struct tx_ring_desc *tx_ring_desc, int mapped)
1008 {
1009         int i;
1010         for (i = 0; i < mapped; i++) {
1011                 if (i == 0 || (i == 7 && mapped > 7)) {
1012                         /*
1013                          * Unmap the skb->data area, or the
1014                          * external sglist (AKA the Outbound
1015                          * Address List (OAL)).
1016                          * If its the zeroeth element, then it's
1017                          * the skb->data area.  If it's the 7th
1018                          * element and there is more than 6 frags,
1019                          * then its an OAL.
1020                          */
1021                         if (i == 7) {
1022                                 QPRINTK(qdev, TX_DONE, DEBUG,
1023                                         "unmapping OAL area.\n");
1024                         }
1025                         pci_unmap_single(qdev->pdev,
1026                                          pci_unmap_addr(&tx_ring_desc->map[i],
1027                                                         mapaddr),
1028                                          pci_unmap_len(&tx_ring_desc->map[i],
1029                                                        maplen),
1030                                          PCI_DMA_TODEVICE);
1031                 } else {
1032                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1033                                 i);
1034                         pci_unmap_page(qdev->pdev,
1035                                        pci_unmap_addr(&tx_ring_desc->map[i],
1036                                                       mapaddr),
1037                                        pci_unmap_len(&tx_ring_desc->map[i],
1038                                                      maplen), PCI_DMA_TODEVICE);
1039                 }
1040         }
1041
1042 }
1043
1044 /* Map the buffers for this transmit.  This will return
1045  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1046  */
1047 static int ql_map_send(struct ql_adapter *qdev,
1048                        struct ob_mac_iocb_req *mac_iocb_ptr,
1049                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1050 {
1051         int len = skb_headlen(skb);
1052         dma_addr_t map;
1053         int frag_idx, err, map_idx = 0;
1054         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1055         int frag_cnt = skb_shinfo(skb)->nr_frags;
1056
1057         if (frag_cnt) {
1058                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1059         }
1060         /*
1061          * Map the skb buffer first.
1062          */
1063         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1064
1065         err = pci_dma_mapping_error(qdev->pdev, map);
1066         if (err) {
1067                 QPRINTK(qdev, TX_QUEUED, ERR,
1068                         "PCI mapping failed with error: %d\n", err);
1069
1070                 return NETDEV_TX_BUSY;
1071         }
1072
1073         tbd->len = cpu_to_le32(len);
1074         tbd->addr = cpu_to_le64(map);
1075         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1076         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1077         map_idx++;
1078
1079         /*
1080          * This loop fills the remainder of the 8 address descriptors
1081          * in the IOCB.  If there are more than 7 fragments, then the
1082          * eighth address desc will point to an external list (OAL).
1083          * When this happens, the remainder of the frags will be stored
1084          * in this list.
1085          */
1086         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1087                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1088                 tbd++;
1089                 if (frag_idx == 6 && frag_cnt > 7) {
1090                         /* Let's tack on an sglist.
1091                          * Our control block will now
1092                          * look like this:
1093                          * iocb->seg[0] = skb->data
1094                          * iocb->seg[1] = frag[0]
1095                          * iocb->seg[2] = frag[1]
1096                          * iocb->seg[3] = frag[2]
1097                          * iocb->seg[4] = frag[3]
1098                          * iocb->seg[5] = frag[4]
1099                          * iocb->seg[6] = frag[5]
1100                          * iocb->seg[7] = ptr to OAL (external sglist)
1101                          * oal->seg[0] = frag[6]
1102                          * oal->seg[1] = frag[7]
1103                          * oal->seg[2] = frag[8]
1104                          * oal->seg[3] = frag[9]
1105                          * oal->seg[4] = frag[10]
1106                          *      etc...
1107                          */
1108                         /* Tack on the OAL in the eighth segment of IOCB. */
1109                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1110                                              sizeof(struct oal),
1111                                              PCI_DMA_TODEVICE);
1112                         err = pci_dma_mapping_error(qdev->pdev, map);
1113                         if (err) {
1114                                 QPRINTK(qdev, TX_QUEUED, ERR,
1115                                         "PCI mapping outbound address list with error: %d\n",
1116                                         err);
1117                                 goto map_error;
1118                         }
1119
1120                         tbd->addr = cpu_to_le64(map);
1121                         /*
1122                          * The length is the number of fragments
1123                          * that remain to be mapped times the length
1124                          * of our sglist (OAL).
1125                          */
1126                         tbd->len =
1127                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1128                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1129                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1130                                            map);
1131                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1132                                           sizeof(struct oal));
1133                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1134                         map_idx++;
1135                 }
1136
1137                 map =
1138                     pci_map_page(qdev->pdev, frag->page,
1139                                  frag->page_offset, frag->size,
1140                                  PCI_DMA_TODEVICE);
1141
1142                 err = pci_dma_mapping_error(qdev->pdev, map);
1143                 if (err) {
1144                         QPRINTK(qdev, TX_QUEUED, ERR,
1145                                 "PCI mapping frags failed with error: %d.\n",
1146                                 err);
1147                         goto map_error;
1148                 }
1149
1150                 tbd->addr = cpu_to_le64(map);
1151                 tbd->len = cpu_to_le32(frag->size);
1152                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1153                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1154                                   frag->size);
1155
1156         }
1157         /* Save the number of segments we've mapped. */
1158         tx_ring_desc->map_cnt = map_idx;
1159         /* Terminate the last segment. */
1160         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1161         return NETDEV_TX_OK;
1162
1163 map_error:
1164         /*
1165          * If the first frag mapping failed, then i will be zero.
1166          * This causes the unmap of the skb->data area.  Otherwise
1167          * we pass in the number of frags that mapped successfully
1168          * so they can be umapped.
1169          */
1170         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1171         return NETDEV_TX_BUSY;
1172 }
1173
1174 static void ql_realign_skb(struct sk_buff *skb, int len)
1175 {
1176         void *temp_addr = skb->data;
1177
1178         /* Undo the skb_reserve(skb,32) we did before
1179          * giving to hardware, and realign data on
1180          * a 2-byte boundary.
1181          */
1182         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1183         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1184         skb_copy_to_linear_data(skb, temp_addr,
1185                 (unsigned int)len);
1186 }
1187
1188 /*
1189  * This function builds an skb for the given inbound
1190  * completion.  It will be rewritten for readability in the near
1191  * future, but for not it works well.
1192  */
1193 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1194                                        struct rx_ring *rx_ring,
1195                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1196 {
1197         struct bq_desc *lbq_desc;
1198         struct bq_desc *sbq_desc;
1199         struct sk_buff *skb = NULL;
1200         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1201        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1202
1203         /*
1204          * Handle the header buffer if present.
1205          */
1206         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1207             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1208                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1209                 /*
1210                  * Headers fit nicely into a small buffer.
1211                  */
1212                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1213                 pci_unmap_single(qdev->pdev,
1214                                 pci_unmap_addr(sbq_desc, mapaddr),
1215                                 pci_unmap_len(sbq_desc, maplen),
1216                                 PCI_DMA_FROMDEVICE);
1217                 skb = sbq_desc->p.skb;
1218                 ql_realign_skb(skb, hdr_len);
1219                 skb_put(skb, hdr_len);
1220                 sbq_desc->p.skb = NULL;
1221         }
1222
1223         /*
1224          * Handle the data buffer(s).
1225          */
1226         if (unlikely(!length)) {        /* Is there data too? */
1227                 QPRINTK(qdev, RX_STATUS, DEBUG,
1228                         "No Data buffer in this packet.\n");
1229                 return skb;
1230         }
1231
1232         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1233                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1234                         QPRINTK(qdev, RX_STATUS, DEBUG,
1235                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1236                         /*
1237                          * Data is less than small buffer size so it's
1238                          * stuffed in a small buffer.
1239                          * For this case we append the data
1240                          * from the "data" small buffer to the "header" small
1241                          * buffer.
1242                          */
1243                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1244                         pci_dma_sync_single_for_cpu(qdev->pdev,
1245                                                     pci_unmap_addr
1246                                                     (sbq_desc, mapaddr),
1247                                                     pci_unmap_len
1248                                                     (sbq_desc, maplen),
1249                                                     PCI_DMA_FROMDEVICE);
1250                         memcpy(skb_put(skb, length),
1251                                sbq_desc->p.skb->data, length);
1252                         pci_dma_sync_single_for_device(qdev->pdev,
1253                                                        pci_unmap_addr
1254                                                        (sbq_desc,
1255                                                         mapaddr),
1256                                                        pci_unmap_len
1257                                                        (sbq_desc,
1258                                                         maplen),
1259                                                        PCI_DMA_FROMDEVICE);
1260                 } else {
1261                         QPRINTK(qdev, RX_STATUS, DEBUG,
1262                                 "%d bytes in a single small buffer.\n", length);
1263                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1264                         skb = sbq_desc->p.skb;
1265                         ql_realign_skb(skb, length);
1266                         skb_put(skb, length);
1267                         pci_unmap_single(qdev->pdev,
1268                                          pci_unmap_addr(sbq_desc,
1269                                                         mapaddr),
1270                                          pci_unmap_len(sbq_desc,
1271                                                        maplen),
1272                                          PCI_DMA_FROMDEVICE);
1273                         sbq_desc->p.skb = NULL;
1274                 }
1275         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1276                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1277                         QPRINTK(qdev, RX_STATUS, DEBUG,
1278                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1279                         /*
1280                          * The data is in a single large buffer.  We
1281                          * chain it to the header buffer's skb and let
1282                          * it rip.
1283                          */
1284                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1285                         pci_unmap_page(qdev->pdev,
1286                                        pci_unmap_addr(lbq_desc,
1287                                                       mapaddr),
1288                                        pci_unmap_len(lbq_desc, maplen),
1289                                        PCI_DMA_FROMDEVICE);
1290                         QPRINTK(qdev, RX_STATUS, DEBUG,
1291                                 "Chaining page to skb.\n");
1292                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1293                                            0, length);
1294                         skb->len += length;
1295                         skb->data_len += length;
1296                         skb->truesize += length;
1297                         lbq_desc->p.lbq_page = NULL;
1298                 } else {
1299                         /*
1300                          * The headers and data are in a single large buffer. We
1301                          * copy it to a new skb and let it go. This can happen with
1302                          * jumbo mtu on a non-TCP/UDP frame.
1303                          */
1304                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1305                         skb = netdev_alloc_skb(qdev->ndev, length);
1306                         if (skb == NULL) {
1307                                 QPRINTK(qdev, PROBE, DEBUG,
1308                                         "No skb available, drop the packet.\n");
1309                                 return NULL;
1310                         }
1311                         pci_unmap_page(qdev->pdev,
1312                                        pci_unmap_addr(lbq_desc,
1313                                                       mapaddr),
1314                                        pci_unmap_len(lbq_desc, maplen),
1315                                        PCI_DMA_FROMDEVICE);
1316                         skb_reserve(skb, NET_IP_ALIGN);
1317                         QPRINTK(qdev, RX_STATUS, DEBUG,
1318                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1319                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1320                                            0, length);
1321                         skb->len += length;
1322                         skb->data_len += length;
1323                         skb->truesize += length;
1324                         length -= length;
1325                         lbq_desc->p.lbq_page = NULL;
1326                         __pskb_pull_tail(skb,
1327                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1328                                 VLAN_ETH_HLEN : ETH_HLEN);
1329                 }
1330         } else {
1331                 /*
1332                  * The data is in a chain of large buffers
1333                  * pointed to by a small buffer.  We loop
1334                  * thru and chain them to the our small header
1335                  * buffer's skb.
1336                  * frags:  There are 18 max frags and our small
1337                  *         buffer will hold 32 of them. The thing is,
1338                  *         we'll use 3 max for our 9000 byte jumbo
1339                  *         frames.  If the MTU goes up we could
1340                  *          eventually be in trouble.
1341                  */
1342                 int size, offset, i = 0;
1343                 struct bq_element *bq, bq_array[8];
1344                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1345                 pci_unmap_single(qdev->pdev,
1346                                  pci_unmap_addr(sbq_desc, mapaddr),
1347                                  pci_unmap_len(sbq_desc, maplen),
1348                                  PCI_DMA_FROMDEVICE);
1349                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1350                         /*
1351                          * This is an non TCP/UDP IP frame, so
1352                          * the headers aren't split into a small
1353                          * buffer.  We have to use the small buffer
1354                          * that contains our sg list as our skb to
1355                          * send upstairs. Copy the sg list here to
1356                          * a local buffer and use it to find the
1357                          * pages to chain.
1358                          */
1359                         QPRINTK(qdev, RX_STATUS, DEBUG,
1360                                 "%d bytes of headers & data in chain of large.\n", length);
1361                         skb = sbq_desc->p.skb;
1362                         bq = &bq_array[0];
1363                         memcpy(bq, skb->data, sizeof(bq_array));
1364                         sbq_desc->p.skb = NULL;
1365                         skb_reserve(skb, NET_IP_ALIGN);
1366                 } else {
1367                         QPRINTK(qdev, RX_STATUS, DEBUG,
1368                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1369                         bq = (struct bq_element *)sbq_desc->p.skb->data;
1370                 }
1371                 while (length > 0) {
1372                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1373                         if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
1374                                 QPRINTK(qdev, RX_STATUS, ERR,
1375                                         "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1376                                         lbq_desc->bq->addr_lo, bq->addr_lo);
1377                                 return NULL;
1378                         }
1379                         pci_unmap_page(qdev->pdev,
1380                                        pci_unmap_addr(lbq_desc,
1381                                                       mapaddr),
1382                                        pci_unmap_len(lbq_desc,
1383                                                      maplen),
1384                                        PCI_DMA_FROMDEVICE);
1385                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1386                         offset = 0;
1387
1388                         QPRINTK(qdev, RX_STATUS, DEBUG,
1389                                 "Adding page %d to skb for %d bytes.\n",
1390                                 i, size);
1391                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1392                                            offset, size);
1393                         skb->len += size;
1394                         skb->data_len += size;
1395                         skb->truesize += size;
1396                         length -= size;
1397                         lbq_desc->p.lbq_page = NULL;
1398                         bq++;
1399                         i++;
1400                 }
1401                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1402                                 VLAN_ETH_HLEN : ETH_HLEN);
1403         }
1404         return skb;
1405 }
1406
1407 /* Process an inbound completion from an rx ring. */
1408 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1409                                    struct rx_ring *rx_ring,
1410                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1411 {
1412         struct net_device *ndev = qdev->ndev;
1413         struct sk_buff *skb = NULL;
1414
1415         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1416
1417         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1418         if (unlikely(!skb)) {
1419                 QPRINTK(qdev, RX_STATUS, DEBUG,
1420                         "No skb available, drop packet.\n");
1421                 return;
1422         }
1423
1424         prefetch(skb->data);
1425         skb->dev = ndev;
1426         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1427                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1428                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1429                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1430                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1431                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1432                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1433                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1434         }
1435         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1436                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1437         }
1438         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1439                 QPRINTK(qdev, RX_STATUS, ERR,
1440                         "Bad checksum for this %s packet.\n",
1441                         ((ib_mac_rsp->
1442                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1443                 skb->ip_summed = CHECKSUM_NONE;
1444         } else if (qdev->rx_csum &&
1445                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1446                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1447                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1448                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1449                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1450         }
1451         qdev->stats.rx_packets++;
1452         qdev->stats.rx_bytes += skb->len;
1453         skb->protocol = eth_type_trans(skb, ndev);
1454         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1455                 QPRINTK(qdev, RX_STATUS, DEBUG,
1456                         "Passing a VLAN packet upstream.\n");
1457                 vlan_hwaccel_rx(skb, qdev->vlgrp,
1458                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1459         } else {
1460                 QPRINTK(qdev, RX_STATUS, DEBUG,
1461                         "Passing a normal packet upstream.\n");
1462                 netif_rx(skb);
1463         }
1464 }
1465
1466 /* Process an outbound completion from an rx ring. */
1467 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1468                                    struct ob_mac_iocb_rsp *mac_rsp)
1469 {
1470         struct tx_ring *tx_ring;
1471         struct tx_ring_desc *tx_ring_desc;
1472
1473         QL_DUMP_OB_MAC_RSP(mac_rsp);
1474         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1475         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1476         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1477         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1478         qdev->stats.tx_packets++;
1479         dev_kfree_skb(tx_ring_desc->skb);
1480         tx_ring_desc->skb = NULL;
1481
1482         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1483                                         OB_MAC_IOCB_RSP_S |
1484                                         OB_MAC_IOCB_RSP_L |
1485                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1486                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1487                         QPRINTK(qdev, TX_DONE, WARNING,
1488                                 "Total descriptor length did not match transfer length.\n");
1489                 }
1490                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1491                         QPRINTK(qdev, TX_DONE, WARNING,
1492                                 "Frame too short to be legal, not sent.\n");
1493                 }
1494                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1495                         QPRINTK(qdev, TX_DONE, WARNING,
1496                                 "Frame too long, but sent anyway.\n");
1497                 }
1498                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1499                         QPRINTK(qdev, TX_DONE, WARNING,
1500                                 "PCI backplane error. Frame not sent.\n");
1501                 }
1502         }
1503         atomic_inc(&tx_ring->tx_count);
1504 }
1505
1506 /* Fire up a handler to reset the MPI processor. */
1507 void ql_queue_fw_error(struct ql_adapter *qdev)
1508 {
1509         netif_stop_queue(qdev->ndev);
1510         netif_carrier_off(qdev->ndev);
1511         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1512 }
1513
1514 void ql_queue_asic_error(struct ql_adapter *qdev)
1515 {
1516         netif_stop_queue(qdev->ndev);
1517         netif_carrier_off(qdev->ndev);
1518         ql_disable_interrupts(qdev);
1519         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1520 }
1521
1522 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1523                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1524 {
1525         switch (ib_ae_rsp->event) {
1526         case MGMT_ERR_EVENT:
1527                 QPRINTK(qdev, RX_ERR, ERR,
1528                         "Management Processor Fatal Error.\n");
1529                 ql_queue_fw_error(qdev);
1530                 return;
1531
1532         case CAM_LOOKUP_ERR_EVENT:
1533                 QPRINTK(qdev, LINK, ERR,
1534                         "Multiple CAM hits lookup occurred.\n");
1535                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1536                 ql_queue_asic_error(qdev);
1537                 return;
1538
1539         case SOFT_ECC_ERROR_EVENT:
1540                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1541                 ql_queue_asic_error(qdev);
1542                 break;
1543
1544         case PCI_ERR_ANON_BUF_RD:
1545                 QPRINTK(qdev, RX_ERR, ERR,
1546                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1547                         ib_ae_rsp->q_id);
1548                 ql_queue_asic_error(qdev);
1549                 break;
1550
1551         default:
1552                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1553                         ib_ae_rsp->event);
1554                 ql_queue_asic_error(qdev);
1555                 break;
1556         }
1557 }
1558
1559 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1560 {
1561         struct ql_adapter *qdev = rx_ring->qdev;
1562         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1563         struct ob_mac_iocb_rsp *net_rsp = NULL;
1564         int count = 0;
1565
1566         /* While there are entries in the completion queue. */
1567         while (prod != rx_ring->cnsmr_idx) {
1568
1569                 QPRINTK(qdev, RX_STATUS, DEBUG,
1570                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1571                         prod, rx_ring->cnsmr_idx);
1572
1573                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1574                 rmb();
1575                 switch (net_rsp->opcode) {
1576
1577                 case OPCODE_OB_MAC_TSO_IOCB:
1578                 case OPCODE_OB_MAC_IOCB:
1579                         ql_process_mac_tx_intr(qdev, net_rsp);
1580                         break;
1581                 default:
1582                         QPRINTK(qdev, RX_STATUS, DEBUG,
1583                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1584                                 net_rsp->opcode);
1585                 }
1586                 count++;
1587                 ql_update_cq(rx_ring);
1588                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1589         }
1590         ql_write_cq_idx(rx_ring);
1591         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1592                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1593                 if (atomic_read(&tx_ring->queue_stopped) &&
1594                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1595                         /*
1596                          * The queue got stopped because the tx_ring was full.
1597                          * Wake it up, because it's now at least 25% empty.
1598                          */
1599                         netif_wake_queue(qdev->ndev);
1600         }
1601
1602         return count;
1603 }
1604
1605 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1606 {
1607         struct ql_adapter *qdev = rx_ring->qdev;
1608         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1609         struct ql_net_rsp_iocb *net_rsp;
1610         int count = 0;
1611
1612         /* While there are entries in the completion queue. */
1613         while (prod != rx_ring->cnsmr_idx) {
1614
1615                 QPRINTK(qdev, RX_STATUS, DEBUG,
1616                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1617                         prod, rx_ring->cnsmr_idx);
1618
1619                 net_rsp = rx_ring->curr_entry;
1620                 rmb();
1621                 switch (net_rsp->opcode) {
1622                 case OPCODE_IB_MAC_IOCB:
1623                         ql_process_mac_rx_intr(qdev, rx_ring,
1624                                                (struct ib_mac_iocb_rsp *)
1625                                                net_rsp);
1626                         break;
1627
1628                 case OPCODE_IB_AE_IOCB:
1629                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1630                                                 net_rsp);
1631                         break;
1632                 default:
1633                         {
1634                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1635                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1636                                         net_rsp->opcode);
1637                         }
1638                 }
1639                 count++;
1640                 ql_update_cq(rx_ring);
1641                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1642                 if (count == budget)
1643                         break;
1644         }
1645         ql_update_buffer_queues(qdev, rx_ring);
1646         ql_write_cq_idx(rx_ring);
1647         return count;
1648 }
1649
1650 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1651 {
1652         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1653         struct ql_adapter *qdev = rx_ring->qdev;
1654         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1655
1656         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1657                 rx_ring->cq_id);
1658
1659         if (work_done < budget) {
1660                 __netif_rx_complete(napi);
1661                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1662         }
1663         return work_done;
1664 }
1665
1666 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1667 {
1668         struct ql_adapter *qdev = netdev_priv(ndev);
1669
1670         qdev->vlgrp = grp;
1671         if (grp) {
1672                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1673                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1674                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1675         } else {
1676                 QPRINTK(qdev, IFUP, DEBUG,
1677                         "Turning off VLAN in NIC_RCV_CFG.\n");
1678                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1679         }
1680 }
1681
1682 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1683 {
1684         struct ql_adapter *qdev = netdev_priv(ndev);
1685         u32 enable_bit = MAC_ADDR_E;
1686
1687         spin_lock(&qdev->hw_lock);
1688         if (ql_set_mac_addr_reg
1689             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1690                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1691         }
1692         spin_unlock(&qdev->hw_lock);
1693 }
1694
1695 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1696 {
1697         struct ql_adapter *qdev = netdev_priv(ndev);
1698         u32 enable_bit = 0;
1699
1700         spin_lock(&qdev->hw_lock);
1701         if (ql_set_mac_addr_reg
1702             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1703                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1704         }
1705         spin_unlock(&qdev->hw_lock);
1706
1707 }
1708
1709 /* Worker thread to process a given rx_ring that is dedicated
1710  * to outbound completions.
1711  */
1712 static void ql_tx_clean(struct work_struct *work)
1713 {
1714         struct rx_ring *rx_ring =
1715             container_of(work, struct rx_ring, rx_work.work);
1716         ql_clean_outbound_rx_ring(rx_ring);
1717         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1718
1719 }
1720
1721 /* Worker thread to process a given rx_ring that is dedicated
1722  * to inbound completions.
1723  */
1724 static void ql_rx_clean(struct work_struct *work)
1725 {
1726         struct rx_ring *rx_ring =
1727             container_of(work, struct rx_ring, rx_work.work);
1728         ql_clean_inbound_rx_ring(rx_ring, 64);
1729         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1730 }
1731
1732 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1733 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1734 {
1735         struct rx_ring *rx_ring = dev_id;
1736         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1737                               &rx_ring->rx_work, 0);
1738         return IRQ_HANDLED;
1739 }
1740
1741 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1742 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1743 {
1744         struct rx_ring *rx_ring = dev_id;
1745         netif_rx_schedule(&rx_ring->napi);
1746         return IRQ_HANDLED;
1747 }
1748
1749 /* This handles a fatal error, MPI activity, and the default
1750  * rx_ring in an MSI-X multiple vector environment.
1751  * In MSI/Legacy environment it also process the rest of
1752  * the rx_rings.
1753  */
1754 static irqreturn_t qlge_isr(int irq, void *dev_id)
1755 {
1756         struct rx_ring *rx_ring = dev_id;
1757         struct ql_adapter *qdev = rx_ring->qdev;
1758         struct intr_context *intr_context = &qdev->intr_context[0];
1759         u32 var;
1760         int i;
1761         int work_done = 0;
1762
1763         spin_lock(&qdev->hw_lock);
1764         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1765                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1766                 spin_unlock(&qdev->hw_lock);
1767                 return IRQ_NONE;
1768         }
1769         spin_unlock(&qdev->hw_lock);
1770
1771         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1772
1773         /*
1774          * Check for fatal error.
1775          */
1776         if (var & STS_FE) {
1777                 ql_queue_asic_error(qdev);
1778                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1779                 var = ql_read32(qdev, ERR_STS);
1780                 QPRINTK(qdev, INTR, ERR,
1781                         "Resetting chip. Error Status Register = 0x%x\n", var);
1782                 return IRQ_HANDLED;
1783         }
1784
1785         /*
1786          * Check MPI processor activity.
1787          */
1788         if (var & STS_PI) {
1789                 /*
1790                  * We've got an async event or mailbox completion.
1791                  * Handle it and clear the source of the interrupt.
1792                  */
1793                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1794                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1795                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1796                                       &qdev->mpi_work, 0);
1797                 work_done++;
1798         }
1799
1800         /*
1801          * Check the default queue and wake handler if active.
1802          */
1803         rx_ring = &qdev->rx_ring[0];
1804         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1805                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1806                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1807                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1808                                       &rx_ring->rx_work, 0);
1809                 work_done++;
1810         }
1811
1812         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1813                 /*
1814                  * Start the DPC for each active queue.
1815                  */
1816                 for (i = 1; i < qdev->rx_ring_count; i++) {
1817                         rx_ring = &qdev->rx_ring[i];
1818                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1819                             rx_ring->cnsmr_idx) {
1820                                 QPRINTK(qdev, INTR, INFO,
1821                                         "Waking handler for rx_ring[%d].\n", i);
1822                                 ql_disable_completion_interrupt(qdev,
1823                                                                 intr_context->
1824                                                                 intr);
1825                                 if (i < qdev->rss_ring_first_cq_id)
1826                                         queue_delayed_work_on(rx_ring->cpu,
1827                                                               qdev->q_workqueue,
1828                                                               &rx_ring->rx_work,
1829                                                               0);
1830                                 else
1831                                         netif_rx_schedule(&rx_ring->napi);
1832                                 work_done++;
1833                         }
1834                 }
1835         }
1836         ql_enable_completion_interrupt(qdev, intr_context->intr);
1837         return work_done ? IRQ_HANDLED : IRQ_NONE;
1838 }
1839
1840 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1841 {
1842
1843         if (skb_is_gso(skb)) {
1844                 int err;
1845                 if (skb_header_cloned(skb)) {
1846                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1847                         if (err)
1848                                 return err;
1849                 }
1850
1851                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1852                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1853                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1854                 mac_iocb_ptr->total_hdrs_len =
1855                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1856                 mac_iocb_ptr->net_trans_offset =
1857                     cpu_to_le16(skb_network_offset(skb) |
1858                                 skb_transport_offset(skb)
1859                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1860                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1861                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1862                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1863                         struct iphdr *iph = ip_hdr(skb);
1864                         iph->check = 0;
1865                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1866                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1867                                                                  iph->daddr, 0,
1868                                                                  IPPROTO_TCP,
1869                                                                  0);
1870                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1871                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1872                         tcp_hdr(skb)->check =
1873                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1874                                              &ipv6_hdr(skb)->daddr,
1875                                              0, IPPROTO_TCP, 0);
1876                 }
1877                 return 1;
1878         }
1879         return 0;
1880 }
1881
1882 static void ql_hw_csum_setup(struct sk_buff *skb,
1883                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1884 {
1885         int len;
1886         struct iphdr *iph = ip_hdr(skb);
1887         u16 *check;
1888         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1889         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1890         mac_iocb_ptr->net_trans_offset =
1891                 cpu_to_le16(skb_network_offset(skb) |
1892                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1893
1894         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1895         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1896         if (likely(iph->protocol == IPPROTO_TCP)) {
1897                 check = &(tcp_hdr(skb)->check);
1898                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1899                 mac_iocb_ptr->total_hdrs_len =
1900                     cpu_to_le16(skb_transport_offset(skb) +
1901                                 (tcp_hdr(skb)->doff << 2));
1902         } else {
1903                 check = &(udp_hdr(skb)->check);
1904                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1905                 mac_iocb_ptr->total_hdrs_len =
1906                     cpu_to_le16(skb_transport_offset(skb) +
1907                                 sizeof(struct udphdr));
1908         }
1909         *check = ~csum_tcpudp_magic(iph->saddr,
1910                                     iph->daddr, len, iph->protocol, 0);
1911 }
1912
1913 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1914 {
1915         struct tx_ring_desc *tx_ring_desc;
1916         struct ob_mac_iocb_req *mac_iocb_ptr;
1917         struct ql_adapter *qdev = netdev_priv(ndev);
1918         int tso;
1919         struct tx_ring *tx_ring;
1920         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1921
1922         tx_ring = &qdev->tx_ring[tx_ring_idx];
1923
1924         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1925                 QPRINTK(qdev, TX_QUEUED, INFO,
1926                         "%s: shutting down tx queue %d du to lack of resources.\n",
1927                         __func__, tx_ring_idx);
1928                 netif_stop_queue(ndev);
1929                 atomic_inc(&tx_ring->queue_stopped);
1930                 return NETDEV_TX_BUSY;
1931         }
1932         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1933         mac_iocb_ptr = tx_ring_desc->queue_entry;
1934         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1935         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1936                 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1937                 return NETDEV_TX_BUSY;
1938         }
1939
1940         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1941         mac_iocb_ptr->tid = tx_ring_desc->index;
1942         /* We use the upper 32-bits to store the tx queue for this IO.
1943          * When we get the completion we can use it to establish the context.
1944          */
1945         mac_iocb_ptr->txq_idx = tx_ring_idx;
1946         tx_ring_desc->skb = skb;
1947
1948         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1949
1950         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1951                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1952                         vlan_tx_tag_get(skb));
1953                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1954                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1955         }
1956         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1957         if (tso < 0) {
1958                 dev_kfree_skb_any(skb);
1959                 return NETDEV_TX_OK;
1960         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1961                 ql_hw_csum_setup(skb,
1962                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1963         }
1964         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1965         tx_ring->prod_idx++;
1966         if (tx_ring->prod_idx == tx_ring->wq_len)
1967                 tx_ring->prod_idx = 0;
1968         wmb();
1969
1970         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1971         ndev->trans_start = jiffies;
1972         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1973                 tx_ring->prod_idx, skb->len);
1974
1975         atomic_dec(&tx_ring->tx_count);
1976         return NETDEV_TX_OK;
1977 }
1978
1979 static void ql_free_shadow_space(struct ql_adapter *qdev)
1980 {
1981         if (qdev->rx_ring_shadow_reg_area) {
1982                 pci_free_consistent(qdev->pdev,
1983                                     PAGE_SIZE,
1984                                     qdev->rx_ring_shadow_reg_area,
1985                                     qdev->rx_ring_shadow_reg_dma);
1986                 qdev->rx_ring_shadow_reg_area = NULL;
1987         }
1988         if (qdev->tx_ring_shadow_reg_area) {
1989                 pci_free_consistent(qdev->pdev,
1990                                     PAGE_SIZE,
1991                                     qdev->tx_ring_shadow_reg_area,
1992                                     qdev->tx_ring_shadow_reg_dma);
1993                 qdev->tx_ring_shadow_reg_area = NULL;
1994         }
1995 }
1996
1997 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1998 {
1999         qdev->rx_ring_shadow_reg_area =
2000             pci_alloc_consistent(qdev->pdev,
2001                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2002         if (qdev->rx_ring_shadow_reg_area == NULL) {
2003                 QPRINTK(qdev, IFUP, ERR,
2004                         "Allocation of RX shadow space failed.\n");
2005                 return -ENOMEM;
2006         }
2007         qdev->tx_ring_shadow_reg_area =
2008             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2009                                  &qdev->tx_ring_shadow_reg_dma);
2010         if (qdev->tx_ring_shadow_reg_area == NULL) {
2011                 QPRINTK(qdev, IFUP, ERR,
2012                         "Allocation of TX shadow space failed.\n");
2013                 goto err_wqp_sh_area;
2014         }
2015         return 0;
2016
2017 err_wqp_sh_area:
2018         pci_free_consistent(qdev->pdev,
2019                             PAGE_SIZE,
2020                             qdev->rx_ring_shadow_reg_area,
2021                             qdev->rx_ring_shadow_reg_dma);
2022         return -ENOMEM;
2023 }
2024
2025 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2026 {
2027         struct tx_ring_desc *tx_ring_desc;
2028         int i;
2029         struct ob_mac_iocb_req *mac_iocb_ptr;
2030
2031         mac_iocb_ptr = tx_ring->wq_base;
2032         tx_ring_desc = tx_ring->q;
2033         for (i = 0; i < tx_ring->wq_len; i++) {
2034                 tx_ring_desc->index = i;
2035                 tx_ring_desc->skb = NULL;
2036                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2037                 mac_iocb_ptr++;
2038                 tx_ring_desc++;
2039         }
2040         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2041         atomic_set(&tx_ring->queue_stopped, 0);
2042 }
2043
2044 static void ql_free_tx_resources(struct ql_adapter *qdev,
2045                                  struct tx_ring *tx_ring)
2046 {
2047         if (tx_ring->wq_base) {
2048                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2049                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2050                 tx_ring->wq_base = NULL;
2051         }
2052         kfree(tx_ring->q);
2053         tx_ring->q = NULL;
2054 }
2055
2056 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2057                                  struct tx_ring *tx_ring)
2058 {
2059         tx_ring->wq_base =
2060             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2061                                  &tx_ring->wq_base_dma);
2062
2063         if ((tx_ring->wq_base == NULL)
2064             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2065                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2066                 return -ENOMEM;
2067         }
2068         tx_ring->q =
2069             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2070         if (tx_ring->q == NULL)
2071                 goto err;
2072
2073         return 0;
2074 err:
2075         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2076                             tx_ring->wq_base, tx_ring->wq_base_dma);
2077         return -ENOMEM;
2078 }
2079
2080 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2081 {
2082         int i;
2083         struct bq_desc *lbq_desc;
2084
2085         for (i = 0; i < rx_ring->lbq_len; i++) {
2086                 lbq_desc = &rx_ring->lbq[i];
2087                 if (lbq_desc->p.lbq_page) {
2088                         pci_unmap_page(qdev->pdev,
2089                                        pci_unmap_addr(lbq_desc, mapaddr),
2090                                        pci_unmap_len(lbq_desc, maplen),
2091                                        PCI_DMA_FROMDEVICE);
2092
2093                         put_page(lbq_desc->p.lbq_page);
2094                         lbq_desc->p.lbq_page = NULL;
2095                 }
2096                 lbq_desc->bq->addr_lo = 0;
2097                 lbq_desc->bq->addr_hi = 0;
2098         }
2099 }
2100
2101 /*
2102  * Allocate and map a page for each element of the lbq.
2103  */
2104 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2105                                 struct rx_ring *rx_ring)
2106 {
2107         int i;
2108         struct bq_desc *lbq_desc;
2109         u64 map;
2110         struct bq_element *bq = rx_ring->lbq_base;
2111
2112         for (i = 0; i < rx_ring->lbq_len; i++) {
2113                 lbq_desc = &rx_ring->lbq[i];
2114                 memset(lbq_desc, 0, sizeof(lbq_desc));
2115                 lbq_desc->bq = bq;
2116                 lbq_desc->index = i;
2117                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2118                 if (unlikely(!lbq_desc->p.lbq_page)) {
2119                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2120                         goto mem_error;
2121                 } else {
2122                         map = pci_map_page(qdev->pdev,
2123                                            lbq_desc->p.lbq_page,
2124                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2125                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2126                                 QPRINTK(qdev, IFUP, ERR,
2127                                         "PCI mapping failed.\n");
2128                                 goto mem_error;
2129                         }
2130                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2131                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2132                         bq->addr_lo = cpu_to_le32(map);
2133                         bq->addr_hi = cpu_to_le32(map >> 32);
2134                 }
2135                 bq++;
2136         }
2137         return 0;
2138 mem_error:
2139         ql_free_lbq_buffers(qdev, rx_ring);
2140         return -ENOMEM;
2141 }
2142
2143 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2144 {
2145         int i;
2146         struct bq_desc *sbq_desc;
2147
2148         for (i = 0; i < rx_ring->sbq_len; i++) {
2149                 sbq_desc = &rx_ring->sbq[i];
2150                 if (sbq_desc == NULL) {
2151                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2152                         return;
2153                 }
2154                 if (sbq_desc->p.skb) {
2155                         pci_unmap_single(qdev->pdev,
2156                                          pci_unmap_addr(sbq_desc, mapaddr),
2157                                          pci_unmap_len(sbq_desc, maplen),
2158                                          PCI_DMA_FROMDEVICE);
2159                         dev_kfree_skb(sbq_desc->p.skb);
2160                         sbq_desc->p.skb = NULL;
2161                 }
2162                 if (sbq_desc->bq == NULL) {
2163                         QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
2164                                 i);
2165                         return;
2166                 }
2167                 sbq_desc->bq->addr_lo = 0;
2168                 sbq_desc->bq->addr_hi = 0;
2169         }
2170 }
2171
2172 /* Allocate and map an skb for each element of the sbq. */
2173 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2174                                 struct rx_ring *rx_ring)
2175 {
2176         int i;
2177         struct bq_desc *sbq_desc;
2178         struct sk_buff *skb;
2179         u64 map;
2180         struct bq_element *bq = rx_ring->sbq_base;
2181
2182         for (i = 0; i < rx_ring->sbq_len; i++) {
2183                 sbq_desc = &rx_ring->sbq[i];
2184                 memset(sbq_desc, 0, sizeof(sbq_desc));
2185                 sbq_desc->index = i;
2186                 sbq_desc->bq = bq;
2187                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2188                 if (unlikely(!skb)) {
2189                         /* Better luck next round */
2190                         QPRINTK(qdev, IFUP, ERR,
2191                                 "small buff alloc failed for %d bytes at index %d.\n",
2192                                 rx_ring->sbq_buf_size, i);
2193                         goto mem_err;
2194                 }
2195                 skb_reserve(skb, QLGE_SB_PAD);
2196                 sbq_desc->p.skb = skb;
2197                 /*
2198                  * Map only half the buffer. Because the
2199                  * other half may get some data copied to it
2200                  * when the completion arrives.
2201                  */
2202                 map = pci_map_single(qdev->pdev,
2203                                      skb->data,
2204                                      rx_ring->sbq_buf_size / 2,
2205                                      PCI_DMA_FROMDEVICE);
2206                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2207                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2208                         goto mem_err;
2209                 }
2210                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2211                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2212                 bq->addr_lo =   /*sbq_desc->addr_lo = */
2213                     cpu_to_le32(map);
2214                 bq->addr_hi =   /*sbq_desc->addr_hi = */
2215                     cpu_to_le32(map >> 32);
2216                 bq++;
2217         }
2218         return 0;
2219 mem_err:
2220         ql_free_sbq_buffers(qdev, rx_ring);
2221         return -ENOMEM;
2222 }
2223
2224 static void ql_free_rx_resources(struct ql_adapter *qdev,
2225                                  struct rx_ring *rx_ring)
2226 {
2227         if (rx_ring->sbq_len)
2228                 ql_free_sbq_buffers(qdev, rx_ring);
2229         if (rx_ring->lbq_len)
2230                 ql_free_lbq_buffers(qdev, rx_ring);
2231
2232         /* Free the small buffer queue. */
2233         if (rx_ring->sbq_base) {
2234                 pci_free_consistent(qdev->pdev,
2235                                     rx_ring->sbq_size,
2236                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2237                 rx_ring->sbq_base = NULL;
2238         }
2239
2240         /* Free the small buffer queue control blocks. */
2241         kfree(rx_ring->sbq);
2242         rx_ring->sbq = NULL;
2243
2244         /* Free the large buffer queue. */
2245         if (rx_ring->lbq_base) {
2246                 pci_free_consistent(qdev->pdev,
2247                                     rx_ring->lbq_size,
2248                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2249                 rx_ring->lbq_base = NULL;
2250         }
2251
2252         /* Free the large buffer queue control blocks. */
2253         kfree(rx_ring->lbq);
2254         rx_ring->lbq = NULL;
2255
2256         /* Free the rx queue. */
2257         if (rx_ring->cq_base) {
2258                 pci_free_consistent(qdev->pdev,
2259                                     rx_ring->cq_size,
2260                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2261                 rx_ring->cq_base = NULL;
2262         }
2263 }
2264
2265 /* Allocate queues and buffers for this completions queue based
2266  * on the values in the parameter structure. */
2267 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2268                                  struct rx_ring *rx_ring)
2269 {
2270
2271         /*
2272          * Allocate the completion queue for this rx_ring.
2273          */
2274         rx_ring->cq_base =
2275             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2276                                  &rx_ring->cq_base_dma);
2277
2278         if (rx_ring->cq_base == NULL) {
2279                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2280                 return -ENOMEM;
2281         }
2282
2283         if (rx_ring->sbq_len) {
2284                 /*
2285                  * Allocate small buffer queue.
2286                  */
2287                 rx_ring->sbq_base =
2288                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2289                                          &rx_ring->sbq_base_dma);
2290
2291                 if (rx_ring->sbq_base == NULL) {
2292                         QPRINTK(qdev, IFUP, ERR,
2293                                 "Small buffer queue allocation failed.\n");
2294                         goto err_mem;
2295                 }
2296
2297                 /*
2298                  * Allocate small buffer queue control blocks.
2299                  */
2300                 rx_ring->sbq =
2301                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2302                             GFP_KERNEL);
2303                 if (rx_ring->sbq == NULL) {
2304                         QPRINTK(qdev, IFUP, ERR,
2305                                 "Small buffer queue control block allocation failed.\n");
2306                         goto err_mem;
2307                 }
2308
2309                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2310                         QPRINTK(qdev, IFUP, ERR,
2311                                 "Small buffer allocation failed.\n");
2312                         goto err_mem;
2313                 }
2314         }
2315
2316         if (rx_ring->lbq_len) {
2317                 /*
2318                  * Allocate large buffer queue.
2319                  */
2320                 rx_ring->lbq_base =
2321                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2322                                          &rx_ring->lbq_base_dma);
2323
2324                 if (rx_ring->lbq_base == NULL) {
2325                         QPRINTK(qdev, IFUP, ERR,
2326                                 "Large buffer queue allocation failed.\n");
2327                         goto err_mem;
2328                 }
2329                 /*
2330                  * Allocate large buffer queue control blocks.
2331                  */
2332                 rx_ring->lbq =
2333                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2334                             GFP_KERNEL);
2335                 if (rx_ring->lbq == NULL) {
2336                         QPRINTK(qdev, IFUP, ERR,
2337                                 "Large buffer queue control block allocation failed.\n");
2338                         goto err_mem;
2339                 }
2340
2341                 /*
2342                  * Allocate the buffers.
2343                  */
2344                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2345                         QPRINTK(qdev, IFUP, ERR,
2346                                 "Large buffer allocation failed.\n");
2347                         goto err_mem;
2348                 }
2349         }
2350
2351         return 0;
2352
2353 err_mem:
2354         ql_free_rx_resources(qdev, rx_ring);
2355         return -ENOMEM;
2356 }
2357
2358 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2359 {
2360         struct tx_ring *tx_ring;
2361         struct tx_ring_desc *tx_ring_desc;
2362         int i, j;
2363
2364         /*
2365          * Loop through all queues and free
2366          * any resources.
2367          */
2368         for (j = 0; j < qdev->tx_ring_count; j++) {
2369                 tx_ring = &qdev->tx_ring[j];
2370                 for (i = 0; i < tx_ring->wq_len; i++) {
2371                         tx_ring_desc = &tx_ring->q[i];
2372                         if (tx_ring_desc && tx_ring_desc->skb) {
2373                                 QPRINTK(qdev, IFDOWN, ERR,
2374                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2375                                         tx_ring_desc->skb, j,
2376                                         tx_ring_desc->index);
2377                                 ql_unmap_send(qdev, tx_ring_desc,
2378                                               tx_ring_desc->map_cnt);
2379                                 dev_kfree_skb(tx_ring_desc->skb);
2380                                 tx_ring_desc->skb = NULL;
2381                         }
2382                 }
2383         }
2384 }
2385
2386 static void ql_free_ring_cb(struct ql_adapter *qdev)
2387 {
2388         kfree(qdev->ring_mem);
2389 }
2390
2391 static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2392 {
2393         /* Allocate space for tx/rx ring control blocks. */
2394         qdev->ring_mem_size =
2395             (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2396             (qdev->rx_ring_count * sizeof(struct rx_ring));
2397         qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2398         if (qdev->ring_mem == NULL) {
2399                 return -ENOMEM;
2400         } else {
2401                 qdev->rx_ring = qdev->ring_mem;
2402                 qdev->tx_ring = qdev->ring_mem +
2403                     (qdev->rx_ring_count * sizeof(struct rx_ring));
2404         }
2405         return 0;
2406 }
2407
2408 static void ql_free_mem_resources(struct ql_adapter *qdev)
2409 {
2410         int i;
2411
2412         for (i = 0; i < qdev->tx_ring_count; i++)
2413                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2414         for (i = 0; i < qdev->rx_ring_count; i++)
2415                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2416         ql_free_shadow_space(qdev);
2417 }
2418
2419 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2420 {
2421         int i;
2422
2423         /* Allocate space for our shadow registers and such. */
2424         if (ql_alloc_shadow_space(qdev))
2425                 return -ENOMEM;
2426
2427         for (i = 0; i < qdev->rx_ring_count; i++) {
2428                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2429                         QPRINTK(qdev, IFUP, ERR,
2430                                 "RX resource allocation failed.\n");
2431                         goto err_mem;
2432                 }
2433         }
2434         /* Allocate tx queue resources */
2435         for (i = 0; i < qdev->tx_ring_count; i++) {
2436                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2437                         QPRINTK(qdev, IFUP, ERR,
2438                                 "TX resource allocation failed.\n");
2439                         goto err_mem;
2440                 }
2441         }
2442         return 0;
2443
2444 err_mem:
2445         ql_free_mem_resources(qdev);
2446         return -ENOMEM;
2447 }
2448
2449 /* Set up the rx ring control block and pass it to the chip.
2450  * The control block is defined as
2451  * "Completion Queue Initialization Control Block", or cqicb.
2452  */
2453 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2454 {
2455         struct cqicb *cqicb = &rx_ring->cqicb;
2456         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2457             (rx_ring->cq_id * sizeof(u64) * 4);
2458         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2459             (rx_ring->cq_id * sizeof(u64) * 4);
2460         void __iomem *doorbell_area =
2461             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2462         int err = 0;
2463         u16 bq_len;
2464
2465         /* Set up the shadow registers for this ring. */
2466         rx_ring->prod_idx_sh_reg = shadow_reg;
2467         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2468         shadow_reg += sizeof(u64);
2469         shadow_reg_dma += sizeof(u64);
2470         rx_ring->lbq_base_indirect = shadow_reg;
2471         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2472         shadow_reg += sizeof(u64);
2473         shadow_reg_dma += sizeof(u64);
2474         rx_ring->sbq_base_indirect = shadow_reg;
2475         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2476
2477         /* PCI doorbell mem area + 0x00 for consumer index register */
2478         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2479         rx_ring->cnsmr_idx = 0;
2480         rx_ring->curr_entry = rx_ring->cq_base;
2481
2482         /* PCI doorbell mem area + 0x04 for valid register */
2483         rx_ring->valid_db_reg = doorbell_area + 0x04;
2484
2485         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2486         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2487
2488         /* PCI doorbell mem area + 0x1c */
2489         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2490
2491         memset((void *)cqicb, 0, sizeof(struct cqicb));
2492         cqicb->msix_vect = rx_ring->irq;
2493
2494         cqicb->len = cpu_to_le16(rx_ring->cq_len | LEN_V | LEN_CPP_CONT);
2495
2496         cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
2497         cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
2498
2499         cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma);
2500         cqicb->prod_idx_addr_hi =
2501             cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32);
2502
2503         /*
2504          * Set up the control block load flags.
2505          */
2506         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2507             FLAGS_LV |          /* Load MSI-X vector */
2508             FLAGS_LI;           /* Load irq delay values */
2509         if (rx_ring->lbq_len) {
2510                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2511                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2512                 cqicb->lbq_addr_lo =
2513                     cpu_to_le32(rx_ring->lbq_base_indirect_dma);
2514                 cqicb->lbq_addr_hi =
2515                     cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
2516                 cqicb->lbq_buf_size = cpu_to_le32(rx_ring->lbq_buf_size);
2517                 bq_len = (u16) rx_ring->lbq_len;
2518                 cqicb->lbq_len = cpu_to_le16(bq_len);
2519                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2520                 rx_ring->lbq_curr_idx = 0;
2521                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2522                 rx_ring->lbq_free_cnt = 16;
2523         }
2524         if (rx_ring->sbq_len) {
2525                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2526                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2527                 cqicb->sbq_addr_lo =
2528                     cpu_to_le32(rx_ring->sbq_base_indirect_dma);
2529                 cqicb->sbq_addr_hi =
2530                     cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
2531                 cqicb->sbq_buf_size =
2532                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2533                 bq_len = (u16) rx_ring->sbq_len;
2534                 cqicb->sbq_len = cpu_to_le16(bq_len);
2535                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2536                 rx_ring->sbq_curr_idx = 0;
2537                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2538                 rx_ring->sbq_free_cnt = 16;
2539         }
2540         switch (rx_ring->type) {
2541         case TX_Q:
2542                 /* If there's only one interrupt, then we use
2543                  * worker threads to process the outbound
2544                  * completion handling rx_rings. We do this so
2545                  * they can be run on multiple CPUs. There is
2546                  * room to play with this more where we would only
2547                  * run in a worker if there are more than x number
2548                  * of outbound completions on the queue and more
2549                  * than one queue active.  Some threshold that
2550                  * would indicate a benefit in spite of the cost
2551                  * of a context switch.
2552                  * If there's more than one interrupt, then the
2553                  * outbound completions are processed in the ISR.
2554                  */
2555                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2556                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2557                 else {
2558                         /* With all debug warnings on we see a WARN_ON message
2559                          * when we free the skb in the interrupt context.
2560                          */
2561                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2562                 }
2563                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2564                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2565                 break;
2566         case DEFAULT_Q:
2567                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2568                 cqicb->irq_delay = 0;
2569                 cqicb->pkt_delay = 0;
2570                 break;
2571         case RX_Q:
2572                 /* Inbound completion handling rx_rings run in
2573                  * separate NAPI contexts.
2574                  */
2575                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2576                                64);
2577                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2578                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2579                 break;
2580         default:
2581                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2582                         rx_ring->type);
2583         }
2584         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2585         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2586                            CFG_LCQ, rx_ring->cq_id);
2587         if (err) {
2588                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2589                 return err;
2590         }
2591         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2592         /*
2593          * Advance the producer index for the buffer queues.
2594          */
2595         wmb();
2596         if (rx_ring->lbq_len)
2597                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2598                                 rx_ring->lbq_prod_idx_db_reg);
2599         if (rx_ring->sbq_len)
2600                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2601                                 rx_ring->sbq_prod_idx_db_reg);
2602         return err;
2603 }
2604
2605 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2606 {
2607         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2608         void __iomem *doorbell_area =
2609             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2610         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2611             (tx_ring->wq_id * sizeof(u64));
2612         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2613             (tx_ring->wq_id * sizeof(u64));
2614         int err = 0;
2615
2616         /*
2617          * Assign doorbell registers for this tx_ring.
2618          */
2619         /* TX PCI doorbell mem area for tx producer index */
2620         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2621         tx_ring->prod_idx = 0;
2622         /* TX PCI doorbell mem area + 0x04 */
2623         tx_ring->valid_db_reg = doorbell_area + 0x04;
2624
2625         /*
2626          * Assign shadow registers for this tx_ring.
2627          */
2628         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2629         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2630
2631         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2632         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2633                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2634         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2635         wqicb->rid = 0;
2636         wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma);
2637         wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32);
2638
2639         wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma);
2640         wqicb->cnsmr_idx_addr_hi =
2641             cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32);
2642
2643         ql_init_tx_ring(qdev, tx_ring);
2644
2645         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2646                            (u16) tx_ring->wq_id);
2647         if (err) {
2648                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2649                 return err;
2650         }
2651         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2652         return err;
2653 }
2654
2655 static void ql_disable_msix(struct ql_adapter *qdev)
2656 {
2657         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2658                 pci_disable_msix(qdev->pdev);
2659                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2660                 kfree(qdev->msi_x_entry);
2661                 qdev->msi_x_entry = NULL;
2662         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2663                 pci_disable_msi(qdev->pdev);
2664                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2665         }
2666 }
2667
2668 static void ql_enable_msix(struct ql_adapter *qdev)
2669 {
2670         int i;
2671
2672         qdev->intr_count = 1;
2673         /* Get the MSIX vectors. */
2674         if (irq_type == MSIX_IRQ) {
2675                 /* Try to alloc space for the msix struct,
2676                  * if it fails then go to MSI/legacy.
2677                  */
2678                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2679                                             sizeof(struct msix_entry),
2680                                             GFP_KERNEL);
2681                 if (!qdev->msi_x_entry) {
2682                         irq_type = MSI_IRQ;
2683                         goto msi;
2684                 }
2685
2686                 for (i = 0; i < qdev->rx_ring_count; i++)
2687                         qdev->msi_x_entry[i].entry = i;
2688
2689                 if (!pci_enable_msix
2690                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2691                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2692                         qdev->intr_count = qdev->rx_ring_count;
2693                         QPRINTK(qdev, IFUP, INFO,
2694                                 "MSI-X Enabled, got %d vectors.\n",
2695                                 qdev->intr_count);
2696                         return;
2697                 } else {
2698                         kfree(qdev->msi_x_entry);
2699                         qdev->msi_x_entry = NULL;
2700                         QPRINTK(qdev, IFUP, WARNING,
2701                                 "MSI-X Enable failed, trying MSI.\n");
2702                         irq_type = MSI_IRQ;
2703                 }
2704         }
2705 msi:
2706         if (irq_type == MSI_IRQ) {
2707                 if (!pci_enable_msi(qdev->pdev)) {
2708                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2709                         QPRINTK(qdev, IFUP, INFO,
2710                                 "Running with MSI interrupts.\n");
2711                         return;
2712                 }
2713         }
2714         irq_type = LEG_IRQ;
2715         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2716 }
2717
2718 /*
2719  * Here we build the intr_context structures based on
2720  * our rx_ring count and intr vector count.
2721  * The intr_context structure is used to hook each vector
2722  * to possibly different handlers.
2723  */
2724 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2725 {
2726         int i = 0;
2727         struct intr_context *intr_context = &qdev->intr_context[0];
2728
2729         ql_enable_msix(qdev);
2730
2731         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2732                 /* Each rx_ring has it's
2733                  * own intr_context since we have separate
2734                  * vectors for each queue.
2735                  * This only true when MSI-X is enabled.
2736                  */
2737                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2738                         qdev->rx_ring[i].irq = i;
2739                         intr_context->intr = i;
2740                         intr_context->qdev = qdev;
2741                         /*
2742                          * We set up each vectors enable/disable/read bits so
2743                          * there's no bit/mask calculations in the critical path.
2744                          */
2745                         intr_context->intr_en_mask =
2746                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2747                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2748                             | i;
2749                         intr_context->intr_dis_mask =
2750                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2751                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2752                             INTR_EN_IHD | i;
2753                         intr_context->intr_read_mask =
2754                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2755                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2756                             i;
2757
2758                         if (i == 0) {
2759                                 /*
2760                                  * Default queue handles bcast/mcast plus
2761                                  * async events.  Needs buffers.
2762                                  */
2763                                 intr_context->handler = qlge_isr;
2764                                 sprintf(intr_context->name, "%s-default-queue",
2765                                         qdev->ndev->name);
2766                         } else if (i < qdev->rss_ring_first_cq_id) {
2767                                 /*
2768                                  * Outbound queue is for outbound completions only.
2769                                  */
2770                                 intr_context->handler = qlge_msix_tx_isr;
2771                                 sprintf(intr_context->name, "%s-txq-%d",
2772                                         qdev->ndev->name, i);
2773                         } else {
2774                                 /*
2775                                  * Inbound queues handle unicast frames only.
2776                                  */
2777                                 intr_context->handler = qlge_msix_rx_isr;
2778                                 sprintf(intr_context->name, "%s-rxq-%d",
2779                                         qdev->ndev->name, i);
2780                         }
2781                 }
2782         } else {
2783                 /*
2784                  * All rx_rings use the same intr_context since
2785                  * there is only one vector.
2786                  */
2787                 intr_context->intr = 0;
2788                 intr_context->qdev = qdev;
2789                 /*
2790                  * We set up each vectors enable/disable/read bits so
2791                  * there's no bit/mask calculations in the critical path.
2792                  */
2793                 intr_context->intr_en_mask =
2794                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2795                 intr_context->intr_dis_mask =
2796                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2797                     INTR_EN_TYPE_DISABLE;
2798                 intr_context->intr_read_mask =
2799                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2800                 /*
2801                  * Single interrupt means one handler for all rings.
2802                  */
2803                 intr_context->handler = qlge_isr;
2804                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2805                 for (i = 0; i < qdev->rx_ring_count; i++)
2806                         qdev->rx_ring[i].irq = 0;
2807         }
2808 }
2809
2810 static void ql_free_irq(struct ql_adapter *qdev)
2811 {
2812         int i;
2813         struct intr_context *intr_context = &qdev->intr_context[0];
2814
2815         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2816                 if (intr_context->hooked) {
2817                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2818                                 free_irq(qdev->msi_x_entry[i].vector,
2819                                          &qdev->rx_ring[i]);
2820                                 QPRINTK(qdev, IFDOWN, ERR,
2821                                         "freeing msix interrupt %d.\n", i);
2822                         } else {
2823                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2824                                 QPRINTK(qdev, IFDOWN, ERR,
2825                                         "freeing msi interrupt %d.\n", i);
2826                         }
2827                 }
2828         }
2829         ql_disable_msix(qdev);
2830 }
2831
2832 static int ql_request_irq(struct ql_adapter *qdev)
2833 {
2834         int i;
2835         int status = 0;
2836         struct pci_dev *pdev = qdev->pdev;
2837         struct intr_context *intr_context = &qdev->intr_context[0];
2838
2839         ql_resolve_queues_to_irqs(qdev);
2840
2841         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2842                 atomic_set(&intr_context->irq_cnt, 0);
2843                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2844                         status = request_irq(qdev->msi_x_entry[i].vector,
2845                                              intr_context->handler,
2846                                              0,
2847                                              intr_context->name,
2848                                              &qdev->rx_ring[i]);
2849                         if (status) {
2850                                 QPRINTK(qdev, IFUP, ERR,
2851                                         "Failed request for MSIX interrupt %d.\n",
2852                                         i);
2853                                 goto err_irq;
2854                         } else {
2855                                 QPRINTK(qdev, IFUP, INFO,
2856                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2857                                         i,
2858                                         qdev->rx_ring[i].type ==
2859                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2860                                         qdev->rx_ring[i].type ==
2861                                         TX_Q ? "TX_Q" : "",
2862                                         qdev->rx_ring[i].type ==
2863                                         RX_Q ? "RX_Q" : "", intr_context->name);
2864                         }
2865                 } else {
2866                         QPRINTK(qdev, IFUP, DEBUG,
2867                                 "trying msi or legacy interrupts.\n");
2868                         QPRINTK(qdev, IFUP, DEBUG,
2869                                 "%s: irq = %d.\n", __func__, pdev->irq);
2870                         QPRINTK(qdev, IFUP, DEBUG,
2871                                 "%s: context->name = %s.\n", __func__,
2872                                intr_context->name);
2873                         QPRINTK(qdev, IFUP, DEBUG,
2874                                 "%s: dev_id = 0x%p.\n", __func__,
2875                                &qdev->rx_ring[0]);
2876                         status =
2877                             request_irq(pdev->irq, qlge_isr,
2878                                         test_bit(QL_MSI_ENABLED,
2879                                                  &qdev->
2880                                                  flags) ? 0 : IRQF_SHARED,
2881                                         intr_context->name, &qdev->rx_ring[0]);
2882                         if (status)
2883                                 goto err_irq;
2884
2885                         QPRINTK(qdev, IFUP, ERR,
2886                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2887                                 i,
2888                                 qdev->rx_ring[0].type ==
2889                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2890                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2891                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2892                                 intr_context->name);
2893                 }
2894                 intr_context->hooked = 1;
2895         }
2896         return status;
2897 err_irq:
2898         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2899         ql_free_irq(qdev);
2900         return status;
2901 }
2902
2903 static int ql_start_rss(struct ql_adapter *qdev)
2904 {
2905         struct ricb *ricb = &qdev->ricb;
2906         int status = 0;
2907         int i;
2908         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2909
2910         memset((void *)ricb, 0, sizeof(ricb));
2911
2912         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2913         ricb->flags =
2914             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2915              RSS_RT6);
2916         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2917
2918         /*
2919          * Fill out the Indirection Table.
2920          */
2921         for (i = 0; i < 32; i++)
2922                 hash_id[i] = i & 1;
2923
2924         /*
2925          * Random values for the IPv6 and IPv4 Hash Keys.
2926          */
2927         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2928         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2929
2930         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2931
2932         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2933         if (status) {
2934                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2935                 return status;
2936         }
2937         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2938         return status;
2939 }
2940
2941 /* Initialize the frame-to-queue routing. */
2942 static int ql_route_initialize(struct ql_adapter *qdev)
2943 {
2944         int status = 0;
2945         int i;
2946
2947         /* Clear all the entries in the routing table. */
2948         for (i = 0; i < 16; i++) {
2949                 status = ql_set_routing_reg(qdev, i, 0, 0);
2950                 if (status) {
2951                         QPRINTK(qdev, IFUP, ERR,
2952                                 "Failed to init routing register for CAM packets.\n");
2953                         return status;
2954                 }
2955         }
2956
2957         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2958         if (status) {
2959                 QPRINTK(qdev, IFUP, ERR,
2960                         "Failed to init routing register for error packets.\n");
2961                 return status;
2962         }
2963         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2964         if (status) {
2965                 QPRINTK(qdev, IFUP, ERR,
2966                         "Failed to init routing register for broadcast packets.\n");
2967                 return status;
2968         }
2969         /* If we have more than one inbound queue, then turn on RSS in the
2970          * routing block.
2971          */
2972         if (qdev->rss_ring_count > 1) {
2973                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2974                                         RT_IDX_RSS_MATCH, 1);
2975                 if (status) {
2976                         QPRINTK(qdev, IFUP, ERR,
2977                                 "Failed to init routing register for MATCH RSS packets.\n");
2978                         return status;
2979                 }
2980         }
2981
2982         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2983                                     RT_IDX_CAM_HIT, 1);
2984         if (status) {
2985                 QPRINTK(qdev, IFUP, ERR,
2986                         "Failed to init routing register for CAM packets.\n");
2987                 return status;
2988         }
2989         return status;
2990 }
2991
2992 static int ql_adapter_initialize(struct ql_adapter *qdev)
2993 {
2994         u32 value, mask;
2995         int i;
2996         int status = 0;
2997
2998         /*
2999          * Set up the System register to halt on errors.
3000          */
3001         value = SYS_EFE | SYS_FAE;
3002         mask = value << 16;
3003         ql_write32(qdev, SYS, mask | value);
3004
3005         /* Set the default queue. */
3006         value = NIC_RCV_CFG_DFQ;
3007         mask = NIC_RCV_CFG_DFQ_MASK;
3008         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3009
3010         /* Set the MPI interrupt to enabled. */
3011         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3012
3013         /* Enable the function, set pagesize, enable error checking. */
3014         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3015             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3016
3017         /* Set/clear header splitting. */
3018         mask = FSC_VM_PAGESIZE_MASK |
3019             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3020         ql_write32(qdev, FSC, mask | value);
3021
3022         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3023                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3024
3025         /* Start up the rx queues. */
3026         for (i = 0; i < qdev->rx_ring_count; i++) {
3027                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3028                 if (status) {
3029                         QPRINTK(qdev, IFUP, ERR,
3030                                 "Failed to start rx ring[%d].\n", i);
3031                         return status;
3032                 }
3033         }
3034
3035         /* If there is more than one inbound completion queue
3036          * then download a RICB to configure RSS.
3037          */
3038         if (qdev->rss_ring_count > 1) {
3039                 status = ql_start_rss(qdev);
3040                 if (status) {
3041                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3042                         return status;
3043                 }
3044         }
3045
3046         /* Start up the tx queues. */
3047         for (i = 0; i < qdev->tx_ring_count; i++) {
3048                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3049                 if (status) {
3050                         QPRINTK(qdev, IFUP, ERR,
3051                                 "Failed to start tx ring[%d].\n", i);
3052                         return status;
3053                 }
3054         }
3055
3056         status = ql_port_initialize(qdev);
3057         if (status) {
3058                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3059                 return status;
3060         }
3061
3062         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3063                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3064         if (status) {
3065                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3066                 return status;
3067         }
3068
3069         status = ql_route_initialize(qdev);
3070         if (status) {
3071                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3072                 return status;
3073         }
3074
3075         /* Start NAPI for the RSS queues. */
3076         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3077                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3078                         i);
3079                 napi_enable(&qdev->rx_ring[i].napi);
3080         }
3081
3082         return status;
3083 }
3084
3085 /* Issue soft reset to chip. */
3086 static int ql_adapter_reset(struct ql_adapter *qdev)
3087 {
3088         u32 value;
3089         int max_wait_time;
3090         int status = 0;
3091         int resetCnt = 0;
3092
3093 #define MAX_RESET_CNT   1
3094 issueReset:
3095         resetCnt++;
3096         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3097         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3098         /* Wait for reset to complete. */
3099         max_wait_time = 3;
3100         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3101                 max_wait_time);
3102         do {
3103                 value = ql_read32(qdev, RST_FO);
3104                 if ((value & RST_FO_FR) == 0)
3105                         break;
3106
3107                 ssleep(1);
3108         } while ((--max_wait_time));
3109         if (value & RST_FO_FR) {
3110                 QPRINTK(qdev, IFDOWN, ERR,
3111                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3112                 if (resetCnt < MAX_RESET_CNT)
3113                         goto issueReset;
3114         }
3115         if (max_wait_time == 0) {
3116                 status = -ETIMEDOUT;
3117                 QPRINTK(qdev, IFDOWN, ERR,
3118                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3119         }
3120
3121         return status;
3122 }
3123
3124 static void ql_display_dev_info(struct net_device *ndev)
3125 {
3126         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3127
3128         QPRINTK(qdev, PROBE, INFO,
3129                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3130                 "XG Roll = %d, XG Rev = %d.\n",
3131                 qdev->func,
3132                 qdev->chip_rev_id & 0x0000000f,
3133                 qdev->chip_rev_id >> 4 & 0x0000000f,
3134                 qdev->chip_rev_id >> 8 & 0x0000000f,
3135                 qdev->chip_rev_id >> 12 & 0x0000000f);
3136         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3137 }
3138
3139 static int ql_adapter_down(struct ql_adapter *qdev)
3140 {
3141         struct net_device *ndev = qdev->ndev;
3142         int i, status = 0;
3143         struct rx_ring *rx_ring;
3144
3145         netif_stop_queue(ndev);
3146         netif_carrier_off(ndev);
3147
3148         cancel_delayed_work_sync(&qdev->asic_reset_work);
3149         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3150         cancel_delayed_work_sync(&qdev->mpi_work);
3151
3152         /* The default queue at index 0 is always processed in
3153          * a workqueue.
3154          */
3155         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3156
3157         /* The rest of the rx_rings are processed in
3158          * a workqueue only if it's a single interrupt
3159          * environment (MSI/Legacy).
3160          */
3161         for (i = 1; i < qdev->rx_ring_count; i++) {
3162                 rx_ring = &qdev->rx_ring[i];
3163                 /* Only the RSS rings use NAPI on multi irq
3164                  * environment.  Outbound completion processing
3165                  * is done in interrupt context.
3166                  */
3167                 if (i >= qdev->rss_ring_first_cq_id) {
3168                         napi_disable(&rx_ring->napi);
3169                 } else {
3170                         cancel_delayed_work_sync(&rx_ring->rx_work);
3171                 }
3172         }
3173
3174         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3175
3176         ql_disable_interrupts(qdev);
3177
3178         ql_tx_ring_clean(qdev);
3179
3180         spin_lock(&qdev->hw_lock);
3181         status = ql_adapter_reset(qdev);
3182         if (status)
3183                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3184                         qdev->func);
3185         spin_unlock(&qdev->hw_lock);
3186         return status;
3187 }
3188
3189 static int ql_adapter_up(struct ql_adapter *qdev)
3190 {
3191         int err = 0;
3192
3193         spin_lock(&qdev->hw_lock);
3194         err = ql_adapter_initialize(qdev);
3195         if (err) {
3196                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3197                 spin_unlock(&qdev->hw_lock);
3198                 goto err_init;
3199         }
3200         spin_unlock(&qdev->hw_lock);
3201         set_bit(QL_ADAPTER_UP, &qdev->flags);
3202         ql_enable_interrupts(qdev);
3203         ql_enable_all_completion_interrupts(qdev);
3204         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3205                 netif_carrier_on(qdev->ndev);
3206                 netif_start_queue(qdev->ndev);
3207         }
3208
3209         return 0;
3210 err_init:
3211         ql_adapter_reset(qdev);
3212         return err;
3213 }
3214
3215 static int ql_cycle_adapter(struct ql_adapter *qdev)
3216 {
3217         int status;
3218
3219         status = ql_adapter_down(qdev);
3220         if (status)
3221                 goto error;
3222
3223         status = ql_adapter_up(qdev);
3224         if (status)
3225                 goto error;
3226
3227         return status;
3228 error:
3229         QPRINTK(qdev, IFUP, ALERT,
3230                 "Driver up/down cycle failed, closing device\n");
3231         rtnl_lock();
3232         dev_close(qdev->ndev);
3233         rtnl_unlock();
3234         return status;
3235 }
3236
3237 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3238 {
3239         ql_free_mem_resources(qdev);
3240         ql_free_irq(qdev);
3241 }
3242
3243 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3244 {
3245         int status = 0;
3246
3247         if (ql_alloc_mem_resources(qdev)) {
3248                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3249                 return -ENOMEM;
3250         }
3251         status = ql_request_irq(qdev);
3252         if (status)
3253                 goto err_irq;
3254         return status;
3255 err_irq:
3256         ql_free_mem_resources(qdev);
3257         return status;
3258 }
3259
3260 static int qlge_close(struct net_device *ndev)
3261 {
3262         struct ql_adapter *qdev = netdev_priv(ndev);
3263
3264         /*
3265          * Wait for device to recover from a reset.
3266          * (Rarely happens, but possible.)
3267          */
3268         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3269                 msleep(1);
3270         ql_adapter_down(qdev);
3271         ql_release_adapter_resources(qdev);
3272         ql_free_ring_cb(qdev);
3273         return 0;
3274 }
3275
3276 static int ql_configure_rings(struct ql_adapter *qdev)
3277 {
3278         int i;
3279         struct rx_ring *rx_ring;
3280         struct tx_ring *tx_ring;
3281         int cpu_cnt = num_online_cpus();
3282
3283         /*
3284          * For each processor present we allocate one
3285          * rx_ring for outbound completions, and one
3286          * rx_ring for inbound completions.  Plus there is
3287          * always the one default queue.  For the CPU
3288          * counts we end up with the following rx_rings:
3289          * rx_ring count =
3290          *  one default queue +
3291          *  (CPU count * outbound completion rx_ring) +
3292          *  (CPU count * inbound (RSS) completion rx_ring)
3293          * To keep it simple we limit the total number of
3294          * queues to < 32, so we truncate CPU to 8.
3295          * This limitation can be removed when requested.
3296          */
3297
3298         if (cpu_cnt > 8)
3299                 cpu_cnt = 8;
3300
3301         /*
3302          * rx_ring[0] is always the default queue.
3303          */
3304         /* Allocate outbound completion ring for each CPU. */
3305         qdev->tx_ring_count = cpu_cnt;
3306         /* Allocate inbound completion (RSS) ring for each CPU. */
3307         qdev->rss_ring_count = cpu_cnt;
3308         /* cq_id for the first inbound ring handler. */
3309         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3310         /*
3311          * qdev->rx_ring_count:
3312          * Total number of rx_rings.  This includes the one
3313          * default queue, a number of outbound completion
3314          * handler rx_rings, and the number of inbound
3315          * completion handler rx_rings.
3316          */
3317         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3318
3319         if (ql_alloc_ring_cb(qdev))
3320                 return -ENOMEM;
3321
3322         for (i = 0; i < qdev->tx_ring_count; i++) {
3323                 tx_ring = &qdev->tx_ring[i];
3324                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3325                 tx_ring->qdev = qdev;
3326                 tx_ring->wq_id = i;
3327                 tx_ring->wq_len = qdev->tx_ring_size;
3328                 tx_ring->wq_size =
3329                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3330
3331                 /*
3332                  * The completion queue ID for the tx rings start
3333                  * immediately after the default Q ID, which is zero.
3334                  */
3335                 tx_ring->cq_id = i + 1;
3336         }
3337
3338         for (i = 0; i < qdev->rx_ring_count; i++) {
3339                 rx_ring = &qdev->rx_ring[i];
3340                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3341                 rx_ring->qdev = qdev;
3342                 rx_ring->cq_id = i;
3343                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3344                 if (i == 0) {   /* Default queue at index 0. */
3345                         /*
3346                          * Default queue handles bcast/mcast plus
3347                          * async events.  Needs buffers.
3348                          */
3349                         rx_ring->cq_len = qdev->rx_ring_size;
3350                         rx_ring->cq_size =
3351                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3352                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3353                         rx_ring->lbq_size =
3354                             rx_ring->lbq_len * sizeof(struct bq_element);
3355                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3356                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3357                         rx_ring->sbq_size =
3358                             rx_ring->sbq_len * sizeof(struct bq_element);
3359                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3360                         rx_ring->type = DEFAULT_Q;
3361                 } else if (i < qdev->rss_ring_first_cq_id) {
3362                         /*
3363                          * Outbound queue handles outbound completions only.
3364                          */
3365                         /* outbound cq is same size as tx_ring it services. */
3366                         rx_ring->cq_len = qdev->tx_ring_size;
3367                         rx_ring->cq_size =
3368                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3369                         rx_ring->lbq_len = 0;
3370                         rx_ring->lbq_size = 0;
3371                         rx_ring->lbq_buf_size = 0;
3372                         rx_ring->sbq_len = 0;
3373                         rx_ring->sbq_size = 0;
3374                         rx_ring->sbq_buf_size = 0;
3375                         rx_ring->type = TX_Q;
3376                 } else {        /* Inbound completions (RSS) queues */
3377                         /*
3378                          * Inbound queues handle unicast frames only.
3379                          */
3380                         rx_ring->cq_len = qdev->rx_ring_size;
3381                         rx_ring->cq_size =
3382                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3383                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3384                         rx_ring->lbq_size =
3385                             rx_ring->lbq_len * sizeof(struct bq_element);
3386                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3387                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3388                         rx_ring->sbq_size =
3389                             rx_ring->sbq_len * sizeof(struct bq_element);
3390                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3391                         rx_ring->type = RX_Q;
3392                 }
3393         }
3394         return 0;
3395 }
3396
3397 static int qlge_open(struct net_device *ndev)
3398 {
3399         int err = 0;
3400         struct ql_adapter *qdev = netdev_priv(ndev);
3401
3402         err = ql_configure_rings(qdev);
3403         if (err)
3404                 return err;
3405
3406         err = ql_get_adapter_resources(qdev);
3407         if (err)
3408                 goto error_up;
3409
3410         err = ql_adapter_up(qdev);
3411         if (err)
3412                 goto error_up;
3413
3414         return err;
3415
3416 error_up:
3417         ql_release_adapter_resources(qdev);
3418         ql_free_ring_cb(qdev);
3419         return err;
3420 }
3421
3422 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3423 {
3424         struct ql_adapter *qdev = netdev_priv(ndev);
3425
3426         if (ndev->mtu == 1500 && new_mtu == 9000) {
3427                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3428         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3429                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3430         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3431                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3432                 return 0;
3433         } else
3434                 return -EINVAL;
3435         ndev->mtu = new_mtu;
3436         return 0;
3437 }
3438
3439 static struct net_device_stats *qlge_get_stats(struct net_device
3440                                                *ndev)
3441 {
3442         struct ql_adapter *qdev = netdev_priv(ndev);
3443         return &qdev->stats;
3444 }
3445
3446 static void qlge_set_multicast_list(struct net_device *ndev)
3447 {
3448         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3449         struct dev_mc_list *mc_ptr;
3450         int i;
3451
3452         spin_lock(&qdev->hw_lock);
3453         /*
3454          * Set or clear promiscuous mode if a
3455          * transition is taking place.
3456          */
3457         if (ndev->flags & IFF_PROMISC) {
3458                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3459                         if (ql_set_routing_reg
3460                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3461                                 QPRINTK(qdev, HW, ERR,
3462                                         "Failed to set promiscous mode.\n");
3463                         } else {
3464                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3465                         }
3466                 }
3467         } else {
3468                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3469                         if (ql_set_routing_reg
3470                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3471                                 QPRINTK(qdev, HW, ERR,
3472                                         "Failed to clear promiscous mode.\n");
3473                         } else {
3474                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3475                         }
3476                 }
3477         }
3478
3479         /*
3480          * Set or clear all multicast mode if a
3481          * transition is taking place.
3482          */
3483         if ((ndev->flags & IFF_ALLMULTI) ||
3484             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3485                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3486                         if (ql_set_routing_reg
3487                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3488                                 QPRINTK(qdev, HW, ERR,
3489                                         "Failed to set all-multi mode.\n");
3490                         } else {
3491                                 set_bit(QL_ALLMULTI, &qdev->flags);
3492                         }
3493                 }
3494         } else {
3495                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3496                         if (ql_set_routing_reg
3497                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3498                                 QPRINTK(qdev, HW, ERR,
3499                                         "Failed to clear all-multi mode.\n");
3500                         } else {
3501                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3502                         }
3503                 }
3504         }
3505
3506         if (ndev->mc_count) {
3507                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3508                      i++, mc_ptr = mc_ptr->next)
3509                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3510                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3511                                 QPRINTK(qdev, HW, ERR,
3512                                         "Failed to loadmulticast address.\n");
3513                                 goto exit;
3514                         }
3515                 if (ql_set_routing_reg
3516                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3517                         QPRINTK(qdev, HW, ERR,
3518                                 "Failed to set multicast match mode.\n");
3519                 } else {
3520                         set_bit(QL_ALLMULTI, &qdev->flags);
3521                 }
3522         }
3523 exit:
3524         spin_unlock(&qdev->hw_lock);
3525 }
3526
3527 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3528 {
3529         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3530         struct sockaddr *addr = p;
3531         int ret = 0;
3532
3533         if (netif_running(ndev))
3534                 return -EBUSY;
3535
3536         if (!is_valid_ether_addr(addr->sa_data))
3537                 return -EADDRNOTAVAIL;
3538         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3539
3540         spin_lock(&qdev->hw_lock);
3541         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3542                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3543                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3544                 ret = -1;
3545         }
3546         spin_unlock(&qdev->hw_lock);
3547
3548         return ret;
3549 }
3550
3551 static void qlge_tx_timeout(struct net_device *ndev)
3552 {
3553         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3554         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3555 }
3556
3557 static void ql_asic_reset_work(struct work_struct *work)
3558 {
3559         struct ql_adapter *qdev =
3560             container_of(work, struct ql_adapter, asic_reset_work.work);
3561         ql_cycle_adapter(qdev);
3562 }
3563
3564 static void ql_get_board_info(struct ql_adapter *qdev)
3565 {
3566         qdev->func =
3567             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3568         if (qdev->func) {
3569                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3570                 qdev->port_link_up = STS_PL1;
3571                 qdev->port_init = STS_PI1;
3572                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3573                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3574         } else {
3575                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3576                 qdev->port_link_up = STS_PL0;
3577                 qdev->port_init = STS_PI0;
3578                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3579                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3580         }
3581         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3582 }
3583
3584 static void ql_release_all(struct pci_dev *pdev)
3585 {
3586         struct net_device *ndev = pci_get_drvdata(pdev);
3587         struct ql_adapter *qdev = netdev_priv(ndev);
3588
3589         if (qdev->workqueue) {
3590                 destroy_workqueue(qdev->workqueue);
3591                 qdev->workqueue = NULL;
3592         }
3593         if (qdev->q_workqueue) {
3594                 destroy_workqueue(qdev->q_workqueue);
3595                 qdev->q_workqueue = NULL;
3596         }
3597         if (qdev->reg_base)
3598                 iounmap(qdev->reg_base);
3599         if (qdev->doorbell_area)
3600                 iounmap(qdev->doorbell_area);
3601         pci_release_regions(pdev);
3602         pci_set_drvdata(pdev, NULL);
3603 }
3604
3605 static int __devinit ql_init_device(struct pci_dev *pdev,
3606                                     struct net_device *ndev, int cards_found)
3607 {
3608         struct ql_adapter *qdev = netdev_priv(ndev);
3609         int pos, err = 0;
3610         u16 val16;
3611
3612         memset((void *)qdev, 0, sizeof(qdev));
3613         err = pci_enable_device(pdev);
3614         if (err) {
3615                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3616                 return err;
3617         }
3618
3619         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3620         if (pos <= 0) {
3621                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3622                         "aborting.\n");
3623                 goto err_out;
3624         } else {
3625                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3626                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3627                 val16 |= (PCI_EXP_DEVCTL_CERE |
3628                           PCI_EXP_DEVCTL_NFERE |
3629                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3630                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3631         }
3632
3633         err = pci_request_regions(pdev, DRV_NAME);
3634         if (err) {
3635                 dev_err(&pdev->dev, "PCI region request failed.\n");
3636                 goto err_out;
3637         }
3638
3639         pci_set_master(pdev);
3640         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3641                 set_bit(QL_DMA64, &qdev->flags);
3642                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3643         } else {
3644                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3645                 if (!err)
3646                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3647         }
3648
3649         if (err) {
3650                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3651                 goto err_out;
3652         }
3653
3654         pci_set_drvdata(pdev, ndev);
3655         qdev->reg_base =
3656             ioremap_nocache(pci_resource_start(pdev, 1),
3657                             pci_resource_len(pdev, 1));
3658         if (!qdev->reg_base) {
3659                 dev_err(&pdev->dev, "Register mapping failed.\n");
3660                 err = -ENOMEM;
3661                 goto err_out;
3662         }
3663
3664         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3665         qdev->doorbell_area =
3666             ioremap_nocache(pci_resource_start(pdev, 3),
3667                             pci_resource_len(pdev, 3));
3668         if (!qdev->doorbell_area) {
3669                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3670                 err = -ENOMEM;
3671                 goto err_out;
3672         }
3673
3674         ql_get_board_info(qdev);
3675         qdev->ndev = ndev;
3676         qdev->pdev = pdev;
3677         qdev->msg_enable = netif_msg_init(debug, default_msg);
3678         spin_lock_init(&qdev->hw_lock);
3679         spin_lock_init(&qdev->stats_lock);
3680
3681         /* make sure the EEPROM is good */
3682         err = ql_get_flash_params(qdev);
3683         if (err) {
3684                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3685                 goto err_out;
3686         }
3687
3688         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3689                 goto err_out;
3690
3691         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3692         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3693
3694         /* Set up the default ring sizes. */
3695         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3696         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3697
3698         /* Set up the coalescing parameters. */
3699         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3700         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3701         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3702         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3703
3704         /*
3705          * Set up the operating parameters.
3706          */
3707         qdev->rx_csum = 1;
3708
3709         qdev->q_workqueue = create_workqueue(ndev->name);
3710         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3711         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3712         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3713         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3714
3715         if (!cards_found) {
3716                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3717                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3718                          DRV_NAME, DRV_VERSION);
3719         }
3720         return 0;
3721 err_out:
3722         ql_release_all(pdev);
3723         pci_disable_device(pdev);
3724         return err;
3725 }
3726
3727
3728 static const struct net_device_ops qlge_netdev_ops = {
3729         .ndo_open               = qlge_open,
3730         .ndo_stop               = qlge_close,
3731         .ndo_start_xmit         = qlge_send,
3732         .ndo_change_mtu         = qlge_change_mtu,
3733         .ndo_get_stats          = qlge_get_stats,
3734         .ndo_set_multicast_list = qlge_set_multicast_list,
3735         .ndo_set_mac_address    = qlge_set_mac_address,
3736         .ndo_validate_addr      = eth_validate_addr,
3737         .ndo_tx_timeout         = qlge_tx_timeout,
3738         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3739         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3740         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3741 };
3742
3743 static int __devinit qlge_probe(struct pci_dev *pdev,
3744                                 const struct pci_device_id *pci_entry)
3745 {
3746         struct net_device *ndev = NULL;
3747         struct ql_adapter *qdev = NULL;
3748         static int cards_found = 0;
3749         int err = 0;
3750
3751         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3752         if (!ndev)
3753                 return -ENOMEM;
3754
3755         err = ql_init_device(pdev, ndev, cards_found);
3756         if (err < 0) {
3757                 free_netdev(ndev);
3758                 return err;
3759         }
3760
3761         qdev = netdev_priv(ndev);
3762         SET_NETDEV_DEV(ndev, &pdev->dev);
3763         ndev->features = (0
3764                           | NETIF_F_IP_CSUM
3765                           | NETIF_F_SG
3766                           | NETIF_F_TSO
3767                           | NETIF_F_TSO6
3768                           | NETIF_F_TSO_ECN
3769                           | NETIF_F_HW_VLAN_TX
3770                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3771
3772         if (test_bit(QL_DMA64, &qdev->flags))
3773                 ndev->features |= NETIF_F_HIGHDMA;
3774
3775         /*
3776          * Set up net_device structure.
3777          */
3778         ndev->tx_queue_len = qdev->tx_ring_size;
3779         ndev->irq = pdev->irq;
3780
3781         ndev->netdev_ops = &qlge_netdev_ops;
3782         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3783         ndev->watchdog_timeo = 10 * HZ;
3784
3785         err = register_netdev(ndev);
3786         if (err) {
3787                 dev_err(&pdev->dev, "net device registration failed.\n");
3788                 ql_release_all(pdev);
3789                 pci_disable_device(pdev);
3790                 return err;
3791         }
3792         netif_carrier_off(ndev);
3793         netif_stop_queue(ndev);
3794         ql_display_dev_info(ndev);
3795         cards_found++;
3796         return 0;
3797 }
3798
3799 static void __devexit qlge_remove(struct pci_dev *pdev)
3800 {
3801         struct net_device *ndev = pci_get_drvdata(pdev);
3802         unregister_netdev(ndev);
3803         ql_release_all(pdev);
3804         pci_disable_device(pdev);
3805         free_netdev(ndev);
3806 }
3807
3808 /*
3809  * This callback is called by the PCI subsystem whenever
3810  * a PCI bus error is detected.
3811  */
3812 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3813                                                enum pci_channel_state state)
3814 {
3815         struct net_device *ndev = pci_get_drvdata(pdev);
3816         struct ql_adapter *qdev = netdev_priv(ndev);
3817
3818         if (netif_running(ndev))
3819                 ql_adapter_down(qdev);
3820
3821         pci_disable_device(pdev);
3822
3823         /* Request a slot reset. */
3824         return PCI_ERS_RESULT_NEED_RESET;
3825 }
3826
3827 /*
3828  * This callback is called after the PCI buss has been reset.
3829  * Basically, this tries to restart the card from scratch.
3830  * This is a shortened version of the device probe/discovery code,
3831  * it resembles the first-half of the () routine.
3832  */
3833 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3834 {
3835         struct net_device *ndev = pci_get_drvdata(pdev);
3836         struct ql_adapter *qdev = netdev_priv(ndev);
3837
3838         if (pci_enable_device(pdev)) {
3839                 QPRINTK(qdev, IFUP, ERR,
3840                         "Cannot re-enable PCI device after reset.\n");
3841                 return PCI_ERS_RESULT_DISCONNECT;
3842         }
3843
3844         pci_set_master(pdev);
3845
3846         netif_carrier_off(ndev);
3847         netif_stop_queue(ndev);
3848         ql_adapter_reset(qdev);
3849
3850         /* Make sure the EEPROM is good */
3851         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3852
3853         if (!is_valid_ether_addr(ndev->perm_addr)) {
3854                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3855                 return PCI_ERS_RESULT_DISCONNECT;
3856         }
3857
3858         return PCI_ERS_RESULT_RECOVERED;
3859 }
3860
3861 static void qlge_io_resume(struct pci_dev *pdev)
3862 {
3863         struct net_device *ndev = pci_get_drvdata(pdev);
3864         struct ql_adapter *qdev = netdev_priv(ndev);
3865
3866         pci_set_master(pdev);
3867
3868         if (netif_running(ndev)) {
3869                 if (ql_adapter_up(qdev)) {
3870                         QPRINTK(qdev, IFUP, ERR,
3871                                 "Device initialization failed after reset.\n");
3872                         return;
3873                 }
3874         }
3875
3876         netif_device_attach(ndev);
3877 }
3878
3879 static struct pci_error_handlers qlge_err_handler = {
3880         .error_detected = qlge_io_error_detected,
3881         .slot_reset = qlge_io_slot_reset,
3882         .resume = qlge_io_resume,
3883 };
3884
3885 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3886 {
3887         struct net_device *ndev = pci_get_drvdata(pdev);
3888         struct ql_adapter *qdev = netdev_priv(ndev);
3889         int err;
3890
3891         netif_device_detach(ndev);
3892
3893         if (netif_running(ndev)) {
3894                 err = ql_adapter_down(qdev);
3895                 if (!err)
3896                         return err;
3897         }
3898
3899         err = pci_save_state(pdev);
3900         if (err)
3901                 return err;
3902
3903         pci_disable_device(pdev);
3904
3905         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3906
3907         return 0;
3908 }
3909
3910 #ifdef CONFIG_PM
3911 static int qlge_resume(struct pci_dev *pdev)
3912 {
3913         struct net_device *ndev = pci_get_drvdata(pdev);
3914         struct ql_adapter *qdev = netdev_priv(ndev);
3915         int err;
3916
3917         pci_set_power_state(pdev, PCI_D0);
3918         pci_restore_state(pdev);
3919         err = pci_enable_device(pdev);
3920         if (err) {
3921                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3922                 return err;
3923         }
3924         pci_set_master(pdev);
3925
3926         pci_enable_wake(pdev, PCI_D3hot, 0);
3927         pci_enable_wake(pdev, PCI_D3cold, 0);
3928
3929         if (netif_running(ndev)) {
3930                 err = ql_adapter_up(qdev);
3931                 if (err)
3932                         return err;
3933         }
3934
3935         netif_device_attach(ndev);
3936
3937         return 0;
3938 }
3939 #endif /* CONFIG_PM */
3940
3941 static void qlge_shutdown(struct pci_dev *pdev)
3942 {
3943         qlge_suspend(pdev, PMSG_SUSPEND);
3944 }
3945
3946 static struct pci_driver qlge_driver = {
3947         .name = DRV_NAME,
3948         .id_table = qlge_pci_tbl,
3949         .probe = qlge_probe,
3950         .remove = __devexit_p(qlge_remove),
3951 #ifdef CONFIG_PM
3952         .suspend = qlge_suspend,
3953         .resume = qlge_resume,
3954 #endif
3955         .shutdown = qlge_shutdown,
3956         .err_handler = &qlge_err_handler
3957 };
3958
3959 static int __init qlge_init_module(void)
3960 {
3961         return pci_register_driver(&qlge_driver);
3962 }
3963
3964 static void __exit qlge_exit(void)
3965 {
3966         pci_unregister_driver(&qlge_driver);
3967 }
3968
3969 module_init(qlge_init_module);
3970 module_exit(qlge_exit);