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   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61 /*  NETIF_MSG_TX_QUEUED | */
  62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int wait_count = 30;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 udelay(100);
 135         } while (--wait_count);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_wait_cfg(qdev, bit);
 218         if (status) {
 219                 QPRINTK(qdev, IFUP, ERR,
 220                         "Timed out waiting for CFG to come ready.\n");
 221                 goto exit;
 222         }
 223
 224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 225         if (status)
 226                 goto exit;
 227         ql_write32(qdev, ICB_L, (u32) map);
 228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         pci_unmap_single(qdev->pdev, map, size, direction);
 241         return status;
 242 }
 243
 244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 246                         u32 *value)
 247 {
 248         u32 offset = 0;
 249         int status;
 250
 251         switch (type) {
 252         case MAC_ADDR_TYPE_MULTI_MAC:
 253         case MAC_ADDR_TYPE_CAM_MAC:
 254                 {
 255                         status =
 256                             ql_wait_reg_rdy(qdev,
 257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 258                         if (status)
 259                                 goto exit;
 260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 263                         status =
 264                             ql_wait_reg_rdy(qdev,
 265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 266                         if (status)
 267                                 goto exit;
 268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 269                         status =
 270                             ql_wait_reg_rdy(qdev,
 271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 272                         if (status)
 273                                 goto exit;
 274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 277                         status =
 278                             ql_wait_reg_rdy(qdev,
 279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 280                         if (status)
 281                                 goto exit;
 282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 284                                 status =
 285                                     ql_wait_reg_rdy(qdev,
 286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 287                                 if (status)
 288                                         goto exit;
 289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 292                                 status =
 293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 294                                                     MAC_ADDR_MR, 0);
 295                                 if (status)
 296                                         goto exit;
 297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 298                         }
 299                         break;
 300                 }
 301         case MAC_ADDR_TYPE_VLAN:
 302         case MAC_ADDR_TYPE_MULTI_FLTR:
 303         default:
 304                 QPRINTK(qdev, IFUP, CRIT,
 305                         "Address type %d not yet supported.\n", type);
 306                 status = -EPERM;
 307         }
 308 exit:
 309         return status;
 310 }
 311
 312 /* Set up a MAC, multicast or VLAN address for the
 313  * inbound frame matching.
 314  */
 315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 316                                u16 index)
 317 {
 318         u32 offset = 0;
 319         int status = 0;
 320
 321         switch (type) {
 322         case MAC_ADDR_TYPE_MULTI_MAC:
 323         case MAC_ADDR_TYPE_CAM_MAC:
 324                 {
 325                         u32 cam_output;
 326                         u32 upper = (addr[0] << 8) | addr[1];
 327                         u32 lower =
 328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 329                             (addr[5]);
 330
 331                         QPRINTK(qdev, IFUP, DEBUG,
 332                                 "Adding %s address %pM"
 333                                 " at index %d in the CAM.\n",
 334                                 ((type ==
 335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 336                                  "UNICAST"), addr, index);
 337
 338                         status =
 339                             ql_wait_reg_rdy(qdev,
 340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 341                         if (status)
 342                                 goto exit;
 343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 345                                    type);       /* type */
 346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 347                         status =
 348                             ql_wait_reg_rdy(qdev,
 349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 350                         if (status)
 351                                 goto exit;
 352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 354                                    type);       /* type */
 355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 356                         status =
 357                             ql_wait_reg_rdy(qdev,
 358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 359                         if (status)
 360                                 goto exit;
 361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 363                                    type);       /* type */
 364                         /* This field should also include the queue id
 365                            and possibly the function id.  Right now we hardcode
 366                            the route field to NIC core.
 367                          */
 368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 369                                 cam_output = (CAM_OUT_ROUTE_NIC |
 370                                               (qdev->
 371                                                func << CAM_OUT_FUNC_SHIFT) |
 372                                               (qdev->
 373                                                rss_ring_first_cq_id <<
 374                                                CAM_OUT_CQ_ID_SHIFT));
 375                                 if (qdev->vlgrp)
 376                                         cam_output |= CAM_OUT_RV;
 377                                 /* route to NIC core */
 378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 379                         }
 380                         break;
 381                 }
 382         case MAC_ADDR_TYPE_VLAN:
 383                 {
 384                         u32 enable_bit = *((u32 *) &addr[0]);
 385                         /* For VLAN, the addr actually holds a bit that
 386                          * either enables or disables the vlan id we are
 387                          * addressing. It's either MAC_ADDR_E on or off.
 388                          * That's bit-27 we're talking about.
 389                          */
 390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 391                                 (enable_bit ? "Adding" : "Removing"),
 392                                 index, (enable_bit ? "to" : "from"));
 393
 394                         status =
 395                             ql_wait_reg_rdy(qdev,
 396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 397                         if (status)
 398                                 goto exit;
 399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 401                                    type |       /* type */
 402                                    enable_bit); /* enable/disable */
 403                         break;
 404                 }
 405         case MAC_ADDR_TYPE_MULTI_FLTR:
 406         default:
 407                 QPRINTK(qdev, IFUP, CRIT,
 408                         "Address type %d not yet supported.\n", type);
 409                 status = -EPERM;
 410         }
 411 exit:
 412         return status;
 413 }
 414
 415 /* Get a specific frame routing value from the CAM.
 416  * Used for debug and reg dump.
 417  */
 418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 419 {
 420         int status = 0;
 421
 422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 423         if (status)
 424                 goto exit;
 425
 426         ql_write32(qdev, RT_IDX,
 427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 429         if (status)
 430                 goto exit;
 431         *value = ql_read32(qdev, RT_DATA);
 432 exit:
 433         return status;
 434 }
 435
 436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 437  * to route different frame types to various inbound queues.  We send broadcast/
 438  * multicast/error frames to the default queue for slow handling,
 439  * and CAM hit/RSS frames to the fast handling queues.
 440  */
 441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 442                               int enable)
 443 {
 444         int status = -EINVAL; /* Return error if no mask match. */
 445         u32 value = 0;
 446
 447         QPRINTK(qdev, IFUP, DEBUG,
 448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 449                 (enable ? "Adding" : "Removing"),
 450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 452                 ((index ==
 453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 467                 (enable ? "to" : "from"));
 468
 469         switch (mask) {
 470         case RT_IDX_CAM_HIT:
 471                 {
 472                         value = RT_IDX_DST_CAM_Q |      /* dest */
 473                             RT_IDX_TYPE_NICQ |  /* type */
 474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 475                         break;
 476                 }
 477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 478                 {
 479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 480                             RT_IDX_TYPE_NICQ |  /* type */
 481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 482                         break;
 483                 }
 484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 485                 {
 486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 487                             RT_IDX_TYPE_NICQ |  /* type */
 488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 489                         break;
 490                 }
 491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 492                 {
 493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 494                             RT_IDX_TYPE_NICQ |  /* type */
 495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 496                         break;
 497                 }
 498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 499                 {
 500                         value = RT_IDX_DST_CAM_Q |      /* dest */
 501                             RT_IDX_TYPE_NICQ |  /* type */
 502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 503                         break;
 504                 }
 505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 506                 {
 507                         value = RT_IDX_DST_CAM_Q |      /* dest */
 508                             RT_IDX_TYPE_NICQ |  /* type */
 509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 510                         break;
 511                 }
 512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 513                 {
 514                         value = RT_IDX_DST_RSS |        /* dest */
 515                             RT_IDX_TYPE_NICQ |  /* type */
 516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 517                         break;
 518                 }
 519         case 0:         /* Clear the E-bit on an entry. */
 520                 {
 521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 522                             RT_IDX_TYPE_NICQ |  /* type */
 523                             (index << RT_IDX_IDX_SHIFT);/* index */
 524                         break;
 525                 }
 526         default:
 527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 528                         mask);
 529                 status = -EPERM;
 530                 goto exit;
 531         }
 532
 533         if (value) {
 534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 535                 if (status)
 536                         goto exit;
 537                 value |= (enable ? RT_IDX_E : 0);
 538                 ql_write32(qdev, RT_IDX, value);
 539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 540         }
 541 exit:
 542         return status;
 543 }
 544
 545 static void ql_enable_interrupts(struct ql_adapter *qdev)
 546 {
 547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 548 }
 549
 550 static void ql_disable_interrupts(struct ql_adapter *qdev)
 551 {
 552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 553 }
 554
 555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 556  * Otherwise, we may have multiple outstanding workers and don't want to
 557  * enable until the last one finishes. In this case, the irq_cnt gets
 558  * incremented everytime we queue a worker and decremented everytime
 559  * a worker finishes.  Once it hits zero we enable the interrupt.
 560  */
 561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 562 {
 563         u32 var = 0;
 564         unsigned long hw_flags = 0;
 565         struct intr_context *ctx = qdev->intr_context + intr;
 566
 567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 568                 /* Always enable if we're MSIX multi interrupts and
 569                  * it's not the default (zeroeth) interrupt.
 570                  */
 571                 ql_write32(qdev, INTR_EN,
 572                            ctx->intr_en_mask);
 573                 var = ql_read32(qdev, STS);
 574                 return var;
 575         }
 576
 577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 579                 ql_write32(qdev, INTR_EN,
 580                            ctx->intr_en_mask);
 581                 var = ql_read32(qdev, STS);
 582         }
 583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 584         return var;
 585 }
 586
 587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 588 {
 589         u32 var = 0;
 590         struct intr_context *ctx;
 591
 592         /* HW disables for us if we're MSIX multi interrupts and
 593          * it's not the default (zeroeth) interrupt.
 594          */
 595         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 596                 return 0;
 597
 598         ctx = qdev->intr_context + intr;
 599         spin_lock(&qdev->hw_lock);
 600         if (!atomic_read(&ctx->irq_cnt)) {
 601                 ql_write32(qdev, INTR_EN,
 602                 ctx->intr_dis_mask);
 603                 var = ql_read32(qdev, STS);
 604         }
 605         atomic_inc(&ctx->irq_cnt);
 606         spin_unlock(&qdev->hw_lock);
 607         return var;
 608 }
 609
 610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 611 {
 612         int i;
 613         for (i = 0; i < qdev->intr_count; i++) {
 614                 /* The enable call does a atomic_dec_and_test
 615                  * and enables only if the result is zero.
 616                  * So we precharge it here.
 617                  */
 618                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 619                         i == 0))
 620                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 621                 ql_enable_completion_interrupt(qdev, i);
 622         }
 623
 624 }
 625
 626 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
 627 {
 628         int status, i;
 629         u16 csum = 0;
 630         __le16 *flash = (__le16 *)&qdev->flash;
 631
 632         status = strncmp((char *)&qdev->flash, str, 4);
 633         if (status) {
 634                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
 635                 return  status;
 636         }
 637
 638         for (i = 0; i < size; i++)
 639                 csum += le16_to_cpu(*flash++);
 640
 641         if (csum)
 642                 QPRINTK(qdev, IFUP, ERR,
 643                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
 644
 645         return csum;
 646 }
 647
 648 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 649 {
 650         int status = 0;
 651         /* wait for reg to come ready */
 652         status = ql_wait_reg_rdy(qdev,
 653                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 654         if (status)
 655                 goto exit;
 656         /* set up for reg read */
 657         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 658         /* wait for reg to come ready */
 659         status = ql_wait_reg_rdy(qdev,
 660                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 661         if (status)
 662                 goto exit;
 663          /* This data is stored on flash as an array of
 664          * __le32.  Since ql_read32() returns cpu endian
 665          * we need to swap it back.
 666          */
 667         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 668 exit:
 669         return status;
 670 }
 671
 672 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
 673 {
 674         u32 i, size;
 675         int status;
 676         __le32 *p = (__le32 *)&qdev->flash;
 677         u32 offset;
 678
 679         /* Get flash offset for function and adjust
 680          * for dword access.
 681          */
 682         if (!qdev->func)
 683                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
 684         else
 685                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
 686
 687         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 688                 return -ETIMEDOUT;
 689
 690         size = sizeof(struct flash_params_8000) / sizeof(u32);
 691         for (i = 0; i < size; i++, p++) {
 692                 status = ql_read_flash_word(qdev, i+offset, p);
 693                 if (status) {
 694                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 695                         goto exit;
 696                 }
 697         }
 698
 699         status = ql_validate_flash(qdev,
 700                         sizeof(struct flash_params_8000) / sizeof(u16),
 701                         "8000");
 702         if (status) {
 703                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 704                 status = -EINVAL;
 705                 goto exit;
 706         }
 707
 708         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
 709                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
 710                 status = -EINVAL;
 711                 goto exit;
 712         }
 713
 714         memcpy(qdev->ndev->dev_addr,
 715                 qdev->flash.flash_params_8000.mac_addr,
 716                 qdev->ndev->addr_len);
 717
 718 exit:
 719         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 720         return status;
 721 }
 722
 723 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
 724 {
 725         int i;
 726         int status;
 727         __le32 *p = (__le32 *)&qdev->flash;
 728         u32 offset = 0;
 729         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
 730
 731         /* Second function's parameters follow the first
 732          * function's.
 733          */
 734         if (qdev->func)
 735                 offset = size;
 736
 737         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 738                 return -ETIMEDOUT;
 739
 740         for (i = 0; i < size; i++, p++) {
 741                 status = ql_read_flash_word(qdev, i+offset, p);
 742                 if (status) {
 743                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 744                         goto exit;
 745                 }
 746
 747         }
 748
 749         status = ql_validate_flash(qdev,
 750                         sizeof(struct flash_params_8012) / sizeof(u16),
 751                         "8012");
 752         if (status) {
 753                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 754                 status = -EINVAL;
 755                 goto exit;
 756         }
 757
 758         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
 759                 status = -EINVAL;
 760                 goto exit;
 761         }
 762
 763         memcpy(qdev->ndev->dev_addr,
 764                 qdev->flash.flash_params_8012.mac_addr,
 765                 qdev->ndev->addr_len);
 766
 767 exit:
 768         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 769         return status;
 770 }
 771
 772 /* xgmac register are located behind the xgmac_addr and xgmac_data
 773  * register pair.  Each read/write requires us to wait for the ready
 774  * bit before reading/writing the data.
 775  */
 776 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 777 {
 778         int status;
 779         /* wait for reg to come ready */
 780         status = ql_wait_reg_rdy(qdev,
 781                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 782         if (status)
 783                 return status;
 784         /* write the data to the data reg */
 785         ql_write32(qdev, XGMAC_DATA, data);
 786         /* trigger the write */
 787         ql_write32(qdev, XGMAC_ADDR, reg);
 788         return status;
 789 }
 790
 791 /* xgmac register are located behind the xgmac_addr and xgmac_data
 792  * register pair.  Each read/write requires us to wait for the ready
 793  * bit before reading/writing the data.
 794  */
 795 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 796 {
 797         int status = 0;
 798         /* wait for reg to come ready */
 799         status = ql_wait_reg_rdy(qdev,
 800                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 801         if (status)
 802                 goto exit;
 803         /* set up for reg read */
 804         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 805         /* wait for reg to come ready */
 806         status = ql_wait_reg_rdy(qdev,
 807                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 808         if (status)
 809                 goto exit;
 810         /* get the data */
 811         *data = ql_read32(qdev, XGMAC_DATA);
 812 exit:
 813         return status;
 814 }
 815
 816 /* This is used for reading the 64-bit statistics regs. */
 817 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 818 {
 819         int status = 0;
 820         u32 hi = 0;
 821         u32 lo = 0;
 822
 823         status = ql_read_xgmac_reg(qdev, reg, &lo);
 824         if (status)
 825                 goto exit;
 826
 827         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 828         if (status)
 829                 goto exit;
 830
 831         *data = (u64) lo | ((u64) hi << 32);
 832
 833 exit:
 834         return status;
 835 }
 836
 837 static int ql_8000_port_initialize(struct ql_adapter *qdev)
 838 {
 839         int status;
 840         /*
 841          * Get MPI firmware version for driver banner
 842          * and ethool info.
 843          */
 844         status = ql_mb_about_fw(qdev);
 845         if (status)
 846                 goto exit;
 847         status = ql_mb_get_fw_state(qdev);
 848         if (status)
 849                 goto exit;
 850         /* Wake up a worker to get/set the TX/RX frame sizes. */
 851         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
 852 exit:
 853         return status;
 854 }
 855
 856 /* Take the MAC Core out of reset.
 857  * Enable statistics counting.
 858  * Take the transmitter/receiver out of reset.
 859  * This functionality may be done in the MPI firmware at a
 860  * later date.
 861  */
 862 static int ql_8012_port_initialize(struct ql_adapter *qdev)
 863 {
 864         int status = 0;
 865         u32 data;
 866
 867         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 868                 /* Another function has the semaphore, so
 869                  * wait for the port init bit to come ready.
 870                  */
 871                 QPRINTK(qdev, LINK, INFO,
 872                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 873                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 874                 if (status) {
 875                         QPRINTK(qdev, LINK, CRIT,
 876                                 "Port initialize timed out.\n");
 877                 }
 878                 return status;
 879         }
 880
 881         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 882         /* Set the core reset. */
 883         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 884         if (status)
 885                 goto end;
 886         data |= GLOBAL_CFG_RESET;
 887         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 888         if (status)
 889                 goto end;
 890
 891         /* Clear the core reset and turn on jumbo for receiver. */
 892         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 893         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 894         data |= GLOBAL_CFG_TX_STAT_EN;
 895         data |= GLOBAL_CFG_RX_STAT_EN;
 896         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 897         if (status)
 898                 goto end;
 899
 900         /* Enable transmitter, and clear it's reset. */
 901         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 902         if (status)
 903                 goto end;
 904         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 905         data |= TX_CFG_EN;      /* Enable the transmitter. */
 906         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 907         if (status)
 908                 goto end;
 909
 910         /* Enable receiver and clear it's reset. */
 911         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 912         if (status)
 913                 goto end;
 914         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 915         data |= RX_CFG_EN;      /* Enable the receiver. */
 916         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 917         if (status)
 918                 goto end;
 919
 920         /* Turn on jumbo. */
 921         status =
 922             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 923         if (status)
 924                 goto end;
 925         status =
 926             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 927         if (status)
 928                 goto end;
 929
 930         /* Signal to the world that the port is enabled.        */
 931         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 932 end:
 933         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 934         return status;
 935 }
 936
 937 /* Get the next large buffer. */
 938 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 939 {
 940         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 941         rx_ring->lbq_curr_idx++;
 942         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 943                 rx_ring->lbq_curr_idx = 0;
 944         rx_ring->lbq_free_cnt++;
 945         return lbq_desc;
 946 }
 947
 948 /* Get the next small buffer. */
 949 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 950 {
 951         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 952         rx_ring->sbq_curr_idx++;
 953         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 954                 rx_ring->sbq_curr_idx = 0;
 955         rx_ring->sbq_free_cnt++;
 956         return sbq_desc;
 957 }
 958
 959 /* Update an rx ring index. */
 960 static void ql_update_cq(struct rx_ring *rx_ring)
 961 {
 962         rx_ring->cnsmr_idx++;
 963         rx_ring->curr_entry++;
 964         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 965                 rx_ring->cnsmr_idx = 0;
 966                 rx_ring->curr_entry = rx_ring->cq_base;
 967         }
 968 }
 969
 970 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 971 {
 972         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 973 }
 974
 975 /* Process (refill) a large buffer queue. */
 976 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 977 {
 978         u32 clean_idx = rx_ring->lbq_clean_idx;
 979         u32 start_idx = clean_idx;
 980         struct bq_desc *lbq_desc;
 981         u64 map;
 982         int i;
 983
 984         while (rx_ring->lbq_free_cnt > 16) {
 985                 for (i = 0; i < 16; i++) {
 986                         QPRINTK(qdev, RX_STATUS, DEBUG,
 987                                 "lbq: try cleaning clean_idx = %d.\n",
 988                                 clean_idx);
 989                         lbq_desc = &rx_ring->lbq[clean_idx];
 990                         if (lbq_desc->p.lbq_page == NULL) {
 991                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 992                                         "lbq: getting new page for index %d.\n",
 993                                         lbq_desc->index);
 994                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 995                                 if (lbq_desc->p.lbq_page == NULL) {
 996                                         rx_ring->lbq_clean_idx = clean_idx;
 997                                         QPRINTK(qdev, RX_STATUS, ERR,
 998                                                 "Couldn't get a page.\n");
 999                                         return;
1000                                 }
1001                                 map = pci_map_page(qdev->pdev,
1002                                                    lbq_desc->p.lbq_page,
1003                                                    0, PAGE_SIZE,
1004                                                    PCI_DMA_FROMDEVICE);
1005                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1006                                         rx_ring->lbq_clean_idx = clean_idx;
1007                                         put_page(lbq_desc->p.lbq_page);
1008                                         lbq_desc->p.lbq_page = NULL;
1009                                         QPRINTK(qdev, RX_STATUS, ERR,
1010                                                 "PCI mapping failed.\n");
1011                                         return;
1012                                 }
1013                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1014                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1015                                 *lbq_desc->addr = cpu_to_le64(map);
1016                         }
1017                         clean_idx++;
1018                         if (clean_idx == rx_ring->lbq_len)
1019                                 clean_idx = 0;
1020                 }
1021
1022                 rx_ring->lbq_clean_idx = clean_idx;
1023                 rx_ring->lbq_prod_idx += 16;
1024                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1025                         rx_ring->lbq_prod_idx = 0;
1026                 rx_ring->lbq_free_cnt -= 16;
1027         }
1028
1029         if (start_idx != clean_idx) {
1030                 QPRINTK(qdev, RX_STATUS, DEBUG,
1031                         "lbq: updating prod idx = %d.\n",
1032                         rx_ring->lbq_prod_idx);
1033                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1034                                 rx_ring->lbq_prod_idx_db_reg);
1035         }
1036 }
1037
1038 /* Process (refill) a small buffer queue. */
1039 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1040 {
1041         u32 clean_idx = rx_ring->sbq_clean_idx;
1042         u32 start_idx = clean_idx;
1043         struct bq_desc *sbq_desc;
1044         u64 map;
1045         int i;
1046
1047         while (rx_ring->sbq_free_cnt > 16) {
1048                 for (i = 0; i < 16; i++) {
1049                         sbq_desc = &rx_ring->sbq[clean_idx];
1050                         QPRINTK(qdev, RX_STATUS, DEBUG,
1051                                 "sbq: try cleaning clean_idx = %d.\n",
1052                                 clean_idx);
1053                         if (sbq_desc->p.skb == NULL) {
1054                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1055                                         "sbq: getting new skb for index %d.\n",
1056                                         sbq_desc->index);
1057                                 sbq_desc->p.skb =
1058                                     netdev_alloc_skb(qdev->ndev,
1059                                                      rx_ring->sbq_buf_size);
1060                                 if (sbq_desc->p.skb == NULL) {
1061                                         QPRINTK(qdev, PROBE, ERR,
1062                                                 "Couldn't get an skb.\n");
1063                                         rx_ring->sbq_clean_idx = clean_idx;
1064                                         return;
1065                                 }
1066                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1067                                 map = pci_map_single(qdev->pdev,
1068                                                      sbq_desc->p.skb->data,
1069                                                      rx_ring->sbq_buf_size /
1070                                                      2, PCI_DMA_FROMDEVICE);
1071                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1072                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1073                                         rx_ring->sbq_clean_idx = clean_idx;
1074                                         dev_kfree_skb_any(sbq_desc->p.skb);
1075                                         sbq_desc->p.skb = NULL;
1076                                         return;
1077                                 }
1078                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1079                                 pci_unmap_len_set(sbq_desc, maplen,
1080                                                   rx_ring->sbq_buf_size / 2);
1081                                 *sbq_desc->addr = cpu_to_le64(map);
1082                         }
1083
1084                         clean_idx++;
1085                         if (clean_idx == rx_ring->sbq_len)
1086                                 clean_idx = 0;
1087                 }
1088                 rx_ring->sbq_clean_idx = clean_idx;
1089                 rx_ring->sbq_prod_idx += 16;
1090                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1091                         rx_ring->sbq_prod_idx = 0;
1092                 rx_ring->sbq_free_cnt -= 16;
1093         }
1094
1095         if (start_idx != clean_idx) {
1096                 QPRINTK(qdev, RX_STATUS, DEBUG,
1097                         "sbq: updating prod idx = %d.\n",
1098                         rx_ring->sbq_prod_idx);
1099                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1100                                 rx_ring->sbq_prod_idx_db_reg);
1101         }
1102 }
1103
1104 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1105                                     struct rx_ring *rx_ring)
1106 {
1107         ql_update_sbq(qdev, rx_ring);
1108         ql_update_lbq(qdev, rx_ring);
1109 }
1110
1111 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1112  * fails at some stage, or from the interrupt when a tx completes.
1113  */
1114 static void ql_unmap_send(struct ql_adapter *qdev,
1115                           struct tx_ring_desc *tx_ring_desc, int mapped)
1116 {
1117         int i;
1118         for (i = 0; i < mapped; i++) {
1119                 if (i == 0 || (i == 7 && mapped > 7)) {
1120                         /*
1121                          * Unmap the skb->data area, or the
1122                          * external sglist (AKA the Outbound
1123                          * Address List (OAL)).
1124                          * If its the zeroeth element, then it's
1125                          * the skb->data area.  If it's the 7th
1126                          * element and there is more than 6 frags,
1127                          * then its an OAL.
1128                          */
1129                         if (i == 7) {
1130                                 QPRINTK(qdev, TX_DONE, DEBUG,
1131                                         "unmapping OAL area.\n");
1132                         }
1133                         pci_unmap_single(qdev->pdev,
1134                                          pci_unmap_addr(&tx_ring_desc->map[i],
1135                                                         mapaddr),
1136                                          pci_unmap_len(&tx_ring_desc->map[i],
1137                                                        maplen),
1138                                          PCI_DMA_TODEVICE);
1139                 } else {
1140                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1141                                 i);
1142                         pci_unmap_page(qdev->pdev,
1143                                        pci_unmap_addr(&tx_ring_desc->map[i],
1144                                                       mapaddr),
1145                                        pci_unmap_len(&tx_ring_desc->map[i],
1146                                                      maplen), PCI_DMA_TODEVICE);
1147                 }
1148         }
1149
1150 }
1151
1152 /* Map the buffers for this transmit.  This will return
1153  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1154  */
1155 static int ql_map_send(struct ql_adapter *qdev,
1156                        struct ob_mac_iocb_req *mac_iocb_ptr,
1157                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1158 {
1159         int len = skb_headlen(skb);
1160         dma_addr_t map;
1161         int frag_idx, err, map_idx = 0;
1162         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1163         int frag_cnt = skb_shinfo(skb)->nr_frags;
1164
1165         if (frag_cnt) {
1166                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1167         }
1168         /*
1169          * Map the skb buffer first.
1170          */
1171         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1172
1173         err = pci_dma_mapping_error(qdev->pdev, map);
1174         if (err) {
1175                 QPRINTK(qdev, TX_QUEUED, ERR,
1176                         "PCI mapping failed with error: %d\n", err);
1177
1178                 return NETDEV_TX_BUSY;
1179         }
1180
1181         tbd->len = cpu_to_le32(len);
1182         tbd->addr = cpu_to_le64(map);
1183         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1184         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1185         map_idx++;
1186
1187         /*
1188          * This loop fills the remainder of the 8 address descriptors
1189          * in the IOCB.  If there are more than 7 fragments, then the
1190          * eighth address desc will point to an external list (OAL).
1191          * When this happens, the remainder of the frags will be stored
1192          * in this list.
1193          */
1194         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1195                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1196                 tbd++;
1197                 if (frag_idx == 6 && frag_cnt > 7) {
1198                         /* Let's tack on an sglist.
1199                          * Our control block will now
1200                          * look like this:
1201                          * iocb->seg[0] = skb->data
1202                          * iocb->seg[1] = frag[0]
1203                          * iocb->seg[2] = frag[1]
1204                          * iocb->seg[3] = frag[2]
1205                          * iocb->seg[4] = frag[3]
1206                          * iocb->seg[5] = frag[4]
1207                          * iocb->seg[6] = frag[5]
1208                          * iocb->seg[7] = ptr to OAL (external sglist)
1209                          * oal->seg[0] = frag[6]
1210                          * oal->seg[1] = frag[7]
1211                          * oal->seg[2] = frag[8]
1212                          * oal->seg[3] = frag[9]
1213                          * oal->seg[4] = frag[10]
1214                          *      etc...
1215                          */
1216                         /* Tack on the OAL in the eighth segment of IOCB. */
1217                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1218                                              sizeof(struct oal),
1219                                              PCI_DMA_TODEVICE);
1220                         err = pci_dma_mapping_error(qdev->pdev, map);
1221                         if (err) {
1222                                 QPRINTK(qdev, TX_QUEUED, ERR,
1223                                         "PCI mapping outbound address list with error: %d\n",
1224                                         err);
1225                                 goto map_error;
1226                         }
1227
1228                         tbd->addr = cpu_to_le64(map);
1229                         /*
1230                          * The length is the number of fragments
1231                          * that remain to be mapped times the length
1232                          * of our sglist (OAL).
1233                          */
1234                         tbd->len =
1235                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1236                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1237                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1238                                            map);
1239                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1240                                           sizeof(struct oal));
1241                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1242                         map_idx++;
1243                 }
1244
1245                 map =
1246                     pci_map_page(qdev->pdev, frag->page,
1247                                  frag->page_offset, frag->size,
1248                                  PCI_DMA_TODEVICE);
1249
1250                 err = pci_dma_mapping_error(qdev->pdev, map);
1251                 if (err) {
1252                         QPRINTK(qdev, TX_QUEUED, ERR,
1253                                 "PCI mapping frags failed with error: %d.\n",
1254                                 err);
1255                         goto map_error;
1256                 }
1257
1258                 tbd->addr = cpu_to_le64(map);
1259                 tbd->len = cpu_to_le32(frag->size);
1260                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1261                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1262                                   frag->size);
1263
1264         }
1265         /* Save the number of segments we've mapped. */
1266         tx_ring_desc->map_cnt = map_idx;
1267         /* Terminate the last segment. */
1268         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1269         return NETDEV_TX_OK;
1270
1271 map_error:
1272         /*
1273          * If the first frag mapping failed, then i will be zero.
1274          * This causes the unmap of the skb->data area.  Otherwise
1275          * we pass in the number of frags that mapped successfully
1276          * so they can be umapped.
1277          */
1278         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1279         return NETDEV_TX_BUSY;
1280 }
1281
1282 static void ql_realign_skb(struct sk_buff *skb, int len)
1283 {
1284         void *temp_addr = skb->data;
1285
1286         /* Undo the skb_reserve(skb,32) we did before
1287          * giving to hardware, and realign data on
1288          * a 2-byte boundary.
1289          */
1290         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1291         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1292         skb_copy_to_linear_data(skb, temp_addr,
1293                 (unsigned int)len);
1294 }
1295
1296 /*
1297  * This function builds an skb for the given inbound
1298  * completion.  It will be rewritten for readability in the near
1299  * future, but for not it works well.
1300  */
1301 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1302                                        struct rx_ring *rx_ring,
1303                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1304 {
1305         struct bq_desc *lbq_desc;
1306         struct bq_desc *sbq_desc;
1307         struct sk_buff *skb = NULL;
1308         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1309        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1310
1311         /*
1312          * Handle the header buffer if present.
1313          */
1314         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1315             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1316                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1317                 /*
1318                  * Headers fit nicely into a small buffer.
1319                  */
1320                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1321                 pci_unmap_single(qdev->pdev,
1322                                 pci_unmap_addr(sbq_desc, mapaddr),
1323                                 pci_unmap_len(sbq_desc, maplen),
1324                                 PCI_DMA_FROMDEVICE);
1325                 skb = sbq_desc->p.skb;
1326                 ql_realign_skb(skb, hdr_len);
1327                 skb_put(skb, hdr_len);
1328                 sbq_desc->p.skb = NULL;
1329         }
1330
1331         /*
1332          * Handle the data buffer(s).
1333          */
1334         if (unlikely(!length)) {        /* Is there data too? */
1335                 QPRINTK(qdev, RX_STATUS, DEBUG,
1336                         "No Data buffer in this packet.\n");
1337                 return skb;
1338         }
1339
1340         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1341                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1342                         QPRINTK(qdev, RX_STATUS, DEBUG,
1343                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1344                         /*
1345                          * Data is less than small buffer size so it's
1346                          * stuffed in a small buffer.
1347                          * For this case we append the data
1348                          * from the "data" small buffer to the "header" small
1349                          * buffer.
1350                          */
1351                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1352                         pci_dma_sync_single_for_cpu(qdev->pdev,
1353                                                     pci_unmap_addr
1354                                                     (sbq_desc, mapaddr),
1355                                                     pci_unmap_len
1356                                                     (sbq_desc, maplen),
1357                                                     PCI_DMA_FROMDEVICE);
1358                         memcpy(skb_put(skb, length),
1359                                sbq_desc->p.skb->data, length);
1360                         pci_dma_sync_single_for_device(qdev->pdev,
1361                                                        pci_unmap_addr
1362                                                        (sbq_desc,
1363                                                         mapaddr),
1364                                                        pci_unmap_len
1365                                                        (sbq_desc,
1366                                                         maplen),
1367                                                        PCI_DMA_FROMDEVICE);
1368                 } else {
1369                         QPRINTK(qdev, RX_STATUS, DEBUG,
1370                                 "%d bytes in a single small buffer.\n", length);
1371                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1372                         skb = sbq_desc->p.skb;
1373                         ql_realign_skb(skb, length);
1374                         skb_put(skb, length);
1375                         pci_unmap_single(qdev->pdev,
1376                                          pci_unmap_addr(sbq_desc,
1377                                                         mapaddr),
1378                                          pci_unmap_len(sbq_desc,
1379                                                        maplen),
1380                                          PCI_DMA_FROMDEVICE);
1381                         sbq_desc->p.skb = NULL;
1382                 }
1383         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1384                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1385                         QPRINTK(qdev, RX_STATUS, DEBUG,
1386                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1387                         /*
1388                          * The data is in a single large buffer.  We
1389                          * chain it to the header buffer's skb and let
1390                          * it rip.
1391                          */
1392                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1393                         pci_unmap_page(qdev->pdev,
1394                                        pci_unmap_addr(lbq_desc,
1395                                                       mapaddr),
1396                                        pci_unmap_len(lbq_desc, maplen),
1397                                        PCI_DMA_FROMDEVICE);
1398                         QPRINTK(qdev, RX_STATUS, DEBUG,
1399                                 "Chaining page to skb.\n");
1400                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1401                                            0, length);
1402                         skb->len += length;
1403                         skb->data_len += length;
1404                         skb->truesize += length;
1405                         lbq_desc->p.lbq_page = NULL;
1406                 } else {
1407                         /*
1408                          * The headers and data are in a single large buffer. We
1409                          * copy it to a new skb and let it go. This can happen with
1410                          * jumbo mtu on a non-TCP/UDP frame.
1411                          */
1412                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1413                         skb = netdev_alloc_skb(qdev->ndev, length);
1414                         if (skb == NULL) {
1415                                 QPRINTK(qdev, PROBE, DEBUG,
1416                                         "No skb available, drop the packet.\n");
1417                                 return NULL;
1418                         }
1419                         pci_unmap_page(qdev->pdev,
1420                                        pci_unmap_addr(lbq_desc,
1421                                                       mapaddr),
1422                                        pci_unmap_len(lbq_desc, maplen),
1423                                        PCI_DMA_FROMDEVICE);
1424                         skb_reserve(skb, NET_IP_ALIGN);
1425                         QPRINTK(qdev, RX_STATUS, DEBUG,
1426                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1427                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1428                                            0, length);
1429                         skb->len += length;
1430                         skb->data_len += length;
1431                         skb->truesize += length;
1432                         length -= length;
1433                         lbq_desc->p.lbq_page = NULL;
1434                         __pskb_pull_tail(skb,
1435                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1436                                 VLAN_ETH_HLEN : ETH_HLEN);
1437                 }
1438         } else {
1439                 /*
1440                  * The data is in a chain of large buffers
1441                  * pointed to by a small buffer.  We loop
1442                  * thru and chain them to the our small header
1443                  * buffer's skb.
1444                  * frags:  There are 18 max frags and our small
1445                  *         buffer will hold 32 of them. The thing is,
1446                  *         we'll use 3 max for our 9000 byte jumbo
1447                  *         frames.  If the MTU goes up we could
1448                  *          eventually be in trouble.
1449                  */
1450                 int size, offset, i = 0;
1451                 __le64 *bq, bq_array[8];
1452                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1453                 pci_unmap_single(qdev->pdev,
1454                                  pci_unmap_addr(sbq_desc, mapaddr),
1455                                  pci_unmap_len(sbq_desc, maplen),
1456                                  PCI_DMA_FROMDEVICE);
1457                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1458                         /*
1459                          * This is an non TCP/UDP IP frame, so
1460                          * the headers aren't split into a small
1461                          * buffer.  We have to use the small buffer
1462                          * that contains our sg list as our skb to
1463                          * send upstairs. Copy the sg list here to
1464                          * a local buffer and use it to find the
1465                          * pages to chain.
1466                          */
1467                         QPRINTK(qdev, RX_STATUS, DEBUG,
1468                                 "%d bytes of headers & data in chain of large.\n", length);
1469                         skb = sbq_desc->p.skb;
1470                         bq = &bq_array[0];
1471                         memcpy(bq, skb->data, sizeof(bq_array));
1472                         sbq_desc->p.skb = NULL;
1473                         skb_reserve(skb, NET_IP_ALIGN);
1474                 } else {
1475                         QPRINTK(qdev, RX_STATUS, DEBUG,
1476                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1477                         bq = (__le64 *)sbq_desc->p.skb->data;
1478                 }
1479                 while (length > 0) {
1480                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1481                         pci_unmap_page(qdev->pdev,
1482                                        pci_unmap_addr(lbq_desc,
1483                                                       mapaddr),
1484                                        pci_unmap_len(lbq_desc,
1485                                                      maplen),
1486                                        PCI_DMA_FROMDEVICE);
1487                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1488                         offset = 0;
1489
1490                         QPRINTK(qdev, RX_STATUS, DEBUG,
1491                                 "Adding page %d to skb for %d bytes.\n",
1492                                 i, size);
1493                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1494                                            offset, size);
1495                         skb->len += size;
1496                         skb->data_len += size;
1497                         skb->truesize += size;
1498                         length -= size;
1499                         lbq_desc->p.lbq_page = NULL;
1500                         bq++;
1501                         i++;
1502                 }
1503                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1504                                 VLAN_ETH_HLEN : ETH_HLEN);
1505         }
1506         return skb;
1507 }
1508
1509 /* Process an inbound completion from an rx ring. */
1510 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1511                                    struct rx_ring *rx_ring,
1512                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1513 {
1514         struct net_device *ndev = qdev->ndev;
1515         struct sk_buff *skb = NULL;
1516         u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1517                         IB_MAC_IOCB_RSP_VLAN_MASK)
1518
1519         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1520
1521         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1522         if (unlikely(!skb)) {
1523                 QPRINTK(qdev, RX_STATUS, DEBUG,
1524                         "No skb available, drop packet.\n");
1525                 return;
1526         }
1527
1528         /* Frame error, so drop the packet. */
1529         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1530                 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1531                                         ib_mac_rsp->flags2);
1532                 dev_kfree_skb_any(skb);
1533                 return;
1534         }
1535         prefetch(skb->data);
1536         skb->dev = ndev;
1537         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1538                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1539                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1540                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1541                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1542                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1543                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1544                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1545         }
1546         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1547                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1548         }
1549
1550         skb->protocol = eth_type_trans(skb, ndev);
1551         skb->ip_summed = CHECKSUM_NONE;
1552
1553         /* If rx checksum is on, and there are no
1554          * csum or frame errors.
1555          */
1556         if (qdev->rx_csum &&
1557                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1558                 /* TCP frame. */
1559                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1560                         QPRINTK(qdev, RX_STATUS, DEBUG,
1561                                         "TCP checksum done!\n");
1562                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1563                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1564                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1565                 /* Unfragmented ipv4 UDP frame. */
1566                         struct iphdr *iph = (struct iphdr *) skb->data;
1567                         if (!(iph->frag_off &
1568                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1569                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1570                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1571                                                 "TCP checksum done!\n");
1572                         }
1573                 }
1574         }
1575
1576         qdev->stats.rx_packets++;
1577         qdev->stats.rx_bytes += skb->len;
1578         skb_record_rx_queue(skb,
1579                 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1580         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1581                 if (qdev->vlgrp &&
1582                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1583                         (vlan_id != 0))
1584                         vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1585                                 vlan_id, skb);
1586                 else
1587                         napi_gro_receive(&rx_ring->napi, skb);
1588         } else {
1589                 if (qdev->vlgrp &&
1590                         (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1591                         (vlan_id != 0))
1592                         vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1593                 else
1594                         netif_receive_skb(skb);
1595         }
1596 }
1597
1598 /* Process an outbound completion from an rx ring. */
1599 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1600                                    struct ob_mac_iocb_rsp *mac_rsp)
1601 {
1602         struct tx_ring *tx_ring;
1603         struct tx_ring_desc *tx_ring_desc;
1604
1605         QL_DUMP_OB_MAC_RSP(mac_rsp);
1606         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1607         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1608         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1609         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1610         qdev->stats.tx_packets++;
1611         dev_kfree_skb(tx_ring_desc->skb);
1612         tx_ring_desc->skb = NULL;
1613
1614         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1615                                         OB_MAC_IOCB_RSP_S |
1616                                         OB_MAC_IOCB_RSP_L |
1617                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1618                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1619                         QPRINTK(qdev, TX_DONE, WARNING,
1620                                 "Total descriptor length did not match transfer length.\n");
1621                 }
1622                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1623                         QPRINTK(qdev, TX_DONE, WARNING,
1624                                 "Frame too short to be legal, not sent.\n");
1625                 }
1626                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1627                         QPRINTK(qdev, TX_DONE, WARNING,
1628                                 "Frame too long, but sent anyway.\n");
1629                 }
1630                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1631                         QPRINTK(qdev, TX_DONE, WARNING,
1632                                 "PCI backplane error. Frame not sent.\n");
1633                 }
1634         }
1635         atomic_inc(&tx_ring->tx_count);
1636 }
1637
1638 /* Fire up a handler to reset the MPI processor. */
1639 void ql_queue_fw_error(struct ql_adapter *qdev)
1640 {
1641         netif_carrier_off(qdev->ndev);
1642         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1643 }
1644
1645 void ql_queue_asic_error(struct ql_adapter *qdev)
1646 {
1647         netif_carrier_off(qdev->ndev);
1648         ql_disable_interrupts(qdev);
1649         /* Clear adapter up bit to signal the recovery
1650          * process that it shouldn't kill the reset worker
1651          * thread
1652          */
1653         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1654         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1655 }
1656
1657 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1658                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1659 {
1660         switch (ib_ae_rsp->event) {
1661         case MGMT_ERR_EVENT:
1662                 QPRINTK(qdev, RX_ERR, ERR,
1663                         "Management Processor Fatal Error.\n");
1664                 ql_queue_fw_error(qdev);
1665                 return;
1666
1667         case CAM_LOOKUP_ERR_EVENT:
1668                 QPRINTK(qdev, LINK, ERR,
1669                         "Multiple CAM hits lookup occurred.\n");
1670                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1671                 ql_queue_asic_error(qdev);
1672                 return;
1673
1674         case SOFT_ECC_ERROR_EVENT:
1675                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1676                 ql_queue_asic_error(qdev);
1677                 break;
1678
1679         case PCI_ERR_ANON_BUF_RD:
1680                 QPRINTK(qdev, RX_ERR, ERR,
1681                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1682                         ib_ae_rsp->q_id);
1683                 ql_queue_asic_error(qdev);
1684                 break;
1685
1686         default:
1687                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1688                         ib_ae_rsp->event);
1689                 ql_queue_asic_error(qdev);
1690                 break;
1691         }
1692 }
1693
1694 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1695 {
1696         struct ql_adapter *qdev = rx_ring->qdev;
1697         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1698         struct ob_mac_iocb_rsp *net_rsp = NULL;
1699         int count = 0;
1700
1701         struct tx_ring *tx_ring;
1702         /* While there are entries in the completion queue. */
1703         while (prod != rx_ring->cnsmr_idx) {
1704
1705                 QPRINTK(qdev, RX_STATUS, DEBUG,
1706                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1707                         prod, rx_ring->cnsmr_idx);
1708
1709                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1710                 rmb();
1711                 switch (net_rsp->opcode) {
1712
1713                 case OPCODE_OB_MAC_TSO_IOCB:
1714                 case OPCODE_OB_MAC_IOCB:
1715                         ql_process_mac_tx_intr(qdev, net_rsp);
1716                         break;
1717                 default:
1718                         QPRINTK(qdev, RX_STATUS, DEBUG,
1719                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1720                                 net_rsp->opcode);
1721                 }
1722                 count++;
1723                 ql_update_cq(rx_ring);
1724                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1725         }
1726         ql_write_cq_idx(rx_ring);
1727         tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1728         if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1729                                         net_rsp != NULL) {
1730                 if (atomic_read(&tx_ring->queue_stopped) &&
1731                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1732                         /*
1733                          * The queue got stopped because the tx_ring was full.
1734                          * Wake it up, because it's now at least 25% empty.
1735                          */
1736                         netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1737         }
1738
1739         return count;
1740 }
1741
1742 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1743 {
1744         struct ql_adapter *qdev = rx_ring->qdev;
1745         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1746         struct ql_net_rsp_iocb *net_rsp;
1747         int count = 0;
1748
1749         /* While there are entries in the completion queue. */
1750         while (prod != rx_ring->cnsmr_idx) {
1751
1752                 QPRINTK(qdev, RX_STATUS, DEBUG,
1753                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1754                         prod, rx_ring->cnsmr_idx);
1755
1756                 net_rsp = rx_ring->curr_entry;
1757                 rmb();
1758                 switch (net_rsp->opcode) {
1759                 case OPCODE_IB_MAC_IOCB:
1760                         ql_process_mac_rx_intr(qdev, rx_ring,
1761                                                (struct ib_mac_iocb_rsp *)
1762                                                net_rsp);
1763                         break;
1764
1765                 case OPCODE_IB_AE_IOCB:
1766                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1767                                                 net_rsp);
1768                         break;
1769                 default:
1770                         {
1771                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1772                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1773                                         net_rsp->opcode);
1774                         }
1775                 }
1776                 count++;
1777                 ql_update_cq(rx_ring);
1778                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1779                 if (count == budget)
1780                         break;
1781         }
1782         ql_update_buffer_queues(qdev, rx_ring);
1783         ql_write_cq_idx(rx_ring);
1784         return count;
1785 }
1786
1787 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1788 {
1789         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1790         struct ql_adapter *qdev = rx_ring->qdev;
1791         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1792
1793         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1794                 rx_ring->cq_id);
1795
1796         if (work_done < budget) {
1797                 napi_complete(napi);
1798                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1799         }
1800         return work_done;
1801 }
1802
1803 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1804 {
1805         struct ql_adapter *qdev = netdev_priv(ndev);
1806
1807         qdev->vlgrp = grp;
1808         if (grp) {
1809                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1810                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1811                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1812         } else {
1813                 QPRINTK(qdev, IFUP, DEBUG,
1814                         "Turning off VLAN in NIC_RCV_CFG.\n");
1815                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1816         }
1817 }
1818
1819 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1820 {
1821         struct ql_adapter *qdev = netdev_priv(ndev);
1822         u32 enable_bit = MAC_ADDR_E;
1823         int status;
1824
1825         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1826         if (status)
1827                 return;
1828         spin_lock(&qdev->hw_lock);
1829         if (ql_set_mac_addr_reg
1830             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1831                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1832         }
1833         spin_unlock(&qdev->hw_lock);
1834         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1835 }
1836
1837 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1838 {
1839         struct ql_adapter *qdev = netdev_priv(ndev);
1840         u32 enable_bit = 0;
1841         int status;
1842
1843         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1844         if (status)
1845                 return;
1846
1847         spin_lock(&qdev->hw_lock);
1848         if (ql_set_mac_addr_reg
1849             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1850                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1851         }
1852         spin_unlock(&qdev->hw_lock);
1853         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1854
1855 }
1856
1857 /* Worker thread to process a given rx_ring that is dedicated
1858  * to outbound completions.
1859  */
1860 static void ql_tx_clean(struct work_struct *work)
1861 {
1862         struct rx_ring *rx_ring =
1863             container_of(work, struct rx_ring, rx_work.work);
1864         ql_clean_outbound_rx_ring(rx_ring);
1865         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1866
1867 }
1868
1869 /* Worker thread to process a given rx_ring that is dedicated
1870  * to inbound completions.
1871  */
1872 static void ql_rx_clean(struct work_struct *work)
1873 {
1874         struct rx_ring *rx_ring =
1875             container_of(work, struct rx_ring, rx_work.work);
1876         ql_clean_inbound_rx_ring(rx_ring, 64);
1877         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1878 }
1879
1880 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1881 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1882 {
1883         struct rx_ring *rx_ring = dev_id;
1884         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1885                               &rx_ring->rx_work, 0);
1886         return IRQ_HANDLED;
1887 }
1888
1889 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1890 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1891 {
1892         struct rx_ring *rx_ring = dev_id;
1893         napi_schedule(&rx_ring->napi);
1894         return IRQ_HANDLED;
1895 }
1896
1897 /* This handles a fatal error, MPI activity, and the default
1898  * rx_ring in an MSI-X multiple vector environment.
1899  * In MSI/Legacy environment it also process the rest of
1900  * the rx_rings.
1901  */
1902 static irqreturn_t qlge_isr(int irq, void *dev_id)
1903 {
1904         struct rx_ring *rx_ring = dev_id;
1905         struct ql_adapter *qdev = rx_ring->qdev;
1906         struct intr_context *intr_context = &qdev->intr_context[0];
1907         u32 var;
1908         int i;
1909         int work_done = 0;
1910
1911         spin_lock(&qdev->hw_lock);
1912         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1913                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1914                 spin_unlock(&qdev->hw_lock);
1915                 return IRQ_NONE;
1916         }
1917         spin_unlock(&qdev->hw_lock);
1918
1919         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1920
1921         /*
1922          * Check for fatal error.
1923          */
1924         if (var & STS_FE) {
1925                 ql_queue_asic_error(qdev);
1926                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1927                 var = ql_read32(qdev, ERR_STS);
1928                 QPRINTK(qdev, INTR, ERR,
1929                         "Resetting chip. Error Status Register = 0x%x\n", var);
1930                 return IRQ_HANDLED;
1931         }
1932
1933         /*
1934          * Check MPI processor activity.
1935          */
1936         if (var & STS_PI) {
1937                 /*
1938                  * We've got an async event or mailbox completion.
1939                  * Handle it and clear the source of the interrupt.
1940                  */
1941                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1942                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1943                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1944                                       &qdev->mpi_work, 0);
1945                 work_done++;
1946         }
1947
1948         /*
1949          * Check the default queue and wake handler if active.
1950          */
1951         rx_ring = &qdev->rx_ring[0];
1952         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1953                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1954                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1955                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1956                                       &rx_ring->rx_work, 0);
1957                 work_done++;
1958         }
1959
1960         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1961                 /*
1962                  * Start the DPC for each active queue.
1963                  */
1964                 for (i = 1; i < qdev->rx_ring_count; i++) {
1965                         rx_ring = &qdev->rx_ring[i];
1966                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1967                             rx_ring->cnsmr_idx) {
1968                                 QPRINTK(qdev, INTR, INFO,
1969                                         "Waking handler for rx_ring[%d].\n", i);
1970                                 ql_disable_completion_interrupt(qdev,
1971                                                                 intr_context->
1972                                                                 intr);
1973                                 if (i < qdev->rss_ring_first_cq_id)
1974                                         queue_delayed_work_on(rx_ring->cpu,
1975                                                               qdev->q_workqueue,
1976                                                               &rx_ring->rx_work,
1977                                                               0);
1978                                 else
1979                                         napi_schedule(&rx_ring->napi);
1980                                 work_done++;
1981                         }
1982                 }
1983         }
1984         ql_enable_completion_interrupt(qdev, intr_context->intr);
1985         return work_done ? IRQ_HANDLED : IRQ_NONE;
1986 }
1987
1988 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1989 {
1990
1991         if (skb_is_gso(skb)) {
1992                 int err;
1993                 if (skb_header_cloned(skb)) {
1994                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1995                         if (err)
1996                                 return err;
1997                 }
1998
1999                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2000                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2001                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2002                 mac_iocb_ptr->total_hdrs_len =
2003                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2004                 mac_iocb_ptr->net_trans_offset =
2005                     cpu_to_le16(skb_network_offset(skb) |
2006                                 skb_transport_offset(skb)
2007                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
2008                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2009                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2010                 if (likely(skb->protocol == htons(ETH_P_IP))) {
2011                         struct iphdr *iph = ip_hdr(skb);
2012                         iph->check = 0;
2013                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2014                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2015                                                                  iph->daddr, 0,
2016                                                                  IPPROTO_TCP,
2017                                                                  0);
2018                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2019                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2020                         tcp_hdr(skb)->check =
2021                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2022                                              &ipv6_hdr(skb)->daddr,
2023                                              0, IPPROTO_TCP, 0);
2024                 }
2025                 return 1;
2026         }
2027         return 0;
2028 }
2029
2030 static void ql_hw_csum_setup(struct sk_buff *skb,
2031                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2032 {
2033         int len;
2034         struct iphdr *iph = ip_hdr(skb);
2035         __sum16 *check;
2036         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2037         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2038         mac_iocb_ptr->net_trans_offset =
2039                 cpu_to_le16(skb_network_offset(skb) |
2040                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2041
2042         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2043         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2044         if (likely(iph->protocol == IPPROTO_TCP)) {
2045                 check = &(tcp_hdr(skb)->check);
2046                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2047                 mac_iocb_ptr->total_hdrs_len =
2048                     cpu_to_le16(skb_transport_offset(skb) +
2049                                 (tcp_hdr(skb)->doff << 2));
2050         } else {
2051                 check = &(udp_hdr(skb)->check);
2052                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2053                 mac_iocb_ptr->total_hdrs_len =
2054                     cpu_to_le16(skb_transport_offset(skb) +
2055                                 sizeof(struct udphdr));
2056         }
2057         *check = ~csum_tcpudp_magic(iph->saddr,
2058                                     iph->daddr, len, iph->protocol, 0);
2059 }
2060
2061 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2062 {
2063         struct tx_ring_desc *tx_ring_desc;
2064         struct ob_mac_iocb_req *mac_iocb_ptr;
2065         struct ql_adapter *qdev = netdev_priv(ndev);
2066         int tso;
2067         struct tx_ring *tx_ring;
2068         u32 tx_ring_idx = (u32) skb->queue_mapping;
2069
2070         tx_ring = &qdev->tx_ring[tx_ring_idx];
2071
2072         if (skb_padto(skb, ETH_ZLEN))
2073                 return NETDEV_TX_OK;
2074
2075         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2076                 QPRINTK(qdev, TX_QUEUED, INFO,
2077                         "%s: shutting down tx queue %d du to lack of resources.\n",
2078                         __func__, tx_ring_idx);
2079                 netif_stop_subqueue(ndev, tx_ring->wq_id);
2080                 atomic_inc(&tx_ring->queue_stopped);
2081                 return NETDEV_TX_BUSY;
2082         }
2083         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2084         mac_iocb_ptr = tx_ring_desc->queue_entry;
2085         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2086
2087         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2088         mac_iocb_ptr->tid = tx_ring_desc->index;
2089         /* We use the upper 32-bits to store the tx queue for this IO.
2090          * When we get the completion we can use it to establish the context.
2091          */
2092         mac_iocb_ptr->txq_idx = tx_ring_idx;
2093         tx_ring_desc->skb = skb;
2094
2095         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2096
2097         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2098                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2099                         vlan_tx_tag_get(skb));
2100                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2101                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2102         }
2103         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2104         if (tso < 0) {
2105                 dev_kfree_skb_any(skb);
2106                 return NETDEV_TX_OK;
2107         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2108                 ql_hw_csum_setup(skb,
2109                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2110         }
2111         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2112                         NETDEV_TX_OK) {
2113                 QPRINTK(qdev, TX_QUEUED, ERR,
2114                                 "Could not map the segments.\n");
2115                 return NETDEV_TX_BUSY;
2116         }
2117         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2118         tx_ring->prod_idx++;
2119         if (tx_ring->prod_idx == tx_ring->wq_len)
2120                 tx_ring->prod_idx = 0;
2121         wmb();
2122
2123         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2124         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2125                 tx_ring->prod_idx, skb->len);
2126
2127         atomic_dec(&tx_ring->tx_count);
2128         return NETDEV_TX_OK;
2129 }
2130
2131 static void ql_free_shadow_space(struct ql_adapter *qdev)
2132 {
2133         if (qdev->rx_ring_shadow_reg_area) {
2134                 pci_free_consistent(qdev->pdev,
2135                                     PAGE_SIZE,
2136                                     qdev->rx_ring_shadow_reg_area,
2137                                     qdev->rx_ring_shadow_reg_dma);
2138                 qdev->rx_ring_shadow_reg_area = NULL;
2139         }
2140         if (qdev->tx_ring_shadow_reg_area) {
2141                 pci_free_consistent(qdev->pdev,
2142                                     PAGE_SIZE,
2143                                     qdev->tx_ring_shadow_reg_area,
2144                                     qdev->tx_ring_shadow_reg_dma);
2145                 qdev->tx_ring_shadow_reg_area = NULL;
2146         }
2147 }
2148
2149 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2150 {
2151         qdev->rx_ring_shadow_reg_area =
2152             pci_alloc_consistent(qdev->pdev,
2153                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2154         if (qdev->rx_ring_shadow_reg_area == NULL) {
2155                 QPRINTK(qdev, IFUP, ERR,
2156                         "Allocation of RX shadow space failed.\n");
2157                 return -ENOMEM;
2158         }
2159         memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2160         qdev->tx_ring_shadow_reg_area =
2161             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2162                                  &qdev->tx_ring_shadow_reg_dma);
2163         if (qdev->tx_ring_shadow_reg_area == NULL) {
2164                 QPRINTK(qdev, IFUP, ERR,
2165                         "Allocation of TX shadow space failed.\n");
2166                 goto err_wqp_sh_area;
2167         }
2168         memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2169         return 0;
2170
2171 err_wqp_sh_area:
2172         pci_free_consistent(qdev->pdev,
2173                             PAGE_SIZE,
2174                             qdev->rx_ring_shadow_reg_area,
2175                             qdev->rx_ring_shadow_reg_dma);
2176         return -ENOMEM;
2177 }
2178
2179 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2180 {
2181         struct tx_ring_desc *tx_ring_desc;
2182         int i;
2183         struct ob_mac_iocb_req *mac_iocb_ptr;
2184
2185         mac_iocb_ptr = tx_ring->wq_base;
2186         tx_ring_desc = tx_ring->q;
2187         for (i = 0; i < tx_ring->wq_len; i++) {
2188                 tx_ring_desc->index = i;
2189                 tx_ring_desc->skb = NULL;
2190                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2191                 mac_iocb_ptr++;
2192                 tx_ring_desc++;
2193         }
2194         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2195         atomic_set(&tx_ring->queue_stopped, 0);
2196 }
2197
2198 static void ql_free_tx_resources(struct ql_adapter *qdev,
2199                                  struct tx_ring *tx_ring)
2200 {
2201         if (tx_ring->wq_base) {
2202                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2203                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2204                 tx_ring->wq_base = NULL;
2205         }
2206         kfree(tx_ring->q);
2207         tx_ring->q = NULL;
2208 }
2209
2210 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2211                                  struct tx_ring *tx_ring)
2212 {
2213         tx_ring->wq_base =
2214             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2215                                  &tx_ring->wq_base_dma);
2216
2217         if ((tx_ring->wq_base == NULL)
2218             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2219                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2220                 return -ENOMEM;
2221         }
2222         tx_ring->q =
2223             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2224         if (tx_ring->q == NULL)
2225                 goto err;
2226
2227         return 0;
2228 err:
2229         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2230                             tx_ring->wq_base, tx_ring->wq_base_dma);
2231         return -ENOMEM;
2232 }
2233
2234 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2235 {
2236         int i;
2237         struct bq_desc *lbq_desc;
2238
2239         for (i = 0; i < rx_ring->lbq_len; i++) {
2240                 lbq_desc = &rx_ring->lbq[i];
2241                 if (lbq_desc->p.lbq_page) {
2242                         pci_unmap_page(qdev->pdev,
2243                                        pci_unmap_addr(lbq_desc, mapaddr),
2244                                        pci_unmap_len(lbq_desc, maplen),
2245                                        PCI_DMA_FROMDEVICE);
2246
2247                         put_page(lbq_desc->p.lbq_page);
2248                         lbq_desc->p.lbq_page = NULL;
2249                 }
2250         }
2251 }
2252
2253 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2254 {
2255         int i;
2256         struct bq_desc *sbq_desc;
2257
2258         for (i = 0; i < rx_ring->sbq_len; i++) {
2259                 sbq_desc = &rx_ring->sbq[i];
2260                 if (sbq_desc == NULL) {
2261                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2262                         return;
2263                 }
2264                 if (sbq_desc->p.skb) {
2265                         pci_unmap_single(qdev->pdev,
2266                                          pci_unmap_addr(sbq_desc, mapaddr),
2267                                          pci_unmap_len(sbq_desc, maplen),
2268                                          PCI_DMA_FROMDEVICE);
2269                         dev_kfree_skb(sbq_desc->p.skb);
2270                         sbq_desc->p.skb = NULL;
2271                 }
2272         }
2273 }
2274
2275 /* Free all large and small rx buffers associated
2276  * with the completion queues for this device.
2277  */
2278 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2279 {
2280         int i;
2281         struct rx_ring *rx_ring;
2282
2283         for (i = 0; i < qdev->rx_ring_count; i++) {
2284                 rx_ring = &qdev->rx_ring[i];
2285                 if (rx_ring->lbq)
2286                         ql_free_lbq_buffers(qdev, rx_ring);
2287                 if (rx_ring->sbq)
2288                         ql_free_sbq_buffers(qdev, rx_ring);
2289         }
2290 }
2291
2292 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2293 {
2294         struct rx_ring *rx_ring;
2295         int i;
2296
2297         for (i = 0; i < qdev->rx_ring_count; i++) {
2298                 rx_ring = &qdev->rx_ring[i];
2299                 if (rx_ring->type != TX_Q)
2300                         ql_update_buffer_queues(qdev, rx_ring);
2301         }
2302 }
2303
2304 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2305                                 struct rx_ring *rx_ring)
2306 {
2307         int i;
2308         struct bq_desc *lbq_desc;
2309         __le64 *bq = rx_ring->lbq_base;
2310
2311         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2312         for (i = 0; i < rx_ring->lbq_len; i++) {
2313                 lbq_desc = &rx_ring->lbq[i];
2314                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2315                 lbq_desc->index = i;
2316                 lbq_desc->addr = bq;
2317                 bq++;
2318         }
2319 }
2320
2321 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2322                                 struct rx_ring *rx_ring)
2323 {
2324         int i;
2325         struct bq_desc *sbq_desc;
2326         __le64 *bq = rx_ring->sbq_base;
2327
2328         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2329         for (i = 0; i < rx_ring->sbq_len; i++) {
2330                 sbq_desc = &rx_ring->sbq[i];
2331                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2332                 sbq_desc->index = i;
2333                 sbq_desc->addr = bq;
2334                 bq++;
2335         }
2336 }
2337
2338 static void ql_free_rx_resources(struct ql_adapter *qdev,
2339                                  struct rx_ring *rx_ring)
2340 {
2341         /* Free the small buffer queue. */
2342         if (rx_ring->sbq_base) {
2343                 pci_free_consistent(qdev->pdev,
2344                                     rx_ring->sbq_size,
2345                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2346                 rx_ring->sbq_base = NULL;
2347         }
2348
2349         /* Free the small buffer queue control blocks. */
2350         kfree(rx_ring->sbq);
2351         rx_ring->sbq = NULL;
2352
2353         /* Free the large buffer queue. */
2354         if (rx_ring->lbq_base) {
2355                 pci_free_consistent(qdev->pdev,
2356                                     rx_ring->lbq_size,
2357                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2358                 rx_ring->lbq_base = NULL;
2359         }
2360
2361         /* Free the large buffer queue control blocks. */
2362         kfree(rx_ring->lbq);
2363         rx_ring->lbq = NULL;
2364
2365         /* Free the rx queue. */
2366         if (rx_ring->cq_base) {
2367                 pci_free_consistent(qdev->pdev,
2368                                     rx_ring->cq_size,
2369                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2370                 rx_ring->cq_base = NULL;
2371         }
2372 }
2373
2374 /* Allocate queues and buffers for this completions queue based
2375  * on the values in the parameter structure. */
2376 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2377                                  struct rx_ring *rx_ring)
2378 {
2379
2380         /*
2381          * Allocate the completion queue for this rx_ring.
2382          */
2383         rx_ring->cq_base =
2384             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2385                                  &rx_ring->cq_base_dma);
2386
2387         if (rx_ring->cq_base == NULL) {
2388                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2389                 return -ENOMEM;
2390         }
2391
2392         if (rx_ring->sbq_len) {
2393                 /*
2394                  * Allocate small buffer queue.
2395                  */
2396                 rx_ring->sbq_base =
2397                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2398                                          &rx_ring->sbq_base_dma);
2399
2400                 if (rx_ring->sbq_base == NULL) {
2401                         QPRINTK(qdev, IFUP, ERR,
2402                                 "Small buffer queue allocation failed.\n");
2403                         goto err_mem;
2404                 }
2405
2406                 /*
2407                  * Allocate small buffer queue control blocks.
2408                  */
2409                 rx_ring->sbq =
2410                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2411                             GFP_KERNEL);
2412                 if (rx_ring->sbq == NULL) {
2413                         QPRINTK(qdev, IFUP, ERR,
2414                                 "Small buffer queue control block allocation failed.\n");
2415                         goto err_mem;
2416                 }
2417
2418                 ql_init_sbq_ring(qdev, rx_ring);
2419         }
2420
2421         if (rx_ring->lbq_len) {
2422                 /*
2423                  * Allocate large buffer queue.
2424                  */
2425                 rx_ring->lbq_base =
2426                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2427                                          &rx_ring->lbq_base_dma);
2428
2429                 if (rx_ring->lbq_base == NULL) {
2430                         QPRINTK(qdev, IFUP, ERR,
2431                                 "Large buffer queue allocation failed.\n");
2432                         goto err_mem;
2433                 }
2434                 /*
2435                  * Allocate large buffer queue control blocks.
2436                  */
2437                 rx_ring->lbq =
2438                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2439                             GFP_KERNEL);
2440                 if (rx_ring->lbq == NULL) {
2441                         QPRINTK(qdev, IFUP, ERR,
2442                                 "Large buffer queue control block allocation failed.\n");
2443                         goto err_mem;
2444                 }
2445
2446                 ql_init_lbq_ring(qdev, rx_ring);
2447         }
2448
2449         return 0;
2450
2451 err_mem:
2452         ql_free_rx_resources(qdev, rx_ring);
2453         return -ENOMEM;
2454 }
2455
2456 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2457 {
2458         struct tx_ring *tx_ring;
2459         struct tx_ring_desc *tx_ring_desc;
2460         int i, j;
2461
2462         /*
2463          * Loop through all queues and free
2464          * any resources.
2465          */
2466         for (j = 0; j < qdev->tx_ring_count; j++) {
2467                 tx_ring = &qdev->tx_ring[j];
2468                 for (i = 0; i < tx_ring->wq_len; i++) {
2469                         tx_ring_desc = &tx_ring->q[i];
2470                         if (tx_ring_desc && tx_ring_desc->skb) {
2471                                 QPRINTK(qdev, IFDOWN, ERR,
2472                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2473                                         tx_ring_desc->skb, j,
2474                                         tx_ring_desc->index);
2475                                 ql_unmap_send(qdev, tx_ring_desc,
2476                                               tx_ring_desc->map_cnt);
2477                                 dev_kfree_skb(tx_ring_desc->skb);
2478                                 tx_ring_desc->skb = NULL;
2479                         }
2480                 }
2481         }
2482 }
2483
2484 static void ql_free_mem_resources(struct ql_adapter *qdev)
2485 {
2486         int i;
2487
2488         for (i = 0; i < qdev->tx_ring_count; i++)
2489                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2490         for (i = 0; i < qdev->rx_ring_count; i++)
2491                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2492         ql_free_shadow_space(qdev);
2493 }
2494
2495 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2496 {
2497         int i;
2498
2499         /* Allocate space for our shadow registers and such. */
2500         if (ql_alloc_shadow_space(qdev))
2501                 return -ENOMEM;
2502
2503         for (i = 0; i < qdev->rx_ring_count; i++) {
2504                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2505                         QPRINTK(qdev, IFUP, ERR,
2506                                 "RX resource allocation failed.\n");
2507                         goto err_mem;
2508                 }
2509         }
2510         /* Allocate tx queue resources */
2511         for (i = 0; i < qdev->tx_ring_count; i++) {
2512                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2513                         QPRINTK(qdev, IFUP, ERR,
2514                                 "TX resource allocation failed.\n");
2515                         goto err_mem;
2516                 }
2517         }
2518         return 0;
2519
2520 err_mem:
2521         ql_free_mem_resources(qdev);
2522         return -ENOMEM;
2523 }
2524
2525 /* Set up the rx ring control block and pass it to the chip.
2526  * The control block is defined as
2527  * "Completion Queue Initialization Control Block", or cqicb.
2528  */
2529 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2530 {
2531         struct cqicb *cqicb = &rx_ring->cqicb;
2532         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2533             (rx_ring->cq_id * sizeof(u64) * 4);
2534         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2535             (rx_ring->cq_id * sizeof(u64) * 4);
2536         void __iomem *doorbell_area =
2537             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2538         int err = 0;
2539         u16 bq_len;
2540         u64 tmp;
2541
2542         /* Set up the shadow registers for this ring. */
2543         rx_ring->prod_idx_sh_reg = shadow_reg;
2544         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2545         shadow_reg += sizeof(u64);
2546         shadow_reg_dma += sizeof(u64);
2547         rx_ring->lbq_base_indirect = shadow_reg;
2548         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2549         shadow_reg += sizeof(u64);
2550         shadow_reg_dma += sizeof(u64);
2551         rx_ring->sbq_base_indirect = shadow_reg;
2552         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2553
2554         /* PCI doorbell mem area + 0x00 for consumer index register */
2555         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2556         rx_ring->cnsmr_idx = 0;
2557         rx_ring->curr_entry = rx_ring->cq_base;
2558
2559         /* PCI doorbell mem area + 0x04 for valid register */
2560         rx_ring->valid_db_reg = doorbell_area + 0x04;
2561
2562         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2563         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2564
2565         /* PCI doorbell mem area + 0x1c */
2566         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2567
2568         memset((void *)cqicb, 0, sizeof(struct cqicb));
2569         cqicb->msix_vect = rx_ring->irq;
2570
2571         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2572         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2573
2574         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2575
2576         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2577
2578         /*
2579          * Set up the control block load flags.
2580          */
2581         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2582             FLAGS_LV |          /* Load MSI-X vector */
2583             FLAGS_LI;           /* Load irq delay values */
2584         if (rx_ring->lbq_len) {
2585                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2586                 tmp = (u64)rx_ring->lbq_base_dma;;
2587                 *((__le64 *) rx_ring->lbq_base_indirect) = cpu_to_le64(tmp);
2588                 cqicb->lbq_addr =
2589                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2590                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2591                         (u16) rx_ring->lbq_buf_size;
2592                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2593                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2594                         (u16) rx_ring->lbq_len;
2595                 cqicb->lbq_len = cpu_to_le16(bq_len);
2596                 rx_ring->lbq_prod_idx = 0;
2597                 rx_ring->lbq_curr_idx = 0;
2598                 rx_ring->lbq_clean_idx = 0;
2599                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2600         }
2601         if (rx_ring->sbq_len) {
2602                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2603                 tmp = (u64)rx_ring->sbq_base_dma;;
2604                 *((__le64 *) rx_ring->sbq_base_indirect) = cpu_to_le64(tmp);
2605                 cqicb->sbq_addr =
2606                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2607                 cqicb->sbq_buf_size =
2608                     cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2609                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2610                         (u16) rx_ring->sbq_len;
2611                 cqicb->sbq_len = cpu_to_le16(bq_len);
2612                 rx_ring->sbq_prod_idx = 0;
2613                 rx_ring->sbq_curr_idx = 0;
2614                 rx_ring->sbq_clean_idx = 0;
2615                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2616         }
2617         switch (rx_ring->type) {
2618         case TX_Q:
2619                 /* If there's only one interrupt, then we use
2620                  * worker threads to process the outbound
2621                  * completion handling rx_rings. We do this so
2622                  * they can be run on multiple CPUs. There is
2623                  * room to play with this more where we would only
2624                  * run in a worker if there are more than x number
2625                  * of outbound completions on the queue and more
2626                  * than one queue active.  Some threshold that
2627                  * would indicate a benefit in spite of the cost
2628                  * of a context switch.
2629                  * If there's more than one interrupt, then the
2630                  * outbound completions are processed in the ISR.
2631                  */
2632                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2633                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2634                 else {
2635                         /* With all debug warnings on we see a WARN_ON message
2636                          * when we free the skb in the interrupt context.
2637                          */
2638                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2639                 }
2640                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2641                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2642                 break;
2643         case DEFAULT_Q:
2644                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2645                 cqicb->irq_delay = 0;
2646                 cqicb->pkt_delay = 0;
2647                 break;
2648         case RX_Q:
2649                 /* Inbound completion handling rx_rings run in
2650                  * separate NAPI contexts.
2651                  */
2652                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2653                                64);
2654                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2655                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2656                 break;
2657         default:
2658                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2659                         rx_ring->type);
2660         }
2661         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2662         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2663                            CFG_LCQ, rx_ring->cq_id);
2664         if (err) {
2665                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2666                 return err;
2667         }
2668         return err;
2669 }
2670
2671 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2672 {
2673         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2674         void __iomem *doorbell_area =
2675             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2676         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2677             (tx_ring->wq_id * sizeof(u64));
2678         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2679             (tx_ring->wq_id * sizeof(u64));
2680         int err = 0;
2681
2682         /*
2683          * Assign doorbell registers for this tx_ring.
2684          */
2685         /* TX PCI doorbell mem area for tx producer index */
2686         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2687         tx_ring->prod_idx = 0;
2688         /* TX PCI doorbell mem area + 0x04 */
2689         tx_ring->valid_db_reg = doorbell_area + 0x04;
2690
2691         /*
2692          * Assign shadow registers for this tx_ring.
2693          */
2694         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2695         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2696
2697         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2698         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2699                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2700         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2701         wqicb->rid = 0;
2702         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2703
2704         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2705
2706         ql_init_tx_ring(qdev, tx_ring);
2707
2708         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2709                            (u16) tx_ring->wq_id);
2710         if (err) {
2711                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2712                 return err;
2713         }
2714         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2715         return err;
2716 }
2717
2718 static void ql_disable_msix(struct ql_adapter *qdev)
2719 {
2720         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2721                 pci_disable_msix(qdev->pdev);
2722                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2723                 kfree(qdev->msi_x_entry);
2724                 qdev->msi_x_entry = NULL;
2725         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2726                 pci_disable_msi(qdev->pdev);
2727                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2728         }
2729 }
2730
2731 static void ql_enable_msix(struct ql_adapter *qdev)
2732 {
2733         int i;
2734
2735         qdev->intr_count = 1;
2736         /* Get the MSIX vectors. */
2737         if (irq_type == MSIX_IRQ) {
2738                 /* Try to alloc space for the msix struct,
2739                  * if it fails then go to MSI/legacy.
2740                  */
2741                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2742                                             sizeof(struct msix_entry),
2743                                             GFP_KERNEL);
2744                 if (!qdev->msi_x_entry) {
2745                         irq_type = MSI_IRQ;
2746                         goto msi;
2747                 }
2748
2749                 for (i = 0; i < qdev->rx_ring_count; i++)
2750                         qdev->msi_x_entry[i].entry = i;
2751
2752                 if (!pci_enable_msix
2753                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2754                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2755                         qdev->intr_count = qdev->rx_ring_count;
2756                         QPRINTK(qdev, IFUP, DEBUG,
2757                                 "MSI-X Enabled, got %d vectors.\n",
2758                                 qdev->intr_count);
2759                         return;
2760                 } else {
2761                         kfree(qdev->msi_x_entry);
2762                         qdev->msi_x_entry = NULL;
2763                         QPRINTK(qdev, IFUP, WARNING,
2764                                 "MSI-X Enable failed, trying MSI.\n");
2765                         irq_type = MSI_IRQ;
2766                 }
2767         }
2768 msi:
2769         if (irq_type == MSI_IRQ) {
2770                 if (!pci_enable_msi(qdev->pdev)) {
2771                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2772                         QPRINTK(qdev, IFUP, INFO,
2773                                 "Running with MSI interrupts.\n");
2774                         return;
2775                 }
2776         }
2777         irq_type = LEG_IRQ;
2778         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2779 }
2780
2781 /*
2782  * Here we build the intr_context structures based on
2783  * our rx_ring count and intr vector count.
2784  * The intr_context structure is used to hook each vector
2785  * to possibly different handlers.
2786  */
2787 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2788 {
2789         int i = 0;
2790         struct intr_context *intr_context = &qdev->intr_context[0];
2791
2792         ql_enable_msix(qdev);
2793
2794         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2795                 /* Each rx_ring has it's
2796                  * own intr_context since we have separate
2797                  * vectors for each queue.
2798                  * This only true when MSI-X is enabled.
2799                  */
2800                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2801                         qdev->rx_ring[i].irq = i;
2802                         intr_context->intr = i;
2803                         intr_context->qdev = qdev;
2804                         /*
2805                          * We set up each vectors enable/disable/read bits so
2806                          * there's no bit/mask calculations in the critical path.
2807                          */
2808                         intr_context->intr_en_mask =
2809                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2810                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2811                             | i;
2812                         intr_context->intr_dis_mask =
2813                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2814                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2815                             INTR_EN_IHD | i;
2816                         intr_context->intr_read_mask =
2817                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2818                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2819                             i;
2820
2821                         if (i == 0) {
2822                                 /*
2823                                  * Default queue handles bcast/mcast plus
2824                                  * async events.  Needs buffers.
2825                                  */
2826                                 intr_context->handler = qlge_isr;
2827                                 sprintf(intr_context->name, "%s-default-queue",
2828                                         qdev->ndev->name);
2829                         } else if (i < qdev->rss_ring_first_cq_id) {
2830                                 /*
2831                                  * Outbound queue is for outbound completions only.
2832                                  */
2833                                 intr_context->handler = qlge_msix_tx_isr;
2834                                 sprintf(intr_context->name, "%s-tx-%d",
2835                                         qdev->ndev->name, i);
2836                         } else {
2837                                 /*
2838                                  * Inbound queues handle unicast frames only.
2839                                  */
2840                                 intr_context->handler = qlge_msix_rx_isr;
2841                                 sprintf(intr_context->name, "%s-rx-%d",
2842                                         qdev->ndev->name, i);
2843                         }
2844                 }
2845         } else {
2846                 /*
2847                  * All rx_rings use the same intr_context since
2848                  * there is only one vector.
2849                  */
2850                 intr_context->intr = 0;
2851                 intr_context->qdev = qdev;
2852                 /*
2853                  * We set up each vectors enable/disable/read bits so
2854                  * there's no bit/mask calculations in the critical path.
2855                  */
2856                 intr_context->intr_en_mask =
2857                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2858                 intr_context->intr_dis_mask =
2859                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2860                     INTR_EN_TYPE_DISABLE;
2861                 intr_context->intr_read_mask =
2862                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2863                 /*
2864                  * Single interrupt means one handler for all rings.
2865                  */
2866                 intr_context->handler = qlge_isr;
2867                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2868                 for (i = 0; i < qdev->rx_ring_count; i++)
2869                         qdev->rx_ring[i].irq = 0;
2870         }
2871 }
2872
2873 static void ql_free_irq(struct ql_adapter *qdev)
2874 {
2875         int i;
2876         struct intr_context *intr_context = &qdev->intr_context[0];
2877
2878         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2879                 if (intr_context->hooked) {
2880                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2881                                 free_irq(qdev->msi_x_entry[i].vector,
2882                                          &qdev->rx_ring[i]);
2883                                 QPRINTK(qdev, IFDOWN, DEBUG,
2884                                         "freeing msix interrupt %d.\n", i);
2885                         } else {
2886                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2887                                 QPRINTK(qdev, IFDOWN, DEBUG,
2888                                         "freeing msi interrupt %d.\n", i);
2889                         }
2890                 }
2891         }
2892         ql_disable_msix(qdev);
2893 }
2894
2895 static int ql_request_irq(struct ql_adapter *qdev)
2896 {
2897         int i;
2898         int status = 0;
2899         struct pci_dev *pdev = qdev->pdev;
2900         struct intr_context *intr_context = &qdev->intr_context[0];
2901
2902         ql_resolve_queues_to_irqs(qdev);
2903
2904         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2905                 atomic_set(&intr_context->irq_cnt, 0);
2906                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2907                         status = request_irq(qdev->msi_x_entry[i].vector,
2908                                              intr_context->handler,
2909                                              0,
2910                                              intr_context->name,
2911                                              &qdev->rx_ring[i]);
2912                         if (status) {
2913                                 QPRINTK(qdev, IFUP, ERR,
2914                                         "Failed request for MSIX interrupt %d.\n",
2915                                         i);
2916                                 goto err_irq;
2917                         } else {
2918                                 QPRINTK(qdev, IFUP, DEBUG,
2919                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2920                                         i,
2921                                         qdev->rx_ring[i].type ==
2922                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2923                                         qdev->rx_ring[i].type ==
2924                                         TX_Q ? "TX_Q" : "",
2925                                         qdev->rx_ring[i].type ==
2926                                         RX_Q ? "RX_Q" : "", intr_context->name);
2927                         }
2928                 } else {
2929                         QPRINTK(qdev, IFUP, DEBUG,
2930                                 "trying msi or legacy interrupts.\n");
2931                         QPRINTK(qdev, IFUP, DEBUG,
2932                                 "%s: irq = %d.\n", __func__, pdev->irq);
2933                         QPRINTK(qdev, IFUP, DEBUG,
2934                                 "%s: context->name = %s.\n", __func__,
2935                                intr_context->name);
2936                         QPRINTK(qdev, IFUP, DEBUG,
2937                                 "%s: dev_id = 0x%p.\n", __func__,
2938                                &qdev->rx_ring[0]);
2939                         status =
2940                             request_irq(pdev->irq, qlge_isr,
2941                                         test_bit(QL_MSI_ENABLED,
2942                                                  &qdev->
2943                                                  flags) ? 0 : IRQF_SHARED,
2944                                         intr_context->name, &qdev->rx_ring[0]);
2945                         if (status)
2946                                 goto err_irq;
2947
2948                         QPRINTK(qdev, IFUP, ERR,
2949                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2950                                 i,
2951                                 qdev->rx_ring[0].type ==
2952                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2953                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2954                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2955                                 intr_context->name);
2956                 }
2957                 intr_context->hooked = 1;
2958         }
2959         return status;
2960 err_irq:
2961         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2962         ql_free_irq(qdev);
2963         return status;
2964 }
2965
2966 static int ql_start_rss(struct ql_adapter *qdev)
2967 {
2968         struct ricb *ricb = &qdev->ricb;
2969         int status = 0;
2970         int i;
2971         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2972
2973         memset((void *)ricb, 0, sizeof(ricb));
2974
2975         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2976         ricb->flags =
2977             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2978              RSS_RT6);
2979         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2980
2981         /*
2982          * Fill out the Indirection Table.
2983          */
2984         for (i = 0; i < 256; i++)
2985                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2986
2987         /*
2988          * Random values for the IPv6 and IPv4 Hash Keys.
2989          */
2990         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2991         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2992
2993         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2994
2995         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2996         if (status) {
2997                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2998                 return status;
2999         }
3000         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
3001         return status;
3002 }
3003
3004 /* Initialize the frame-to-queue routing. */
3005 static int ql_route_initialize(struct ql_adapter *qdev)
3006 {
3007         int status = 0;
3008         int i;
3009
3010         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3011         if (status)
3012                 return status;
3013
3014         /* Clear all the entries in the routing table. */
3015         for (i = 0; i < 16; i++) {
3016                 status = ql_set_routing_reg(qdev, i, 0, 0);
3017                 if (status) {
3018                         QPRINTK(qdev, IFUP, ERR,
3019                                 "Failed to init routing register for CAM packets.\n");
3020                         goto exit;
3021                 }
3022         }
3023
3024         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3025         if (status) {
3026                 QPRINTK(qdev, IFUP, ERR,
3027                         "Failed to init routing register for error packets.\n");
3028                 goto exit;
3029         }
3030         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3031         if (status) {
3032                 QPRINTK(qdev, IFUP, ERR,
3033                         "Failed to init routing register for broadcast packets.\n");
3034                 goto exit;
3035         }
3036         /* If we have more than one inbound queue, then turn on RSS in the
3037          * routing block.
3038          */
3039         if (qdev->rss_ring_count > 1) {
3040                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3041                                         RT_IDX_RSS_MATCH, 1);
3042                 if (status) {
3043                         QPRINTK(qdev, IFUP, ERR,
3044                                 "Failed to init routing register for MATCH RSS packets.\n");
3045                         goto exit;
3046                 }
3047         }
3048
3049         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3050                                     RT_IDX_CAM_HIT, 1);
3051         if (status)
3052                 QPRINTK(qdev, IFUP, ERR,
3053                         "Failed to init routing register for CAM packets.\n");
3054 exit:
3055         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3056         return status;
3057 }
3058
3059 int ql_cam_route_initialize(struct ql_adapter *qdev)
3060 {
3061         int status;
3062
3063         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3064         if (status)
3065                 return status;
3066         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3067                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3068         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3069         if (status) {
3070                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3071                 return status;
3072         }
3073
3074         status = ql_route_initialize(qdev);
3075         if (status)
3076                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3077
3078         return status;
3079 }
3080
3081 static int ql_adapter_initialize(struct ql_adapter *qdev)
3082 {
3083         u32 value, mask;
3084         int i;
3085         int status = 0;
3086
3087         /*
3088          * Set up the System register to halt on errors.
3089          */
3090         value = SYS_EFE | SYS_FAE;
3091         mask = value << 16;
3092         ql_write32(qdev, SYS, mask | value);
3093
3094         /* Set the default queue, and VLAN behavior. */
3095         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3096         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3097         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3098
3099         /* Set the MPI interrupt to enabled. */
3100         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3101
3102         /* Enable the function, set pagesize, enable error checking. */
3103         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3104             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3105
3106         /* Set/clear header splitting. */
3107         mask = FSC_VM_PAGESIZE_MASK |
3108             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3109         ql_write32(qdev, FSC, mask | value);
3110
3111         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3112                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3113
3114         /* Start up the rx queues. */
3115         for (i = 0; i < qdev->rx_ring_count; i++) {
3116                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3117                 if (status) {
3118                         QPRINTK(qdev, IFUP, ERR,
3119                                 "Failed to start rx ring[%d].\n", i);
3120                         return status;
3121                 }
3122         }
3123
3124         /* If there is more than one inbound completion queue
3125          * then download a RICB to configure RSS.
3126          */
3127         if (qdev->rss_ring_count > 1) {
3128                 status = ql_start_rss(qdev);
3129                 if (status) {
3130                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3131                         return status;
3132                 }
3133         }
3134
3135         /* Start up the tx queues. */
3136         for (i = 0; i < qdev->tx_ring_count; i++) {
3137                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3138                 if (status) {
3139                         QPRINTK(qdev, IFUP, ERR,
3140                                 "Failed to start tx ring[%d].\n", i);
3141                         return status;
3142                 }
3143         }
3144
3145         /* Initialize the port and set the max framesize. */
3146         status = qdev->nic_ops->port_initialize(qdev);
3147        if (status) {
3148               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3149               return status;
3150        }
3151
3152         /* Set up the MAC address and frame routing filter. */
3153         status = ql_cam_route_initialize(qdev);
3154         if (status) {
3155                 QPRINTK(qdev, IFUP, ERR,
3156                                 "Failed to init CAM/Routing tables.\n");
3157                 return status;
3158         }
3159
3160         /* Start NAPI for the RSS queues. */
3161         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3162                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3163                         i);
3164                 napi_enable(&qdev->rx_ring[i].napi);
3165         }
3166
3167         return status;
3168 }
3169
3170 /* Issue soft reset to chip. */
3171 static int ql_adapter_reset(struct ql_adapter *qdev)
3172 {
3173         u32 value;
3174         int status = 0;
3175         unsigned long end_jiffies = jiffies +
3176                 max((unsigned long)1, usecs_to_jiffies(30));
3177
3178         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3179
3180         do {
3181                 value = ql_read32(qdev, RST_FO);
3182                 if ((value & RST_FO_FR) == 0)
3183                         break;
3184                 cpu_relax();
3185         } while (time_before(jiffies, end_jiffies));
3186
3187         if (value & RST_FO_FR) {
3188                 QPRINTK(qdev, IFDOWN, ERR,
3189                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3190                 status = -ETIMEDOUT;
3191         }
3192
3193         return status;
3194 }
3195
3196 static void ql_display_dev_info(struct net_device *ndev)
3197 {
3198         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3199
3200         QPRINTK(qdev, PROBE, INFO,
3201                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3202                 "XG Roll = %d, XG Rev = %d.\n",
3203                 qdev->func,
3204                 qdev->chip_rev_id & 0x0000000f,
3205                 qdev->chip_rev_id >> 4 & 0x0000000f,
3206                 qdev->chip_rev_id >> 8 & 0x0000000f,
3207                 qdev->chip_rev_id >> 12 & 0x0000000f);
3208         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3209 }
3210
3211 static int ql_adapter_down(struct ql_adapter *qdev)
3212 {
3213         int i, status = 0;
3214         struct rx_ring *rx_ring;
3215
3216         netif_carrier_off(qdev->ndev);
3217
3218         /* Don't kill the reset worker thread if we
3219          * are in the process of recovery.
3220          */
3221         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3222                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3223         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3224         cancel_delayed_work_sync(&qdev->mpi_work);
3225         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3226         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3227
3228         /* The default queue at index 0 is always processed in
3229          * a workqueue.
3230          */
3231         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3232
3233         /* The rest of the rx_rings are processed in
3234          * a workqueue only if it's a single interrupt
3235          * environment (MSI/Legacy).
3236          */
3237         for (i = 1; i < qdev->rx_ring_count; i++) {
3238                 rx_ring = &qdev->rx_ring[i];
3239                 /* Only the RSS rings use NAPI on multi irq
3240                  * environment.  Outbound completion processing
3241                  * is done in interrupt context.
3242                  */
3243                 if (i >= qdev->rss_ring_first_cq_id) {
3244                         napi_disable(&rx_ring->napi);
3245                 } else {
3246                         cancel_delayed_work_sync(&rx_ring->rx_work);
3247                 }
3248         }
3249
3250         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3251
3252         ql_disable_interrupts(qdev);
3253
3254         ql_tx_ring_clean(qdev);
3255
3256         /* Call netif_napi_del() from common point.
3257          */
3258         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3259                 netif_napi_del(&qdev->rx_ring[i].napi);
3260
3261         ql_free_rx_buffers(qdev);
3262
3263         spin_lock(&qdev->hw_lock);
3264         status = ql_adapter_reset(qdev);
3265         if (status)
3266                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3267                         qdev->func);
3268         spin_unlock(&qdev->hw_lock);
3269         return status;
3270 }
3271
3272 static int ql_adapter_up(struct ql_adapter *qdev)
3273 {
3274         int err = 0;
3275
3276         err = ql_adapter_initialize(qdev);
3277         if (err) {
3278                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3279                 spin_unlock(&qdev->hw_lock);
3280                 goto err_init;
3281         }
3282         set_bit(QL_ADAPTER_UP, &qdev->flags);
3283         ql_alloc_rx_buffers(qdev);
3284         if ((ql_read32(qdev, STS) & qdev->port_init))
3285                 netif_carrier_on(qdev->ndev);
3286         ql_enable_interrupts(qdev);
3287         ql_enable_all_completion_interrupts(qdev);
3288         netif_tx_start_all_queues(qdev->ndev);
3289
3290         return 0;
3291 err_init:
3292         ql_adapter_reset(qdev);
3293         return err;
3294 }
3295
3296 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3297 {
3298         ql_free_mem_resources(qdev);
3299         ql_free_irq(qdev);
3300 }
3301
3302 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3303 {
3304         int status = 0;
3305
3306         if (ql_alloc_mem_resources(qdev)) {
3307                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3308                 return -ENOMEM;
3309         }
3310         status = ql_request_irq(qdev);
3311         if (status)
3312                 goto err_irq;
3313         return status;
3314 err_irq:
3315         ql_free_mem_resources(qdev);
3316         return status;
3317 }
3318
3319 static int qlge_close(struct net_device *ndev)
3320 {
3321         struct ql_adapter *qdev = netdev_priv(ndev);
3322
3323         /*
3324          * Wait for device to recover from a reset.
3325          * (Rarely happens, but possible.)
3326          */
3327         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3328                 msleep(1);
3329         ql_adapter_down(qdev);
3330         ql_release_adapter_resources(qdev);
3331         return 0;
3332 }
3333
3334 static int ql_configure_rings(struct ql_adapter *qdev)
3335 {
3336         int i;
3337         struct rx_ring *rx_ring;
3338         struct tx_ring *tx_ring;
3339         int cpu_cnt = num_online_cpus();
3340
3341         /*
3342          * For each processor present we allocate one
3343          * rx_ring for outbound completions, and one
3344          * rx_ring for inbound completions.  Plus there is
3345          * always the one default queue.  For the CPU
3346          * counts we end up with the following rx_rings:
3347          * rx_ring count =
3348          *  one default queue +
3349          *  (CPU count * outbound completion rx_ring) +
3350          *  (CPU count * inbound (RSS) completion rx_ring)
3351          * To keep it simple we limit the total number of
3352          * queues to < 32, so we truncate CPU to 8.
3353          * This limitation can be removed when requested.
3354          */
3355
3356         if (cpu_cnt > MAX_CPUS)
3357                 cpu_cnt = MAX_CPUS;
3358
3359         /*
3360          * rx_ring[0] is always the default queue.
3361          */
3362         /* Allocate outbound completion ring for each CPU. */
3363         qdev->tx_ring_count = cpu_cnt;
3364         /* Allocate inbound completion (RSS) ring for each CPU. */
3365         qdev->rss_ring_count = cpu_cnt;
3366         /* cq_id for the first inbound ring handler. */
3367         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3368         /*
3369          * qdev->rx_ring_count:
3370          * Total number of rx_rings.  This includes the one
3371          * default queue, a number of outbound completion
3372          * handler rx_rings, and the number of inbound
3373          * completion handler rx_rings.
3374          */
3375         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3376
3377         for (i = 0; i < qdev->tx_ring_count; i++) {
3378                 tx_ring = &qdev->tx_ring[i];
3379                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3380                 tx_ring->qdev = qdev;
3381                 tx_ring->wq_id = i;
3382                 tx_ring->wq_len = qdev->tx_ring_size;
3383                 tx_ring->wq_size =
3384                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3385
3386                 /*
3387                  * The completion queue ID for the tx rings start
3388                  * immediately after the default Q ID, which is zero.
3389                  */
3390                 tx_ring->cq_id = i + 1;
3391         }
3392
3393         for (i = 0; i < qdev->rx_ring_count; i++) {
3394                 rx_ring = &qdev->rx_ring[i];
3395                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3396                 rx_ring->qdev = qdev;
3397                 rx_ring->cq_id = i;
3398                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3399                 if (i == 0) {   /* Default queue at index 0. */
3400                         /*
3401                          * Default queue handles bcast/mcast plus
3402                          * async events.  Needs buffers.
3403                          */
3404                         rx_ring->cq_len = qdev->rx_ring_size;
3405                         rx_ring->cq_size =
3406                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3407                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3408                         rx_ring->lbq_size =
3409                             rx_ring->lbq_len * sizeof(__le64);
3410                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3411                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3412                         rx_ring->sbq_size =
3413                             rx_ring->sbq_len * sizeof(__le64);
3414                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3415                         rx_ring->type = DEFAULT_Q;
3416                 } else if (i < qdev->rss_ring_first_cq_id) {
3417                         /*
3418                          * Outbound queue handles outbound completions only.
3419                          */
3420                         /* outbound cq is same size as tx_ring it services. */
3421                         rx_ring->cq_len = qdev->tx_ring_size;
3422                         rx_ring->cq_size =
3423                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3424                         rx_ring->lbq_len = 0;
3425                         rx_ring->lbq_size = 0;
3426                         rx_ring->lbq_buf_size = 0;
3427                         rx_ring->sbq_len = 0;
3428                         rx_ring->sbq_size = 0;
3429                         rx_ring->sbq_buf_size = 0;
3430                         rx_ring->type = TX_Q;
3431                 } else {        /* Inbound completions (RSS) queues */
3432                         /*
3433                          * Inbound queues handle unicast frames only.
3434                          */
3435                         rx_ring->cq_len = qdev->rx_ring_size;
3436                         rx_ring->cq_size =
3437                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3438                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3439                         rx_ring->lbq_size =
3440                             rx_ring->lbq_len * sizeof(__le64);
3441                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3442                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3443                         rx_ring->sbq_size =
3444                             rx_ring->sbq_len * sizeof(__le64);
3445                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3446                         rx_ring->type = RX_Q;
3447                 }
3448         }
3449         return 0;
3450 }
3451
3452 static int qlge_open(struct net_device *ndev)
3453 {
3454         int err = 0;
3455         struct ql_adapter *qdev = netdev_priv(ndev);
3456
3457         err = ql_configure_rings(qdev);
3458         if (err)
3459                 return err;
3460
3461         err = ql_get_adapter_resources(qdev);
3462         if (err)
3463                 goto error_up;
3464
3465         err = ql_adapter_up(qdev);
3466         if (err)
3467                 goto error_up;
3468
3469         return err;
3470
3471 error_up:
3472         ql_release_adapter_resources(qdev);
3473         return err;
3474 }
3475
3476 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3477 {
3478         struct ql_adapter *qdev = netdev_priv(ndev);
3479
3480         if (ndev->mtu == 1500 && new_mtu == 9000) {
3481                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3482                 queue_delayed_work(qdev->workqueue,
3483                                 &qdev->mpi_port_cfg_work, 0);
3484         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3485                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3486         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3487                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3488                 return 0;
3489         } else
3490                 return -EINVAL;
3491         ndev->mtu = new_mtu;
3492         return 0;
3493 }
3494
3495 static struct net_device_stats *qlge_get_stats(struct net_device
3496                                                *ndev)
3497 {
3498         struct ql_adapter *qdev = netdev_priv(ndev);
3499         return &qdev->stats;
3500 }
3501
3502 static void qlge_set_multicast_list(struct net_device *ndev)
3503 {
3504         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3505         struct dev_mc_list *mc_ptr;
3506         int i, status;
3507
3508         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3509         if (status)
3510                 return;
3511         spin_lock(&qdev->hw_lock);
3512         /*
3513          * Set or clear promiscuous mode if a
3514          * transition is taking place.
3515          */
3516         if (ndev->flags & IFF_PROMISC) {
3517                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3518                         if (ql_set_routing_reg
3519                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3520                                 QPRINTK(qdev, HW, ERR,
3521                                         "Failed to set promiscous mode.\n");
3522                         } else {
3523                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3524                         }
3525                 }
3526         } else {
3527                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3528                         if (ql_set_routing_reg
3529                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3530                                 QPRINTK(qdev, HW, ERR,
3531                                         "Failed to clear promiscous mode.\n");
3532                         } else {
3533                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3534                         }
3535                 }
3536         }
3537
3538         /*
3539          * Set or clear all multicast mode if a
3540          * transition is taking place.
3541          */
3542         if ((ndev->flags & IFF_ALLMULTI) ||
3543             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3544                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3545                         if (ql_set_routing_reg
3546                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3547                                 QPRINTK(qdev, HW, ERR,
3548                                         "Failed to set all-multi mode.\n");
3549                         } else {
3550                                 set_bit(QL_ALLMULTI, &qdev->flags);
3551                         }
3552                 }
3553         } else {
3554                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3555                         if (ql_set_routing_reg
3556                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3557                                 QPRINTK(qdev, HW, ERR,
3558                                         "Failed to clear all-multi mode.\n");
3559                         } else {
3560                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3561                         }
3562                 }
3563         }
3564
3565         if (ndev->mc_count) {
3566                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3567                 if (status)
3568                         goto exit;
3569                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3570                      i++, mc_ptr = mc_ptr->next)
3571                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3572                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3573                                 QPRINTK(qdev, HW, ERR,
3574                                         "Failed to loadmulticast address.\n");
3575                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3576                                 goto exit;
3577                         }
3578                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3579                 if (ql_set_routing_reg
3580                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3581                         QPRINTK(qdev, HW, ERR,
3582                                 "Failed to set multicast match mode.\n");
3583                 } else {
3584                         set_bit(QL_ALLMULTI, &qdev->flags);
3585                 }
3586         }
3587 exit:
3588         spin_unlock(&qdev->hw_lock);
3589         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3590 }
3591
3592 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3593 {
3594         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3595         struct sockaddr *addr = p;
3596         int status;
3597
3598         if (netif_running(ndev))
3599                 return -EBUSY;
3600
3601         if (!is_valid_ether_addr(addr->sa_data))
3602                 return -EADDRNOTAVAIL;
3603         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3604
3605         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3606         if (status)
3607                 return status;
3608         spin_lock(&qdev->hw_lock);
3609         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3610                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3611         spin_unlock(&qdev->hw_lock);
3612         if (status)
3613                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3614         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3615         return status;
3616 }
3617
3618 static void qlge_tx_timeout(struct net_device *ndev)
3619 {
3620         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3621         ql_queue_asic_error(qdev);
3622 }
3623
3624 static void ql_asic_reset_work(struct work_struct *work)
3625 {
3626         struct ql_adapter *qdev =
3627             container_of(work, struct ql_adapter, asic_reset_work.work);
3628         int status;
3629
3630         status = ql_adapter_down(qdev);
3631         if (status)
3632                 goto error;
3633
3634         status = ql_adapter_up(qdev);
3635         if (status)
3636                 goto error;
3637
3638         return;
3639 error:
3640         QPRINTK(qdev, IFUP, ALERT,
3641                 "Driver up/down cycle failed, closing device\n");
3642         rtnl_lock();
3643         set_bit(QL_ADAPTER_UP, &qdev->flags);
3644         dev_close(qdev->ndev);
3645         rtnl_unlock();
3646 }
3647
3648 static struct nic_operations qla8012_nic_ops = {
3649         .get_flash              = ql_get_8012_flash_params,
3650         .port_initialize        = ql_8012_port_initialize,
3651 };
3652
3653 static struct nic_operations qla8000_nic_ops = {
3654         .get_flash              = ql_get_8000_flash_params,
3655         .port_initialize        = ql_8000_port_initialize,
3656 };
3657
3658
3659 static void ql_get_board_info(struct ql_adapter *qdev)
3660 {
3661         qdev->func =
3662             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3663         if (qdev->func) {
3664                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3665                 qdev->port_link_up = STS_PL1;
3666                 qdev->port_init = STS_PI1;
3667                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3668                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3669         } else {
3670                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3671                 qdev->port_link_up = STS_PL0;
3672                 qdev->port_init = STS_PI0;
3673                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3674                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3675         }
3676         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3677         qdev->device_id = qdev->pdev->device;
3678         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3679                 qdev->nic_ops = &qla8012_nic_ops;
3680         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3681                 qdev->nic_ops = &qla8000_nic_ops;
3682 }
3683
3684 static void ql_release_all(struct pci_dev *pdev)
3685 {
3686         struct net_device *ndev = pci_get_drvdata(pdev);
3687         struct ql_adapter *qdev = netdev_priv(ndev);
3688
3689         if (qdev->workqueue) {
3690                 destroy_workqueue(qdev->workqueue);
3691                 qdev->workqueue = NULL;
3692         }
3693         if (qdev->q_workqueue) {
3694                 destroy_workqueue(qdev->q_workqueue);
3695                 qdev->q_workqueue = NULL;
3696         }
3697         if (qdev->reg_base)
3698                 iounmap(qdev->reg_base);
3699         if (qdev->doorbell_area)
3700                 iounmap(qdev->doorbell_area);
3701         pci_release_regions(pdev);
3702         pci_set_drvdata(pdev, NULL);
3703 }
3704
3705 static int __devinit ql_init_device(struct pci_dev *pdev,
3706                                     struct net_device *ndev, int cards_found)
3707 {
3708         struct ql_adapter *qdev = netdev_priv(ndev);
3709         int pos, err = 0;
3710         u16 val16;
3711
3712         memset((void *)qdev, 0, sizeof(qdev));
3713         err = pci_enable_device(pdev);
3714         if (err) {
3715                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3716                 return err;
3717         }
3718
3719         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3720         if (pos <= 0) {
3721                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3722                         "aborting.\n");
3723                 goto err_out;
3724         } else {
3725                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3726                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3727                 val16 |= (PCI_EXP_DEVCTL_CERE |
3728                           PCI_EXP_DEVCTL_NFERE |
3729                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3730                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3731         }
3732
3733         err = pci_request_regions(pdev, DRV_NAME);
3734         if (err) {
3735                 dev_err(&pdev->dev, "PCI region request failed.\n");
3736                 goto err_out;
3737         }
3738
3739         pci_set_master(pdev);
3740         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3741                 set_bit(QL_DMA64, &qdev->flags);
3742                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3743         } else {
3744                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3745                 if (!err)
3746                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3747         }
3748
3749         if (err) {
3750                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3751                 goto err_out;
3752         }
3753
3754         pci_set_drvdata(pdev, ndev);
3755         qdev->reg_base =
3756             ioremap_nocache(pci_resource_start(pdev, 1),
3757                             pci_resource_len(pdev, 1));
3758         if (!qdev->reg_base) {
3759                 dev_err(&pdev->dev, "Register mapping failed.\n");
3760                 err = -ENOMEM;
3761                 goto err_out;
3762         }
3763
3764         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3765         qdev->doorbell_area =
3766             ioremap_nocache(pci_resource_start(pdev, 3),
3767                             pci_resource_len(pdev, 3));
3768         if (!qdev->doorbell_area) {
3769                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3770                 err = -ENOMEM;
3771                 goto err_out;
3772         }
3773
3774         qdev->ndev = ndev;
3775         qdev->pdev = pdev;
3776         ql_get_board_info(qdev);
3777         qdev->msg_enable = netif_msg_init(debug, default_msg);
3778         spin_lock_init(&qdev->hw_lock);
3779         spin_lock_init(&qdev->stats_lock);
3780
3781         /* make sure the EEPROM is good */
3782         err = qdev->nic_ops->get_flash(qdev);
3783         if (err) {
3784                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3785                 goto err_out;
3786         }
3787
3788         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3789
3790         /* Set up the default ring sizes. */
3791         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3792         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3793
3794         /* Set up the coalescing parameters. */
3795         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3796         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3797         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3798         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3799
3800         /*
3801          * Set up the operating parameters.
3802          */
3803         qdev->rx_csum = 1;
3804
3805         qdev->q_workqueue = create_workqueue(ndev->name);
3806         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3807         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3808         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3809         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3810         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3811         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3812         mutex_init(&qdev->mpi_mutex);
3813         init_completion(&qdev->ide_completion);
3814
3815         if (!cards_found) {
3816                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3817                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3818                          DRV_NAME, DRV_VERSION);
3819         }
3820         return 0;
3821 err_out:
3822         ql_release_all(pdev);
3823         pci_disable_device(pdev);
3824         return err;
3825 }
3826
3827
3828 static const struct net_device_ops qlge_netdev_ops = {
3829         .ndo_open               = qlge_open,
3830         .ndo_stop               = qlge_close,
3831         .ndo_start_xmit         = qlge_send,
3832         .ndo_change_mtu         = qlge_change_mtu,
3833         .ndo_get_stats          = qlge_get_stats,
3834         .ndo_set_multicast_list = qlge_set_multicast_list,
3835         .ndo_set_mac_address    = qlge_set_mac_address,
3836         .ndo_validate_addr      = eth_validate_addr,
3837         .ndo_tx_timeout         = qlge_tx_timeout,
3838         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3839         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3840         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3841 };
3842
3843 static int __devinit qlge_probe(struct pci_dev *pdev,
3844                                 const struct pci_device_id *pci_entry)
3845 {
3846         struct net_device *ndev = NULL;
3847         struct ql_adapter *qdev = NULL;
3848         static int cards_found = 0;
3849         int err = 0;
3850
3851         ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3852                         min(MAX_CPUS, (int)num_online_cpus()));
3853         if (!ndev)
3854                 return -ENOMEM;
3855
3856         err = ql_init_device(pdev, ndev, cards_found);
3857         if (err < 0) {
3858                 free_netdev(ndev);
3859                 return err;
3860         }
3861
3862         qdev = netdev_priv(ndev);
3863         SET_NETDEV_DEV(ndev, &pdev->dev);
3864         ndev->features = (0
3865                           | NETIF_F_IP_CSUM
3866                           | NETIF_F_SG
3867                           | NETIF_F_TSO
3868                           | NETIF_F_TSO6
3869                           | NETIF_F_TSO_ECN
3870                           | NETIF_F_HW_VLAN_TX
3871                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3872         ndev->features |= NETIF_F_GRO;
3873
3874         if (test_bit(QL_DMA64, &qdev->flags))
3875                 ndev->features |= NETIF_F_HIGHDMA;
3876
3877         /*
3878          * Set up net_device structure.
3879          */
3880         ndev->tx_queue_len = qdev->tx_ring_size;
3881         ndev->irq = pdev->irq;
3882
3883         ndev->netdev_ops = &qlge_netdev_ops;
3884         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3885         ndev->watchdog_timeo = 10 * HZ;
3886
3887         err = register_netdev(ndev);
3888         if (err) {
3889                 dev_err(&pdev->dev, "net device registration failed.\n");
3890                 ql_release_all(pdev);
3891                 pci_disable_device(pdev);
3892                 return err;
3893         }
3894         netif_carrier_off(ndev);
3895         ql_display_dev_info(ndev);
3896         cards_found++;
3897         return 0;
3898 }
3899
3900 static void __devexit qlge_remove(struct pci_dev *pdev)
3901 {
3902         struct net_device *ndev = pci_get_drvdata(pdev);
3903         unregister_netdev(ndev);
3904         ql_release_all(pdev);
3905         pci_disable_device(pdev);
3906         free_netdev(ndev);
3907 }
3908
3909 /*
3910  * This callback is called by the PCI subsystem whenever
3911  * a PCI bus error is detected.
3912  */
3913 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3914                                                enum pci_channel_state state)
3915 {
3916         struct net_device *ndev = pci_get_drvdata(pdev);
3917         struct ql_adapter *qdev = netdev_priv(ndev);
3918
3919         if (netif_running(ndev))
3920                 ql_adapter_down(qdev);
3921
3922         pci_disable_device(pdev);
3923
3924         /* Request a slot reset. */
3925         return PCI_ERS_RESULT_NEED_RESET;
3926 }
3927
3928 /*
3929  * This callback is called after the PCI buss has been reset.
3930  * Basically, this tries to restart the card from scratch.
3931  * This is a shortened version of the device probe/discovery code,
3932  * it resembles the first-half of the () routine.
3933  */
3934 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3935 {
3936         struct net_device *ndev = pci_get_drvdata(pdev);
3937         struct ql_adapter *qdev = netdev_priv(ndev);
3938
3939         if (pci_enable_device(pdev)) {
3940                 QPRINTK(qdev, IFUP, ERR,
3941                         "Cannot re-enable PCI device after reset.\n");
3942                 return PCI_ERS_RESULT_DISCONNECT;
3943         }
3944
3945         pci_set_master(pdev);
3946
3947         netif_carrier_off(ndev);
3948         ql_adapter_reset(qdev);
3949
3950         /* Make sure the EEPROM is good */
3951         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3952
3953         if (!is_valid_ether_addr(ndev->perm_addr)) {
3954                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3955                 return PCI_ERS_RESULT_DISCONNECT;
3956         }
3957
3958         return PCI_ERS_RESULT_RECOVERED;
3959 }
3960
3961 static void qlge_io_resume(struct pci_dev *pdev)
3962 {
3963         struct net_device *ndev = pci_get_drvdata(pdev);
3964         struct ql_adapter *qdev = netdev_priv(ndev);
3965
3966         pci_set_master(pdev);
3967
3968         if (netif_running(ndev)) {
3969                 if (ql_adapter_up(qdev)) {
3970                         QPRINTK(qdev, IFUP, ERR,
3971                                 "Device initialization failed after reset.\n");
3972                         return;
3973                 }
3974         }
3975
3976         netif_device_attach(ndev);
3977 }
3978
3979 static struct pci_error_handlers qlge_err_handler = {
3980         .error_detected = qlge_io_error_detected,
3981         .slot_reset = qlge_io_slot_reset,
3982         .resume = qlge_io_resume,
3983 };
3984
3985 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3986 {
3987         struct net_device *ndev = pci_get_drvdata(pdev);
3988         struct ql_adapter *qdev = netdev_priv(ndev);
3989         int err;
3990
3991         netif_device_detach(ndev);
3992
3993         if (netif_running(ndev)) {
3994                 err = ql_adapter_down(qdev);
3995                 if (!err)
3996                         return err;
3997         }
3998
3999         err = pci_save_state(pdev);
4000         if (err)
4001                 return err;
4002
4003         pci_disable_device(pdev);
4004
4005         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4006
4007         return 0;
4008 }
4009
4010 #ifdef CONFIG_PM
4011 static int qlge_resume(struct pci_dev *pdev)
4012 {
4013         struct net_device *ndev = pci_get_drvdata(pdev);
4014         struct ql_adapter *qdev = netdev_priv(ndev);
4015         int err;
4016
4017         pci_set_power_state(pdev, PCI_D0);
4018         pci_restore_state(pdev);
4019         err = pci_enable_device(pdev);
4020         if (err) {
4021                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4022                 return err;
4023         }
4024         pci_set_master(pdev);
4025
4026         pci_enable_wake(pdev, PCI_D3hot, 0);
4027         pci_enable_wake(pdev, PCI_D3cold, 0);
4028
4029         if (netif_running(ndev)) {
4030                 err = ql_adapter_up(qdev);
4031                 if (err)
4032                         return err;
4033         }
4034
4035         netif_device_attach(ndev);
4036
4037         return 0;
4038 }
4039 #endif /* CONFIG_PM */
4040
4041 static void qlge_shutdown(struct pci_dev *pdev)
4042 {
4043         qlge_suspend(pdev, PMSG_SUSPEND);
4044 }
4045
4046 static struct pci_driver qlge_driver = {
4047         .name = DRV_NAME,
4048         .id_table = qlge_pci_tbl,
4049         .probe = qlge_probe,
4050         .remove = __devexit_p(qlge_remove),
4051 #ifdef CONFIG_PM
4052         .suspend = qlge_suspend,
4053         .resume = qlge_resume,
4054 #endif
4055         .shutdown = qlge_shutdown,
4056         .err_handler = &qlge_err_handler
4057 };
4058
4059 static int __init qlge_init_module(void)
4060 {
4061         return pci_register_driver(&qlge_driver);
4062 }
4063
4064 static void __exit qlge_exit(void)
4065 {
4066         pci_unregister_driver(&qlge_driver);
4067 }
4068
4069 module_init(qlge_init_module);
4070 module_exit(qlge_exit);