SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <net/ip.h>
  28
  29 #define MASK(n) ((1ULL<<(n))-1)
  30 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  31
  32 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  33
  34 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  35 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  36 #define CRB_WINDOW_2M   (0x130060)
  37 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  38 #define CRB_INDIRECT_2M (0x1e0000UL)
  39
  40
  41 #ifndef readq
  42 static inline u64 readq(void __iomem *addr)
  43 {
  44         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  45 }
  46 #endif
  47
  48 #ifndef writeq
  49 static inline void writeq(u64 val, void __iomem *addr)
  50 {
  51         writel(((u32) (val)), (addr));
  52         writel(((u32) (val >> 32)), (addr + 4));
  53 }
  54 #endif
  55
  56 #define ADDR_IN_RANGE(addr, low, high)  \
  57         (((addr) < (high)) && ((addr) >= (low)))
  58
  59 #define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
  60         ((adapter)->ahw.pci_base0 + (off))
  61
  62 static void __iomem *pci_base_offset(struct qlcnic_adapter *adapter,
  63                                             unsigned long off)
  64 {
  65         if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
  66                 return PCI_OFFSET_FIRST_RANGE(adapter, off);
  67
  68         return NULL;
  69 }
  70
  71 static const struct crb_128M_2M_block_map
  72 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  73     {{{0, 0,         0,         0} } },         /* 0: PCI */
  74     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  75           {1, 0x0110000, 0x0120000, 0x130000},
  76           {1, 0x0120000, 0x0122000, 0x124000},
  77           {1, 0x0130000, 0x0132000, 0x126000},
  78           {1, 0x0140000, 0x0142000, 0x128000},
  79           {1, 0x0150000, 0x0152000, 0x12a000},
  80           {1, 0x0160000, 0x0170000, 0x110000},
  81           {1, 0x0170000, 0x0172000, 0x12e000},
  82           {0, 0x0000000, 0x0000000, 0x000000},
  83           {0, 0x0000000, 0x0000000, 0x000000},
  84           {0, 0x0000000, 0x0000000, 0x000000},
  85           {0, 0x0000000, 0x0000000, 0x000000},
  86           {0, 0x0000000, 0x0000000, 0x000000},
  87           {0, 0x0000000, 0x0000000, 0x000000},
  88           {1, 0x01e0000, 0x01e0800, 0x122000},
  89           {0, 0x0000000, 0x0000000, 0x000000} } },
  90         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  91     {{{0, 0,         0,         0} } },     /* 3: */
  92     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  93     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  94     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  95     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  96     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {1, 0x08f0000, 0x08f2000, 0x172000} } },
 112     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 128     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 144     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 145       {0, 0x0000000, 0x0000000, 0x000000},
 146       {0, 0x0000000, 0x0000000, 0x000000},
 147       {0, 0x0000000, 0x0000000, 0x000000},
 148       {0, 0x0000000, 0x0000000, 0x000000},
 149       {0, 0x0000000, 0x0000000, 0x000000},
 150       {0, 0x0000000, 0x0000000, 0x000000},
 151       {0, 0x0000000, 0x0000000, 0x000000},
 152       {0, 0x0000000, 0x0000000, 0x000000},
 153       {0, 0x0000000, 0x0000000, 0x000000},
 154       {0, 0x0000000, 0x0000000, 0x000000},
 155       {0, 0x0000000, 0x0000000, 0x000000},
 156       {0, 0x0000000, 0x0000000, 0x000000},
 157       {0, 0x0000000, 0x0000000, 0x000000},
 158       {0, 0x0000000, 0x0000000, 0x000000},
 159       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 160         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 161         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 162         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 163         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 164         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 165         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 166         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 167         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 168         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 169         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 170         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 171         {{{0, 0,         0,         0} } },     /* 23: */
 172         {{{0, 0,         0,         0} } },     /* 24: */
 173         {{{0, 0,         0,         0} } },     /* 25: */
 174         {{{0, 0,         0,         0} } },     /* 26: */
 175         {{{0, 0,         0,         0} } },     /* 27: */
 176         {{{0, 0,         0,         0} } },     /* 28: */
 177         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 178     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 179     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 180         {{{0} } },                              /* 32: PCI */
 181         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 182           {1, 0x2110000, 0x2120000, 0x130000},
 183           {1, 0x2120000, 0x2122000, 0x124000},
 184           {1, 0x2130000, 0x2132000, 0x126000},
 185           {1, 0x2140000, 0x2142000, 0x128000},
 186           {1, 0x2150000, 0x2152000, 0x12a000},
 187           {1, 0x2160000, 0x2170000, 0x110000},
 188           {1, 0x2170000, 0x2172000, 0x12e000},
 189           {0, 0x0000000, 0x0000000, 0x000000},
 190           {0, 0x0000000, 0x0000000, 0x000000},
 191           {0, 0x0000000, 0x0000000, 0x000000},
 192           {0, 0x0000000, 0x0000000, 0x000000},
 193           {0, 0x0000000, 0x0000000, 0x000000},
 194           {0, 0x0000000, 0x0000000, 0x000000},
 195           {0, 0x0000000, 0x0000000, 0x000000},
 196           {0, 0x0000000, 0x0000000, 0x000000} } },
 197         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 198         {{{0} } },                              /* 35: */
 199         {{{0} } },                              /* 36: */
 200         {{{0} } },                              /* 37: */
 201         {{{0} } },                              /* 38: */
 202         {{{0} } },                              /* 39: */
 203         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 204         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 205         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 206         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 207         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 208         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 209         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 210         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 211         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 212         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 213         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 214         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 215         {{{0} } },                              /* 52: */
 216         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 217         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 218         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 219         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 220         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 221         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 222         {{{0} } },                              /* 59: I2C0 */
 223         {{{0} } },                              /* 60: I2C1 */
 224         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 225         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 226         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 227 };
 228
 229 /*
 230  * top 12 bits of crb internal address (hub, agent)
 231  */
 232 static const unsigned crb_hub_agt[64] = {
 233         0,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 237         0,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 249         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 251         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 254         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 260         0,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 263         0,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 268         0,
 269         0,
 270         0,
 271         0,
 272         0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 276         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 280         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 282         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 283         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 284         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 285         0,
 286         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 287         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 288         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 289         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 290         0,
 291         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 292         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 293         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 294         0,
 295         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 296         0,
 297 };
 298
 299 /*  PCI Windowing for DDR regions.  */
 300
 301 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 302
 303 int
 304 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 305 {
 306         int done = 0, timeout = 0;
 307
 308         while (!done) {
 309                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 310                 if (done == 1)
 311                         break;
 312                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT)
 313                         return -EIO;
 314                 msleep(1);
 315         }
 316
 317         if (id_reg)
 318                 QLCWR32(adapter, id_reg, adapter->portnum);
 319
 320         return 0;
 321 }
 322
 323 void
 324 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 325 {
 326         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 327 }
 328
 329 static int
 330 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 331                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 332 {
 333         u32 i, producer, consumer;
 334         struct qlcnic_cmd_buffer *pbuf;
 335         struct cmd_desc_type0 *cmd_desc;
 336         struct qlcnic_host_tx_ring *tx_ring;
 337
 338         i = 0;
 339
 340         if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
 341                 return -EIO;
 342
 343         tx_ring = adapter->tx_ring;
 344         __netif_tx_lock_bh(tx_ring->txq);
 345
 346         producer = tx_ring->producer;
 347         consumer = tx_ring->sw_consumer;
 348
 349         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 350                 netif_tx_stop_queue(tx_ring->txq);
 351                 __netif_tx_unlock_bh(tx_ring->txq);
 352                 return -EBUSY;
 353         }
 354
 355         do {
 356                 cmd_desc = &cmd_desc_arr[i];
 357
 358                 pbuf = &tx_ring->cmd_buf_arr[producer];
 359                 pbuf->skb = NULL;
 360                 pbuf->frag_count = 0;
 361
 362                 memcpy(&tx_ring->desc_head[producer],
 363                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 364
 365                 producer = get_next_index(producer, tx_ring->num_desc);
 366                 i++;
 367
 368         } while (i != nr_desc);
 369
 370         tx_ring->producer = producer;
 371
 372         qlcnic_update_cmd_producer(adapter, tx_ring);
 373
 374         __netif_tx_unlock_bh(tx_ring->txq);
 375
 376         return 0;
 377 }
 378
 379 static int
 380 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 381                                 unsigned op)
 382 {
 383         struct qlcnic_nic_req req;
 384         struct qlcnic_mac_req *mac_req;
 385         u64 word;
 386
 387         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 388         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 389
 390         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 391         req.req_hdr = cpu_to_le64(word);
 392
 393         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 394         mac_req->op = op;
 395         memcpy(mac_req->mac_addr, addr, 6);
 396
 397         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 398 }
 399
 400 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter,
 401                 u8 *addr, struct list_head *del_list)
 402 {
 403         struct list_head *head;
 404         struct qlcnic_mac_list_s *cur;
 405
 406         /* look up if already exists */
 407         list_for_each(head, del_list) {
 408                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 409
 410                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
 411                         list_move_tail(head, &adapter->mac_list);
 412                         return 0;
 413                 }
 414         }
 415
 416         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 417         if (cur == NULL) {
 418                 dev_err(&adapter->netdev->dev,
 419                         "failed to add mac address filter\n");
 420                 return -ENOMEM;
 421         }
 422         memcpy(cur->mac_addr, addr, ETH_ALEN);
 423         list_add_tail(&cur->list, &adapter->mac_list);
 424
 425         return qlcnic_sre_macaddr_change(adapter,
 426                                 cur->mac_addr, QLCNIC_MAC_ADD);
 427 }
 428
 429 void qlcnic_set_multi(struct net_device *netdev)
 430 {
 431         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 432         struct dev_mc_list *mc_ptr;
 433         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 434         u32 mode = VPORT_MISS_MODE_DROP;
 435         LIST_HEAD(del_list);
 436         struct list_head *head;
 437         struct qlcnic_mac_list_s *cur;
 438
 439         list_splice_tail_init(&adapter->mac_list, &del_list);
 440
 441         qlcnic_nic_add_mac(adapter, adapter->mac_addr, &del_list);
 442         qlcnic_nic_add_mac(adapter, bcast_addr, &del_list);
 443
 444         if (netdev->flags & IFF_PROMISC) {
 445                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 446                 goto send_fw_cmd;
 447         }
 448
 449         if ((netdev->flags & IFF_ALLMULTI) ||
 450             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 451                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 452                 goto send_fw_cmd;
 453         }
 454
 455         if (!netdev_mc_empty(netdev)) {
 456                 for (mc_ptr = netdev->mc_list; mc_ptr;
 457                                      mc_ptr = mc_ptr->next) {
 458                         qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr,
 459                                                         &del_list);
 460                 }
 461         }
 462
 463 send_fw_cmd:
 464         qlcnic_nic_set_promisc(adapter, mode);
 465         head = &del_list;
 466         while (!list_empty(head)) {
 467                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 468
 469                 qlcnic_sre_macaddr_change(adapter,
 470                                 cur->mac_addr, QLCNIC_MAC_DEL);
 471                 list_del(&cur->list);
 472                 kfree(cur);
 473         }
 474 }
 475
 476 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 477 {
 478         struct qlcnic_nic_req req;
 479         u64 word;
 480
 481         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 482
 483         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 484
 485         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 486                         ((u64)adapter->portnum << 16);
 487         req.req_hdr = cpu_to_le64(word);
 488
 489         req.words[0] = cpu_to_le64(mode);
 490
 491         return qlcnic_send_cmd_descs(adapter,
 492                                 (struct cmd_desc_type0 *)&req, 1);
 493 }
 494
 495 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 496 {
 497         struct qlcnic_mac_list_s *cur;
 498         struct list_head *head = &adapter->mac_list;
 499
 500         while (!list_empty(head)) {
 501                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 502                 qlcnic_sre_macaddr_change(adapter,
 503                                 cur->mac_addr, QLCNIC_MAC_DEL);
 504                 list_del(&cur->list);
 505                 kfree(cur);
 506         }
 507 }
 508
 509 #define QLCNIC_CONFIG_INTR_COALESCE     3
 510
 511 /*
 512  * Send the interrupt coalescing parameter set by ethtool to the card.
 513  */
 514 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 515 {
 516         struct qlcnic_nic_req req;
 517         u64 word[6];
 518         int rv, i;
 519
 520         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 521
 522         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 523
 524         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 525         req.req_hdr = cpu_to_le64(word[0]);
 526
 527         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 528         for (i = 0; i < 6; i++)
 529                 req.words[i] = cpu_to_le64(word[i]);
 530
 531         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 532         if (rv != 0)
 533                 dev_err(&adapter->netdev->dev,
 534                         "Could not send interrupt coalescing parameters\n");
 535
 536         return rv;
 537 }
 538
 539 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 540 {
 541         struct qlcnic_nic_req req;
 542         u64 word;
 543         int rv;
 544
 545         if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
 546                 return 0;
 547
 548         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 549
 550         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 551
 552         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 553         req.req_hdr = cpu_to_le64(word);
 554
 555         req.words[0] = cpu_to_le64(enable);
 556
 557         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 558         if (rv != 0)
 559                 dev_err(&adapter->netdev->dev,
 560                         "Could not send configure hw lro request\n");
 561
 562         adapter->flags ^= QLCNIC_LRO_ENABLED;
 563
 564         return rv;
 565 }
 566
 567 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
 568 {
 569         struct qlcnic_nic_req req;
 570         u64 word;
 571         int rv;
 572
 573         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 574                 return 0;
 575
 576         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 577
 578         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 579
 580         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 581                 ((u64)adapter->portnum << 16);
 582         req.req_hdr = cpu_to_le64(word);
 583
 584         req.words[0] = cpu_to_le64(enable);
 585
 586         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 587         if (rv != 0)
 588                 dev_err(&adapter->netdev->dev,
 589                         "Could not send configure bridge mode request\n");
 590
 591         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 592
 593         return rv;
 594 }
 595
 596
 597 #define RSS_HASHTYPE_IP_TCP     0x3
 598
 599 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 600 {
 601         struct qlcnic_nic_req req;
 602         u64 word;
 603         int i, rv;
 604
 605         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 606                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 607                         0x255b0ec26d5a56daULL };
 608
 609
 610         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 611         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 612
 613         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 614         req.req_hdr = cpu_to_le64(word);
 615
 616         /*
 617          * RSS request:
 618          * bits 3-0: hash_method
 619          *      5-4: hash_type_ipv4
 620          *      7-6: hash_type_ipv6
 621          *        8: enable
 622          *        9: use indirection table
 623          *    47-10: reserved
 624          *    63-48: indirection table mask
 625          */
 626         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 627                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 628                 ((u64)(enable & 0x1) << 8) |
 629                 ((0x7ULL) << 48);
 630         req.words[0] = cpu_to_le64(word);
 631         for (i = 0; i < 5; i++)
 632                 req.words[i+1] = cpu_to_le64(key[i]);
 633
 634         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 635         if (rv != 0)
 636                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 637
 638         return rv;
 639 }
 640
 641 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
 642 {
 643         struct qlcnic_nic_req req;
 644         u64 word;
 645         int rv;
 646
 647         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 648         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 649
 650         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 651         req.req_hdr = cpu_to_le64(word);
 652
 653         req.words[0] = cpu_to_le64(cmd);
 654         req.words[1] = cpu_to_le64(ip);
 655
 656         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 657         if (rv != 0)
 658                 dev_err(&adapter->netdev->dev,
 659                                 "could not notify %s IP 0x%x reuqest\n",
 660                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 661
 662         return rv;
 663 }
 664
 665 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 666 {
 667         struct qlcnic_nic_req req;
 668         u64 word;
 669         int rv;
 670
 671         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 672         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 673
 674         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 675         req.req_hdr = cpu_to_le64(word);
 676         req.words[0] = cpu_to_le64(enable | (enable << 8));
 677
 678         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 679         if (rv != 0)
 680                 dev_err(&adapter->netdev->dev,
 681                                 "could not configure link notification\n");
 682
 683         return rv;
 684 }
 685
 686 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 687 {
 688         struct qlcnic_nic_req req;
 689         u64 word;
 690         int rv;
 691
 692         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 693         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 694
 695         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 696                 ((u64)adapter->portnum << 16) |
 697                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 698
 699         req.req_hdr = cpu_to_le64(word);
 700
 701         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 702         if (rv != 0)
 703                 dev_err(&adapter->netdev->dev,
 704                                  "could not cleanup lro flows\n");
 705
 706         return rv;
 707 }
 708
 709 /*
 710  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 711  * @returns 0 on success, negative on failure
 712  */
 713
 714 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 715 {
 716         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 717         int rc = 0;
 718
 719         if (mtu > P3_MAX_MTU) {
 720                 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
 721                                                 P3_MAX_MTU);
 722                 return -EINVAL;
 723         }
 724
 725         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 726
 727         if (!rc)
 728                 netdev->mtu = mtu;
 729
 730         return rc;
 731 }
 732
 733 int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
 734 {
 735         u32 crbaddr, mac_hi, mac_lo;
 736         int pci_func = adapter->ahw.pci_func;
 737
 738         crbaddr = CRB_MAC_BLOCK_START +
 739                 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
 740
 741         mac_lo = QLCRD32(adapter, crbaddr);
 742         mac_hi = QLCRD32(adapter, crbaddr+4);
 743
 744         if (pci_func & 1)
 745                 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
 746         else
 747                 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
 748
 749         return 0;
 750 }
 751
 752 /*
 753  * Changes the CRB window to the specified window.
 754  */
 755  /* Returns < 0 if off is not valid,
 756  *       1 if window access is needed. 'off' is set to offset from
 757  *         CRB space in 128M pci map
 758  *       0 if no window access is needed. 'off' is set to 2M addr
 759  * In: 'off' is offset from base in 128M pci map
 760  */
 761 static int
 762 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 763                 ulong off, void __iomem **addr)
 764 {
 765         const struct crb_128M_2M_sub_block_map *m;
 766
 767         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 768                 return -EINVAL;
 769
 770         off -= QLCNIC_PCI_CRBSPACE;
 771
 772         /*
 773          * Try direct map
 774          */
 775         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 776
 777         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 778                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 779                         (off - m->start_128M);
 780                 return 0;
 781         }
 782
 783         /*
 784          * Not in direct map, use crb window
 785          */
 786         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 787         return 1;
 788 }
 789
 790 /*
 791  * In: 'off' is offset from CRB space in 128M pci map
 792  * Out: 'off' is 2M pci map addr
 793  * side effect: lock crb window
 794  */
 795 static void
 796 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 797 {
 798         u32 window;
 799         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 800
 801         off -= QLCNIC_PCI_CRBSPACE;
 802
 803         window = CRB_HI(off);
 804
 805         if (adapter->ahw.crb_win == window)
 806                 return;
 807
 808         writel(window, addr);
 809         if (readl(addr) != window) {
 810                 if (printk_ratelimit())
 811                         dev_warn(&adapter->pdev->dev,
 812                                 "failed to set CRB window to %d off 0x%lx\n",
 813                                 window, off);
 814         }
 815         adapter->ahw.crb_win = window;
 816 }
 817
 818 int
 819 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 820 {
 821         unsigned long flags;
 822         int rv;
 823         void __iomem *addr = NULL;
 824
 825         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 826
 827         if (rv == 0) {
 828                 writel(data, addr);
 829                 return 0;
 830         }
 831
 832         if (rv > 0) {
 833                 /* indirect access */
 834                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 835                 crb_win_lock(adapter);
 836                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 837                 writel(data, addr);
 838                 crb_win_unlock(adapter);
 839                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 840                 return 0;
 841         }
 842
 843         dev_err(&adapter->pdev->dev,
 844                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 845         dump_stack();
 846         return -EIO;
 847 }
 848
 849 u32
 850 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 851 {
 852         unsigned long flags;
 853         int rv;
 854         u32 data;
 855         void __iomem *addr = NULL;
 856
 857         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 858
 859         if (rv == 0)
 860                 return readl(addr);
 861
 862         if (rv > 0) {
 863                 /* indirect access */
 864                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 865                 crb_win_lock(adapter);
 866                 qlcnic_pci_set_crbwindow_2M(adapter, off);
 867                 data = readl(addr);
 868                 crb_win_unlock(adapter);
 869                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 870                 return data;
 871         }
 872
 873         dev_err(&adapter->pdev->dev,
 874                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 875         dump_stack();
 876         return -1;
 877 }
 878
 879
 880 void __iomem *
 881 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 882 {
 883         void __iomem *addr = NULL;
 884
 885         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 886
 887         return addr;
 888 }
 889
 890
 891 static int
 892 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 893                 u64 addr, u32 *start)
 894 {
 895         u32 window;
 896         struct pci_dev *pdev = adapter->pdev;
 897
 898         if ((addr & 0x00ff800) == 0xff800) {
 899                 if (printk_ratelimit())
 900                         dev_warn(&pdev->dev, "QM access not handled\n");
 901                 return -EIO;
 902         }
 903
 904         window = OCM_WIN_P3P(addr);
 905
 906         writel(window, adapter->ahw.ocm_win_crb);
 907         /* read back to flush */
 908         readl(adapter->ahw.ocm_win_crb);
 909
 910         adapter->ahw.ocm_win = window;
 911         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 912         return 0;
 913 }
 914
 915 static int
 916 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 917                 u64 *data, int op)
 918 {
 919         void __iomem *addr, *mem_ptr = NULL;
 920         resource_size_t mem_base;
 921         int ret;
 922         u32 start;
 923
 924         mutex_lock(&adapter->ahw.mem_lock);
 925
 926         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 927         if (ret != 0)
 928                 goto unlock;
 929
 930         addr = pci_base_offset(adapter, start);
 931         if (addr)
 932                 goto noremap;
 933
 934         mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
 935
 936         mem_ptr = ioremap(mem_base, PAGE_SIZE);
 937         if (mem_ptr == NULL) {
 938                 ret = -EIO;
 939                 goto unlock;
 940         }
 941
 942         addr = mem_ptr + (start & (PAGE_SIZE - 1));
 943
 944 noremap:
 945         if (op == 0)    /* read */
 946                 *data = readq(addr);
 947         else            /* write */
 948                 writeq(*data, addr);
 949
 950 unlock:
 951         mutex_unlock(&adapter->ahw.mem_lock);
 952
 953         if (mem_ptr)
 954                 iounmap(mem_ptr);
 955         return ret;
 956 }
 957
 958 #define MAX_CTL_CHECK   1000
 959
 960 int
 961 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 962                 u64 off, u64 data)
 963 {
 964         int i, j, ret;
 965         u32 temp, off8;
 966         u64 stride;
 967         void __iomem *mem_crb;
 968
 969         /* Only 64-bit aligned access */
 970         if (off & 7)
 971                 return -EIO;
 972
 973         /* P3 onward, test agent base for MIU and SIU is same */
 974         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 975                                 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
 976                 mem_crb = qlcnic_get_ioaddr(adapter,
 977                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 978                 goto correct;
 979         }
 980
 981         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
 982                 mem_crb = qlcnic_get_ioaddr(adapter,
 983                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
 984                 goto correct;
 985         }
 986
 987         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
 988                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
 989
 990         return -EIO;
 991
 992 correct:
 993         stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
 994
 995         off8 = off & ~(stride-1);
 996
 997         mutex_lock(&adapter->ahw.mem_lock);
 998
 999         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1000         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1001
1002         i = 0;
1003         if (stride == 16) {
1004                 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1005                 writel((TA_CTL_START | TA_CTL_ENABLE),
1006                                 (mem_crb + TEST_AGT_CTRL));
1007
1008                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1009                         temp = readl(mem_crb + TEST_AGT_CTRL);
1010                         if ((temp & TA_CTL_BUSY) == 0)
1011                                 break;
1012                 }
1013
1014                 if (j >= MAX_CTL_CHECK) {
1015                         ret = -EIO;
1016                         goto done;
1017                 }
1018
1019                 i = (off & 0xf) ? 0 : 2;
1020                 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1021                                 mem_crb + MIU_TEST_AGT_WRDATA(i));
1022                 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1023                                 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1024                 i = (off & 0xf) ? 2 : 0;
1025         }
1026
1027         writel(data & 0xffffffff,
1028                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1029         writel((data >> 32) & 0xffffffff,
1030                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1031
1032         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1033         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1034                         (mem_crb + TEST_AGT_CTRL));
1035
1036         for (j = 0; j < MAX_CTL_CHECK; j++) {
1037                 temp = readl(mem_crb + TEST_AGT_CTRL);
1038                 if ((temp & TA_CTL_BUSY) == 0)
1039                         break;
1040         }
1041
1042         if (j >= MAX_CTL_CHECK) {
1043                 if (printk_ratelimit())
1044                         dev_err(&adapter->pdev->dev,
1045                                         "failed to write through agent\n");
1046                 ret = -EIO;
1047         } else
1048                 ret = 0;
1049
1050 done:
1051         mutex_unlock(&adapter->ahw.mem_lock);
1052
1053         return ret;
1054 }
1055
1056 int
1057 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1058                 u64 off, u64 *data)
1059 {
1060         int j, ret;
1061         u32 temp, off8;
1062         u64 val, stride;
1063         void __iomem *mem_crb;
1064
1065         /* Only 64-bit aligned access */
1066         if (off & 7)
1067                 return -EIO;
1068
1069         /* P3 onward, test agent base for MIU and SIU is same */
1070         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1071                                 QLCNIC_ADDR_QDR_NET_MAX_P3)) {
1072                 mem_crb = qlcnic_get_ioaddr(adapter,
1073                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1074                 goto correct;
1075         }
1076
1077         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1078                 mem_crb = qlcnic_get_ioaddr(adapter,
1079                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1080                 goto correct;
1081         }
1082
1083         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1084                 return qlcnic_pci_mem_access_direct(adapter,
1085                                 off, data, 0);
1086         }
1087
1088         return -EIO;
1089
1090 correct:
1091         stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1092
1093         off8 = off & ~(stride-1);
1094
1095         mutex_lock(&adapter->ahw.mem_lock);
1096
1097         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1098         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1099         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1100         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1101
1102         for (j = 0; j < MAX_CTL_CHECK; j++) {
1103                 temp = readl(mem_crb + TEST_AGT_CTRL);
1104                 if ((temp & TA_CTL_BUSY) == 0)
1105                         break;
1106         }
1107
1108         if (j >= MAX_CTL_CHECK) {
1109                 if (printk_ratelimit())
1110                         dev_err(&adapter->pdev->dev,
1111                                         "failed to read through agent\n");
1112                 ret = -EIO;
1113         } else {
1114                 off8 = MIU_TEST_AGT_RDDATA_LO;
1115                 if ((stride == 16) && (off & 0xf))
1116                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1117
1118                 temp = readl(mem_crb + off8 + 4);
1119                 val = (u64)temp << 32;
1120                 val |= readl(mem_crb + off8);
1121                 *data = val;
1122                 ret = 0;
1123         }
1124
1125         mutex_unlock(&adapter->ahw.mem_lock);
1126
1127         return ret;
1128 }
1129
1130 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1131 {
1132         int offset, board_type, magic;
1133         struct pci_dev *pdev = adapter->pdev;
1134
1135         offset = QLCNIC_FW_MAGIC_OFFSET;
1136         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1137                 return -EIO;
1138
1139         if (magic != QLCNIC_BDINFO_MAGIC) {
1140                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1141                         magic);
1142                 return -EIO;
1143         }
1144
1145         offset = QLCNIC_BRDTYPE_OFFSET;
1146         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1147                 return -EIO;
1148
1149         adapter->ahw.board_type = board_type;
1150
1151         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1152                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1153                 if ((gpio & 0x8000) == 0)
1154                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1155         }
1156
1157         switch (board_type) {
1158         case QLCNIC_BRDTYPE_P3_HMEZ:
1159         case QLCNIC_BRDTYPE_P3_XG_LOM:
1160         case QLCNIC_BRDTYPE_P3_10G_CX4:
1161         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1162         case QLCNIC_BRDTYPE_P3_IMEZ:
1163         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1164         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1165         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1166         case QLCNIC_BRDTYPE_P3_10G_XFP:
1167         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1168                 adapter->ahw.port_type = QLCNIC_XGBE;
1169                 break;
1170         case QLCNIC_BRDTYPE_P3_REF_QG:
1171         case QLCNIC_BRDTYPE_P3_4_GB:
1172         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1173                 adapter->ahw.port_type = QLCNIC_GBE;
1174                 break;
1175         case QLCNIC_BRDTYPE_P3_10G_TP:
1176                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1177                         QLCNIC_XGBE : QLCNIC_GBE;
1178                 break;
1179         default:
1180                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1181                 adapter->ahw.port_type = QLCNIC_XGBE;
1182                 break;
1183         }
1184
1185         return 0;
1186 }
1187
1188 int
1189 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1190 {
1191         u32 wol_cfg;
1192
1193         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1194         if (wol_cfg & (1UL << adapter->portnum)) {
1195                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1196                 if (wol_cfg & (1 << adapter->portnum))
1197                         return 1;
1198         }
1199
1200         return 0;
1201 }
1202
1203 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1204 {
1205         struct qlcnic_nic_req   req;
1206         int rv;
1207         u64 word;
1208
1209         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1210         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1211
1212         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1213         req.req_hdr = cpu_to_le64(word);
1214
1215         req.words[0] = cpu_to_le64((u64)rate << 32);
1216         req.words[1] = cpu_to_le64(state);
1217
1218         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1219         if (rv)
1220                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1221
1222         return rv;
1223 }
1224
1225 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1226 {
1227         struct qlcnic_nic_req   req;
1228         int                     rv;
1229         u64                     word;
1230
1231         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1232         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1233
1234         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1235                         ((u64)adapter->portnum << 16);
1236         req.req_hdr = cpu_to_le64(word);
1237         req.words[0] = cpu_to_le64(flag);
1238
1239         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1240         if (rv)
1241                 dev_err(&adapter->pdev->dev,
1242                         "%sting loopback mode failed.\n",
1243                                         flag ? "Set" : "Reset");
1244         return rv;
1245 }
1246
1247 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1248 {
1249         if (qlcnic_set_fw_loopback(adapter, 1))
1250                 return -EIO;
1251
1252         if (qlcnic_nic_set_promisc(adapter,
1253                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1254                 qlcnic_set_fw_loopback(adapter, 0);
1255                 return -EIO;
1256         }
1257
1258         msleep(1000);
1259         return 0;
1260 }
1261
1262 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1263 {
1264         int mode = VPORT_MISS_MODE_DROP;
1265         struct net_device *netdev = adapter->netdev;
1266
1267         qlcnic_set_fw_loopback(adapter, 0);
1268
1269         if (netdev->flags & IFF_PROMISC)
1270                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1271         else if (netdev->flags & IFF_ALLMULTI)
1272                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1273
1274         qlcnic_nic_set_promisc(adapter, mode);
1275 }