SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/qla3xxx.c

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/mempool.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/kthread.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/if_ether.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/delay.h>
  35 #include <linux/mm.h>
  36
  37 #include "qla3xxx.h"
  38
  39 #define DRV_NAME        "qla3xxx"
  40 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
  41 #define DRV_VERSION     "v2.03.00-k4"
  42 #define PFX             DRV_NAME " "
  43
  44 static const char ql3xxx_driver_name[] = DRV_NAME;
  45 static const char ql3xxx_driver_version[] = DRV_VERSION;
  46
  47 MODULE_AUTHOR("QLogic Corporation");
  48 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  49 MODULE_LICENSE("GPL");
  50 MODULE_VERSION(DRV_VERSION);
  51
  52 static const u32 default_msg
  53     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  54     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  55
  56 static int debug = -1;          /* defaults above */
  57 module_param(debug, int, 0);
  58 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  59
  60 static int msi;
  61 module_param(msi, int, 0);
  62 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  63
  64 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  65         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  67         /* required last entry */
  68         {0,}
  69 };
  70
  71 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  72
  73 /*
  74  *  These are the known PHY's which are used
  75  */
  76 typedef enum {
  77    PHY_TYPE_UNKNOWN   = 0,
  78    PHY_VITESSE_VSC8211,
  79    PHY_AGERE_ET1011C,
  80    MAX_PHY_DEV_TYPES
  81 } PHY_DEVICE_et;
  82
  83 typedef struct {
  84         PHY_DEVICE_et phyDevice;
  85         u32             phyIdOUI;
  86         u16             phyIdModel;
  87         char            *name;
  88 } PHY_DEVICE_INFO_t;
  89
  90 static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
  91         {{PHY_TYPE_UNKNOWN,    0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
  92          {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
  93          {PHY_AGERE_ET1011C,   0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
  94 };
  95
  96
  97 /*
  98  * Caller must take hw_lock.
  99  */
 100 static int ql_sem_spinlock(struct ql3_adapter *qdev,
 101                             u32 sem_mask, u32 sem_bits)
 102 {
 103         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 104         u32 value;
 105         unsigned int seconds = 3;
 106
 107         do {
 108                 writel((sem_mask | sem_bits),
 109                        &port_regs->CommonRegs.semaphoreReg);
 110                 value = readl(&port_regs->CommonRegs.semaphoreReg);
 111                 if ((value & (sem_mask >> 16)) == sem_bits)
 112                         return 0;
 113                 ssleep(1);
 114         } while(--seconds);
 115         return -1;
 116 }
 117
 118 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
 119 {
 120         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 121         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
 122         readl(&port_regs->CommonRegs.semaphoreReg);
 123 }
 124
 125 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
 126 {
 127         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 128         u32 value;
 129
 130         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
 131         value = readl(&port_regs->CommonRegs.semaphoreReg);
 132         return ((value & (sem_mask >> 16)) == sem_bits);
 133 }
 134
 135 /*
 136  * Caller holds hw_lock.
 137  */
 138 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
 139 {
 140         int i = 0;
 141
 142         while (1) {
 143                 if (!ql_sem_lock(qdev,
 144                                  QL_DRVR_SEM_MASK,
 145                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
 146                                   * 2) << 1)) {
 147                         if (i < 10) {
 148                                 ssleep(1);
 149                                 i++;
 150                         } else {
 151                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
 152                                        "driver lock...\n",
 153                                        qdev->ndev->name);
 154                                 return 0;
 155                         }
 156                 } else {
 157                         printk(KERN_DEBUG PFX
 158                                "%s: driver lock acquired.\n",
 159                                qdev->ndev->name);
 160                         return 1;
 161                 }
 162         }
 163 }
 164
 165 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
 166 {
 167         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 168
 169         writel(((ISP_CONTROL_NP_MASK << 16) | page),
 170                         &port_regs->CommonRegs.ispControlStatus);
 171         readl(&port_regs->CommonRegs.ispControlStatus);
 172         qdev->current_page = page;
 173 }
 174
 175 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
 176                               u32 __iomem * reg)
 177 {
 178         u32 value;
 179         unsigned long hw_flags;
 180
 181         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 182         value = readl(reg);
 183         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 184
 185         return value;
 186 }
 187
 188 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
 189                               u32 __iomem * reg)
 190 {
 191         return readl(reg);
 192 }
 193
 194 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
 195 {
 196         u32 value;
 197         unsigned long hw_flags;
 198
 199         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 200
 201         if (qdev->current_page != 0)
 202                 ql_set_register_page(qdev,0);
 203         value = readl(reg);
 204
 205         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 206         return value;
 207 }
 208
 209 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
 210 {
 211         if (qdev->current_page != 0)
 212                 ql_set_register_page(qdev,0);
 213         return readl(reg);
 214 }
 215
 216 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
 217                                 u32 __iomem *reg, u32 value)
 218 {
 219         unsigned long hw_flags;
 220
 221         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 222         writel(value, reg);
 223         readl(reg);
 224         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 225         return;
 226 }
 227
 228 static void ql_write_common_reg(struct ql3_adapter *qdev,
 229                                 u32 __iomem *reg, u32 value)
 230 {
 231         writel(value, reg);
 232         readl(reg);
 233         return;
 234 }
 235
 236 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
 237                                 u32 __iomem *reg, u32 value)
 238 {
 239         writel(value, reg);
 240         readl(reg);
 241         udelay(1);
 242         return;
 243 }
 244
 245 static void ql_write_page0_reg(struct ql3_adapter *qdev,
 246                                u32 __iomem *reg, u32 value)
 247 {
 248         if (qdev->current_page != 0)
 249                 ql_set_register_page(qdev,0);
 250         writel(value, reg);
 251         readl(reg);
 252         return;
 253 }
 254
 255 /*
 256  * Caller holds hw_lock. Only called during init.
 257  */
 258 static void ql_write_page1_reg(struct ql3_adapter *qdev,
 259                                u32 __iomem *reg, u32 value)
 260 {
 261         if (qdev->current_page != 1)
 262                 ql_set_register_page(qdev,1);
 263         writel(value, reg);
 264         readl(reg);
 265         return;
 266 }
 267
 268 /*
 269  * Caller holds hw_lock. Only called during init.
 270  */
 271 static void ql_write_page2_reg(struct ql3_adapter *qdev,
 272                                u32 __iomem *reg, u32 value)
 273 {
 274         if (qdev->current_page != 2)
 275                 ql_set_register_page(qdev,2);
 276         writel(value, reg);
 277         readl(reg);
 278         return;
 279 }
 280
 281 static void ql_disable_interrupts(struct ql3_adapter *qdev)
 282 {
 283         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 284
 285         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 286                             (ISP_IMR_ENABLE_INT << 16));
 287
 288 }
 289
 290 static void ql_enable_interrupts(struct ql3_adapter *qdev)
 291 {
 292         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 293
 294         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 295                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
 296
 297 }
 298
 299 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
 300                                             struct ql_rcv_buf_cb *lrg_buf_cb)
 301 {
 302         dma_addr_t map;
 303         int err;
 304         lrg_buf_cb->next = NULL;
 305
 306         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
 307                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
 308         } else {
 309                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
 310                 qdev->lrg_buf_free_tail = lrg_buf_cb;
 311         }
 312
 313         if (!lrg_buf_cb->skb) {
 314                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
 315                                                    qdev->lrg_buffer_len);
 316                 if (unlikely(!lrg_buf_cb->skb)) {
 317                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
 318                                qdev->ndev->name);
 319                         qdev->lrg_buf_skb_check++;
 320                 } else {
 321                         /*
 322                          * We save some space to copy the ethhdr from first
 323                          * buffer
 324                          */
 325                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
 326                         map = pci_map_single(qdev->pdev,
 327                                              lrg_buf_cb->skb->data,
 328                                              qdev->lrg_buffer_len -
 329                                              QL_HEADER_SPACE,
 330                                              PCI_DMA_FROMDEVICE);
 331                         err = pci_dma_mapping_error(map);
 332                         if(err) {
 333                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
 334                                        qdev->ndev->name, err);
 335                                 dev_kfree_skb(lrg_buf_cb->skb);
 336                                 lrg_buf_cb->skb = NULL;
 337
 338                                 qdev->lrg_buf_skb_check++;
 339                                 return;
 340                         }
 341
 342                         lrg_buf_cb->buf_phy_addr_low =
 343                             cpu_to_le32(LS_64BITS(map));
 344                         lrg_buf_cb->buf_phy_addr_high =
 345                             cpu_to_le32(MS_64BITS(map));
 346                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
 347                         pci_unmap_len_set(lrg_buf_cb, maplen,
 348                                           qdev->lrg_buffer_len -
 349                                           QL_HEADER_SPACE);
 350                 }
 351         }
 352
 353         qdev->lrg_buf_free_count++;
 354 }
 355
 356 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
 357                                                            *qdev)
 358 {
 359         struct ql_rcv_buf_cb *lrg_buf_cb;
 360
 361         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
 362                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
 363                         qdev->lrg_buf_free_tail = NULL;
 364                 qdev->lrg_buf_free_count--;
 365         }
 366
 367         return lrg_buf_cb;
 368 }
 369
 370 static u32 addrBits = EEPROM_NO_ADDR_BITS;
 371 static u32 dataBits = EEPROM_NO_DATA_BITS;
 372
 373 static void fm93c56a_deselect(struct ql3_adapter *qdev);
 374 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
 375                             unsigned short *value);
 376
 377 /*
 378  * Caller holds hw_lock.
 379  */
 380 static void fm93c56a_select(struct ql3_adapter *qdev)
 381 {
 382         struct ql3xxx_port_registers __iomem *port_regs =
 383                         qdev->mem_map_registers;
 384
 385         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
 386         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 387                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 388         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 389                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
 390 }
 391
 392 /*
 393  * Caller holds hw_lock.
 394  */
 395 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
 396 {
 397         int i;
 398         u32 mask;
 399         u32 dataBit;
 400         u32 previousBit;
 401         struct ql3xxx_port_registers __iomem *port_regs =
 402                         qdev->mem_map_registers;
 403
 404         /* Clock in a zero, then do the start bit */
 405         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 406                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 407                             AUBURN_EEPROM_DO_1);
 408         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 409                             ISP_NVRAM_MASK | qdev->
 410                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 411                             AUBURN_EEPROM_CLK_RISE);
 412         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 413                             ISP_NVRAM_MASK | qdev->
 414                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 415                             AUBURN_EEPROM_CLK_FALL);
 416
 417         mask = 1 << (FM93C56A_CMD_BITS - 1);
 418         /* Force the previous data bit to be different */
 419         previousBit = 0xffff;
 420         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
 421                 dataBit =
 422                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
 423                 if (previousBit != dataBit) {
 424                         /*
 425                          * If the bit changed, then change the DO state to
 426                          * match
 427                          */
 428                         ql_write_nvram_reg(qdev,
 429                                             &port_regs->CommonRegs.
 430                                             serialPortInterfaceReg,
 431                                             ISP_NVRAM_MASK | qdev->
 432                                             eeprom_cmd_data | dataBit);
 433                         previousBit = dataBit;
 434                 }
 435                 ql_write_nvram_reg(qdev,
 436                                     &port_regs->CommonRegs.
 437                                     serialPortInterfaceReg,
 438                                     ISP_NVRAM_MASK | qdev->
 439                                     eeprom_cmd_data | dataBit |
 440                                     AUBURN_EEPROM_CLK_RISE);
 441                 ql_write_nvram_reg(qdev,
 442                                     &port_regs->CommonRegs.
 443                                     serialPortInterfaceReg,
 444                                     ISP_NVRAM_MASK | qdev->
 445                                     eeprom_cmd_data | dataBit |
 446                                     AUBURN_EEPROM_CLK_FALL);
 447                 cmd = cmd << 1;
 448         }
 449
 450         mask = 1 << (addrBits - 1);
 451         /* Force the previous data bit to be different */
 452         previousBit = 0xffff;
 453         for (i = 0; i < addrBits; i++) {
 454                 dataBit =
 455                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
 456                     AUBURN_EEPROM_DO_0;
 457                 if (previousBit != dataBit) {
 458                         /*
 459                          * If the bit changed, then change the DO state to
 460                          * match
 461                          */
 462                         ql_write_nvram_reg(qdev,
 463                                             &port_regs->CommonRegs.
 464                                             serialPortInterfaceReg,
 465                                             ISP_NVRAM_MASK | qdev->
 466                                             eeprom_cmd_data | dataBit);
 467                         previousBit = dataBit;
 468                 }
 469                 ql_write_nvram_reg(qdev,
 470                                     &port_regs->CommonRegs.
 471                                     serialPortInterfaceReg,
 472                                     ISP_NVRAM_MASK | qdev->
 473                                     eeprom_cmd_data | dataBit |
 474                                     AUBURN_EEPROM_CLK_RISE);
 475                 ql_write_nvram_reg(qdev,
 476                                     &port_regs->CommonRegs.
 477                                     serialPortInterfaceReg,
 478                                     ISP_NVRAM_MASK | qdev->
 479                                     eeprom_cmd_data | dataBit |
 480                                     AUBURN_EEPROM_CLK_FALL);
 481                 eepromAddr = eepromAddr << 1;
 482         }
 483 }
 484
 485 /*
 486  * Caller holds hw_lock.
 487  */
 488 static void fm93c56a_deselect(struct ql3_adapter *qdev)
 489 {
 490         struct ql3xxx_port_registers __iomem *port_regs =
 491                         qdev->mem_map_registers;
 492         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
 493         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 494                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 495 }
 496
 497 /*
 498  * Caller holds hw_lock.
 499  */
 500 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
 501 {
 502         int i;
 503         u32 data = 0;
 504         u32 dataBit;
 505         struct ql3xxx_port_registers __iomem *port_regs =
 506                         qdev->mem_map_registers;
 507
 508         /* Read the data bits */
 509         /* The first bit is a dummy.  Clock right over it. */
 510         for (i = 0; i < dataBits; i++) {
 511                 ql_write_nvram_reg(qdev,
 512                                     &port_regs->CommonRegs.
 513                                     serialPortInterfaceReg,
 514                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 515                                     AUBURN_EEPROM_CLK_RISE);
 516                 ql_write_nvram_reg(qdev,
 517                                     &port_regs->CommonRegs.
 518                                     serialPortInterfaceReg,
 519                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 520                                     AUBURN_EEPROM_CLK_FALL);
 521                 dataBit =
 522                     (ql_read_common_reg
 523                      (qdev,
 524                       &port_regs->CommonRegs.
 525                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
 526                 data = (data << 1) | dataBit;
 527         }
 528         *value = (u16) data;
 529 }
 530
 531 /*
 532  * Caller holds hw_lock.
 533  */
 534 static void eeprom_readword(struct ql3_adapter *qdev,
 535                             u32 eepromAddr, unsigned short *value)
 536 {
 537         fm93c56a_select(qdev);
 538         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
 539         fm93c56a_datain(qdev, value);
 540         fm93c56a_deselect(qdev);
 541 }
 542
 543 static void ql_swap_mac_addr(u8 * macAddress)
 544 {
 545 #ifdef __BIG_ENDIAN
 546         u8 temp;
 547         temp = macAddress[0];
 548         macAddress[0] = macAddress[1];
 549         macAddress[1] = temp;
 550         temp = macAddress[2];
 551         macAddress[2] = macAddress[3];
 552         macAddress[3] = temp;
 553         temp = macAddress[4];
 554         macAddress[4] = macAddress[5];
 555         macAddress[5] = temp;
 556 #endif
 557 }
 558
 559 static int ql_get_nvram_params(struct ql3_adapter *qdev)
 560 {
 561         u16 *pEEPROMData;
 562         u16 checksum = 0;
 563         u32 index;
 564         unsigned long hw_flags;
 565
 566         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 567
 568         pEEPROMData = (u16 *) & qdev->nvram_data;
 569         qdev->eeprom_cmd_data = 0;
 570         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
 571                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
 572                          2) << 10)) {
 573                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
 574                         __func__);
 575                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 576                 return -1;
 577         }
 578
 579         for (index = 0; index < EEPROM_SIZE; index++) {
 580                 eeprom_readword(qdev, index, pEEPROMData);
 581                 checksum += *pEEPROMData;
 582                 pEEPROMData++;
 583         }
 584         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
 585
 586         if (checksum != 0) {
 587                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
 588                        qdev->ndev->name, checksum);
 589                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 590                 return -1;
 591         }
 592
 593         /*
 594          * We have a problem with endianness for the MAC addresses
 595          * and the two 8-bit values version, and numPorts.  We
 596          * have to swap them on big endian systems.
 597          */
 598         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
 599         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
 600         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
 601         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
 602         pEEPROMData = (u16 *) & qdev->nvram_data.version;
 603         *pEEPROMData = le16_to_cpu(*pEEPROMData);
 604
 605         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 606         return checksum;
 607 }
 608
 609 static const u32 PHYAddr[2] = {
 610         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
 611 };
 612
 613 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
 614 {
 615         struct ql3xxx_port_registers __iomem *port_regs =
 616                         qdev->mem_map_registers;
 617         u32 temp;
 618         int count = 1000;
 619
 620         while (count) {
 621                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
 622                 if (!(temp & MAC_MII_STATUS_BSY))
 623                         return 0;
 624                 udelay(10);
 625                 count--;
 626         }
 627         return -1;
 628 }
 629
 630 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
 631 {
 632         struct ql3xxx_port_registers __iomem *port_regs =
 633                         qdev->mem_map_registers;
 634         u32 scanControl;
 635
 636         if (qdev->numPorts > 1) {
 637                 /* Auto scan will cycle through multiple ports */
 638                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
 639         } else {
 640                 scanControl = MAC_MII_CONTROL_SC;
 641         }
 642
 643         /*
 644          * Scan register 1 of PHY/PETBI,
 645          * Set up to scan both devices
 646          * The autoscan starts from the first register, completes
 647          * the last one before rolling over to the first
 648          */
 649         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 650                            PHYAddr[0] | MII_SCAN_REGISTER);
 651
 652         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 653                            (scanControl) |
 654                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
 655 }
 656
 657 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
 658 {
 659         u8 ret;
 660         struct ql3xxx_port_registers __iomem *port_regs =
 661                                         qdev->mem_map_registers;
 662
 663         /* See if scan mode is enabled before we turn it off */
 664         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
 665             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
 666                 /* Scan is enabled */
 667                 ret = 1;
 668         } else {
 669                 /* Scan is disabled */
 670                 ret = 0;
 671         }
 672
 673         /*
 674          * When disabling scan mode you must first change the MII register
 675          * address
 676          */
 677         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 678                            PHYAddr[0] | MII_SCAN_REGISTER);
 679
 680         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 681                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
 682                              MAC_MII_CONTROL_RC) << 16));
 683
 684         return ret;
 685 }
 686
 687 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
 688                                u16 regAddr, u16 value, u32 phyAddr)
 689 {
 690         struct ql3xxx_port_registers __iomem *port_regs =
 691                         qdev->mem_map_registers;
 692         u8 scanWasEnabled;
 693
 694         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 695
 696         if (ql_wait_for_mii_ready(qdev)) {
 697                 if (netif_msg_link(qdev))
 698                         printk(KERN_WARNING PFX
 699                                "%s Timed out waiting for management port to "
 700                                "get free before issuing command.\n",
 701                                qdev->ndev->name);
 702                 return -1;
 703         }
 704
 705         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 706                            phyAddr | regAddr);
 707
 708         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 709
 710         /* Wait for write to complete 9/10/04 SJP */
 711         if (ql_wait_for_mii_ready(qdev)) {
 712                 if (netif_msg_link(qdev))
 713                         printk(KERN_WARNING PFX
 714                                "%s: Timed out waiting for management port to"
 715                                "get free before issuing command.\n",
 716                                qdev->ndev->name);
 717                 return -1;
 718         }
 719
 720         if (scanWasEnabled)
 721                 ql_mii_enable_scan_mode(qdev);
 722
 723         return 0;
 724 }
 725
 726 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
 727                               u16 * value, u32 phyAddr)
 728 {
 729         struct ql3xxx_port_registers __iomem *port_regs =
 730                         qdev->mem_map_registers;
 731         u8 scanWasEnabled;
 732         u32 temp;
 733
 734         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 735
 736         if (ql_wait_for_mii_ready(qdev)) {
 737                 if (netif_msg_link(qdev))
 738                         printk(KERN_WARNING PFX
 739                                "%s: Timed out waiting for management port to "
 740                                "get free before issuing command.\n",
 741                                qdev->ndev->name);
 742                 return -1;
 743         }
 744
 745         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 746                            phyAddr | regAddr);
 747
 748         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 749                            (MAC_MII_CONTROL_RC << 16));
 750
 751         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 752                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 753
 754         /* Wait for the read to complete */
 755         if (ql_wait_for_mii_ready(qdev)) {
 756                 if (netif_msg_link(qdev))
 757                         printk(KERN_WARNING PFX
 758                                "%s: Timed out waiting for management port to "
 759                                "get free after issuing command.\n",
 760                                qdev->ndev->name);
 761                 return -1;
 762         }
 763
 764         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 765         *value = (u16) temp;
 766
 767         if (scanWasEnabled)
 768                 ql_mii_enable_scan_mode(qdev);
 769
 770         return 0;
 771 }
 772
 773 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
 774 {
 775         struct ql3xxx_port_registers __iomem *port_regs =
 776                         qdev->mem_map_registers;
 777
 778         ql_mii_disable_scan_mode(qdev);
 779
 780         if (ql_wait_for_mii_ready(qdev)) {
 781                 if (netif_msg_link(qdev))
 782                         printk(KERN_WARNING PFX
 783                                "%s: Timed out waiting for management port to "
 784                                "get free before issuing command.\n",
 785                                qdev->ndev->name);
 786                 return -1;
 787         }
 788
 789         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 790                            qdev->PHYAddr | regAddr);
 791
 792         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 793
 794         /* Wait for write to complete. */
 795         if (ql_wait_for_mii_ready(qdev)) {
 796                 if (netif_msg_link(qdev))
 797                         printk(KERN_WARNING PFX
 798                                "%s: Timed out waiting for management port to "
 799                                "get free before issuing command.\n",
 800                                qdev->ndev->name);
 801                 return -1;
 802         }
 803
 804         ql_mii_enable_scan_mode(qdev);
 805
 806         return 0;
 807 }
 808
 809 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
 810 {
 811         u32 temp;
 812         struct ql3xxx_port_registers __iomem *port_regs =
 813                         qdev->mem_map_registers;
 814
 815         ql_mii_disable_scan_mode(qdev);
 816
 817         if (ql_wait_for_mii_ready(qdev)) {
 818                 if (netif_msg_link(qdev))
 819                         printk(KERN_WARNING PFX
 820                                "%s: Timed out waiting for management port to "
 821                                "get free before issuing command.\n",
 822                                qdev->ndev->name);
 823                 return -1;
 824         }
 825
 826         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 827                            qdev->PHYAddr | regAddr);
 828
 829         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 830                            (MAC_MII_CONTROL_RC << 16));
 831
 832         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 833                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 834
 835         /* Wait for the read to complete */
 836         if (ql_wait_for_mii_ready(qdev)) {
 837                 if (netif_msg_link(qdev))
 838                         printk(KERN_WARNING PFX
 839                                "%s: Timed out waiting for management port to "
 840                                "get free before issuing command.\n",
 841                                qdev->ndev->name);
 842                 return -1;
 843         }
 844
 845         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 846         *value = (u16) temp;
 847
 848         ql_mii_enable_scan_mode(qdev);
 849
 850         return 0;
 851 }
 852
 853 static void ql_petbi_reset(struct ql3_adapter *qdev)
 854 {
 855         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
 856 }
 857
 858 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
 859 {
 860         u16 reg;
 861
 862         /* Enable Auto-negotiation sense */
 863         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
 864         reg |= PETBI_TBI_AUTO_SENSE;
 865         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
 866
 867         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
 868                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
 869
 870         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
 871                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 872                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
 873
 874 }
 875
 876 static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
 877 {
 878         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
 879                             PHYAddr[qdev->mac_index]);
 880 }
 881
 882 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
 883 {
 884         u16 reg;
 885
 886         /* Enable Auto-negotiation sense */
 887         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
 888                            PHYAddr[qdev->mac_index]);
 889         reg |= PETBI_TBI_AUTO_SENSE;
 890         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
 891                             PHYAddr[qdev->mac_index]);
 892
 893         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
 894                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
 895                             PHYAddr[qdev->mac_index]);
 896
 897         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
 898                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 899                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
 900                             PHYAddr[qdev->mac_index]);
 901 }
 902
 903 static void ql_petbi_init(struct ql3_adapter *qdev)
 904 {
 905         ql_petbi_reset(qdev);
 906         ql_petbi_start_neg(qdev);
 907 }
 908
 909 static void ql_petbi_init_ex(struct ql3_adapter *qdev)
 910 {
 911         ql_petbi_reset_ex(qdev);
 912         ql_petbi_start_neg_ex(qdev);
 913 }
 914
 915 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
 916 {
 917         u16 reg;
 918
 919         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
 920                 return 0;
 921
 922         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
 923 }
 924
 925 static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
 926 {
 927         printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
 928         /* power down device bit 11 = 1 */
 929         ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
 930         /* enable diagnostic mode bit 2 = 1 */
 931         ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
 932         /* 1000MB amplitude adjust (see Agere errata) */
 933         ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
 934         /* 1000MB amplitude adjust (see Agere errata) */
 935         ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
 936         /* 100MB amplitude adjust (see Agere errata) */
 937         ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
 938         /* 100MB amplitude adjust (see Agere errata) */
 939         ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
 940         /* 10MB amplitude adjust (see Agere errata) */
 941         ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
 942         /* 10MB amplitude adjust (see Agere errata) */
 943         ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
 944         /* point to hidden reg 0x2806 */
 945         ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
 946         /* Write new PHYAD w/bit 5 set */
 947         ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
 948         /*
 949          * Disable diagnostic mode bit 2 = 0
 950          * Power up device bit 11 = 0
 951          * Link up (on) and activity (blink)
 952          */
 953         ql_mii_write_reg(qdev, 0x12, 0x840a);
 954         ql_mii_write_reg(qdev, 0x00, 0x1140);
 955         ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
 956 }
 957
 958 static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
 959                                  u16 phyIdReg0, u16 phyIdReg1)
 960 {
 961         PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
 962         u32   oui;
 963         u16   model;
 964         int i;
 965
 966         if (phyIdReg0 == 0xffff) {
 967                 return result;
 968         }
 969
 970         if (phyIdReg1 == 0xffff) {
 971                 return result;
 972         }
 973
 974         /* oui is split between two registers */
 975         oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
 976
 977         model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
 978
 979         /* Scan table for this PHY */
 980         for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
 981                 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
 982                 {
 983                         result = PHY_DEVICES[i].phyDevice;
 984
 985                         printk(KERN_INFO "%s: Phy: %s\n",
 986                                 qdev->ndev->name, PHY_DEVICES[i].name);
 987
 988                         break;
 989                 }
 990         }
 991
 992         return result;
 993 }
 994
 995 static int ql_phy_get_speed(struct ql3_adapter *qdev)
 996 {
 997         u16 reg;
 998
 999         switch(qdev->phyType) {
1000         case PHY_AGERE_ET1011C:
1001         {
1002                 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
1003                         return 0;
1004
1005                 reg = (reg >> 8) & 3;
1006                 break;
1007         }
1008         default:
1009         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1010                 return 0;
1011
1012         reg = (((reg & 0x18) >> 3) & 3);
1013         }
1014
1015         switch(reg) {
1016                 case 2:
1017                 return SPEED_1000;
1018                 case 1:
1019                 return SPEED_100;
1020                 case 0:
1021                 return SPEED_10;
1022                 default:
1023                 return -1;
1024         }
1025 }
1026
1027 static int ql_is_full_dup(struct ql3_adapter *qdev)
1028 {
1029         u16 reg;
1030
1031         switch(qdev->phyType) {
1032         case PHY_AGERE_ET1011C:
1033         {
1034                 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1035                         return 0;
1036
1037                 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1038         }
1039         case PHY_VITESSE_VSC8211:
1040         default:
1041         {
1042                 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1043                         return 0;
1044                 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1045         }
1046         }
1047 }
1048
1049 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1050 {
1051         u16 reg;
1052
1053         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1054                 return 0;
1055
1056         return (reg & PHY_NEG_PAUSE) != 0;
1057 }
1058
1059 static int PHY_Setup(struct ql3_adapter *qdev)
1060 {
1061         u16   reg1;
1062         u16   reg2;
1063         bool  agereAddrChangeNeeded = false;
1064         u32 miiAddr = 0;
1065         int err;
1066
1067         /*  Determine the PHY we are using by reading the ID's */
1068         err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1069         if(err != 0) {
1070                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1071                        qdev->ndev->name);
1072                 return err;
1073         }
1074
1075         err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1076         if(err != 0) {
1077                 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1078                        qdev->ndev->name);
1079                 return err;
1080         }
1081
1082         /*  Check if we have a Agere PHY */
1083         if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1084
1085                 /* Determine which MII address we should be using
1086                    determined by the index of the card */
1087                 if (qdev->mac_index == 0) {
1088                         miiAddr = MII_AGERE_ADDR_1;
1089                 } else {
1090                         miiAddr = MII_AGERE_ADDR_2;
1091                 }
1092
1093                 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1094                 if(err != 0) {
1095                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1096                                qdev->ndev->name);
1097                         return err;
1098                 }
1099
1100                 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1101                 if(err != 0) {
1102                         printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1103                                qdev->ndev->name);
1104                         return err;
1105                 }
1106
1107                 /*  We need to remember to initialize the Agere PHY */
1108                 agereAddrChangeNeeded = true;
1109         }
1110
1111         /*  Determine the particular PHY we have on board to apply
1112             PHY specific initializations */
1113         qdev->phyType = getPhyType(qdev, reg1, reg2);
1114
1115         if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1116                 /* need this here so address gets changed */
1117                 phyAgereSpecificInit(qdev, miiAddr);
1118         } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1119                 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1120                 return -EIO;
1121         }
1122
1123         return 0;
1124 }
1125
1126 /*
1127  * Caller holds hw_lock.
1128  */
1129 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1130 {
1131         struct ql3xxx_port_registers __iomem *port_regs =
1132                         qdev->mem_map_registers;
1133         u32 value;
1134
1135         if (enable)
1136                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1137         else
1138                 value = (MAC_CONFIG_REG_PE << 16);
1139
1140         if (qdev->mac_index)
1141                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1142         else
1143                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1144 }
1145
1146 /*
1147  * Caller holds hw_lock.
1148  */
1149 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1150 {
1151         struct ql3xxx_port_registers __iomem *port_regs =
1152                         qdev->mem_map_registers;
1153         u32 value;
1154
1155         if (enable)
1156                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1157         else
1158                 value = (MAC_CONFIG_REG_SR << 16);
1159
1160         if (qdev->mac_index)
1161                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1162         else
1163                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1164 }
1165
1166 /*
1167  * Caller holds hw_lock.
1168  */
1169 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1170 {
1171         struct ql3xxx_port_registers __iomem *port_regs =
1172                         qdev->mem_map_registers;
1173         u32 value;
1174
1175         if (enable)
1176                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1177         else
1178                 value = (MAC_CONFIG_REG_GM << 16);
1179
1180         if (qdev->mac_index)
1181                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1182         else
1183                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1184 }
1185
1186 /*
1187  * Caller holds hw_lock.
1188  */
1189 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1190 {
1191         struct ql3xxx_port_registers __iomem *port_regs =
1192                         qdev->mem_map_registers;
1193         u32 value;
1194
1195         if (enable)
1196                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1197         else
1198                 value = (MAC_CONFIG_REG_FD << 16);
1199
1200         if (qdev->mac_index)
1201                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1202         else
1203                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1204 }
1205
1206 /*
1207  * Caller holds hw_lock.
1208  */
1209 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1210 {
1211         struct ql3xxx_port_registers __iomem *port_regs =
1212                         qdev->mem_map_registers;
1213         u32 value;
1214
1215         if (enable)
1216                 value =
1217                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1218                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1219         else
1220                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1221
1222         if (qdev->mac_index)
1223                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1224         else
1225                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1226 }
1227
1228 /*
1229  * Caller holds hw_lock.
1230  */
1231 static int ql_is_fiber(struct ql3_adapter *qdev)
1232 {
1233         struct ql3xxx_port_registers __iomem *port_regs =
1234                         qdev->mem_map_registers;
1235         u32 bitToCheck = 0;
1236         u32 temp;
1237
1238         switch (qdev->mac_index) {
1239         case 0:
1240                 bitToCheck = PORT_STATUS_SM0;
1241                 break;
1242         case 1:
1243                 bitToCheck = PORT_STATUS_SM1;
1244                 break;
1245         }
1246
1247         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1248         return (temp & bitToCheck) != 0;
1249 }
1250
1251 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1252 {
1253         u16 reg;
1254         ql_mii_read_reg(qdev, 0x00, &reg);
1255         return (reg & 0x1000) != 0;
1256 }
1257
1258 /*
1259  * Caller holds hw_lock.
1260  */
1261 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1262 {
1263         struct ql3xxx_port_registers __iomem *port_regs =
1264                         qdev->mem_map_registers;
1265         u32 bitToCheck = 0;
1266         u32 temp;
1267
1268         switch (qdev->mac_index) {
1269         case 0:
1270                 bitToCheck = PORT_STATUS_AC0;
1271                 break;
1272         case 1:
1273                 bitToCheck = PORT_STATUS_AC1;
1274                 break;
1275         }
1276
1277         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1278         if (temp & bitToCheck) {
1279                 if (netif_msg_link(qdev))
1280                         printk(KERN_INFO PFX
1281                                "%s: Auto-Negotiate complete.\n",
1282                                qdev->ndev->name);
1283                 return 1;
1284         } else {
1285                 if (netif_msg_link(qdev))
1286                         printk(KERN_WARNING PFX
1287                                "%s: Auto-Negotiate incomplete.\n",
1288                                qdev->ndev->name);
1289                 return 0;
1290         }
1291 }
1292
1293 /*
1294  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1295  */
1296 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1297 {
1298         if (ql_is_fiber(qdev))
1299                 return ql_is_petbi_neg_pause(qdev);
1300         else
1301                 return ql_is_phy_neg_pause(qdev);
1302 }
1303
1304 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1305 {
1306         struct ql3xxx_port_registers __iomem *port_regs =
1307                         qdev->mem_map_registers;
1308         u32 bitToCheck = 0;
1309         u32 temp;
1310
1311         switch (qdev->mac_index) {
1312         case 0:
1313                 bitToCheck = PORT_STATUS_AE0;
1314                 break;
1315         case 1:
1316                 bitToCheck = PORT_STATUS_AE1;
1317                 break;
1318         }
1319         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1320         return (temp & bitToCheck) != 0;
1321 }
1322
1323 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1324 {
1325         if (ql_is_fiber(qdev))
1326                 return SPEED_1000;
1327         else
1328                 return ql_phy_get_speed(qdev);
1329 }
1330
1331 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1332 {
1333         if (ql_is_fiber(qdev))
1334                 return 1;
1335         else
1336                 return ql_is_full_dup(qdev);
1337 }
1338
1339 /*
1340  * Caller holds hw_lock.
1341  */
1342 static int ql_link_down_detect(struct ql3_adapter *qdev)
1343 {
1344         struct ql3xxx_port_registers __iomem *port_regs =
1345                         qdev->mem_map_registers;
1346         u32 bitToCheck = 0;
1347         u32 temp;
1348
1349         switch (qdev->mac_index) {
1350         case 0:
1351                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1352                 break;
1353         case 1:
1354                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1355                 break;
1356         }
1357
1358         temp =
1359             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1360         return (temp & bitToCheck) != 0;
1361 }
1362
1363 /*
1364  * Caller holds hw_lock.
1365  */
1366 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1367 {
1368         struct ql3xxx_port_registers __iomem *port_regs =
1369                         qdev->mem_map_registers;
1370
1371         switch (qdev->mac_index) {
1372         case 0:
1373                 ql_write_common_reg(qdev,
1374                                     &port_regs->CommonRegs.ispControlStatus,
1375                                     (ISP_CONTROL_LINK_DN_0) |
1376                                     (ISP_CONTROL_LINK_DN_0 << 16));
1377                 break;
1378
1379         case 1:
1380                 ql_write_common_reg(qdev,
1381                                     &port_regs->CommonRegs.ispControlStatus,
1382                                     (ISP_CONTROL_LINK_DN_1) |
1383                                     (ISP_CONTROL_LINK_DN_1 << 16));
1384                 break;
1385
1386         default:
1387                 return 1;
1388         }
1389
1390         return 0;
1391 }
1392
1393 /*
1394  * Caller holds hw_lock.
1395  */
1396 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1397 {
1398         struct ql3xxx_port_registers __iomem *port_regs =
1399                         qdev->mem_map_registers;
1400         u32 bitToCheck = 0;
1401         u32 temp;
1402
1403         switch (qdev->mac_index) {
1404         case 0:
1405                 bitToCheck = PORT_STATUS_F1_ENABLED;
1406                 break;
1407         case 1:
1408                 bitToCheck = PORT_STATUS_F3_ENABLED;
1409                 break;
1410         default:
1411                 break;
1412         }
1413
1414         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1415         if (temp & bitToCheck) {
1416                 if (netif_msg_link(qdev))
1417                         printk(KERN_DEBUG PFX
1418                                "%s: is not link master.\n", qdev->ndev->name);
1419                 return 0;
1420         } else {
1421                 if (netif_msg_link(qdev))
1422                         printk(KERN_DEBUG PFX
1423                                "%s: is link master.\n", qdev->ndev->name);
1424                 return 1;
1425         }
1426 }
1427
1428 static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1429 {
1430         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1431                             PHYAddr[qdev->mac_index]);
1432 }
1433
1434 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1435 {
1436         u16 reg;
1437         u16 portConfiguration;
1438
1439         if(qdev->phyType == PHY_AGERE_ET1011C) {
1440                 /* turn off external loopback */
1441                 ql_mii_write_reg(qdev, 0x13, 0x0000);
1442         }
1443
1444         if(qdev->mac_index == 0)
1445                 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1446         else
1447                 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1448
1449         /*  Some HBA's in the field are set to 0 and they need to
1450             be reinterpreted with a default value */
1451         if(portConfiguration == 0)
1452                 portConfiguration = PORT_CONFIG_DEFAULT;
1453
1454         /* Set the 1000 advertisements */
1455         ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
1456                            PHYAddr[qdev->mac_index]);
1457         reg &= ~PHY_GIG_ALL_PARAMS;
1458
1459         if(portConfiguration &
1460            PORT_CONFIG_FULL_DUPLEX_ENABLED &
1461            PORT_CONFIG_1000MB_SPEED) {
1462                 reg |= PHY_GIG_ADV_1000F;
1463         }
1464
1465         if(portConfiguration &
1466            PORT_CONFIG_HALF_DUPLEX_ENABLED &
1467            PORT_CONFIG_1000MB_SPEED) {
1468                 reg |= PHY_GIG_ADV_1000H;
1469         }
1470
1471         ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1472                             PHYAddr[qdev->mac_index]);
1473
1474         /* Set the 10/100 & pause negotiation advertisements */
1475         ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1476                            PHYAddr[qdev->mac_index]);
1477         reg &= ~PHY_NEG_ALL_PARAMS;
1478
1479         if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1480                 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1481
1482         if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1483                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1484                         reg |= PHY_NEG_ADV_100F;
1485
1486                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1487                         reg |= PHY_NEG_ADV_10F;
1488         }
1489
1490         if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1491                 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1492                         reg |= PHY_NEG_ADV_100H;
1493
1494                 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1495                         reg |= PHY_NEG_ADV_10H;
1496         }
1497
1498         if(portConfiguration &
1499            PORT_CONFIG_1000MB_SPEED) {
1500                 reg |= 1;
1501         }
1502
1503         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1504                             PHYAddr[qdev->mac_index]);
1505
1506         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
1507
1508         ql_mii_write_reg_ex(qdev, CONTROL_REG,
1509                             reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1510                             PHYAddr[qdev->mac_index]);
1511 }
1512
1513 static void ql_phy_init_ex(struct ql3_adapter *qdev)
1514 {
1515         ql_phy_reset_ex(qdev);
1516         PHY_Setup(qdev);
1517         ql_phy_start_neg_ex(qdev);
1518 }
1519
1520 /*
1521  * Caller holds hw_lock.
1522  */
1523 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1524 {
1525         struct ql3xxx_port_registers __iomem *port_regs =
1526                         qdev->mem_map_registers;
1527         u32 bitToCheck = 0;
1528         u32 temp, linkState;
1529
1530         switch (qdev->mac_index) {
1531         case 0:
1532                 bitToCheck = PORT_STATUS_UP0;
1533                 break;
1534         case 1:
1535                 bitToCheck = PORT_STATUS_UP1;
1536                 break;
1537         }
1538         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1539         if (temp & bitToCheck) {
1540                 linkState = LS_UP;
1541         } else {
1542                 linkState = LS_DOWN;
1543                 if (netif_msg_link(qdev))
1544                         printk(KERN_WARNING PFX
1545                                "%s: Link is down.\n", qdev->ndev->name);
1546         }
1547         return linkState;
1548 }
1549
1550 static int ql_port_start(struct ql3_adapter *qdev)
1551 {
1552         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1553                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1554                          2) << 7)) {
1555                 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1556                        qdev->ndev->name);
1557                 return -1;
1558         }
1559
1560         if (ql_is_fiber(qdev)) {
1561                 ql_petbi_init(qdev);
1562         } else {
1563                 /* Copper port */
1564                 ql_phy_init_ex(qdev);
1565         }
1566
1567         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1568         return 0;
1569 }
1570
1571 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1572 {
1573
1574         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1575                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1576                          2) << 7))
1577                 return -1;
1578
1579         if (!ql_auto_neg_error(qdev)) {
1580                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1581                         /* configure the MAC */
1582                         if (netif_msg_link(qdev))
1583                                 printk(KERN_DEBUG PFX
1584                                        "%s: Configuring link.\n",
1585                                        qdev->ndev->
1586                                        name);
1587                         ql_mac_cfg_soft_reset(qdev, 1);
1588                         ql_mac_cfg_gig(qdev,
1589                                        (ql_get_link_speed
1590                                         (qdev) ==
1591                                         SPEED_1000));
1592                         ql_mac_cfg_full_dup(qdev,
1593                                             ql_is_link_full_dup
1594                                             (qdev));
1595                         ql_mac_cfg_pause(qdev,
1596                                          ql_is_neg_pause
1597                                          (qdev));
1598                         ql_mac_cfg_soft_reset(qdev, 0);
1599
1600                         /* enable the MAC */
1601                         if (netif_msg_link(qdev))
1602                                 printk(KERN_DEBUG PFX
1603                                        "%s: Enabling mac.\n",
1604                                        qdev->ndev->
1605                                                name);
1606                         ql_mac_enable(qdev, 1);
1607                 }
1608
1609                 if (netif_msg_link(qdev))
1610                         printk(KERN_DEBUG PFX
1611                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1612                                qdev->ndev->name);
1613                 qdev->port_link_state = LS_UP;
1614                 netif_start_queue(qdev->ndev);
1615                 netif_carrier_on(qdev->ndev);
1616                 if (netif_msg_link(qdev))
1617                         printk(KERN_INFO PFX
1618                                "%s: Link is up at %d Mbps, %s duplex.\n",
1619                                qdev->ndev->name,
1620                                ql_get_link_speed(qdev),
1621                                ql_is_link_full_dup(qdev)
1622                                ? "full" : "half");
1623
1624         } else {        /* Remote error detected */
1625
1626                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1627                         if (netif_msg_link(qdev))
1628                                 printk(KERN_DEBUG PFX
1629                                        "%s: Remote error detected. "
1630                                        "Calling ql_port_start().\n",
1631                                        qdev->ndev->
1632                                        name);
1633                         /*
1634                          * ql_port_start() is shared code and needs
1635                          * to lock the PHY on it's own.
1636                          */
1637                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1638                         if(ql_port_start(qdev)) {/* Restart port */
1639                                 return -1;
1640                         } else
1641                                 return 0;
1642                 }
1643         }
1644         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1645         return 0;
1646 }
1647
1648 static void ql_link_state_machine_work(struct work_struct *work)
1649 {
1650         struct ql3_adapter *qdev =
1651                 container_of(work, struct ql3_adapter, link_state_work.work);
1652
1653         u32 curr_link_state;
1654         unsigned long hw_flags;
1655
1656         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1657
1658         curr_link_state = ql_get_link_state(qdev);
1659
1660         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1661                 if (netif_msg_link(qdev))
1662                         printk(KERN_INFO PFX
1663                                "%s: Reset in progress, skip processing link "
1664                                "state.\n", qdev->ndev->name);
1665
1666                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1667
1668                 /* Restart timer on 2 second interval. */
1669                 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);\
1670
1671                 return;
1672         }
1673
1674         switch (qdev->port_link_state) {
1675         default:
1676                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1677                         ql_port_start(qdev);
1678                 }
1679                 qdev->port_link_state = LS_DOWN;
1680                 /* Fall Through */
1681
1682         case LS_DOWN:
1683                 if (netif_msg_link(qdev))
1684                         printk(KERN_DEBUG PFX
1685                                "%s: port_link_state = LS_DOWN.\n",
1686                                qdev->ndev->name);
1687                 if (curr_link_state == LS_UP) {
1688                         if (netif_msg_link(qdev))
1689                                 printk(KERN_DEBUG PFX
1690                                        "%s: curr_link_state = LS_UP.\n",
1691                                        qdev->ndev->name);
1692                         if (ql_is_auto_neg_complete(qdev))
1693                                 ql_finish_auto_neg(qdev);
1694
1695                         if (qdev->port_link_state == LS_UP)
1696                                 ql_link_down_detect_clear(qdev);
1697
1698                 }
1699                 break;
1700
1701         case LS_UP:
1702                 /*
1703                  * See if the link is currently down or went down and came
1704                  * back up
1705                  */
1706                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1707                         if (netif_msg_link(qdev))
1708                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1709                                        qdev->ndev->name);
1710                         qdev->port_link_state = LS_DOWN;
1711                 }
1712                 break;
1713         }
1714         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1715
1716         /* Restart timer on 2 second interval. */
1717         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1718 }
1719
1720 /*
1721  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1722  */
1723 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1724 {
1725         if (ql_this_adapter_controls_port(qdev))
1726                 set_bit(QL_LINK_MASTER,&qdev->flags);
1727         else
1728                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1729 }
1730
1731 /*
1732  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1733  */
1734 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1735 {
1736         ql_mii_enable_scan_mode(qdev);
1737
1738         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1739                 if (ql_this_adapter_controls_port(qdev))
1740                         ql_petbi_init_ex(qdev);
1741         } else {
1742                 if (ql_this_adapter_controls_port(qdev))
1743                         ql_phy_init_ex(qdev);
1744         }
1745 }
1746
1747 /*
1748  * MII_Setup needs to be called before taking the PHY out of reset so that the
1749  * management interface clock speed can be set properly.  It would be better if
1750  * we had a way to disable MDC until after the PHY is out of reset, but we
1751  * don't have that capability.
1752  */
1753 static int ql_mii_setup(struct ql3_adapter *qdev)
1754 {
1755         u32 reg;
1756         struct ql3xxx_port_registers __iomem *port_regs =
1757                         qdev->mem_map_registers;
1758
1759         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1760                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1761                          2) << 7))
1762                 return -1;
1763
1764         if (qdev->device_id == QL3032_DEVICE_ID)
1765                 ql_write_page0_reg(qdev,
1766                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1767
1768         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1769         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1770
1771         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1772                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1773
1774         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1775         return 0;
1776 }
1777
1778 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1779 {
1780         u32 supported;
1781
1782         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1783                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1784                     | SUPPORTED_Autoneg;
1785         } else {
1786                 supported = SUPPORTED_10baseT_Half
1787                     | SUPPORTED_10baseT_Full
1788                     | SUPPORTED_100baseT_Half
1789                     | SUPPORTED_100baseT_Full
1790                     | SUPPORTED_1000baseT_Half
1791                     | SUPPORTED_1000baseT_Full
1792                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1793         }
1794
1795         return supported;
1796 }
1797
1798 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1799 {
1800         int status;
1801         unsigned long hw_flags;
1802         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1803         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1804                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1805                          2) << 7)) {
1806                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1807                 return 0;
1808         }
1809         status = ql_is_auto_cfg(qdev);
1810         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1811         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1812         return status;
1813 }
1814
1815 static u32 ql_get_speed(struct ql3_adapter *qdev)
1816 {
1817         u32 status;
1818         unsigned long hw_flags;
1819         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1820         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1821                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1822                          2) << 7)) {
1823                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1824                 return 0;
1825         }
1826         status = ql_get_link_speed(qdev);
1827         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1828         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1829         return status;
1830 }
1831
1832 static int ql_get_full_dup(struct ql3_adapter *qdev)
1833 {
1834         int status;
1835         unsigned long hw_flags;
1836         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1837         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1838                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1839                          2) << 7)) {
1840                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1841                 return 0;
1842         }
1843         status = ql_is_link_full_dup(qdev);
1844         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1845         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1846         return status;
1847 }
1848
1849
1850 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1851 {
1852         struct ql3_adapter *qdev = netdev_priv(ndev);
1853
1854         ecmd->transceiver = XCVR_INTERNAL;
1855         ecmd->supported = ql_supported_modes(qdev);
1856
1857         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1858                 ecmd->port = PORT_FIBRE;
1859         } else {
1860                 ecmd->port = PORT_TP;
1861                 ecmd->phy_address = qdev->PHYAddr;
1862         }
1863         ecmd->advertising = ql_supported_modes(qdev);
1864         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1865         ecmd->speed = ql_get_speed(qdev);
1866         ecmd->duplex = ql_get_full_dup(qdev);
1867         return 0;
1868 }
1869
1870 static void ql_get_drvinfo(struct net_device *ndev,
1871                            struct ethtool_drvinfo *drvinfo)
1872 {
1873         struct ql3_adapter *qdev = netdev_priv(ndev);
1874         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1875         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1876         strncpy(drvinfo->fw_version, "N/A", 32);
1877         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1878         drvinfo->regdump_len = 0;
1879         drvinfo->eedump_len = 0;
1880 }
1881
1882 static u32 ql_get_msglevel(struct net_device *ndev)
1883 {
1884         struct ql3_adapter *qdev = netdev_priv(ndev);
1885         return qdev->msg_enable;
1886 }
1887
1888 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1889 {
1890         struct ql3_adapter *qdev = netdev_priv(ndev);
1891         qdev->msg_enable = value;
1892 }
1893
1894 static void ql_get_pauseparam(struct net_device *ndev,
1895                               struct ethtool_pauseparam *pause)
1896 {
1897         struct ql3_adapter *qdev = netdev_priv(ndev);
1898         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1899
1900         u32 reg;
1901         if(qdev->mac_index == 0)
1902                 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1903         else
1904                 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1905
1906         pause->autoneg  = ql_get_auto_cfg_status(qdev);
1907         pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1908         pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1909 }
1910
1911 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1912         .get_settings = ql_get_settings,
1913         .get_drvinfo = ql_get_drvinfo,
1914         .get_link = ethtool_op_get_link,
1915         .get_msglevel = ql_get_msglevel,
1916         .set_msglevel = ql_set_msglevel,
1917         .get_pauseparam = ql_get_pauseparam,
1918 };
1919
1920 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1921 {
1922         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1923         dma_addr_t map;
1924         int err;
1925
1926         while (lrg_buf_cb) {
1927                 if (!lrg_buf_cb->skb) {
1928                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1929                                                            qdev->lrg_buffer_len);
1930                         if (unlikely(!lrg_buf_cb->skb)) {
1931                                 printk(KERN_DEBUG PFX
1932                                        "%s: Failed netdev_alloc_skb().\n",
1933                                        qdev->ndev->name);
1934                                 break;
1935                         } else {
1936                                 /*
1937                                  * We save some space to copy the ethhdr from
1938                                  * first buffer
1939                                  */
1940                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1941                                 map = pci_map_single(qdev->pdev,
1942                                                      lrg_buf_cb->skb->data,
1943                                                      qdev->lrg_buffer_len -
1944                                                      QL_HEADER_SPACE,
1945                                                      PCI_DMA_FROMDEVICE);
1946
1947                                 err = pci_dma_mapping_error(map);
1948                                 if(err) {
1949                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1950                                                qdev->ndev->name, err);
1951                                         dev_kfree_skb(lrg_buf_cb->skb);
1952                                         lrg_buf_cb->skb = NULL;
1953                                         break;
1954                                 }
1955
1956
1957                                 lrg_buf_cb->buf_phy_addr_low =
1958                                     cpu_to_le32(LS_64BITS(map));
1959                                 lrg_buf_cb->buf_phy_addr_high =
1960                                     cpu_to_le32(MS_64BITS(map));
1961                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1962                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1963                                                   qdev->lrg_buffer_len -
1964                                                   QL_HEADER_SPACE);
1965                                 --qdev->lrg_buf_skb_check;
1966                                 if (!qdev->lrg_buf_skb_check)
1967                                         return 1;
1968                         }
1969                 }
1970                 lrg_buf_cb = lrg_buf_cb->next;
1971         }
1972         return 0;
1973 }
1974
1975 /*
1976  * Caller holds hw_lock.
1977  */
1978 static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1979 {
1980         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1981         if (qdev->small_buf_release_cnt >= 16) {
1982                 while (qdev->small_buf_release_cnt >= 16) {
1983                         qdev->small_buf_q_producer_index++;
1984
1985                         if (qdev->small_buf_q_producer_index ==
1986                             NUM_SBUFQ_ENTRIES)
1987                                 qdev->small_buf_q_producer_index = 0;
1988                         qdev->small_buf_release_cnt -= 8;
1989                 }
1990                 wmb();
1991                 writel(qdev->small_buf_q_producer_index,
1992                         &port_regs->CommonRegs.rxSmallQProducerIndex);
1993         }
1994 }
1995
1996 /*
1997  * Caller holds hw_lock.
1998  */
1999 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
2000 {
2001         struct bufq_addr_element *lrg_buf_q_ele;
2002         int i;
2003         struct ql_rcv_buf_cb *lrg_buf_cb;
2004         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2005
2006         if ((qdev->lrg_buf_free_count >= 8)
2007             && (qdev->lrg_buf_release_cnt >= 16)) {
2008
2009                 if (qdev->lrg_buf_skb_check)
2010                         if (!ql_populate_free_queue(qdev))
2011                                 return;
2012
2013                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
2014
2015                 while ((qdev->lrg_buf_release_cnt >= 16)
2016                        && (qdev->lrg_buf_free_count >= 8)) {
2017
2018                         for (i = 0; i < 8; i++) {
2019                                 lrg_buf_cb =
2020                                     ql_get_from_lrg_buf_free_list(qdev);
2021                                 lrg_buf_q_ele->addr_high =
2022                                     lrg_buf_cb->buf_phy_addr_high;
2023                                 lrg_buf_q_ele->addr_low =
2024                                     lrg_buf_cb->buf_phy_addr_low;
2025                                 lrg_buf_q_ele++;
2026
2027                                 qdev->lrg_buf_release_cnt--;
2028                         }
2029
2030                         qdev->lrg_buf_q_producer_index++;
2031
2032                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
2033                                 qdev->lrg_buf_q_producer_index = 0;
2034
2035                         if (qdev->lrg_buf_q_producer_index ==
2036                             (qdev->num_lbufq_entries - 1)) {
2037                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2038                         }
2039                 }
2040                 wmb();
2041                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
2042                 writel(qdev->lrg_buf_q_producer_index,
2043                         &port_regs->CommonRegs.rxLargeQProducerIndex);
2044         }
2045 }
2046
2047 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2048                                    struct ob_mac_iocb_rsp *mac_rsp)
2049 {
2050         struct ql_tx_buf_cb *tx_cb;
2051         int i;
2052         int retval = 0;
2053
2054         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2055                 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2056         }
2057
2058         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
2059
2060         /*  Check the transmit response flags for any errors */
2061         if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2062                 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2063
2064                 qdev->ndev->stats.tx_errors++;
2065                 retval = -EIO;
2066                 goto frame_not_sent;
2067         }
2068
2069         if(tx_cb->seg_count == 0) {
2070                 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2071
2072                 qdev->ndev->stats.tx_errors++;
2073                 retval = -EIO;
2074                 goto invalid_seg_count;
2075         }
2076
2077         pci_unmap_single(qdev->pdev,
2078                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2079                          pci_unmap_len(&tx_cb->map[0], maplen),
2080                          PCI_DMA_TODEVICE);
2081         tx_cb->seg_count--;
2082         if (tx_cb->seg_count) {
2083                 for (i = 1; i < tx_cb->seg_count; i++) {
2084                         pci_unmap_page(qdev->pdev,
2085                                        pci_unmap_addr(&tx_cb->map[i],
2086                                                       mapaddr),
2087                                        pci_unmap_len(&tx_cb->map[i], maplen),
2088                                        PCI_DMA_TODEVICE);
2089                 }
2090         }
2091         qdev->ndev->stats.tx_packets++;
2092         qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
2093
2094 frame_not_sent:
2095         dev_kfree_skb_irq(tx_cb->skb);
2096         tx_cb->skb = NULL;
2097
2098 invalid_seg_count:
2099         atomic_inc(&qdev->tx_count);
2100 }
2101
2102 static void ql_get_sbuf(struct ql3_adapter *qdev)
2103 {
2104         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2105                 qdev->small_buf_index = 0;
2106         qdev->small_buf_release_cnt++;
2107 }
2108
2109 static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
2110 {
2111         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2112         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2113         qdev->lrg_buf_release_cnt++;
2114         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2115                 qdev->lrg_buf_index = 0;
2116         return(lrg_buf_cb);
2117 }
2118
2119 /*
2120  * The difference between 3022 and 3032 for inbound completions:
2121  * 3022 uses two buffers per completion.  The first buffer contains
2122  * (some) header info, the second the remainder of the headers plus
2123  * the data.  For this chip we reserve some space at the top of the
2124  * receive buffer so that the header info in buffer one can be
2125  * prepended to the buffer two.  Buffer two is the sent up while
2126  * buffer one is returned to the hardware to be reused.
2127  * 3032 receives all of it's data and headers in one buffer for a
2128  * simpler process.  3032 also supports checksum verification as
2129  * can be seen in ql_process_macip_rx_intr().
2130  */
2131 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2132                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2133 {
2134         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2135         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2136         struct sk_buff *skb;
2137         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2138
2139         /*
2140          * Get the inbound address list (small buffer).
2141          */
2142         ql_get_sbuf(qdev);
2143
2144         if (qdev->device_id == QL3022_DEVICE_ID)
2145                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2146
2147         /* start of second buffer */
2148         lrg_buf_cb2 = ql_get_lbuf(qdev);
2149         skb = lrg_buf_cb2->skb;
2150
2151         qdev->ndev->stats.rx_packets++;
2152         qdev->ndev->stats.rx_bytes += length;
2153
2154         skb_put(skb, length);
2155         pci_unmap_single(qdev->pdev,
2156                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2157                          pci_unmap_len(lrg_buf_cb2, maplen),
2158                          PCI_DMA_FROMDEVICE);
2159         prefetch(skb->data);
2160         skb->ip_summed = CHECKSUM_NONE;
2161         skb->protocol = eth_type_trans(skb, qdev->ndev);
2162
2163         netif_receive_skb(skb);
2164         qdev->ndev->last_rx = jiffies;
2165         lrg_buf_cb2->skb = NULL;
2166
2167         if (qdev->device_id == QL3022_DEVICE_ID)
2168                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2169         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2170 }
2171
2172 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2173                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2174 {
2175         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2176         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2177         struct sk_buff *skb1 = NULL, *skb2;
2178         struct net_device *ndev = qdev->ndev;
2179         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2180         u16 size = 0;
2181
2182         /*
2183          * Get the inbound address list (small buffer).
2184          */
2185
2186         ql_get_sbuf(qdev);
2187
2188         if (qdev->device_id == QL3022_DEVICE_ID) {
2189                 /* start of first buffer on 3022 */
2190                 lrg_buf_cb1 = ql_get_lbuf(qdev);
2191                 skb1 = lrg_buf_cb1->skb;
2192                 size = ETH_HLEN;
2193                 if (*((u16 *) skb1->data) != 0xFFFF)
2194                         size += VLAN_ETH_HLEN - ETH_HLEN;
2195         }
2196
2197         /* start of second buffer */
2198         lrg_buf_cb2 = ql_get_lbuf(qdev);
2199         skb2 = lrg_buf_cb2->skb;
2200
2201         skb_put(skb2, length);  /* Just the second buffer length here. */
2202         pci_unmap_single(qdev->pdev,
2203                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
2204                          pci_unmap_len(lrg_buf_cb2, maplen),
2205                          PCI_DMA_FROMDEVICE);
2206         prefetch(skb2->data);
2207
2208         skb2->ip_summed = CHECKSUM_NONE;
2209         if (qdev->device_id == QL3022_DEVICE_ID) {
2210                 /*
2211                  * Copy the ethhdr from first buffer to second. This
2212                  * is necessary for 3022 IP completions.
2213                  */
2214                 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2215                                                  skb_push(skb2, size), size);
2216         } else {
2217                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2218                 if (checksum &
2219                         (IB_IP_IOCB_RSP_3032_ICE |
2220                          IB_IP_IOCB_RSP_3032_CE)) {
2221                         printk(KERN_ERR
2222                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
2223                                __func__,
2224                                ((checksum &
2225                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2226                                 "UDP"),checksum);
2227                 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2228                                 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2229                                 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2230                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
2231                 }
2232         }
2233         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2234
2235         netif_receive_skb(skb2);
2236         ndev->stats.rx_packets++;
2237         ndev->stats.rx_bytes += length;
2238         ndev->last_rx = jiffies;
2239         lrg_buf_cb2->skb = NULL;
2240
2241         if (qdev->device_id == QL3022_DEVICE_ID)
2242                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2243         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2244 }
2245
2246 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2247                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
2248 {
2249         struct net_rsp_iocb *net_rsp;
2250         struct net_device *ndev = qdev->ndev;
2251         int work_done = 0;
2252
2253         /* While there are entries in the completion queue. */
2254         while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2255                 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2256
2257                 net_rsp = qdev->rsp_current;
2258                 rmb();
2259                 /*
2260                  * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2261                  * inbound completion is for a VLAN.
2262                  */
2263                 if (qdev->device_id == QL3032_DEVICE_ID)
2264                         net_rsp->opcode &= 0x7f;
2265                 switch (net_rsp->opcode) {
2266
2267                 case OPCODE_OB_MAC_IOCB_FN0:
2268                 case OPCODE_OB_MAC_IOCB_FN2:
2269                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2270                                                net_rsp);
2271                         (*tx_cleaned)++;
2272                         break;
2273
2274                 case OPCODE_IB_MAC_IOCB:
2275                 case OPCODE_IB_3032_MAC_IOCB:
2276                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2277                                                net_rsp);
2278                         (*rx_cleaned)++;
2279                         break;
2280
2281                 case OPCODE_IB_IP_IOCB:
2282                 case OPCODE_IB_3032_IP_IOCB:
2283                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2284                                                  net_rsp);
2285                         (*rx_cleaned)++;
2286                         break;
2287                 default:
2288                         {
2289                                 u32 *tmp = (u32 *) net_rsp;
2290                                 printk(KERN_ERR PFX
2291                                        "%s: Hit default case, not "
2292                                        "handled!\n"
2293                                        "        dropping the packet, opcode = "
2294                                        "%x.\n",
2295                                        ndev->name, net_rsp->opcode);
2296                                 printk(KERN_ERR PFX
2297                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2298                                        (unsigned long int)tmp[0],
2299                                        (unsigned long int)tmp[1],
2300                                        (unsigned long int)tmp[2],
2301                                        (unsigned long int)tmp[3]);
2302                         }
2303                 }
2304
2305                 qdev->rsp_consumer_index++;
2306
2307                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2308                         qdev->rsp_consumer_index = 0;
2309                         qdev->rsp_current = qdev->rsp_q_virt_addr;
2310                 } else {
2311                         qdev->rsp_current++;
2312                 }
2313
2314                 work_done = *tx_cleaned + *rx_cleaned;
2315         }
2316
2317         return work_done;
2318 }
2319
2320 static int ql_poll(struct napi_struct *napi, int budget)
2321 {
2322         struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2323         struct net_device *ndev = qdev->ndev;
2324         int rx_cleaned = 0, tx_cleaned = 0;
2325         unsigned long hw_flags;
2326         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2327
2328         if (!netif_carrier_ok(ndev))
2329                 goto quit_polling;
2330
2331         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2332
2333         if (tx_cleaned + rx_cleaned != budget ||
2334             !netif_running(ndev)) {
2335 quit_polling:
2336                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2337                 __netif_rx_complete(ndev, napi);
2338                 ql_update_small_bufq_prod_index(qdev);
2339                 ql_update_lrg_bufq_prod_index(qdev);
2340                 writel(qdev->rsp_consumer_index,
2341                             &port_regs->CommonRegs.rspQConsumerIndex);
2342                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2343
2344                 ql_enable_interrupts(qdev);
2345         }
2346         return tx_cleaned + rx_cleaned;
2347 }
2348
2349 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2350 {
2351
2352         struct net_device *ndev = dev_id;
2353         struct ql3_adapter *qdev = netdev_priv(ndev);
2354         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2355         u32 value;
2356         int handled = 1;
2357         u32 var;
2358
2359         port_regs = qdev->mem_map_registers;
2360
2361         value =
2362             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2363
2364         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2365                 spin_lock(&qdev->adapter_lock);
2366                 netif_stop_queue(qdev->ndev);
2367                 netif_carrier_off(qdev->ndev);
2368                 ql_disable_interrupts(qdev);
2369                 qdev->port_link_state = LS_DOWN;
2370                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2371
2372                 if (value & ISP_CONTROL_FE) {
2373                         /*
2374                          * Chip Fatal Error.
2375                          */
2376                         var =
2377                             ql_read_page0_reg_l(qdev,
2378                                               &port_regs->PortFatalErrStatus);
2379                         printk(KERN_WARNING PFX
2380                                "%s: Resetting chip. PortFatalErrStatus "
2381                                "register = 0x%x\n", ndev->name, var);
2382                         set_bit(QL_RESET_START,&qdev->flags) ;
2383                 } else {
2384                         /*
2385                          * Soft Reset Requested.
2386                          */
2387                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2388                         printk(KERN_ERR PFX
2389                                "%s: Another function issued a reset to the "
2390                                "chip. ISR value = %x.\n", ndev->name, value);
2391                 }
2392                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2393                 spin_unlock(&qdev->adapter_lock);
2394         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2395                 ql_disable_interrupts(qdev);
2396                 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2397                         __netif_rx_schedule(ndev, &qdev->napi);
2398                 }
2399         } else {
2400                 return IRQ_NONE;
2401         }
2402
2403         return IRQ_RETVAL(handled);
2404 }
2405
2406 /*
2407  * Get the total number of segments needed for the
2408  * given number of fragments.  This is necessary because
2409  * outbound address lists (OAL) will be used when more than
2410  * two frags are given.  Each address list has 5 addr/len
2411  * pairs.  The 5th pair in each AOL is used to  point to
2412  * the next AOL if more frags are coming.
2413  * That is why the frags:segment count  ratio is not linear.
2414  */
2415 static int ql_get_seg_count(struct ql3_adapter *qdev,
2416                             unsigned short frags)
2417 {
2418         if (qdev->device_id == QL3022_DEVICE_ID)
2419                 return 1;
2420
2421         switch(frags) {
2422         case 0: return 1;       /* just the skb->data seg */
2423         case 1: return 2;       /* skb->data + 1 frag */
2424         case 2: return 3;       /* skb->data + 2 frags */
2425         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2426         case 4: return 6;
2427         case 5: return 7;
2428         case 6: return 8;
2429         case 7: return 10;
2430         case 8: return 11;
2431         case 9: return 12;
2432         case 10: return 13;
2433         case 11: return 15;
2434         case 12: return 16;
2435         case 13: return 17;
2436         case 14: return 18;
2437         case 15: return 20;
2438         case 16: return 21;
2439         case 17: return 22;
2440         case 18: return 23;
2441         }
2442         return -1;
2443 }
2444
2445 static void ql_hw_csum_setup(const struct sk_buff *skb,
2446                              struct ob_mac_iocb_req *mac_iocb_ptr)
2447 {
2448         const struct iphdr *ip = ip_hdr(skb);
2449
2450         mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2451         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2452
2453         if (ip->protocol == IPPROTO_TCP) {
2454                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2455                         OB_3032MAC_IOCB_REQ_IC;
2456         } else {
2457                 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2458                         OB_3032MAC_IOCB_REQ_IC;
2459         }
2460
2461 }
2462
2463 /*
2464  * Map the buffers for this transmit.  This will return
2465  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2466  */
2467 static int ql_send_map(struct ql3_adapter *qdev,
2468                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2469                                 struct ql_tx_buf_cb *tx_cb,
2470                                 struct sk_buff *skb)
2471 {
2472         struct oal *oal;
2473         struct oal_entry *oal_entry;
2474         int len = skb_headlen(skb);
2475         dma_addr_t map;
2476         int err;
2477         int completed_segs, i;
2478         int seg_cnt, seg = 0;
2479         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2480
2481         seg_cnt = tx_cb->seg_count;
2482         /*
2483          * Map the skb buffer first.
2484          */
2485         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2486
2487         err = pci_dma_mapping_error(map);
2488         if(err) {
2489                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2490                        qdev->ndev->name, err);
2491
2492                 return NETDEV_TX_BUSY;
2493         }
2494
2495         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2496         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2497         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2498         oal_entry->len = cpu_to_le32(len);
2499         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2500         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2501         seg++;
2502
2503         if (seg_cnt == 1) {
2504                 /* Terminate the last segment. */
2505                 oal_entry->len =
2506                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2507         } else {
2508                 oal = tx_cb->oal;
2509                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2510                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2511                         oal_entry++;
2512                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2513                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2514                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2515                             (seg == 17 && seg_cnt > 18)) {
2516                                 /* Continuation entry points to outbound address list. */
2517                                 map = pci_map_single(qdev->pdev, oal,
2518                                                      sizeof(struct oal),
2519                                                      PCI_DMA_TODEVICE);
2520
2521                                 err = pci_dma_mapping_error(map);
2522                                 if(err) {
2523
2524                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2525                                                qdev->ndev->name, err);
2526                                         goto map_error;
2527                                 }
2528
2529                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2530                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2531                                 oal_entry->len =
2532                                     cpu_to_le32(sizeof(struct oal) |
2533                                                 OAL_CONT_ENTRY);
2534                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2535                                                    map);
2536                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2537                                                   sizeof(struct oal));
2538                                 oal_entry = (struct oal_entry *)oal;
2539                                 oal++;
2540                                 seg++;
2541                         }
2542
2543                         map =
2544                             pci_map_page(qdev->pdev, frag->page,
2545                                          frag->page_offset, frag->size,
2546                                          PCI_DMA_TODEVICE);
2547
2548                         err = pci_dma_mapping_error(map);
2549                         if(err) {
2550                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2551                                        qdev->ndev->name, err);
2552                                 goto map_error;
2553                         }
2554
2555                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2556                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2557                         oal_entry->len = cpu_to_le32(frag->size);
2558                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2559                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2560                                           frag->size);
2561                 }
2562                 /* Terminate the last segment. */
2563                 oal_entry->len =
2564                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2565         }
2566
2567         return NETDEV_TX_OK;
2568
2569 map_error:
2570         /* A PCI mapping failed and now we will need to back out
2571          * We need to traverse through the oal's and associated pages which
2572          * have been mapped and now we must unmap them to clean up properly
2573          */
2574
2575         seg = 1;
2576         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2577         oal = tx_cb->oal;
2578         for (i=0; i<completed_segs; i++,seg++) {
2579                 oal_entry++;
2580
2581                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2582                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2583                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2584                    (seg == 17 && seg_cnt > 18)) {
2585                         pci_unmap_single(qdev->pdev,
2586                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2587                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2588                                  PCI_DMA_TODEVICE);
2589                         oal++;
2590                         seg++;
2591                 }
2592
2593                 pci_unmap_page(qdev->pdev,
2594                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2595                                pci_unmap_len(&tx_cb->map[seg], maplen),
2596                                PCI_DMA_TODEVICE);
2597         }
2598
2599         pci_unmap_single(qdev->pdev,
2600                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2601                          pci_unmap_addr(&tx_cb->map[0], maplen),
2602                          PCI_DMA_TODEVICE);
2603
2604         return NETDEV_TX_BUSY;
2605
2606 }
2607
2608 /*
2609  * The difference between 3022 and 3032 sends:
2610  * 3022 only supports a simple single segment transmission.
2611  * 3032 supports checksumming and scatter/gather lists (fragments).
2612  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2613  * in the IOCB plus a chain of outbound address lists (OAL) that
2614  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2615  * will used to point to an OAL when more ALP entries are required.
2616  * The IOCB is always the top of the chain followed by one or more
2617  * OALs (when necessary).
2618  */
2619 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2620 {
2621         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2622         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2623         struct ql_tx_buf_cb *tx_cb;
2624         u32 tot_len = skb->len;
2625         struct ob_mac_iocb_req *mac_iocb_ptr;
2626
2627         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2628                 return NETDEV_TX_BUSY;
2629         }
2630
2631         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2632         if((tx_cb->seg_count = ql_get_seg_count(qdev,
2633                                                 (skb_shinfo(skb)->nr_frags))) == -1) {
2634                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2635                 return NETDEV_TX_OK;
2636         }
2637
2638         mac_iocb_ptr = tx_cb->queue_entry;
2639         memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2640         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2641         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2642         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2643         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2644         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2645         tx_cb->skb = skb;
2646         if (qdev->device_id == QL3032_DEVICE_ID &&
2647             skb->ip_summed == CHECKSUM_PARTIAL)
2648                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2649
2650         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2651                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2652                 return NETDEV_TX_BUSY;
2653         }
2654
2655         wmb();
2656         qdev->req_producer_index++;
2657         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2658                 qdev->req_producer_index = 0;
2659         wmb();
2660         ql_write_common_reg_l(qdev,
2661                             &port_regs->CommonRegs.reqQProducerIndex,
2662                             qdev->req_producer_index);
2663
2664         ndev->trans_start = jiffies;
2665         if (netif_msg_tx_queued(qdev))
2666                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2667                        ndev->name, qdev->req_producer_index, skb->len);
2668
2669         atomic_dec(&qdev->tx_count);
2670         return NETDEV_TX_OK;
2671 }
2672
2673 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2674 {
2675         qdev->req_q_size =
2676             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2677
2678         qdev->req_q_virt_addr =
2679             pci_alloc_consistent(qdev->pdev,
2680                                  (size_t) qdev->req_q_size,
2681                                  &qdev->req_q_phy_addr);
2682
2683         if ((qdev->req_q_virt_addr == NULL) ||
2684             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2685                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2686                        qdev->ndev->name);
2687                 return -ENOMEM;
2688         }
2689
2690         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2691
2692         qdev->rsp_q_virt_addr =
2693             pci_alloc_consistent(qdev->pdev,
2694                                  (size_t) qdev->rsp_q_size,
2695                                  &qdev->rsp_q_phy_addr);
2696
2697         if ((qdev->rsp_q_virt_addr == NULL) ||
2698             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2699                 printk(KERN_ERR PFX
2700                        "%s: rspQ allocation failed\n",
2701                        qdev->ndev->name);
2702                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2703                                     qdev->req_q_virt_addr,
2704                                     qdev->req_q_phy_addr);
2705                 return -ENOMEM;
2706         }
2707
2708         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2709
2710         return 0;
2711 }
2712
2713 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2714 {
2715         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2716                 printk(KERN_INFO PFX
2717                        "%s: Already done.\n", qdev->ndev->name);
2718                 return;
2719         }
2720
2721         pci_free_consistent(qdev->pdev,
2722                             qdev->req_q_size,
2723                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2724
2725         qdev->req_q_virt_addr = NULL;
2726
2727         pci_free_consistent(qdev->pdev,
2728                             qdev->rsp_q_size,
2729                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2730
2731         qdev->rsp_q_virt_addr = NULL;
2732
2733         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2734 }
2735
2736 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2737 {
2738         /* Create Large Buffer Queue */
2739         qdev->lrg_buf_q_size =
2740             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2741         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2742                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2743         else
2744                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2745
2746         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2747         if (qdev->lrg_buf == NULL) {
2748                 printk(KERN_ERR PFX
2749                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2750                 return -ENOMEM;
2751         }
2752
2753         qdev->lrg_buf_q_alloc_virt_addr =
2754             pci_alloc_consistent(qdev->pdev,
2755                                  qdev->lrg_buf_q_alloc_size,
2756                                  &qdev->lrg_buf_q_alloc_phy_addr);
2757
2758         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2759                 printk(KERN_ERR PFX
2760                        "%s: lBufQ failed\n", qdev->ndev->name);
2761                 return -ENOMEM;
2762         }
2763         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2764         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2765
2766         /* Create Small Buffer Queue */
2767         qdev->small_buf_q_size =
2768             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2769         if (qdev->small_buf_q_size < PAGE_SIZE)
2770                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2771         else
2772                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2773
2774         qdev->small_buf_q_alloc_virt_addr =
2775             pci_alloc_consistent(qdev->pdev,
2776                                  qdev->small_buf_q_alloc_size,
2777                                  &qdev->small_buf_q_alloc_phy_addr);
2778
2779         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2780                 printk(KERN_ERR PFX
2781                        "%s: Small Buffer Queue allocation failed.\n",
2782                        qdev->ndev->name);
2783                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2784                                     qdev->lrg_buf_q_alloc_virt_addr,
2785                                     qdev->lrg_buf_q_alloc_phy_addr);
2786                 return -ENOMEM;
2787         }
2788
2789         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2790         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2791         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2792         return 0;
2793 }
2794
2795 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2796 {
2797         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2798                 printk(KERN_INFO PFX
2799                        "%s: Already done.\n", qdev->ndev->name);
2800                 return;
2801         }
2802         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2803         pci_free_consistent(qdev->pdev,
2804                             qdev->lrg_buf_q_alloc_size,
2805                             qdev->lrg_buf_q_alloc_virt_addr,
2806                             qdev->lrg_buf_q_alloc_phy_addr);
2807
2808         qdev->lrg_buf_q_virt_addr = NULL;
2809
2810         pci_free_consistent(qdev->pdev,
2811                             qdev->small_buf_q_alloc_size,
2812                             qdev->small_buf_q_alloc_virt_addr,
2813                             qdev->small_buf_q_alloc_phy_addr);
2814
2815         qdev->small_buf_q_virt_addr = NULL;
2816
2817         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2818 }
2819
2820 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2821 {
2822         int i;
2823         struct bufq_addr_element *small_buf_q_entry;
2824
2825         /* Currently we allocate on one of memory and use it for smallbuffers */
2826         qdev->small_buf_total_size =
2827             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2828              QL_SMALL_BUFFER_SIZE);
2829
2830         qdev->small_buf_virt_addr =
2831             pci_alloc_consistent(qdev->pdev,
2832                                  qdev->small_buf_total_size,
2833                                  &qdev->small_buf_phy_addr);
2834
2835         if (qdev->small_buf_virt_addr == NULL) {
2836                 printk(KERN_ERR PFX
2837                        "%s: Failed to get small buffer memory.\n",
2838                        qdev->ndev->name);
2839                 return -ENOMEM;
2840         }
2841
2842         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2843         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2844
2845         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2846
2847         /* Initialize the small buffer queue. */
2848         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2849                 small_buf_q_entry->addr_high =
2850                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2851                 small_buf_q_entry->addr_low =
2852                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2853                                 (i * QL_SMALL_BUFFER_SIZE));
2854                 small_buf_q_entry++;
2855         }
2856         qdev->small_buf_index = 0;
2857         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2858         return 0;
2859 }
2860
2861 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2862 {
2863         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2864                 printk(KERN_INFO PFX
2865                        "%s: Already done.\n", qdev->ndev->name);
2866                 return;
2867         }
2868         if (qdev->small_buf_virt_addr != NULL) {
2869                 pci_free_consistent(qdev->pdev,
2870                                     qdev->small_buf_total_size,
2871                                     qdev->small_buf_virt_addr,
2872                                     qdev->small_buf_phy_addr);
2873
2874                 qdev->small_buf_virt_addr = NULL;
2875         }
2876 }
2877
2878 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2879 {
2880         int i = 0;
2881         struct ql_rcv_buf_cb *lrg_buf_cb;
2882
2883         for (i = 0; i < qdev->num_large_buffers; i++) {
2884                 lrg_buf_cb = &qdev->lrg_buf[i];
2885                 if (lrg_buf_cb->skb) {
2886                         dev_kfree_skb(lrg_buf_cb->skb);
2887                         pci_unmap_single(qdev->pdev,
2888                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2889                                          pci_unmap_len(lrg_buf_cb, maplen),
2890                                          PCI_DMA_FROMDEVICE);
2891                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2892                 } else {
2893                         break;
2894                 }
2895         }
2896 }
2897
2898 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2899 {
2900         int i;
2901         struct ql_rcv_buf_cb *lrg_buf_cb;
2902         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2903
2904         for (i = 0; i < qdev->num_large_buffers; i++) {
2905                 lrg_buf_cb = &qdev->lrg_buf[i];
2906                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2907                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2908                 buf_addr_ele++;
2909         }
2910         qdev->lrg_buf_index = 0;
2911         qdev->lrg_buf_skb_check = 0;
2912 }
2913
2914 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2915 {
2916         int i;
2917         struct ql_rcv_buf_cb *lrg_buf_cb;
2918         struct sk_buff *skb;
2919         dma_addr_t map;
2920         int err;
2921
2922         for (i = 0; i < qdev->num_large_buffers; i++) {
2923                 skb = netdev_alloc_skb(qdev->ndev,
2924                                        qdev->lrg_buffer_len);
2925                 if (unlikely(!skb)) {
2926                         /* Better luck next round */
2927                         printk(KERN_ERR PFX
2928                                "%s: large buff alloc failed, "
2929                                "for %d bytes at index %d.\n",
2930                                qdev->ndev->name,
2931                                qdev->lrg_buffer_len * 2, i);
2932                         ql_free_large_buffers(qdev);
2933                         return -ENOMEM;
2934                 } else {
2935
2936                         lrg_buf_cb = &qdev->lrg_buf[i];
2937                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2938                         lrg_buf_cb->index = i;
2939                         lrg_buf_cb->skb = skb;
2940                         /*
2941                          * We save some space to copy the ethhdr from first
2942                          * buffer
2943                          */
2944                         skb_reserve(skb, QL_HEADER_SPACE);
2945                         map = pci_map_single(qdev->pdev,
2946                                              skb->data,
2947                                              qdev->lrg_buffer_len -
2948                                              QL_HEADER_SPACE,
2949                                              PCI_DMA_FROMDEVICE);
2950
2951                         err = pci_dma_mapping_error(map);
2952                         if(err) {
2953                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2954                                        qdev->ndev->name, err);
2955                                 ql_free_large_buffers(qdev);
2956                                 return -ENOMEM;
2957                         }
2958
2959                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2960                         pci_unmap_len_set(lrg_buf_cb, maplen,
2961                                           qdev->lrg_buffer_len -
2962                                           QL_HEADER_SPACE);
2963                         lrg_buf_cb->buf_phy_addr_low =
2964                             cpu_to_le32(LS_64BITS(map));
2965                         lrg_buf_cb->buf_phy_addr_high =
2966                             cpu_to_le32(MS_64BITS(map));
2967                 }
2968         }
2969         return 0;
2970 }
2971
2972 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2973 {
2974         struct ql_tx_buf_cb *tx_cb;
2975         int i;
2976
2977         tx_cb = &qdev->tx_buf[0];
2978         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2979                 if (tx_cb->oal) {
2980                         kfree(tx_cb->oal);
2981                         tx_cb->oal = NULL;
2982                 }
2983                 tx_cb++;
2984         }
2985 }
2986
2987 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2988 {
2989         struct ql_tx_buf_cb *tx_cb;
2990         int i;
2991         struct ob_mac_iocb_req *req_q_curr =
2992                                         qdev->req_q_virt_addr;
2993
2994         /* Create free list of transmit buffers */
2995         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2996
2997                 tx_cb = &qdev->tx_buf[i];
2998                 tx_cb->skb = NULL;
2999                 tx_cb->queue_entry = req_q_curr;
3000                 req_q_curr++;
3001                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
3002                 if (tx_cb->oal == NULL)
3003                         return -1;
3004         }
3005         return 0;
3006 }
3007
3008 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
3009 {
3010         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
3011                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
3012                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
3013         }
3014         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
3015                 /*
3016                  * Bigger buffers, so less of them.
3017                  */
3018                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
3019                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
3020         } else {
3021                 printk(KERN_ERR PFX
3022                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
3023                        qdev->ndev->name);
3024                 return -ENOMEM;
3025         }
3026         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
3027         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
3028         qdev->max_frame_size =
3029             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
3030
3031         /*
3032          * First allocate a page of shared memory and use it for shadow
3033          * locations of Network Request Queue Consumer Address Register and
3034          * Network Completion Queue Producer Index Register
3035          */
3036         qdev->shadow_reg_virt_addr =
3037             pci_alloc_consistent(qdev->pdev,
3038                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3039
3040         if (qdev->shadow_reg_virt_addr != NULL) {
3041                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3042                 qdev->req_consumer_index_phy_addr_high =
3043                     MS_64BITS(qdev->shadow_reg_phy_addr);
3044                 qdev->req_consumer_index_phy_addr_low =
3045                     LS_64BITS(qdev->shadow_reg_phy_addr);
3046
3047                 qdev->prsp_producer_index =
3048                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
3049                 qdev->rsp_producer_index_phy_addr_high =
3050                     qdev->req_consumer_index_phy_addr_high;
3051                 qdev->rsp_producer_index_phy_addr_low =
3052                     qdev->req_consumer_index_phy_addr_low + 8;
3053         } else {
3054                 printk(KERN_ERR PFX
3055                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3056                 return -ENOMEM;
3057         }
3058
3059         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3060                 printk(KERN_ERR PFX
3061                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
3062                        qdev->ndev->name);
3063                 goto err_req_rsp;
3064         }
3065
3066         if (ql_alloc_buffer_queues(qdev) != 0) {
3067                 printk(KERN_ERR PFX
3068                        "%s: ql_alloc_buffer_queues failed.\n",
3069                        qdev->ndev->name);
3070                 goto err_buffer_queues;
3071         }
3072
3073         if (ql_alloc_small_buffers(qdev) != 0) {
3074                 printk(KERN_ERR PFX
3075                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3076                 goto err_small_buffers;
3077         }
3078
3079         if (ql_alloc_large_buffers(qdev) != 0) {
3080                 printk(KERN_ERR PFX
3081                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3082                 goto err_small_buffers;
3083         }
3084
3085         /* Initialize the large buffer queue. */
3086         ql_init_large_buffers(qdev);
3087         if (ql_create_send_free_list(qdev))
3088                 goto err_free_list;
3089
3090         qdev->rsp_current = qdev->rsp_q_virt_addr;
3091
3092         return 0;
3093 err_free_list:
3094         ql_free_send_free_list(qdev);
3095 err_small_buffers:
3096         ql_free_buffer_queues(qdev);
3097 err_buffer_queues:
3098         ql_free_net_req_rsp_queues(qdev);
3099 err_req_rsp:
3100         pci_free_consistent(qdev->pdev,
3101                             PAGE_SIZE,
3102                             qdev->shadow_reg_virt_addr,
3103                             qdev->shadow_reg_phy_addr);
3104
3105         return -ENOMEM;
3106 }
3107
3108 static void ql_free_mem_resources(struct ql3_adapter *qdev)
3109 {
3110         ql_free_send_free_list(qdev);
3111         ql_free_large_buffers(qdev);
3112         ql_free_small_buffers(qdev);
3113         ql_free_buffer_queues(qdev);
3114         ql_free_net_req_rsp_queues(qdev);
3115         if (qdev->shadow_reg_virt_addr != NULL) {
3116                 pci_free_consistent(qdev->pdev,
3117                                     PAGE_SIZE,
3118                                     qdev->shadow_reg_virt_addr,
3119                                     qdev->shadow_reg_phy_addr);
3120                 qdev->shadow_reg_virt_addr = NULL;
3121         }
3122 }
3123
3124 static int ql_init_misc_registers(struct ql3_adapter *qdev)
3125 {
3126         struct ql3xxx_local_ram_registers __iomem *local_ram =
3127             (void __iomem *)qdev->mem_map_registers;
3128
3129         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3130                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3131                          2) << 4))
3132                 return -1;
3133
3134         ql_write_page2_reg(qdev,
3135                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3136
3137         ql_write_page2_reg(qdev,
3138                            &local_ram->maxBufletCount,
3139                            qdev->nvram_data.bufletCount);
3140
3141         ql_write_page2_reg(qdev,
3142                            &local_ram->freeBufletThresholdLow,
3143                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3144                            (qdev->nvram_data.tcpWindowThreshold0));
3145
3146         ql_write_page2_reg(qdev,
3147                            &local_ram->freeBufletThresholdHigh,
3148                            qdev->nvram_data.tcpWindowThreshold50);
3149
3150         ql_write_page2_reg(qdev,
3151                            &local_ram->ipHashTableBase,
3152                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
3153                            qdev->nvram_data.ipHashTableBaseLo);
3154         ql_write_page2_reg(qdev,
3155                            &local_ram->ipHashTableCount,
3156                            qdev->nvram_data.ipHashTableSize);
3157         ql_write_page2_reg(qdev,
3158                            &local_ram->tcpHashTableBase,
3159                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3160                            qdev->nvram_data.tcpHashTableBaseLo);
3161         ql_write_page2_reg(qdev,
3162                            &local_ram->tcpHashTableCount,
3163                            qdev->nvram_data.tcpHashTableSize);
3164         ql_write_page2_reg(qdev,
3165                            &local_ram->ncbBase,
3166                            (qdev->nvram_data.ncbTableBaseHi << 16) |
3167                            qdev->nvram_data.ncbTableBaseLo);
3168         ql_write_page2_reg(qdev,
3169                            &local_ram->maxNcbCount,
3170                            qdev->nvram_data.ncbTableSize);
3171         ql_write_page2_reg(qdev,
3172                            &local_ram->drbBase,
3173                            (qdev->nvram_data.drbTableBaseHi << 16) |
3174                            qdev->nvram_data.drbTableBaseLo);
3175         ql_write_page2_reg(qdev,
3176                            &local_ram->maxDrbCount,
3177                            qdev->nvram_data.drbTableSize);
3178         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3179         return 0;
3180 }
3181
3182 static int ql_adapter_initialize(struct ql3_adapter *qdev)
3183 {
3184         u32 value;
3185         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3186         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3187                                                 (void __iomem *)port_regs;
3188         u32 delay = 10;
3189         int status = 0;
3190
3191         if(ql_mii_setup(qdev))
3192                 return -1;
3193
3194         /* Bring out PHY out of reset */
3195         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3196                             (ISP_SERIAL_PORT_IF_WE |
3197                              (ISP_SERIAL_PORT_IF_WE << 16)));
3198
3199         qdev->port_link_state = LS_DOWN;
3200         netif_carrier_off(qdev->ndev);
3201
3202         /* V2 chip fix for ARS-39168. */
3203         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3204                             (ISP_SERIAL_PORT_IF_SDE |
3205                              (ISP_SERIAL_PORT_IF_SDE << 16)));
3206
3207         /* Request Queue Registers */
3208         *((u32 *) (qdev->preq_consumer_index)) = 0;
3209         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3210         qdev->req_producer_index = 0;
3211
3212         ql_write_page1_reg(qdev,
3213                            &hmem_regs->reqConsumerIndexAddrHigh,
3214                            qdev->req_consumer_index_phy_addr_high);
3215         ql_write_page1_reg(qdev,
3216                            &hmem_regs->reqConsumerIndexAddrLow,
3217                            qdev->req_consumer_index_phy_addr_low);
3218
3219         ql_write_page1_reg(qdev,
3220                            &hmem_regs->reqBaseAddrHigh,
3221                            MS_64BITS(qdev->req_q_phy_addr));
3222         ql_write_page1_reg(qdev,
3223                            &hmem_regs->reqBaseAddrLow,
3224                            LS_64BITS(qdev->req_q_phy_addr));
3225         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3226
3227         /* Response Queue Registers */
3228         *((u16 *) (qdev->prsp_producer_index)) = 0;
3229         qdev->rsp_consumer_index = 0;
3230         qdev->rsp_current = qdev->rsp_q_virt_addr;
3231
3232         ql_write_page1_reg(qdev,
3233                            &hmem_regs->rspProducerIndexAddrHigh,
3234                            qdev->rsp_producer_index_phy_addr_high);
3235
3236         ql_write_page1_reg(qdev,
3237                            &hmem_regs->rspProducerIndexAddrLow,
3238                            qdev->rsp_producer_index_phy_addr_low);
3239
3240         ql_write_page1_reg(qdev,
3241                            &hmem_regs->rspBaseAddrHigh,
3242                            MS_64BITS(qdev->rsp_q_phy_addr));
3243
3244         ql_write_page1_reg(qdev,
3245                            &hmem_regs->rspBaseAddrLow,
3246                            LS_64BITS(qdev->rsp_q_phy_addr));
3247
3248         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3249
3250         /* Large Buffer Queue */
3251         ql_write_page1_reg(qdev,
3252                            &hmem_regs->rxLargeQBaseAddrHigh,
3253                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
3254
3255         ql_write_page1_reg(qdev,
3256                            &hmem_regs->rxLargeQBaseAddrLow,
3257                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
3258
3259         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
3260
3261         ql_write_page1_reg(qdev,
3262                            &hmem_regs->rxLargeBufferLength,
3263                            qdev->lrg_buffer_len);
3264
3265         /* Small Buffer Queue */
3266         ql_write_page1_reg(qdev,
3267                            &hmem_regs->rxSmallQBaseAddrHigh,
3268                            MS_64BITS(qdev->small_buf_q_phy_addr));
3269
3270         ql_write_page1_reg(qdev,
3271                            &hmem_regs->rxSmallQBaseAddrLow,
3272                            LS_64BITS(qdev->small_buf_q_phy_addr));
3273
3274         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3275         ql_write_page1_reg(qdev,
3276                            &hmem_regs->rxSmallBufferLength,
3277                            QL_SMALL_BUFFER_SIZE);
3278
3279         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3280         qdev->small_buf_release_cnt = 8;
3281         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3282         qdev->lrg_buf_release_cnt = 8;
3283         qdev->lrg_buf_next_free =
3284             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3285         qdev->small_buf_index = 0;
3286         qdev->lrg_buf_index = 0;
3287         qdev->lrg_buf_free_count = 0;
3288         qdev->lrg_buf_free_head = NULL;
3289         qdev->lrg_buf_free_tail = NULL;
3290
3291         ql_write_common_reg(qdev,
3292                             &port_regs->CommonRegs.
3293                             rxSmallQProducerIndex,
3294                             qdev->small_buf_q_producer_index);
3295         ql_write_common_reg(qdev,
3296                             &port_regs->CommonRegs.
3297                             rxLargeQProducerIndex,
3298                             qdev->lrg_buf_q_producer_index);
3299
3300         /*
3301          * Find out if the chip has already been initialized.  If it has, then
3302          * we skip some of the initialization.
3303          */
3304         clear_bit(QL_LINK_MASTER, &qdev->flags);
3305         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3306         if ((value & PORT_STATUS_IC) == 0) {
3307
3308                 /* Chip has not been configured yet, so let it rip. */
3309                 if(ql_init_misc_registers(qdev)) {
3310                         status = -1;
3311                         goto out;
3312                 }
3313
3314                 value = qdev->nvram_data.tcpMaxWindowSize;
3315                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3316
3317                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3318
3319                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3320                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3321                                  * 2) << 13)) {
3322                         status = -1;
3323                         goto out;
3324                 }
3325                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3326                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3327                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3328                                      16) | (INTERNAL_CHIP_SD |
3329                                             INTERNAL_CHIP_WE)));
3330                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3331         }
3332
3333         if (qdev->mac_index)
3334                 ql_write_page0_reg(qdev,
3335                                    &port_regs->mac1MaxFrameLengthReg,
3336                                    qdev->max_frame_size);
3337         else
3338                 ql_write_page0_reg(qdev,
3339                                            &port_regs->mac0MaxFrameLengthReg,
3340                                            qdev->max_frame_size);
3341
3342         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3343                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3344                          2) << 7)) {
3345                 status = -1;
3346                 goto out;
3347         }
3348
3349         PHY_Setup(qdev);
3350         ql_init_scan_mode(qdev);
3351         ql_get_phy_owner(qdev);
3352
3353         /* Load the MAC Configuration */
3354
3355         /* Program lower 32 bits of the MAC address */
3356         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3357                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3358         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3359                            ((qdev->ndev->dev_addr[2] << 24)
3360                             | (qdev->ndev->dev_addr[3] << 16)
3361                             | (qdev->ndev->dev_addr[4] << 8)
3362                             | qdev->ndev->dev_addr[5]));
3363
3364         /* Program top 16 bits of the MAC address */
3365         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3366                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3367         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3368                            ((qdev->ndev->dev_addr[0] << 8)
3369                             | qdev->ndev->dev_addr[1]));
3370
3371         /* Enable Primary MAC */
3372         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3373                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3374                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3375
3376         /* Clear Primary and Secondary IP addresses */
3377         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3378                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3379                             (qdev->mac_index << 2)));
3380         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3381
3382         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3383                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3384                             ((qdev->mac_index << 2) + 1)));
3385         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3386
3387         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3388
3389         /* Indicate Configuration Complete */
3390         ql_write_page0_reg(qdev,
3391                            &port_regs->portControl,
3392                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3393
3394         do {
3395                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3396                 if (value & PORT_STATUS_IC)
3397                         break;
3398                 msleep(500);
3399         } while (--delay);
3400
3401         if (delay == 0) {
3402                 printk(KERN_ERR PFX
3403                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3404                 status = -1;
3405                 goto out;
3406         }
3407
3408         /* Enable Ethernet Function */
3409         if (qdev->device_id == QL3032_DEVICE_ID) {
3410                 value =
3411                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3412                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3413                         QL3032_PORT_CONTROL_ET);
3414                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3415                                    ((value << 16) | value));
3416         } else {
3417                 value =
3418                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3419                      PORT_CONTROL_HH);
3420                 ql_write_page0_reg(qdev, &port_regs->portControl,
3421                                    ((value << 16) | value));
3422         }
3423
3424
3425 out:
3426         return status;
3427 }
3428
3429 /*
3430  * Caller holds hw_lock.
3431  */
3432 static int ql_adapter_reset(struct ql3_adapter *qdev)
3433 {
3434         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3435         int status = 0;
3436         u16 value;
3437         int max_wait_time;
3438
3439         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3440         clear_bit(QL_RESET_DONE, &qdev->flags);
3441
3442         /*
3443          * Issue soft reset to chip.
3444          */
3445         printk(KERN_DEBUG PFX
3446                "%s: Issue soft reset to chip.\n",
3447                qdev->ndev->name);
3448         ql_write_common_reg(qdev,
3449                             &port_regs->CommonRegs.ispControlStatus,
3450                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3451
3452         /* Wait 3 seconds for reset to complete. */
3453         printk(KERN_DEBUG PFX
3454                "%s: Wait 10 milliseconds for reset to complete.\n",
3455                qdev->ndev->name);
3456
3457         /* Wait until the firmware tells us the Soft Reset is done */
3458         max_wait_time = 5;
3459         do {
3460                 value =
3461                     ql_read_common_reg(qdev,
3462                                        &port_regs->CommonRegs.ispControlStatus);
3463                 if ((value & ISP_CONTROL_SR) == 0)
3464                         break;
3465
3466                 ssleep(1);
3467         } while ((--max_wait_time));
3468
3469         /*
3470          * Also, make sure that the Network Reset Interrupt bit has been
3471          * cleared after the soft reset has taken place.
3472          */
3473         value =
3474             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3475         if (value & ISP_CONTROL_RI) {
3476                 printk(KERN_DEBUG PFX
3477                        "ql_adapter_reset: clearing RI after reset.\n");
3478                 ql_write_common_reg(qdev,
3479                                     &port_regs->CommonRegs.
3480                                     ispControlStatus,
3481                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3482         }
3483
3484         if (max_wait_time == 0) {
3485                 /* Issue Force Soft Reset */
3486                 ql_write_common_reg(qdev,
3487                                     &port_regs->CommonRegs.
3488                                     ispControlStatus,
3489                                     ((ISP_CONTROL_FSR << 16) |
3490                                      ISP_CONTROL_FSR));
3491                 /*
3492                  * Wait until the firmware tells us the Force Soft Reset is
3493                  * done
3494                  */
3495                 max_wait_time = 5;
3496                 do {
3497                         value =
3498                             ql_read_common_reg(qdev,
3499                                                &port_regs->CommonRegs.
3500                                                ispControlStatus);
3501                         if ((value & ISP_CONTROL_FSR) == 0) {
3502                                 break;
3503                         }
3504                         ssleep(1);
3505                 } while ((--max_wait_time));
3506         }
3507         if (max_wait_time == 0)
3508                 status = 1;
3509
3510         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3511         set_bit(QL_RESET_DONE, &qdev->flags);
3512         return status;
3513 }
3514
3515 static void ql_set_mac_info(struct ql3_adapter *qdev)
3516 {
3517         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3518         u32 value, port_status;
3519         u8 func_number;
3520
3521         /* Get the function number */
3522         value =
3523             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3524         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3525         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3526         switch (value & ISP_CONTROL_FN_MASK) {
3527         case ISP_CONTROL_FN0_NET:
3528                 qdev->mac_index = 0;
3529                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3530                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3531                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3532                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3533                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3534                 if (port_status & PORT_STATUS_SM0)
3535                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3536                 else
3537                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3538                 break;
3539
3540         case ISP_CONTROL_FN1_NET:
3541                 qdev->mac_index = 1;
3542                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3543                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3544                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3545                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3546                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3547                 if (port_status & PORT_STATUS_SM1)
3548                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3549                 else
3550                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3551                 break;
3552
3553         case ISP_CONTROL_FN0_SCSI:
3554         case ISP_CONTROL_FN1_SCSI:
3555         default:
3556                 printk(KERN_DEBUG PFX
3557                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3558                        qdev->ndev->name,value);
3559                 break;
3560         }
3561         qdev->numPorts = qdev->nvram_data.numPorts;
3562 }
3563
3564 static void ql_display_dev_info(struct net_device *ndev)
3565 {
3566         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3567         struct pci_dev *pdev = qdev->pdev;
3568         DECLARE_MAC_BUF(mac);
3569
3570         printk(KERN_INFO PFX
3571                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3572                DRV_NAME, qdev->index, qdev->chip_rev_id,
3573                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3574                qdev->pci_slot);
3575         printk(KERN_INFO PFX
3576                "%s Interface.\n",
3577                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3578
3579         /*
3580          * Print PCI bus width/type.
3581          */
3582         printk(KERN_INFO PFX
3583                "Bus interface is %s %s.\n",
3584                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3585                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3586
3587         printk(KERN_INFO PFX
3588                "mem  IO base address adjusted = 0x%p\n",
3589                qdev->mem_map_registers);
3590         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3591
3592         if (netif_msg_probe(qdev))
3593                 printk(KERN_INFO PFX
3594                        "%s: MAC address %s\n",
3595                        ndev->name, print_mac(mac, ndev->dev_addr));
3596 }
3597
3598 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3599 {
3600         struct net_device *ndev = qdev->ndev;
3601         int retval = 0;
3602
3603         netif_stop_queue(ndev);
3604         netif_carrier_off(ndev);
3605
3606         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3607         clear_bit(QL_LINK_MASTER,&qdev->flags);
3608
3609         ql_disable_interrupts(qdev);
3610
3611         free_irq(qdev->pdev->irq, ndev);
3612
3613         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3614                 printk(KERN_INFO PFX
3615                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3616                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3617                 pci_disable_msi(qdev->pdev);
3618         }
3619
3620         del_timer_sync(&qdev->adapter_timer);
3621
3622         napi_disable(&qdev->napi);
3623
3624         if (do_reset) {
3625                 int soft_reset;
3626                 unsigned long hw_flags;
3627
3628                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3629                 if (ql_wait_for_drvr_lock(qdev)) {
3630                         if ((soft_reset = ql_adapter_reset(qdev))) {
3631                                 printk(KERN_ERR PFX
3632                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3633                                        ndev->name, qdev->index);
3634                         }
3635                         printk(KERN_ERR PFX
3636                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3637                 } else {
3638                         printk(KERN_ERR PFX
3639                                "%s: Could not acquire driver lock to do "
3640                                "reset!\n", ndev->name);
3641                         retval = -1;
3642                 }
3643                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3644         }
3645         ql_free_mem_resources(qdev);
3646         return retval;
3647 }
3648
3649 static int ql_adapter_up(struct ql3_adapter *qdev)
3650 {
3651         struct net_device *ndev = qdev->ndev;
3652         int err;
3653         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3654         unsigned long hw_flags;
3655
3656         if (ql_alloc_mem_resources(qdev)) {
3657                 printk(KERN_ERR PFX
3658                        "%s Unable to  allocate buffers.\n", ndev->name);
3659                 return -ENOMEM;
3660         }
3661
3662         if (qdev->msi) {
3663                 if (pci_enable_msi(qdev->pdev)) {
3664                         printk(KERN_ERR PFX
3665                                "%s: User requested MSI, but MSI failed to "
3666                                "initialize.  Continuing without MSI.\n",
3667                                qdev->ndev->name);
3668                         qdev->msi = 0;
3669                 } else {
3670                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3671                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3672                         irq_flags &= ~IRQF_SHARED;
3673                 }
3674         }
3675
3676         if ((err = request_irq(qdev->pdev->irq,
3677                                ql3xxx_isr,
3678                                irq_flags, ndev->name, ndev))) {
3679                 printk(KERN_ERR PFX
3680                        "%s: Failed to reserve interrupt %d already in use.\n",
3681                        ndev->name, qdev->pdev->irq);
3682                 goto err_irq;
3683         }
3684
3685         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3686
3687         if ((err = ql_wait_for_drvr_lock(qdev))) {
3688                 if ((err = ql_adapter_initialize(qdev))) {
3689                         printk(KERN_ERR PFX
3690                                "%s: Unable to initialize adapter.\n",
3691                                ndev->name);
3692                         goto err_init;
3693                 }
3694                 printk(KERN_ERR PFX
3695                                 "%s: Releaseing driver lock.\n",ndev->name);
3696                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3697         } else {
3698                 printk(KERN_ERR PFX
3699                        "%s: Could not aquire driver lock.\n",
3700                        ndev->name);
3701                 goto err_lock;
3702         }
3703
3704         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3705
3706         set_bit(QL_ADAPTER_UP,&qdev->flags);
3707
3708         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3709
3710         napi_enable(&qdev->napi);
3711         ql_enable_interrupts(qdev);
3712         return 0;
3713
3714 err_init:
3715         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3716 err_lock:
3717         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3718         free_irq(qdev->pdev->irq, ndev);
3719 err_irq:
3720         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3721                 printk(KERN_INFO PFX
3722                        "%s: calling pci_disable_msi().\n",
3723                        qdev->ndev->name);
3724                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3725                 pci_disable_msi(qdev->pdev);
3726         }
3727         return err;
3728 }
3729
3730 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3731 {
3732         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3733                 printk(KERN_ERR PFX
3734                                 "%s: Driver up/down cycle failed, "
3735                                 "closing device\n",qdev->ndev->name);
3736                 dev_close(qdev->ndev);
3737                 return -1;
3738         }
3739         return 0;
3740 }
3741
3742 static int ql3xxx_close(struct net_device *ndev)
3743 {
3744         struct ql3_adapter *qdev = netdev_priv(ndev);
3745
3746         /*
3747          * Wait for device to recover from a reset.
3748          * (Rarely happens, but possible.)
3749          */
3750         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3751                 msleep(50);
3752
3753         ql_adapter_down(qdev,QL_DO_RESET);
3754         return 0;
3755 }
3756
3757 static int ql3xxx_open(struct net_device *ndev)
3758 {
3759         struct ql3_adapter *qdev = netdev_priv(ndev);
3760         return (ql_adapter_up(qdev));
3761 }
3762
3763 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3764 {
3765         /*
3766          * We are manually parsing the list in the net_device structure.
3767          */
3768         return;
3769 }
3770
3771 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3772 {
3773         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3774         struct ql3xxx_port_registers __iomem *port_regs =
3775                         qdev->mem_map_registers;
3776         struct sockaddr *addr = p;
3777         unsigned long hw_flags;
3778
3779         if (netif_running(ndev))
3780                 return -EBUSY;
3781
3782         if (!is_valid_ether_addr(addr->sa_data))
3783                 return -EADDRNOTAVAIL;
3784
3785         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3786
3787         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3788         /* Program lower 32 bits of the MAC address */
3789         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3790                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3791         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3792                            ((ndev->dev_addr[2] << 24) | (ndev->
3793                                                          dev_addr[3] << 16) |
3794                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3795
3796         /* Program top 16 bits of the MAC address */
3797         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3798                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3799         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3800                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3801         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3802
3803         return 0;
3804 }
3805
3806 static void ql3xxx_tx_timeout(struct net_device *ndev)
3807 {
3808         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3809
3810         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3811         /*
3812          * Stop the queues, we've got a problem.
3813          */
3814         netif_stop_queue(ndev);
3815
3816         /*
3817          * Wake up the worker to process this event.
3818          */
3819         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3820 }
3821
3822 static void ql_reset_work(struct work_struct *work)
3823 {
3824         struct ql3_adapter *qdev =
3825                 container_of(work, struct ql3_adapter, reset_work.work);
3826         struct net_device *ndev = qdev->ndev;
3827         u32 value;
3828         struct ql_tx_buf_cb *tx_cb;
3829         int max_wait_time, i;
3830         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3831         unsigned long hw_flags;
3832
3833         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3834                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3835
3836                 /*
3837                  * Loop through the active list and return the skb.
3838                  */
3839                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3840                         int j;
3841                         tx_cb = &qdev->tx_buf[i];
3842                         if (tx_cb->skb) {
3843                                 printk(KERN_DEBUG PFX
3844                                        "%s: Freeing lost SKB.\n",
3845                                        qdev->ndev->name);
3846                                 pci_unmap_single(qdev->pdev,
3847                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3848                                          pci_unmap_len(&tx_cb->map[0], maplen),
3849                                          PCI_DMA_TODEVICE);
3850                                 for(j=1;j<tx_cb->seg_count;j++) {
3851                                         pci_unmap_page(qdev->pdev,
3852                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3853                                                pci_unmap_len(&tx_cb->map[j],maplen),
3854                                                PCI_DMA_TODEVICE);
3855                                 }
3856                                 dev_kfree_skb(tx_cb->skb);
3857                                 tx_cb->skb = NULL;
3858                         }
3859                 }
3860
3861                 printk(KERN_ERR PFX
3862                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3863                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3864                 ql_write_common_reg(qdev,
3865                                     &port_regs->CommonRegs.
3866                                     ispControlStatus,
3867                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3868                 /*
3869                  * Wait the for Soft Reset to Complete.
3870                  */
3871                 max_wait_time = 10;
3872                 do {
3873                         value = ql_read_common_reg(qdev,
3874                                                    &port_regs->CommonRegs.
3875
3876                                                    ispControlStatus);
3877                         if ((value & ISP_CONTROL_SR) == 0) {
3878                                 printk(KERN_DEBUG PFX
3879                                        "%s: reset completed.\n",
3880                                        qdev->ndev->name);
3881                                 break;
3882                         }
3883
3884                         if (value & ISP_CONTROL_RI) {
3885                                 printk(KERN_DEBUG PFX
3886                                        "%s: clearing NRI after reset.\n",
3887                                        qdev->ndev->name);
3888                                 ql_write_common_reg(qdev,
3889                                                     &port_regs->
3890                                                     CommonRegs.
3891                                                     ispControlStatus,
3892                                                     ((ISP_CONTROL_RI <<
3893                                                       16) | ISP_CONTROL_RI));
3894                         }
3895
3896                         ssleep(1);
3897                 } while (--max_wait_time);
3898                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3899
3900                 if (value & ISP_CONTROL_SR) {
3901
3902                         /*
3903                          * Set the reset flags and clear the board again.
3904                          * Nothing else to do...
3905                          */
3906                         printk(KERN_ERR PFX
3907                                "%s: Timed out waiting for reset to "
3908                                "complete.\n", ndev->name);
3909                         printk(KERN_ERR PFX
3910                                "%s: Do a reset.\n", ndev->name);
3911                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3912                         clear_bit(QL_RESET_START,&qdev->flags);
3913                         ql_cycle_adapter(qdev,QL_DO_RESET);
3914                         return;
3915                 }
3916
3917                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3918                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3919                 clear_bit(QL_RESET_START,&qdev->flags);
3920                 ql_cycle_adapter(qdev,QL_NO_RESET);
3921         }
3922 }
3923
3924 static void ql_tx_timeout_work(struct work_struct *work)
3925 {
3926         struct ql3_adapter *qdev =
3927                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3928
3929         ql_cycle_adapter(qdev, QL_DO_RESET);
3930 }
3931
3932 static void ql_get_board_info(struct ql3_adapter *qdev)
3933 {
3934         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3935         u32 value;
3936
3937         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3938
3939         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3940         if (value & PORT_STATUS_64)
3941                 qdev->pci_width = 64;
3942         else
3943                 qdev->pci_width = 32;
3944         if (value & PORT_STATUS_X)
3945                 qdev->pci_x = 1;
3946         else
3947                 qdev->pci_x = 0;
3948         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3949 }
3950
3951 static void ql3xxx_timer(unsigned long ptr)
3952 {
3953         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3954         queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3955 }
3956
3957 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3958                                   const struct pci_device_id *pci_entry)
3959 {
3960         struct net_device *ndev = NULL;
3961         struct ql3_adapter *qdev = NULL;
3962         static int cards_found = 0;
3963         int pci_using_dac, err;
3964
3965         err = pci_enable_device(pdev);
3966         if (err) {
3967                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3968                        pci_name(pdev));
3969                 goto err_out;
3970         }
3971
3972         err = pci_request_regions(pdev, DRV_NAME);
3973         if (err) {
3974                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3975                        pci_name(pdev));
3976                 goto err_out_disable_pdev;
3977         }
3978
3979         pci_set_master(pdev);
3980
3981         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3982                 pci_using_dac = 1;
3983                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3984         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3985                 pci_using_dac = 0;
3986                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3987         }
3988
3989         if (err) {
3990                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3991                        pci_name(pdev));
3992                 goto err_out_free_regions;
3993         }
3994
3995         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3996         if (!ndev) {
3997                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3998                        pci_name(pdev));
3999                 err = -ENOMEM;
4000                 goto err_out_free_regions;
4001         }
4002
4003         SET_NETDEV_DEV(ndev, &pdev->dev);
4004
4005         pci_set_drvdata(pdev, ndev);
4006
4007         qdev = netdev_priv(ndev);
4008         qdev->index = cards_found;
4009         qdev->ndev = ndev;
4010         qdev->pdev = pdev;
4011         qdev->device_id = pci_entry->device;
4012         qdev->port_link_state = LS_DOWN;
4013         if (msi)
4014                 qdev->msi = 1;
4015
4016         qdev->msg_enable = netif_msg_init(debug, default_msg);
4017
4018         if (pci_using_dac)
4019                 ndev->features |= NETIF_F_HIGHDMA;
4020         if (qdev->device_id == QL3032_DEVICE_ID)
4021                 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4022
4023         qdev->mem_map_registers =
4024             ioremap_nocache(pci_resource_start(pdev, 1),
4025                             pci_resource_len(qdev->pdev, 1));
4026         if (!qdev->mem_map_registers) {
4027                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
4028                        pci_name(pdev));
4029                 err = -EIO;
4030                 goto err_out_free_ndev;
4031         }
4032
4033         spin_lock_init(&qdev->adapter_lock);
4034         spin_lock_init(&qdev->hw_lock);
4035
4036         /* Set driver entry points */
4037         ndev->open = ql3xxx_open;
4038         ndev->hard_start_xmit = ql3xxx_send;
4039         ndev->stop = ql3xxx_close;
4040         ndev->set_multicast_list = ql3xxx_set_multicast_list;
4041         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4042         ndev->set_mac_address = ql3xxx_set_mac_address;
4043         ndev->tx_timeout = ql3xxx_tx_timeout;
4044         ndev->watchdog_timeo = 5 * HZ;
4045
4046         netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
4047
4048         ndev->irq = pdev->irq;
4049
4050         /* make sure the EEPROM is good */
4051         if (ql_get_nvram_params(qdev)) {
4052                 printk(KERN_ALERT PFX
4053                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4054                        qdev->index);
4055                 err = -EIO;
4056                 goto err_out_iounmap;
4057         }
4058
4059         ql_set_mac_info(qdev);
4060
4061         /* Validate and set parameters */
4062         if (qdev->mac_index) {
4063                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
4064                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
4065                        ETH_ALEN);
4066         } else {
4067                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
4068                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
4069                        ETH_ALEN);
4070         }
4071         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4072
4073         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4074
4075         /* Turn off support for multicasting */
4076         ndev->flags &= ~IFF_MULTICAST;
4077
4078         /* Record PCI bus information. */
4079         ql_get_board_info(qdev);
4080
4081         /*
4082          * Set the Maximum Memory Read Byte Count value. We do this to handle
4083          * jumbo frames.
4084          */
4085         if (qdev->pci_x) {
4086                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4087         }
4088
4089         err = register_netdev(ndev);
4090         if (err) {
4091                 printk(KERN_ERR PFX "%s: cannot register net device\n",
4092                        pci_name(pdev));
4093                 goto err_out_iounmap;
4094         }
4095
4096         /* we're going to reset, so assume we have no link for now */
4097
4098         netif_carrier_off(ndev);
4099         netif_stop_queue(ndev);
4100
4101         qdev->workqueue = create_singlethread_workqueue(ndev->name);
4102         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4103         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
4104         INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
4105
4106         init_timer(&qdev->adapter_timer);
4107         qdev->adapter_timer.function = ql3xxx_timer;
4108         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4109         qdev->adapter_timer.data = (unsigned long)qdev;
4110
4111         if(!cards_found) {
4112                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4113                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4114                    DRV_NAME, DRV_VERSION);
4115         }
4116         ql_display_dev_info(ndev);
4117
4118         cards_found++;
4119         return 0;
4120
4121 err_out_iounmap:
4122         iounmap(qdev->mem_map_registers);
4123 err_out_free_ndev:
4124         free_netdev(ndev);
4125 err_out_free_regions:
4126         pci_release_regions(pdev);
4127 err_out_disable_pdev:
4128         pci_disable_device(pdev);
4129         pci_set_drvdata(pdev, NULL);
4130 err_out:
4131         return err;
4132 }
4133
4134 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4135 {
4136         struct net_device *ndev = pci_get_drvdata(pdev);
4137         struct ql3_adapter *qdev = netdev_priv(ndev);
4138
4139         unregister_netdev(ndev);
4140         qdev = netdev_priv(ndev);
4141
4142         ql_disable_interrupts(qdev);
4143
4144         if (qdev->workqueue) {
4145                 cancel_delayed_work(&qdev->reset_work);
4146                 cancel_delayed_work(&qdev->tx_timeout_work);
4147                 destroy_workqueue(qdev->workqueue);
4148                 qdev->workqueue = NULL;
4149         }
4150
4151         iounmap(qdev->mem_map_registers);
4152         pci_release_regions(pdev);
4153         pci_set_drvdata(pdev, NULL);
4154         free_netdev(ndev);
4155 }
4156
4157 static struct pci_driver ql3xxx_driver = {
4158
4159         .name = DRV_NAME,
4160         .id_table = ql3xxx_pci_tbl,
4161         .probe = ql3xxx_probe,
4162         .remove = __devexit_p(ql3xxx_remove),
4163 };
4164
4165 static int __init ql3xxx_init_module(void)
4166 {
4167         return pci_register_driver(&ql3xxx_driver);
4168 }
4169
4170 static void __exit ql3xxx_exit(void)
4171 {
4172         pci_unregister_driver(&ql3xxx_driver);
4173 }
4174
4175 module_init(ql3xxx_init_module);
4176 module_exit(ql3xxx_exit);