2 * Copyright (C) 2006 PA Semi, Inc
4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
5 * hardware register layouts.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/ethtool.h>
25 #include <linux/netdevice.h>
26 #include <linux/spinlock.h>
27 #include <linux/phy.h>
29 struct pasemi_mac_txring {
31 u64 *status; /* Ptr to cacheable status area */
35 unsigned int next_to_fill;
36 unsigned int next_to_clean;
37 struct pasemi_mac_buffer *ring_info;
39 struct pasemi_mac *mac; /* Needed in intr handler */
42 struct pasemi_mac_rxring {
44 u64 *status; /* Ptr to cacheable status area */
45 u64 *ring; /* RX channel descriptor ring */
47 u64 *buffers; /* RX interface buffer ring */
50 unsigned int next_to_fill;
51 unsigned int next_to_clean;
52 struct pasemi_mac_buffer *ring_info;
53 struct pasemi_mac *mac; /* Needed in intr handler */
57 struct net_device *netdev;
59 void __iomem *dma_regs;
60 void __iomem *iob_regs;
62 struct pci_dev *dma_pdev;
63 struct pci_dev *iob_pdev;
64 struct phy_device *phydev;
65 struct napi_struct napi;
68 #define MAC_TYPE_GMAC 1
69 #define MAC_TYPE_XAUI 2
76 struct timer_list rxtimer;
78 struct pasemi_mac_txring *tx;
79 struct pasemi_mac_rxring *rx;
82 char tx_irq_name[10]; /* "eth%d tx" */
83 char rx_irq_name[10]; /* "eth%d rx" */
88 unsigned int msg_enable;
89 char phy_id[BUS_ID_SIZE];
92 /* Software status descriptor (ring_info) */
93 struct pasemi_mac_buffer {
99 /* status register layout in IOB region, at 0xfb800000 */
100 struct pasdma_status {
105 /* MAC CFG register offsets */
107 PAS_MAC_CFG_PCFG = 0x80,
108 PAS_MAC_CFG_TXP = 0x98,
109 PAS_MAC_IPC_CHNL = 0x208,
112 /* MAC CFG register fields */
113 #define PAS_MAC_CFG_PCFG_PE 0x80000000
114 #define PAS_MAC_CFG_PCFG_CE 0x40000000
115 #define PAS_MAC_CFG_PCFG_BU 0x20000000
116 #define PAS_MAC_CFG_PCFG_TT 0x10000000
117 #define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
118 #define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
119 #define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
120 #define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
121 #define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
122 #define PAS_MAC_CFG_PCFG_T24 0x02000000
123 #define PAS_MAC_CFG_PCFG_PR 0x01000000
124 #define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
125 #define PAS_MAC_CFG_PCFG_CRO_S 16
126 #define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
127 #define PAS_MAC_CFG_PCFG_IPO_S 8
128 #define PAS_MAC_CFG_PCFG_S1 0x00000080
129 #define PAS_MAC_CFG_PCFG_IO_M 0x00000060
130 #define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
131 #define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
132 #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
133 #define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
134 #define PAS_MAC_CFG_PCFG_LP 0x00000010
135 #define PAS_MAC_CFG_PCFG_TS 0x00000008
136 #define PAS_MAC_CFG_PCFG_HD 0x00000004
137 #define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
138 #define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
139 #define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
140 #define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
141 #define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
142 #define PAS_MAC_CFG_TXP_FCF 0x01000000
143 #define PAS_MAC_CFG_TXP_FCE 0x00800000
144 #define PAS_MAC_CFG_TXP_FC 0x00400000
145 #define PAS_MAC_CFG_TXP_FPC_M 0x00300000
146 #define PAS_MAC_CFG_TXP_FPC_S 20
147 #define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
148 PAS_MAC_CFG_TXP_FPC_M)
149 #define PAS_MAC_CFG_TXP_RT 0x00080000
150 #define PAS_MAC_CFG_TXP_BL 0x00040000
151 #define PAS_MAC_CFG_TXP_SL_M 0x00030000
152 #define PAS_MAC_CFG_TXP_SL_S 16
153 #define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
154 PAS_MAC_CFG_TXP_SL_M)
155 #define PAS_MAC_CFG_TXP_COB_M 0x0000f000
156 #define PAS_MAC_CFG_TXP_COB_S 12
157 #define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
158 PAS_MAC_CFG_TXP_COB_M)
159 #define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
160 #define PAS_MAC_CFG_TXP_TIFT_S 8
161 #define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
162 PAS_MAC_CFG_TXP_TIFT_M)
163 #define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
164 #define PAS_MAC_CFG_TXP_TIFG_S 0
165 #define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
166 PAS_MAC_CFG_TXP_TIFG_M)
168 #define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
169 #define PAS_MAC_IPC_CHNL_DCHNO_S 16
170 #define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
171 PAS_MAC_IPC_CHNL_DCHNO_M)
172 #define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
173 #define PAS_MAC_IPC_CHNL_BCH_S 0
174 #define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
175 PAS_MAC_IPC_CHNL_BCH_M)
177 /* All these registers live in the PCI configuration space for the DMA PCI
178 * device. Use the normal PCI config access functions for them.
181 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
182 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
183 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
184 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
186 #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
187 #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
188 #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
189 #define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
192 /* Per-interface and per-channel registers */
193 #define _PAS_DMA_RXINT_STRIDE 0x20
194 #define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
195 #define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
196 #define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
197 #define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
198 #define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
199 #define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
200 #define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
201 #define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
202 #define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
203 #define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
204 #define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
205 #define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
206 #define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
207 #define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
208 #define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
209 #define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
210 #define PAS_DMA_RXINT_CFG_RBP 0x80000000
211 #define PAS_DMA_RXINT_CFG_ITRR 0x40000000
212 #define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
213 #define PAS_DMA_RXINT_CFG_DHL_S 24
214 #define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
215 PAS_DMA_RXINT_CFG_DHL_M)
216 #define PAS_DMA_RXINT_CFG_ITR 0x00400000
217 #define PAS_DMA_RXINT_CFG_LW 0x00200000
218 #define PAS_DMA_RXINT_CFG_L2 0x00100000
219 #define PAS_DMA_RXINT_CFG_HEN 0x00080000
220 #define PAS_DMA_RXINT_CFG_WIF 0x00000002
221 #define PAS_DMA_RXINT_CFG_WIL 0x00000001
223 #define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
224 #define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
225 #define PAS_DMA_RXINT_INCR_INCR_S 0
226 #define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
227 #define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
228 #define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
229 #define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
230 #define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
231 #define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
232 #define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
233 #define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
234 PAS_DMA_RXINT_BASEU_SIZ_M)
237 #define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
238 #define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
239 #define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
240 #define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
241 #define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
242 #define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
243 #define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
244 #define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
245 #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
246 #define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
247 #define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
248 #define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
249 #define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800
250 #define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400
251 #define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200
252 #define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
253 #define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
254 #define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
255 #define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
256 #define PAS_DMA_TXCHAN_CFG_TATTR_S 2
257 #define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
258 PAS_DMA_TXCHAN_CFG_TATTR_M)
259 #define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
260 #define PAS_DMA_TXCHAN_CFG_WT_S 6
261 #define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
262 PAS_DMA_TXCHAN_CFG_WT_M)
263 #define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */
264 #define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */
265 #define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
266 #define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
267 #define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
268 #define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
269 #define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
270 #define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
271 #define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
272 #define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
273 PAS_DMA_TXCHAN_BASEL_BRBL_M)
274 #define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
275 #define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
276 #define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
277 #define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
278 PAS_DMA_TXCHAN_BASEU_BRBH_M)
279 /* # of cache lines worth of buffer ring */
280 #define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
281 #define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
282 #define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
283 PAS_DMA_TXCHAN_BASEU_SIZ_M)
285 #define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
286 #define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
287 #define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
288 #define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
289 #define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
290 #define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
291 #define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
292 #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
293 #define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
294 #define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
295 #define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
296 #define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
297 #define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000
298 #define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000
299 #define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800
300 #define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
301 #define PAS_DMA_RXCHAN_CFG_CTR 0x00000400
302 #define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
303 #define PAS_DMA_RXCHAN_CFG_HBU_S 7
304 #define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
305 PAS_DMA_RXCHAN_CFG_HBU_M)
306 #define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
307 #define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
308 #define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
309 #define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
310 #define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
311 PAS_DMA_RXCHAN_BASEL_BRBL_M)
312 #define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
313 #define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
314 #define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
315 #define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
316 PAS_DMA_RXCHAN_BASEU_BRBH_M)
317 /* # of cache lines worth of buffer ring */
318 #define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
319 #define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
320 #define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
321 PAS_DMA_RXCHAN_BASEU_SIZ_M)
323 #define PAS_STATUS_PCNT_M 0x000000000000ffffull
324 #define PAS_STATUS_PCNT_S 0
325 #define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
326 #define PAS_STATUS_DCNT_S 16
327 #define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
328 #define PAS_STATUS_BPCNT_S 32
329 #define PAS_STATUS_CAUSE_M 0xf000000000000000ull
330 #define PAS_STATUS_TIMER 0x1000000000000000ull
331 #define PAS_STATUS_ERROR 0x2000000000000000ull
332 #define PAS_STATUS_SOFT 0x4000000000000000ull
333 #define PAS_STATUS_INT 0x8000000000000000ull
335 #define PAS_IOB_COM_PKTHDRCNT 0x120
336 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000
337 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16
338 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff
339 #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0
341 #define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
342 #define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
343 #define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
344 #define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
345 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
346 #define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
347 #define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
348 #define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
349 #define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
350 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
351 #define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
352 #define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
353 #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
354 #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
355 #define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
356 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
357 #define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
358 #define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
359 #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
360 #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
361 #define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
362 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
363 #define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
364 #define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
365 #define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16
366 #define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
367 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
368 #define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
369 #define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
370 #define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
371 #define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
372 #define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
373 #define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
374 #define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
375 #define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
376 #define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16
377 #define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
378 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
379 #define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
380 #define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
381 #define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
382 #define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
383 #define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
384 #define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
386 #define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
387 #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
388 #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
389 #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
390 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
392 /* Transmit descriptor fields */
393 #define XCT_MACTX_T 0x8000000000000000ull
394 #define XCT_MACTX_ST 0x4000000000000000ull
395 #define XCT_MACTX_NORES 0x0000000000000000ull
396 #define XCT_MACTX_8BRES 0x1000000000000000ull
397 #define XCT_MACTX_24BRES 0x2000000000000000ull
398 #define XCT_MACTX_40BRES 0x3000000000000000ull
399 #define XCT_MACTX_I 0x0800000000000000ull
400 #define XCT_MACTX_O 0x0400000000000000ull
401 #define XCT_MACTX_E 0x0200000000000000ull
402 #define XCT_MACTX_VLAN_M 0x0180000000000000ull
403 #define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
404 #define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
405 #define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
406 #define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
407 #define XCT_MACTX_CRC_M 0x0060000000000000ull
408 #define XCT_MACTX_CRC_NOP 0x0000000000000000ull
409 #define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
410 #define XCT_MACTX_CRC_PAD 0x0040000000000000ull
411 #define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
412 #define XCT_MACTX_SS 0x0010000000000000ull
413 #define XCT_MACTX_LLEN_M 0x00007fff00000000ull
414 #define XCT_MACTX_LLEN_S 32ull
415 #define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
417 #define XCT_MACTX_IPH_M 0x00000000f8000000ull
418 #define XCT_MACTX_IPH_S 27ull
419 #define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
421 #define XCT_MACTX_IPO_M 0x0000000007c00000ull
422 #define XCT_MACTX_IPO_S 22ull
423 #define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
425 #define XCT_MACTX_CSUM_M 0x0000000000000060ull
426 #define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
427 #define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
428 #define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
429 #define XCT_MACTX_V6 0x0000000000000010ull
430 #define XCT_MACTX_C 0x0000000000000004ull
431 #define XCT_MACTX_AL2 0x0000000000000002ull
433 /* Receive descriptor fields */
434 #define XCT_MACRX_T 0x8000000000000000ull
435 #define XCT_MACRX_ST 0x4000000000000000ull
436 #define XCT_MACRX_RR_M 0x3000000000000000ull
437 #define XCT_MACRX_RR_NORES 0x0000000000000000ull
438 #define XCT_MACRX_RR_8BRES 0x1000000000000000ull
439 #define XCT_MACRX_O 0x0400000000000000ull
440 #define XCT_MACRX_E 0x0200000000000000ull
441 #define XCT_MACRX_FF 0x0100000000000000ull
442 #define XCT_MACRX_PF 0x0080000000000000ull
443 #define XCT_MACRX_OB 0x0040000000000000ull
444 #define XCT_MACRX_OD 0x0020000000000000ull
445 #define XCT_MACRX_FS 0x0010000000000000ull
446 #define XCT_MACRX_NB_M 0x000fc00000000000ull
447 #define XCT_MACRX_NB_S 46ULL
448 #define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
450 #define XCT_MACRX_LLEN_M 0x00003fff00000000ull
451 #define XCT_MACRX_LLEN_S 32ULL
452 #define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
454 #define XCT_MACRX_CRC 0x0000000080000000ull
455 #define XCT_MACRX_LEN_M 0x0000000060000000ull
456 #define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
457 #define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
458 #define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
459 #define XCT_MACRX_CAST_M 0x0000000018000000ull
460 #define XCT_MACRX_CAST_UNI 0x0000000000000000ull
461 #define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
462 #define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
463 #define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
464 #define XCT_MACRX_VLC_M 0x0000000006000000ull
465 #define XCT_MACRX_FM 0x0000000001000000ull
466 #define XCT_MACRX_HTY_M 0x0000000000c00000ull
467 #define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
468 #define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
469 #define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
470 #define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
471 #define XCT_MACRX_IPP_M 0x00000000003f0000ull
472 #define XCT_MACRX_IPP_S 16
473 #define XCT_MACRX_CSUM_M 0x000000000000ffffull
474 #define XCT_MACRX_CSUM_S 0
476 #define XCT_PTR_T 0x8000000000000000ull
477 #define XCT_PTR_LEN_M 0x7ffff00000000000ull
478 #define XCT_PTR_LEN_S 44
479 #define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
481 #define XCT_PTR_ADDR_M 0x00000fffffffffffull
482 #define XCT_PTR_ADDR_S 0
483 #define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
486 /* Receive interface 8byte result fields */
487 #define XCT_RXRES_8B_L4O_M 0xff00000000000000ull
488 #define XCT_RXRES_8B_L4O_S 56
489 #define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull
490 #define XCT_RXRES_8B_RULE_S 40
491 #define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull
492 #define XCT_RXRES_8B_EVAL_S 24
493 #define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull
494 #define XCT_RXRES_8B_HASH_M 0x00000000000fffffull
495 #define XCT_RXRES_8B_HASH_S 0
497 /* Receive interface buffer fields */
498 #define XCT_RXB_LEN_M 0x0ffff00000000000ull
499 #define XCT_RXB_LEN_S 44
500 #define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
501 #define XCT_RXB_ADDR_M 0x00000fffffffffffull
502 #define XCT_RXB_ADDR_S 0
503 #define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
506 #endif /* PASEMI_MAC_H */