2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <asm/dma-mapping.h>
30 #include <linux/skbuff.h>
33 #include <linux/tcp.h>
34 #include <net/checksum.h>
38 #include "pasemi_mac.h"
43 * - Get rid of pci_{read,write}_config(), map registers with ioremap
48 * - Other performance improvements
52 /* Must be a power of two */
53 #define RX_RING_SIZE 512
54 #define TX_RING_SIZE 512
56 #define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)])
57 #define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)])
58 #define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)])
59 #define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)])
60 #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
62 #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
64 /* XXXOJN these should come out of the device tree some day */
65 #define PAS_DMA_CAP_BASE 0xe00d0040
66 #define PAS_DMA_CAP_SIZE 0x100
67 #define PAS_DMA_COM_BASE 0xe00d0100
68 #define PAS_DMA_COM_SIZE 0x100
70 static struct pasdma_status *dma_status;
72 static int pasemi_get_mac_addr(struct pasemi_mac *mac)
74 struct pci_dev *pdev = mac->pdev;
75 struct device_node *dn = pci_device_to_OF_node(pdev);
81 "No device node for mac, not configuring\n");
85 maddr = get_property(dn, "mac-address", NULL);
88 "no mac address in device tree, not configuring\n");
92 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
93 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
95 "can't parse mac address, not configuring\n");
99 memcpy(mac->mac_addr, addr, sizeof(addr));
103 static int pasemi_mac_setup_rx_resources(struct net_device *dev)
105 struct pasemi_mac_rxring *ring;
106 struct pasemi_mac *mac = netdev_priv(dev);
107 int chan_id = mac->dma_rxch;
109 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
114 spin_lock_init(&ring->lock);
116 ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
117 RX_RING_SIZE, GFP_KERNEL);
119 if (!ring->desc_info)
122 /* Allocate descriptors */
123 ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
125 sizeof(struct pas_dma_xct_descr),
126 &ring->dma, GFP_KERNEL);
131 memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
133 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
134 RX_RING_SIZE * sizeof(u64),
135 &ring->buf_dma, GFP_KERNEL);
139 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
141 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id),
142 PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
144 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id),
145 PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
146 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
148 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id),
149 PAS_DMA_RXCHAN_CFG_HBU(1));
151 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if),
152 PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
154 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if),
155 PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
156 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
158 ring->next_to_fill = 0;
159 ring->next_to_clean = 0;
161 snprintf(ring->irq_name, sizeof(ring->irq_name),
168 dma_free_coherent(&mac->dma_pdev->dev,
169 RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
170 mac->rx->desc, mac->rx->dma);
172 kfree(ring->desc_info);
180 static int pasemi_mac_setup_tx_resources(struct net_device *dev)
182 struct pasemi_mac *mac = netdev_priv(dev);
184 int chan_id = mac->dma_txch;
185 struct pasemi_mac_txring *ring;
187 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
191 spin_lock_init(&ring->lock);
193 ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
194 TX_RING_SIZE, GFP_KERNEL);
195 if (!ring->desc_info)
198 /* Allocate descriptors */
199 ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
201 sizeof(struct pas_dma_xct_descr),
202 &ring->dma, GFP_KERNEL);
206 memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
208 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id),
209 PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
210 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
211 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2);
213 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val);
215 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id),
216 PAS_DMA_TXCHAN_CFG_TY_IFACE |
217 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
218 PAS_DMA_TXCHAN_CFG_UP |
219 PAS_DMA_TXCHAN_CFG_WT(2));
221 ring->next_to_use = 0;
222 ring->next_to_clean = 0;
224 snprintf(ring->irq_name, sizeof(ring->irq_name),
231 kfree(ring->desc_info);
238 static void pasemi_mac_free_tx_resources(struct net_device *dev)
240 struct pasemi_mac *mac = netdev_priv(dev);
242 struct pasemi_mac_buffer *info;
243 struct pas_dma_xct_descr *dp;
245 for (i = 0; i < TX_RING_SIZE; i++) {
246 info = &TX_DESC_INFO(mac, i);
247 dp = &TX_DESC(mac, i);
250 pci_unmap_single(mac->dma_pdev,
254 dev_kfree_skb_any(info->skb);
263 dma_free_coherent(&mac->dma_pdev->dev,
264 TX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
265 mac->tx->desc, mac->tx->dma);
267 kfree(mac->tx->desc_info);
272 static void pasemi_mac_free_rx_resources(struct net_device *dev)
274 struct pasemi_mac *mac = netdev_priv(dev);
276 struct pasemi_mac_buffer *info;
277 struct pas_dma_xct_descr *dp;
279 for (i = 0; i < RX_RING_SIZE; i++) {
280 info = &RX_DESC_INFO(mac, i);
281 dp = &RX_DESC(mac, i);
284 pci_unmap_single(mac->dma_pdev,
288 dev_kfree_skb_any(info->skb);
297 dma_free_coherent(&mac->dma_pdev->dev,
298 RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
299 mac->rx->desc, mac->rx->dma);
301 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
302 mac->rx->buffers, mac->rx->buf_dma);
304 kfree(mac->rx->desc_info);
309 static void pasemi_mac_replenish_rx_ring(struct net_device *dev)
311 struct pasemi_mac *mac = netdev_priv(dev);
313 int start = mac->rx->next_to_fill;
316 count = (mac->rx->next_to_clean + RX_RING_SIZE -
317 mac->rx->next_to_fill) & (RX_RING_SIZE - 1);
319 /* Check to see if we're doing first-time setup */
320 if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0))
321 count = RX_RING_SIZE;
326 for (i = start; i < start + count; i++) {
327 struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i);
328 u64 *buff = &RX_BUFF(mac, i);
332 /* skb might still be in there for recycle on short receives */
336 skb = dev_alloc_skb(BUF_SIZE);
341 dma = pci_map_single(mac->dma_pdev, skb->data, skb->len,
344 if (dma_mapping_error(dma)) {
345 dev_kfree_skb_irq(info->skb);
352 *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
357 pci_write_config_dword(mac->dma_pdev,
358 PAS_DMA_RXCHAN_INCR(mac->dma_rxch),
360 pci_write_config_dword(mac->dma_pdev,
361 PAS_DMA_RXINT_INCR(mac->dma_if),
364 mac->rx->next_to_fill += count;
367 static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
369 unsigned int reg, stat;
370 /* Re-enable packet count interrupts: finally
371 * ack the packet count interrupt we got in rx_intr.
374 pci_read_config_dword(mac->iob_pdev,
375 PAS_IOB_DMA_RXCH_STAT(mac->dma_rxch),
378 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(stat & PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
379 | PAS_IOB_DMA_RXCH_RESET_PINTC;
381 pci_write_config_dword(mac->iob_pdev,
382 PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch),
386 static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
388 unsigned int reg, stat;
390 /* Re-enable packet count interrupts */
391 pci_read_config_dword(mac->iob_pdev,
392 PAS_IOB_DMA_TXCH_STAT(mac->dma_txch), &stat);
394 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(stat & PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
395 | PAS_IOB_DMA_TXCH_RESET_PINTC;
397 pci_write_config_dword(mac->iob_pdev,
398 PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
403 static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
408 spin_lock(&mac->rx->lock);
410 start = mac->rx->next_to_clean;
413 for (i = start; i < (start + RX_RING_SIZE) && count < limit; i++) {
414 struct pas_dma_xct_descr *dp;
415 struct pasemi_mac_buffer *info;
422 dp = &RX_DESC(mac, i);
424 if (!(dp->macrx & XCT_MACRX_O))
431 /* We have to scan for our skb since there's no way
432 * to back-map them from the descriptor, and if we
433 * have several receive channels then they might not
434 * show up in the same order as they were put on the
438 dma = (dp->ptr & XCT_PTR_ADDR_M);
439 for (j = start; j < (start + RX_RING_SIZE); j++) {
440 info = &RX_DESC_INFO(mac, j);
441 if (info->dma == dma)
446 BUG_ON(info->dma != dma);
449 pci_unmap_single(mac->dma_pdev, info->dma, info->skb->len,
454 len = (dp->macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
456 struct sk_buff *new_skb =
457 netdev_alloc_skb(mac->netdev, len + NET_IP_ALIGN);
459 skb_reserve(new_skb, NET_IP_ALIGN);
460 memcpy(new_skb->data - NET_IP_ALIGN,
461 skb->data - NET_IP_ALIGN,
463 /* save the skb in buffer_info as good */
466 /* else just continue with the old one */
472 skb->protocol = eth_type_trans(skb, mac->netdev);
474 if ((dp->macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) {
475 skb->ip_summed = CHECKSUM_COMPLETE;
476 skb->csum = (dp->macrx & XCT_MACRX_CSUM_M) >>
479 skb->ip_summed = CHECKSUM_NONE;
481 mac->stats.rx_bytes += len;
482 mac->stats.rx_packets++;
484 netif_receive_skb(skb);
492 mac->rx->next_to_clean += count;
493 pasemi_mac_replenish_rx_ring(mac->netdev);
495 spin_unlock(&mac->rx->lock);
500 static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
503 struct pasemi_mac_buffer *info;
504 struct pas_dma_xct_descr *dp;
508 spin_lock_irqsave(&mac->tx->lock, flags);
510 start = mac->tx->next_to_clean;
513 for (i = start; i < mac->tx->next_to_use; i++) {
514 dp = &TX_DESC(mac, i);
515 if (!dp || (dp->mactx & XCT_MACTX_O))
520 info = &TX_DESC_INFO(mac, i);
522 pci_unmap_single(mac->dma_pdev, info->dma,
523 info->skb->len, PCI_DMA_TODEVICE);
524 dev_kfree_skb_irq(info->skb);
531 mac->tx->next_to_clean += count;
532 spin_unlock_irqrestore(&mac->tx->lock, flags);
534 netif_wake_queue(mac->netdev);
540 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
542 struct net_device *dev = data;
543 struct pasemi_mac *mac = netdev_priv(dev);
546 if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
549 if (*mac->rx_status & PAS_STATUS_ERROR)
550 printk("rx_status reported error\n");
552 /* Don't reset packet count so it won't fire again but clear
556 pci_read_config_dword(mac->dma_pdev, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), ®);
559 if (*mac->rx_status & PAS_STATUS_SOFT)
560 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
561 if (*mac->rx_status & PAS_STATUS_ERROR)
562 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
563 if (*mac->rx_status & PAS_STATUS_TIMER)
564 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
566 netif_rx_schedule(dev);
568 pci_write_config_dword(mac->iob_pdev,
569 PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
575 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
577 struct net_device *dev = data;
578 struct pasemi_mac *mac = netdev_priv(dev);
581 if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
584 pasemi_mac_clean_tx(mac);
586 reg = PAS_IOB_DMA_TXCH_RESET_PINTC;
588 if (*mac->tx_status & PAS_STATUS_SOFT)
589 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
590 if (*mac->tx_status & PAS_STATUS_ERROR)
591 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
593 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch),
599 static int pasemi_mac_open(struct net_device *dev)
601 struct pasemi_mac *mac = netdev_priv(dev);
606 /* enable rx section */
607 pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD,
608 PAS_DMA_COM_RXCMD_EN);
610 /* enable tx section */
611 pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD,
612 PAS_DMA_COM_TXCMD_EN);
614 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
615 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
616 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
618 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags);
620 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
621 PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
623 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
625 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
626 PAS_IOB_DMA_RXCH_CFG_CNTTH(1));
628 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
629 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
631 /* Clear out any residual packet count state from firmware */
632 pasemi_mac_restart_rx_intr(mac);
633 pasemi_mac_restart_tx_intr(mac);
635 /* 0xffffff is max value, about 16ms */
636 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
637 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
639 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
641 ret = pasemi_mac_setup_rx_resources(dev);
643 goto out_rx_resources;
645 ret = pasemi_mac_setup_tx_resources(dev);
647 goto out_tx_resources;
649 pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL,
650 PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
651 PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
654 pci_write_config_dword(mac->dma_pdev,
655 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
656 PAS_DMA_RXINT_RCMDSTA_EN);
658 /* enable rx channel */
659 pci_write_config_dword(mac->dma_pdev,
660 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
661 PAS_DMA_RXCHAN_CCMDSTA_EN |
662 PAS_DMA_RXCHAN_CCMDSTA_DU);
664 /* enable tx channel */
665 pci_write_config_dword(mac->dma_pdev,
666 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
667 PAS_DMA_TXCHAN_TCMDSTA_EN);
669 pasemi_mac_replenish_rx_ring(dev);
671 netif_start_queue(dev);
672 netif_poll_enable(dev);
674 /* Interrupts are a bit different for our DMA controller: While
675 * it's got one a regular PCI device header, the interrupt there
676 * is really the base of the range it's using. Each tx and rx
677 * channel has it's own interrupt source.
680 base_irq = virq_to_hw(mac->dma_pdev->irq);
682 mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
683 mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
685 ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
686 mac->tx->irq_name, dev);
688 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
689 base_irq + mac->dma_txch, ret);
693 ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
694 mac->rx->irq_name, dev);
696 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
697 base_irq + 20 + mac->dma_rxch, ret);
704 free_irq(mac->tx_irq, dev);
706 netif_poll_disable(dev);
707 netif_stop_queue(dev);
708 pasemi_mac_free_tx_resources(dev);
710 pasemi_mac_free_rx_resources(dev);
716 #define MAX_RETRIES 5000
718 static int pasemi_mac_close(struct net_device *dev)
720 struct pasemi_mac *mac = netdev_priv(dev);
724 netif_stop_queue(dev);
726 /* Clean out any pending buffers */
727 pasemi_mac_clean_tx(mac);
728 pasemi_mac_clean_rx(mac, RX_RING_SIZE);
730 /* Disable interface */
731 pci_write_config_dword(mac->dma_pdev,
732 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
733 PAS_DMA_TXCHAN_TCMDSTA_ST);
734 pci_write_config_dword(mac->dma_pdev,
735 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
736 PAS_DMA_RXINT_RCMDSTA_ST);
737 pci_write_config_dword(mac->dma_pdev,
738 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
739 PAS_DMA_RXCHAN_CCMDSTA_ST);
741 for (retries = 0; retries < MAX_RETRIES; retries++) {
742 pci_read_config_dword(mac->dma_pdev,
743 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
745 if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
750 if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
751 dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
753 for (retries = 0; retries < MAX_RETRIES; retries++) {
754 pci_read_config_dword(mac->dma_pdev,
755 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
757 if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
762 if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
763 dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
765 for (retries = 0; retries < MAX_RETRIES; retries++) {
766 pci_read_config_dword(mac->dma_pdev,
767 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
769 if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
774 if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
775 dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
777 /* Then, disable the channel. This must be done separately from
778 * stopping, since you can't disable when active.
781 pci_write_config_dword(mac->dma_pdev,
782 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
783 pci_write_config_dword(mac->dma_pdev,
784 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
785 pci_write_config_dword(mac->dma_pdev,
786 PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
788 free_irq(mac->tx_irq, dev);
789 free_irq(mac->rx_irq, dev);
792 pasemi_mac_free_rx_resources(dev);
793 pasemi_mac_free_tx_resources(dev);
798 static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
800 struct pasemi_mac *mac = netdev_priv(dev);
801 struct pasemi_mac_txring *txring;
802 struct pasemi_mac_buffer *info;
803 struct pas_dma_xct_descr *dp;
808 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
810 if (skb->ip_summed == CHECKSUM_PARTIAL) {
811 const unsigned char *nh = skb_network_header(skb);
813 switch (ip_hdr(skb)->protocol) {
815 dflags |= XCT_MACTX_CSUM_TCP;
816 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
817 dflags |= XCT_MACTX_IPO(nh - skb->data);
820 dflags |= XCT_MACTX_CSUM_UDP;
821 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
822 dflags |= XCT_MACTX_IPO(nh - skb->data);
827 map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
829 if (dma_mapping_error(map))
830 return NETDEV_TX_BUSY;
834 spin_lock_irqsave(&txring->lock, flags);
836 if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) {
837 spin_unlock_irqrestore(&txring->lock, flags);
838 pasemi_mac_clean_tx(mac);
839 spin_lock_irqsave(&txring->lock, flags);
841 if (txring->next_to_clean - txring->next_to_use ==
843 /* Still no room -- stop the queue and wait for tx
844 * intr when there's room.
846 netif_stop_queue(dev);
852 dp = &TX_DESC(mac, txring->next_to_use);
853 info = &TX_DESC_INFO(mac, txring->next_to_use);
855 dp->mactx = dflags | XCT_MACTX_LLEN(skb->len);
856 dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map);
860 txring->next_to_use++;
861 mac->stats.tx_packets++;
862 mac->stats.tx_bytes += skb->len;
864 spin_unlock_irqrestore(&txring->lock, flags);
866 pci_write_config_dword(mac->dma_pdev,
867 PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1);
872 spin_unlock_irqrestore(&txring->lock, flags);
873 pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE);
874 return NETDEV_TX_BUSY;
877 static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev)
879 struct pasemi_mac *mac = netdev_priv(dev);
884 static void pasemi_mac_set_rx_mode(struct net_device *dev)
886 struct pasemi_mac *mac = netdev_priv(dev);
889 pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
891 /* Set promiscuous */
892 if (dev->flags & IFF_PROMISC)
893 flags |= PAS_MAC_CFG_PCFG_PR;
895 flags &= ~PAS_MAC_CFG_PCFG_PR;
897 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
901 static int pasemi_mac_poll(struct net_device *dev, int *budget)
903 int pkts, limit = min(*budget, dev->quota);
904 struct pasemi_mac *mac = netdev_priv(dev);
906 pkts = pasemi_mac_clean_rx(mac, limit);
909 /* all done, no more packets present */
910 netif_rx_complete(dev);
912 pasemi_mac_restart_rx_intr(mac);
915 /* used up our quantum, so reschedule */
923 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
925 static int index = 0;
926 struct net_device *dev;
927 struct pasemi_mac *mac;
930 err = pci_enable_device(pdev);
934 dev = alloc_etherdev(sizeof(struct pasemi_mac));
937 "pasemi_mac: Could not allocate ethernet device.\n");
939 goto out_disable_device;
942 SET_MODULE_OWNER(dev);
943 pci_set_drvdata(pdev, dev);
944 SET_NETDEV_DEV(dev, &pdev->dev);
946 mac = netdev_priv(dev);
950 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
952 if (!mac->dma_pdev) {
953 dev_err(&pdev->dev, "Can't find DMA Controller\n");
955 goto out_free_netdev;
958 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
960 if (!mac->iob_pdev) {
961 dev_err(&pdev->dev, "Can't find I/O Bridge\n");
963 goto out_put_dma_pdev;
966 /* These should come out of the device tree eventually */
967 mac->dma_txch = index;
968 mac->dma_rxch = index;
970 /* We probe GMAC before XAUI, but the DMA interfaces are
971 * in XAUI, GMAC order.
974 mac->dma_if = index + 2;
976 mac->dma_if = index - 4;
979 switch (pdev->device) {
981 mac->type = MAC_TYPE_GMAC;
984 mac->type = MAC_TYPE_XAUI;
991 /* get mac addr from device tree */
992 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
996 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
998 dev->open = pasemi_mac_open;
999 dev->stop = pasemi_mac_close;
1000 dev->hard_start_xmit = pasemi_mac_start_tx;
1001 dev->get_stats = pasemi_mac_get_stats;
1002 dev->set_multicast_list = pasemi_mac_set_rx_mode;
1004 dev->poll = pasemi_mac_poll;
1005 dev->features = NETIF_F_HW_CSUM;
1007 /* The dma status structure is located in the I/O bridge, and
1008 * is cache coherent.
1011 /* XXXOJN This should come from the device tree */
1012 dma_status = __ioremap(0xfd800000, 0x1000, 0);
1014 mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
1015 mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
1017 err = register_netdev(dev);
1020 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1024 printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
1025 "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n",
1026 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1027 mac->dma_if, mac->dma_txch, mac->dma_rxch,
1028 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1029 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1034 pci_dev_put(mac->iob_pdev);
1036 pci_dev_put(mac->dma_pdev);
1040 pci_disable_device(pdev);
1045 static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
1047 struct net_device *netdev = pci_get_drvdata(pdev);
1048 struct pasemi_mac *mac;
1053 mac = netdev_priv(netdev);
1055 unregister_netdev(netdev);
1057 pci_disable_device(pdev);
1058 pci_dev_put(mac->dma_pdev);
1059 pci_dev_put(mac->iob_pdev);
1061 pci_set_drvdata(pdev, NULL);
1062 free_netdev(netdev);
1065 static struct pci_device_id pasemi_mac_pci_tbl[] = {
1066 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1070 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1072 static struct pci_driver pasemi_mac_driver = {
1073 .name = "pasemi_mac",
1074 .id_table = pasemi_mac_pci_tbl,
1075 .probe = pasemi_mac_probe,
1076 .remove = __devexit_p(pasemi_mac_remove),
1079 static void __exit pasemi_mac_cleanup_module(void)
1081 pci_unregister_driver(&pasemi_mac_driver);
1082 __iounmap(dma_status);
1086 int pasemi_mac_init_module(void)
1088 return pci_register_driver(&pasemi_mac_driver);
1091 MODULE_LICENSE("GPL");
1092 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
1093 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
1095 module_init(pasemi_mac_init_module);
1096 module_exit(pasemi_mac_cleanup_module);