SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/pci.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_ether.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/ip.h>
  22 #include <linux/in.h>
  23 #include <linux/ipv6.h>
  24 #include <linux/log2.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/crc32.h>
  27 #include <linux/list.h>
  28
  29 #include <linux/io.h>
  30
  31 #ifdef CONFIG_SPARC64
  32 #include <linux/of_device.h>
  33 #endif
  34
  35 #include "niu.h"
  36
  37 #define DRV_MODULE_NAME         "niu"
  38 #define DRV_MODULE_VERSION      "1.0"
  39 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  40
  41 static char version[] __devinitdata =
  42         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  43
  44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  45 MODULE_DESCRIPTION("NIU ethernet driver");
  46 MODULE_LICENSE("GPL");
  47 MODULE_VERSION(DRV_MODULE_VERSION);
  48
  49 #ifndef readq
  50 static u64 readq(void __iomem *reg)
  51 {
  52         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  53 }
  54
  55 static void writeq(u64 val, void __iomem *reg)
  56 {
  57         writel(val & 0xffffffff, reg);
  58         writel(val >> 32, reg + 0x4UL);
  59 }
  60 #endif
  61
  62 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
  63         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  64         {}
  65 };
  66
  67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  68
  69 #define NIU_TX_TIMEOUT                  (5 * HZ)
  70
  71 #define nr64(reg)               readq(np->regs + (reg))
  72 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  73
  74 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  75 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  76
  77 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  78 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  79
  80 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  81 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  82
  83 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  84 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  85
  86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  87
  88 static int niu_debug;
  89 static int debug = -1;
  90 module_param(debug, int, 0);
  91 MODULE_PARM_DESC(debug, "NIU debug level");
  92
  93 #define niu_lock_parent(np, flags) \
  94         spin_lock_irqsave(&np->parent->lock, flags)
  95 #define niu_unlock_parent(np, flags) \
  96         spin_unlock_irqrestore(&np->parent->lock, flags)
  97
  98 static int serdes_init_10g_serdes(struct niu *np);
  99
 100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 101                                      u64 bits, int limit, int delay)
 102 {
 103         while (--limit >= 0) {
 104                 u64 val = nr64_mac(reg);
 105
 106                 if (!(val & bits))
 107                         break;
 108                 udelay(delay);
 109         }
 110         if (limit < 0)
 111                 return -ENODEV;
 112         return 0;
 113 }
 114
 115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 116                                         u64 bits, int limit, int delay,
 117                                         const char *reg_name)
 118 {
 119         int err;
 120
 121         nw64_mac(reg, bits);
 122         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 123         if (err)
 124                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 125                            (unsigned long long)bits, reg_name,
 126                            (unsigned long long)nr64_mac(reg));
 127         return err;
 128 }
 129
 130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 131 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 132         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 133 })
 134
 135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 136                                      u64 bits, int limit, int delay)
 137 {
 138         while (--limit >= 0) {
 139                 u64 val = nr64_ipp(reg);
 140
 141                 if (!(val & bits))
 142                         break;
 143                 udelay(delay);
 144         }
 145         if (limit < 0)
 146                 return -ENODEV;
 147         return 0;
 148 }
 149
 150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 151                                         u64 bits, int limit, int delay,
 152                                         const char *reg_name)
 153 {
 154         int err;
 155         u64 val;
 156
 157         val = nr64_ipp(reg);
 158         val |= bits;
 159         nw64_ipp(reg, val);
 160
 161         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 162         if (err)
 163                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 164                            (unsigned long long)bits, reg_name,
 165                            (unsigned long long)nr64_ipp(reg));
 166         return err;
 167 }
 168
 169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 170 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 171         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 172 })
 173
 174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 175                                  u64 bits, int limit, int delay)
 176 {
 177         while (--limit >= 0) {
 178                 u64 val = nr64(reg);
 179
 180                 if (!(val & bits))
 181                         break;
 182                 udelay(delay);
 183         }
 184         if (limit < 0)
 185                 return -ENODEV;
 186         return 0;
 187 }
 188
 189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 190 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 191         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 192 })
 193
 194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 195                                     u64 bits, int limit, int delay,
 196                                     const char *reg_name)
 197 {
 198         int err;
 199
 200         nw64(reg, bits);
 201         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 202         if (err)
 203                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 204                            (unsigned long long)bits, reg_name,
 205                            (unsigned long long)nr64(reg));
 206         return err;
 207 }
 208
 209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 210 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 211         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 212 })
 213
 214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 215 {
 216         u64 val = (u64) lp->timer;
 217
 218         if (on)
 219                 val |= LDG_IMGMT_ARM;
 220
 221         nw64(LDG_IMGMT(lp->ldg_num), val);
 222 }
 223
 224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 225 {
 226         unsigned long mask_reg, bits;
 227         u64 val;
 228
 229         if (ldn < 0 || ldn > LDN_MAX)
 230                 return -EINVAL;
 231
 232         if (ldn < 64) {
 233                 mask_reg = LD_IM0(ldn);
 234                 bits = LD_IM0_MASK;
 235         } else {
 236                 mask_reg = LD_IM1(ldn - 64);
 237                 bits = LD_IM1_MASK;
 238         }
 239
 240         val = nr64(mask_reg);
 241         if (on)
 242                 val &= ~bits;
 243         else
 244                 val |= bits;
 245         nw64(mask_reg, val);
 246
 247         return 0;
 248 }
 249
 250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 251 {
 252         struct niu_parent *parent = np->parent;
 253         int i;
 254
 255         for (i = 0; i <= LDN_MAX; i++) {
 256                 int err;
 257
 258                 if (parent->ldg_map[i] != lp->ldg_num)
 259                         continue;
 260
 261                 err = niu_ldn_irq_enable(np, i, on);
 262                 if (err)
 263                         return err;
 264         }
 265         return 0;
 266 }
 267
 268 static int niu_enable_interrupts(struct niu *np, int on)
 269 {
 270         int i;
 271
 272         for (i = 0; i < np->num_ldg; i++) {
 273                 struct niu_ldg *lp = &np->ldg[i];
 274                 int err;
 275
 276                 err = niu_enable_ldn_in_ldg(np, lp, on);
 277                 if (err)
 278                         return err;
 279         }
 280         for (i = 0; i < np->num_ldg; i++)
 281                 niu_ldg_rearm(np, &np->ldg[i], on);
 282
 283         return 0;
 284 }
 285
 286 static u32 phy_encode(u32 type, int port)
 287 {
 288         return (type << (port * 2));
 289 }
 290
 291 static u32 phy_decode(u32 val, int port)
 292 {
 293         return (val >> (port * 2)) & PORT_TYPE_MASK;
 294 }
 295
 296 static int mdio_wait(struct niu *np)
 297 {
 298         int limit = 1000;
 299         u64 val;
 300
 301         while (--limit > 0) {
 302                 val = nr64(MIF_FRAME_OUTPUT);
 303                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 304                         return val & MIF_FRAME_OUTPUT_DATA;
 305
 306                 udelay(10);
 307         }
 308
 309         return -ENODEV;
 310 }
 311
 312 static int mdio_read(struct niu *np, int port, int dev, int reg)
 313 {
 314         int err;
 315
 316         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 317         err = mdio_wait(np);
 318         if (err < 0)
 319                 return err;
 320
 321         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 322         return mdio_wait(np);
 323 }
 324
 325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 326 {
 327         int err;
 328
 329         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 330         err = mdio_wait(np);
 331         if (err < 0)
 332                 return err;
 333
 334         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 335         err = mdio_wait(np);
 336         if (err < 0)
 337                 return err;
 338
 339         return 0;
 340 }
 341
 342 static int mii_read(struct niu *np, int port, int reg)
 343 {
 344         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 345         return mdio_wait(np);
 346 }
 347
 348 static int mii_write(struct niu *np, int port, int reg, int data)
 349 {
 350         int err;
 351
 352         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 353         err = mdio_wait(np);
 354         if (err < 0)
 355                 return err;
 356
 357         return 0;
 358 }
 359
 360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 361 {
 362         int err;
 363
 364         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 365                          ESR2_TI_PLL_TX_CFG_L(channel),
 366                          val & 0xffff);
 367         if (!err)
 368                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 369                                  ESR2_TI_PLL_TX_CFG_H(channel),
 370                                  val >> 16);
 371         return err;
 372 }
 373
 374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 375 {
 376         int err;
 377
 378         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 379                          ESR2_TI_PLL_RX_CFG_L(channel),
 380                          val & 0xffff);
 381         if (!err)
 382                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 383                                  ESR2_TI_PLL_RX_CFG_H(channel),
 384                                  val >> 16);
 385         return err;
 386 }
 387
 388 /* Mode is always 10G fiber.  */
 389 static int serdes_init_niu_10g_fiber(struct niu *np)
 390 {
 391         struct niu_link_config *lp = &np->link_config;
 392         u32 tx_cfg, rx_cfg;
 393         unsigned long i;
 394
 395         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 396         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 397                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 398                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 399
 400         if (lp->loopback_mode == LOOPBACK_PHY) {
 401                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 402
 403                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 404                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 405
 406                 tx_cfg |= PLL_TX_CFG_ENTEST;
 407                 rx_cfg |= PLL_RX_CFG_ENTEST;
 408         }
 409
 410         /* Initialize all 4 lanes of the SERDES.  */
 411         for (i = 0; i < 4; i++) {
 412                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 413                 if (err)
 414                         return err;
 415         }
 416
 417         for (i = 0; i < 4; i++) {
 418                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 419                 if (err)
 420                         return err;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int serdes_init_niu_1g_serdes(struct niu *np)
 427 {
 428         struct niu_link_config *lp = &np->link_config;
 429         u16 pll_cfg, pll_sts;
 430         int max_retry = 100;
 431         u64 uninitialized_var(sig), mask, val;
 432         u32 tx_cfg, rx_cfg;
 433         unsigned long i;
 434         int err;
 435
 436         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 437                   PLL_TX_CFG_RATE_HALF);
 438         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 439                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 440                   PLL_RX_CFG_RATE_HALF);
 441
 442         if (np->port == 0)
 443                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 444
 445         if (lp->loopback_mode == LOOPBACK_PHY) {
 446                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 447
 448                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 449                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 450
 451                 tx_cfg |= PLL_TX_CFG_ENTEST;
 452                 rx_cfg |= PLL_RX_CFG_ENTEST;
 453         }
 454
 455         /* Initialize PLL for 1G */
 456         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 457
 458         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 459                          ESR2_TI_PLL_CFG_L, pll_cfg);
 460         if (err) {
 461                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 462                            np->port, __func__);
 463                 return err;
 464         }
 465
 466         pll_sts = PLL_CFG_ENPLL;
 467
 468         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                          ESR2_TI_PLL_STS_L, pll_sts);
 470         if (err) {
 471                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 472                            np->port, __func__);
 473                 return err;
 474         }
 475
 476         udelay(200);
 477
 478         /* Initialize all 4 lanes of the SERDES.  */
 479         for (i = 0; i < 4; i++) {
 480                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 481                 if (err)
 482                         return err;
 483         }
 484
 485         for (i = 0; i < 4; i++) {
 486                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 487                 if (err)
 488                         return err;
 489         }
 490
 491         switch (np->port) {
 492         case 0:
 493                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 494                 mask = val;
 495                 break;
 496
 497         case 1:
 498                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 499                 mask = val;
 500                 break;
 501
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         while (max_retry--) {
 507                 sig = nr64(ESR_INT_SIGNALS);
 508                 if ((sig & mask) == val)
 509                         break;
 510
 511                 mdelay(500);
 512         }
 513
 514         if ((sig & mask) != val) {
 515                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 516                            np->port, (int)(sig & mask), (int)val);
 517                 return -ENODEV;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int serdes_init_niu_10g_serdes(struct niu *np)
 524 {
 525         struct niu_link_config *lp = &np->link_config;
 526         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 527         int max_retry = 100;
 528         u64 uninitialized_var(sig), mask, val;
 529         unsigned long i;
 530         int err;
 531
 532         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 533         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 534                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 535                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 536
 537         if (lp->loopback_mode == LOOPBACK_PHY) {
 538                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 539
 540                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 541                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 542
 543                 tx_cfg |= PLL_TX_CFG_ENTEST;
 544                 rx_cfg |= PLL_RX_CFG_ENTEST;
 545         }
 546
 547         /* Initialize PLL for 10G */
 548         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 549
 550         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 551                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 552         if (err) {
 553                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 554                            np->port, __func__);
 555                 return err;
 556         }
 557
 558         pll_sts = PLL_CFG_ENPLL;
 559
 560         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 561                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 562         if (err) {
 563                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 564                            np->port, __func__);
 565                 return err;
 566         }
 567
 568         udelay(200);
 569
 570         /* Initialize all 4 lanes of the SERDES.  */
 571         for (i = 0; i < 4; i++) {
 572                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 573                 if (err)
 574                         return err;
 575         }
 576
 577         for (i = 0; i < 4; i++) {
 578                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 579                 if (err)
 580                         return err;
 581         }
 582
 583         /* check if serdes is ready */
 584
 585         switch (np->port) {
 586         case 0:
 587                 mask = ESR_INT_SIGNALS_P0_BITS;
 588                 val = (ESR_INT_SRDY0_P0 |
 589                        ESR_INT_DET0_P0 |
 590                        ESR_INT_XSRDY_P0 |
 591                        ESR_INT_XDP_P0_CH3 |
 592                        ESR_INT_XDP_P0_CH2 |
 593                        ESR_INT_XDP_P0_CH1 |
 594                        ESR_INT_XDP_P0_CH0);
 595                 break;
 596
 597         case 1:
 598                 mask = ESR_INT_SIGNALS_P1_BITS;
 599                 val = (ESR_INT_SRDY0_P1 |
 600                        ESR_INT_DET0_P1 |
 601                        ESR_INT_XSRDY_P1 |
 602                        ESR_INT_XDP_P1_CH3 |
 603                        ESR_INT_XDP_P1_CH2 |
 604                        ESR_INT_XDP_P1_CH1 |
 605                        ESR_INT_XDP_P1_CH0);
 606                 break;
 607
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         while (max_retry--) {
 613                 sig = nr64(ESR_INT_SIGNALS);
 614                 if ((sig & mask) == val)
 615                         break;
 616
 617                 mdelay(500);
 618         }
 619
 620         if ((sig & mask) != val) {
 621                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
 622                         np->port, (int)(sig & mask), (int)val);
 623
 624                 /* 10G failed, try initializing at 1G */
 625                 err = serdes_init_niu_1g_serdes(np);
 626                 if (!err) {
 627                         np->flags &= ~NIU_FLAGS_10G;
 628                         np->mac_xcvr = MAC_XCVR_PCS;
 629                 }  else {
 630                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
 631                                    np->port);
 632                         return -ENODEV;
 633                 }
 634         }
 635         return 0;
 636 }
 637
 638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 639 {
 640         int err;
 641
 642         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 643         if (err >= 0) {
 644                 *val = (err & 0xffff);
 645                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 646                                 ESR_RXTX_CTRL_H(chan));
 647                 if (err >= 0)
 648                         *val |= ((err & 0xffff) << 16);
 649                 err = 0;
 650         }
 651         return err;
 652 }
 653
 654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 655 {
 656         int err;
 657
 658         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 659                         ESR_GLUE_CTRL0_L(chan));
 660         if (err >= 0) {
 661                 *val = (err & 0xffff);
 662                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 663                                 ESR_GLUE_CTRL0_H(chan));
 664                 if (err >= 0) {
 665                         *val |= ((err & 0xffff) << 16);
 666                         err = 0;
 667                 }
 668         }
 669         return err;
 670 }
 671
 672 static int esr_read_reset(struct niu *np, u32 *val)
 673 {
 674         int err;
 675
 676         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 677                         ESR_RXTX_RESET_CTRL_L);
 678         if (err >= 0) {
 679                 *val = (err & 0xffff);
 680                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 681                                 ESR_RXTX_RESET_CTRL_H);
 682                 if (err >= 0) {
 683                         *val |= ((err & 0xffff) << 16);
 684                         err = 0;
 685                 }
 686         }
 687         return err;
 688 }
 689
 690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 691 {
 692         int err;
 693
 694         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 695                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 696         if (!err)
 697                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 698                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 699         return err;
 700 }
 701
 702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 703 {
 704         int err;
 705
 706         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 707                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 708         if (!err)
 709                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 710                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 711         return err;
 712 }
 713
 714 static int esr_reset(struct niu *np)
 715 {
 716         u32 uninitialized_var(reset);
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 721         if (err)
 722                 return err;
 723         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 724                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 725         if (err)
 726                 return err;
 727         udelay(200);
 728
 729         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 730                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 731         if (err)
 732                 return err;
 733         udelay(200);
 734
 735         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 736                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 737         if (err)
 738                 return err;
 739         udelay(200);
 740
 741         err = esr_read_reset(np, &reset);
 742         if (err)
 743                 return err;
 744         if (reset != 0) {
 745                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
 746                            np->port, reset);
 747                 return -ENODEV;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int serdes_init_10g(struct niu *np)
 754 {
 755         struct niu_link_config *lp = &np->link_config;
 756         unsigned long ctrl_reg, test_cfg_reg, i;
 757         u64 ctrl_val, test_cfg_val, sig, mask, val;
 758         int err;
 759
 760         switch (np->port) {
 761         case 0:
 762                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 763                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 764                 break;
 765         case 1:
 766                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 767                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 768                 break;
 769
 770         default:
 771                 return -EINVAL;
 772         }
 773         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 774                     ENET_SERDES_CTRL_SDET_1 |
 775                     ENET_SERDES_CTRL_SDET_2 |
 776                     ENET_SERDES_CTRL_SDET_3 |
 777                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 778                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 779                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 780                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 781                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 782                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 783                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 784                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 785         test_cfg_val = 0;
 786
 787         if (lp->loopback_mode == LOOPBACK_PHY) {
 788                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 789                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 790                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 791                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 792                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 793                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 794                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 795                                   ENET_SERDES_TEST_MD_3_SHIFT));
 796         }
 797
 798         nw64(ctrl_reg, ctrl_val);
 799         nw64(test_cfg_reg, test_cfg_val);
 800
 801         /* Initialize all 4 lanes of the SERDES.  */
 802         for (i = 0; i < 4; i++) {
 803                 u32 rxtx_ctrl, glue0;
 804
 805                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 806                 if (err)
 807                         return err;
 808                 err = esr_read_glue0(np, i, &glue0);
 809                 if (err)
 810                         return err;
 811
 812                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 813                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 814                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 815
 816                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 817                            ESR_GLUE_CTRL0_THCNT |
 818                            ESR_GLUE_CTRL0_BLTIME);
 819                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 820                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 821                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 822                           (BLTIME_300_CYCLES <<
 823                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 824
 825                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 826                 if (err)
 827                         return err;
 828                 err = esr_write_glue0(np, i, glue0);
 829                 if (err)
 830                         return err;
 831         }
 832
 833         err = esr_reset(np);
 834         if (err)
 835                 return err;
 836
 837         sig = nr64(ESR_INT_SIGNALS);
 838         switch (np->port) {
 839         case 0:
 840                 mask = ESR_INT_SIGNALS_P0_BITS;
 841                 val = (ESR_INT_SRDY0_P0 |
 842                        ESR_INT_DET0_P0 |
 843                        ESR_INT_XSRDY_P0 |
 844                        ESR_INT_XDP_P0_CH3 |
 845                        ESR_INT_XDP_P0_CH2 |
 846                        ESR_INT_XDP_P0_CH1 |
 847                        ESR_INT_XDP_P0_CH0);
 848                 break;
 849
 850         case 1:
 851                 mask = ESR_INT_SIGNALS_P1_BITS;
 852                 val = (ESR_INT_SRDY0_P1 |
 853                        ESR_INT_DET0_P1 |
 854                        ESR_INT_XSRDY_P1 |
 855                        ESR_INT_XDP_P1_CH3 |
 856                        ESR_INT_XDP_P1_CH2 |
 857                        ESR_INT_XDP_P1_CH1 |
 858                        ESR_INT_XDP_P1_CH0);
 859                 break;
 860
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         if ((sig & mask) != val) {
 866                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 867                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 868                         return 0;
 869                 }
 870                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 871                            np->port, (int)(sig & mask), (int)val);
 872                 return -ENODEV;
 873         }
 874         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 875                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 876         return 0;
 877 }
 878
 879 static int serdes_init_1g(struct niu *np)
 880 {
 881         u64 val;
 882
 883         val = nr64(ENET_SERDES_1_PLL_CFG);
 884         val &= ~ENET_SERDES_PLL_FBDIV2;
 885         switch (np->port) {
 886         case 0:
 887                 val |= ENET_SERDES_PLL_HRATE0;
 888                 break;
 889         case 1:
 890                 val |= ENET_SERDES_PLL_HRATE1;
 891                 break;
 892         case 2:
 893                 val |= ENET_SERDES_PLL_HRATE2;
 894                 break;
 895         case 3:
 896                 val |= ENET_SERDES_PLL_HRATE3;
 897                 break;
 898         default:
 899                 return -EINVAL;
 900         }
 901         nw64(ENET_SERDES_1_PLL_CFG, val);
 902
 903         return 0;
 904 }
 905
 906 static int serdes_init_1g_serdes(struct niu *np)
 907 {
 908         struct niu_link_config *lp = &np->link_config;
 909         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 910         u64 ctrl_val, test_cfg_val, sig, mask, val;
 911         int err;
 912         u64 reset_val, val_rd;
 913
 914         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 915                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 916                 ENET_SERDES_PLL_FBDIV0;
 917         switch (np->port) {
 918         case 0:
 919                 reset_val =  ENET_SERDES_RESET_0;
 920                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 921                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 922                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 923                 break;
 924         case 1:
 925                 reset_val =  ENET_SERDES_RESET_1;
 926                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 927                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 928                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 929                 break;
 930
 931         default:
 932                 return -EINVAL;
 933         }
 934         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 935                     ENET_SERDES_CTRL_SDET_1 |
 936                     ENET_SERDES_CTRL_SDET_2 |
 937                     ENET_SERDES_CTRL_SDET_3 |
 938                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 939                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 940                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 941                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 942                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 943                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 944                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 945                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 946         test_cfg_val = 0;
 947
 948         if (lp->loopback_mode == LOOPBACK_PHY) {
 949                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 950                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 951                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 952                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 953                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 954                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 955                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 956                                   ENET_SERDES_TEST_MD_3_SHIFT));
 957         }
 958
 959         nw64(ENET_SERDES_RESET, reset_val);
 960         mdelay(20);
 961         val_rd = nr64(ENET_SERDES_RESET);
 962         val_rd &= ~reset_val;
 963         nw64(pll_cfg, val);
 964         nw64(ctrl_reg, ctrl_val);
 965         nw64(test_cfg_reg, test_cfg_val);
 966         nw64(ENET_SERDES_RESET, val_rd);
 967         mdelay(2000);
 968
 969         /* Initialize all 4 lanes of the SERDES.  */
 970         for (i = 0; i < 4; i++) {
 971                 u32 rxtx_ctrl, glue0;
 972
 973                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 974                 if (err)
 975                         return err;
 976                 err = esr_read_glue0(np, i, &glue0);
 977                 if (err)
 978                         return err;
 979
 980                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 981                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 982                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 983
 984                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 985                            ESR_GLUE_CTRL0_THCNT |
 986                            ESR_GLUE_CTRL0_BLTIME);
 987                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 988                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 989                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 990                           (BLTIME_300_CYCLES <<
 991                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 992
 993                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 994                 if (err)
 995                         return err;
 996                 err = esr_write_glue0(np, i, glue0);
 997                 if (err)
 998                         return err;
 999         }
1000
1001
1002         sig = nr64(ESR_INT_SIGNALS);
1003         switch (np->port) {
1004         case 0:
1005                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1006                 mask = val;
1007                 break;
1008
1009         case 1:
1010                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1011                 mask = val;
1012                 break;
1013
1014         default:
1015                 return -EINVAL;
1016         }
1017
1018         if ((sig & mask) != val) {
1019                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020                            np->port, (int)(sig & mask), (int)val);
1021                 return -ENODEV;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028 {
1029         struct niu_link_config *lp = &np->link_config;
1030         int link_up;
1031         u64 val;
1032         u16 current_speed;
1033         unsigned long flags;
1034         u8 current_duplex;
1035
1036         link_up = 0;
1037         current_speed = SPEED_INVALID;
1038         current_duplex = DUPLEX_INVALID;
1039
1040         spin_lock_irqsave(&np->lock, flags);
1041
1042         val = nr64_pcs(PCS_MII_STAT);
1043
1044         if (val & PCS_MII_STAT_LINK_STATUS) {
1045                 link_up = 1;
1046                 current_speed = SPEED_1000;
1047                 current_duplex = DUPLEX_FULL;
1048         }
1049
1050         lp->active_speed = current_speed;
1051         lp->active_duplex = current_duplex;
1052         spin_unlock_irqrestore(&np->lock, flags);
1053
1054         *link_up_p = link_up;
1055         return 0;
1056 }
1057
1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059 {
1060         unsigned long flags;
1061         struct niu_link_config *lp = &np->link_config;
1062         int link_up = 0;
1063         int link_ok = 1;
1064         u64 val, val2;
1065         u16 current_speed;
1066         u8 current_duplex;
1067
1068         if (!(np->flags & NIU_FLAGS_10G))
1069                 return link_status_1g_serdes(np, link_up_p);
1070
1071         current_speed = SPEED_INVALID;
1072         current_duplex = DUPLEX_INVALID;
1073         spin_lock_irqsave(&np->lock, flags);
1074
1075         val = nr64_xpcs(XPCS_STATUS(0));
1076         val2 = nr64_mac(XMAC_INTER2);
1077         if (val2 & 0x01000000)
1078                 link_ok = 0;
1079
1080         if ((val & 0x1000ULL) && link_ok) {
1081                 link_up = 1;
1082                 current_speed = SPEED_10000;
1083                 current_duplex = DUPLEX_FULL;
1084         }
1085         lp->active_speed = current_speed;
1086         lp->active_duplex = current_duplex;
1087         spin_unlock_irqrestore(&np->lock, flags);
1088         *link_up_p = link_up;
1089         return 0;
1090 }
1091
1092 static int link_status_mii(struct niu *np, int *link_up_p)
1093 {
1094         struct niu_link_config *lp = &np->link_config;
1095         int err;
1096         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097         int supported, advertising, active_speed, active_duplex;
1098
1099         err = mii_read(np, np->phy_addr, MII_BMCR);
1100         if (unlikely(err < 0))
1101                 return err;
1102         bmcr = err;
1103
1104         err = mii_read(np, np->phy_addr, MII_BMSR);
1105         if (unlikely(err < 0))
1106                 return err;
1107         bmsr = err;
1108
1109         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110         if (unlikely(err < 0))
1111                 return err;
1112         advert = err;
1113
1114         err = mii_read(np, np->phy_addr, MII_LPA);
1115         if (unlikely(err < 0))
1116                 return err;
1117         lpa = err;
1118
1119         if (likely(bmsr & BMSR_ESTATEN)) {
1120                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121                 if (unlikely(err < 0))
1122                         return err;
1123                 estatus = err;
1124
1125                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126                 if (unlikely(err < 0))
1127                         return err;
1128                 ctrl1000 = err;
1129
1130                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131                 if (unlikely(err < 0))
1132                         return err;
1133                 stat1000 = err;
1134         } else
1135                 estatus = ctrl1000 = stat1000 = 0;
1136
1137         supported = 0;
1138         if (bmsr & BMSR_ANEGCAPABLE)
1139                 supported |= SUPPORTED_Autoneg;
1140         if (bmsr & BMSR_10HALF)
1141                 supported |= SUPPORTED_10baseT_Half;
1142         if (bmsr & BMSR_10FULL)
1143                 supported |= SUPPORTED_10baseT_Full;
1144         if (bmsr & BMSR_100HALF)
1145                 supported |= SUPPORTED_100baseT_Half;
1146         if (bmsr & BMSR_100FULL)
1147                 supported |= SUPPORTED_100baseT_Full;
1148         if (estatus & ESTATUS_1000_THALF)
1149                 supported |= SUPPORTED_1000baseT_Half;
1150         if (estatus & ESTATUS_1000_TFULL)
1151                 supported |= SUPPORTED_1000baseT_Full;
1152         lp->supported = supported;
1153
1154         advertising = 0;
1155         if (advert & ADVERTISE_10HALF)
1156                 advertising |= ADVERTISED_10baseT_Half;
1157         if (advert & ADVERTISE_10FULL)
1158                 advertising |= ADVERTISED_10baseT_Full;
1159         if (advert & ADVERTISE_100HALF)
1160                 advertising |= ADVERTISED_100baseT_Half;
1161         if (advert & ADVERTISE_100FULL)
1162                 advertising |= ADVERTISED_100baseT_Full;
1163         if (ctrl1000 & ADVERTISE_1000HALF)
1164                 advertising |= ADVERTISED_1000baseT_Half;
1165         if (ctrl1000 & ADVERTISE_1000FULL)
1166                 advertising |= ADVERTISED_1000baseT_Full;
1167
1168         if (bmcr & BMCR_ANENABLE) {
1169                 int neg, neg1000;
1170
1171                 lp->active_autoneg = 1;
1172                 advertising |= ADVERTISED_Autoneg;
1173
1174                 neg = advert & lpa;
1175                 neg1000 = (ctrl1000 << 2) & stat1000;
1176
1177                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1178                         active_speed = SPEED_1000;
1179                 else if (neg & LPA_100)
1180                         active_speed = SPEED_100;
1181                 else if (neg & (LPA_10HALF | LPA_10FULL))
1182                         active_speed = SPEED_10;
1183                 else
1184                         active_speed = SPEED_INVALID;
1185
1186                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1187                         active_duplex = DUPLEX_FULL;
1188                 else if (active_speed != SPEED_INVALID)
1189                         active_duplex = DUPLEX_HALF;
1190                 else
1191                         active_duplex = DUPLEX_INVALID;
1192         } else {
1193                 lp->active_autoneg = 0;
1194
1195                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1196                         active_speed = SPEED_1000;
1197                 else if (bmcr & BMCR_SPEED100)
1198                         active_speed = SPEED_100;
1199                 else
1200                         active_speed = SPEED_10;
1201
1202                 if (bmcr & BMCR_FULLDPLX)
1203                         active_duplex = DUPLEX_FULL;
1204                 else
1205                         active_duplex = DUPLEX_HALF;
1206         }
1207
1208         lp->active_advertising = advertising;
1209         lp->active_speed = active_speed;
1210         lp->active_duplex = active_duplex;
1211         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1212
1213         return 0;
1214 }
1215
1216 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1217 {
1218         struct niu_link_config *lp = &np->link_config;
1219         u16 current_speed, bmsr;
1220         unsigned long flags;
1221         u8 current_duplex;
1222         int err, link_up;
1223
1224         link_up = 0;
1225         current_speed = SPEED_INVALID;
1226         current_duplex = DUPLEX_INVALID;
1227
1228         spin_lock_irqsave(&np->lock, flags);
1229
1230         err = -EINVAL;
1231
1232         err = mii_read(np, np->phy_addr, MII_BMSR);
1233         if (err < 0)
1234                 goto out;
1235
1236         bmsr = err;
1237         if (bmsr & BMSR_LSTATUS) {
1238                 u16 adv, lpa, common, estat;
1239
1240                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1241                 if (err < 0)
1242                         goto out;
1243                 adv = err;
1244
1245                 err = mii_read(np, np->phy_addr, MII_LPA);
1246                 if (err < 0)
1247                         goto out;
1248                 lpa = err;
1249
1250                 common = adv & lpa;
1251
1252                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1253                 if (err < 0)
1254                         goto out;
1255                 estat = err;
1256                 link_up = 1;
1257                 current_speed = SPEED_1000;
1258                 current_duplex = DUPLEX_FULL;
1259
1260         }
1261         lp->active_speed = current_speed;
1262         lp->active_duplex = current_duplex;
1263         err = 0;
1264
1265 out:
1266         spin_unlock_irqrestore(&np->lock, flags);
1267
1268         *link_up_p = link_up;
1269         return err;
1270 }
1271
1272 static int link_status_1g(struct niu *np, int *link_up_p)
1273 {
1274         struct niu_link_config *lp = &np->link_config;
1275         unsigned long flags;
1276         int err;
1277
1278         spin_lock_irqsave(&np->lock, flags);
1279
1280         err = link_status_mii(np, link_up_p);
1281         lp->supported |= SUPPORTED_TP;
1282         lp->active_advertising |= ADVERTISED_TP;
1283
1284         spin_unlock_irqrestore(&np->lock, flags);
1285         return err;
1286 }
1287
1288 static int bcm8704_reset(struct niu *np)
1289 {
1290         int err, limit;
1291
1292         err = mdio_read(np, np->phy_addr,
1293                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1294         if (err < 0 || err == 0xffff)
1295                 return err;
1296         err |= BMCR_RESET;
1297         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1298                          MII_BMCR, err);
1299         if (err)
1300                 return err;
1301
1302         limit = 1000;
1303         while (--limit >= 0) {
1304                 err = mdio_read(np, np->phy_addr,
1305                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1306                 if (err < 0)
1307                         return err;
1308                 if (!(err & BMCR_RESET))
1309                         break;
1310         }
1311         if (limit < 0) {
1312                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1313                            np->port, (err & 0xffff));
1314                 return -ENODEV;
1315         }
1316         return 0;
1317 }
1318
1319 /* When written, certain PHY registers need to be read back twice
1320  * in order for the bits to settle properly.
1321  */
1322 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1323 {
1324         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1325         if (err < 0)
1326                 return err;
1327         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1328         if (err < 0)
1329                 return err;
1330         return 0;
1331 }
1332
1333 static int bcm8706_init_user_dev3(struct niu *np)
1334 {
1335         int err;
1336
1337
1338         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1339                         BCM8704_USER_OPT_DIGITAL_CTRL);
1340         if (err < 0)
1341                 return err;
1342         err &= ~USER_ODIG_CTRL_GPIOS;
1343         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1344         err |=  USER_ODIG_CTRL_RESV2;
1345         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1346                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1347         if (err)
1348                 return err;
1349
1350         mdelay(1000);
1351
1352         return 0;
1353 }
1354
1355 static int bcm8704_init_user_dev3(struct niu *np)
1356 {
1357         int err;
1358
1359         err = mdio_write(np, np->phy_addr,
1360                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1361                          (USER_CONTROL_OPTXRST_LVL |
1362                           USER_CONTROL_OPBIASFLT_LVL |
1363                           USER_CONTROL_OBTMPFLT_LVL |
1364                           USER_CONTROL_OPPRFLT_LVL |
1365                           USER_CONTROL_OPTXFLT_LVL |
1366                           USER_CONTROL_OPRXLOS_LVL |
1367                           USER_CONTROL_OPRXFLT_LVL |
1368                           USER_CONTROL_OPTXON_LVL |
1369                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1370         if (err)
1371                 return err;
1372
1373         err = mdio_write(np, np->phy_addr,
1374                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1375                          (USER_PMD_TX_CTL_XFP_CLKEN |
1376                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1377                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1378                           USER_PMD_TX_CTL_TSCK_LPWREN));
1379         if (err)
1380                 return err;
1381
1382         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1383         if (err)
1384                 return err;
1385         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1386         if (err)
1387                 return err;
1388
1389         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1390                         BCM8704_USER_OPT_DIGITAL_CTRL);
1391         if (err < 0)
1392                 return err;
1393         err &= ~USER_ODIG_CTRL_GPIOS;
1394         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1395         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1396                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1397         if (err)
1398                 return err;
1399
1400         mdelay(1000);
1401
1402         return 0;
1403 }
1404
1405 static int mrvl88x2011_act_led(struct niu *np, int val)
1406 {
1407         int     err;
1408
1409         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1410                 MRVL88X2011_LED_8_TO_11_CTL);
1411         if (err < 0)
1412                 return err;
1413
1414         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1415         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1416
1417         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1418                           MRVL88X2011_LED_8_TO_11_CTL, err);
1419 }
1420
1421 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1422 {
1423         int     err;
1424
1425         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1426                         MRVL88X2011_LED_BLINK_CTL);
1427         if (err >= 0) {
1428                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1429                 err |= (rate << 4);
1430
1431                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1432                                  MRVL88X2011_LED_BLINK_CTL, err);
1433         }
1434
1435         return err;
1436 }
1437
1438 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1439 {
1440         int     err;
1441
1442         /* Set LED functions */
1443         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1444         if (err)
1445                 return err;
1446
1447         /* led activity */
1448         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1449         if (err)
1450                 return err;
1451
1452         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1453                         MRVL88X2011_GENERAL_CTL);
1454         if (err < 0)
1455                 return err;
1456
1457         err |= MRVL88X2011_ENA_XFPREFCLK;
1458
1459         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1460                          MRVL88X2011_GENERAL_CTL, err);
1461         if (err < 0)
1462                 return err;
1463
1464         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1465                         MRVL88X2011_PMA_PMD_CTL_1);
1466         if (err < 0)
1467                 return err;
1468
1469         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1470                 err |= MRVL88X2011_LOOPBACK;
1471         else
1472                 err &= ~MRVL88X2011_LOOPBACK;
1473
1474         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1475                          MRVL88X2011_PMA_PMD_CTL_1, err);
1476         if (err < 0)
1477                 return err;
1478
1479         /* Enable PMD  */
1480         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1481                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1482 }
1483
1484
1485 static int xcvr_diag_bcm870x(struct niu *np)
1486 {
1487         u16 analog_stat0, tx_alarm_status;
1488         int err = 0;
1489
1490 #if 1
1491         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1492                         MII_STAT1000);
1493         if (err < 0)
1494                 return err;
1495         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1496
1497         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1498         if (err < 0)
1499                 return err;
1500         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1501
1502         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1503                         MII_NWAYTEST);
1504         if (err < 0)
1505                 return err;
1506         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1507 #endif
1508
1509         /* XXX dig this out it might not be so useful XXX */
1510         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511                         BCM8704_USER_ANALOG_STATUS0);
1512         if (err < 0)
1513                 return err;
1514         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1515                         BCM8704_USER_ANALOG_STATUS0);
1516         if (err < 0)
1517                 return err;
1518         analog_stat0 = err;
1519
1520         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1521                         BCM8704_USER_TX_ALARM_STATUS);
1522         if (err < 0)
1523                 return err;
1524         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1525                         BCM8704_USER_TX_ALARM_STATUS);
1526         if (err < 0)
1527                 return err;
1528         tx_alarm_status = err;
1529
1530         if (analog_stat0 != 0x03fc) {
1531                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1532                         pr_info("Port %u cable not connected or bad cable\n",
1533                                 np->port);
1534                 } else if (analog_stat0 == 0x639c) {
1535                         pr_info("Port %u optical module is bad or missing\n",
1536                                 np->port);
1537                 }
1538         }
1539
1540         return 0;
1541 }
1542
1543 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1544 {
1545         struct niu_link_config *lp = &np->link_config;
1546         int err;
1547
1548         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1549                         MII_BMCR);
1550         if (err < 0)
1551                 return err;
1552
1553         err &= ~BMCR_LOOPBACK;
1554
1555         if (lp->loopback_mode == LOOPBACK_MAC)
1556                 err |= BMCR_LOOPBACK;
1557
1558         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1559                          MII_BMCR, err);
1560         if (err)
1561                 return err;
1562
1563         return 0;
1564 }
1565
1566 static int xcvr_init_10g_bcm8706(struct niu *np)
1567 {
1568         int err = 0;
1569         u64 val;
1570
1571         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1572             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1573                         return err;
1574
1575         val = nr64_mac(XMAC_CONFIG);
1576         val &= ~XMAC_CONFIG_LED_POLARITY;
1577         val |= XMAC_CONFIG_FORCE_LED_ON;
1578         nw64_mac(XMAC_CONFIG, val);
1579
1580         val = nr64(MIF_CONFIG);
1581         val |= MIF_CONFIG_INDIRECT_MODE;
1582         nw64(MIF_CONFIG, val);
1583
1584         err = bcm8704_reset(np);
1585         if (err)
1586                 return err;
1587
1588         err = xcvr_10g_set_lb_bcm870x(np);
1589         if (err)
1590                 return err;
1591
1592         err = bcm8706_init_user_dev3(np);
1593         if (err)
1594                 return err;
1595
1596         err = xcvr_diag_bcm870x(np);
1597         if (err)
1598                 return err;
1599
1600         return 0;
1601 }
1602
1603 static int xcvr_init_10g_bcm8704(struct niu *np)
1604 {
1605         int err;
1606
1607         err = bcm8704_reset(np);
1608         if (err)
1609                 return err;
1610
1611         err = bcm8704_init_user_dev3(np);
1612         if (err)
1613                 return err;
1614
1615         err = xcvr_10g_set_lb_bcm870x(np);
1616         if (err)
1617                 return err;
1618
1619         err =  xcvr_diag_bcm870x(np);
1620         if (err)
1621                 return err;
1622
1623         return 0;
1624 }
1625
1626 static int xcvr_init_10g(struct niu *np)
1627 {
1628         int phy_id, err;
1629         u64 val;
1630
1631         val = nr64_mac(XMAC_CONFIG);
1632         val &= ~XMAC_CONFIG_LED_POLARITY;
1633         val |= XMAC_CONFIG_FORCE_LED_ON;
1634         nw64_mac(XMAC_CONFIG, val);
1635
1636         /* XXX shared resource, lock parent XXX */
1637         val = nr64(MIF_CONFIG);
1638         val |= MIF_CONFIG_INDIRECT_MODE;
1639         nw64(MIF_CONFIG, val);
1640
1641         phy_id = phy_decode(np->parent->port_phy, np->port);
1642         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1643
1644         /* handle different phy types */
1645         switch (phy_id & NIU_PHY_ID_MASK) {
1646         case NIU_PHY_ID_MRVL88X2011:
1647                 err = xcvr_init_10g_mrvl88x2011(np);
1648                 break;
1649
1650         default: /* bcom 8704 */
1651                 err = xcvr_init_10g_bcm8704(np);
1652                 break;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int mii_reset(struct niu *np)
1659 {
1660         int limit, err;
1661
1662         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1663         if (err)
1664                 return err;
1665
1666         limit = 1000;
1667         while (--limit >= 0) {
1668                 udelay(500);
1669                 err = mii_read(np, np->phy_addr, MII_BMCR);
1670                 if (err < 0)
1671                         return err;
1672                 if (!(err & BMCR_RESET))
1673                         break;
1674         }
1675         if (limit < 0) {
1676                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1677                            np->port, err);
1678                 return -ENODEV;
1679         }
1680
1681         return 0;
1682 }
1683
1684 static int xcvr_init_1g_rgmii(struct niu *np)
1685 {
1686         int err;
1687         u64 val;
1688         u16 bmcr, bmsr, estat;
1689
1690         val = nr64(MIF_CONFIG);
1691         val &= ~MIF_CONFIG_INDIRECT_MODE;
1692         nw64(MIF_CONFIG, val);
1693
1694         err = mii_reset(np);
1695         if (err)
1696                 return err;
1697
1698         err = mii_read(np, np->phy_addr, MII_BMSR);
1699         if (err < 0)
1700                 return err;
1701         bmsr = err;
1702
1703         estat = 0;
1704         if (bmsr & BMSR_ESTATEN) {
1705                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1706                 if (err < 0)
1707                         return err;
1708                 estat = err;
1709         }
1710
1711         bmcr = 0;
1712         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1713         if (err)
1714                 return err;
1715
1716         if (bmsr & BMSR_ESTATEN) {
1717                 u16 ctrl1000 = 0;
1718
1719                 if (estat & ESTATUS_1000_TFULL)
1720                         ctrl1000 |= ADVERTISE_1000FULL;
1721                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1722                 if (err)
1723                         return err;
1724         }
1725
1726         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1727
1728         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1729         if (err)
1730                 return err;
1731
1732         err = mii_read(np, np->phy_addr, MII_BMCR);
1733         if (err < 0)
1734                 return err;
1735         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1736
1737         err = mii_read(np, np->phy_addr, MII_BMSR);
1738         if (err < 0)
1739                 return err;
1740
1741         return 0;
1742 }
1743
1744 static int mii_init_common(struct niu *np)
1745 {
1746         struct niu_link_config *lp = &np->link_config;
1747         u16 bmcr, bmsr, adv, estat;
1748         int err;
1749
1750         err = mii_reset(np);
1751         if (err)
1752                 return err;
1753
1754         err = mii_read(np, np->phy_addr, MII_BMSR);
1755         if (err < 0)
1756                 return err;
1757         bmsr = err;
1758
1759         estat = 0;
1760         if (bmsr & BMSR_ESTATEN) {
1761                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1762                 if (err < 0)
1763                         return err;
1764                 estat = err;
1765         }
1766
1767         bmcr = 0;
1768         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1769         if (err)
1770                 return err;
1771
1772         if (lp->loopback_mode == LOOPBACK_MAC) {
1773                 bmcr |= BMCR_LOOPBACK;
1774                 if (lp->active_speed == SPEED_1000)
1775                         bmcr |= BMCR_SPEED1000;
1776                 if (lp->active_duplex == DUPLEX_FULL)
1777                         bmcr |= BMCR_FULLDPLX;
1778         }
1779
1780         if (lp->loopback_mode == LOOPBACK_PHY) {
1781                 u16 aux;
1782
1783                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1784                        BCM5464R_AUX_CTL_WRITE_1);
1785                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1786                 if (err)
1787                         return err;
1788         }
1789
1790         if (lp->autoneg) {
1791                 u16 ctrl1000;
1792
1793                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1794                 if ((bmsr & BMSR_10HALF) &&
1795                         (lp->advertising & ADVERTISED_10baseT_Half))
1796                         adv |= ADVERTISE_10HALF;
1797                 if ((bmsr & BMSR_10FULL) &&
1798                         (lp->advertising & ADVERTISED_10baseT_Full))
1799                         adv |= ADVERTISE_10FULL;
1800                 if ((bmsr & BMSR_100HALF) &&
1801                         (lp->advertising & ADVERTISED_100baseT_Half))
1802                         adv |= ADVERTISE_100HALF;
1803                 if ((bmsr & BMSR_100FULL) &&
1804                         (lp->advertising & ADVERTISED_100baseT_Full))
1805                         adv |= ADVERTISE_100FULL;
1806                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1807                 if (err)
1808                         return err;
1809
1810                 if (likely(bmsr & BMSR_ESTATEN)) {
1811                         ctrl1000 = 0;
1812                         if ((estat & ESTATUS_1000_THALF) &&
1813                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1814                                 ctrl1000 |= ADVERTISE_1000HALF;
1815                         if ((estat & ESTATUS_1000_TFULL) &&
1816                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1817                                 ctrl1000 |= ADVERTISE_1000FULL;
1818                         err = mii_write(np, np->phy_addr,
1819                                         MII_CTRL1000, ctrl1000);
1820                         if (err)
1821                                 return err;
1822                 }
1823
1824                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1825         } else {
1826                 /* !lp->autoneg */
1827                 int fulldpx;
1828
1829                 if (lp->duplex == DUPLEX_FULL) {
1830                         bmcr |= BMCR_FULLDPLX;
1831                         fulldpx = 1;
1832                 } else if (lp->duplex == DUPLEX_HALF)
1833                         fulldpx = 0;
1834                 else
1835                         return -EINVAL;
1836
1837                 if (lp->speed == SPEED_1000) {
1838                         /* if X-full requested while not supported, or
1839                            X-half requested while not supported... */
1840                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1841                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1842                                 return -EINVAL;
1843                         bmcr |= BMCR_SPEED1000;
1844                 } else if (lp->speed == SPEED_100) {
1845                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1846                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1847                                 return -EINVAL;
1848                         bmcr |= BMCR_SPEED100;
1849                 } else if (lp->speed == SPEED_10) {
1850                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1851                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1852                                 return -EINVAL;
1853                 } else
1854                         return -EINVAL;
1855         }
1856
1857         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1858         if (err)
1859                 return err;
1860
1861 #if 0
1862         err = mii_read(np, np->phy_addr, MII_BMCR);
1863         if (err < 0)
1864                 return err;
1865         bmcr = err;
1866
1867         err = mii_read(np, np->phy_addr, MII_BMSR);
1868         if (err < 0)
1869                 return err;
1870         bmsr = err;
1871
1872         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1873                 np->port, bmcr, bmsr);
1874 #endif
1875
1876         return 0;
1877 }
1878
1879 static int xcvr_init_1g(struct niu *np)
1880 {
1881         u64 val;
1882
1883         /* XXX shared resource, lock parent XXX */
1884         val = nr64(MIF_CONFIG);
1885         val &= ~MIF_CONFIG_INDIRECT_MODE;
1886         nw64(MIF_CONFIG, val);
1887
1888         return mii_init_common(np);
1889 }
1890
1891 static int niu_xcvr_init(struct niu *np)
1892 {
1893         const struct niu_phy_ops *ops = np->phy_ops;
1894         int err;
1895
1896         err = 0;
1897         if (ops->xcvr_init)
1898                 err = ops->xcvr_init(np);
1899
1900         return err;
1901 }
1902
1903 static int niu_serdes_init(struct niu *np)
1904 {
1905         const struct niu_phy_ops *ops = np->phy_ops;
1906         int err;
1907
1908         err = 0;
1909         if (ops->serdes_init)
1910                 err = ops->serdes_init(np);
1911
1912         return err;
1913 }
1914
1915 static void niu_init_xif(struct niu *);
1916 static void niu_handle_led(struct niu *, int status);
1917
1918 static int niu_link_status_common(struct niu *np, int link_up)
1919 {
1920         struct niu_link_config *lp = &np->link_config;
1921         struct net_device *dev = np->dev;
1922         unsigned long flags;
1923
1924         if (!netif_carrier_ok(dev) && link_up) {
1925                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1926                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1927                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1928                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1929                            "10Mbit/sec",
1930                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1931
1932                 spin_lock_irqsave(&np->lock, flags);
1933                 niu_init_xif(np);
1934                 niu_handle_led(np, 1);
1935                 spin_unlock_irqrestore(&np->lock, flags);
1936
1937                 netif_carrier_on(dev);
1938         } else if (netif_carrier_ok(dev) && !link_up) {
1939                 netif_warn(np, link, dev, "Link is down\n");
1940                 spin_lock_irqsave(&np->lock, flags);
1941                 niu_handle_led(np, 0);
1942                 spin_unlock_irqrestore(&np->lock, flags);
1943                 netif_carrier_off(dev);
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1950 {
1951         int err, link_up, pma_status, pcs_status;
1952
1953         link_up = 0;
1954
1955         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1956                         MRVL88X2011_10G_PMD_STATUS_2);
1957         if (err < 0)
1958                 goto out;
1959
1960         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1961         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1962                         MRVL88X2011_PMA_PMD_STATUS_1);
1963         if (err < 0)
1964                 goto out;
1965
1966         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1967
1968         /* Check PMC Register : 3.0001.2 == 1: read twice */
1969         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1970                         MRVL88X2011_PMA_PMD_STATUS_1);
1971         if (err < 0)
1972                 goto out;
1973
1974         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1975                         MRVL88X2011_PMA_PMD_STATUS_1);
1976         if (err < 0)
1977                 goto out;
1978
1979         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1980
1981         /* Check XGXS Register : 4.0018.[0-3,12] */
1982         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1983                         MRVL88X2011_10G_XGXS_LANE_STAT);
1984         if (err < 0)
1985                 goto out;
1986
1987         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1988                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1989                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1990                     0x800))
1991                 link_up = (pma_status && pcs_status) ? 1 : 0;
1992
1993         np->link_config.active_speed = SPEED_10000;
1994         np->link_config.active_duplex = DUPLEX_FULL;
1995         err = 0;
1996 out:
1997         mrvl88x2011_act_led(np, (link_up ?
1998                                  MRVL88X2011_LED_CTL_PCS_ACT :
1999                                  MRVL88X2011_LED_CTL_OFF));
2000
2001         *link_up_p = link_up;
2002         return err;
2003 }
2004
2005 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2006 {
2007         int err, link_up;
2008         link_up = 0;
2009
2010         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2011                         BCM8704_PMD_RCV_SIGDET);
2012         if (err < 0 || err == 0xffff)
2013                 goto out;
2014         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2015                 err = 0;
2016                 goto out;
2017         }
2018
2019         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2020                         BCM8704_PCS_10G_R_STATUS);
2021         if (err < 0)
2022                 goto out;
2023
2024         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2025                 err = 0;
2026                 goto out;
2027         }
2028
2029         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2030                         BCM8704_PHYXS_XGXS_LANE_STAT);
2031         if (err < 0)
2032                 goto out;
2033         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2034                     PHYXS_XGXS_LANE_STAT_MAGIC |
2035                     PHYXS_XGXS_LANE_STAT_PATTEST |
2036                     PHYXS_XGXS_LANE_STAT_LANE3 |
2037                     PHYXS_XGXS_LANE_STAT_LANE2 |
2038                     PHYXS_XGXS_LANE_STAT_LANE1 |
2039                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2040                 err = 0;
2041                 np->link_config.active_speed = SPEED_INVALID;
2042                 np->link_config.active_duplex = DUPLEX_INVALID;
2043                 goto out;
2044         }
2045
2046         link_up = 1;
2047         np->link_config.active_speed = SPEED_10000;
2048         np->link_config.active_duplex = DUPLEX_FULL;
2049         err = 0;
2050
2051 out:
2052         *link_up_p = link_up;
2053         return err;
2054 }
2055
2056 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2057 {
2058         int err, link_up;
2059
2060         link_up = 0;
2061
2062         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2063                         BCM8704_PMD_RCV_SIGDET);
2064         if (err < 0)
2065                 goto out;
2066         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2067                 err = 0;
2068                 goto out;
2069         }
2070
2071         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2072                         BCM8704_PCS_10G_R_STATUS);
2073         if (err < 0)
2074                 goto out;
2075         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2076                 err = 0;
2077                 goto out;
2078         }
2079
2080         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2081                         BCM8704_PHYXS_XGXS_LANE_STAT);
2082         if (err < 0)
2083                 goto out;
2084
2085         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2086                     PHYXS_XGXS_LANE_STAT_MAGIC |
2087                     PHYXS_XGXS_LANE_STAT_LANE3 |
2088                     PHYXS_XGXS_LANE_STAT_LANE2 |
2089                     PHYXS_XGXS_LANE_STAT_LANE1 |
2090                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2091                 err = 0;
2092                 goto out;
2093         }
2094
2095         link_up = 1;
2096         np->link_config.active_speed = SPEED_10000;
2097         np->link_config.active_duplex = DUPLEX_FULL;
2098         err = 0;
2099
2100 out:
2101         *link_up_p = link_up;
2102         return err;
2103 }
2104
2105 static int link_status_10g(struct niu *np, int *link_up_p)
2106 {
2107         unsigned long flags;
2108         int err = -EINVAL;
2109
2110         spin_lock_irqsave(&np->lock, flags);
2111
2112         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2113                 int phy_id;
2114
2115                 phy_id = phy_decode(np->parent->port_phy, np->port);
2116                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2117
2118                 /* handle different phy types */
2119                 switch (phy_id & NIU_PHY_ID_MASK) {
2120                 case NIU_PHY_ID_MRVL88X2011:
2121                         err = link_status_10g_mrvl(np, link_up_p);
2122                         break;
2123
2124                 default: /* bcom 8704 */
2125                         err = link_status_10g_bcom(np, link_up_p);
2126                         break;
2127                 }
2128         }
2129
2130         spin_unlock_irqrestore(&np->lock, flags);
2131
2132         return err;
2133 }
2134
2135 static int niu_10g_phy_present(struct niu *np)
2136 {
2137         u64 sig, mask, val;
2138
2139         sig = nr64(ESR_INT_SIGNALS);
2140         switch (np->port) {
2141         case 0:
2142                 mask = ESR_INT_SIGNALS_P0_BITS;
2143                 val = (ESR_INT_SRDY0_P0 |
2144                        ESR_INT_DET0_P0 |
2145                        ESR_INT_XSRDY_P0 |
2146                        ESR_INT_XDP_P0_CH3 |
2147                        ESR_INT_XDP_P0_CH2 |
2148                        ESR_INT_XDP_P0_CH1 |
2149                        ESR_INT_XDP_P0_CH0);
2150                 break;
2151
2152         case 1:
2153                 mask = ESR_INT_SIGNALS_P1_BITS;
2154                 val = (ESR_INT_SRDY0_P1 |
2155                        ESR_INT_DET0_P1 |
2156                        ESR_INT_XSRDY_P1 |
2157                        ESR_INT_XDP_P1_CH3 |
2158                        ESR_INT_XDP_P1_CH2 |
2159                        ESR_INT_XDP_P1_CH1 |
2160                        ESR_INT_XDP_P1_CH0);
2161                 break;
2162
2163         default:
2164                 return 0;
2165         }
2166
2167         if ((sig & mask) != val)
2168                 return 0;
2169         return 1;
2170 }
2171
2172 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2173 {
2174         unsigned long flags;
2175         int err = 0;
2176         int phy_present;
2177         int phy_present_prev;
2178
2179         spin_lock_irqsave(&np->lock, flags);
2180
2181         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2182                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2183                         1 : 0;
2184                 phy_present = niu_10g_phy_present(np);
2185                 if (phy_present != phy_present_prev) {
2186                         /* state change */
2187                         if (phy_present) {
2188                                 /* A NEM was just plugged in */
2189                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2190                                 if (np->phy_ops->xcvr_init)
2191                                         err = np->phy_ops->xcvr_init(np);
2192                                 if (err) {
2193                                         err = mdio_read(np, np->phy_addr,
2194                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2195                                         if (err == 0xffff) {
2196                                                 /* No mdio, back-to-back XAUI */
2197                                                 goto out;
2198                                         }
2199                                         /* debounce */
2200                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2201                                 }
2202                         } else {
2203                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2204                                 *link_up_p = 0;
2205                                 netif_warn(np, link, np->dev,
2206                                            "Hotplug PHY Removed\n");
2207                         }
2208                 }
2209 out:
2210                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2211                         err = link_status_10g_bcm8706(np, link_up_p);
2212                         if (err == 0xffff) {
2213                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2214                                 *link_up_p = 1;
2215                                 np->link_config.active_speed = SPEED_10000;
2216                                 np->link_config.active_duplex = DUPLEX_FULL;
2217                         }
2218                 }
2219         }
2220
2221         spin_unlock_irqrestore(&np->lock, flags);
2222
2223         return 0;
2224 }
2225
2226 static int niu_link_status(struct niu *np, int *link_up_p)
2227 {
2228         const struct niu_phy_ops *ops = np->phy_ops;
2229         int err;
2230
2231         err = 0;
2232         if (ops->link_status)
2233                 err = ops->link_status(np, link_up_p);
2234
2235         return err;
2236 }
2237
2238 static void niu_timer(unsigned long __opaque)
2239 {
2240         struct niu *np = (struct niu *) __opaque;
2241         unsigned long off;
2242         int err, link_up;
2243
2244         err = niu_link_status(np, &link_up);
2245         if (!err)
2246                 niu_link_status_common(np, link_up);
2247
2248         if (netif_carrier_ok(np->dev))
2249                 off = 5 * HZ;
2250         else
2251                 off = 1 * HZ;
2252         np->timer.expires = jiffies + off;
2253
2254         add_timer(&np->timer);
2255 }
2256
2257 static const struct niu_phy_ops phy_ops_10g_serdes = {
2258         .serdes_init            = serdes_init_10g_serdes,
2259         .link_status            = link_status_10g_serdes,
2260 };
2261
2262 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2263         .serdes_init            = serdes_init_niu_10g_serdes,
2264         .link_status            = link_status_10g_serdes,
2265 };
2266
2267 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2268         .serdes_init            = serdes_init_niu_1g_serdes,
2269         .link_status            = link_status_1g_serdes,
2270 };
2271
2272 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2273         .xcvr_init              = xcvr_init_1g_rgmii,
2274         .link_status            = link_status_1g_rgmii,
2275 };
2276
2277 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2278         .serdes_init            = serdes_init_niu_10g_fiber,
2279         .xcvr_init              = xcvr_init_10g,
2280         .link_status            = link_status_10g,
2281 };
2282
2283 static const struct niu_phy_ops phy_ops_10g_fiber = {
2284         .serdes_init            = serdes_init_10g,
2285         .xcvr_init              = xcvr_init_10g,
2286         .link_status            = link_status_10g,
2287 };
2288
2289 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2290         .serdes_init            = serdes_init_10g,
2291         .xcvr_init              = xcvr_init_10g_bcm8706,
2292         .link_status            = link_status_10g_hotplug,
2293 };
2294
2295 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2296         .serdes_init            = serdes_init_niu_10g_fiber,
2297         .xcvr_init              = xcvr_init_10g_bcm8706,
2298         .link_status            = link_status_10g_hotplug,
2299 };
2300
2301 static const struct niu_phy_ops phy_ops_10g_copper = {
2302         .serdes_init            = serdes_init_10g,
2303         .link_status            = link_status_10g, /* XXX */
2304 };
2305
2306 static const struct niu_phy_ops phy_ops_1g_fiber = {
2307         .serdes_init            = serdes_init_1g,
2308         .xcvr_init              = xcvr_init_1g,
2309         .link_status            = link_status_1g,
2310 };
2311
2312 static const struct niu_phy_ops phy_ops_1g_copper = {
2313         .xcvr_init              = xcvr_init_1g,
2314         .link_status            = link_status_1g,
2315 };
2316
2317 struct niu_phy_template {
2318         const struct niu_phy_ops        *ops;
2319         u32                             phy_addr_base;
2320 };
2321
2322 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2323         .ops            = &phy_ops_10g_fiber_niu,
2324         .phy_addr_base  = 16,
2325 };
2326
2327 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2328         .ops            = &phy_ops_10g_serdes_niu,
2329         .phy_addr_base  = 0,
2330 };
2331
2332 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2333         .ops            = &phy_ops_1g_serdes_niu,
2334         .phy_addr_base  = 0,
2335 };
2336
2337 static const struct niu_phy_template phy_template_10g_fiber = {
2338         .ops            = &phy_ops_10g_fiber,
2339         .phy_addr_base  = 8,
2340 };
2341
2342 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2343         .ops            = &phy_ops_10g_fiber_hotplug,
2344         .phy_addr_base  = 8,
2345 };
2346
2347 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2348         .ops            = &phy_ops_niu_10g_hotplug,
2349         .phy_addr_base  = 8,
2350 };
2351
2352 static const struct niu_phy_template phy_template_10g_copper = {
2353         .ops            = &phy_ops_10g_copper,
2354         .phy_addr_base  = 10,
2355 };
2356
2357 static const struct niu_phy_template phy_template_1g_fiber = {
2358         .ops            = &phy_ops_1g_fiber,
2359         .phy_addr_base  = 0,
2360 };
2361
2362 static const struct niu_phy_template phy_template_1g_copper = {
2363         .ops            = &phy_ops_1g_copper,
2364         .phy_addr_base  = 0,
2365 };
2366
2367 static const struct niu_phy_template phy_template_1g_rgmii = {
2368         .ops            = &phy_ops_1g_rgmii,
2369         .phy_addr_base  = 0,
2370 };
2371
2372 static const struct niu_phy_template phy_template_10g_serdes = {
2373         .ops            = &phy_ops_10g_serdes,
2374         .phy_addr_base  = 0,
2375 };
2376
2377 static int niu_atca_port_num[4] = {
2378         0, 0,  11, 10
2379 };
2380
2381 static int serdes_init_10g_serdes(struct niu *np)
2382 {
2383         struct niu_link_config *lp = &np->link_config;
2384         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2385         u64 ctrl_val, test_cfg_val, sig, mask, val;
2386         u64 reset_val;
2387
2388         switch (np->port) {
2389         case 0:
2390                 reset_val =  ENET_SERDES_RESET_0;
2391                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2392                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2393                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2394                 break;
2395         case 1:
2396                 reset_val =  ENET_SERDES_RESET_1;
2397                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2398                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2399                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2400                 break;
2401
2402         default:
2403                 return -EINVAL;
2404         }
2405         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2406                     ENET_SERDES_CTRL_SDET_1 |
2407                     ENET_SERDES_CTRL_SDET_2 |
2408                     ENET_SERDES_CTRL_SDET_3 |
2409                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2410                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2411                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2412                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2413                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2414                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2415                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2416                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2417         test_cfg_val = 0;
2418
2419         if (lp->loopback_mode == LOOPBACK_PHY) {
2420                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2421                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2422                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2423                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2424                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2425                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2426                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2427                                   ENET_SERDES_TEST_MD_3_SHIFT));
2428         }
2429
2430         esr_reset(np);
2431         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2432         nw64(ctrl_reg, ctrl_val);
2433         nw64(test_cfg_reg, test_cfg_val);
2434
2435         /* Initialize all 4 lanes of the SERDES.  */
2436         for (i = 0; i < 4; i++) {
2437                 u32 rxtx_ctrl, glue0;
2438                 int err;
2439
2440                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2441                 if (err)
2442                         return err;
2443                 err = esr_read_glue0(np, i, &glue0);
2444                 if (err)
2445                         return err;
2446
2447                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2448                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2449                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2450
2451                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2452                            ESR_GLUE_CTRL0_THCNT |
2453                            ESR_GLUE_CTRL0_BLTIME);
2454                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2455                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2456                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2457                           (BLTIME_300_CYCLES <<
2458                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2459
2460                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2461                 if (err)
2462                         return err;
2463                 err = esr_write_glue0(np, i, glue0);
2464                 if (err)
2465                         return err;
2466         }
2467
2468
2469         sig = nr64(ESR_INT_SIGNALS);
2470         switch (np->port) {
2471         case 0:
2472                 mask = ESR_INT_SIGNALS_P0_BITS;
2473                 val = (ESR_INT_SRDY0_P0 |
2474                        ESR_INT_DET0_P0 |
2475                        ESR_INT_XSRDY_P0 |
2476                        ESR_INT_XDP_P0_CH3 |
2477                        ESR_INT_XDP_P0_CH2 |
2478                        ESR_INT_XDP_P0_CH1 |
2479                        ESR_INT_XDP_P0_CH0);
2480                 break;
2481
2482         case 1:
2483                 mask = ESR_INT_SIGNALS_P1_BITS;
2484                 val = (ESR_INT_SRDY0_P1 |
2485                        ESR_INT_DET0_P1 |
2486                        ESR_INT_XSRDY_P1 |
2487                        ESR_INT_XDP_P1_CH3 |
2488                        ESR_INT_XDP_P1_CH2 |
2489                        ESR_INT_XDP_P1_CH1 |
2490                        ESR_INT_XDP_P1_CH0);
2491                 break;
2492
2493         default:
2494                 return -EINVAL;
2495         }
2496
2497         if ((sig & mask) != val) {
2498                 int err;
2499                 err = serdes_init_1g_serdes(np);
2500                 if (!err) {
2501                         np->flags &= ~NIU_FLAGS_10G;
2502                         np->mac_xcvr = MAC_XCVR_PCS;
2503                 }  else {
2504                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2505                                    np->port);
2506                         return -ENODEV;
2507                 }
2508         }
2509
2510         return 0;
2511 }
2512
2513 static int niu_determine_phy_disposition(struct niu *np)
2514 {
2515         struct niu_parent *parent = np->parent;
2516         u8 plat_type = parent->plat_type;
2517         const struct niu_phy_template *tp;
2518         u32 phy_addr_off = 0;
2519
2520         if (plat_type == PLAT_TYPE_NIU) {
2521                 switch (np->flags &
2522                         (NIU_FLAGS_10G |
2523                          NIU_FLAGS_FIBER |
2524                          NIU_FLAGS_XCVR_SERDES)) {
2525                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2526                         /* 10G Serdes */
2527                         tp = &phy_template_niu_10g_serdes;
2528                         break;
2529                 case NIU_FLAGS_XCVR_SERDES:
2530                         /* 1G Serdes */
2531                         tp = &phy_template_niu_1g_serdes;
2532                         break;
2533                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2534                         /* 10G Fiber */
2535                 default:
2536                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2537                                 tp = &phy_template_niu_10g_hotplug;
2538                                 if (np->port == 0)
2539                                         phy_addr_off = 8;
2540                                 if (np->port == 1)
2541                                         phy_addr_off = 12;
2542                         } else {
2543                                 tp = &phy_template_niu_10g_fiber;
2544                                 phy_addr_off += np->port;
2545                         }
2546                         break;
2547                 }
2548         } else {
2549                 switch (np->flags &
2550                         (NIU_FLAGS_10G |
2551                          NIU_FLAGS_FIBER |
2552                          NIU_FLAGS_XCVR_SERDES)) {
2553                 case 0:
2554                         /* 1G copper */
2555                         tp = &phy_template_1g_copper;
2556                         if (plat_type == PLAT_TYPE_VF_P0)
2557                                 phy_addr_off = 10;
2558                         else if (plat_type == PLAT_TYPE_VF_P1)
2559                                 phy_addr_off = 26;
2560
2561                         phy_addr_off += (np->port ^ 0x3);
2562                         break;
2563
2564                 case NIU_FLAGS_10G:
2565                         /* 10G copper */
2566                         tp = &phy_template_10g_copper;
2567                         break;
2568
2569                 case NIU_FLAGS_FIBER:
2570                         /* 1G fiber */
2571                         tp = &phy_template_1g_fiber;
2572                         break;
2573
2574                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2575                         /* 10G fiber */
2576                         tp = &phy_template_10g_fiber;
2577                         if (plat_type == PLAT_TYPE_VF_P0 ||
2578                             plat_type == PLAT_TYPE_VF_P1)
2579                                 phy_addr_off = 8;
2580                         phy_addr_off += np->port;
2581                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2582                                 tp = &phy_template_10g_fiber_hotplug;
2583                                 if (np->port == 0)
2584                                         phy_addr_off = 8;
2585                                 if (np->port == 1)
2586                                         phy_addr_off = 12;
2587                         }
2588                         break;
2589
2590                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2591                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2592                 case NIU_FLAGS_XCVR_SERDES:
2593                         switch(np->port) {
2594                         case 0:
2595                         case 1:
2596                                 tp = &phy_template_10g_serdes;
2597                                 break;
2598                         case 2:
2599                         case 3:
2600                                 tp = &phy_template_1g_rgmii;
2601                                 break;
2602                         default:
2603                                 return -EINVAL;
2604                                 break;
2605                         }
2606                         phy_addr_off = niu_atca_port_num[np->port];
2607                         break;
2608
2609                 default:
2610                         return -EINVAL;
2611                 }
2612         }
2613
2614         np->phy_ops = tp->ops;
2615         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2616
2617         return 0;
2618 }
2619
2620 static int niu_init_link(struct niu *np)
2621 {
2622         struct niu_parent *parent = np->parent;
2623         int err, ignore;
2624
2625         if (parent->plat_type == PLAT_TYPE_NIU) {
2626                 err = niu_xcvr_init(np);
2627                 if (err)
2628                         return err;
2629                 msleep(200);
2630         }
2631         err = niu_serdes_init(np);
2632         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2633                 return err;
2634         msleep(200);
2635         err = niu_xcvr_init(np);
2636         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2637                 niu_link_status(np, &ignore);
2638         return 0;
2639 }
2640
2641 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2642 {
2643         u16 reg0 = addr[4] << 8 | addr[5];
2644         u16 reg1 = addr[2] << 8 | addr[3];
2645         u16 reg2 = addr[0] << 8 | addr[1];
2646
2647         if (np->flags & NIU_FLAGS_XMAC) {
2648                 nw64_mac(XMAC_ADDR0, reg0);
2649                 nw64_mac(XMAC_ADDR1, reg1);
2650                 nw64_mac(XMAC_ADDR2, reg2);
2651         } else {
2652                 nw64_mac(BMAC_ADDR0, reg0);
2653                 nw64_mac(BMAC_ADDR1, reg1);
2654                 nw64_mac(BMAC_ADDR2, reg2);
2655         }
2656 }
2657
2658 static int niu_num_alt_addr(struct niu *np)
2659 {
2660         if (np->flags & NIU_FLAGS_XMAC)
2661                 return XMAC_NUM_ALT_ADDR;
2662         else
2663                 return BMAC_NUM_ALT_ADDR;
2664 }
2665
2666 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2667 {
2668         u16 reg0 = addr[4] << 8 | addr[5];
2669         u16 reg1 = addr[2] << 8 | addr[3];
2670         u16 reg2 = addr[0] << 8 | addr[1];
2671
2672         if (index >= niu_num_alt_addr(np))
2673                 return -EINVAL;
2674
2675         if (np->flags & NIU_FLAGS_XMAC) {
2676                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2677                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2678                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2679         } else {
2680                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2681                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2682                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2683         }
2684
2685         return 0;
2686 }
2687
2688 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2689 {
2690         unsigned long reg;
2691         u64 val, mask;
2692
2693         if (index >= niu_num_alt_addr(np))
2694                 return -EINVAL;
2695
2696         if (np->flags & NIU_FLAGS_XMAC) {
2697                 reg = XMAC_ADDR_CMPEN;
2698                 mask = 1 << index;
2699         } else {
2700                 reg = BMAC_ADDR_CMPEN;
2701                 mask = 1 << (index + 1);
2702         }
2703
2704         val = nr64_mac(reg);
2705         if (on)
2706                 val |= mask;
2707         else
2708                 val &= ~mask;
2709         nw64_mac(reg, val);
2710
2711         return 0;
2712 }
2713
2714 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2715                                    int num, int mac_pref)
2716 {
2717         u64 val = nr64_mac(reg);
2718         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2719         val |= num;
2720         if (mac_pref)
2721                 val |= HOST_INFO_MPR;
2722         nw64_mac(reg, val);
2723 }
2724
2725 static int __set_rdc_table_num(struct niu *np,
2726                                int xmac_index, int bmac_index,
2727                                int rdc_table_num, int mac_pref)
2728 {
2729         unsigned long reg;
2730
2731         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2732                 return -EINVAL;
2733         if (np->flags & NIU_FLAGS_XMAC)
2734                 reg = XMAC_HOST_INFO(xmac_index);
2735         else
2736                 reg = BMAC_HOST_INFO(bmac_index);
2737         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2738         return 0;
2739 }
2740
2741 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2742                                          int mac_pref)
2743 {
2744         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2745 }
2746
2747 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2748                                            int mac_pref)
2749 {
2750         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2751 }
2752
2753 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2754                                      int table_num, int mac_pref)
2755 {
2756         if (idx >= niu_num_alt_addr(np))
2757                 return -EINVAL;
2758         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2759 }
2760
2761 static u64 vlan_entry_set_parity(u64 reg_val)
2762 {
2763         u64 port01_mask;
2764         u64 port23_mask;
2765
2766         port01_mask = 0x00ff;
2767         port23_mask = 0xff00;
2768
2769         if (hweight64(reg_val & port01_mask) & 1)
2770                 reg_val |= ENET_VLAN_TBL_PARITY0;
2771         else
2772                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2773
2774         if (hweight64(reg_val & port23_mask) & 1)
2775                 reg_val |= ENET_VLAN_TBL_PARITY1;
2776         else
2777                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2778
2779         return reg_val;
2780 }
2781
2782 static void vlan_tbl_write(struct niu *np, unsigned long index,
2783                            int port, int vpr, int rdc_table)
2784 {
2785         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2786
2787         reg_val &= ~((ENET_VLAN_TBL_VPR |
2788                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2789                      ENET_VLAN_TBL_SHIFT(port));
2790         if (vpr)
2791                 reg_val |= (ENET_VLAN_TBL_VPR <<
2792                             ENET_VLAN_TBL_SHIFT(port));
2793         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2794
2795         reg_val = vlan_entry_set_parity(reg_val);
2796
2797         nw64(ENET_VLAN_TBL(index), reg_val);
2798 }
2799
2800 static void vlan_tbl_clear(struct niu *np)
2801 {
2802         int i;
2803
2804         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2805                 nw64(ENET_VLAN_TBL(i), 0);
2806 }
2807
2808 static int tcam_wait_bit(struct niu *np, u64 bit)
2809 {
2810         int limit = 1000;
2811
2812         while (--limit > 0) {
2813                 if (nr64(TCAM_CTL) & bit)
2814                         break;
2815                 udelay(1);
2816         }
2817         if (limit <= 0)
2818                 return -ENODEV;
2819
2820         return 0;
2821 }
2822
2823 static int tcam_flush(struct niu *np, int index)
2824 {
2825         nw64(TCAM_KEY_0, 0x00);
2826         nw64(TCAM_KEY_MASK_0, 0xff);
2827         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2828
2829         return tcam_wait_bit(np, TCAM_CTL_STAT);
2830 }
2831
2832 #if 0
2833 static int tcam_read(struct niu *np, int index,
2834                      u64 *key, u64 *mask)
2835 {
2836         int err;
2837
2838         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2839         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2840         if (!err) {
2841                 key[0] = nr64(TCAM_KEY_0);
2842                 key[1] = nr64(TCAM_KEY_1);
2843                 key[2] = nr64(TCAM_KEY_2);
2844                 key[3] = nr64(TCAM_KEY_3);
2845                 mask[0] = nr64(TCAM_KEY_MASK_0);
2846                 mask[1] = nr64(TCAM_KEY_MASK_1);
2847                 mask[2] = nr64(TCAM_KEY_MASK_2);
2848                 mask[3] = nr64(TCAM_KEY_MASK_3);
2849         }
2850         return err;
2851 }
2852 #endif
2853
2854 static int tcam_write(struct niu *np, int index,
2855                       u64 *key, u64 *mask)
2856 {
2857         nw64(TCAM_KEY_0, key[0]);
2858         nw64(TCAM_KEY_1, key[1]);
2859         nw64(TCAM_KEY_2, key[2]);
2860         nw64(TCAM_KEY_3, key[3]);
2861         nw64(TCAM_KEY_MASK_0, mask[0]);
2862         nw64(TCAM_KEY_MASK_1, mask[1]);
2863         nw64(TCAM_KEY_MASK_2, mask[2]);
2864         nw64(TCAM_KEY_MASK_3, mask[3]);
2865         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2866
2867         return tcam_wait_bit(np, TCAM_CTL_STAT);
2868 }
2869
2870 #if 0
2871 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2872 {
2873         int err;
2874
2875         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2876         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2877         if (!err)
2878                 *data = nr64(TCAM_KEY_1);
2879
2880         return err;
2881 }
2882 #endif
2883
2884 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2885 {
2886         nw64(TCAM_KEY_1, assoc_data);
2887         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2888
2889         return tcam_wait_bit(np, TCAM_CTL_STAT);
2890 }
2891
2892 static void tcam_enable(struct niu *np, int on)
2893 {
2894         u64 val = nr64(FFLP_CFG_1);
2895
2896         if (on)
2897                 val &= ~FFLP_CFG_1_TCAM_DIS;
2898         else
2899                 val |= FFLP_CFG_1_TCAM_DIS;
2900         nw64(FFLP_CFG_1, val);
2901 }
2902
2903 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2904 {
2905         u64 val = nr64(FFLP_CFG_1);
2906
2907         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2908                  FFLP_CFG_1_CAMLAT |
2909                  FFLP_CFG_1_CAMRATIO);
2910         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2911         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2912         nw64(FFLP_CFG_1, val);
2913
2914         val = nr64(FFLP_CFG_1);
2915         val |= FFLP_CFG_1_FFLPINITDONE;
2916         nw64(FFLP_CFG_1, val);
2917 }
2918
2919 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2920                                       int on)
2921 {
2922         unsigned long reg;
2923         u64 val;
2924
2925         if (class < CLASS_CODE_ETHERTYPE1 ||
2926             class > CLASS_CODE_ETHERTYPE2)
2927                 return -EINVAL;
2928
2929         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2930         val = nr64(reg);
2931         if (on)
2932                 val |= L2_CLS_VLD;
2933         else
2934                 val &= ~L2_CLS_VLD;
2935         nw64(reg, val);
2936
2937         return 0;
2938 }
2939
2940 #if 0
2941 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2942                                    u64 ether_type)
2943 {
2944         unsigned long reg;
2945         u64 val;
2946
2947         if (class < CLASS_CODE_ETHERTYPE1 ||
2948             class > CLASS_CODE_ETHERTYPE2 ||
2949             (ether_type & ~(u64)0xffff) != 0)
2950                 return -EINVAL;
2951
2952         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2953         val = nr64(reg);
2954         val &= ~L2_CLS_ETYPE;
2955         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2956         nw64(reg, val);
2957
2958         return 0;
2959 }
2960 #endif
2961
2962 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2963                                      int on)
2964 {
2965         unsigned long reg;
2966         u64 val;
2967
2968         if (class < CLASS_CODE_USER_PROG1 ||
2969             class > CLASS_CODE_USER_PROG4)
2970                 return -EINVAL;
2971
2972         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2973         val = nr64(reg);
2974         if (on)
2975                 val |= L3_CLS_VALID;
2976         else
2977                 val &= ~L3_CLS_VALID;
2978         nw64(reg, val);
2979
2980         return 0;
2981 }
2982
2983 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2984                                   int ipv6, u64 protocol_id,
2985                                   u64 tos_mask, u64 tos_val)
2986 {
2987         unsigned long reg;
2988         u64 val;
2989
2990         if (class < CLASS_CODE_USER_PROG1 ||
2991             class > CLASS_CODE_USER_PROG4 ||
2992             (protocol_id & ~(u64)0xff) != 0 ||
2993             (tos_mask & ~(u64)0xff) != 0 ||
2994             (tos_val & ~(u64)0xff) != 0)
2995                 return -EINVAL;
2996
2997         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2998         val = nr64(reg);
2999         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3000                  L3_CLS_TOSMASK | L3_CLS_TOS);
3001         if (ipv6)
3002                 val |= L3_CLS_IPVER;
3003         val |= (protocol_id << L3_CLS_PID_SHIFT);
3004         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3005         val |= (tos_val << L3_CLS_TOS_SHIFT);
3006         nw64(reg, val);
3007
3008         return 0;
3009 }
3010
3011 static int tcam_early_init(struct niu *np)
3012 {
3013         unsigned long i;
3014         int err;
3015
3016         tcam_enable(np, 0);
3017         tcam_set_lat_and_ratio(np,
3018                                DEFAULT_TCAM_LATENCY,
3019                                DEFAULT_TCAM_ACCESS_RATIO);
3020         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3021                 err = tcam_user_eth_class_enable(np, i, 0);
3022                 if (err)
3023                         return err;
3024         }
3025         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3026                 err = tcam_user_ip_class_enable(np, i, 0);
3027                 if (err)
3028                         return err;
3029         }
3030
3031         return 0;
3032 }
3033
3034 static int tcam_flush_all(struct niu *np)
3035 {
3036         unsigned long i;
3037
3038         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3039                 int err = tcam_flush(np, i);
3040                 if (err)
3041                         return err;
3042         }
3043         return 0;
3044 }
3045
3046 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3047 {
3048         return ((u64)index | (num_entries == 1 ?
3049                               HASH_TBL_ADDR_AUTOINC : 0));
3050 }
3051
3052 #if 0
3053 static int hash_read(struct niu *np, unsigned long partition,
3054                      unsigned long index, unsigned long num_entries,
3055                      u64 *data)
3056 {
3057         u64 val = hash_addr_regval(index, num_entries);
3058         unsigned long i;
3059
3060         if (partition >= FCRAM_NUM_PARTITIONS ||
3061             index + num_entries > FCRAM_SIZE)
3062                 return -EINVAL;
3063
3064         nw64(HASH_TBL_ADDR(partition), val);
3065         for (i = 0; i < num_entries; i++)
3066                 data[i] = nr64(HASH_TBL_DATA(partition));
3067
3068         return 0;
3069 }
3070 #endif
3071
3072 static int hash_write(struct niu *np, unsigned long partition,
3073                       unsigned long index, unsigned long num_entries,
3074                       u64 *data)
3075 {
3076         u64 val = hash_addr_regval(index, num_entries);
3077         unsigned long i;
3078
3079         if (partition >= FCRAM_NUM_PARTITIONS ||
3080             index + (num_entries * 8) > FCRAM_SIZE)
3081                 return -EINVAL;
3082
3083         nw64(HASH_TBL_ADDR(partition), val);
3084         for (i = 0; i < num_entries; i++)
3085                 nw64(HASH_TBL_DATA(partition), data[i]);
3086
3087         return 0;
3088 }
3089
3090 static void fflp_reset(struct niu *np)
3091 {
3092         u64 val;
3093
3094         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3095         udelay(10);
3096         nw64(FFLP_CFG_1, 0);
3097
3098         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3099         nw64(FFLP_CFG_1, val);
3100 }
3101
3102 static void fflp_set_timings(struct niu *np)
3103 {
3104         u64 val = nr64(FFLP_CFG_1);
3105
3106         val &= ~FFLP_CFG_1_FFLPINITDONE;
3107         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3108         nw64(FFLP_CFG_1, val);
3109
3110         val = nr64(FFLP_CFG_1);
3111         val |= FFLP_CFG_1_FFLPINITDONE;
3112         nw64(FFLP_CFG_1, val);
3113
3114         val = nr64(FCRAM_REF_TMR);
3115         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3116         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3117         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3118         nw64(FCRAM_REF_TMR, val);
3119 }
3120
3121 static int fflp_set_partition(struct niu *np, u64 partition,
3122                               u64 mask, u64 base, int enable)
3123 {
3124         unsigned long reg;
3125         u64 val;
3126
3127         if (partition >= FCRAM_NUM_PARTITIONS ||
3128             (mask & ~(u64)0x1f) != 0 ||
3129             (base & ~(u64)0x1f) != 0)
3130                 return -EINVAL;
3131
3132         reg = FLW_PRT_SEL(partition);
3133
3134         val = nr64(reg);
3135         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3136         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3137         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3138         if (enable)
3139                 val |= FLW_PRT_SEL_EXT;
3140         nw64(reg, val);
3141
3142         return 0;
3143 }
3144
3145 static int fflp_disable_all_partitions(struct niu *np)
3146 {
3147         unsigned long i;
3148
3149         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3150                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3151                 if (err)
3152                         return err;
3153         }
3154         return 0;
3155 }
3156
3157 static void fflp_llcsnap_enable(struct niu *np, int on)
3158 {
3159         u64 val = nr64(FFLP_CFG_1);
3160
3161         if (on)
3162                 val |= FFLP_CFG_1_LLCSNAP;
3163         else
3164                 val &= ~FFLP_CFG_1_LLCSNAP;
3165         nw64(FFLP_CFG_1, val);
3166 }
3167
3168 static void fflp_errors_enable(struct niu *np, int on)
3169 {
3170         u64 val = nr64(FFLP_CFG_1);
3171
3172         if (on)
3173                 val &= ~FFLP_CFG_1_ERRORDIS;
3174         else
3175                 val |= FFLP_CFG_1_ERRORDIS;
3176         nw64(FFLP_CFG_1, val);
3177 }
3178
3179 static int fflp_hash_clear(struct niu *np)
3180 {
3181         struct fcram_hash_ipv4 ent;
3182         unsigned long i;
3183
3184         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3185         memset(&ent, 0, sizeof(ent));
3186         ent.header = HASH_HEADER_EXT;
3187
3188         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3189                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3190                 if (err)
3191                         return err;
3192         }
3193         return 0;
3194 }
3195
3196 static int fflp_early_init(struct niu *np)
3197 {
3198         struct niu_parent *parent;
3199         unsigned long flags;
3200         int err;
3201
3202         niu_lock_parent(np, flags);
3203
3204         parent = np->parent;
3205         err = 0;
3206         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3207                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3208                              "%s() Initting hw on port %u\n",
3209                              __func__, np->port);
3210                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3211                         fflp_reset(np);
3212                         fflp_set_timings(np);
3213                         err = fflp_disable_all_partitions(np);
3214                         if (err) {
3215                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3216                                              "fflp_disable_all_partitions failed, err=%d\n",
3217                                              err);
3218                                 goto out;
3219                         }
3220                 }
3221
3222                 err = tcam_early_init(np);
3223                 if (err) {
3224                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3225                                      "tcam_early_init failed, err=%d\n", err);
3226                         goto out;
3227                 }
3228                 fflp_llcsnap_enable(np, 1);
3229                 fflp_errors_enable(np, 0);
3230                 nw64(H1POLY, 0);
3231                 nw64(H2POLY, 0);
3232
3233                 err = tcam_flush_all(np);
3234                 if (err) {
3235                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3236                                      "tcam_flush_all failed, err=%d\n", err);
3237                         goto out;
3238                 }
3239                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3240                         err = fflp_hash_clear(np);
3241                         if (err) {
3242                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3243                                              "fflp_hash_clear failed, err=%d\n",
3244                                              err);
3245                                 goto out;
3246                         }
3247                 }
3248
3249                 vlan_tbl_clear(np);
3250
3251                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3252                              "%s() Success\n", __func__);
3253                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3254         }
3255 out:
3256         niu_unlock_parent(np, flags);
3257         return err;
3258 }
3259
3260 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3261 {
3262         if (class_code < CLASS_CODE_USER_PROG1 ||
3263             class_code > CLASS_CODE_SCTP_IPV6)
3264                 return -EINVAL;
3265
3266         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3267         return 0;
3268 }
3269
3270 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3271 {
3272         if (class_code < CLASS_CODE_USER_PROG1 ||
3273             class_code > CLASS_CODE_SCTP_IPV6)
3274                 return -EINVAL;
3275
3276         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3277         return 0;
3278 }
3279
3280 /* Entries for the ports are interleaved in the TCAM */
3281 static u16 tcam_get_index(struct niu *np, u16 idx)
3282 {
3283         /* One entry reserved for IP fragment rule */
3284         if (idx >= (np->clas.tcam_sz - 1))
3285                 idx = 0;
3286         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3287 }
3288
3289 static u16 tcam_get_size(struct niu *np)
3290 {
3291         /* One entry reserved for IP fragment rule */
3292         return np->clas.tcam_sz - 1;
3293 }
3294
3295 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3296 {
3297         /* One entry reserved for IP fragment rule */
3298         return np->clas.tcam_valid_entries - 1;
3299 }
3300
3301 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3302                               u32 offset, u32 size)
3303 {
3304         int i = skb_shinfo(skb)->nr_frags;
3305         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3306
3307         frag->page = page;
3308         frag->page_offset = offset;
3309         frag->size = size;
3310
3311         skb->len += size;
3312         skb->data_len += size;
3313         skb->truesize += size;
3314
3315         skb_shinfo(skb)->nr_frags = i + 1;
3316 }
3317
3318 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3319 {
3320         a >>= PAGE_SHIFT;
3321         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3322
3323         return (a & (MAX_RBR_RING_SIZE - 1));
3324 }
3325
3326 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3327                                     struct page ***link)
3328 {
3329         unsigned int h = niu_hash_rxaddr(rp, addr);
3330         struct page *p, **pp;
3331
3332         addr &= PAGE_MASK;
3333         pp = &rp->rxhash[h];
3334         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3335                 if (p->index == addr) {
3336                         *link = pp;
3337                         break;
3338                 }
3339         }
3340
3341         return p;
3342 }
3343
3344 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3345 {
3346         unsigned int h = niu_hash_rxaddr(rp, base);
3347
3348         page->index = base;
3349         page->mapping = (struct address_space *) rp->rxhash[h];
3350         rp->rxhash[h] = page;
3351 }
3352
3353 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3354                             gfp_t mask, int start_index)
3355 {
3356         struct page *page;
3357         u64 addr;
3358         int i;
3359
3360         page = alloc_page(mask);
3361         if (!page)
3362                 return -ENOMEM;
3363
3364         addr = np->ops->map_page(np->device, page, 0,
3365                                  PAGE_SIZE, DMA_FROM_DEVICE);
3366
3367         niu_hash_page(rp, page, addr);
3368         if (rp->rbr_blocks_per_page > 1)
3369                 atomic_add(rp->rbr_blocks_per_page - 1,
3370                            &compound_head(page)->_count);
3371
3372         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3373                 __le32 *rbr = &rp->rbr[start_index + i];
3374
3375                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3376                 addr += rp->rbr_block_size;
3377         }
3378
3379         return 0;
3380 }
3381
3382 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3383 {
3384         int index = rp->rbr_index;
3385
3386         rp->rbr_pending++;
3387         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3388                 int err = niu_rbr_add_page(np, rp, mask, index);
3389
3390                 if (unlikely(err)) {
3391                         rp->rbr_pending--;
3392                         return;
3393                 }
3394
3395                 rp->rbr_index += rp->rbr_blocks_per_page;
3396                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3397                 if (rp->rbr_index == rp->rbr_table_size)
3398                         rp->rbr_index = 0;
3399
3400                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3401                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3402                         rp->rbr_pending = 0;
3403                 }
3404         }
3405 }
3406
3407 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3408 {
3409         unsigned int index = rp->rcr_index;
3410         int num_rcr = 0;
3411
3412         rp->rx_dropped++;
3413         while (1) {
3414                 struct page *page, **link;
3415                 u64 addr, val;
3416                 u32 rcr_size;
3417
3418                 num_rcr++;
3419
3420                 val = le64_to_cpup(&rp->rcr[index]);
3421                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3422                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3423                 page = niu_find_rxpage(rp, addr, &link);
3424
3425                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3426                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3427                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3428                         *link = (struct page *) page->mapping;
3429                         np->ops->unmap_page(np->device, page->index,
3430                                             PAGE_SIZE, DMA_FROM_DEVICE);
3431                         page->index = 0;
3432                         page->mapping = NULL;
3433                         __free_page(page);
3434                         rp->rbr_refill_pending++;
3435                 }
3436
3437                 index = NEXT_RCR(rp, index);
3438                 if (!(val & RCR_ENTRY_MULTI))
3439                         break;
3440
3441         }
3442         rp->rcr_index = index;
3443
3444         return num_rcr;
3445 }
3446
3447 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3448                               struct rx_ring_info *rp)
3449 {
3450         unsigned int index = rp->rcr_index;
3451         struct sk_buff *skb;
3452         int len, num_rcr;
3453
3454         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3455         if (unlikely(!skb))
3456                 return niu_rx_pkt_ignore(np, rp);
3457
3458         num_rcr = 0;
3459         while (1) {
3460                 struct page *page, **link;
3461                 u32 rcr_size, append_size;
3462                 u64 addr, val, off;
3463
3464                 num_rcr++;
3465
3466                 val = le64_to_cpup(&rp->rcr[index]);
3467
3468                 len = (val & RCR_ENTRY_L2_LEN) >>
3469                         RCR_ENTRY_L2_LEN_SHIFT;
3470                 len -= ETH_FCS_LEN;
3471
3472                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3473                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3474                 page = niu_find_rxpage(rp, addr, &link);
3475
3476                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3477                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3478
3479                 off = addr & ~PAGE_MASK;
3480                 append_size = rcr_size;
3481                 if (num_rcr == 1) {
3482                         int ptype;
3483
3484                         off += 2;
3485                         append_size -= 2;
3486
3487                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3488                         if ((ptype == RCR_PKT_TYPE_TCP ||
3489                              ptype == RCR_PKT_TYPE_UDP) &&
3490                             !(val & (RCR_ENTRY_NOPORT |
3491                                      RCR_ENTRY_ERROR)))
3492                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3493                         else
3494                                 skb->ip_summed = CHECKSUM_NONE;
3495                 }
3496                 if (!(val & RCR_ENTRY_MULTI))
3497                         append_size = len - skb->len;
3498
3499                 niu_rx_skb_append(skb, page, off, append_size);
3500                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3501                         *link = (struct page *) page->mapping;
3502                         np->ops->unmap_page(np->device, page->index,
3503                                             PAGE_SIZE, DMA_FROM_DEVICE);
3504                         page->index = 0;
3505                         page->mapping = NULL;
3506                         rp->rbr_refill_pending++;
3507                 } else
3508                         get_page(page);
3509
3510                 index = NEXT_RCR(rp, index);
3511                 if (!(val & RCR_ENTRY_MULTI))
3512                         break;
3513
3514         }
3515         rp->rcr_index = index;
3516
3517         skb_reserve(skb, NET_IP_ALIGN);
3518         __pskb_pull_tail(skb, min(len, VLAN_ETH_HLEN));
3519
3520         rp->rx_packets++;
3521         rp->rx_bytes += skb->len;
3522
3523         skb->protocol = eth_type_trans(skb, np->dev);
3524         skb_record_rx_queue(skb, rp->rx_channel);
3525         napi_gro_receive(napi, skb);
3526
3527         return num_rcr;
3528 }
3529
3530 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3531 {
3532         int blocks_per_page = rp->rbr_blocks_per_page;
3533         int err, index = rp->rbr_index;
3534
3535         err = 0;
3536         while (index < (rp->rbr_table_size - blocks_per_page)) {
3537                 err = niu_rbr_add_page(np, rp, mask, index);
3538                 if (err)
3539                         break;
3540
3541                 index += blocks_per_page;
3542         }
3543
3544         rp->rbr_index = index;
3545         return err;
3546 }
3547
3548 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3549 {
3550         int i;
3551
3552         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3553                 struct page *page;
3554
3555                 page = rp->rxhash[i];
3556                 while (page) {
3557                         struct page *next = (struct page *) page->mapping;
3558                         u64 base = page->index;
3559
3560                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3561                                             DMA_FROM_DEVICE);
3562                         page->index = 0;
3563                         page->mapping = NULL;
3564
3565                         __free_page(page);
3566
3567                         page = next;
3568                 }
3569         }
3570
3571         for (i = 0; i < rp->rbr_table_size; i++)
3572                 rp->rbr[i] = cpu_to_le32(0);
3573         rp->rbr_index = 0;
3574 }
3575
3576 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3577 {
3578         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3579         struct sk_buff *skb = tb->skb;
3580         struct tx_pkt_hdr *tp;
3581         u64 tx_flags;
3582         int i, len;
3583
3584         tp = (struct tx_pkt_hdr *) skb->data;
3585         tx_flags = le64_to_cpup(&tp->flags);
3586
3587         rp->tx_packets++;
3588         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3589                          ((tx_flags & TXHDR_PAD) / 2));
3590
3591         len = skb_headlen(skb);
3592         np->ops->unmap_single(np->device, tb->mapping,
3593                               len, DMA_TO_DEVICE);
3594
3595         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3596                 rp->mark_pending--;
3597
3598         tb->skb = NULL;
3599         do {
3600                 idx = NEXT_TX(rp, idx);
3601                 len -= MAX_TX_DESC_LEN;
3602         } while (len > 0);
3603
3604         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3605                 tb = &rp->tx_buffs[idx];
3606                 BUG_ON(tb->skb != NULL);
3607                 np->ops->unmap_page(np->device, tb->mapping,
3608                                     skb_shinfo(skb)->frags[i].size,
3609                                     DMA_TO_DEVICE);
3610                 idx = NEXT_TX(rp, idx);
3611         }
3612
3613         dev_kfree_skb(skb);
3614
3615         return idx;
3616 }
3617
3618 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3619
3620 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3621 {
3622         struct netdev_queue *txq;
3623         u16 pkt_cnt, tmp;
3624         int cons, index;
3625         u64 cs;
3626
3627         index = (rp - np->tx_rings);
3628         txq = netdev_get_tx_queue(np->dev, index);
3629
3630         cs = rp->tx_cs;
3631         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3632                 goto out;
3633
3634         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3635         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3636                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3637
3638         rp->last_pkt_cnt = tmp;
3639
3640         cons = rp->cons;
3641
3642         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3643                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3644
3645         while (pkt_cnt--)
3646                 cons = release_tx_packet(np, rp, cons);
3647
3648         rp->cons = cons;
3649         smp_mb();
3650
3651 out:
3652         if (unlikely(netif_tx_queue_stopped(txq) &&
3653                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3654                 __netif_tx_lock(txq, smp_processor_id());
3655                 if (netif_tx_queue_stopped(txq) &&
3656                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3657                         netif_tx_wake_queue(txq);
3658                 __netif_tx_unlock(txq);
3659         }
3660 }
3661
3662 static inline void niu_sync_rx_discard_stats(struct niu *np,
3663                                              struct rx_ring_info *rp,
3664                                              const int limit)
3665 {
3666         /* This elaborate scheme is needed for reading the RX discard
3667          * counters, as they are only 16-bit and can overflow quickly,
3668          * and because the overflow indication bit is not usable as
3669          * the counter value does not wrap, but remains at max value
3670          * 0xFFFF.
3671          *
3672          * In theory and in practice counters can be lost in between
3673          * reading nr64() and clearing the counter nw64().  For this
3674          * reason, the number of counter clearings nw64() is
3675          * limited/reduced though the limit parameter.
3676          */
3677         int rx_channel = rp->rx_channel;
3678         u32 misc, wred;
3679
3680         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3681          * following discard events: IPP (Input Port Process),
3682          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3683          * Block Ring) prefetch buffer is empty.
3684          */
3685         misc = nr64(RXMISC(rx_channel));
3686         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3687                 nw64(RXMISC(rx_channel), 0);
3688                 rp->rx_errors += misc & RXMISC_COUNT;
3689
3690                 if (unlikely(misc & RXMISC_OFLOW))
3691                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3692                                 rx_channel);
3693
3694                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3695                              "rx-%d: MISC drop=%u over=%u\n",
3696                              rx_channel, misc, misc-limit);
3697         }
3698
3699         /* WRED (Weighted Random Early Discard) by hardware */
3700         wred = nr64(RED_DIS_CNT(rx_channel));
3701         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3702                 nw64(RED_DIS_CNT(rx_channel), 0);
3703                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3704
3705                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3706                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3707
3708                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3709                              "rx-%d: WRED drop=%u over=%u\n",
3710                              rx_channel, wred, wred-limit);
3711         }
3712 }
3713
3714 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3715                        struct rx_ring_info *rp, int budget)
3716 {
3717         int qlen, rcr_done = 0, work_done = 0;
3718         struct rxdma_mailbox *mbox = rp->mbox;
3719         u64 stat;
3720
3721 #if 1
3722         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3723         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3724 #else
3725         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3726         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3727 #endif
3728         mbox->rx_dma_ctl_stat = 0;
3729         mbox->rcrstat_a = 0;
3730
3731         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3732                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3733                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3734
3735         rcr_done = work_done = 0;
3736         qlen = min(qlen, budget);
3737         while (work_done < qlen) {
3738                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3739                 work_done++;
3740         }
3741
3742         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3743                 unsigned int i;
3744
3745                 for (i = 0; i < rp->rbr_refill_pending; i++)
3746                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3747                 rp->rbr_refill_pending = 0;
3748         }
3749
3750         stat = (RX_DMA_CTL_STAT_MEX |
3751                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3752                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3753
3754         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3755
3756         /* Only sync discards stats when qlen indicate potential for drops */
3757         if (qlen > 10)
3758                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3759
3760         return work_done;
3761 }
3762
3763 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3764 {
3765         u64 v0 = lp->v0;
3766         u32 tx_vec = (v0 >> 32);
3767         u32 rx_vec = (v0 & 0xffffffff);
3768         int i, work_done = 0;
3769
3770         netif_printk(np, intr, KERN_DEBUG, np->dev,
3771                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3772
3773         for (i = 0; i < np->num_tx_rings; i++) {
3774                 struct tx_ring_info *rp = &np->tx_rings[i];
3775                 if (tx_vec & (1 << rp->tx_channel))
3776                         niu_tx_work(np, rp);
3777                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3778         }
3779
3780         for (i = 0; i < np->num_rx_rings; i++) {
3781                 struct rx_ring_info *rp = &np->rx_rings[i];
3782
3783                 if (rx_vec & (1 << rp->rx_channel)) {
3784                         int this_work_done;
3785
3786                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3787                                                      budget);
3788
3789                         budget -= this_work_done;
3790                         work_done += this_work_done;
3791                 }
3792                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3793         }
3794
3795         return work_done;
3796 }
3797
3798 static int niu_poll(struct napi_struct *napi, int budget)
3799 {
3800         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3801         struct niu *np = lp->np;
3802         int work_done;
3803
3804         work_done = niu_poll_core(np, lp, budget);
3805
3806         if (work_done < budget) {
3807                 napi_complete(napi);
3808                 niu_ldg_rearm(np, lp, 1);
3809         }
3810         return work_done;
3811 }
3812
3813 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3814                                   u64 stat)
3815 {
3816         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3817
3818         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3819                 pr_cont("RBR_TMOUT ");
3820         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3821                 pr_cont("RSP_CNT ");
3822         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3823                 pr_cont("BYTE_EN_BUS ");
3824         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3825                 pr_cont("RSP_DAT ");
3826         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3827                 pr_cont("RCR_ACK ");
3828         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3829                 pr_cont("RCR_SHA_PAR ");
3830         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3831                 pr_cont("RBR_PRE_PAR ");
3832         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3833                 pr_cont("CONFIG ");
3834         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3835                 pr_cont("RCRINCON ");
3836         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3837                 pr_cont("RCRFULL ");
3838         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3839                 pr_cont("RBRFULL ");
3840         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3841                 pr_cont("RBRLOGPAGE ");
3842         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3843                 pr_cont("CFIGLOGPAGE ");
3844         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3845                 pr_cont("DC_FIDO ");
3846
3847         pr_cont(")\n");
3848 }
3849
3850 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3851 {
3852         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3853         int err = 0;
3854
3855
3856         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3857                     RX_DMA_CTL_STAT_PORT_FATAL))
3858                 err = -EINVAL;
3859
3860         if (err) {
3861                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3862                            rp->rx_channel,
3863                            (unsigned long long) stat);
3864
3865                 niu_log_rxchan_errors(np, rp, stat);
3866         }
3867
3868         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3869              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3870
3871         return err;
3872 }
3873
3874 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3875                                   u64 cs)
3876 {
3877         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3878
3879         if (cs & TX_CS_MBOX_ERR)
3880                 pr_cont("MBOX ");
3881         if (cs & TX_CS_PKT_SIZE_ERR)
3882                 pr_cont("PKT_SIZE ");
3883         if (cs & TX_CS_TX_RING_OFLOW)
3884                 pr_cont("TX_RING_OFLOW ");
3885         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3886                 pr_cont("PREF_BUF_PAR ");
3887         if (cs & TX_CS_NACK_PREF)
3888                 pr_cont("NACK_PREF ");
3889         if (cs & TX_CS_NACK_PKT_RD)
3890                 pr_cont("NACK_PKT_RD ");
3891         if (cs & TX_CS_CONF_PART_ERR)
3892                 pr_cont("CONF_PART ");
3893         if (cs & TX_CS_PKT_PRT_ERR)
3894                 pr_cont("PKT_PTR ");
3895
3896         pr_cont(")\n");
3897 }
3898
3899 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3900 {
3901         u64 cs, logh, logl;
3902
3903         cs = nr64(TX_CS(rp->tx_channel));
3904         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3905         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3906
3907         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3908                    rp->tx_channel,
3909                    (unsigned long long)cs,
3910                    (unsigned long long)logh,
3911                    (unsigned long long)logl);
3912
3913         niu_log_txchan_errors(np, rp, cs);
3914
3915         return -ENODEV;
3916 }
3917
3918 static int niu_mif_interrupt(struct niu *np)
3919 {
3920         u64 mif_status = nr64(MIF_STATUS);
3921         int phy_mdint = 0;
3922
3923         if (np->flags & NIU_FLAGS_XMAC) {
3924                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3925
3926                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3927                         phy_mdint = 1;
3928         }
3929
3930         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3931                    (unsigned long long)mif_status, phy_mdint);
3932
3933         return -ENODEV;
3934 }
3935
3936 static void niu_xmac_interrupt(struct niu *np)
3937 {
3938         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3939         u64 val;
3940
3941         val = nr64_mac(XTXMAC_STATUS);
3942         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3943                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3944         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3945                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3946         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3947                 mp->tx_fifo_errors++;
3948         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3949                 mp->tx_overflow_errors++;
3950         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3951                 mp->tx_max_pkt_size_errors++;
3952         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3953                 mp->tx_underflow_errors++;
3954
3955         val = nr64_mac(XRXMAC_STATUS);
3956         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3957                 mp->rx_local_faults++;
3958         if (val & XRXMAC_STATUS_RFLT_DET)
3959                 mp->rx_remote_faults++;
3960         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3961                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3962         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3963                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3964         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3965                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3966         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3967                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3968         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3969                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3970         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3971                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3972         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3973                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3974         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3975                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3976         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3977                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3978         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3979                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3980         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3981                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3982         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3983                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3984         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3985                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3986         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3987                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3988         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3989                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3990         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3991                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3992         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3993                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3994         if (val & XRXMAC_STATUS_RXUFLOW)
3995                 mp->rx_underflows++;
3996         if (val & XRXMAC_STATUS_RXOFLOW)
3997                 mp->rx_overflows++;
3998
3999         val = nr64_mac(XMAC_FC_STAT);
4000         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4001                 mp->pause_off_state++;
4002         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4003                 mp->pause_on_state++;
4004         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4005                 mp->pause_received++;
4006 }
4007
4008 static void niu_bmac_interrupt(struct niu *np)
4009 {
4010         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4011         u64 val;
4012
4013         val = nr64_mac(BTXMAC_STATUS);
4014         if (val & BTXMAC_STATUS_UNDERRUN)
4015                 mp->tx_underflow_errors++;
4016         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4017                 mp->tx_max_pkt_size_errors++;
4018         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4019                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4020         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4021                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4022
4023         val = nr64_mac(BRXMAC_STATUS);
4024         if (val & BRXMAC_STATUS_OVERFLOW)
4025                 mp->rx_overflows++;
4026         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4027                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4028         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4029                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4030         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4031                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4032         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4033                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4034
4035         val = nr64_mac(BMAC_CTRL_STATUS);
4036         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4037                 mp->pause_off_state++;
4038         if (val & BMAC_CTRL_STATUS_PAUSE)
4039                 mp->pause_on_state++;
4040         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4041                 mp->pause_received++;
4042 }
4043
4044 static int niu_mac_interrupt(struct niu *np)
4045 {
4046         if (np->flags & NIU_FLAGS_XMAC)
4047                 niu_xmac_interrupt(np);
4048         else
4049                 niu_bmac_interrupt(np);
4050
4051         return 0;
4052 }
4053
4054 static void niu_log_device_error(struct niu *np, u64 stat)
4055 {
4056         netdev_err(np->dev, "Core device errors ( ");
4057
4058         if (stat & SYS_ERR_MASK_META2)
4059                 pr_cont("META2 ");
4060         if (stat & SYS_ERR_MASK_META1)
4061                 pr_cont("META1 ");
4062         if (stat & SYS_ERR_MASK_PEU)
4063                 pr_cont("PEU ");
4064         if (stat & SYS_ERR_MASK_TXC)
4065                 pr_cont("TXC ");
4066         if (stat & SYS_ERR_MASK_RDMC)
4067                 pr_cont("RDMC ");
4068         if (stat & SYS_ERR_MASK_TDMC)
4069                 pr_cont("TDMC ");
4070         if (stat & SYS_ERR_MASK_ZCP)
4071                 pr_cont("ZCP ");
4072         if (stat & SYS_ERR_MASK_FFLP)
4073                 pr_cont("FFLP ");
4074         if (stat & SYS_ERR_MASK_IPP)
4075                 pr_cont("IPP ");
4076         if (stat & SYS_ERR_MASK_MAC)
4077                 pr_cont("MAC ");
4078         if (stat & SYS_ERR_MASK_SMX)
4079                 pr_cont("SMX ");
4080
4081         pr_cont(")\n");
4082 }
4083
4084 static int niu_device_error(struct niu *np)
4085 {
4086         u64 stat = nr64(SYS_ERR_STAT);
4087
4088         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4089                    (unsigned long long)stat);
4090
4091         niu_log_device_error(np, stat);
4092
4093         return -ENODEV;
4094 }
4095
4096 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4097                               u64 v0, u64 v1, u64 v2)
4098 {
4099
4100         int i, err = 0;
4101
4102         lp->v0 = v0;
4103         lp->v1 = v1;
4104         lp->v2 = v2;
4105
4106         if (v1 & 0x00000000ffffffffULL) {
4107                 u32 rx_vec = (v1 & 0xffffffff);
4108
4109                 for (i = 0; i < np->num_rx_rings; i++) {
4110                         struct rx_ring_info *rp = &np->rx_rings[i];
4111
4112                         if (rx_vec & (1 << rp->rx_channel)) {
4113                                 int r = niu_rx_error(np, rp);
4114                                 if (r) {
4115                                         err = r;
4116                                 } else {
4117                                         if (!v0)
4118                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4119                                                      RX_DMA_CTL_STAT_MEX);
4120                                 }
4121                         }
4122                 }
4123         }
4124         if (v1 & 0x7fffffff00000000ULL) {
4125                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4126
4127                 for (i = 0; i < np->num_tx_rings; i++) {
4128                         struct tx_ring_info *rp = &np->tx_rings[i];
4129
4130                         if (tx_vec & (1 << rp->tx_channel)) {
4131                                 int r = niu_tx_error(np, rp);
4132                                 if (r)
4133                                         err = r;
4134                         }
4135                 }
4136         }
4137         if ((v0 | v1) & 0x8000000000000000ULL) {
4138                 int r = niu_mif_interrupt(np);
4139                 if (r)
4140                         err = r;
4141         }
4142         if (v2) {
4143                 if (v2 & 0x01ef) {
4144                         int r = niu_mac_interrupt(np);
4145                         if (r)
4146                                 err = r;
4147                 }
4148                 if (v2 & 0x0210) {
4149                         int r = niu_device_error(np);
4150                         if (r)
4151                                 err = r;
4152                 }
4153         }
4154
4155         if (err)
4156                 niu_enable_interrupts(np, 0);
4157
4158         return err;
4159 }
4160
4161 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4162                             int ldn)
4163 {
4164         struct rxdma_mailbox *mbox = rp->mbox;
4165         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4166
4167         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4168                       RX_DMA_CTL_STAT_RCRTO);
4169         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4170
4171         netif_printk(np, intr, KERN_DEBUG, np->dev,
4172                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4173 }
4174
4175 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4176                             int ldn)
4177 {
4178         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4179
4180         netif_printk(np, intr, KERN_DEBUG, np->dev,
4181                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4182 }
4183
4184 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4185 {
4186         struct niu_parent *parent = np->parent;
4187         u32 rx_vec, tx_vec;
4188         int i;
4189
4190         tx_vec = (v0 >> 32);
4191         rx_vec = (v0 & 0xffffffff);
4192
4193         for (i = 0; i < np->num_rx_rings; i++) {
4194                 struct rx_ring_info *rp = &np->rx_rings[i];
4195                 int ldn = LDN_RXDMA(rp->rx_channel);
4196
4197                 if (parent->ldg_map[ldn] != ldg)
4198                         continue;
4199
4200                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4201                 if (rx_vec & (1 << rp->rx_channel))
4202                         niu_rxchan_intr(np, rp, ldn);
4203         }
4204
4205         for (i = 0; i < np->num_tx_rings; i++) {
4206                 struct tx_ring_info *rp = &np->tx_rings[i];
4207                 int ldn = LDN_TXDMA(rp->tx_channel);
4208
4209                 if (parent->ldg_map[ldn] != ldg)
4210                         continue;
4211
4212                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4213                 if (tx_vec & (1 << rp->tx_channel))
4214                         niu_txchan_intr(np, rp, ldn);
4215         }
4216 }
4217
4218 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4219                               u64 v0, u64 v1, u64 v2)
4220 {
4221         if (likely(napi_schedule_prep(&lp->napi))) {
4222                 lp->v0 = v0;
4223                 lp->v1 = v1;
4224                 lp->v2 = v2;
4225                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4226                 __napi_schedule(&lp->napi);
4227         }
4228 }
4229
4230 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4231 {
4232         struct niu_ldg *lp = dev_id;
4233         struct niu *np = lp->np;
4234         int ldg = lp->ldg_num;
4235         unsigned long flags;
4236         u64 v0, v1, v2;
4237
4238         if (netif_msg_intr(np))
4239                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4240                        __func__, lp, ldg);
4241
4242         spin_lock_irqsave(&np->lock, flags);
4243
4244         v0 = nr64(LDSV0(ldg));
4245         v1 = nr64(LDSV1(ldg));
4246         v2 = nr64(LDSV2(ldg));
4247
4248         if (netif_msg_intr(np))
4249                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]",
4250                        (unsigned long long) v0,
4251                        (unsigned long long) v1,
4252                        (unsigned long long) v2);
4253
4254         pr_cont("\n");
4255
4256         if (unlikely(!v0 && !v1 && !v2)) {
4257                 spin_unlock_irqrestore(&np->lock, flags);
4258                 return IRQ_NONE;
4259         }
4260
4261         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4262                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4263                 if (err)
4264                         goto out;
4265         }
4266         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4267                 niu_schedule_napi(np, lp, v0, v1, v2);
4268         else
4269                 niu_ldg_rearm(np, lp, 1);
4270 out:
4271         spin_unlock_irqrestore(&np->lock, flags);
4272
4273         return IRQ_HANDLED;
4274 }
4275
4276 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4277 {
4278         if (rp->mbox) {
4279                 np->ops->free_coherent(np->device,
4280                                        sizeof(struct rxdma_mailbox),
4281                                        rp->mbox, rp->mbox_dma);
4282                 rp->mbox = NULL;
4283         }
4284         if (rp->rcr) {
4285                 np->ops->free_coherent(np->device,
4286                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4287                                        rp->rcr, rp->rcr_dma);
4288                 rp->rcr = NULL;
4289                 rp->rcr_table_size = 0;
4290                 rp->rcr_index = 0;
4291         }
4292         if (rp->rbr) {
4293                 niu_rbr_free(np, rp);
4294
4295                 np->ops->free_coherent(np->device,
4296                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4297                                        rp->rbr, rp->rbr_dma);
4298                 rp->rbr = NULL;
4299                 rp->rbr_table_size = 0;
4300                 rp->rbr_index = 0;
4301         }
4302         kfree(rp->rxhash);
4303         rp->rxhash = NULL;
4304 }
4305
4306 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4307 {
4308         if (rp->mbox) {
4309                 np->ops->free_coherent(np->device,
4310                                        sizeof(struct txdma_mailbox),
4311                                        rp->mbox, rp->mbox_dma);
4312                 rp->mbox = NULL;
4313         }
4314         if (rp->descr) {
4315                 int i;
4316
4317                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4318                         if (rp->tx_buffs[i].skb)
4319                                 (void) release_tx_packet(np, rp, i);
4320                 }
4321
4322                 np->ops->free_coherent(np->device,
4323                                        MAX_TX_RING_SIZE * sizeof(__le64),
4324                                        rp->descr, rp->descr_dma);
4325                 rp->descr = NULL;
4326                 rp->pending = 0;
4327                 rp->prod = 0;
4328                 rp->cons = 0;
4329                 rp->wrap_bit = 0;
4330         }
4331 }
4332
4333 static void niu_free_channels(struct niu *np)
4334 {
4335         int i;
4336
4337         if (np->rx_rings) {
4338                 for (i = 0; i < np->num_rx_rings; i++) {
4339                         struct rx_ring_info *rp = &np->rx_rings[i];
4340
4341                         niu_free_rx_ring_info(np, rp);
4342                 }
4343                 kfree(np->rx_rings);
4344                 np->rx_rings = NULL;
4345                 np->num_rx_rings = 0;
4346         }
4347
4348         if (np->tx_rings) {
4349                 for (i = 0; i < np->num_tx_rings; i++) {
4350                         struct tx_ring_info *rp = &np->tx_rings[i];
4351
4352                         niu_free_tx_ring_info(np, rp);
4353                 }
4354                 kfree(np->tx_rings);
4355                 np->tx_rings = NULL;
4356                 np->num_tx_rings = 0;
4357         }
4358 }
4359
4360 static int niu_alloc_rx_ring_info(struct niu *np,
4361                                   struct rx_ring_info *rp)
4362 {
4363         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4364
4365         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4366                              GFP_KERNEL);
4367         if (!rp->rxhash)
4368                 return -ENOMEM;
4369
4370         rp->mbox = np->ops->alloc_coherent(np->device,
4371                                            sizeof(struct rxdma_mailbox),
4372                                            &rp->mbox_dma, GFP_KERNEL);
4373         if (!rp->mbox)
4374                 return -ENOMEM;
4375         if ((unsigned long)rp->mbox & (64UL - 1)) {
4376                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4377                            rp->mbox);
4378                 return -EINVAL;
4379         }
4380
4381         rp->rcr = np->ops->alloc_coherent(np->device,
4382                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4383                                           &rp->rcr_dma, GFP_KERNEL);
4384         if (!rp->rcr)
4385                 return -ENOMEM;
4386         if ((unsigned long)rp->rcr & (64UL - 1)) {
4387                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4388                            rp->rcr);
4389                 return -EINVAL;
4390         }
4391         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4392         rp->rcr_index = 0;
4393
4394         rp->rbr = np->ops->alloc_coherent(np->device,
4395                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4396                                           &rp->rbr_dma, GFP_KERNEL);
4397         if (!rp->rbr)
4398                 return -ENOMEM;
4399         if ((unsigned long)rp->rbr & (64UL - 1)) {
4400                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4401                            rp->rbr);
4402                 return -EINVAL;
4403         }
4404         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4405         rp->rbr_index = 0;
4406         rp->rbr_pending = 0;
4407
4408         return 0;
4409 }
4410
4411 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4412 {
4413         int mtu = np->dev->mtu;
4414
4415         /* These values are recommended by the HW designers for fair
4416          * utilization of DRR amongst the rings.
4417          */
4418         rp->max_burst = mtu + 32;
4419         if (rp->max_burst > 4096)
4420                 rp->max_burst = 4096;
4421 }
4422
4423 static int niu_alloc_tx_ring_info(struct niu *np,
4424                                   struct tx_ring_info *rp)
4425 {
4426         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4427
4428         rp->mbox = np->ops->alloc_coherent(np->device,
4429                                            sizeof(struct txdma_mailbox),
4430                                            &rp->mbox_dma, GFP_KERNEL);
4431         if (!rp->mbox)
4432                 return -ENOMEM;
4433         if ((unsigned long)rp->mbox & (64UL - 1)) {
4434                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4435                            rp->mbox);
4436                 return -EINVAL;
4437         }
4438
4439         rp->descr = np->ops->alloc_coherent(np->device,
4440                                             MAX_TX_RING_SIZE * sizeof(__le64),
4441                                             &rp->descr_dma, GFP_KERNEL);
4442         if (!rp->descr)
4443                 return -ENOMEM;
4444         if ((unsigned long)rp->descr & (64UL - 1)) {
4445                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4446                            rp->descr);
4447                 return -EINVAL;
4448         }
4449
4450         rp->pending = MAX_TX_RING_SIZE;
4451         rp->prod = 0;
4452         rp->cons = 0;
4453         rp->wrap_bit = 0;
4454
4455         /* XXX make these configurable... XXX */
4456         rp->mark_freq = rp->pending / 4;
4457
4458         niu_set_max_burst(np, rp);
4459
4460         return 0;
4461 }
4462
4463 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4464 {
4465         u16 bss;
4466
4467         bss = min(PAGE_SHIFT, 15);
4468
4469         rp->rbr_block_size = 1 << bss;
4470         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4471
4472         rp->rbr_sizes[0] = 256;
4473         rp->rbr_sizes[1] = 1024;
4474         if (np->dev->mtu > ETH_DATA_LEN) {
4475                 switch (PAGE_SIZE) {
4476                 case 4 * 1024:
4477                         rp->rbr_sizes[2] = 4096;
4478                         break;
4479
4480                 default:
4481                         rp->rbr_sizes[2] = 8192;
4482                         break;
4483                 }
4484         } else {
4485                 rp->rbr_sizes[2] = 2048;
4486         }
4487         rp->rbr_sizes[3] = rp->rbr_block_size;
4488 }
4489
4490 static int niu_alloc_channels(struct niu *np)
4491 {
4492         struct niu_parent *parent = np->parent;
4493         int first_rx_channel, first_tx_channel;
4494         int i, port, err;
4495
4496         port = np->port;
4497         first_rx_channel = first_tx_channel = 0;
4498         for (i = 0; i < port; i++) {
4499                 first_rx_channel += parent->rxchan_per_port[i];
4500                 first_tx_channel += parent->txchan_per_port[i];
4501         }
4502
4503         np->num_rx_rings = parent->rxchan_per_port[port];
4504         np->num_tx_rings = parent->txchan_per_port[port];
4505
4506         np->dev->real_num_tx_queues = np->num_tx_rings;
4507
4508         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4509                                GFP_KERNEL);
4510         err = -ENOMEM;
4511         if (!np->rx_rings)
4512                 goto out_err;
4513
4514         for (i = 0; i < np->num_rx_rings; i++) {
4515                 struct rx_ring_info *rp = &np->rx_rings[i];
4516
4517                 rp->np = np;
4518                 rp->rx_channel = first_rx_channel + i;
4519
4520                 err = niu_alloc_rx_ring_info(np, rp);
4521                 if (err)
4522                         goto out_err;
4523
4524                 niu_size_rbr(np, rp);
4525
4526                 /* XXX better defaults, configurable, etc... XXX */
4527                 rp->nonsyn_window = 64;
4528                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4529                 rp->syn_window = 64;
4530                 rp->syn_threshold = rp->rcr_table_size - 64;
4531                 rp->rcr_pkt_threshold = 16;
4532                 rp->rcr_timeout = 8;
4533                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4534                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4535                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4536
4537                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4538                 if (err)
4539                         return err;
4540         }
4541
4542         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4543                                GFP_KERNEL);
4544         err = -ENOMEM;
4545         if (!np->tx_rings)
4546                 goto out_err;
4547
4548         for (i = 0; i < np->num_tx_rings; i++) {
4549                 struct tx_ring_info *rp = &np->tx_rings[i];
4550
4551                 rp->np = np;
4552                 rp->tx_channel = first_tx_channel + i;
4553
4554                 err = niu_alloc_tx_ring_info(np, rp);
4555                 if (err)
4556                         goto out_err;
4557         }
4558
4559         return 0;
4560
4561 out_err:
4562         niu_free_channels(np);
4563         return err;
4564 }
4565
4566 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4567 {
4568         int limit = 1000;
4569
4570         while (--limit > 0) {
4571                 u64 val = nr64(TX_CS(channel));
4572                 if (val & TX_CS_SNG_STATE)
4573                         return 0;
4574         }
4575         return -ENODEV;
4576 }
4577
4578 static int niu_tx_channel_stop(struct niu *np, int channel)
4579 {
4580         u64 val = nr64(TX_CS(channel));
4581
4582         val |= TX_CS_STOP_N_GO;
4583         nw64(TX_CS(channel), val);
4584
4585         return niu_tx_cs_sng_poll(np, channel);
4586 }
4587
4588 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4589 {
4590         int limit = 1000;
4591
4592         while (--limit > 0) {
4593                 u64 val = nr64(TX_CS(channel));
4594                 if (!(val & TX_CS_RST))
4595                         return 0;
4596         }
4597         return -ENODEV;
4598 }
4599
4600 static int niu_tx_channel_reset(struct niu *np, int channel)
4601 {
4602         u64 val = nr64(TX_CS(channel));
4603         int err;
4604
4605         val |= TX_CS_RST;
4606         nw64(TX_CS(channel), val);
4607
4608         err = niu_tx_cs_reset_poll(np, channel);
4609         if (!err)
4610                 nw64(TX_RING_KICK(channel), 0);
4611
4612         return err;
4613 }
4614
4615 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4616 {
4617         u64 val;
4618
4619         nw64(TX_LOG_MASK1(channel), 0);
4620         nw64(TX_LOG_VAL1(channel), 0);
4621         nw64(TX_LOG_MASK2(channel), 0);
4622         nw64(TX_LOG_VAL2(channel), 0);
4623         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4624         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4625         nw64(TX_LOG_PAGE_HDL(channel), 0);
4626
4627         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4628         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4629         nw64(TX_LOG_PAGE_VLD(channel), val);
4630
4631         /* XXX TXDMA 32bit mode? XXX */
4632
4633         return 0;
4634 }
4635
4636 static void niu_txc_enable_port(struct niu *np, int on)
4637 {
4638         unsigned long flags;
4639         u64 val, mask;
4640
4641         niu_lock_parent(np, flags);
4642         val = nr64(TXC_CONTROL);
4643         mask = (u64)1 << np->port;
4644         if (on) {
4645                 val |= TXC_CONTROL_ENABLE | mask;
4646         } else {
4647                 val &= ~mask;
4648                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4649                         val &= ~TXC_CONTROL_ENABLE;
4650         }
4651         nw64(TXC_CONTROL, val);
4652         niu_unlock_parent(np, flags);
4653 }
4654
4655 static void niu_txc_set_imask(struct niu *np, u64 imask)
4656 {
4657         unsigned long flags;
4658         u64 val;
4659
4660         niu_lock_parent(np, flags);
4661         val = nr64(TXC_INT_MASK);
4662         val &= ~TXC_INT_MASK_VAL(np->port);
4663         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4664         niu_unlock_parent(np, flags);
4665 }
4666
4667 static void niu_txc_port_dma_enable(struct niu *np, int on)
4668 {
4669         u64 val = 0;
4670
4671         if (on) {
4672                 int i;
4673
4674                 for (i = 0; i < np->num_tx_rings; i++)
4675                         val |= (1 << np->tx_rings[i].tx_channel);
4676         }
4677         nw64(TXC_PORT_DMA(np->port), val);
4678 }
4679
4680 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4681 {
4682         int err, channel = rp->tx_channel;
4683         u64 val, ring_len;
4684
4685         err = niu_tx_channel_stop(np, channel);
4686         if (err)
4687                 return err;
4688
4689         err = niu_tx_channel_reset(np, channel);
4690         if (err)
4691                 return err;
4692
4693         err = niu_tx_channel_lpage_init(np, channel);
4694         if (err)
4695                 return err;
4696
4697         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4698         nw64(TX_ENT_MSK(channel), 0);
4699
4700         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4701                               TX_RNG_CFIG_STADDR)) {
4702                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4703                            channel, (unsigned long long)rp->descr_dma);
4704                 return -EINVAL;
4705         }
4706
4707         /* The length field in TX_RNG_CFIG is measured in 64-byte
4708          * blocks.  rp->pending is the number of TX descriptors in
4709          * our ring, 8 bytes each, thus we divide by 8 bytes more
4710          * to get the proper value the chip wants.
4711          */
4712         ring_len = (rp->pending / 8);
4713
4714         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4715                rp->descr_dma);
4716         nw64(TX_RNG_CFIG(channel), val);
4717
4718         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4719             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4720                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4721                             channel, (unsigned long long)rp->mbox_dma);
4722                 return -EINVAL;
4723         }
4724         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4725         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4726
4727         nw64(TX_CS(channel), 0);
4728
4729         rp->last_pkt_cnt = 0;
4730
4731         return 0;
4732 }
4733
4734 static void niu_init_rdc_groups(struct niu *np)
4735 {
4736         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4737         int i, first_table_num = tp->first_table_num;
4738
4739         for (i = 0; i < tp->num_tables; i++) {
4740                 struct rdc_table *tbl = &tp->tables[i];
4741                 int this_table = first_table_num + i;
4742                 int slot;
4743
4744                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4745                         nw64(RDC_TBL(this_table, slot),
4746                              tbl->rxdma_channel[slot]);
4747         }
4748
4749         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4750 }
4751
4752 static void niu_init_drr_weight(struct niu *np)
4753 {
4754         int type = phy_decode(np->parent->port_phy, np->port);
4755         u64 val;
4756
4757         switch (type) {
4758         case PORT_TYPE_10G:
4759                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4760                 break;
4761
4762         case PORT_TYPE_1G:
4763         default:
4764                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4765                 break;
4766         }
4767         nw64(PT_DRR_WT(np->port), val);
4768 }
4769
4770 static int niu_init_hostinfo(struct niu *np)
4771 {
4772         struct niu_parent *parent = np->parent;
4773         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4774         int i, err, num_alt = niu_num_alt_addr(np);
4775         int first_rdc_table = tp->first_table_num;
4776
4777         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4778         if (err)
4779                 return err;
4780
4781         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4782         if (err)
4783                 return err;
4784
4785         for (i = 0; i < num_alt; i++) {
4786                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4787                 if (err)
4788                         return err;
4789         }
4790
4791         return 0;
4792 }
4793
4794 static int niu_rx_channel_reset(struct niu *np, int channel)
4795 {
4796         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4797                                       RXDMA_CFIG1_RST, 1000, 10,
4798                                       "RXDMA_CFIG1");
4799 }
4800
4801 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4802 {
4803         u64 val;
4804
4805         nw64(RX_LOG_MASK1(channel), 0);
4806         nw64(RX_LOG_VAL1(channel), 0);
4807         nw64(RX_LOG_MASK2(channel), 0);
4808         nw64(RX_LOG_VAL2(channel), 0);
4809         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4810         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4811         nw64(RX_LOG_PAGE_HDL(channel), 0);
4812
4813         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4814         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4815         nw64(RX_LOG_PAGE_VLD(channel), val);
4816
4817         return 0;
4818 }
4819
4820 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4821 {
4822         u64 val;
4823
4824         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4825                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4826                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4827                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4828         nw64(RDC_RED_PARA(rp->rx_channel), val);
4829 }
4830
4831 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4832 {
4833         u64 val = 0;
4834
4835         *ret = 0;
4836         switch (rp->rbr_block_size) {
4837         case 4 * 1024:
4838                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839                 break;
4840         case 8 * 1024:
4841                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842                 break;
4843         case 16 * 1024:
4844                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4845                 break;
4846         case 32 * 1024:
4847                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4848                 break;
4849         default:
4850                 return -EINVAL;
4851         }
4852         val |= RBR_CFIG_B_VLD2;
4853         switch (rp->rbr_sizes[2]) {
4854         case 2 * 1024:
4855                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856                 break;
4857         case 4 * 1024:
4858                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859                 break;
4860         case 8 * 1024:
4861                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4862                 break;
4863         case 16 * 1024:
4864                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4865                 break;
4866
4867         default:
4868                 return -EINVAL;
4869         }
4870         val |= RBR_CFIG_B_VLD1;
4871         switch (rp->rbr_sizes[1]) {
4872         case 1 * 1024:
4873                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874                 break;
4875         case 2 * 1024:
4876                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877                 break;
4878         case 4 * 1024:
4879                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4880                 break;
4881         case 8 * 1024:
4882                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4883                 break;
4884
4885         default:
4886                 return -EINVAL;
4887         }
4888         val |= RBR_CFIG_B_VLD0;
4889         switch (rp->rbr_sizes[0]) {
4890         case 256:
4891                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4892                 break;
4893         case 512:
4894                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4895                 break;
4896         case 1 * 1024:
4897                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4898                 break;
4899         case 2 * 1024:
4900                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4901                 break;
4902
4903         default:
4904                 return -EINVAL;
4905         }
4906
4907         *ret = val;
4908         return 0;
4909 }
4910
4911 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4912 {
4913         u64 val = nr64(RXDMA_CFIG1(channel));
4914         int limit;
4915
4916         if (on)
4917                 val |= RXDMA_CFIG1_EN;
4918         else
4919                 val &= ~RXDMA_CFIG1_EN;
4920         nw64(RXDMA_CFIG1(channel), val);
4921
4922         limit = 1000;
4923         while (--limit > 0) {
4924                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4925                         break;
4926                 udelay(10);
4927         }
4928         if (limit <= 0)
4929                 return -ENODEV;
4930         return 0;
4931 }
4932
4933 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4934 {
4935         int err, channel = rp->rx_channel;
4936         u64 val;
4937
4938         err = niu_rx_channel_reset(np, channel);
4939         if (err)
4940                 return err;
4941
4942         err = niu_rx_channel_lpage_init(np, channel);
4943         if (err)
4944                 return err;
4945
4946         niu_rx_channel_wred_init(np, rp);
4947
4948         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4949         nw64(RX_DMA_CTL_STAT(channel),
4950              (RX_DMA_CTL_STAT_MEX |
4951               RX_DMA_CTL_STAT_RCRTHRES |
4952               RX_DMA_CTL_STAT_RCRTO |
4953               RX_DMA_CTL_STAT_RBR_EMPTY));
4954         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4955         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4956         nw64(RBR_CFIG_A(channel),
4957              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4958              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4959         err = niu_compute_rbr_cfig_b(rp, &val);
4960         if (err)
4961                 return err;
4962         nw64(RBR_CFIG_B(channel), val);
4963         nw64(RCRCFIG_A(channel),
4964              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4965              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4966         nw64(RCRCFIG_B(channel),
4967              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4968              RCRCFIG_B_ENTOUT |
4969              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4970
4971         err = niu_enable_rx_channel(np, channel, 1);
4972         if (err)
4973                 return err;
4974
4975         nw64(RBR_KICK(channel), rp->rbr_index);
4976
4977         val = nr64(RX_DMA_CTL_STAT(channel));
4978         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4979         nw64(RX_DMA_CTL_STAT(channel), val);
4980
4981         return 0;
4982 }
4983
4984 static int niu_init_rx_channels(struct niu *np)
4985 {
4986         unsigned long flags;
4987         u64 seed = jiffies_64;
4988         int err, i;
4989
4990         niu_lock_parent(np, flags);
4991         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4992         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4993         niu_unlock_parent(np, flags);
4994
4995         /* XXX RXDMA 32bit mode? XXX */
4996
4997         niu_init_rdc_groups(np);
4998         niu_init_drr_weight(np);
4999
5000         err = niu_init_hostinfo(np);
5001         if (err)
5002                 return err;
5003
5004         for (i = 0; i < np->num_rx_rings; i++) {
5005                 struct rx_ring_info *rp = &np->rx_rings[i];
5006
5007                 err = niu_init_one_rx_channel(np, rp);
5008                 if (err)
5009                         return err;
5010         }
5011
5012         return 0;
5013 }
5014
5015 static int niu_set_ip_frag_rule(struct niu *np)
5016 {
5017         struct niu_parent *parent = np->parent;
5018         struct niu_classifier *cp = &np->clas;
5019         struct niu_tcam_entry *tp;
5020         int index, err;
5021
5022         index = cp->tcam_top;
5023         tp = &parent->tcam[index];
5024
5025         /* Note that the noport bit is the same in both ipv4 and
5026          * ipv6 format TCAM entries.
5027          */
5028         memset(tp, 0, sizeof(*tp));
5029         tp->key[1] = TCAM_V4KEY1_NOPORT;
5030         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5031         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5032                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5033         err = tcam_write(np, index, tp->key, tp->key_mask);
5034         if (err)
5035                 return err;
5036         err = tcam_assoc_write(np, index, tp->assoc_data);
5037         if (err)
5038                 return err;
5039         tp->valid = 1;
5040         cp->tcam_valid_entries++;
5041
5042         return 0;
5043 }
5044
5045 static int niu_init_classifier_hw(struct niu *np)
5046 {
5047         struct niu_parent *parent = np->parent;
5048         struct niu_classifier *cp = &np->clas;
5049         int i, err;
5050
5051         nw64(H1POLY, cp->h1_init);
5052         nw64(H2POLY, cp->h2_init);
5053
5054         err = niu_init_hostinfo(np);
5055         if (err)
5056                 return err;
5057
5058         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5059                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5060
5061                 vlan_tbl_write(np, i, np->port,
5062                                vp->vlan_pref, vp->rdc_num);
5063         }
5064
5065         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5066                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5067
5068                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5069                                                 ap->rdc_num, ap->mac_pref);
5070                 if (err)
5071                         return err;
5072         }
5073
5074         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5075                 int index = i - CLASS_CODE_USER_PROG1;
5076
5077                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5078                 if (err)
5079                         return err;
5080                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5081                 if (err)
5082                         return err;
5083         }
5084
5085         err = niu_set_ip_frag_rule(np);
5086         if (err)
5087                 return err;
5088
5089         tcam_enable(np, 1);
5090
5091         return 0;
5092 }
5093
5094 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5095 {
5096         nw64(ZCP_RAM_DATA0, data[0]);
5097         nw64(ZCP_RAM_DATA1, data[1]);
5098         nw64(ZCP_RAM_DATA2, data[2]);
5099         nw64(ZCP_RAM_DATA3, data[3]);
5100         nw64(ZCP_RAM_DATA4, data[4]);
5101         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5102         nw64(ZCP_RAM_ACC,
5103              (ZCP_RAM_ACC_WRITE |
5104               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5105               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5106
5107         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5108                                    1000, 100);
5109 }
5110
5111 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5112 {
5113         int err;
5114
5115         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5116                                   1000, 100);
5117         if (err) {
5118                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5119                            (unsigned long long)nr64(ZCP_RAM_ACC));
5120                 return err;
5121         }
5122
5123         nw64(ZCP_RAM_ACC,
5124              (ZCP_RAM_ACC_READ |
5125               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5126               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5127
5128         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5129                                   1000, 100);
5130         if (err) {
5131                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5132                            (unsigned long long)nr64(ZCP_RAM_ACC));
5133                 return err;
5134         }
5135
5136         data[0] = nr64(ZCP_RAM_DATA0);
5137         data[1] = nr64(ZCP_RAM_DATA1);
5138         data[2] = nr64(ZCP_RAM_DATA2);
5139         data[3] = nr64(ZCP_RAM_DATA3);
5140         data[4] = nr64(ZCP_RAM_DATA4);
5141
5142         return 0;
5143 }
5144
5145 static void niu_zcp_cfifo_reset(struct niu *np)
5146 {
5147         u64 val = nr64(RESET_CFIFO);
5148
5149         val |= RESET_CFIFO_RST(np->port);
5150         nw64(RESET_CFIFO, val);
5151         udelay(10);
5152
5153         val &= ~RESET_CFIFO_RST(np->port);
5154         nw64(RESET_CFIFO, val);
5155 }
5156
5157 static int niu_init_zcp(struct niu *np)
5158 {
5159         u64 data[5], rbuf[5];
5160         int i, max, err;
5161
5162         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5163                 if (np->port == 0 || np->port == 1)
5164                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5165                 else
5166                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5167         } else
5168                 max = NIU_CFIFO_ENTRIES;
5169
5170         data[0] = 0;
5171         data[1] = 0;
5172         data[2] = 0;
5173         data[3] = 0;
5174         data[4] = 0;
5175
5176         for (i = 0; i < max; i++) {
5177                 err = niu_zcp_write(np, i, data);
5178                 if (err)
5179                         return err;
5180                 err = niu_zcp_read(np, i, rbuf);
5181                 if (err)
5182                         return err;
5183         }
5184
5185         niu_zcp_cfifo_reset(np);
5186         nw64(CFIFO_ECC(np->port), 0);
5187         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5188         (void) nr64(ZCP_INT_STAT);
5189         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5190
5191         return 0;
5192 }
5193
5194 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5195 {
5196         u64 val = nr64_ipp(IPP_CFIG);
5197
5198         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5199         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5200         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5201         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5202         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5203         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5204         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5205         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5206 }
5207
5208 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5209 {
5210         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5211         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5212         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5213         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5214         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5215         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5216 }
5217
5218 static int niu_ipp_reset(struct niu *np)
5219 {
5220         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5221                                           1000, 100, "IPP_CFIG");
5222 }
5223
5224 static int niu_init_ipp(struct niu *np)
5225 {
5226         u64 data[5], rbuf[5], val;
5227         int i, max, err;
5228
5229         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5230                 if (np->port == 0 || np->port == 1)
5231                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5232                 else
5233                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5234         } else
5235                 max = NIU_DFIFO_ENTRIES;
5236
5237         data[0] = 0;
5238         data[1] = 0;
5239         data[2] = 0;
5240         data[3] = 0;
5241         data[4] = 0;
5242
5243         for (i = 0; i < max; i++) {
5244                 niu_ipp_write(np, i, data);
5245                 niu_ipp_read(np, i, rbuf);
5246         }
5247
5248         (void) nr64_ipp(IPP_INT_STAT);
5249         (void) nr64_ipp(IPP_INT_STAT);
5250
5251         err = niu_ipp_reset(np);
5252         if (err)
5253                 return err;
5254
5255         (void) nr64_ipp(IPP_PKT_DIS);
5256         (void) nr64_ipp(IPP_BAD_CS_CNT);
5257         (void) nr64_ipp(IPP_ECC);
5258
5259         (void) nr64_ipp(IPP_INT_STAT);
5260
5261         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5262
5263         val = nr64_ipp(IPP_CFIG);
5264         val &= ~IPP_CFIG_IP_MAX_PKT;
5265         val |= (IPP_CFIG_IPP_ENABLE |
5266                 IPP_CFIG_DFIFO_ECC_EN |
5267                 IPP_CFIG_DROP_BAD_CRC |
5268                 IPP_CFIG_CKSUM_EN |
5269                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5270         nw64_ipp(IPP_CFIG, val);
5271
5272         return 0;
5273 }
5274
5275 static void niu_handle_led(struct niu *np, int status)
5276 {
5277         u64 val;
5278         val = nr64_mac(XMAC_CONFIG);
5279
5280         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5281             (np->flags & NIU_FLAGS_FIBER) != 0) {
5282                 if (status) {
5283                         val |= XMAC_CONFIG_LED_POLARITY;
5284                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5285                 } else {
5286                         val |= XMAC_CONFIG_FORCE_LED_ON;
5287                         val &= ~XMAC_CONFIG_LED_POLARITY;
5288                 }
5289         }
5290
5291         nw64_mac(XMAC_CONFIG, val);
5292 }
5293
5294 static void niu_init_xif_xmac(struct niu *np)
5295 {
5296         struct niu_link_config *lp = &np->link_config;
5297         u64 val;
5298
5299         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5300                 val = nr64(MIF_CONFIG);
5301                 val |= MIF_CONFIG_ATCA_GE;
5302                 nw64(MIF_CONFIG, val);
5303         }
5304
5305         val = nr64_mac(XMAC_CONFIG);
5306         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5307
5308         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5309
5310         if (lp->loopback_mode == LOOPBACK_MAC) {
5311                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5312                 val |= XMAC_CONFIG_LOOPBACK;
5313         } else {
5314                 val &= ~XMAC_CONFIG_LOOPBACK;
5315         }
5316
5317         if (np->flags & NIU_FLAGS_10G) {
5318                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5319         } else {
5320                 val |= XMAC_CONFIG_LFS_DISABLE;
5321                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5322                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5323                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5324                 else
5325                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5326         }
5327
5328         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5329
5330         if (lp->active_speed == SPEED_100)
5331                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5332         else
5333                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5334
5335         nw64_mac(XMAC_CONFIG, val);
5336
5337         val = nr64_mac(XMAC_CONFIG);
5338         val &= ~XMAC_CONFIG_MODE_MASK;
5339         if (np->flags & NIU_FLAGS_10G) {
5340                 val |= XMAC_CONFIG_MODE_XGMII;
5341         } else {
5342                 if (lp->active_speed == SPEED_1000)
5343                         val |= XMAC_CONFIG_MODE_GMII;
5344                 else
5345                         val |= XMAC_CONFIG_MODE_MII;
5346         }
5347
5348         nw64_mac(XMAC_CONFIG, val);
5349 }
5350
5351 static void niu_init_xif_bmac(struct niu *np)
5352 {
5353         struct niu_link_config *lp = &np->link_config;
5354         u64 val;
5355
5356         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5357
5358         if (lp->loopback_mode == LOOPBACK_MAC)
5359                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5360         else
5361                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5362
5363         if (lp->active_speed == SPEED_1000)
5364                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5365         else
5366                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5367
5368         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5369                  BMAC_XIF_CONFIG_LED_POLARITY);
5370
5371         if (!(np->flags & NIU_FLAGS_10G) &&
5372             !(np->flags & NIU_FLAGS_FIBER) &&
5373             lp->active_speed == SPEED_100)
5374                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5375         else
5376                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5377
5378         nw64_mac(BMAC_XIF_CONFIG, val);
5379 }
5380
5381 static void niu_init_xif(struct niu *np)
5382 {
5383         if (np->flags & NIU_FLAGS_XMAC)
5384                 niu_init_xif_xmac(np);
5385         else
5386                 niu_init_xif_bmac(np);
5387 }
5388
5389 static void niu_pcs_mii_reset(struct niu *np)
5390 {
5391         int limit = 1000;
5392         u64 val = nr64_pcs(PCS_MII_CTL);
5393         val |= PCS_MII_CTL_RST;
5394         nw64_pcs(PCS_MII_CTL, val);
5395         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5396                 udelay(100);
5397                 val = nr64_pcs(PCS_MII_CTL);
5398         }
5399 }
5400
5401 static void niu_xpcs_reset(struct niu *np)
5402 {
5403         int limit = 1000;
5404         u64 val = nr64_xpcs(XPCS_CONTROL1);
5405         val |= XPCS_CONTROL1_RESET;
5406         nw64_xpcs(XPCS_CONTROL1, val);
5407         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5408                 udelay(100);
5409                 val = nr64_xpcs(XPCS_CONTROL1);
5410         }
5411 }
5412
5413 static int niu_init_pcs(struct niu *np)
5414 {
5415         struct niu_link_config *lp = &np->link_config;
5416         u64 val;
5417
5418         switch (np->flags & (NIU_FLAGS_10G |
5419                              NIU_FLAGS_FIBER |
5420                              NIU_FLAGS_XCVR_SERDES)) {
5421         case NIU_FLAGS_FIBER:
5422                 /* 1G fiber */
5423                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5424                 nw64_pcs(PCS_DPATH_MODE, 0);
5425                 niu_pcs_mii_reset(np);
5426                 break;
5427
5428         case NIU_FLAGS_10G:
5429         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5430         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5431                 /* 10G SERDES */
5432                 if (!(np->flags & NIU_FLAGS_XMAC))
5433                         return -EINVAL;
5434
5435                 /* 10G copper or fiber */
5436                 val = nr64_mac(XMAC_CONFIG);
5437                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5438                 nw64_mac(XMAC_CONFIG, val);
5439
5440                 niu_xpcs_reset(np);
5441
5442                 val = nr64_xpcs(XPCS_CONTROL1);
5443                 if (lp->loopback_mode == LOOPBACK_PHY)
5444                         val |= XPCS_CONTROL1_LOOPBACK;
5445                 else
5446                         val &= ~XPCS_CONTROL1_LOOPBACK;
5447                 nw64_xpcs(XPCS_CONTROL1, val);
5448
5449                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5450                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5451                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5452                 break;
5453
5454
5455         case NIU_FLAGS_XCVR_SERDES:
5456                 /* 1G SERDES */
5457                 niu_pcs_mii_reset(np);
5458                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5459                 nw64_pcs(PCS_DPATH_MODE, 0);
5460                 break;
5461
5462         case 0:
5463                 /* 1G copper */
5464         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5465                 /* 1G RGMII FIBER */
5466                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5467                 niu_pcs_mii_reset(np);
5468                 break;
5469
5470         default:
5471                 return -EINVAL;
5472         }
5473
5474         return 0;
5475 }
5476
5477 static int niu_reset_tx_xmac(struct niu *np)
5478 {
5479         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5480                                           (XTXMAC_SW_RST_REG_RS |
5481                                            XTXMAC_SW_RST_SOFT_RST),
5482                                           1000, 100, "XTXMAC_SW_RST");
5483 }
5484
5485 static int niu_reset_tx_bmac(struct niu *np)
5486 {
5487         int limit;
5488
5489         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5490         limit = 1000;
5491         while (--limit >= 0) {
5492                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5493                         break;
5494                 udelay(100);
5495         }
5496         if (limit < 0) {
5497                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5498                         np->port,
5499                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5500                 return -ENODEV;
5501         }
5502
5503         return 0;
5504 }
5505
5506 static int niu_reset_tx_mac(struct niu *np)
5507 {
5508         if (np->flags & NIU_FLAGS_XMAC)
5509                 return niu_reset_tx_xmac(np);
5510         else
5511                 return niu_reset_tx_bmac(np);
5512 }
5513
5514 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5515 {
5516         u64 val;
5517
5518         val = nr64_mac(XMAC_MIN);
5519         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5520                  XMAC_MIN_RX_MIN_PKT_SIZE);
5521         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5522         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5523         nw64_mac(XMAC_MIN, val);
5524
5525         nw64_mac(XMAC_MAX, max);
5526
5527         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5528
5529         val = nr64_mac(XMAC_IPG);
5530         if (np->flags & NIU_FLAGS_10G) {
5531                 val &= ~XMAC_IPG_IPG_XGMII;
5532                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5533         } else {
5534                 val &= ~XMAC_IPG_IPG_MII_GMII;
5535                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5536         }
5537         nw64_mac(XMAC_IPG, val);
5538
5539         val = nr64_mac(XMAC_CONFIG);
5540         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5541                  XMAC_CONFIG_STRETCH_MODE |
5542                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5543                  XMAC_CONFIG_TX_ENABLE);
5544         nw64_mac(XMAC_CONFIG, val);
5545
5546         nw64_mac(TXMAC_FRM_CNT, 0);
5547         nw64_mac(TXMAC_BYTE_CNT, 0);
5548 }
5549
5550 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5551 {
5552         u64 val;
5553
5554         nw64_mac(BMAC_MIN_FRAME, min);
5555         nw64_mac(BMAC_MAX_FRAME, max);
5556
5557         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5558         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5559         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5560
5561         val = nr64_mac(BTXMAC_CONFIG);
5562         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5563                  BTXMAC_CONFIG_ENABLE);
5564         nw64_mac(BTXMAC_CONFIG, val);
5565 }
5566
5567 static void niu_init_tx_mac(struct niu *np)
5568 {
5569         u64 min, max;
5570
5571         min = 64;
5572         if (np->dev->mtu > ETH_DATA_LEN)
5573                 max = 9216;
5574         else
5575                 max = 1522;
5576
5577         /* The XMAC_MIN register only accepts values for TX min which
5578          * have the low 3 bits cleared.
5579          */
5580         BUG_ON(min & 0x7);
5581
5582         if (np->flags & NIU_FLAGS_XMAC)
5583                 niu_init_tx_xmac(np, min, max);
5584         else
5585                 niu_init_tx_bmac(np, min, max);
5586 }
5587
5588 static int niu_reset_rx_xmac(struct niu *np)
5589 {
5590         int limit;
5591
5592         nw64_mac(XRXMAC_SW_RST,
5593                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5594         limit = 1000;
5595         while (--limit >= 0) {
5596                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5597                                                  XRXMAC_SW_RST_SOFT_RST)))
5598                         break;
5599                 udelay(100);
5600         }
5601         if (limit < 0) {
5602                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5603                         np->port,
5604                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5605                 return -ENODEV;
5606         }
5607
5608         return 0;
5609 }
5610
5611 static int niu_reset_rx_bmac(struct niu *np)
5612 {
5613         int limit;
5614
5615         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5616         limit = 1000;
5617         while (--limit >= 0) {
5618                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5619                         break;
5620                 udelay(100);
5621         }
5622         if (limit < 0) {
5623                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5624                         np->port,
5625                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5626                 return -ENODEV;
5627         }
5628
5629         return 0;
5630 }
5631
5632 static int niu_reset_rx_mac(struct niu *np)
5633 {
5634         if (np->flags & NIU_FLAGS_XMAC)
5635                 return niu_reset_rx_xmac(np);
5636         else
5637                 return niu_reset_rx_bmac(np);
5638 }
5639
5640 static void niu_init_rx_xmac(struct niu *np)
5641 {
5642         struct niu_parent *parent = np->parent;
5643         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5644         int first_rdc_table = tp->first_table_num;
5645         unsigned long i;
5646         u64 val;
5647
5648         nw64_mac(XMAC_ADD_FILT0, 0);
5649         nw64_mac(XMAC_ADD_FILT1, 0);
5650         nw64_mac(XMAC_ADD_FILT2, 0);
5651         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5652         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5653         for (i = 0; i < MAC_NUM_HASH; i++)
5654                 nw64_mac(XMAC_HASH_TBL(i), 0);
5655         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5656         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5657         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5658
5659         val = nr64_mac(XMAC_CONFIG);
5660         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5661                  XMAC_CONFIG_PROMISCUOUS |
5662                  XMAC_CONFIG_PROMISC_GROUP |
5663                  XMAC_CONFIG_ERR_CHK_DIS |
5664                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5665                  XMAC_CONFIG_RESERVED_MULTICAST |
5666                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5667                  XMAC_CONFIG_ADDR_FILTER_EN |
5668                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5669                  XMAC_CONFIG_STRIP_CRC |
5670                  XMAC_CONFIG_PASS_FLOW_CTRL |
5671                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5672         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5673         nw64_mac(XMAC_CONFIG, val);
5674
5675         nw64_mac(RXMAC_BT_CNT, 0);
5676         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5677         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5678         nw64_mac(RXMAC_FRAG_CNT, 0);
5679         nw64_mac(RXMAC_HIST_CNT1, 0);
5680         nw64_mac(RXMAC_HIST_CNT2, 0);
5681         nw64_mac(RXMAC_HIST_CNT3, 0);
5682         nw64_mac(RXMAC_HIST_CNT4, 0);
5683         nw64_mac(RXMAC_HIST_CNT5, 0);
5684         nw64_mac(RXMAC_HIST_CNT6, 0);
5685         nw64_mac(RXMAC_HIST_CNT7, 0);
5686         nw64_mac(RXMAC_MPSZER_CNT, 0);
5687         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5688         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5689         nw64_mac(LINK_FAULT_CNT, 0);
5690 }
5691
5692 static void niu_init_rx_bmac(struct niu *np)
5693 {
5694         struct niu_parent *parent = np->parent;
5695         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5696         int first_rdc_table = tp->first_table_num;
5697         unsigned long i;
5698         u64 val;
5699
5700         nw64_mac(BMAC_ADD_FILT0, 0);
5701         nw64_mac(BMAC_ADD_FILT1, 0);
5702         nw64_mac(BMAC_ADD_FILT2, 0);
5703         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5704         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5705         for (i = 0; i < MAC_NUM_HASH; i++)
5706                 nw64_mac(BMAC_HASH_TBL(i), 0);
5707         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5708         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5709         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5710
5711         val = nr64_mac(BRXMAC_CONFIG);
5712         val &= ~(BRXMAC_CONFIG_ENABLE |
5713                  BRXMAC_CONFIG_STRIP_PAD |
5714                  BRXMAC_CONFIG_STRIP_FCS |
5715                  BRXMAC_CONFIG_PROMISC |
5716                  BRXMAC_CONFIG_PROMISC_GRP |
5717                  BRXMAC_CONFIG_ADDR_FILT_EN |
5718                  BRXMAC_CONFIG_DISCARD_DIS);
5719         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5720         nw64_mac(BRXMAC_CONFIG, val);
5721
5722         val = nr64_mac(BMAC_ADDR_CMPEN);
5723         val |= BMAC_ADDR_CMPEN_EN0;
5724         nw64_mac(BMAC_ADDR_CMPEN, val);
5725 }
5726
5727 static void niu_init_rx_mac(struct niu *np)
5728 {
5729         niu_set_primary_mac(np, np->dev->dev_addr);
5730
5731         if (np->flags & NIU_FLAGS_XMAC)
5732                 niu_init_rx_xmac(np);
5733         else
5734                 niu_init_rx_bmac(np);
5735 }
5736
5737 static void niu_enable_tx_xmac(struct niu *np, int on)
5738 {
5739         u64 val = nr64_mac(XMAC_CONFIG);
5740
5741         if (on)
5742                 val |= XMAC_CONFIG_TX_ENABLE;
5743         else
5744                 val &= ~XMAC_CONFIG_TX_ENABLE;
5745         nw64_mac(XMAC_CONFIG, val);
5746 }
5747
5748 static void niu_enable_tx_bmac(struct niu *np, int on)
5749 {
5750         u64 val = nr64_mac(BTXMAC_CONFIG);
5751
5752         if (on)
5753                 val |= BTXMAC_CONFIG_ENABLE;
5754         else
5755                 val &= ~BTXMAC_CONFIG_ENABLE;
5756         nw64_mac(BTXMAC_CONFIG, val);
5757 }
5758
5759 static void niu_enable_tx_mac(struct niu *np, int on)
5760 {
5761         if (np->flags & NIU_FLAGS_XMAC)
5762                 niu_enable_tx_xmac(np, on);
5763         else
5764                 niu_enable_tx_bmac(np, on);
5765 }
5766
5767 static void niu_enable_rx_xmac(struct niu *np, int on)
5768 {
5769         u64 val = nr64_mac(XMAC_CONFIG);
5770
5771         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5772                  XMAC_CONFIG_PROMISCUOUS);
5773
5774         if (np->flags & NIU_FLAGS_MCAST)
5775                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5776         if (np->flags & NIU_FLAGS_PROMISC)
5777                 val |= XMAC_CONFIG_PROMISCUOUS;
5778
5779         if (on)
5780                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5781         else
5782                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5783         nw64_mac(XMAC_CONFIG, val);
5784 }
5785
5786 static void niu_enable_rx_bmac(struct niu *np, int on)
5787 {
5788         u64 val = nr64_mac(BRXMAC_CONFIG);
5789
5790         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5791                  BRXMAC_CONFIG_PROMISC);
5792
5793         if (np->flags & NIU_FLAGS_MCAST)
5794                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5795         if (np->flags & NIU_FLAGS_PROMISC)
5796                 val |= BRXMAC_CONFIG_PROMISC;
5797
5798         if (on)
5799                 val |= BRXMAC_CONFIG_ENABLE;
5800         else
5801                 val &= ~BRXMAC_CONFIG_ENABLE;
5802         nw64_mac(BRXMAC_CONFIG, val);
5803 }
5804
5805 static void niu_enable_rx_mac(struct niu *np, int on)
5806 {
5807         if (np->flags & NIU_FLAGS_XMAC)
5808                 niu_enable_rx_xmac(np, on);
5809         else
5810                 niu_enable_rx_bmac(np, on);
5811 }
5812
5813 static int niu_init_mac(struct niu *np)
5814 {
5815         int err;
5816
5817         niu_init_xif(np);
5818         err = niu_init_pcs(np);
5819         if (err)
5820                 return err;
5821
5822         err = niu_reset_tx_mac(np);
5823         if (err)
5824                 return err;
5825         niu_init_tx_mac(np);
5826         err = niu_reset_rx_mac(np);
5827         if (err)
5828                 return err;
5829         niu_init_rx_mac(np);
5830
5831         /* This looks hookey but the RX MAC reset we just did will
5832          * undo some of the state we setup in niu_init_tx_mac() so we
5833          * have to call it again.  In particular, the RX MAC reset will
5834          * set the XMAC_MAX register back to it's default value.
5835          */
5836         niu_init_tx_mac(np);
5837         niu_enable_tx_mac(np, 1);
5838
5839         niu_enable_rx_mac(np, 1);
5840
5841         return 0;
5842 }
5843
5844 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5845 {
5846         (void) niu_tx_channel_stop(np, rp->tx_channel);
5847 }
5848
5849 static void niu_stop_tx_channels(struct niu *np)
5850 {
5851         int i;
5852
5853         for (i = 0; i < np->num_tx_rings; i++) {
5854                 struct tx_ring_info *rp = &np->tx_rings[i];
5855
5856                 niu_stop_one_tx_channel(np, rp);
5857         }
5858 }
5859
5860 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5861 {
5862         (void) niu_tx_channel_reset(np, rp->tx_channel);
5863 }
5864
5865 static void niu_reset_tx_channels(struct niu *np)
5866 {
5867         int i;
5868
5869         for (i = 0; i < np->num_tx_rings; i++) {
5870                 struct tx_ring_info *rp = &np->tx_rings[i];
5871
5872                 niu_reset_one_tx_channel(np, rp);
5873         }
5874 }
5875
5876 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5877 {
5878         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5879 }
5880
5881 static void niu_stop_rx_channels(struct niu *np)
5882 {
5883         int i;
5884
5885         for (i = 0; i < np->num_rx_rings; i++) {
5886                 struct rx_ring_info *rp = &np->rx_rings[i];
5887
5888                 niu_stop_one_rx_channel(np, rp);
5889         }
5890 }
5891
5892 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5893 {
5894         int channel = rp->rx_channel;
5895
5896         (void) niu_rx_channel_reset(np, channel);
5897         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5898         nw64(RX_DMA_CTL_STAT(channel), 0);
5899         (void) niu_enable_rx_channel(np, channel, 0);
5900 }
5901
5902 static void niu_reset_rx_channels(struct niu *np)
5903 {
5904         int i;
5905
5906         for (i = 0; i < np->num_rx_rings; i++) {
5907                 struct rx_ring_info *rp = &np->rx_rings[i];
5908
5909                 niu_reset_one_rx_channel(np, rp);
5910         }
5911 }
5912
5913 static void niu_disable_ipp(struct niu *np)
5914 {
5915         u64 rd, wr, val;
5916         int limit;
5917
5918         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5919         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5920         limit = 100;
5921         while (--limit >= 0 && (rd != wr)) {
5922                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5923                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5924         }
5925         if (limit < 0 &&
5926             (rd != 0 && wr != 1)) {
5927                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5928                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5929                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5930         }
5931
5932         val = nr64_ipp(IPP_CFIG);
5933         val &= ~(IPP_CFIG_IPP_ENABLE |
5934                  IPP_CFIG_DFIFO_ECC_EN |
5935                  IPP_CFIG_DROP_BAD_CRC |
5936                  IPP_CFIG_CKSUM_EN);
5937         nw64_ipp(IPP_CFIG, val);
5938
5939         (void) niu_ipp_reset(np);
5940 }
5941
5942 static int niu_init_hw(struct niu *np)
5943 {
5944         int i, err;
5945
5946         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5947         niu_txc_enable_port(np, 1);
5948         niu_txc_port_dma_enable(np, 1);
5949         niu_txc_set_imask(np, 0);
5950
5951         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5952         for (i = 0; i < np->num_tx_rings; i++) {
5953                 struct tx_ring_info *rp = &np->tx_rings[i];
5954
5955                 err = niu_init_one_tx_channel(np, rp);
5956                 if (err)
5957                         return err;
5958         }
5959
5960         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5961         err = niu_init_rx_channels(np);
5962         if (err)
5963                 goto out_uninit_tx_channels;
5964
5965         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5966         err = niu_init_classifier_hw(np);
5967         if (err)
5968                 goto out_uninit_rx_channels;
5969
5970         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5971         err = niu_init_zcp(np);
5972         if (err)
5973                 goto out_uninit_rx_channels;
5974
5975         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5976         err = niu_init_ipp(np);
5977         if (err)
5978                 goto out_uninit_rx_channels;
5979
5980         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5981         err = niu_init_mac(np);
5982         if (err)
5983                 goto out_uninit_ipp;
5984
5985         return 0;
5986
5987 out_uninit_ipp:
5988         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5989         niu_disable_ipp(np);
5990
5991 out_uninit_rx_channels:
5992         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5993         niu_stop_rx_channels(np);
5994         niu_reset_rx_channels(np);
5995
5996 out_uninit_tx_channels:
5997         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5998         niu_stop_tx_channels(np);
5999         niu_reset_tx_channels(np);
6000
6001         return err;
6002 }
6003
6004 static void niu_stop_hw(struct niu *np)
6005 {
6006         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6007         niu_enable_interrupts(np, 0);
6008
6009         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6010         niu_enable_rx_mac(np, 0);
6011
6012         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6013         niu_disable_ipp(np);
6014
6015         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6016         niu_stop_tx_channels(np);
6017
6018         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6019         niu_stop_rx_channels(np);
6020
6021         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6022         niu_reset_tx_channels(np);
6023
6024         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6025         niu_reset_rx_channels(np);
6026 }
6027
6028 static void niu_set_irq_name(struct niu *np)
6029 {
6030         int port = np->port;
6031         int i, j = 1;
6032
6033         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6034
6035         if (port == 0) {
6036                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6037                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6038                 j = 3;
6039         }
6040
6041         for (i = 0; i < np->num_ldg - j; i++) {
6042                 if (i < np->num_rx_rings)
6043                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6044                                 np->dev->name, i);
6045                 else if (i < np->num_tx_rings + np->num_rx_rings)
6046                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6047                                 i - np->num_rx_rings);
6048         }
6049 }
6050
6051 static int niu_request_irq(struct niu *np)
6052 {
6053         int i, j, err;
6054
6055         niu_set_irq_name(np);
6056
6057         err = 0;
6058         for (i = 0; i < np->num_ldg; i++) {
6059                 struct niu_ldg *lp = &np->ldg[i];
6060
6061                 err = request_irq(lp->irq, niu_interrupt,
6062                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6063                                   np->irq_name[i], lp);
6064                 if (err)
6065                         goto out_free_irqs;
6066
6067         }
6068
6069         return 0;
6070
6071 out_free_irqs:
6072         for (j = 0; j < i; j++) {
6073                 struct niu_ldg *lp = &np->ldg[j];
6074
6075                 free_irq(lp->irq, lp);
6076         }
6077         return err;
6078 }
6079
6080 static void niu_free_irq(struct niu *np)
6081 {
6082         int i;
6083
6084         for (i = 0; i < np->num_ldg; i++) {
6085                 struct niu_ldg *lp = &np->ldg[i];
6086
6087                 free_irq(lp->irq, lp);
6088         }
6089 }
6090
6091 static void niu_enable_napi(struct niu *np)
6092 {
6093         int i;
6094
6095         for (i = 0; i < np->num_ldg; i++)
6096                 napi_enable(&np->ldg[i].napi);
6097 }
6098
6099 static void niu_disable_napi(struct niu *np)
6100 {
6101         int i;
6102
6103         for (i = 0; i < np->num_ldg; i++)
6104                 napi_disable(&np->ldg[i].napi);
6105 }
6106
6107 static int niu_open(struct net_device *dev)
6108 {
6109         struct niu *np = netdev_priv(dev);
6110         int err;
6111
6112         netif_carrier_off(dev);
6113
6114         err = niu_alloc_channels(np);
6115         if (err)
6116                 goto out_err;
6117
6118         err = niu_enable_interrupts(np, 0);
6119         if (err)
6120                 goto out_free_channels;
6121
6122         err = niu_request_irq(np);
6123         if (err)
6124                 goto out_free_channels;
6125
6126         niu_enable_napi(np);
6127
6128         spin_lock_irq(&np->lock);
6129
6130         err = niu_init_hw(np);
6131         if (!err) {
6132                 init_timer(&np->timer);
6133                 np->timer.expires = jiffies + HZ;
6134                 np->timer.data = (unsigned long) np;
6135                 np->timer.function = niu_timer;
6136
6137                 err = niu_enable_interrupts(np, 1);
6138                 if (err)
6139                         niu_stop_hw(np);
6140         }
6141
6142         spin_unlock_irq(&np->lock);
6143
6144         if (err) {
6145                 niu_disable_napi(np);
6146                 goto out_free_irq;
6147         }
6148
6149         netif_tx_start_all_queues(dev);
6150
6151         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6152                 netif_carrier_on(dev);
6153
6154         add_timer(&np->timer);
6155
6156         return 0;
6157
6158 out_free_irq:
6159         niu_free_irq(np);
6160
6161 out_free_channels:
6162         niu_free_channels(np);
6163
6164 out_err:
6165         return err;
6166 }
6167
6168 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6169 {
6170         cancel_work_sync(&np->reset_task);
6171
6172         niu_disable_napi(np);
6173         netif_tx_stop_all_queues(dev);
6174
6175         del_timer_sync(&np->timer);
6176
6177         spin_lock_irq(&np->lock);
6178
6179         niu_stop_hw(np);
6180
6181         spin_unlock_irq(&np->lock);
6182 }
6183
6184 static int niu_close(struct net_device *dev)
6185 {
6186         struct niu *np = netdev_priv(dev);
6187
6188         niu_full_shutdown(np, dev);
6189
6190         niu_free_irq(np);
6191
6192         niu_free_channels(np);
6193
6194         niu_handle_led(np, 0);
6195
6196         return 0;
6197 }
6198
6199 static void niu_sync_xmac_stats(struct niu *np)
6200 {
6201         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6202
6203         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6204         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6205
6206         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6207         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6208         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6209         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6210         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6211         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6212         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6213         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6214         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6215         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6216         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6217         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6218         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6219         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6220         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6221         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6222 }
6223
6224 static void niu_sync_bmac_stats(struct niu *np)
6225 {
6226         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6227
6228         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6229         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6230
6231         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6232         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6233         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6234         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6235 }
6236
6237 static void niu_sync_mac_stats(struct niu *np)
6238 {
6239         if (np->flags & NIU_FLAGS_XMAC)
6240                 niu_sync_xmac_stats(np);
6241         else
6242                 niu_sync_bmac_stats(np);
6243 }
6244
6245 static void niu_get_rx_stats(struct niu *np)
6246 {
6247         unsigned long pkts, dropped, errors, bytes;
6248         int i;
6249
6250         pkts = dropped = errors = bytes = 0;
6251         for (i = 0; i < np->num_rx_rings; i++) {
6252                 struct rx_ring_info *rp = &np->rx_rings[i];
6253
6254                 niu_sync_rx_discard_stats(np, rp, 0);
6255
6256                 pkts += rp->rx_packets;
6257                 bytes += rp->rx_bytes;
6258                 dropped += rp->rx_dropped;
6259                 errors += rp->rx_errors;
6260         }
6261         np->dev->stats.rx_packets = pkts;
6262         np->dev->stats.rx_bytes = bytes;
6263         np->dev->stats.rx_dropped = dropped;
6264         np->dev->stats.rx_errors = errors;
6265 }
6266
6267 static void niu_get_tx_stats(struct niu *np)
6268 {
6269         unsigned long pkts, errors, bytes;
6270         int i;
6271
6272         pkts = errors = bytes = 0;
6273         for (i = 0; i < np->num_tx_rings; i++) {
6274                 struct tx_ring_info *rp = &np->tx_rings[i];
6275
6276                 pkts += rp->tx_packets;
6277                 bytes += rp->tx_bytes;
6278                 errors += rp->tx_errors;
6279         }
6280         np->dev->stats.tx_packets = pkts;
6281         np->dev->stats.tx_bytes = bytes;
6282         np->dev->stats.tx_errors = errors;
6283 }
6284
6285 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6286 {
6287         struct niu *np = netdev_priv(dev);
6288
6289         niu_get_rx_stats(np);
6290         niu_get_tx_stats(np);
6291
6292         return &dev->stats;
6293 }
6294
6295 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6296 {
6297         int i;
6298
6299         for (i = 0; i < 16; i++)
6300                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6301 }
6302
6303 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6304 {
6305         int i;
6306
6307         for (i = 0; i < 16; i++)
6308                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6309 }
6310
6311 static void niu_load_hash(struct niu *np, u16 *hash)
6312 {
6313         if (np->flags & NIU_FLAGS_XMAC)
6314                 niu_load_hash_xmac(np, hash);
6315         else
6316                 niu_load_hash_bmac(np, hash);
6317 }
6318
6319 static void niu_set_rx_mode(struct net_device *dev)
6320 {
6321         struct niu *np = netdev_priv(dev);
6322         int i, alt_cnt, err;
6323         struct dev_addr_list *addr;
6324         struct netdev_hw_addr *ha;
6325         unsigned long flags;
6326         u16 hash[16] = { 0, };
6327
6328         spin_lock_irqsave(&np->lock, flags);
6329         niu_enable_rx_mac(np, 0);
6330
6331         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6332         if (dev->flags & IFF_PROMISC)
6333                 np->flags |= NIU_FLAGS_PROMISC;
6334         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6335                 np->flags |= NIU_FLAGS_MCAST;
6336
6337         alt_cnt = netdev_uc_count(dev);
6338         if (alt_cnt > niu_num_alt_addr(np)) {
6339                 alt_cnt = 0;
6340                 np->flags |= NIU_FLAGS_PROMISC;
6341         }
6342
6343         if (alt_cnt) {
6344                 int index = 0;
6345
6346                 netdev_for_each_uc_addr(ha, dev) {
6347                         err = niu_set_alt_mac(np, index, ha->addr);
6348                         if (err)
6349                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6350                                             err, index);
6351                         err = niu_enable_alt_mac(np, index, 1);
6352                         if (err)
6353                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6354                                             err, index);
6355
6356                         index++;
6357                 }
6358         } else {
6359                 int alt_start;
6360                 if (np->flags & NIU_FLAGS_XMAC)
6361                         alt_start = 0;
6362                 else
6363                         alt_start = 1;
6364                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6365                         err = niu_enable_alt_mac(np, i, 0);
6366                         if (err)
6367                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6368                                             err, i);
6369                 }
6370         }
6371         if (dev->flags & IFF_ALLMULTI) {
6372                 for (i = 0; i < 16; i++)
6373                         hash[i] = 0xffff;
6374         } else if (!netdev_mc_empty(dev)) {
6375                 for (addr = dev->mc_list; addr; addr = addr->next) {
6376                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6377
6378                         crc >>= 24;
6379                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6380                 }
6381         }
6382
6383         if (np->flags & NIU_FLAGS_MCAST)
6384                 niu_load_hash(np, hash);
6385
6386         niu_enable_rx_mac(np, 1);
6387         spin_unlock_irqrestore(&np->lock, flags);
6388 }
6389
6390 static int niu_set_mac_addr(struct net_device *dev, void *p)
6391 {
6392         struct niu *np = netdev_priv(dev);
6393         struct sockaddr *addr = p;
6394         unsigned long flags;
6395
6396         if (!is_valid_ether_addr(addr->sa_data))
6397                 return -EINVAL;
6398
6399         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6400
6401         if (!netif_running(dev))
6402                 return 0;
6403
6404         spin_lock_irqsave(&np->lock, flags);
6405         niu_enable_rx_mac(np, 0);
6406         niu_set_primary_mac(np, dev->dev_addr);
6407         niu_enable_rx_mac(np, 1);
6408         spin_unlock_irqrestore(&np->lock, flags);
6409
6410         return 0;
6411 }
6412
6413 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6414 {
6415         return -EOPNOTSUPP;
6416 }
6417
6418 static void niu_netif_stop(struct niu *np)
6419 {
6420         np->dev->trans_start = jiffies; /* prevent tx timeout */
6421
6422         niu_disable_napi(np);
6423
6424         netif_tx_disable(np->dev);
6425 }
6426
6427 static void niu_netif_start(struct niu *np)
6428 {
6429         /* NOTE: unconditional netif_wake_queue is only appropriate
6430          * so long as all callers are assured to have free tx slots
6431          * (such as after niu_init_hw).
6432          */
6433         netif_tx_wake_all_queues(np->dev);
6434
6435         niu_enable_napi(np);
6436
6437         niu_enable_interrupts(np, 1);
6438 }
6439
6440 static void niu_reset_buffers(struct niu *np)
6441 {
6442         int i, j, k, err;
6443
6444         if (np->rx_rings) {
6445                 for (i = 0; i < np->num_rx_rings; i++) {
6446                         struct rx_ring_info *rp = &np->rx_rings[i];
6447
6448                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6449                                 struct page *page;
6450
6451                                 page = rp->rxhash[j];
6452                                 while (page) {
6453                                         struct page *next =
6454                                                 (struct page *) page->mapping;
6455                                         u64 base = page->index;
6456                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6457                                         rp->rbr[k++] = cpu_to_le32(base);
6458                                         page = next;
6459                                 }
6460                         }
6461                         for (; k < MAX_RBR_RING_SIZE; k++) {
6462                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6463                                 if (unlikely(err))
6464                                         break;
6465                         }
6466
6467                         rp->rbr_index = rp->rbr_table_size - 1;
6468                         rp->rcr_index = 0;
6469                         rp->rbr_pending = 0;
6470                         rp->rbr_refill_pending = 0;
6471                 }
6472         }
6473         if (np->tx_rings) {
6474                 for (i = 0; i < np->num_tx_rings; i++) {
6475                         struct tx_ring_info *rp = &np->tx_rings[i];
6476
6477                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6478                                 if (rp->tx_buffs[j].skb)
6479                                         (void) release_tx_packet(np, rp, j);
6480                         }
6481
6482                         rp->pending = MAX_TX_RING_SIZE;
6483                         rp->prod = 0;
6484                         rp->cons = 0;
6485                         rp->wrap_bit = 0;
6486                 }
6487         }
6488 }
6489
6490 static void niu_reset_task(struct work_struct *work)
6491 {
6492         struct niu *np = container_of(work, struct niu, reset_task);
6493         unsigned long flags;
6494         int err;
6495
6496         spin_lock_irqsave(&np->lock, flags);
6497         if (!netif_running(np->dev)) {
6498                 spin_unlock_irqrestore(&np->lock, flags);
6499                 return;
6500         }
6501
6502         spin_unlock_irqrestore(&np->lock, flags);
6503
6504         del_timer_sync(&np->timer);
6505
6506         niu_netif_stop(np);
6507
6508         spin_lock_irqsave(&np->lock, flags);
6509
6510         niu_stop_hw(np);
6511
6512         spin_unlock_irqrestore(&np->lock, flags);
6513
6514         niu_reset_buffers(np);
6515
6516         spin_lock_irqsave(&np->lock, flags);
6517
6518         err = niu_init_hw(np);
6519         if (!err) {
6520                 np->timer.expires = jiffies + HZ;
6521                 add_timer(&np->timer);
6522                 niu_netif_start(np);
6523         }
6524
6525         spin_unlock_irqrestore(&np->lock, flags);
6526 }
6527
6528 static void niu_tx_timeout(struct net_device *dev)
6529 {
6530         struct niu *np = netdev_priv(dev);
6531
6532         dev_err(np->device, "%s: Transmit timed out, resetting\n",
6533                 dev->name);
6534
6535         schedule_work(&np->reset_task);
6536 }
6537
6538 static void niu_set_txd(struct tx_ring_info *rp, int index,
6539                         u64 mapping, u64 len, u64 mark,
6540                         u64 n_frags)
6541 {
6542         __le64 *desc = &rp->descr[index];
6543
6544         *desc = cpu_to_le64(mark |
6545                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6546                             (len << TX_DESC_TR_LEN_SHIFT) |
6547                             (mapping & TX_DESC_SAD));
6548 }
6549
6550 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6551                                 u64 pad_bytes, u64 len)
6552 {
6553         u16 eth_proto, eth_proto_inner;
6554         u64 csum_bits, l3off, ihl, ret;
6555         u8 ip_proto;
6556         int ipv6;
6557
6558         eth_proto = be16_to_cpu(ehdr->h_proto);
6559         eth_proto_inner = eth_proto;
6560         if (eth_proto == ETH_P_8021Q) {
6561                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6562                 __be16 val = vp->h_vlan_encapsulated_proto;
6563
6564                 eth_proto_inner = be16_to_cpu(val);
6565         }
6566
6567         ipv6 = ihl = 0;
6568         switch (skb->protocol) {
6569         case cpu_to_be16(ETH_P_IP):
6570                 ip_proto = ip_hdr(skb)->protocol;
6571                 ihl = ip_hdr(skb)->ihl;
6572                 break;
6573         case cpu_to_be16(ETH_P_IPV6):
6574                 ip_proto = ipv6_hdr(skb)->nexthdr;
6575                 ihl = (40 >> 2);
6576                 ipv6 = 1;
6577                 break;
6578         default:
6579                 ip_proto = ihl = 0;
6580                 break;
6581         }
6582
6583         csum_bits = TXHDR_CSUM_NONE;
6584         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6585                 u64 start, stuff;
6586
6587                 csum_bits = (ip_proto == IPPROTO_TCP ?
6588                              TXHDR_CSUM_TCP :
6589                              (ip_proto == IPPROTO_UDP ?
6590                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6591
6592                 start = skb_transport_offset(skb) -
6593                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6594                 stuff = start + skb->csum_offset;
6595
6596                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6597                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6598         }
6599
6600         l3off = skb_network_offset(skb) -
6601                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6602
6603         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6604                (len << TXHDR_LEN_SHIFT) |
6605                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6606                (ihl << TXHDR_IHL_SHIFT) |
6607                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6608                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6609                (ipv6 ? TXHDR_IP_VER : 0) |
6610                csum_bits);
6611
6612         return ret;
6613 }
6614
6615 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6616                                   struct net_device *dev)
6617 {
6618         struct niu *np = netdev_priv(dev);
6619         unsigned long align, headroom;
6620         struct netdev_queue *txq;
6621         struct tx_ring_info *rp;
6622         struct tx_pkt_hdr *tp;
6623         unsigned int len, nfg;
6624         struct ethhdr *ehdr;
6625         int prod, i, tlen;
6626         u64 mapping, mrk;
6627
6628         i = skb_get_queue_mapping(skb);
6629         rp = &np->tx_rings[i];
6630         txq = netdev_get_tx_queue(dev, i);
6631
6632         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6633                 netif_tx_stop_queue(txq);
6634                 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6635                 rp->tx_errors++;
6636                 return NETDEV_TX_BUSY;
6637         }
6638
6639         if (skb->len < ETH_ZLEN) {
6640                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6641
6642                 if (skb_pad(skb, pad_bytes))
6643                         goto out;
6644                 skb_put(skb, pad_bytes);
6645         }
6646
6647         len = sizeof(struct tx_pkt_hdr) + 15;
6648         if (skb_headroom(skb) < len) {
6649                 struct sk_buff *skb_new;
6650
6651                 skb_new = skb_realloc_headroom(skb, len);
6652                 if (!skb_new) {
6653                         rp->tx_errors++;
6654                         goto out_drop;
6655                 }
6656                 kfree_skb(skb);
6657                 skb = skb_new;
6658         } else
6659                 skb_orphan(skb);
6660
6661         align = ((unsigned long) skb->data & (16 - 1));
6662         headroom = align + sizeof(struct tx_pkt_hdr);
6663
6664         ehdr = (struct ethhdr *) skb->data;
6665         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6666
6667         len = skb->len - sizeof(struct tx_pkt_hdr);
6668         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6669         tp->resv = 0;
6670
6671         len = skb_headlen(skb);
6672         mapping = np->ops->map_single(np->device, skb->data,
6673                                       len, DMA_TO_DEVICE);
6674
6675         prod = rp->prod;
6676
6677         rp->tx_buffs[prod].skb = skb;
6678         rp->tx_buffs[prod].mapping = mapping;
6679
6680         mrk = TX_DESC_SOP;
6681         if (++rp->mark_counter == rp->mark_freq) {
6682                 rp->mark_counter = 0;
6683                 mrk |= TX_DESC_MARK;
6684                 rp->mark_pending++;
6685         }
6686
6687         tlen = len;
6688         nfg = skb_shinfo(skb)->nr_frags;
6689         while (tlen > 0) {
6690                 tlen -= MAX_TX_DESC_LEN;
6691                 nfg++;
6692         }
6693
6694         while (len > 0) {
6695                 unsigned int this_len = len;
6696
6697                 if (this_len > MAX_TX_DESC_LEN)
6698                         this_len = MAX_TX_DESC_LEN;
6699
6700                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6701                 mrk = nfg = 0;
6702
6703                 prod = NEXT_TX(rp, prod);
6704                 mapping += this_len;
6705                 len -= this_len;
6706         }
6707
6708         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6709                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6710
6711                 len = frag->size;
6712                 mapping = np->ops->map_page(np->device, frag->page,
6713                                             frag->page_offset, len,
6714                                             DMA_TO_DEVICE);
6715
6716                 rp->tx_buffs[prod].skb = NULL;
6717                 rp->tx_buffs[prod].mapping = mapping;
6718
6719                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6720
6721                 prod = NEXT_TX(rp, prod);
6722         }
6723
6724         if (prod < rp->prod)
6725                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6726         rp->prod = prod;
6727
6728         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6729
6730         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6731                 netif_tx_stop_queue(txq);
6732                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6733                         netif_tx_wake_queue(txq);
6734         }
6735
6736 out:
6737         return NETDEV_TX_OK;
6738
6739 out_drop:
6740         rp->tx_errors++;
6741         kfree_skb(skb);
6742         goto out;
6743 }
6744
6745 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6746 {
6747         struct niu *np = netdev_priv(dev);
6748         int err, orig_jumbo, new_jumbo;
6749
6750         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6751                 return -EINVAL;
6752
6753         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6754         new_jumbo = (new_mtu > ETH_DATA_LEN);
6755
6756         dev->mtu = new_mtu;
6757
6758         if (!netif_running(dev) ||
6759             (orig_jumbo == new_jumbo))
6760                 return 0;
6761
6762         niu_full_shutdown(np, dev);
6763
6764         niu_free_channels(np);
6765
6766         niu_enable_napi(np);
6767
6768         err = niu_alloc_channels(np);
6769         if (err)
6770                 return err;
6771
6772         spin_lock_irq(&np->lock);
6773
6774         err = niu_init_hw(np);
6775         if (!err) {
6776                 init_timer(&np->timer);
6777                 np->timer.expires = jiffies + HZ;
6778                 np->timer.data = (unsigned long) np;
6779                 np->timer.function = niu_timer;
6780
6781                 err = niu_enable_interrupts(np, 1);
6782                 if (err)
6783                         niu_stop_hw(np);
6784         }
6785
6786         spin_unlock_irq(&np->lock);
6787
6788         if (!err) {
6789                 netif_tx_start_all_queues(dev);
6790                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6791                         netif_carrier_on(dev);
6792
6793                 add_timer(&np->timer);
6794         }
6795
6796         return err;
6797 }
6798
6799 static void niu_get_drvinfo(struct net_device *dev,
6800                             struct ethtool_drvinfo *info)
6801 {
6802         struct niu *np = netdev_priv(dev);
6803         struct niu_vpd *vpd = &np->vpd;
6804
6805         strcpy(info->driver, DRV_MODULE_NAME);
6806         strcpy(info->version, DRV_MODULE_VERSION);
6807         sprintf(info->fw_version, "%d.%d",
6808                 vpd->fcode_major, vpd->fcode_minor);
6809         if (np->parent->plat_type != PLAT_TYPE_NIU)
6810                 strcpy(info->bus_info, pci_name(np->pdev));
6811 }
6812
6813 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6814 {
6815         struct niu *np = netdev_priv(dev);
6816         struct niu_link_config *lp;
6817
6818         lp = &np->link_config;
6819
6820         memset(cmd, 0, sizeof(*cmd));
6821         cmd->phy_address = np->phy_addr;
6822         cmd->supported = lp->supported;
6823         cmd->advertising = lp->active_advertising;
6824         cmd->autoneg = lp->active_autoneg;
6825         cmd->speed = lp->active_speed;
6826         cmd->duplex = lp->active_duplex;
6827         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6828         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6829                 XCVR_EXTERNAL : XCVR_INTERNAL;
6830
6831         return 0;
6832 }
6833
6834 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6835 {
6836         struct niu *np = netdev_priv(dev);
6837         struct niu_link_config *lp = &np->link_config;
6838
6839         lp->advertising = cmd->advertising;
6840         lp->speed = cmd->speed;
6841         lp->duplex = cmd->duplex;
6842         lp->autoneg = cmd->autoneg;
6843         return niu_init_link(np);
6844 }
6845
6846 static u32 niu_get_msglevel(struct net_device *dev)
6847 {
6848         struct niu *np = netdev_priv(dev);
6849         return np->msg_enable;
6850 }
6851
6852 static void niu_set_msglevel(struct net_device *dev, u32 value)
6853 {
6854         struct niu *np = netdev_priv(dev);
6855         np->msg_enable = value;
6856 }
6857
6858 static int niu_nway_reset(struct net_device *dev)
6859 {
6860         struct niu *np = netdev_priv(dev);
6861
6862         if (np->link_config.autoneg)
6863                 return niu_init_link(np);
6864
6865         return 0;
6866 }
6867
6868 static int niu_get_eeprom_len(struct net_device *dev)
6869 {
6870         struct niu *np = netdev_priv(dev);
6871
6872         return np->eeprom_len;
6873 }
6874
6875 static int niu_get_eeprom(struct net_device *dev,
6876                           struct ethtool_eeprom *eeprom, u8 *data)
6877 {
6878         struct niu *np = netdev_priv(dev);
6879         u32 offset, len, val;
6880
6881         offset = eeprom->offset;
6882         len = eeprom->len;
6883
6884         if (offset + len < offset)
6885                 return -EINVAL;
6886         if (offset >= np->eeprom_len)
6887                 return -EINVAL;
6888         if (offset + len > np->eeprom_len)
6889                 len = eeprom->len = np->eeprom_len - offset;
6890
6891         if (offset & 3) {
6892                 u32 b_offset, b_count;
6893
6894                 b_offset = offset & 3;
6895                 b_count = 4 - b_offset;
6896                 if (b_count > len)
6897                         b_count = len;
6898
6899                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6900                 memcpy(data, ((char *)&val) + b_offset, b_count);
6901                 data += b_count;
6902                 len -= b_count;
6903                 offset += b_count;
6904         }
6905         while (len >= 4) {
6906                 val = nr64(ESPC_NCR(offset / 4));
6907                 memcpy(data, &val, 4);
6908                 data += 4;
6909                 len -= 4;
6910                 offset += 4;
6911         }
6912         if (len) {
6913                 val = nr64(ESPC_NCR(offset / 4));
6914                 memcpy(data, &val, len);
6915         }
6916         return 0;
6917 }
6918
6919 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6920 {
6921         switch (flow_type) {
6922         case TCP_V4_FLOW:
6923         case TCP_V6_FLOW:
6924                 *pid = IPPROTO_TCP;
6925                 break;
6926         case UDP_V4_FLOW:
6927         case UDP_V6_FLOW:
6928                 *pid = IPPROTO_UDP;
6929                 break;
6930         case SCTP_V4_FLOW:
6931         case SCTP_V6_FLOW:
6932                 *pid = IPPROTO_SCTP;
6933                 break;
6934         case AH_V4_FLOW:
6935         case AH_V6_FLOW:
6936                 *pid = IPPROTO_AH;
6937                 break;
6938         case ESP_V4_FLOW:
6939         case ESP_V6_FLOW:
6940                 *pid = IPPROTO_ESP;
6941                 break;
6942         default:
6943                 *pid = 0;
6944                 break;
6945         }
6946 }
6947
6948 static int niu_class_to_ethflow(u64 class, int *flow_type)
6949 {
6950         switch (class) {
6951         case CLASS_CODE_TCP_IPV4:
6952                 *flow_type = TCP_V4_FLOW;
6953                 break;
6954         case CLASS_CODE_UDP_IPV4:
6955                 *flow_type = UDP_V4_FLOW;
6956                 break;
6957         case CLASS_CODE_AH_ESP_IPV4:
6958                 *flow_type = AH_V4_FLOW;
6959                 break;
6960         case CLASS_CODE_SCTP_IPV4:
6961                 *flow_type = SCTP_V4_FLOW;
6962                 break;
6963         case CLASS_CODE_TCP_IPV6:
6964                 *flow_type = TCP_V6_FLOW;
6965                 break;
6966         case CLASS_CODE_UDP_IPV6:
6967                 *flow_type = UDP_V6_FLOW;
6968                 break;
6969         case CLASS_CODE_AH_ESP_IPV6:
6970                 *flow_type = AH_V6_FLOW;
6971                 break;
6972         case CLASS_CODE_SCTP_IPV6:
6973                 *flow_type = SCTP_V6_FLOW;
6974                 break;
6975         case CLASS_CODE_USER_PROG1:
6976         case CLASS_CODE_USER_PROG2:
6977         case CLASS_CODE_USER_PROG3:
6978         case CLASS_CODE_USER_PROG4:
6979                 *flow_type = IP_USER_FLOW;
6980                 break;
6981         default:
6982                 return 0;
6983         }
6984
6985         return 1;
6986 }
6987
6988 static int niu_ethflow_to_class(int flow_type, u64 *class)
6989 {
6990         switch (flow_type) {
6991         case TCP_V4_FLOW:
6992                 *class = CLASS_CODE_TCP_IPV4;
6993                 break;
6994         case UDP_V4_FLOW:
6995                 *class = CLASS_CODE_UDP_IPV4;
6996                 break;
6997         case AH_V4_FLOW:
6998         case ESP_V4_FLOW:
6999                 *class = CLASS_CODE_AH_ESP_IPV4;
7000                 break;
7001         case SCTP_V4_FLOW:
7002                 *class = CLASS_CODE_SCTP_IPV4;
7003                 break;
7004         case TCP_V6_FLOW:
7005                 *class = CLASS_CODE_TCP_IPV6;
7006                 break;
7007         case UDP_V6_FLOW:
7008                 *class = CLASS_CODE_UDP_IPV6;
7009                 break;
7010         case AH_V6_FLOW:
7011         case ESP_V6_FLOW:
7012                 *class = CLASS_CODE_AH_ESP_IPV6;
7013                 break;
7014         case SCTP_V6_FLOW:
7015                 *class = CLASS_CODE_SCTP_IPV6;
7016                 break;
7017         default:
7018                 return 0;
7019         }
7020
7021         return 1;
7022 }
7023
7024 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7025 {
7026         u64 ethflow = 0;
7027
7028         if (flow_key & FLOW_KEY_L2DA)
7029                 ethflow |= RXH_L2DA;
7030         if (flow_key & FLOW_KEY_VLAN)
7031                 ethflow |= RXH_VLAN;
7032         if (flow_key & FLOW_KEY_IPSA)
7033                 ethflow |= RXH_IP_SRC;
7034         if (flow_key & FLOW_KEY_IPDA)
7035                 ethflow |= RXH_IP_DST;
7036         if (flow_key & FLOW_KEY_PROTO)
7037                 ethflow |= RXH_L3_PROTO;
7038         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7039                 ethflow |= RXH_L4_B_0_1;
7040         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7041                 ethflow |= RXH_L4_B_2_3;
7042
7043         return ethflow;
7044
7045 }
7046
7047 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7048 {
7049         u64 key = 0;
7050
7051         if (ethflow & RXH_L2DA)
7052                 key |= FLOW_KEY_L2DA;
7053         if (ethflow & RXH_VLAN)
7054                 key |= FLOW_KEY_VLAN;
7055         if (ethflow & RXH_IP_SRC)
7056                 key |= FLOW_KEY_IPSA;
7057         if (ethflow & RXH_IP_DST)
7058                 key |= FLOW_KEY_IPDA;
7059         if (ethflow & RXH_L3_PROTO)
7060                 key |= FLOW_KEY_PROTO;
7061         if (ethflow & RXH_L4_B_0_1)
7062                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7063         if (ethflow & RXH_L4_B_2_3)
7064                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7065
7066         *flow_key = key;
7067
7068         return 1;
7069
7070 }
7071
7072 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7073 {
7074         u64 class;
7075
7076         nfc->data = 0;
7077
7078         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7079                 return -EINVAL;
7080
7081         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7082             TCAM_KEY_DISC)
7083                 nfc->data = RXH_DISCARD;
7084         else
7085                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7086                                                       CLASS_CODE_USER_PROG1]);
7087         return 0;
7088 }
7089
7090 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7091                                         struct ethtool_rx_flow_spec *fsp)
7092 {
7093
7094         fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7095                 TCAM_V4KEY3_SADDR_SHIFT;
7096         fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7097                 TCAM_V4KEY3_DADDR_SHIFT;
7098         fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7099                 TCAM_V4KEY3_SADDR_SHIFT;
7100         fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7101                 TCAM_V4KEY3_DADDR_SHIFT;
7102
7103         fsp->h_u.tcp_ip4_spec.ip4src =
7104                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7105         fsp->m_u.tcp_ip4_spec.ip4src =
7106                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7107         fsp->h_u.tcp_ip4_spec.ip4dst =
7108                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7109         fsp->m_u.tcp_ip4_spec.ip4dst =
7110                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7111
7112         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7113                 TCAM_V4KEY2_TOS_SHIFT;
7114         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7115                 TCAM_V4KEY2_TOS_SHIFT;
7116
7117         switch (fsp->flow_type) {
7118         case TCP_V4_FLOW:
7119         case UDP_V4_FLOW:
7120         case SCTP_V4_FLOW:
7121                 fsp->h_u.tcp_ip4_spec.psrc =
7122                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7123                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7124                 fsp->h_u.tcp_ip4_spec.pdst =
7125                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7126                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7127                 fsp->m_u.tcp_ip4_spec.psrc =
7128                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7129                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7130                 fsp->m_u.tcp_ip4_spec.pdst =
7131                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7132                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7133
7134                 fsp->h_u.tcp_ip4_spec.psrc =
7135                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7136                 fsp->h_u.tcp_ip4_spec.pdst =
7137                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7138                 fsp->m_u.tcp_ip4_spec.psrc =
7139                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7140                 fsp->m_u.tcp_ip4_spec.pdst =
7141                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7142                 break;
7143         case AH_V4_FLOW:
7144         case ESP_V4_FLOW:
7145                 fsp->h_u.ah_ip4_spec.spi =
7146                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7147                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7148                 fsp->m_u.ah_ip4_spec.spi =
7149                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7150                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7151
7152                 fsp->h_u.ah_ip4_spec.spi =
7153                         cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7154                 fsp->m_u.ah_ip4_spec.spi =
7155                         cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7156                 break;
7157         case IP_USER_FLOW:
7158                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7159                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7160                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7161                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7162                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7163                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7164
7165                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7166                         cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7167                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7168                         cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7169
7170                 fsp->h_u.usr_ip4_spec.proto =
7171                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7172                         TCAM_V4KEY2_PROTO_SHIFT;
7173                 fsp->m_u.usr_ip4_spec.proto =
7174                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7175                         TCAM_V4KEY2_PROTO_SHIFT;
7176
7177                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7178                 break;
7179         default:
7180                 break;
7181         }
7182 }
7183
7184 static int niu_get_ethtool_tcam_entry(struct niu *np,
7185                                       struct ethtool_rxnfc *nfc)
7186 {
7187         struct niu_parent *parent = np->parent;
7188         struct niu_tcam_entry *tp;
7189         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7190         u16 idx;
7191         u64 class;
7192         int ret = 0;
7193
7194         idx = tcam_get_index(np, (u16)nfc->fs.location);
7195
7196         tp = &parent->tcam[idx];
7197         if (!tp->valid) {
7198                 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7199                             parent->index, (u16)nfc->fs.location, idx);
7200                 return -EINVAL;
7201         }
7202
7203         /* fill the flow spec entry */
7204         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7205                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7206         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7207
7208         if (ret < 0) {
7209                 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7210                             parent->index);
7211                 ret = -EINVAL;
7212                 goto out;
7213         }
7214
7215         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7216                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7217                         TCAM_V4KEY2_PROTO_SHIFT;
7218                 if (proto == IPPROTO_ESP) {
7219                         if (fsp->flow_type == AH_V4_FLOW)
7220                                 fsp->flow_type = ESP_V4_FLOW;
7221                         else
7222                                 fsp->flow_type = ESP_V6_FLOW;
7223                 }
7224         }
7225
7226         switch (fsp->flow_type) {
7227         case TCP_V4_FLOW:
7228         case UDP_V4_FLOW:
7229         case SCTP_V4_FLOW:
7230         case AH_V4_FLOW:
7231         case ESP_V4_FLOW:
7232                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7233                 break;
7234         case TCP_V6_FLOW:
7235         case UDP_V6_FLOW:
7236         case SCTP_V6_FLOW:
7237         case AH_V6_FLOW:
7238         case ESP_V6_FLOW:
7239                 /* Not yet implemented */
7240                 ret = -EINVAL;
7241                 break;
7242         case IP_USER_FLOW:
7243                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7244                 break;
7245         default:
7246                 ret = -EINVAL;
7247                 break;
7248         }
7249
7250         if (ret < 0)
7251                 goto out;
7252
7253         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7254                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7255         else
7256                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7257                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7258
7259         /* put the tcam size here */
7260         nfc->data = tcam_get_size(np);
7261 out:
7262         return ret;
7263 }
7264
7265 static int niu_get_ethtool_tcam_all(struct niu *np,
7266                                     struct ethtool_rxnfc *nfc,
7267                                     u32 *rule_locs)
7268 {
7269         struct niu_parent *parent = np->parent;
7270         struct niu_tcam_entry *tp;
7271         int i, idx, cnt;
7272         u16 n_entries;
7273         unsigned long flags;
7274
7275
7276         /* put the tcam size here */
7277         nfc->data = tcam_get_size(np);
7278
7279         niu_lock_parent(np, flags);
7280         n_entries = nfc->rule_cnt;
7281         for (cnt = 0, i = 0; i < nfc->data; i++) {
7282                 idx = tcam_get_index(np, i);
7283                 tp = &parent->tcam[idx];
7284                 if (!tp->valid)
7285                         continue;
7286                 rule_locs[cnt] = i;
7287                 cnt++;
7288         }
7289         niu_unlock_parent(np, flags);
7290
7291         if (n_entries != cnt) {
7292                 /* print warning, this should not happen */
7293                 netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7294                             np->parent->index, __func__, n_entries, cnt);
7295         }
7296
7297         return 0;
7298 }
7299
7300 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7301                        void *rule_locs)
7302 {
7303         struct niu *np = netdev_priv(dev);
7304         int ret = 0;
7305
7306         switch (cmd->cmd) {
7307         case ETHTOOL_GRXFH:
7308                 ret = niu_get_hash_opts(np, cmd);
7309                 break;
7310         case ETHTOOL_GRXRINGS:
7311                 cmd->data = np->num_rx_rings;
7312                 break;
7313         case ETHTOOL_GRXCLSRLCNT:
7314                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7315                 break;
7316         case ETHTOOL_GRXCLSRULE:
7317                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7318                 break;
7319         case ETHTOOL_GRXCLSRLALL:
7320                 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7321                 break;
7322         default:
7323                 ret = -EINVAL;
7324                 break;
7325         }
7326
7327         return ret;
7328 }
7329
7330 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7331 {
7332         u64 class;
7333         u64 flow_key = 0;
7334         unsigned long flags;
7335
7336         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7337                 return -EINVAL;
7338
7339         if (class < CLASS_CODE_USER_PROG1 ||
7340             class > CLASS_CODE_SCTP_IPV6)
7341                 return -EINVAL;
7342
7343         if (nfc->data & RXH_DISCARD) {
7344                 niu_lock_parent(np, flags);
7345                 flow_key = np->parent->tcam_key[class -
7346                                                CLASS_CODE_USER_PROG1];
7347                 flow_key |= TCAM_KEY_DISC;
7348                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7349                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7350                 niu_unlock_parent(np, flags);
7351                 return 0;
7352         } else {
7353                 /* Discard was set before, but is not set now */
7354                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7355                     TCAM_KEY_DISC) {
7356                         niu_lock_parent(np, flags);
7357                         flow_key = np->parent->tcam_key[class -
7358                                                CLASS_CODE_USER_PROG1];
7359                         flow_key &= ~TCAM_KEY_DISC;
7360                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7361                              flow_key);
7362                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7363                                 flow_key;
7364                         niu_unlock_parent(np, flags);
7365                 }
7366         }
7367
7368         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7369                 return -EINVAL;
7370
7371         niu_lock_parent(np, flags);
7372         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7373         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7374         niu_unlock_parent(np, flags);
7375
7376         return 0;
7377 }
7378
7379 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7380                                        struct niu_tcam_entry *tp,
7381                                        int l2_rdc_tab, u64 class)
7382 {
7383         u8 pid = 0;
7384         u32 sip, dip, sipm, dipm, spi, spim;
7385         u16 sport, dport, spm, dpm;
7386
7387         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7388         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7389         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7390         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7391
7392         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7393         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7394         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7395         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7396
7397         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7398         tp->key[3] |= dip;
7399
7400         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7401         tp->key_mask[3] |= dipm;
7402
7403         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7404                        TCAM_V4KEY2_TOS_SHIFT);
7405         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7406                             TCAM_V4KEY2_TOS_SHIFT);
7407         switch (fsp->flow_type) {
7408         case TCP_V4_FLOW:
7409         case UDP_V4_FLOW:
7410         case SCTP_V4_FLOW:
7411                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7412                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7413                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7414                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7415
7416                 tp->key[2] |= (((u64)sport << 16) | dport);
7417                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7418                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7419                 break;
7420         case AH_V4_FLOW:
7421         case ESP_V4_FLOW:
7422                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7423                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7424
7425                 tp->key[2] |= spi;
7426                 tp->key_mask[2] |= spim;
7427                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7428                 break;
7429         case IP_USER_FLOW:
7430                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7431                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7432
7433                 tp->key[2] |= spi;
7434                 tp->key_mask[2] |= spim;
7435                 pid = fsp->h_u.usr_ip4_spec.proto;
7436                 break;
7437         default:
7438                 break;
7439         }
7440
7441         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7442         if (pid) {
7443                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7444         }
7445 }
7446
7447 static int niu_add_ethtool_tcam_entry(struct niu *np,
7448                                       struct ethtool_rxnfc *nfc)
7449 {
7450         struct niu_parent *parent = np->parent;
7451         struct niu_tcam_entry *tp;
7452         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7453         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7454         int l2_rdc_table = rdc_table->first_table_num;
7455         u16 idx;
7456         u64 class;
7457         unsigned long flags;
7458         int err, ret;
7459
7460         ret = 0;
7461
7462         idx = nfc->fs.location;
7463         if (idx >= tcam_get_size(np))
7464                 return -EINVAL;
7465
7466         if (fsp->flow_type == IP_USER_FLOW) {
7467                 int i;
7468                 int add_usr_cls = 0;
7469                 int ipv6 = 0;
7470                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7471                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7472
7473                 niu_lock_parent(np, flags);
7474
7475                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7476                         if (parent->l3_cls[i]) {
7477                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7478                                         class = parent->l3_cls[i];
7479                                         parent->l3_cls_refcnt[i]++;
7480                                         add_usr_cls = 1;
7481                                         break;
7482                                 }
7483                         } else {
7484                                 /* Program new user IP class */
7485                                 switch (i) {
7486                                 case 0:
7487                                         class = CLASS_CODE_USER_PROG1;
7488                                         break;
7489                                 case 1:
7490                                         class = CLASS_CODE_USER_PROG2;
7491                                         break;
7492                                 case 2:
7493                                         class = CLASS_CODE_USER_PROG3;
7494                                         break;
7495                                 case 3:
7496                                         class = CLASS_CODE_USER_PROG4;
7497                                         break;
7498                                 default:
7499                                         break;
7500                                 }
7501                                 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7502                                         ipv6 = 1;
7503                                 ret = tcam_user_ip_class_set(np, class, ipv6,
7504                                                              uspec->proto,
7505                                                              uspec->tos,
7506                                                              umask->tos);
7507                                 if (ret)
7508                                         goto out;
7509
7510                                 ret = tcam_user_ip_class_enable(np, class, 1);
7511                                 if (ret)
7512                                         goto out;
7513                                 parent->l3_cls[i] = class;
7514                                 parent->l3_cls_pid[i] = uspec->proto;
7515                                 parent->l3_cls_refcnt[i]++;
7516                                 add_usr_cls = 1;
7517                                 break;
7518                         }
7519                 }
7520                 if (!add_usr_cls) {
7521                         netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7522                                     parent->index, __func__, uspec->proto);
7523                         ret = -EINVAL;
7524                         goto out;
7525                 }
7526                 niu_unlock_parent(np, flags);
7527         } else {
7528                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7529                         return -EINVAL;
7530                 }
7531         }
7532
7533         niu_lock_parent(np, flags);
7534
7535         idx = tcam_get_index(np, idx);
7536         tp = &parent->tcam[idx];
7537
7538         memset(tp, 0, sizeof(*tp));
7539
7540         /* fill in the tcam key and mask */
7541         switch (fsp->flow_type) {
7542         case TCP_V4_FLOW:
7543         case UDP_V4_FLOW:
7544         case SCTP_V4_FLOW:
7545         case AH_V4_FLOW:
7546         case ESP_V4_FLOW:
7547                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7548                 break;
7549         case TCP_V6_FLOW:
7550         case UDP_V6_FLOW:
7551         case SCTP_V6_FLOW:
7552         case AH_V6_FLOW:
7553         case ESP_V6_FLOW:
7554                 /* Not yet implemented */
7555                 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7556                             parent->index, __func__, fsp->flow_type);
7557                 ret = -EINVAL;
7558                 goto out;
7559         case IP_USER_FLOW:
7560                 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7561                         niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7562                                                    class);
7563                 } else {
7564                         /* Not yet implemented */
7565                         netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7566                                     parent->index, __func__);
7567                         ret = -EINVAL;
7568                         goto out;
7569                 }
7570                 break;
7571         default:
7572                 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7573                             parent->index, __func__, fsp->flow_type);
7574                 ret = -EINVAL;
7575                 goto out;
7576         }
7577
7578         /* fill in the assoc data */
7579         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7580                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7581         } else {
7582                 if (fsp->ring_cookie >= np->num_rx_rings) {
7583                         netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7584                                     parent->index, __func__,
7585                                     (long long)fsp->ring_cookie);
7586                         ret = -EINVAL;
7587                         goto out;
7588                 }
7589                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7590                                   (fsp->ring_cookie <<
7591                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7592         }
7593
7594         err = tcam_write(np, idx, tp->key, tp->key_mask);
7595         if (err) {
7596                 ret = -EINVAL;
7597                 goto out;
7598         }
7599         err = tcam_assoc_write(np, idx, tp->assoc_data);
7600         if (err) {
7601                 ret = -EINVAL;
7602                 goto out;
7603         }
7604
7605         /* validate the entry */
7606         tp->valid = 1;
7607         np->clas.tcam_valid_entries++;
7608 out:
7609         niu_unlock_parent(np, flags);
7610
7611         return ret;
7612 }
7613
7614 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7615 {
7616         struct niu_parent *parent = np->parent;
7617         struct niu_tcam_entry *tp;
7618         u16 idx;
7619         unsigned long flags;
7620         u64 class;
7621         int ret = 0;
7622
7623         if (loc >= tcam_get_size(np))
7624                 return -EINVAL;
7625
7626         niu_lock_parent(np, flags);
7627
7628         idx = tcam_get_index(np, loc);
7629         tp = &parent->tcam[idx];
7630
7631         /* if the entry is of a user defined class, then update*/
7632         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7633                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7634
7635         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7636                 int i;
7637                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7638                         if (parent->l3_cls[i] == class) {
7639                                 parent->l3_cls_refcnt[i]--;
7640                                 if (!parent->l3_cls_refcnt[i]) {
7641                                         /* disable class */
7642                                         ret = tcam_user_ip_class_enable(np,
7643                                                                         class,
7644                                                                         0);
7645                                         if (ret)
7646                                                 goto out;
7647                                         parent->l3_cls[i] = 0;
7648                                         parent->l3_cls_pid[i] = 0;
7649                                 }
7650                                 break;
7651                         }
7652                 }
7653                 if (i == NIU_L3_PROG_CLS) {
7654                         netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7655                                     parent->index, __func__,
7656                                     (unsigned long long)class);
7657                         ret = -EINVAL;
7658                         goto out;
7659                 }
7660         }
7661
7662         ret = tcam_flush(np, idx);
7663         if (ret)
7664                 goto out;
7665
7666         /* invalidate the entry */
7667         tp->valid = 0;
7668         np->clas.tcam_valid_entries--;
7669 out:
7670         niu_unlock_parent(np, flags);
7671
7672         return ret;
7673 }
7674
7675 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7676 {
7677         struct niu *np = netdev_priv(dev);
7678         int ret = 0;
7679
7680         switch (cmd->cmd) {
7681         case ETHTOOL_SRXFH:
7682                 ret = niu_set_hash_opts(np, cmd);
7683                 break;
7684         case ETHTOOL_SRXCLSRLINS:
7685                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7686                 break;
7687         case ETHTOOL_SRXCLSRLDEL:
7688                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7689                 break;
7690         default:
7691                 ret = -EINVAL;
7692                 break;
7693         }
7694
7695         return ret;
7696 }
7697
7698 static const struct {
7699         const char string[ETH_GSTRING_LEN];
7700 } niu_xmac_stat_keys[] = {
7701         { "tx_frames" },
7702         { "tx_bytes" },
7703         { "tx_fifo_errors" },
7704         { "tx_overflow_errors" },
7705         { "tx_max_pkt_size_errors" },
7706         { "tx_underflow_errors" },
7707         { "rx_local_faults" },
7708         { "rx_remote_faults" },
7709         { "rx_link_faults" },
7710         { "rx_align_errors" },
7711         { "rx_frags" },
7712         { "rx_mcasts" },
7713         { "rx_bcasts" },
7714         { "rx_hist_cnt1" },
7715         { "rx_hist_cnt2" },
7716         { "rx_hist_cnt3" },
7717         { "rx_hist_cnt4" },
7718         { "rx_hist_cnt5" },
7719         { "rx_hist_cnt6" },
7720         { "rx_hist_cnt7" },
7721         { "rx_octets" },
7722         { "rx_code_violations" },
7723         { "rx_len_errors" },
7724         { "rx_crc_errors" },
7725         { "rx_underflows" },
7726         { "rx_overflows" },
7727         { "pause_off_state" },
7728         { "pause_on_state" },
7729         { "pause_received" },
7730 };
7731
7732 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7733
7734 static const struct {
7735         const char string[ETH_GSTRING_LEN];
7736 } niu_bmac_stat_keys[] = {
7737         { "tx_underflow_errors" },
7738         { "tx_max_pkt_size_errors" },
7739         { "tx_bytes" },
7740         { "tx_frames" },
7741         { "rx_overflows" },
7742         { "rx_frames" },
7743         { "rx_align_errors" },
7744         { "rx_crc_errors" },
7745         { "rx_len_errors" },
7746         { "pause_off_state" },
7747         { "pause_on_state" },
7748         { "pause_received" },
7749 };
7750
7751 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7752
7753 static const struct {
7754         const char string[ETH_GSTRING_LEN];
7755 } niu_rxchan_stat_keys[] = {
7756         { "rx_channel" },
7757         { "rx_packets" },
7758         { "rx_bytes" },
7759         { "rx_dropped" },
7760         { "rx_errors" },
7761 };
7762
7763 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7764
7765 static const struct {
7766         const char string[ETH_GSTRING_LEN];
7767 } niu_txchan_stat_keys[] = {
7768         { "tx_channel" },
7769         { "tx_packets" },
7770         { "tx_bytes" },
7771         { "tx_errors" },
7772 };
7773
7774 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7775
7776 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7777 {
7778         struct niu *np = netdev_priv(dev);
7779         int i;
7780
7781         if (stringset != ETH_SS_STATS)
7782                 return;
7783
7784         if (np->flags & NIU_FLAGS_XMAC) {
7785                 memcpy(data, niu_xmac_stat_keys,
7786                        sizeof(niu_xmac_stat_keys));
7787                 data += sizeof(niu_xmac_stat_keys);
7788         } else {
7789                 memcpy(data, niu_bmac_stat_keys,
7790                        sizeof(niu_bmac_stat_keys));
7791                 data += sizeof(niu_bmac_stat_keys);
7792         }
7793         for (i = 0; i < np->num_rx_rings; i++) {
7794                 memcpy(data, niu_rxchan_stat_keys,
7795                        sizeof(niu_rxchan_stat_keys));
7796                 data += sizeof(niu_rxchan_stat_keys);
7797         }
7798         for (i = 0; i < np->num_tx_rings; i++) {
7799                 memcpy(data, niu_txchan_stat_keys,
7800                        sizeof(niu_txchan_stat_keys));
7801                 data += sizeof(niu_txchan_stat_keys);
7802         }
7803 }
7804
7805 static int niu_get_sset_count(struct net_device *dev, int stringset)
7806 {
7807         struct niu *np = netdev_priv(dev);
7808
7809         if (stringset != ETH_SS_STATS)
7810                 return -EINVAL;
7811
7812         return ((np->flags & NIU_FLAGS_XMAC ?
7813                  NUM_XMAC_STAT_KEYS :
7814                  NUM_BMAC_STAT_KEYS) +
7815                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7816                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7817 }
7818
7819 static void niu_get_ethtool_stats(struct net_device *dev,
7820                                   struct ethtool_stats *stats, u64 *data)
7821 {
7822         struct niu *np = netdev_priv(dev);
7823         int i;
7824
7825         niu_sync_mac_stats(np);
7826         if (np->flags & NIU_FLAGS_XMAC) {
7827                 memcpy(data, &np->mac_stats.xmac,
7828                        sizeof(struct niu_xmac_stats));
7829                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7830         } else {
7831                 memcpy(data, &np->mac_stats.bmac,
7832                        sizeof(struct niu_bmac_stats));
7833                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7834         }
7835         for (i = 0; i < np->num_rx_rings; i++) {
7836                 struct rx_ring_info *rp = &np->rx_rings[i];
7837
7838                 niu_sync_rx_discard_stats(np, rp, 0);
7839
7840                 data[0] = rp->rx_channel;
7841                 data[1] = rp->rx_packets;
7842                 data[2] = rp->rx_bytes;
7843                 data[3] = rp->rx_dropped;
7844                 data[4] = rp->rx_errors;
7845                 data += 5;
7846         }
7847         for (i = 0; i < np->num_tx_rings; i++) {
7848                 struct tx_ring_info *rp = &np->tx_rings[i];
7849
7850                 data[0] = rp->tx_channel;
7851                 data[1] = rp->tx_packets;
7852                 data[2] = rp->tx_bytes;
7853                 data[3] = rp->tx_errors;
7854                 data += 4;
7855         }
7856 }
7857
7858 static u64 niu_led_state_save(struct niu *np)
7859 {
7860         if (np->flags & NIU_FLAGS_XMAC)
7861                 return nr64_mac(XMAC_CONFIG);
7862         else
7863                 return nr64_mac(BMAC_XIF_CONFIG);
7864 }
7865
7866 static void niu_led_state_restore(struct niu *np, u64 val)
7867 {
7868         if (np->flags & NIU_FLAGS_XMAC)
7869                 nw64_mac(XMAC_CONFIG, val);
7870         else
7871                 nw64_mac(BMAC_XIF_CONFIG, val);
7872 }
7873
7874 static void niu_force_led(struct niu *np, int on)
7875 {
7876         u64 val, reg, bit;
7877
7878         if (np->flags & NIU_FLAGS_XMAC) {
7879                 reg = XMAC_CONFIG;
7880                 bit = XMAC_CONFIG_FORCE_LED_ON;
7881         } else {
7882                 reg = BMAC_XIF_CONFIG;
7883                 bit = BMAC_XIF_CONFIG_LINK_LED;
7884         }
7885
7886         val = nr64_mac(reg);
7887         if (on)
7888                 val |= bit;
7889         else
7890                 val &= ~bit;
7891         nw64_mac(reg, val);
7892 }
7893
7894 static int niu_phys_id(struct net_device *dev, u32 data)
7895 {
7896         struct niu *np = netdev_priv(dev);
7897         u64 orig_led_state;
7898         int i;
7899
7900         if (!netif_running(dev))
7901                 return -EAGAIN;
7902
7903         if (data == 0)
7904                 data = 2;
7905
7906         orig_led_state = niu_led_state_save(np);
7907         for (i = 0; i < (data * 2); i++) {
7908                 int on = ((i % 2) == 0);
7909
7910                 niu_force_led(np, on);
7911
7912                 if (msleep_interruptible(500))
7913                         break;
7914         }
7915         niu_led_state_restore(np, orig_led_state);
7916
7917         return 0;
7918 }
7919
7920 static const struct ethtool_ops niu_ethtool_ops = {
7921         .get_drvinfo            = niu_get_drvinfo,
7922         .get_link               = ethtool_op_get_link,
7923         .get_msglevel           = niu_get_msglevel,
7924         .set_msglevel           = niu_set_msglevel,
7925         .nway_reset             = niu_nway_reset,
7926         .get_eeprom_len         = niu_get_eeprom_len,
7927         .get_eeprom             = niu_get_eeprom,
7928         .get_settings           = niu_get_settings,
7929         .set_settings           = niu_set_settings,
7930         .get_strings            = niu_get_strings,
7931         .get_sset_count         = niu_get_sset_count,
7932         .get_ethtool_stats      = niu_get_ethtool_stats,
7933         .phys_id                = niu_phys_id,
7934         .get_rxnfc              = niu_get_nfc,
7935         .set_rxnfc              = niu_set_nfc,
7936 };
7937
7938 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7939                               int ldg, int ldn)
7940 {
7941         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7942                 return -EINVAL;
7943         if (ldn < 0 || ldn > LDN_MAX)
7944                 return -EINVAL;
7945
7946         parent->ldg_map[ldn] = ldg;
7947
7948         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7949                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7950                  * the firmware, and we're not supposed to change them.
7951                  * Validate the mapping, because if it's wrong we probably
7952                  * won't get any interrupts and that's painful to debug.
7953                  */
7954                 if (nr64(LDG_NUM(ldn)) != ldg) {
7955                         dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7956                                 np->port, ldn, ldg,
7957                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7958                         return -EINVAL;
7959                 }
7960         } else
7961                 nw64(LDG_NUM(ldn), ldg);
7962
7963         return 0;
7964 }
7965
7966 static int niu_set_ldg_timer_res(struct niu *np, int res)
7967 {
7968         if (res < 0 || res > LDG_TIMER_RES_VAL)
7969                 return -EINVAL;
7970
7971
7972         nw64(LDG_TIMER_RES, res);
7973
7974         return 0;
7975 }
7976
7977 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7978 {
7979         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7980             (func < 0 || func > 3) ||
7981             (vector < 0 || vector > 0x1f))
7982                 return -EINVAL;
7983
7984         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7985
7986         return 0;
7987 }
7988
7989 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7990 {
7991         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7992                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7993         int limit;
7994
7995         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7996                 return -EINVAL;
7997
7998         frame = frame_base;
7999         nw64(ESPC_PIO_STAT, frame);
8000         limit = 64;
8001         do {
8002                 udelay(5);
8003                 frame = nr64(ESPC_PIO_STAT);
8004                 if (frame & ESPC_PIO_STAT_READ_END)
8005                         break;
8006         } while (limit--);
8007         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8008                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8009                         (unsigned long long) frame);
8010                 return -ENODEV;
8011         }
8012
8013         frame = frame_base;
8014         nw64(ESPC_PIO_STAT, frame);
8015         limit = 64;
8016         do {
8017                 udelay(5);
8018                 frame = nr64(ESPC_PIO_STAT);
8019                 if (frame & ESPC_PIO_STAT_READ_END)
8020                         break;
8021         } while (limit--);
8022         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8023                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8024                         (unsigned long long) frame);
8025                 return -ENODEV;
8026         }
8027
8028         frame = nr64(ESPC_PIO_STAT);
8029         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8030 }
8031
8032 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8033 {
8034         int err = niu_pci_eeprom_read(np, off);
8035         u16 val;
8036
8037         if (err < 0)
8038                 return err;
8039         val = (err << 8);
8040         err = niu_pci_eeprom_read(np, off + 1);
8041         if (err < 0)
8042                 return err;
8043         val |= (err & 0xff);
8044
8045         return val;
8046 }
8047
8048 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8049 {
8050         int err = niu_pci_eeprom_read(np, off);
8051         u16 val;
8052
8053         if (err < 0)
8054                 return err;
8055
8056         val = (err & 0xff);
8057         err = niu_pci_eeprom_read(np, off + 1);
8058         if (err < 0)
8059                 return err;
8060
8061         val |= (err & 0xff) << 8;
8062
8063         return val;
8064 }
8065
8066 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8067                                               u32 off,
8068                                               char *namebuf,
8069                                               int namebuf_len)
8070 {
8071         int i;
8072
8073         for (i = 0; i < namebuf_len; i++) {
8074                 int err = niu_pci_eeprom_read(np, off + i);
8075                 if (err < 0)
8076                         return err;
8077                 *namebuf++ = err;
8078                 if (!err)
8079                         break;
8080         }
8081         if (i >= namebuf_len)
8082                 return -EINVAL;
8083
8084         return i + 1;
8085 }
8086
8087 static void __devinit niu_vpd_parse_version(struct niu *np)
8088 {
8089         struct niu_vpd *vpd = &np->vpd;
8090         int len = strlen(vpd->version) + 1;
8091         const char *s = vpd->version;
8092         int i;
8093
8094         for (i = 0; i < len - 5; i++) {
8095                 if (!strncmp(s + i, "FCode ", 6))
8096                         break;
8097         }
8098         if (i >= len - 5)
8099                 return;
8100
8101         s += i + 5;
8102         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8103
8104         netif_printk(np, probe, KERN_DEBUG, np->dev,
8105                      "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8106                      vpd->fcode_major, vpd->fcode_minor);
8107         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8108             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8109              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8110                 np->flags |= NIU_FLAGS_VPD_VALID;
8111 }
8112
8113 /* ESPC_PIO_EN_ENABLE must be set */
8114 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8115                                             u32 start, u32 end)
8116 {
8117         unsigned int found_mask = 0;
8118 #define FOUND_MASK_MODEL        0x00000001
8119 #define FOUND_MASK_BMODEL       0x00000002
8120 #define FOUND_MASK_VERS         0x00000004
8121 #define FOUND_MASK_MAC          0x00000008
8122 #define FOUND_MASK_NMAC         0x00000010
8123 #define FOUND_MASK_PHY          0x00000020
8124 #define FOUND_MASK_ALL          0x0000003f
8125
8126         netif_printk(np, probe, KERN_DEBUG, np->dev,
8127                      "VPD_SCAN: start[%x] end[%x]\n", start, end);
8128         while (start < end) {
8129                 int len, err, instance, type, prop_len;
8130                 char namebuf[64];
8131                 u8 *prop_buf;
8132                 int max_len;
8133
8134                 if (found_mask == FOUND_MASK_ALL) {
8135                         niu_vpd_parse_version(np);
8136                         return 1;
8137                 }
8138
8139                 err = niu_pci_eeprom_read(np, start + 2);
8140                 if (err < 0)
8141                         return err;
8142                 len = err;
8143                 start += 3;
8144
8145                 instance = niu_pci_eeprom_read(np, start);
8146                 type = niu_pci_eeprom_read(np, start + 3);
8147                 prop_len = niu_pci_eeprom_read(np, start + 4);
8148                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8149                 if (err < 0)
8150                         return err;
8151
8152                 prop_buf = NULL;
8153                 max_len = 0;
8154                 if (!strcmp(namebuf, "model")) {
8155                         prop_buf = np->vpd.model;
8156                         max_len = NIU_VPD_MODEL_MAX;
8157                         found_mask |= FOUND_MASK_MODEL;
8158                 } else if (!strcmp(namebuf, "board-model")) {
8159                         prop_buf = np->vpd.board_model;
8160                         max_len = NIU_VPD_BD_MODEL_MAX;
8161                         found_mask |= FOUND_MASK_BMODEL;
8162                 } else if (!strcmp(namebuf, "version")) {
8163                         prop_buf = np->vpd.version;
8164                         max_len = NIU_VPD_VERSION_MAX;
8165                         found_mask |= FOUND_MASK_VERS;
8166                 } else if (!strcmp(namebuf, "local-mac-address")) {
8167                         prop_buf = np->vpd.local_mac;
8168                         max_len = ETH_ALEN;
8169                         found_mask |= FOUND_MASK_MAC;
8170                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8171                         prop_buf = &np->vpd.mac_num;
8172                         max_len = 1;
8173                         found_mask |= FOUND_MASK_NMAC;
8174                 } else if (!strcmp(namebuf, "phy-type")) {
8175                         prop_buf = np->vpd.phy_type;
8176                         max_len = NIU_VPD_PHY_TYPE_MAX;
8177                         found_mask |= FOUND_MASK_PHY;
8178                 }
8179
8180                 if (max_len && prop_len > max_len) {
8181                         dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8182                         return -EINVAL;
8183                 }
8184
8185                 if (prop_buf) {
8186                         u32 off = start + 5 + err;
8187                         int i;
8188
8189                         netif_printk(np, probe, KERN_DEBUG, np->dev,
8190                                      "VPD_SCAN: Reading in property [%s] len[%d]\n",
8191                                      namebuf, prop_len);
8192                         for (i = 0; i < prop_len; i++)
8193                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8194                 }
8195
8196                 start += len;
8197         }
8198
8199         return 0;
8200 }
8201
8202 /* ESPC_PIO_EN_ENABLE must be set */
8203 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8204 {
8205         u32 offset;
8206         int err;
8207
8208         err = niu_pci_eeprom_read16_swp(np, start + 1);
8209         if (err < 0)
8210                 return;
8211
8212         offset = err + 3;
8213
8214         while (start + offset < ESPC_EEPROM_SIZE) {
8215                 u32 here = start + offset;
8216                 u32 end;
8217
8218                 err = niu_pci_eeprom_read(np, here);
8219                 if (err != 0x90)
8220                         return;
8221
8222                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8223                 if (err < 0)
8224                         return;
8225
8226                 here = start + offset + 3;
8227                 end = start + offset + err;
8228
8229                 offset += err;
8230
8231                 err = niu_pci_vpd_scan_props(np, here, end);
8232                 if (err < 0 || err == 1)
8233                         return;
8234         }
8235 }
8236
8237 /* ESPC_PIO_EN_ENABLE must be set */
8238 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8239 {
8240         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8241         int err;
8242
8243         while (start < end) {
8244                 ret = start;
8245
8246                 /* ROM header signature?  */
8247                 err = niu_pci_eeprom_read16(np, start +  0);
8248                 if (err != 0x55aa)
8249                         return 0;
8250
8251                 /* Apply offset to PCI data structure.  */
8252                 err = niu_pci_eeprom_read16(np, start + 23);
8253                 if (err < 0)
8254                         return 0;
8255                 start += err;
8256
8257                 /* Check for "PCIR" signature.  */
8258                 err = niu_pci_eeprom_read16(np, start +  0);
8259                 if (err != 0x5043)
8260                         return 0;
8261                 err = niu_pci_eeprom_read16(np, start +  2);
8262                 if (err != 0x4952)
8263                         return 0;
8264
8265                 /* Check for OBP image type.  */
8266                 err = niu_pci_eeprom_read(np, start + 20);
8267                 if (err < 0)
8268                         return 0;
8269                 if (err != 0x01) {
8270                         err = niu_pci_eeprom_read(np, ret + 2);
8271                         if (err < 0)
8272                                 return 0;
8273
8274                         start = ret + (err * 512);
8275                         continue;
8276                 }
8277
8278                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8279                 if (err < 0)
8280                         return err;
8281                 ret += err;
8282
8283                 err = niu_pci_eeprom_read(np, ret + 0);
8284                 if (err != 0x82)
8285                         return 0;
8286
8287                 return ret;
8288         }
8289
8290         return 0;
8291 }
8292
8293 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8294                                               const char *phy_prop)
8295 {
8296         if (!strcmp(phy_prop, "mif")) {
8297                 /* 1G copper, MII */
8298                 np->flags &= ~(NIU_FLAGS_FIBER |
8299                                NIU_FLAGS_10G);
8300                 np->mac_xcvr = MAC_XCVR_MII;
8301         } else if (!strcmp(phy_prop, "xgf")) {
8302                 /* 10G fiber, XPCS */
8303                 np->flags |= (NIU_FLAGS_10G |
8304                               NIU_FLAGS_FIBER);
8305                 np->mac_xcvr = MAC_XCVR_XPCS;
8306         } else if (!strcmp(phy_prop, "pcs")) {
8307                 /* 1G fiber, PCS */
8308                 np->flags &= ~NIU_FLAGS_10G;
8309                 np->flags |= NIU_FLAGS_FIBER;
8310                 np->mac_xcvr = MAC_XCVR_PCS;
8311         } else if (!strcmp(phy_prop, "xgc")) {
8312                 /* 10G copper, XPCS */
8313                 np->flags |= NIU_FLAGS_10G;
8314                 np->flags &= ~NIU_FLAGS_FIBER;
8315                 np->mac_xcvr = MAC_XCVR_XPCS;
8316         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8317                 /* 10G Serdes or 1G Serdes, default to 10G */
8318                 np->flags |= NIU_FLAGS_10G;
8319                 np->flags &= ~NIU_FLAGS_FIBER;
8320                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8321                 np->mac_xcvr = MAC_XCVR_XPCS;
8322         } else {
8323                 return -EINVAL;
8324         }
8325         return 0;
8326 }
8327
8328 static int niu_pci_vpd_get_nports(struct niu *np)
8329 {
8330         int ports = 0;
8331
8332         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8333             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8334             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8335             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8336             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8337                 ports = 4;
8338         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8339                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8340                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8341                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8342                 ports = 2;
8343         }
8344
8345         return ports;
8346 }
8347
8348 static void __devinit niu_pci_vpd_validate(struct niu *np)
8349 {
8350         struct net_device *dev = np->dev;
8351         struct niu_vpd *vpd = &np->vpd;
8352         u8 val8;
8353
8354         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8355                 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8356
8357                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8358                 return;
8359         }
8360
8361         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8362             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8363                 np->flags |= NIU_FLAGS_10G;
8364                 np->flags &= ~NIU_FLAGS_FIBER;
8365                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8366                 np->mac_xcvr = MAC_XCVR_PCS;
8367                 if (np->port > 1) {
8368                         np->flags |= NIU_FLAGS_FIBER;
8369                         np->flags &= ~NIU_FLAGS_10G;
8370                 }
8371                 if (np->flags & NIU_FLAGS_10G)
8372                         np->mac_xcvr = MAC_XCVR_XPCS;
8373         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8374                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8375                               NIU_FLAGS_HOTPLUG_PHY);
8376         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8377                 dev_err(np->device, "Illegal phy string [%s]\n",
8378                         np->vpd.phy_type);
8379                 dev_err(np->device, "Falling back to SPROM\n");
8380                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8381                 return;
8382         }
8383
8384         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8385
8386         val8 = dev->perm_addr[5];
8387         dev->perm_addr[5] += np->port;
8388         if (dev->perm_addr[5] < val8)
8389                 dev->perm_addr[4]++;
8390
8391         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8392 }
8393
8394 static int __devinit niu_pci_probe_sprom(struct niu *np)
8395 {
8396         struct net_device *dev = np->dev;
8397         int len, i;
8398         u64 val, sum;
8399         u8 val8;
8400
8401         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8402         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8403         len = val / 4;
8404
8405         np->eeprom_len = len;
8406
8407         netif_printk(np, probe, KERN_DEBUG, np->dev,
8408                      "SPROM: Image size %llu\n", (unsigned long long)val);
8409
8410         sum = 0;
8411         for (i = 0; i < len; i++) {
8412                 val = nr64(ESPC_NCR(i));
8413                 sum += (val >>  0) & 0xff;
8414                 sum += (val >>  8) & 0xff;
8415                 sum += (val >> 16) & 0xff;
8416                 sum += (val >> 24) & 0xff;
8417         }
8418         netif_printk(np, probe, KERN_DEBUG, np->dev,
8419                      "SPROM: Checksum %x\n", (int)(sum & 0xff));
8420         if ((sum & 0xff) != 0xab) {
8421                 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8422                 return -EINVAL;
8423         }
8424
8425         val = nr64(ESPC_PHY_TYPE);
8426         switch (np->port) {
8427         case 0:
8428                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8429                         ESPC_PHY_TYPE_PORT0_SHIFT;
8430                 break;
8431         case 1:
8432                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8433                         ESPC_PHY_TYPE_PORT1_SHIFT;
8434                 break;
8435         case 2:
8436                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8437                         ESPC_PHY_TYPE_PORT2_SHIFT;
8438                 break;
8439         case 3:
8440                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8441                         ESPC_PHY_TYPE_PORT3_SHIFT;
8442                 break;
8443         default:
8444                 dev_err(np->device, "Bogus port number %u\n",
8445                         np->port);
8446                 return -EINVAL;
8447         }
8448         netif_printk(np, probe, KERN_DEBUG, np->dev,
8449                      "SPROM: PHY type %x\n", val8);
8450
8451         switch (val8) {
8452         case ESPC_PHY_TYPE_1G_COPPER:
8453                 /* 1G copper, MII */
8454                 np->flags &= ~(NIU_FLAGS_FIBER |
8455                                NIU_FLAGS_10G);
8456                 np->mac_xcvr = MAC_XCVR_MII;
8457                 break;
8458
8459         case ESPC_PHY_TYPE_1G_FIBER:
8460                 /* 1G fiber, PCS */
8461                 np->flags &= ~NIU_FLAGS_10G;
8462                 np->flags |= NIU_FLAGS_FIBER;
8463                 np->mac_xcvr = MAC_XCVR_PCS;
8464                 break;
8465
8466         case ESPC_PHY_TYPE_10G_COPPER:
8467                 /* 10G copper, XPCS */
8468                 np->flags |= NIU_FLAGS_10G;
8469                 np->flags &= ~NIU_FLAGS_FIBER;
8470                 np->mac_xcvr = MAC_XCVR_XPCS;
8471                 break;
8472
8473         case ESPC_PHY_TYPE_10G_FIBER:
8474                 /* 10G fiber, XPCS */
8475                 np->flags |= (NIU_FLAGS_10G |
8476                               NIU_FLAGS_FIBER);
8477                 np->mac_xcvr = MAC_XCVR_XPCS;
8478                 break;
8479
8480         default:
8481                 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8482                 return -EINVAL;
8483         }
8484
8485         val = nr64(ESPC_MAC_ADDR0);
8486         netif_printk(np, probe, KERN_DEBUG, np->dev,
8487                      "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8488         dev->perm_addr[0] = (val >>  0) & 0xff;
8489         dev->perm_addr[1] = (val >>  8) & 0xff;
8490         dev->perm_addr[2] = (val >> 16) & 0xff;
8491         dev->perm_addr[3] = (val >> 24) & 0xff;
8492
8493         val = nr64(ESPC_MAC_ADDR1);
8494         netif_printk(np, probe, KERN_DEBUG, np->dev,
8495                      "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8496         dev->perm_addr[4] = (val >>  0) & 0xff;
8497         dev->perm_addr[5] = (val >>  8) & 0xff;
8498
8499         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8500                 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8501                         dev->perm_addr);
8502                 return -EINVAL;
8503         }
8504
8505         val8 = dev->perm_addr[5];
8506         dev->perm_addr[5] += np->port;
8507         if (dev->perm_addr[5] < val8)
8508                 dev->perm_addr[4]++;
8509
8510         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8511
8512         val = nr64(ESPC_MOD_STR_LEN);
8513         netif_printk(np, probe, KERN_DEBUG, np->dev,
8514                      "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8515         if (val >= 8 * 4)
8516                 return -EINVAL;
8517
8518         for (i = 0; i < val; i += 4) {
8519                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8520
8521                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8522                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8523                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8524                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8525         }
8526         np->vpd.model[val] = '\0';
8527
8528         val = nr64(ESPC_BD_MOD_STR_LEN);
8529         netif_printk(np, probe, KERN_DEBUG, np->dev,
8530                      "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8531         if (val >= 4 * 4)
8532                 return -EINVAL;
8533
8534         for (i = 0; i < val; i += 4) {
8535                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8536
8537                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8538                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8539                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8540                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8541         }
8542         np->vpd.board_model[val] = '\0';
8543
8544         np->vpd.mac_num =
8545                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8546         netif_printk(np, probe, KERN_DEBUG, np->dev,
8547                      "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8548
8549         return 0;
8550 }
8551
8552 static int __devinit niu_get_and_validate_port(struct niu *np)
8553 {
8554         struct niu_parent *parent = np->parent;
8555
8556         if (np->port <= 1)
8557                 np->flags |= NIU_FLAGS_XMAC;
8558
8559         if (!parent->num_ports) {
8560                 if (parent->plat_type == PLAT_TYPE_NIU) {
8561                         parent->num_ports = 2;
8562                 } else {
8563                         parent->num_ports = niu_pci_vpd_get_nports(np);
8564                         if (!parent->num_ports) {
8565                                 /* Fall back to SPROM as last resort.
8566                                  * This will fail on most cards.
8567                                  */
8568                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8569                                         ESPC_NUM_PORTS_MACS_VAL;
8570
8571                                 /* All of the current probing methods fail on
8572                                  * Maramba on-board parts.
8573                                  */
8574                                 if (!parent->num_ports)
8575                                         parent->num_ports = 4;
8576                         }
8577                 }
8578         }
8579
8580         netif_printk(np, probe, KERN_DEBUG, np->dev,
8581                      "%s() port[%d] num_ports[%d]\n",
8582                      __func__, np->port, parent->num_ports);
8583         if (np->port >= parent->num_ports)
8584                 return -ENODEV;
8585
8586         return 0;
8587 }
8588
8589 static int __devinit phy_record(struct niu_parent *parent,
8590                                 struct phy_probe_info *p,
8591                                 int dev_id_1, int dev_id_2, u8 phy_port,
8592                                 int type)
8593 {
8594         u32 id = (dev_id_1 << 16) | dev_id_2;
8595         u8 idx;
8596
8597         if (dev_id_1 < 0 || dev_id_2 < 0)
8598                 return 0;
8599         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8600                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8601                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8602                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8603                         return 0;
8604         } else {
8605                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8606                         return 0;
8607         }
8608
8609         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8610                 parent->index, id,
8611                 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8612                 type == PHY_TYPE_PCS ? "PCS" : "MII",
8613                 phy_port);
8614
8615         if (p->cur[type] >= NIU_MAX_PORTS) {
8616                 pr_err("Too many PHY ports\n");
8617                 return -EINVAL;
8618         }
8619         idx = p->cur[type];
8620         p->phy_id[type][idx] = id;
8621         p->phy_port[type][idx] = phy_port;
8622         p->cur[type] = idx + 1;
8623         return 0;
8624 }
8625
8626 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8627 {
8628         int i;
8629
8630         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8631                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8632                         return 1;
8633         }
8634         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8635                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8636                         return 1;
8637         }
8638
8639         return 0;
8640 }
8641
8642 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8643 {
8644         int port, cnt;
8645
8646         cnt = 0;
8647         *lowest = 32;
8648         for (port = 8; port < 32; port++) {
8649                 if (port_has_10g(p, port)) {
8650                         if (!cnt)
8651                                 *lowest = port;
8652                         cnt++;
8653                 }
8654         }
8655
8656         return cnt;
8657 }
8658
8659 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8660 {
8661         *lowest = 32;
8662         if (p->cur[PHY_TYPE_MII])
8663                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8664
8665         return p->cur[PHY_TYPE_MII];
8666 }
8667
8668 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8669 {
8670         int num_ports = parent->num_ports;
8671         int i;
8672
8673         for (i = 0; i < num_ports; i++) {
8674                 parent->rxchan_per_port[i] = (16 / num_ports);
8675                 parent->txchan_per_port[i] = (16 / num_ports);
8676
8677                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8678                         parent->index, i,
8679                         parent->rxchan_per_port[i],
8680                         parent->txchan_per_port[i]);
8681         }
8682 }
8683
8684 static void __devinit niu_divide_channels(struct niu_parent *parent,
8685                                           int num_10g, int num_1g)
8686 {
8687         int num_ports = parent->num_ports;
8688         int rx_chans_per_10g, rx_chans_per_1g;
8689         int tx_chans_per_10g, tx_chans_per_1g;
8690         int i, tot_rx, tot_tx;
8691
8692         if (!num_10g || !num_1g) {
8693                 rx_chans_per_10g = rx_chans_per_1g =
8694                         (NIU_NUM_RXCHAN / num_ports);
8695                 tx_chans_per_10g = tx_chans_per_1g =
8696                         (NIU_NUM_TXCHAN / num_ports);
8697         } else {
8698                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8699                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8700                                     (rx_chans_per_1g * num_1g)) /
8701                         num_10g;
8702
8703                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8704                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8705                                     (tx_chans_per_1g * num_1g)) /
8706                         num_10g;
8707         }
8708
8709         tot_rx = tot_tx = 0;
8710         for (i = 0; i < num_ports; i++) {
8711                 int type = phy_decode(parent->port_phy, i);
8712
8713                 if (type == PORT_TYPE_10G) {
8714                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8715                         parent->txchan_per_port[i] = tx_chans_per_10g;
8716                 } else {
8717                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8718                         parent->txchan_per_port[i] = tx_chans_per_1g;
8719                 }
8720                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8721                         parent->index, i,
8722                         parent->rxchan_per_port[i],
8723                         parent->txchan_per_port[i]);
8724                 tot_rx += parent->rxchan_per_port[i];
8725                 tot_tx += parent->txchan_per_port[i];
8726         }
8727
8728         if (tot_rx > NIU_NUM_RXCHAN) {
8729                 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8730                        parent->index, tot_rx);
8731                 for (i = 0; i < num_ports; i++)
8732                         parent->rxchan_per_port[i] = 1;
8733         }
8734         if (tot_tx > NIU_NUM_TXCHAN) {
8735                 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8736                        parent->index, tot_tx);
8737                 for (i = 0; i < num_ports; i++)
8738                         parent->txchan_per_port[i] = 1;
8739         }
8740         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8741                 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8742                            parent->index, tot_rx, tot_tx);
8743         }
8744 }
8745
8746 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8747                                             int num_10g, int num_1g)
8748 {
8749         int i, num_ports = parent->num_ports;
8750         int rdc_group, rdc_groups_per_port;
8751         int rdc_channel_base;
8752
8753         rdc_group = 0;
8754         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8755
8756         rdc_channel_base = 0;
8757
8758         for (i = 0; i < num_ports; i++) {
8759                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8760                 int grp, num_channels = parent->rxchan_per_port[i];
8761                 int this_channel_offset;
8762
8763                 tp->first_table_num = rdc_group;
8764                 tp->num_tables = rdc_groups_per_port;
8765                 this_channel_offset = 0;
8766                 for (grp = 0; grp < tp->num_tables; grp++) {
8767                         struct rdc_table *rt = &tp->tables[grp];
8768                         int slot;
8769
8770                         pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8771                                 parent->index, i, tp->first_table_num + grp);
8772                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8773                                 rt->rxdma_channel[slot] =
8774                                         rdc_channel_base + this_channel_offset;
8775
8776                                 pr_cont("%d ", rt->rxdma_channel[slot]);
8777
8778                                 if (++this_channel_offset == num_channels)
8779                                         this_channel_offset = 0;
8780                         }
8781                         pr_cont("]\n");
8782                 }
8783
8784                 parent->rdc_default[i] = rdc_channel_base;
8785
8786                 rdc_channel_base += num_channels;
8787                 rdc_group += rdc_groups_per_port;
8788         }
8789 }
8790
8791 static int __devinit fill_phy_probe_info(struct niu *np,
8792                                          struct niu_parent *parent,
8793                                          struct phy_probe_info *info)
8794 {
8795         unsigned long flags;
8796         int port, err;
8797
8798         memset(info, 0, sizeof(*info));
8799
8800         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8801         niu_lock_parent(np, flags);
8802         err = 0;
8803         for (port = 8; port < 32; port++) {
8804                 int dev_id_1, dev_id_2;
8805
8806                 dev_id_1 = mdio_read(np, port,
8807                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8808                 dev_id_2 = mdio_read(np, port,
8809                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8810                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8811                                  PHY_TYPE_PMA_PMD);
8812                 if (err)
8813                         break;
8814                 dev_id_1 = mdio_read(np, port,
8815                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8816                 dev_id_2 = mdio_read(np, port,
8817                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8818                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8819                                  PHY_TYPE_PCS);
8820                 if (err)
8821                         break;
8822                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8823                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8824                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8825                                  PHY_TYPE_MII);
8826                 if (err)
8827                         break;
8828         }
8829         niu_unlock_parent(np, flags);
8830
8831         return err;
8832 }
8833
8834 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8835 {
8836         struct phy_probe_info *info = &parent->phy_probe_info;
8837         int lowest_10g, lowest_1g;
8838         int num_10g, num_1g;
8839         u32 val;
8840         int err;
8841
8842         num_10g = num_1g = 0;
8843
8844         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8845             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8846                 num_10g = 0;
8847                 num_1g = 2;
8848                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8849                 parent->num_ports = 4;
8850                 val = (phy_encode(PORT_TYPE_1G, 0) |
8851                        phy_encode(PORT_TYPE_1G, 1) |
8852                        phy_encode(PORT_TYPE_1G, 2) |
8853                        phy_encode(PORT_TYPE_1G, 3));
8854         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8855                 num_10g = 2;
8856                 num_1g = 0;
8857                 parent->num_ports = 2;
8858                 val = (phy_encode(PORT_TYPE_10G, 0) |
8859                        phy_encode(PORT_TYPE_10G, 1));
8860         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8861                    (parent->plat_type == PLAT_TYPE_NIU)) {
8862                 /* this is the Monza case */
8863                 if (np->flags & NIU_FLAGS_10G) {
8864                         val = (phy_encode(PORT_TYPE_10G, 0) |
8865                                phy_encode(PORT_TYPE_10G, 1));
8866                 } else {
8867                         val = (phy_encode(PORT_TYPE_1G, 0) |
8868                                phy_encode(PORT_TYPE_1G, 1));
8869                 }
8870         } else {
8871                 err = fill_phy_probe_info(np, parent, info);
8872                 if (err)
8873                         return err;
8874
8875                 num_10g = count_10g_ports(info, &lowest_10g);
8876                 num_1g = count_1g_ports(info, &lowest_1g);
8877
8878                 switch ((num_10g << 4) | num_1g) {
8879                 case 0x24:
8880                         if (lowest_1g == 10)
8881                                 parent->plat_type = PLAT_TYPE_VF_P0;
8882                         else if (lowest_1g == 26)
8883                                 parent->plat_type = PLAT_TYPE_VF_P1;
8884                         else
8885                                 goto unknown_vg_1g_port;
8886
8887                         /* fallthru */
8888                 case 0x22:
8889                         val = (phy_encode(PORT_TYPE_10G, 0) |
8890                                phy_encode(PORT_TYPE_10G, 1) |
8891                                phy_encode(PORT_TYPE_1G, 2) |
8892                                phy_encode(PORT_TYPE_1G, 3));
8893                         break;
8894
8895                 case 0x20:
8896                         val = (phy_encode(PORT_TYPE_10G, 0) |
8897                                phy_encode(PORT_TYPE_10G, 1));
8898                         break;
8899
8900                 case 0x10:
8901                         val = phy_encode(PORT_TYPE_10G, np->port);
8902                         break;
8903
8904                 case 0x14:
8905                         if (lowest_1g == 10)
8906                                 parent->plat_type = PLAT_TYPE_VF_P0;
8907                         else if (lowest_1g == 26)
8908                                 parent->plat_type = PLAT_TYPE_VF_P1;
8909                         else
8910                                 goto unknown_vg_1g_port;
8911
8912                         /* fallthru */
8913                 case 0x13:
8914                         if ((lowest_10g & 0x7) == 0)
8915                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8916                                        phy_encode(PORT_TYPE_1G, 1) |
8917                                        phy_encode(PORT_TYPE_1G, 2) |
8918                                        phy_encode(PORT_TYPE_1G, 3));
8919                         else
8920                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8921                                        phy_encode(PORT_TYPE_10G, 1) |
8922                                        phy_encode(PORT_TYPE_1G, 2) |
8923                                        phy_encode(PORT_TYPE_1G, 3));
8924                         break;
8925
8926                 case 0x04:
8927                         if (lowest_1g == 10)
8928                                 parent->plat_type = PLAT_TYPE_VF_P0;
8929                         else if (lowest_1g == 26)
8930                                 parent->plat_type = PLAT_TYPE_VF_P1;
8931                         else
8932                                 goto unknown_vg_1g_port;
8933
8934                         val = (phy_encode(PORT_TYPE_1G, 0) |
8935                                phy_encode(PORT_TYPE_1G, 1) |
8936                                phy_encode(PORT_TYPE_1G, 2) |
8937                                phy_encode(PORT_TYPE_1G, 3));
8938                         break;
8939
8940                 default:
8941                         pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8942                                num_10g, num_1g);
8943                         return -EINVAL;
8944                 }
8945         }
8946
8947         parent->port_phy = val;
8948
8949         if (parent->plat_type == PLAT_TYPE_NIU)
8950                 niu_n2_divide_channels(parent);
8951         else
8952                 niu_divide_channels(parent, num_10g, num_1g);
8953
8954         niu_divide_rdc_groups(parent, num_10g, num_1g);
8955
8956         return 0;
8957
8958 unknown_vg_1g_port:
8959         pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8960         return -EINVAL;
8961 }
8962
8963 static int __devinit niu_probe_ports(struct niu *np)
8964 {
8965         struct niu_parent *parent = np->parent;
8966         int err, i;
8967
8968         netif_printk(np, probe, KERN_DEBUG, np->dev,
8969                      "%s() port_phy[%08x]\n", __func__, parent->port_phy);
8970
8971         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8972                 err = walk_phys(np, parent);
8973                 if (err)
8974                         return err;
8975
8976                 niu_set_ldg_timer_res(np, 2);
8977                 for (i = 0; i <= LDN_MAX; i++)
8978                         niu_ldn_irq_enable(np, i, 0);
8979         }
8980
8981         if (parent->port_phy == PORT_PHY_INVALID)
8982                 return -EINVAL;
8983
8984         return 0;
8985 }
8986
8987 static int __devinit niu_classifier_swstate_init(struct niu *np)
8988 {
8989         struct niu_classifier *cp = &np->clas;
8990
8991         netif_printk(np, probe, KERN_DEBUG, np->dev,
8992                      "%s() num_tcam(%d)\n",
8993                      __func__, np->parent->tcam_num_entries);
8994
8995         cp->tcam_top = (u16) np->port;
8996         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8997         cp->h1_init = 0xffffffff;
8998         cp->h2_init = 0xffff;
8999
9000         return fflp_early_init(np);
9001 }
9002
9003 static void __devinit niu_link_config_init(struct niu *np)
9004 {
9005         struct niu_link_config *lp = &np->link_config;
9006
9007         lp->advertising = (ADVERTISED_10baseT_Half |
9008                            ADVERTISED_10baseT_Full |
9009                            ADVERTISED_100baseT_Half |
9010                            ADVERTISED_100baseT_Full |
9011                            ADVERTISED_1000baseT_Half |
9012                            ADVERTISED_1000baseT_Full |
9013                            ADVERTISED_10000baseT_Full |
9014                            ADVERTISED_Autoneg);
9015         lp->speed = lp->active_speed = SPEED_INVALID;
9016         lp->duplex = DUPLEX_FULL;
9017         lp->active_duplex = DUPLEX_INVALID;
9018         lp->autoneg = 1;
9019 #if 0
9020         lp->loopback_mode = LOOPBACK_MAC;
9021         lp->active_speed = SPEED_10000;
9022         lp->active_duplex = DUPLEX_FULL;
9023 #else
9024         lp->loopback_mode = LOOPBACK_DISABLED;
9025 #endif
9026 }
9027
9028 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9029 {
9030         switch (np->port) {
9031         case 0:
9032                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9033                 np->ipp_off  = 0x00000;
9034                 np->pcs_off  = 0x04000;
9035                 np->xpcs_off = 0x02000;
9036                 break;
9037
9038         case 1:
9039                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9040                 np->ipp_off  = 0x08000;
9041                 np->pcs_off  = 0x0a000;
9042                 np->xpcs_off = 0x08000;
9043                 break;
9044
9045         case 2:
9046                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9047                 np->ipp_off  = 0x04000;
9048                 np->pcs_off  = 0x0e000;
9049                 np->xpcs_off = ~0UL;
9050                 break;
9051
9052         case 3:
9053                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9054                 np->ipp_off  = 0x0c000;
9055                 np->pcs_off  = 0x12000;
9056                 np->xpcs_off = ~0UL;
9057                 break;
9058
9059         default:
9060                 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9061                 return -EINVAL;
9062         }
9063
9064         return 0;
9065 }
9066
9067 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9068 {
9069         struct msix_entry msi_vec[NIU_NUM_LDG];
9070         struct niu_parent *parent = np->parent;
9071         struct pci_dev *pdev = np->pdev;
9072         int i, num_irqs, err;
9073         u8 first_ldg;
9074
9075         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9076         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9077                 ldg_num_map[i] = first_ldg + i;
9078
9079         num_irqs = (parent->rxchan_per_port[np->port] +
9080                     parent->txchan_per_port[np->port] +
9081                     (np->port == 0 ? 3 : 1));
9082         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9083
9084 retry:
9085         for (i = 0; i < num_irqs; i++) {
9086                 msi_vec[i].vector = 0;
9087                 msi_vec[i].entry = i;
9088         }
9089
9090         err = pci_enable_msix(pdev, msi_vec, num_irqs);
9091         if (err < 0) {
9092                 np->flags &= ~NIU_FLAGS_MSIX;
9093                 return;
9094         }
9095         if (err > 0) {
9096                 num_irqs = err;
9097                 goto retry;
9098         }
9099
9100         np->flags |= NIU_FLAGS_MSIX;
9101         for (i = 0; i < num_irqs; i++)
9102                 np->ldg[i].irq = msi_vec[i].vector;
9103         np->num_ldg = num_irqs;
9104 }
9105
9106 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9107 {
9108 #ifdef CONFIG_SPARC64
9109         struct of_device *op = np->op;
9110         const u32 *int_prop;
9111         int i;
9112
9113         int_prop = of_get_property(op->node, "interrupts", NULL);
9114         if (!int_prop)
9115                 return -ENODEV;
9116
9117         for (i = 0; i < op->num_irqs; i++) {
9118                 ldg_num_map[i] = int_prop[i];
9119                 np->ldg[i].irq = op->irqs[i];
9120         }
9121
9122         np->num_ldg = op->num_irqs;
9123
9124         return 0;
9125 #else
9126         return -EINVAL;
9127 #endif
9128 }
9129
9130 static int __devinit niu_ldg_init(struct niu *np)
9131 {
9132         struct niu_parent *parent = np->parent;
9133         u8 ldg_num_map[NIU_NUM_LDG];
9134         int first_chan, num_chan;
9135         int i, err, ldg_rotor;
9136         u8 port;
9137
9138         np->num_ldg = 1;
9139         np->ldg[0].irq = np->dev->irq;
9140         if (parent->plat_type == PLAT_TYPE_NIU) {
9141                 err = niu_n2_irq_init(np, ldg_num_map);
9142                 if (err)
9143                         return err;
9144         } else
9145                 niu_try_msix(np, ldg_num_map);
9146
9147         port = np->port;
9148         for (i = 0; i < np->num_ldg; i++) {
9149                 struct niu_ldg *lp = &np->ldg[i];
9150
9151                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9152
9153                 lp->np = np;
9154                 lp->ldg_num = ldg_num_map[i];
9155                 lp->timer = 2; /* XXX */
9156
9157                 /* On N2 NIU the firmware has setup the SID mappings so they go
9158                  * to the correct values that will route the LDG to the proper
9159                  * interrupt in the NCU interrupt table.
9160                  */
9161                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9162                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9163                         if (err)
9164                                 return err;
9165                 }
9166         }
9167
9168         /* We adopt the LDG assignment ordering used by the N2 NIU
9169          * 'interrupt' properties because that simplifies a lot of
9170          * things.  This ordering is:
9171          *
9172          *      MAC
9173          *      MIF     (if port zero)
9174          *      SYSERR  (if port zero)
9175          *      RX channels
9176          *      TX channels
9177          */
9178
9179         ldg_rotor = 0;
9180
9181         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9182                                   LDN_MAC(port));
9183         if (err)
9184                 return err;
9185
9186         ldg_rotor++;
9187         if (ldg_rotor == np->num_ldg)
9188                 ldg_rotor = 0;
9189
9190         if (port == 0) {
9191                 err = niu_ldg_assign_ldn(np, parent,
9192                                          ldg_num_map[ldg_rotor],
9193                                          LDN_MIF);
9194                 if (err)
9195                         return err;
9196
9197                 ldg_rotor++;
9198                 if (ldg_rotor == np->num_ldg)
9199                         ldg_rotor = 0;
9200
9201                 err = niu_ldg_assign_ldn(np, parent,
9202                                          ldg_num_map[ldg_rotor],
9203                                          LDN_DEVICE_ERROR);
9204                 if (err)
9205                         return err;
9206
9207                 ldg_rotor++;
9208                 if (ldg_rotor == np->num_ldg)
9209                         ldg_rotor = 0;
9210
9211         }
9212
9213         first_chan = 0;
9214         for (i = 0; i < port; i++)
9215                 first_chan += parent->rxchan_per_port[port];
9216         num_chan = parent->rxchan_per_port[port];
9217
9218         for (i = first_chan; i < (first_chan + num_chan); i++) {
9219                 err = niu_ldg_assign_ldn(np, parent,
9220                                          ldg_num_map[ldg_rotor],
9221                                          LDN_RXDMA(i));
9222                 if (err)
9223                         return err;
9224                 ldg_rotor++;
9225                 if (ldg_rotor == np->num_ldg)
9226                         ldg_rotor = 0;
9227         }
9228
9229         first_chan = 0;
9230         for (i = 0; i < port; i++)
9231                 first_chan += parent->txchan_per_port[port];
9232         num_chan = parent->txchan_per_port[port];
9233         for (i = first_chan; i < (first_chan + num_chan); i++) {
9234                 err = niu_ldg_assign_ldn(np, parent,
9235                                          ldg_num_map[ldg_rotor],
9236                                          LDN_TXDMA(i));
9237                 if (err)
9238                         return err;
9239                 ldg_rotor++;
9240                 if (ldg_rotor == np->num_ldg)
9241                         ldg_rotor = 0;
9242         }
9243
9244         return 0;
9245 }
9246
9247 static void __devexit niu_ldg_free(struct niu *np)
9248 {
9249         if (np->flags & NIU_FLAGS_MSIX)
9250                 pci_disable_msix(np->pdev);
9251 }
9252
9253 static int __devinit niu_get_of_props(struct niu *np)
9254 {
9255 #ifdef CONFIG_SPARC64
9256         struct net_device *dev = np->dev;
9257         struct device_node *dp;
9258         const char *phy_type;
9259         const u8 *mac_addr;
9260         const char *model;
9261         int prop_len;
9262
9263         if (np->parent->plat_type == PLAT_TYPE_NIU)
9264                 dp = np->op->node;
9265         else
9266                 dp = pci_device_to_OF_node(np->pdev);
9267
9268         phy_type = of_get_property(dp, "phy-type", &prop_len);
9269         if (!phy_type) {
9270                 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9271                            dp->full_name);
9272                 return -EINVAL;
9273         }
9274
9275         if (!strcmp(phy_type, "none"))
9276                 return -ENODEV;
9277
9278         strcpy(np->vpd.phy_type, phy_type);
9279
9280         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9281                 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9282                            dp->full_name, np->vpd.phy_type);
9283                 return -EINVAL;
9284         }
9285
9286         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9287         if (!mac_addr) {
9288                 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9289                            dp->full_name);
9290                 return -EINVAL;
9291         }
9292         if (prop_len != dev->addr_len) {
9293                 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9294                            dp->full_name, prop_len);
9295         }
9296         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9297         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9298                 netdev_err(dev, "%s: OF MAC address is invalid\n",
9299                            dp->full_name);
9300                 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9301                 return -EINVAL;
9302         }
9303
9304         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9305
9306         model = of_get_property(dp, "model", &prop_len);
9307
9308         if (model)
9309                 strcpy(np->vpd.model, model);
9310
9311         if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9312                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9313                         NIU_FLAGS_HOTPLUG_PHY);
9314         }
9315
9316         return 0;
9317 #else
9318         return -EINVAL;
9319 #endif
9320 }
9321
9322 static int __devinit niu_get_invariants(struct niu *np)
9323 {
9324         int err, have_props;
9325         u32 offset;
9326
9327         err = niu_get_of_props(np);
9328         if (err == -ENODEV)
9329                 return err;
9330
9331         have_props = !err;
9332
9333         err = niu_init_mac_ipp_pcs_base(np);
9334         if (err)
9335                 return err;
9336
9337         if (have_props) {
9338                 err = niu_get_and_validate_port(np);
9339                 if (err)
9340                         return err;
9341
9342         } else  {
9343                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9344                         return -EINVAL;
9345
9346                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9347                 offset = niu_pci_vpd_offset(np);
9348                 netif_printk(np, probe, KERN_DEBUG, np->dev,
9349                              "%s() VPD offset [%08x]\n", __func__, offset);
9350                 if (offset)
9351                         niu_pci_vpd_fetch(np, offset);
9352                 nw64(ESPC_PIO_EN, 0);
9353
9354                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9355                         niu_pci_vpd_validate(np);
9356                         err = niu_get_and_validate_port(np);
9357                         if (err)
9358                                 return err;
9359                 }
9360
9361                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9362                         err = niu_get_and_validate_port(np);
9363                         if (err)
9364                                 return err;
9365                         err = niu_pci_probe_sprom(np);
9366                         if (err)
9367                                 return err;
9368                 }
9369         }
9370
9371         err = niu_probe_ports(np);
9372         if (err)
9373                 return err;
9374
9375         niu_ldg_init(np);
9376
9377         niu_classifier_swstate_init(np);
9378         niu_link_config_init(np);
9379
9380         err = niu_determine_phy_disposition(np);
9381         if (!err)
9382                 err = niu_init_link(np);
9383
9384         return err;
9385 }
9386
9387 static LIST_HEAD(niu_parent_list);
9388 static DEFINE_MUTEX(niu_parent_lock);
9389 static int niu_parent_index;
9390
9391 static ssize_t show_port_phy(struct device *dev,
9392                              struct device_attribute *attr, char *buf)
9393 {
9394         struct platform_device *plat_dev = to_platform_device(dev);
9395         struct niu_parent *p = plat_dev->dev.platform_data;
9396         u32 port_phy = p->port_phy;
9397         char *orig_buf = buf;
9398         int i;
9399
9400         if (port_phy == PORT_PHY_UNKNOWN ||
9401             port_phy == PORT_PHY_INVALID)
9402                 return 0;
9403
9404         for (i = 0; i < p->num_ports; i++) {
9405                 const char *type_str;
9406                 int type;
9407
9408                 type = phy_decode(port_phy, i);
9409                 if (type == PORT_TYPE_10G)
9410                         type_str = "10G";
9411                 else
9412                         type_str = "1G";
9413                 buf += sprintf(buf,
9414                                (i == 0) ? "%s" : " %s",
9415                                type_str);
9416         }
9417         buf += sprintf(buf, "\n");
9418         return buf - orig_buf;
9419 }
9420
9421 static ssize_t show_plat_type(struct device *dev,
9422                               struct device_attribute *attr, char *buf)
9423 {
9424         struct platform_device *plat_dev = to_platform_device(dev);
9425         struct niu_parent *p = plat_dev->dev.platform_data;
9426         const char *type_str;
9427
9428         switch (p->plat_type) {
9429         case PLAT_TYPE_ATLAS:
9430                 type_str = "atlas";
9431                 break;
9432         case PLAT_TYPE_NIU:
9433                 type_str = "niu";
9434                 break;
9435         case PLAT_TYPE_VF_P0:
9436                 type_str = "vf_p0";
9437                 break;
9438         case PLAT_TYPE_VF_P1:
9439                 type_str = "vf_p1";
9440                 break;
9441         default:
9442                 type_str = "unknown";
9443                 break;
9444         }
9445
9446         return sprintf(buf, "%s\n", type_str);
9447 }
9448
9449 static ssize_t __show_chan_per_port(struct device *dev,
9450                                     struct device_attribute *attr, char *buf,
9451                                     int rx)
9452 {
9453         struct platform_device *plat_dev = to_platform_device(dev);
9454         struct niu_parent *p = plat_dev->dev.platform_data;
9455         char *orig_buf = buf;
9456         u8 *arr;
9457         int i;
9458
9459         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9460
9461         for (i = 0; i < p->num_ports; i++) {
9462                 buf += sprintf(buf,
9463                                (i == 0) ? "%d" : " %d",
9464                                arr[i]);
9465         }
9466         buf += sprintf(buf, "\n");
9467
9468         return buf - orig_buf;
9469 }
9470
9471 static ssize_t show_rxchan_per_port(struct device *dev,
9472                                     struct device_attribute *attr, char *buf)
9473 {
9474         return __show_chan_per_port(dev, attr, buf, 1);
9475 }
9476
9477 static ssize_t show_txchan_per_port(struct device *dev,
9478                                     struct device_attribute *attr, char *buf)
9479 {
9480         return __show_chan_per_port(dev, attr, buf, 1);
9481 }
9482
9483 static ssize_t show_num_ports(struct device *dev,
9484                               struct device_attribute *attr, char *buf)
9485 {
9486         struct platform_device *plat_dev = to_platform_device(dev);
9487         struct niu_parent *p = plat_dev->dev.platform_data;
9488
9489         return sprintf(buf, "%d\n", p->num_ports);
9490 }
9491
9492 static struct device_attribute niu_parent_attributes[] = {
9493         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9494         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9495         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9496         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9497         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9498         {}
9499 };
9500
9501 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9502                                                     union niu_parent_id *id,
9503                                                     u8 ptype)
9504 {
9505         struct platform_device *plat_dev;
9506         struct niu_parent *p;
9507         int i;
9508
9509         netif_printk(np, probe, KERN_DEBUG, np->dev,
9510                      "%s() Creating new parent\n", __func__);
9511
9512         plat_dev = platform_device_register_simple("niu", niu_parent_index,
9513                                                    NULL, 0);
9514         if (IS_ERR(plat_dev))
9515                 return NULL;
9516
9517         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9518                 int err = device_create_file(&plat_dev->dev,
9519                                              &niu_parent_attributes[i]);
9520                 if (err)
9521                         goto fail_unregister;
9522         }
9523
9524         p = kzalloc(sizeof(*p), GFP_KERNEL);
9525         if (!p)
9526                 goto fail_unregister;
9527
9528         p->index = niu_parent_index++;
9529
9530         plat_dev->dev.platform_data = p;
9531         p->plat_dev = plat_dev;
9532
9533         memcpy(&p->id, id, sizeof(*id));
9534         p->plat_type = ptype;
9535         INIT_LIST_HEAD(&p->list);
9536         atomic_set(&p->refcnt, 0);
9537         list_add(&p->list, &niu_parent_list);
9538         spin_lock_init(&p->lock);
9539
9540         p->rxdma_clock_divider = 7500;
9541
9542         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9543         if (p->plat_type == PLAT_TYPE_NIU)
9544                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9545
9546         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9547                 int index = i - CLASS_CODE_USER_PROG1;
9548
9549                 p->tcam_key[index] = TCAM_KEY_TSEL;
9550                 p->flow_key[index] = (FLOW_KEY_IPSA |
9551                                       FLOW_KEY_IPDA |
9552                                       FLOW_KEY_PROTO |
9553                                       (FLOW_KEY_L4_BYTE12 <<
9554                                        FLOW_KEY_L4_0_SHIFT) |
9555                                       (FLOW_KEY_L4_BYTE12 <<
9556                                        FLOW_KEY_L4_1_SHIFT));
9557         }
9558
9559         for (i = 0; i < LDN_MAX + 1; i++)
9560                 p->ldg_map[i] = LDG_INVALID;
9561
9562         return p;
9563
9564 fail_unregister:
9565         platform_device_unregister(plat_dev);
9566         return NULL;
9567 }
9568
9569 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9570                                                     union niu_parent_id *id,
9571                                                     u8 ptype)
9572 {
9573         struct niu_parent *p, *tmp;
9574         int port = np->port;
9575
9576         netif_printk(np, probe, KERN_DEBUG, np->dev,
9577                      "%s() platform_type[%u] port[%u]\n",
9578                      __func__, ptype, port);
9579
9580         mutex_lock(&niu_parent_lock);
9581         p = NULL;
9582         list_for_each_entry(tmp, &niu_parent_list, list) {
9583                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9584                         p = tmp;
9585                         break;
9586                 }
9587         }
9588         if (!p)
9589                 p = niu_new_parent(np, id, ptype);
9590
9591         if (p) {
9592                 char port_name[6];
9593                 int err;
9594
9595                 sprintf(port_name, "port%d", port);
9596                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9597                                         &np->device->kobj,
9598                                         port_name);
9599                 if (!err) {
9600                         p->ports[port] = np;
9601                         atomic_inc(&p->refcnt);
9602                 }
9603         }
9604         mutex_unlock(&niu_parent_lock);
9605
9606         return p;
9607 }
9608
9609 static void niu_put_parent(struct niu *np)
9610 {
9611         struct niu_parent *p = np->parent;
9612         u8 port = np->port;
9613         char port_name[6];
9614
9615         BUG_ON(!p || p->ports[port] != np);
9616
9617         netif_printk(np, probe, KERN_DEBUG, np->dev,
9618                      "%s() port[%u]\n", __func__, port);
9619
9620         sprintf(port_name, "port%d", port);
9621
9622         mutex_lock(&niu_parent_lock);
9623
9624         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9625
9626         p->ports[port] = NULL;
9627         np->parent = NULL;
9628
9629         if (atomic_dec_and_test(&p->refcnt)) {
9630                 list_del(&p->list);
9631                 platform_device_unregister(p->plat_dev);
9632         }
9633
9634         mutex_unlock(&niu_parent_lock);
9635 }
9636
9637 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9638                                     u64 *handle, gfp_t flag)
9639 {
9640         dma_addr_t dh;
9641         void *ret;
9642
9643         ret = dma_alloc_coherent(dev, size, &dh, flag);
9644         if (ret)
9645                 *handle = dh;
9646         return ret;
9647 }
9648
9649 static void niu_pci_free_coherent(struct device *dev, size_t size,
9650                                   void *cpu_addr, u64 handle)
9651 {
9652         dma_free_coherent(dev, size, cpu_addr, handle);
9653 }
9654
9655 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9656                             unsigned long offset, size_t size,
9657                             enum dma_data_direction direction)
9658 {
9659         return dma_map_page(dev, page, offset, size, direction);
9660 }
9661
9662 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9663                                size_t size, enum dma_data_direction direction)
9664 {
9665         dma_unmap_page(dev, dma_address, size, direction);
9666 }
9667
9668 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9669                               size_t size,
9670                               enum dma_data_direction direction)
9671 {
9672         return dma_map_single(dev, cpu_addr, size, direction);
9673 }
9674
9675 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9676                                  size_t size,
9677                                  enum dma_data_direction direction)
9678 {
9679         dma_unmap_single(dev, dma_address, size, direction);
9680 }
9681
9682 static const struct niu_ops niu_pci_ops = {
9683         .alloc_coherent = niu_pci_alloc_coherent,
9684         .free_coherent  = niu_pci_free_coherent,
9685         .map_page       = niu_pci_map_page,
9686         .unmap_page     = niu_pci_unmap_page,
9687         .map_single     = niu_pci_map_single,
9688         .unmap_single   = niu_pci_unmap_single,
9689 };
9690
9691 static void __devinit niu_driver_version(void)
9692 {
9693         static int niu_version_printed;
9694
9695         if (niu_version_printed++ == 0)
9696                 pr_info("%s", version);
9697 }
9698
9699 static struct net_device * __devinit niu_alloc_and_init(
9700         struct device *gen_dev, struct pci_dev *pdev,
9701         struct of_device *op, const struct niu_ops *ops,
9702         u8 port)
9703 {
9704         struct net_device *dev;
9705         struct niu *np;
9706
9707         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9708         if (!dev) {
9709                 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9710                 return NULL;
9711         }
9712
9713         SET_NETDEV_DEV(dev, gen_dev);
9714
9715         np = netdev_priv(dev);
9716         np->dev = dev;
9717         np->pdev = pdev;
9718         np->op = op;
9719         np->device = gen_dev;
9720         np->ops = ops;
9721
9722         np->msg_enable = niu_debug;
9723
9724         spin_lock_init(&np->lock);
9725         INIT_WORK(&np->reset_task, niu_reset_task);
9726
9727         np->port = port;
9728
9729         return dev;
9730 }
9731
9732 static const struct net_device_ops niu_netdev_ops = {
9733         .ndo_open               = niu_open,
9734         .ndo_stop               = niu_close,
9735         .ndo_start_xmit         = niu_start_xmit,
9736         .ndo_get_stats          = niu_get_stats,
9737         .ndo_set_multicast_list = niu_set_rx_mode,
9738         .ndo_validate_addr      = eth_validate_addr,
9739         .ndo_set_mac_address    = niu_set_mac_addr,
9740         .ndo_do_ioctl           = niu_ioctl,
9741         .ndo_tx_timeout         = niu_tx_timeout,
9742         .ndo_change_mtu         = niu_change_mtu,
9743 };
9744
9745 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9746 {
9747         dev->netdev_ops = &niu_netdev_ops;
9748         dev->ethtool_ops = &niu_ethtool_ops;
9749         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9750 }
9751
9752 static void __devinit niu_device_announce(struct niu *np)
9753 {
9754         struct net_device *dev = np->dev;
9755
9756         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9757
9758         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9759                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9760                                 dev->name,
9761                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9762                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9763                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9764                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9765                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9766                                 np->vpd.phy_type);
9767         } else {
9768                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9769                                 dev->name,
9770                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9771                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9772                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9773                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9774                                   "COPPER")),
9775                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9776                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9777                                 np->vpd.phy_type);
9778         }
9779 }
9780
9781 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9782                                       const struct pci_device_id *ent)
9783 {
9784         union niu_parent_id parent_id;
9785         struct net_device *dev;
9786         struct niu *np;
9787         int err, pos;
9788         u64 dma_mask;
9789         u16 val16;
9790
9791         niu_driver_version();
9792
9793         err = pci_enable_device(pdev);
9794         if (err) {
9795                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9796                 return err;
9797         }
9798
9799         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9800             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9801                 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9802                 err = -ENODEV;
9803                 goto err_out_disable_pdev;
9804         }
9805
9806         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9807         if (err) {
9808                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9809                 goto err_out_disable_pdev;
9810         }
9811
9812         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9813         if (pos <= 0) {
9814                 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9815                 goto err_out_free_res;
9816         }
9817
9818         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9819                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9820         if (!dev) {
9821                 err = -ENOMEM;
9822                 goto err_out_free_res;
9823         }
9824         np = netdev_priv(dev);
9825
9826         memset(&parent_id, 0, sizeof(parent_id));
9827         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9828         parent_id.pci.bus = pdev->bus->number;
9829         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9830
9831         np->parent = niu_get_parent(np, &parent_id,
9832                                     PLAT_TYPE_ATLAS);
9833         if (!np->parent) {
9834                 err = -ENOMEM;
9835                 goto err_out_free_dev;
9836         }
9837
9838         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9839         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9840         val16 |= (PCI_EXP_DEVCTL_CERE |
9841                   PCI_EXP_DEVCTL_NFERE |
9842                   PCI_EXP_DEVCTL_FERE |
9843                   PCI_EXP_DEVCTL_URRE |
9844                   PCI_EXP_DEVCTL_RELAX_EN);
9845         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9846
9847         dma_mask = DMA_BIT_MASK(44);
9848         err = pci_set_dma_mask(pdev, dma_mask);
9849         if (!err) {
9850                 dev->features |= NETIF_F_HIGHDMA;
9851                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9852                 if (err) {
9853                         dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9854                         goto err_out_release_parent;
9855                 }
9856         }
9857         if (err || dma_mask == DMA_BIT_MASK(32)) {
9858                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9859                 if (err) {
9860                         dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9861                         goto err_out_release_parent;
9862                 }
9863         }
9864
9865         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9866
9867         np->regs = pci_ioremap_bar(pdev, 0);
9868         if (!np->regs) {
9869                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9870                 err = -ENOMEM;
9871                 goto err_out_release_parent;
9872         }
9873
9874         pci_set_master(pdev);
9875         pci_save_state(pdev);
9876
9877         dev->irq = pdev->irq;
9878
9879         niu_assign_netdev_ops(dev);
9880
9881         err = niu_get_invariants(np);
9882         if (err) {
9883                 if (err != -ENODEV)
9884                         dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9885                 goto err_out_iounmap;
9886         }
9887
9888         err = register_netdev(dev);
9889         if (err) {
9890                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9891                 goto err_out_iounmap;
9892         }
9893
9894         pci_set_drvdata(pdev, dev);
9895
9896         niu_device_announce(np);
9897
9898         return 0;
9899
9900 err_out_iounmap:
9901         if (np->regs) {
9902                 iounmap(np->regs);
9903                 np->regs = NULL;
9904         }
9905
9906 err_out_release_parent:
9907         niu_put_parent(np);
9908
9909 err_out_free_dev:
9910         free_netdev(dev);
9911
9912 err_out_free_res:
9913         pci_release_regions(pdev);
9914
9915 err_out_disable_pdev:
9916         pci_disable_device(pdev);
9917         pci_set_drvdata(pdev, NULL);
9918
9919         return err;
9920 }
9921
9922 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9923 {
9924         struct net_device *dev = pci_get_drvdata(pdev);
9925
9926         if (dev) {
9927                 struct niu *np = netdev_priv(dev);
9928
9929                 unregister_netdev(dev);
9930                 if (np->regs) {
9931                         iounmap(np->regs);
9932                         np->regs = NULL;
9933                 }
9934
9935                 niu_ldg_free(np);
9936
9937                 niu_put_parent(np);
9938
9939                 free_netdev(dev);
9940                 pci_release_regions(pdev);
9941                 pci_disable_device(pdev);
9942                 pci_set_drvdata(pdev, NULL);
9943         }
9944 }
9945
9946 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9947 {
9948         struct net_device *dev = pci_get_drvdata(pdev);
9949         struct niu *np = netdev_priv(dev);
9950         unsigned long flags;
9951
9952         if (!netif_running(dev))
9953                 return 0;
9954
9955         flush_scheduled_work();
9956         niu_netif_stop(np);
9957
9958         del_timer_sync(&np->timer);
9959
9960         spin_lock_irqsave(&np->lock, flags);
9961         niu_enable_interrupts(np, 0);
9962         spin_unlock_irqrestore(&np->lock, flags);
9963
9964         netif_device_detach(dev);
9965
9966         spin_lock_irqsave(&np->lock, flags);
9967         niu_stop_hw(np);
9968         spin_unlock_irqrestore(&np->lock, flags);
9969
9970         pci_save_state(pdev);
9971
9972         return 0;
9973 }
9974
9975 static int niu_resume(struct pci_dev *pdev)
9976 {
9977         struct net_device *dev = pci_get_drvdata(pdev);
9978         struct niu *np = netdev_priv(dev);
9979         unsigned long flags;
9980         int err;
9981
9982         if (!netif_running(dev))
9983                 return 0;
9984
9985         pci_restore_state(pdev);
9986
9987         netif_device_attach(dev);
9988
9989         spin_lock_irqsave(&np->lock, flags);
9990
9991         err = niu_init_hw(np);
9992         if (!err) {
9993                 np->timer.expires = jiffies + HZ;
9994                 add_timer(&np->timer);
9995                 niu_netif_start(np);
9996         }
9997
9998         spin_unlock_irqrestore(&np->lock, flags);
9999
10000         return err;
10001 }
10002
10003 static struct pci_driver niu_pci_driver = {
10004         .name           = DRV_MODULE_NAME,
10005         .id_table       = niu_pci_tbl,
10006         .probe          = niu_pci_init_one,
10007         .remove         = __devexit_p(niu_pci_remove_one),
10008         .suspend        = niu_suspend,
10009         .resume         = niu_resume,
10010 };
10011
10012 #ifdef CONFIG_SPARC64
10013 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10014                                      u64 *dma_addr, gfp_t flag)
10015 {
10016         unsigned long order = get_order(size);
10017         unsigned long page = __get_free_pages(flag, order);
10018
10019         if (page == 0UL)
10020                 return NULL;
10021         memset((char *)page, 0, PAGE_SIZE << order);
10022         *dma_addr = __pa(page);
10023
10024         return (void *) page;
10025 }
10026
10027 static void niu_phys_free_coherent(struct device *dev, size_t size,
10028                                    void *cpu_addr, u64 handle)
10029 {
10030         unsigned long order = get_order(size);
10031
10032         free_pages((unsigned long) cpu_addr, order);
10033 }
10034
10035 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10036                              unsigned long offset, size_t size,
10037                              enum dma_data_direction direction)
10038 {
10039         return page_to_phys(page) + offset;
10040 }
10041
10042 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10043                                 size_t size, enum dma_data_direction direction)
10044 {
10045         /* Nothing to do.  */
10046 }
10047
10048 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10049                                size_t size,
10050                                enum dma_data_direction direction)
10051 {
10052         return __pa(cpu_addr);
10053 }
10054
10055 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10056                                   size_t size,
10057                                   enum dma_data_direction direction)
10058 {
10059         /* Nothing to do.  */
10060 }
10061
10062 static const struct niu_ops niu_phys_ops = {
10063         .alloc_coherent = niu_phys_alloc_coherent,
10064         .free_coherent  = niu_phys_free_coherent,
10065         .map_page       = niu_phys_map_page,
10066         .unmap_page     = niu_phys_unmap_page,
10067         .map_single     = niu_phys_map_single,
10068         .unmap_single   = niu_phys_unmap_single,
10069 };
10070
10071 static int __devinit niu_of_probe(struct of_device *op,
10072                                   const struct of_device_id *match)
10073 {
10074         union niu_parent_id parent_id;
10075         struct net_device *dev;
10076         struct niu *np;
10077         const u32 *reg;
10078         int err;
10079
10080         niu_driver_version();
10081
10082         reg = of_get_property(op->node, "reg", NULL);
10083         if (!reg) {
10084                 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10085                         op->node->full_name);
10086                 return -ENODEV;
10087         }
10088
10089         dev = niu_alloc_and_init(&op->dev, NULL, op,
10090                                  &niu_phys_ops, reg[0] & 0x1);
10091         if (!dev) {
10092                 err = -ENOMEM;
10093                 goto err_out;
10094         }
10095         np = netdev_priv(dev);
10096
10097         memset(&parent_id, 0, sizeof(parent_id));
10098         parent_id.of = of_get_parent(op->node);
10099
10100         np->parent = niu_get_parent(np, &parent_id,
10101                                     PLAT_TYPE_NIU);
10102         if (!np->parent) {
10103                 err = -ENOMEM;
10104                 goto err_out_free_dev;
10105         }
10106
10107         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10108
10109         np->regs = of_ioremap(&op->resource[1], 0,
10110                               resource_size(&op->resource[1]),
10111                               "niu regs");
10112         if (!np->regs) {
10113                 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10114                 err = -ENOMEM;
10115                 goto err_out_release_parent;
10116         }
10117
10118         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10119                                     resource_size(&op->resource[2]),
10120                                     "niu vregs-1");
10121         if (!np->vir_regs_1) {
10122                 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10123                 err = -ENOMEM;
10124                 goto err_out_iounmap;
10125         }
10126
10127         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10128                                     resource_size(&op->resource[3]),
10129                                     "niu vregs-2");
10130         if (!np->vir_regs_2) {
10131                 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10132                 err = -ENOMEM;
10133                 goto err_out_iounmap;
10134         }
10135
10136         niu_assign_netdev_ops(dev);
10137
10138         err = niu_get_invariants(np);
10139         if (err) {
10140                 if (err != -ENODEV)
10141                         dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10142                 goto err_out_iounmap;
10143         }
10144
10145         err = register_netdev(dev);
10146         if (err) {
10147                 dev_err(&op->dev, "Cannot register net device, aborting\n");
10148                 goto err_out_iounmap;
10149         }
10150
10151         dev_set_drvdata(&op->dev, dev);
10152
10153         niu_device_announce(np);
10154
10155         return 0;
10156
10157 err_out_iounmap:
10158         if (np->vir_regs_1) {
10159                 of_iounmap(&op->resource[2], np->vir_regs_1,
10160                            resource_size(&op->resource[2]));
10161                 np->vir_regs_1 = NULL;
10162         }
10163
10164         if (np->vir_regs_2) {
10165                 of_iounmap(&op->resource[3], np->vir_regs_2,
10166                            resource_size(&op->resource[3]));
10167                 np->vir_regs_2 = NULL;
10168         }
10169
10170         if (np->regs) {
10171                 of_iounmap(&op->resource[1], np->regs,
10172                            resource_size(&op->resource[1]));
10173                 np->regs = NULL;
10174         }
10175
10176 err_out_release_parent:
10177         niu_put_parent(np);
10178
10179 err_out_free_dev:
10180         free_netdev(dev);
10181
10182 err_out:
10183         return err;
10184 }
10185
10186 static int __devexit niu_of_remove(struct of_device *op)
10187 {
10188         struct net_device *dev = dev_get_drvdata(&op->dev);
10189
10190         if (dev) {
10191                 struct niu *np = netdev_priv(dev);
10192
10193                 unregister_netdev(dev);
10194
10195                 if (np->vir_regs_1) {
10196                         of_iounmap(&op->resource[2], np->vir_regs_1,
10197                                    resource_size(&op->resource[2]));
10198                         np->vir_regs_1 = NULL;
10199                 }
10200
10201                 if (np->vir_regs_2) {
10202                         of_iounmap(&op->resource[3], np->vir_regs_2,
10203                                    resource_size(&op->resource[3]));
10204                         np->vir_regs_2 = NULL;
10205                 }
10206
10207                 if (np->regs) {
10208                         of_iounmap(&op->resource[1], np->regs,
10209                                    resource_size(&op->resource[1]));
10210                         np->regs = NULL;
10211                 }
10212
10213                 niu_ldg_free(np);
10214
10215                 niu_put_parent(np);
10216
10217                 free_netdev(dev);
10218                 dev_set_drvdata(&op->dev, NULL);
10219         }
10220         return 0;
10221 }
10222
10223 static const struct of_device_id niu_match[] = {
10224         {
10225                 .name = "network",
10226                 .compatible = "SUNW,niusl",
10227         },
10228         {},
10229 };
10230 MODULE_DEVICE_TABLE(of, niu_match);
10231
10232 static struct of_platform_driver niu_of_driver = {
10233         .name           = "niu",
10234         .match_table    = niu_match,
10235         .probe          = niu_of_probe,
10236         .remove         = __devexit_p(niu_of_remove),
10237 };
10238
10239 #endif /* CONFIG_SPARC64 */
10240
10241 static int __init niu_init(void)
10242 {
10243         int err = 0;
10244
10245         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10246
10247         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10248
10249 #ifdef CONFIG_SPARC64
10250         err = of_register_driver(&niu_of_driver, &of_bus_type);
10251 #endif
10252
10253         if (!err) {
10254                 err = pci_register_driver(&niu_pci_driver);
10255 #ifdef CONFIG_SPARC64
10256                 if (err)
10257                         of_unregister_driver(&niu_of_driver);
10258 #endif
10259         }
10260
10261         return err;
10262 }
10263
10264 static void __exit niu_exit(void)
10265 {
10266         pci_unregister_driver(&niu_pci_driver);
10267 #ifdef CONFIG_SPARC64
10268         of_unregister_driver(&niu_of_driver);
10269 #endif
10270 }
10271
10272 module_init(niu_init);
10273 module_exit(niu_exit);