SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "1.0"
  37 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  55 }
  56
  57 static void writeq(u64 val, void __iomem *reg)
  58 {
  59         writel(val & 0xffffffff, reg);
  60         writel(val >> 32, reg + 0x4UL);
  61 }
  62 #endif
  63
  64 static struct pci_device_id niu_pci_tbl[] = {
  65         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  66         {}
  67 };
  68
  69 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  70
  71 #define NIU_TX_TIMEOUT                  (5 * HZ)
  72
  73 #define nr64(reg)               readq(np->regs + (reg))
  74 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  75
  76 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  77 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  78
  79 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  80 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  81
  82 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  83 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  84
  85 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  86 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  87
  88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  89
  90 static int niu_debug;
  91 static int debug = -1;
  92 module_param(debug, int, 0);
  93 MODULE_PARM_DESC(debug, "NIU debug level");
  94
  95 #define niudbg(TYPE, f, a...) \
  96 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  97                 printk(KERN_DEBUG PFX f, ## a); \
  98 } while (0)
  99
 100 #define niuinfo(TYPE, f, a...) \
 101 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 102                 printk(KERN_INFO PFX f, ## a); \
 103 } while (0)
 104
 105 #define niuwarn(TYPE, f, a...) \
 106 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 107                 printk(KERN_WARNING PFX f, ## a); \
 108 } while (0)
 109
 110 #define niu_lock_parent(np, flags) \
 111         spin_lock_irqsave(&np->parent->lock, flags)
 112 #define niu_unlock_parent(np, flags) \
 113         spin_unlock_irqrestore(&np->parent->lock, flags)
 114
 115 static int serdes_init_10g_serdes(struct niu *np);
 116
 117 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 118                                      u64 bits, int limit, int delay)
 119 {
 120         while (--limit >= 0) {
 121                 u64 val = nr64_mac(reg);
 122
 123                 if (!(val & bits))
 124                         break;
 125                 udelay(delay);
 126         }
 127         if (limit < 0)
 128                 return -ENODEV;
 129         return 0;
 130 }
 131
 132 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 133                                         u64 bits, int limit, int delay,
 134                                         const char *reg_name)
 135 {
 136         int err;
 137
 138         nw64_mac(reg, bits);
 139         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 140         if (err)
 141                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 142                         "would not clear, val[%llx]\n",
 143                         np->dev->name, (unsigned long long) bits, reg_name,
 144                         (unsigned long long) nr64_mac(reg));
 145         return err;
 146 }
 147
 148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 149 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 150         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 151 })
 152
 153 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 154                                      u64 bits, int limit, int delay)
 155 {
 156         while (--limit >= 0) {
 157                 u64 val = nr64_ipp(reg);
 158
 159                 if (!(val & bits))
 160                         break;
 161                 udelay(delay);
 162         }
 163         if (limit < 0)
 164                 return -ENODEV;
 165         return 0;
 166 }
 167
 168 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 169                                         u64 bits, int limit, int delay,
 170                                         const char *reg_name)
 171 {
 172         int err;
 173         u64 val;
 174
 175         val = nr64_ipp(reg);
 176         val |= bits;
 177         nw64_ipp(reg, val);
 178
 179         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 180         if (err)
 181                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 182                         "would not clear, val[%llx]\n",
 183                         np->dev->name, (unsigned long long) bits, reg_name,
 184                         (unsigned long long) nr64_ipp(reg));
 185         return err;
 186 }
 187
 188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 189 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 190         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 191 })
 192
 193 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 194                                  u64 bits, int limit, int delay)
 195 {
 196         while (--limit >= 0) {
 197                 u64 val = nr64(reg);
 198
 199                 if (!(val & bits))
 200                         break;
 201                 udelay(delay);
 202         }
 203         if (limit < 0)
 204                 return -ENODEV;
 205         return 0;
 206 }
 207
 208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 209 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 210         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 211 })
 212
 213 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 214                                     u64 bits, int limit, int delay,
 215                                     const char *reg_name)
 216 {
 217         int err;
 218
 219         nw64(reg, bits);
 220         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 221         if (err)
 222                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 223                         "would not clear, val[%llx]\n",
 224                         np->dev->name, (unsigned long long) bits, reg_name,
 225                         (unsigned long long) nr64(reg));
 226         return err;
 227 }
 228
 229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 230 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 231         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 232 })
 233
 234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 235 {
 236         u64 val = (u64) lp->timer;
 237
 238         if (on)
 239                 val |= LDG_IMGMT_ARM;
 240
 241         nw64(LDG_IMGMT(lp->ldg_num), val);
 242 }
 243
 244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 245 {
 246         unsigned long mask_reg, bits;
 247         u64 val;
 248
 249         if (ldn < 0 || ldn > LDN_MAX)
 250                 return -EINVAL;
 251
 252         if (ldn < 64) {
 253                 mask_reg = LD_IM0(ldn);
 254                 bits = LD_IM0_MASK;
 255         } else {
 256                 mask_reg = LD_IM1(ldn - 64);
 257                 bits = LD_IM1_MASK;
 258         }
 259
 260         val = nr64(mask_reg);
 261         if (on)
 262                 val &= ~bits;
 263         else
 264                 val |= bits;
 265         nw64(mask_reg, val);
 266
 267         return 0;
 268 }
 269
 270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 271 {
 272         struct niu_parent *parent = np->parent;
 273         int i;
 274
 275         for (i = 0; i <= LDN_MAX; i++) {
 276                 int err;
 277
 278                 if (parent->ldg_map[i] != lp->ldg_num)
 279                         continue;
 280
 281                 err = niu_ldn_irq_enable(np, i, on);
 282                 if (err)
 283                         return err;
 284         }
 285         return 0;
 286 }
 287
 288 static int niu_enable_interrupts(struct niu *np, int on)
 289 {
 290         int i;
 291
 292         for (i = 0; i < np->num_ldg; i++) {
 293                 struct niu_ldg *lp = &np->ldg[i];
 294                 int err;
 295
 296                 err = niu_enable_ldn_in_ldg(np, lp, on);
 297                 if (err)
 298                         return err;
 299         }
 300         for (i = 0; i < np->num_ldg; i++)
 301                 niu_ldg_rearm(np, &np->ldg[i], on);
 302
 303         return 0;
 304 }
 305
 306 static u32 phy_encode(u32 type, int port)
 307 {
 308         return (type << (port * 2));
 309 }
 310
 311 static u32 phy_decode(u32 val, int port)
 312 {
 313         return (val >> (port * 2)) & PORT_TYPE_MASK;
 314 }
 315
 316 static int mdio_wait(struct niu *np)
 317 {
 318         int limit = 1000;
 319         u64 val;
 320
 321         while (--limit > 0) {
 322                 val = nr64(MIF_FRAME_OUTPUT);
 323                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 324                         return val & MIF_FRAME_OUTPUT_DATA;
 325
 326                 udelay(10);
 327         }
 328
 329         return -ENODEV;
 330 }
 331
 332 static int mdio_read(struct niu *np, int port, int dev, int reg)
 333 {
 334         int err;
 335
 336         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 337         err = mdio_wait(np);
 338         if (err < 0)
 339                 return err;
 340
 341         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 342         return mdio_wait(np);
 343 }
 344
 345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 346 {
 347         int err;
 348
 349         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 350         err = mdio_wait(np);
 351         if (err < 0)
 352                 return err;
 353
 354         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 355         err = mdio_wait(np);
 356         if (err < 0)
 357                 return err;
 358
 359         return 0;
 360 }
 361
 362 static int mii_read(struct niu *np, int port, int reg)
 363 {
 364         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 365         return mdio_wait(np);
 366 }
 367
 368 static int mii_write(struct niu *np, int port, int reg, int data)
 369 {
 370         int err;
 371
 372         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 373         err = mdio_wait(np);
 374         if (err < 0)
 375                 return err;
 376
 377         return 0;
 378 }
 379
 380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 381 {
 382         int err;
 383
 384         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 385                          ESR2_TI_PLL_TX_CFG_L(channel),
 386                          val & 0xffff);
 387         if (!err)
 388                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 389                                  ESR2_TI_PLL_TX_CFG_H(channel),
 390                                  val >> 16);
 391         return err;
 392 }
 393
 394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 395 {
 396         int err;
 397
 398         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 399                          ESR2_TI_PLL_RX_CFG_L(channel),
 400                          val & 0xffff);
 401         if (!err)
 402                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 403                                  ESR2_TI_PLL_RX_CFG_H(channel),
 404                                  val >> 16);
 405         return err;
 406 }
 407
 408 /* Mode is always 10G fiber.  */
 409 static int serdes_init_niu_10g_fiber(struct niu *np)
 410 {
 411         struct niu_link_config *lp = &np->link_config;
 412         u32 tx_cfg, rx_cfg;
 413         unsigned long i;
 414
 415         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 416         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 417                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 418                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 419
 420         if (lp->loopback_mode == LOOPBACK_PHY) {
 421                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 422
 423                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 424                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 425
 426                 tx_cfg |= PLL_TX_CFG_ENTEST;
 427                 rx_cfg |= PLL_RX_CFG_ENTEST;
 428         }
 429
 430         /* Initialize all 4 lanes of the SERDES.  */
 431         for (i = 0; i < 4; i++) {
 432                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 433                 if (err)
 434                         return err;
 435         }
 436
 437         for (i = 0; i < 4; i++) {
 438                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 439                 if (err)
 440                         return err;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int serdes_init_niu_1g_serdes(struct niu *np)
 447 {
 448         struct niu_link_config *lp = &np->link_config;
 449         u16 pll_cfg, pll_sts;
 450         int max_retry = 100;
 451         u64 uninitialized_var(sig), mask, val;
 452         u32 tx_cfg, rx_cfg;
 453         unsigned long i;
 454         int err;
 455
 456         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 457                   PLL_TX_CFG_RATE_HALF);
 458         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 459                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 460                   PLL_RX_CFG_RATE_HALF);
 461
 462         if (np->port == 0)
 463                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 464
 465         if (lp->loopback_mode == LOOPBACK_PHY) {
 466                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 467
 468                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 469                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 470
 471                 tx_cfg |= PLL_TX_CFG_ENTEST;
 472                 rx_cfg |= PLL_RX_CFG_ENTEST;
 473         }
 474
 475         /* Initialize PLL for 1G */
 476         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 477
 478         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 479                          ESR2_TI_PLL_CFG_L, pll_cfg);
 480         if (err) {
 481                 dev_err(np->device, PFX "NIU Port %d "
 482                         "serdes_init_niu_1g_serdes: "
 483                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 484                 return err;
 485         }
 486
 487         pll_sts = PLL_CFG_ENPLL;
 488
 489         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 490                          ESR2_TI_PLL_STS_L, pll_sts);
 491         if (err) {
 492                 dev_err(np->device, PFX "NIU Port %d "
 493                         "serdes_init_niu_1g_serdes: "
 494                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 495                 return err;
 496         }
 497
 498         udelay(200);
 499
 500         /* Initialize all 4 lanes of the SERDES.  */
 501         for (i = 0; i < 4; i++) {
 502                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 503                 if (err)
 504                         return err;
 505         }
 506
 507         for (i = 0; i < 4; i++) {
 508                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 509                 if (err)
 510                         return err;
 511         }
 512
 513         switch (np->port) {
 514         case 0:
 515                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 516                 mask = val;
 517                 break;
 518
 519         case 1:
 520                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 521                 mask = val;
 522                 break;
 523
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         while (max_retry--) {
 529                 sig = nr64(ESR_INT_SIGNALS);
 530                 if ((sig & mask) == val)
 531                         break;
 532
 533                 mdelay(500);
 534         }
 535
 536         if ((sig & mask) != val) {
 537                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 538                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 539                 return -ENODEV;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int serdes_init_niu_10g_serdes(struct niu *np)
 546 {
 547         struct niu_link_config *lp = &np->link_config;
 548         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 549         int max_retry = 100;
 550         u64 uninitialized_var(sig), mask, val;
 551         unsigned long i;
 552         int err;
 553
 554         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 555         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 556                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 557                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 558
 559         if (lp->loopback_mode == LOOPBACK_PHY) {
 560                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 561
 562                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 563                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 564
 565                 tx_cfg |= PLL_TX_CFG_ENTEST;
 566                 rx_cfg |= PLL_RX_CFG_ENTEST;
 567         }
 568
 569         /* Initialize PLL for 10G */
 570         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 571
 572         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 573                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 574         if (err) {
 575                 dev_err(np->device, PFX "NIU Port %d "
 576                         "serdes_init_niu_10g_serdes: "
 577                         "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
 578                 return err;
 579         }
 580
 581         pll_sts = PLL_CFG_ENPLL;
 582
 583         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 584                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 585         if (err) {
 586                 dev_err(np->device, PFX "NIU Port %d "
 587                         "serdes_init_niu_10g_serdes: "
 588                         "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
 589                 return err;
 590         }
 591
 592         udelay(200);
 593
 594         /* Initialize all 4 lanes of the SERDES.  */
 595         for (i = 0; i < 4; i++) {
 596                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 597                 if (err)
 598                         return err;
 599         }
 600
 601         for (i = 0; i < 4; i++) {
 602                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 603                 if (err)
 604                         return err;
 605         }
 606
 607         /* check if serdes is ready */
 608
 609         switch (np->port) {
 610         case 0:
 611                 mask = ESR_INT_SIGNALS_P0_BITS;
 612                 val = (ESR_INT_SRDY0_P0 |
 613                        ESR_INT_DET0_P0 |
 614                        ESR_INT_XSRDY_P0 |
 615                        ESR_INT_XDP_P0_CH3 |
 616                        ESR_INT_XDP_P0_CH2 |
 617                        ESR_INT_XDP_P0_CH1 |
 618                        ESR_INT_XDP_P0_CH0);
 619                 break;
 620
 621         case 1:
 622                 mask = ESR_INT_SIGNALS_P1_BITS;
 623                 val = (ESR_INT_SRDY0_P1 |
 624                        ESR_INT_DET0_P1 |
 625                        ESR_INT_XSRDY_P1 |
 626                        ESR_INT_XDP_P1_CH3 |
 627                        ESR_INT_XDP_P1_CH2 |
 628                        ESR_INT_XDP_P1_CH1 |
 629                        ESR_INT_XDP_P1_CH0);
 630                 break;
 631
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         while (max_retry--) {
 637                 sig = nr64(ESR_INT_SIGNALS);
 638                 if ((sig & mask) == val)
 639                         break;
 640
 641                 mdelay(500);
 642         }
 643
 644         if ((sig & mask) != val) {
 645                 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
 646                         "[%08x] for 10G...trying 1G\n",
 647                         np->port, (int) (sig & mask), (int) val);
 648
 649                 /* 10G failed, try initializing at 1G */
 650                 err = serdes_init_niu_1g_serdes(np);
 651                 if (!err) {
 652                         np->flags &= ~NIU_FLAGS_10G;
 653                         np->mac_xcvr = MAC_XCVR_PCS;
 654                 }  else {
 655                         dev_err(np->device, PFX "Port %u 10G/1G SERDES "
 656                                 "Link Failed \n", np->port);
 657                         return -ENODEV;
 658                 }
 659         }
 660         return 0;
 661 }
 662
 663 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 664 {
 665         int err;
 666
 667         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 668         if (err >= 0) {
 669                 *val = (err & 0xffff);
 670                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 671                                 ESR_RXTX_CTRL_H(chan));
 672                 if (err >= 0)
 673                         *val |= ((err & 0xffff) << 16);
 674                 err = 0;
 675         }
 676         return err;
 677 }
 678
 679 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 680 {
 681         int err;
 682
 683         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 684                         ESR_GLUE_CTRL0_L(chan));
 685         if (err >= 0) {
 686                 *val = (err & 0xffff);
 687                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 688                                 ESR_GLUE_CTRL0_H(chan));
 689                 if (err >= 0) {
 690                         *val |= ((err & 0xffff) << 16);
 691                         err = 0;
 692                 }
 693         }
 694         return err;
 695 }
 696
 697 static int esr_read_reset(struct niu *np, u32 *val)
 698 {
 699         int err;
 700
 701         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 702                         ESR_RXTX_RESET_CTRL_L);
 703         if (err >= 0) {
 704                 *val = (err & 0xffff);
 705                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 706                                 ESR_RXTX_RESET_CTRL_H);
 707                 if (err >= 0) {
 708                         *val |= ((err & 0xffff) << 16);
 709                         err = 0;
 710                 }
 711         }
 712         return err;
 713 }
 714
 715 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 716 {
 717         int err;
 718
 719         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 720                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 721         if (!err)
 722                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 723                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 724         return err;
 725 }
 726
 727 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 728 {
 729         int err;
 730
 731         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 732                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 733         if (!err)
 734                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 735                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 736         return err;
 737 }
 738
 739 static int esr_reset(struct niu *np)
 740 {
 741         u32 uninitialized_var(reset);
 742         int err;
 743
 744         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 745                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 746         if (err)
 747                 return err;
 748         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 749                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 750         if (err)
 751                 return err;
 752         udelay(200);
 753
 754         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 755                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 756         if (err)
 757                 return err;
 758         udelay(200);
 759
 760         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 761                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 762         if (err)
 763                 return err;
 764         udelay(200);
 765
 766         err = esr_read_reset(np, &reset);
 767         if (err)
 768                 return err;
 769         if (reset != 0) {
 770                 dev_err(np->device, PFX "Port %u ESR_RESET "
 771                         "did not clear [%08x]\n",
 772                         np->port, reset);
 773                 return -ENODEV;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int serdes_init_10g(struct niu *np)
 780 {
 781         struct niu_link_config *lp = &np->link_config;
 782         unsigned long ctrl_reg, test_cfg_reg, i;
 783         u64 ctrl_val, test_cfg_val, sig, mask, val;
 784         int err;
 785
 786         switch (np->port) {
 787         case 0:
 788                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 789                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 790                 break;
 791         case 1:
 792                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 793                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 794                 break;
 795
 796         default:
 797                 return -EINVAL;
 798         }
 799         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 800                     ENET_SERDES_CTRL_SDET_1 |
 801                     ENET_SERDES_CTRL_SDET_2 |
 802                     ENET_SERDES_CTRL_SDET_3 |
 803                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 804                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 805                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 806                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 807                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 808                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 809                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 810                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 811         test_cfg_val = 0;
 812
 813         if (lp->loopback_mode == LOOPBACK_PHY) {
 814                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 815                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 816                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 817                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 818                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 819                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 820                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 821                                   ENET_SERDES_TEST_MD_3_SHIFT));
 822         }
 823
 824         nw64(ctrl_reg, ctrl_val);
 825         nw64(test_cfg_reg, test_cfg_val);
 826
 827         /* Initialize all 4 lanes of the SERDES.  */
 828         for (i = 0; i < 4; i++) {
 829                 u32 rxtx_ctrl, glue0;
 830
 831                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 832                 if (err)
 833                         return err;
 834                 err = esr_read_glue0(np, i, &glue0);
 835                 if (err)
 836                         return err;
 837
 838                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 839                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 840                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 841
 842                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 843                            ESR_GLUE_CTRL0_THCNT |
 844                            ESR_GLUE_CTRL0_BLTIME);
 845                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 846                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 847                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 848                           (BLTIME_300_CYCLES <<
 849                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 850
 851                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 852                 if (err)
 853                         return err;
 854                 err = esr_write_glue0(np, i, glue0);
 855                 if (err)
 856                         return err;
 857         }
 858
 859         err = esr_reset(np);
 860         if (err)
 861                 return err;
 862
 863         sig = nr64(ESR_INT_SIGNALS);
 864         switch (np->port) {
 865         case 0:
 866                 mask = ESR_INT_SIGNALS_P0_BITS;
 867                 val = (ESR_INT_SRDY0_P0 |
 868                        ESR_INT_DET0_P0 |
 869                        ESR_INT_XSRDY_P0 |
 870                        ESR_INT_XDP_P0_CH3 |
 871                        ESR_INT_XDP_P0_CH2 |
 872                        ESR_INT_XDP_P0_CH1 |
 873                        ESR_INT_XDP_P0_CH0);
 874                 break;
 875
 876         case 1:
 877                 mask = ESR_INT_SIGNALS_P1_BITS;
 878                 val = (ESR_INT_SRDY0_P1 |
 879                        ESR_INT_DET0_P1 |
 880                        ESR_INT_XSRDY_P1 |
 881                        ESR_INT_XDP_P1_CH3 |
 882                        ESR_INT_XDP_P1_CH2 |
 883                        ESR_INT_XDP_P1_CH1 |
 884                        ESR_INT_XDP_P1_CH0);
 885                 break;
 886
 887         default:
 888                 return -EINVAL;
 889         }
 890
 891         if ((sig & mask) != val) {
 892                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 893                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 894                         return 0;
 895                 }
 896                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 897                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 898                 return -ENODEV;
 899         }
 900         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 901                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 902         return 0;
 903 }
 904
 905 static int serdes_init_1g(struct niu *np)
 906 {
 907         u64 val;
 908
 909         val = nr64(ENET_SERDES_1_PLL_CFG);
 910         val &= ~ENET_SERDES_PLL_FBDIV2;
 911         switch (np->port) {
 912         case 0:
 913                 val |= ENET_SERDES_PLL_HRATE0;
 914                 break;
 915         case 1:
 916                 val |= ENET_SERDES_PLL_HRATE1;
 917                 break;
 918         case 2:
 919                 val |= ENET_SERDES_PLL_HRATE2;
 920                 break;
 921         case 3:
 922                 val |= ENET_SERDES_PLL_HRATE3;
 923                 break;
 924         default:
 925                 return -EINVAL;
 926         }
 927         nw64(ENET_SERDES_1_PLL_CFG, val);
 928
 929         return 0;
 930 }
 931
 932 static int serdes_init_1g_serdes(struct niu *np)
 933 {
 934         struct niu_link_config *lp = &np->link_config;
 935         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 936         u64 ctrl_val, test_cfg_val, sig, mask, val;
 937         int err;
 938         u64 reset_val, val_rd;
 939
 940         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 941                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 942                 ENET_SERDES_PLL_FBDIV0;
 943         switch (np->port) {
 944         case 0:
 945                 reset_val =  ENET_SERDES_RESET_0;
 946                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 947                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 948                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 949                 break;
 950         case 1:
 951                 reset_val =  ENET_SERDES_RESET_1;
 952                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 953                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 954                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 955                 break;
 956
 957         default:
 958                 return -EINVAL;
 959         }
 960         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 961                     ENET_SERDES_CTRL_SDET_1 |
 962                     ENET_SERDES_CTRL_SDET_2 |
 963                     ENET_SERDES_CTRL_SDET_3 |
 964                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 965                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 966                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 967                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 968                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 969                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 970                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 971                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 972         test_cfg_val = 0;
 973
 974         if (lp->loopback_mode == LOOPBACK_PHY) {
 975                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 976                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 977                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 978                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 979                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 980                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 981                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 982                                   ENET_SERDES_TEST_MD_3_SHIFT));
 983         }
 984
 985         nw64(ENET_SERDES_RESET, reset_val);
 986         mdelay(20);
 987         val_rd = nr64(ENET_SERDES_RESET);
 988         val_rd &= ~reset_val;
 989         nw64(pll_cfg, val);
 990         nw64(ctrl_reg, ctrl_val);
 991         nw64(test_cfg_reg, test_cfg_val);
 992         nw64(ENET_SERDES_RESET, val_rd);
 993         mdelay(2000);
 994
 995         /* Initialize all 4 lanes of the SERDES.  */
 996         for (i = 0; i < 4; i++) {
 997                 u32 rxtx_ctrl, glue0;
 998
 999                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000                 if (err)
1001                         return err;
1002                 err = esr_read_glue0(np, i, &glue0);
1003                 if (err)
1004                         return err;
1005
1006                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011                            ESR_GLUE_CTRL0_THCNT |
1012                            ESR_GLUE_CTRL0_BLTIME);
1013                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016                           (BLTIME_300_CYCLES <<
1017                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020                 if (err)
1021                         return err;
1022                 err = esr_write_glue0(np, i, glue0);
1023                 if (err)
1024                         return err;
1025         }
1026
1027
1028         sig = nr64(ESR_INT_SIGNALS);
1029         switch (np->port) {
1030         case 0:
1031                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032                 mask = val;
1033                 break;
1034
1035         case 1:
1036                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037                 mask = val;
1038                 break;
1039
1040         default:
1041                 return -EINVAL;
1042         }
1043
1044         if ((sig & mask) != val) {
1045                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047                 return -ENODEV;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054 {
1055         struct niu_link_config *lp = &np->link_config;
1056         int link_up;
1057         u64 val;
1058         u16 current_speed;
1059         unsigned long flags;
1060         u8 current_duplex;
1061
1062         link_up = 0;
1063         current_speed = SPEED_INVALID;
1064         current_duplex = DUPLEX_INVALID;
1065
1066         spin_lock_irqsave(&np->lock, flags);
1067
1068         val = nr64_pcs(PCS_MII_STAT);
1069
1070         if (val & PCS_MII_STAT_LINK_STATUS) {
1071                 link_up = 1;
1072                 current_speed = SPEED_1000;
1073                 current_duplex = DUPLEX_FULL;
1074         }
1075
1076         lp->active_speed = current_speed;
1077         lp->active_duplex = current_duplex;
1078         spin_unlock_irqrestore(&np->lock, flags);
1079
1080         *link_up_p = link_up;
1081         return 0;
1082 }
1083
1084 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085 {
1086         unsigned long flags;
1087         struct niu_link_config *lp = &np->link_config;
1088         int link_up = 0;
1089         int link_ok = 1;
1090         u64 val, val2;
1091         u16 current_speed;
1092         u8 current_duplex;
1093
1094         if (!(np->flags & NIU_FLAGS_10G))
1095                 return link_status_1g_serdes(np, link_up_p);
1096
1097         current_speed = SPEED_INVALID;
1098         current_duplex = DUPLEX_INVALID;
1099         spin_lock_irqsave(&np->lock, flags);
1100
1101         val = nr64_xpcs(XPCS_STATUS(0));
1102         val2 = nr64_mac(XMAC_INTER2);
1103         if (val2 & 0x01000000)
1104                 link_ok = 0;
1105
1106         if ((val & 0x1000ULL) && link_ok) {
1107                 link_up = 1;
1108                 current_speed = SPEED_10000;
1109                 current_duplex = DUPLEX_FULL;
1110         }
1111         lp->active_speed = current_speed;
1112         lp->active_duplex = current_duplex;
1113         spin_unlock_irqrestore(&np->lock, flags);
1114         *link_up_p = link_up;
1115         return 0;
1116 }
1117
1118 static int link_status_mii(struct niu *np, int *link_up_p)
1119 {
1120         struct niu_link_config *lp = &np->link_config;
1121         int err;
1122         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1123         int supported, advertising, active_speed, active_duplex;
1124
1125         err = mii_read(np, np->phy_addr, MII_BMCR);
1126         if (unlikely(err < 0))
1127                 return err;
1128         bmcr = err;
1129
1130         err = mii_read(np, np->phy_addr, MII_BMSR);
1131         if (unlikely(err < 0))
1132                 return err;
1133         bmsr = err;
1134
1135         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1136         if (unlikely(err < 0))
1137                 return err;
1138         advert = err;
1139
1140         err = mii_read(np, np->phy_addr, MII_LPA);
1141         if (unlikely(err < 0))
1142                 return err;
1143         lpa = err;
1144
1145         if (likely(bmsr & BMSR_ESTATEN)) {
1146                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1147                 if (unlikely(err < 0))
1148                         return err;
1149                 estatus = err;
1150
1151                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1152                 if (unlikely(err < 0))
1153                         return err;
1154                 ctrl1000 = err;
1155
1156                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1157                 if (unlikely(err < 0))
1158                         return err;
1159                 stat1000 = err;
1160         } else
1161                 estatus = ctrl1000 = stat1000 = 0;
1162
1163         supported = 0;
1164         if (bmsr & BMSR_ANEGCAPABLE)
1165                 supported |= SUPPORTED_Autoneg;
1166         if (bmsr & BMSR_10HALF)
1167                 supported |= SUPPORTED_10baseT_Half;
1168         if (bmsr & BMSR_10FULL)
1169                 supported |= SUPPORTED_10baseT_Full;
1170         if (bmsr & BMSR_100HALF)
1171                 supported |= SUPPORTED_100baseT_Half;
1172         if (bmsr & BMSR_100FULL)
1173                 supported |= SUPPORTED_100baseT_Full;
1174         if (estatus & ESTATUS_1000_THALF)
1175                 supported |= SUPPORTED_1000baseT_Half;
1176         if (estatus & ESTATUS_1000_TFULL)
1177                 supported |= SUPPORTED_1000baseT_Full;
1178         lp->supported = supported;
1179
1180         advertising = 0;
1181         if (advert & ADVERTISE_10HALF)
1182                 advertising |= ADVERTISED_10baseT_Half;
1183         if (advert & ADVERTISE_10FULL)
1184                 advertising |= ADVERTISED_10baseT_Full;
1185         if (advert & ADVERTISE_100HALF)
1186                 advertising |= ADVERTISED_100baseT_Half;
1187         if (advert & ADVERTISE_100FULL)
1188                 advertising |= ADVERTISED_100baseT_Full;
1189         if (ctrl1000 & ADVERTISE_1000HALF)
1190                 advertising |= ADVERTISED_1000baseT_Half;
1191         if (ctrl1000 & ADVERTISE_1000FULL)
1192                 advertising |= ADVERTISED_1000baseT_Full;
1193
1194         if (bmcr & BMCR_ANENABLE) {
1195                 int neg, neg1000;
1196
1197                 lp->active_autoneg = 1;
1198                 advertising |= ADVERTISED_Autoneg;
1199
1200                 neg = advert & lpa;
1201                 neg1000 = (ctrl1000 << 2) & stat1000;
1202
1203                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1204                         active_speed = SPEED_1000;
1205                 else if (neg & LPA_100)
1206                         active_speed = SPEED_100;
1207                 else if (neg & (LPA_10HALF | LPA_10FULL))
1208                         active_speed = SPEED_10;
1209                 else
1210                         active_speed = SPEED_INVALID;
1211
1212                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1213                         active_duplex = DUPLEX_FULL;
1214                 else if (active_speed != SPEED_INVALID)
1215                         active_duplex = DUPLEX_HALF;
1216                 else
1217                         active_duplex = DUPLEX_INVALID;
1218         } else {
1219                 lp->active_autoneg = 0;
1220
1221                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1222                         active_speed = SPEED_1000;
1223                 else if (bmcr & BMCR_SPEED100)
1224                         active_speed = SPEED_100;
1225                 else
1226                         active_speed = SPEED_10;
1227
1228                 if (bmcr & BMCR_FULLDPLX)
1229                         active_duplex = DUPLEX_FULL;
1230                 else
1231                         active_duplex = DUPLEX_HALF;
1232         }
1233
1234         lp->active_advertising = advertising;
1235         lp->active_speed = active_speed;
1236         lp->active_duplex = active_duplex;
1237         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1238
1239         return 0;
1240 }
1241
1242 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1243 {
1244         struct niu_link_config *lp = &np->link_config;
1245         u16 current_speed, bmsr;
1246         unsigned long flags;
1247         u8 current_duplex;
1248         int err, link_up;
1249
1250         link_up = 0;
1251         current_speed = SPEED_INVALID;
1252         current_duplex = DUPLEX_INVALID;
1253
1254         spin_lock_irqsave(&np->lock, flags);
1255
1256         err = -EINVAL;
1257
1258         err = mii_read(np, np->phy_addr, MII_BMSR);
1259         if (err < 0)
1260                 goto out;
1261
1262         bmsr = err;
1263         if (bmsr & BMSR_LSTATUS) {
1264                 u16 adv, lpa, common, estat;
1265
1266                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1267                 if (err < 0)
1268                         goto out;
1269                 adv = err;
1270
1271                 err = mii_read(np, np->phy_addr, MII_LPA);
1272                 if (err < 0)
1273                         goto out;
1274                 lpa = err;
1275
1276                 common = adv & lpa;
1277
1278                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1279                 if (err < 0)
1280                         goto out;
1281                 estat = err;
1282                 link_up = 1;
1283                 current_speed = SPEED_1000;
1284                 current_duplex = DUPLEX_FULL;
1285
1286         }
1287         lp->active_speed = current_speed;
1288         lp->active_duplex = current_duplex;
1289         err = 0;
1290
1291 out:
1292         spin_unlock_irqrestore(&np->lock, flags);
1293
1294         *link_up_p = link_up;
1295         return err;
1296 }
1297
1298 static int link_status_1g(struct niu *np, int *link_up_p)
1299 {
1300         struct niu_link_config *lp = &np->link_config;
1301         unsigned long flags;
1302         int err;
1303
1304         spin_lock_irqsave(&np->lock, flags);
1305
1306         err = link_status_mii(np, link_up_p);
1307         lp->supported |= SUPPORTED_TP;
1308         lp->active_advertising |= ADVERTISED_TP;
1309
1310         spin_unlock_irqrestore(&np->lock, flags);
1311         return err;
1312 }
1313
1314 static int bcm8704_reset(struct niu *np)
1315 {
1316         int err, limit;
1317
1318         err = mdio_read(np, np->phy_addr,
1319                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1320         if (err < 0 || err == 0xffff)
1321                 return err;
1322         err |= BMCR_RESET;
1323         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1324                          MII_BMCR, err);
1325         if (err)
1326                 return err;
1327
1328         limit = 1000;
1329         while (--limit >= 0) {
1330                 err = mdio_read(np, np->phy_addr,
1331                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1332                 if (err < 0)
1333                         return err;
1334                 if (!(err & BMCR_RESET))
1335                         break;
1336         }
1337         if (limit < 0) {
1338                 dev_err(np->device, PFX "Port %u PHY will not reset "
1339                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
1340                 return -ENODEV;
1341         }
1342         return 0;
1343 }
1344
1345 /* When written, certain PHY registers need to be read back twice
1346  * in order for the bits to settle properly.
1347  */
1348 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1349 {
1350         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1351         if (err < 0)
1352                 return err;
1353         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1354         if (err < 0)
1355                 return err;
1356         return 0;
1357 }
1358
1359 static int bcm8706_init_user_dev3(struct niu *np)
1360 {
1361         int err;
1362
1363
1364         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365                         BCM8704_USER_OPT_DIGITAL_CTRL);
1366         if (err < 0)
1367                 return err;
1368         err &= ~USER_ODIG_CTRL_GPIOS;
1369         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1370         err |=  USER_ODIG_CTRL_RESV2;
1371         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1372                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1373         if (err)
1374                 return err;
1375
1376         mdelay(1000);
1377
1378         return 0;
1379 }
1380
1381 static int bcm8704_init_user_dev3(struct niu *np)
1382 {
1383         int err;
1384
1385         err = mdio_write(np, np->phy_addr,
1386                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1387                          (USER_CONTROL_OPTXRST_LVL |
1388                           USER_CONTROL_OPBIASFLT_LVL |
1389                           USER_CONTROL_OBTMPFLT_LVL |
1390                           USER_CONTROL_OPPRFLT_LVL |
1391                           USER_CONTROL_OPTXFLT_LVL |
1392                           USER_CONTROL_OPRXLOS_LVL |
1393                           USER_CONTROL_OPRXFLT_LVL |
1394                           USER_CONTROL_OPTXON_LVL |
1395                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1396         if (err)
1397                 return err;
1398
1399         err = mdio_write(np, np->phy_addr,
1400                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1401                          (USER_PMD_TX_CTL_XFP_CLKEN |
1402                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1403                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1404                           USER_PMD_TX_CTL_TSCK_LPWREN));
1405         if (err)
1406                 return err;
1407
1408         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1409         if (err)
1410                 return err;
1411         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1412         if (err)
1413                 return err;
1414
1415         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1416                         BCM8704_USER_OPT_DIGITAL_CTRL);
1417         if (err < 0)
1418                 return err;
1419         err &= ~USER_ODIG_CTRL_GPIOS;
1420         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1421         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1422                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1423         if (err)
1424                 return err;
1425
1426         mdelay(1000);
1427
1428         return 0;
1429 }
1430
1431 static int mrvl88x2011_act_led(struct niu *np, int val)
1432 {
1433         int     err;
1434
1435         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1436                 MRVL88X2011_LED_8_TO_11_CTL);
1437         if (err < 0)
1438                 return err;
1439
1440         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1441         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1442
1443         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1444                           MRVL88X2011_LED_8_TO_11_CTL, err);
1445 }
1446
1447 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1448 {
1449         int     err;
1450
1451         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1452                         MRVL88X2011_LED_BLINK_CTL);
1453         if (err >= 0) {
1454                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1455                 err |= (rate << 4);
1456
1457                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1458                                  MRVL88X2011_LED_BLINK_CTL, err);
1459         }
1460
1461         return err;
1462 }
1463
1464 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1465 {
1466         int     err;
1467
1468         /* Set LED functions */
1469         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1470         if (err)
1471                 return err;
1472
1473         /* led activity */
1474         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1475         if (err)
1476                 return err;
1477
1478         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1479                         MRVL88X2011_GENERAL_CTL);
1480         if (err < 0)
1481                 return err;
1482
1483         err |= MRVL88X2011_ENA_XFPREFCLK;
1484
1485         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1486                          MRVL88X2011_GENERAL_CTL, err);
1487         if (err < 0)
1488                 return err;
1489
1490         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1491                         MRVL88X2011_PMA_PMD_CTL_1);
1492         if (err < 0)
1493                 return err;
1494
1495         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1496                 err |= MRVL88X2011_LOOPBACK;
1497         else
1498                 err &= ~MRVL88X2011_LOOPBACK;
1499
1500         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1501                          MRVL88X2011_PMA_PMD_CTL_1, err);
1502         if (err < 0)
1503                 return err;
1504
1505         /* Enable PMD  */
1506         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1507                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1508 }
1509
1510
1511 static int xcvr_diag_bcm870x(struct niu *np)
1512 {
1513         u16 analog_stat0, tx_alarm_status;
1514         int err = 0;
1515
1516 #if 1
1517         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1518                         MII_STAT1000);
1519         if (err < 0)
1520                 return err;
1521         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1522                 np->port, err);
1523
1524         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1525         if (err < 0)
1526                 return err;
1527         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1528                 np->port, err);
1529
1530         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1531                         MII_NWAYTEST);
1532         if (err < 0)
1533                 return err;
1534         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1535                 np->port, err);
1536 #endif
1537
1538         /* XXX dig this out it might not be so useful XXX */
1539         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1540                         BCM8704_USER_ANALOG_STATUS0);
1541         if (err < 0)
1542                 return err;
1543         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1544                         BCM8704_USER_ANALOG_STATUS0);
1545         if (err < 0)
1546                 return err;
1547         analog_stat0 = err;
1548
1549         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1550                         BCM8704_USER_TX_ALARM_STATUS);
1551         if (err < 0)
1552                 return err;
1553         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1554                         BCM8704_USER_TX_ALARM_STATUS);
1555         if (err < 0)
1556                 return err;
1557         tx_alarm_status = err;
1558
1559         if (analog_stat0 != 0x03fc) {
1560                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1561                         pr_info(PFX "Port %u cable not connected "
1562                                 "or bad cable.\n", np->port);
1563                 } else if (analog_stat0 == 0x639c) {
1564                         pr_info(PFX "Port %u optical module is bad "
1565                                 "or missing.\n", np->port);
1566                 }
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1573 {
1574         struct niu_link_config *lp = &np->link_config;
1575         int err;
1576
1577         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1578                         MII_BMCR);
1579         if (err < 0)
1580                 return err;
1581
1582         err &= ~BMCR_LOOPBACK;
1583
1584         if (lp->loopback_mode == LOOPBACK_MAC)
1585                 err |= BMCR_LOOPBACK;
1586
1587         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1588                          MII_BMCR, err);
1589         if (err)
1590                 return err;
1591
1592         return 0;
1593 }
1594
1595 static int xcvr_init_10g_bcm8706(struct niu *np)
1596 {
1597         int err = 0;
1598         u64 val;
1599
1600         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1601             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1602                         return err;
1603
1604         val = nr64_mac(XMAC_CONFIG);
1605         val &= ~XMAC_CONFIG_LED_POLARITY;
1606         val |= XMAC_CONFIG_FORCE_LED_ON;
1607         nw64_mac(XMAC_CONFIG, val);
1608
1609         val = nr64(MIF_CONFIG);
1610         val |= MIF_CONFIG_INDIRECT_MODE;
1611         nw64(MIF_CONFIG, val);
1612
1613         err = bcm8704_reset(np);
1614         if (err)
1615                 return err;
1616
1617         err = xcvr_10g_set_lb_bcm870x(np);
1618         if (err)
1619                 return err;
1620
1621         err = bcm8706_init_user_dev3(np);
1622         if (err)
1623                 return err;
1624
1625         err = xcvr_diag_bcm870x(np);
1626         if (err)
1627                 return err;
1628
1629         return 0;
1630 }
1631
1632 static int xcvr_init_10g_bcm8704(struct niu *np)
1633 {
1634         int err;
1635
1636         err = bcm8704_reset(np);
1637         if (err)
1638                 return err;
1639
1640         err = bcm8704_init_user_dev3(np);
1641         if (err)
1642                 return err;
1643
1644         err = xcvr_10g_set_lb_bcm870x(np);
1645         if (err)
1646                 return err;
1647
1648         err =  xcvr_diag_bcm870x(np);
1649         if (err)
1650                 return err;
1651
1652         return 0;
1653 }
1654
1655 static int xcvr_init_10g(struct niu *np)
1656 {
1657         int phy_id, err;
1658         u64 val;
1659
1660         val = nr64_mac(XMAC_CONFIG);
1661         val &= ~XMAC_CONFIG_LED_POLARITY;
1662         val |= XMAC_CONFIG_FORCE_LED_ON;
1663         nw64_mac(XMAC_CONFIG, val);
1664
1665         /* XXX shared resource, lock parent XXX */
1666         val = nr64(MIF_CONFIG);
1667         val |= MIF_CONFIG_INDIRECT_MODE;
1668         nw64(MIF_CONFIG, val);
1669
1670         phy_id = phy_decode(np->parent->port_phy, np->port);
1671         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1672
1673         /* handle different phy types */
1674         switch (phy_id & NIU_PHY_ID_MASK) {
1675         case NIU_PHY_ID_MRVL88X2011:
1676                 err = xcvr_init_10g_mrvl88x2011(np);
1677                 break;
1678
1679         default: /* bcom 8704 */
1680                 err = xcvr_init_10g_bcm8704(np);
1681                 break;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int mii_reset(struct niu *np)
1688 {
1689         int limit, err;
1690
1691         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1692         if (err)
1693                 return err;
1694
1695         limit = 1000;
1696         while (--limit >= 0) {
1697                 udelay(500);
1698                 err = mii_read(np, np->phy_addr, MII_BMCR);
1699                 if (err < 0)
1700                         return err;
1701                 if (!(err & BMCR_RESET))
1702                         break;
1703         }
1704         if (limit < 0) {
1705                 dev_err(np->device, PFX "Port %u MII would not reset, "
1706                         "bmcr[%04x]\n", np->port, err);
1707                 return -ENODEV;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int xcvr_init_1g_rgmii(struct niu *np)
1714 {
1715         int err;
1716         u64 val;
1717         u16 bmcr, bmsr, estat;
1718
1719         val = nr64(MIF_CONFIG);
1720         val &= ~MIF_CONFIG_INDIRECT_MODE;
1721         nw64(MIF_CONFIG, val);
1722
1723         err = mii_reset(np);
1724         if (err)
1725                 return err;
1726
1727         err = mii_read(np, np->phy_addr, MII_BMSR);
1728         if (err < 0)
1729                 return err;
1730         bmsr = err;
1731
1732         estat = 0;
1733         if (bmsr & BMSR_ESTATEN) {
1734                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1735                 if (err < 0)
1736                         return err;
1737                 estat = err;
1738         }
1739
1740         bmcr = 0;
1741         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1742         if (err)
1743                 return err;
1744
1745         if (bmsr & BMSR_ESTATEN) {
1746                 u16 ctrl1000 = 0;
1747
1748                 if (estat & ESTATUS_1000_TFULL)
1749                         ctrl1000 |= ADVERTISE_1000FULL;
1750                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1751                 if (err)
1752                         return err;
1753         }
1754
1755         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1756
1757         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758         if (err)
1759                 return err;
1760
1761         err = mii_read(np, np->phy_addr, MII_BMCR);
1762         if (err < 0)
1763                 return err;
1764         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1765
1766         err = mii_read(np, np->phy_addr, MII_BMSR);
1767         if (err < 0)
1768                 return err;
1769
1770         return 0;
1771 }
1772
1773 static int mii_init_common(struct niu *np)
1774 {
1775         struct niu_link_config *lp = &np->link_config;
1776         u16 bmcr, bmsr, adv, estat;
1777         int err;
1778
1779         err = mii_reset(np);
1780         if (err)
1781                 return err;
1782
1783         err = mii_read(np, np->phy_addr, MII_BMSR);
1784         if (err < 0)
1785                 return err;
1786         bmsr = err;
1787
1788         estat = 0;
1789         if (bmsr & BMSR_ESTATEN) {
1790                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1791                 if (err < 0)
1792                         return err;
1793                 estat = err;
1794         }
1795
1796         bmcr = 0;
1797         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1798         if (err)
1799                 return err;
1800
1801         if (lp->loopback_mode == LOOPBACK_MAC) {
1802                 bmcr |= BMCR_LOOPBACK;
1803                 if (lp->active_speed == SPEED_1000)
1804                         bmcr |= BMCR_SPEED1000;
1805                 if (lp->active_duplex == DUPLEX_FULL)
1806                         bmcr |= BMCR_FULLDPLX;
1807         }
1808
1809         if (lp->loopback_mode == LOOPBACK_PHY) {
1810                 u16 aux;
1811
1812                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1813                        BCM5464R_AUX_CTL_WRITE_1);
1814                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1815                 if (err)
1816                         return err;
1817         }
1818
1819         if (lp->autoneg) {
1820                 u16 ctrl1000;
1821
1822                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1823                 if ((bmsr & BMSR_10HALF) &&
1824                         (lp->advertising & ADVERTISED_10baseT_Half))
1825                         adv |= ADVERTISE_10HALF;
1826                 if ((bmsr & BMSR_10FULL) &&
1827                         (lp->advertising & ADVERTISED_10baseT_Full))
1828                         adv |= ADVERTISE_10FULL;
1829                 if ((bmsr & BMSR_100HALF) &&
1830                         (lp->advertising & ADVERTISED_100baseT_Half))
1831                         adv |= ADVERTISE_100HALF;
1832                 if ((bmsr & BMSR_100FULL) &&
1833                         (lp->advertising & ADVERTISED_100baseT_Full))
1834                         adv |= ADVERTISE_100FULL;
1835                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1836                 if (err)
1837                         return err;
1838
1839                 if (likely(bmsr & BMSR_ESTATEN)) {
1840                         ctrl1000 = 0;
1841                         if ((estat & ESTATUS_1000_THALF) &&
1842                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1843                                 ctrl1000 |= ADVERTISE_1000HALF;
1844                         if ((estat & ESTATUS_1000_TFULL) &&
1845                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1846                                 ctrl1000 |= ADVERTISE_1000FULL;
1847                         err = mii_write(np, np->phy_addr,
1848                                         MII_CTRL1000, ctrl1000);
1849                         if (err)
1850                                 return err;
1851                 }
1852
1853                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1854         } else {
1855                 /* !lp->autoneg */
1856                 int fulldpx;
1857
1858                 if (lp->duplex == DUPLEX_FULL) {
1859                         bmcr |= BMCR_FULLDPLX;
1860                         fulldpx = 1;
1861                 } else if (lp->duplex == DUPLEX_HALF)
1862                         fulldpx = 0;
1863                 else
1864                         return -EINVAL;
1865
1866                 if (lp->speed == SPEED_1000) {
1867                         /* if X-full requested while not supported, or
1868                            X-half requested while not supported... */
1869                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1870                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1871                                 return -EINVAL;
1872                         bmcr |= BMCR_SPEED1000;
1873                 } else if (lp->speed == SPEED_100) {
1874                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1875                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1876                                 return -EINVAL;
1877                         bmcr |= BMCR_SPEED100;
1878                 } else if (lp->speed == SPEED_10) {
1879                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1880                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1881                                 return -EINVAL;
1882                 } else
1883                         return -EINVAL;
1884         }
1885
1886         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1887         if (err)
1888                 return err;
1889
1890 #if 0
1891         err = mii_read(np, np->phy_addr, MII_BMCR);
1892         if (err < 0)
1893                 return err;
1894         bmcr = err;
1895
1896         err = mii_read(np, np->phy_addr, MII_BMSR);
1897         if (err < 0)
1898                 return err;
1899         bmsr = err;
1900
1901         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902                 np->port, bmcr, bmsr);
1903 #endif
1904
1905         return 0;
1906 }
1907
1908 static int xcvr_init_1g(struct niu *np)
1909 {
1910         u64 val;
1911
1912         /* XXX shared resource, lock parent XXX */
1913         val = nr64(MIF_CONFIG);
1914         val &= ~MIF_CONFIG_INDIRECT_MODE;
1915         nw64(MIF_CONFIG, val);
1916
1917         return mii_init_common(np);
1918 }
1919
1920 static int niu_xcvr_init(struct niu *np)
1921 {
1922         const struct niu_phy_ops *ops = np->phy_ops;
1923         int err;
1924
1925         err = 0;
1926         if (ops->xcvr_init)
1927                 err = ops->xcvr_init(np);
1928
1929         return err;
1930 }
1931
1932 static int niu_serdes_init(struct niu *np)
1933 {
1934         const struct niu_phy_ops *ops = np->phy_ops;
1935         int err;
1936
1937         err = 0;
1938         if (ops->serdes_init)
1939                 err = ops->serdes_init(np);
1940
1941         return err;
1942 }
1943
1944 static void niu_init_xif(struct niu *);
1945 static void niu_handle_led(struct niu *, int status);
1946
1947 static int niu_link_status_common(struct niu *np, int link_up)
1948 {
1949         struct niu_link_config *lp = &np->link_config;
1950         struct net_device *dev = np->dev;
1951         unsigned long flags;
1952
1953         if (!netif_carrier_ok(dev) && link_up) {
1954                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1955                        dev->name,
1956                        (lp->active_speed == SPEED_10000 ?
1957                         "10Gb/sec" :
1958                         (lp->active_speed == SPEED_1000 ?
1959                          "1Gb/sec" :
1960                          (lp->active_speed == SPEED_100 ?
1961                           "100Mbit/sec" : "10Mbit/sec"))),
1962                        (lp->active_duplex == DUPLEX_FULL ?
1963                         "full" : "half"));
1964
1965                 spin_lock_irqsave(&np->lock, flags);
1966                 niu_init_xif(np);
1967                 niu_handle_led(np, 1);
1968                 spin_unlock_irqrestore(&np->lock, flags);
1969
1970                 netif_carrier_on(dev);
1971         } else if (netif_carrier_ok(dev) && !link_up) {
1972                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1973                 spin_lock_irqsave(&np->lock, flags);
1974                 niu_handle_led(np, 0);
1975                 spin_unlock_irqrestore(&np->lock, flags);
1976                 netif_carrier_off(dev);
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1983 {
1984         int err, link_up, pma_status, pcs_status;
1985
1986         link_up = 0;
1987
1988         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1989                         MRVL88X2011_10G_PMD_STATUS_2);
1990         if (err < 0)
1991                 goto out;
1992
1993         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1995                         MRVL88X2011_PMA_PMD_STATUS_1);
1996         if (err < 0)
1997                 goto out;
1998
1999         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2000
2001         /* Check PMC Register : 3.0001.2 == 1: read twice */
2002         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2003                         MRVL88X2011_PMA_PMD_STATUS_1);
2004         if (err < 0)
2005                 goto out;
2006
2007         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2008                         MRVL88X2011_PMA_PMD_STATUS_1);
2009         if (err < 0)
2010                 goto out;
2011
2012         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2013
2014         /* Check XGXS Register : 4.0018.[0-3,12] */
2015         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2016                         MRVL88X2011_10G_XGXS_LANE_STAT);
2017         if (err < 0)
2018                 goto out;
2019
2020         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2021                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2022                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2023                     0x800))
2024                 link_up = (pma_status && pcs_status) ? 1 : 0;
2025
2026         np->link_config.active_speed = SPEED_10000;
2027         np->link_config.active_duplex = DUPLEX_FULL;
2028         err = 0;
2029 out:
2030         mrvl88x2011_act_led(np, (link_up ?
2031                                  MRVL88X2011_LED_CTL_PCS_ACT :
2032                                  MRVL88X2011_LED_CTL_OFF));
2033
2034         *link_up_p = link_up;
2035         return err;
2036 }
2037
2038 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2039 {
2040         int err, link_up;
2041         link_up = 0;
2042
2043         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2044                         BCM8704_PMD_RCV_SIGDET);
2045         if (err < 0 || err == 0xffff)
2046                 goto out;
2047         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2048                 err = 0;
2049                 goto out;
2050         }
2051
2052         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2053                         BCM8704_PCS_10G_R_STATUS);
2054         if (err < 0)
2055                 goto out;
2056
2057         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2058                 err = 0;
2059                 goto out;
2060         }
2061
2062         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2063                         BCM8704_PHYXS_XGXS_LANE_STAT);
2064         if (err < 0)
2065                 goto out;
2066         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2067                     PHYXS_XGXS_LANE_STAT_MAGIC |
2068                     PHYXS_XGXS_LANE_STAT_PATTEST |
2069                     PHYXS_XGXS_LANE_STAT_LANE3 |
2070                     PHYXS_XGXS_LANE_STAT_LANE2 |
2071                     PHYXS_XGXS_LANE_STAT_LANE1 |
2072                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2073                 err = 0;
2074                 np->link_config.active_speed = SPEED_INVALID;
2075                 np->link_config.active_duplex = DUPLEX_INVALID;
2076                 goto out;
2077         }
2078
2079         link_up = 1;
2080         np->link_config.active_speed = SPEED_10000;
2081         np->link_config.active_duplex = DUPLEX_FULL;
2082         err = 0;
2083
2084 out:
2085         *link_up_p = link_up;
2086         return err;
2087 }
2088
2089 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2090 {
2091         int err, link_up;
2092
2093         link_up = 0;
2094
2095         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2096                         BCM8704_PMD_RCV_SIGDET);
2097         if (err < 0)
2098                 goto out;
2099         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2100                 err = 0;
2101                 goto out;
2102         }
2103
2104         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2105                         BCM8704_PCS_10G_R_STATUS);
2106         if (err < 0)
2107                 goto out;
2108         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2109                 err = 0;
2110                 goto out;
2111         }
2112
2113         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2114                         BCM8704_PHYXS_XGXS_LANE_STAT);
2115         if (err < 0)
2116                 goto out;
2117
2118         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2119                     PHYXS_XGXS_LANE_STAT_MAGIC |
2120                     PHYXS_XGXS_LANE_STAT_LANE3 |
2121                     PHYXS_XGXS_LANE_STAT_LANE2 |
2122                     PHYXS_XGXS_LANE_STAT_LANE1 |
2123                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2124                 err = 0;
2125                 goto out;
2126         }
2127
2128         link_up = 1;
2129         np->link_config.active_speed = SPEED_10000;
2130         np->link_config.active_duplex = DUPLEX_FULL;
2131         err = 0;
2132
2133 out:
2134         *link_up_p = link_up;
2135         return err;
2136 }
2137
2138 static int link_status_10g(struct niu *np, int *link_up_p)
2139 {
2140         unsigned long flags;
2141         int err = -EINVAL;
2142
2143         spin_lock_irqsave(&np->lock, flags);
2144
2145         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2146                 int phy_id;
2147
2148                 phy_id = phy_decode(np->parent->port_phy, np->port);
2149                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2150
2151                 /* handle different phy types */
2152                 switch (phy_id & NIU_PHY_ID_MASK) {
2153                 case NIU_PHY_ID_MRVL88X2011:
2154                         err = link_status_10g_mrvl(np, link_up_p);
2155                         break;
2156
2157                 default: /* bcom 8704 */
2158                         err = link_status_10g_bcom(np, link_up_p);
2159                         break;
2160                 }
2161         }
2162
2163         spin_unlock_irqrestore(&np->lock, flags);
2164
2165         return err;
2166 }
2167
2168 static int niu_10g_phy_present(struct niu *np)
2169 {
2170         u64 sig, mask, val;
2171
2172         sig = nr64(ESR_INT_SIGNALS);
2173         switch (np->port) {
2174         case 0:
2175                 mask = ESR_INT_SIGNALS_P0_BITS;
2176                 val = (ESR_INT_SRDY0_P0 |
2177                        ESR_INT_DET0_P0 |
2178                        ESR_INT_XSRDY_P0 |
2179                        ESR_INT_XDP_P0_CH3 |
2180                        ESR_INT_XDP_P0_CH2 |
2181                        ESR_INT_XDP_P0_CH1 |
2182                        ESR_INT_XDP_P0_CH0);
2183                 break;
2184
2185         case 1:
2186                 mask = ESR_INT_SIGNALS_P1_BITS;
2187                 val = (ESR_INT_SRDY0_P1 |
2188                        ESR_INT_DET0_P1 |
2189                        ESR_INT_XSRDY_P1 |
2190                        ESR_INT_XDP_P1_CH3 |
2191                        ESR_INT_XDP_P1_CH2 |
2192                        ESR_INT_XDP_P1_CH1 |
2193                        ESR_INT_XDP_P1_CH0);
2194                 break;
2195
2196         default:
2197                 return 0;
2198         }
2199
2200         if ((sig & mask) != val)
2201                 return 0;
2202         return 1;
2203 }
2204
2205 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2206 {
2207         unsigned long flags;
2208         int err = 0;
2209         int phy_present;
2210         int phy_present_prev;
2211
2212         spin_lock_irqsave(&np->lock, flags);
2213
2214         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2215                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2216                         1 : 0;
2217                 phy_present = niu_10g_phy_present(np);
2218                 if (phy_present != phy_present_prev) {
2219                         /* state change */
2220                         if (phy_present) {
2221                                 /* A NEM was just plugged in */
2222                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2223                                 if (np->phy_ops->xcvr_init)
2224                                         err = np->phy_ops->xcvr_init(np);
2225                                 if (err) {
2226                                         err = mdio_read(np, np->phy_addr,
2227                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2228                                         if (err == 0xffff) {
2229                                                 /* No mdio, back-to-back XAUI */
2230                                                 goto out;
2231                                         }
2232                                         /* debounce */
2233                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2234                                 }
2235                         } else {
2236                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2237                                 *link_up_p = 0;
2238                                 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2239                                         np->dev->name);
2240                         }
2241                 }
2242 out:
2243                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2244                         err = link_status_10g_bcm8706(np, link_up_p);
2245                         if (err == 0xffff) {
2246                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2247                                 *link_up_p = 1;
2248                                 np->link_config.active_speed = SPEED_10000;
2249                                 np->link_config.active_duplex = DUPLEX_FULL;
2250                         }
2251                 }
2252         }
2253
2254         spin_unlock_irqrestore(&np->lock, flags);
2255
2256         return 0;
2257 }
2258
2259 static int niu_link_status(struct niu *np, int *link_up_p)
2260 {
2261         const struct niu_phy_ops *ops = np->phy_ops;
2262         int err;
2263
2264         err = 0;
2265         if (ops->link_status)
2266                 err = ops->link_status(np, link_up_p);
2267
2268         return err;
2269 }
2270
2271 static void niu_timer(unsigned long __opaque)
2272 {
2273         struct niu *np = (struct niu *) __opaque;
2274         unsigned long off;
2275         int err, link_up;
2276
2277         err = niu_link_status(np, &link_up);
2278         if (!err)
2279                 niu_link_status_common(np, link_up);
2280
2281         if (netif_carrier_ok(np->dev))
2282                 off = 5 * HZ;
2283         else
2284                 off = 1 * HZ;
2285         np->timer.expires = jiffies + off;
2286
2287         add_timer(&np->timer);
2288 }
2289
2290 static const struct niu_phy_ops phy_ops_10g_serdes = {
2291         .serdes_init            = serdes_init_10g_serdes,
2292         .link_status            = link_status_10g_serdes,
2293 };
2294
2295 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2296         .serdes_init            = serdes_init_niu_10g_serdes,
2297         .link_status            = link_status_10g_serdes,
2298 };
2299
2300 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2301         .serdes_init            = serdes_init_niu_1g_serdes,
2302         .link_status            = link_status_1g_serdes,
2303 };
2304
2305 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2306         .xcvr_init              = xcvr_init_1g_rgmii,
2307         .link_status            = link_status_1g_rgmii,
2308 };
2309
2310 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2311         .serdes_init            = serdes_init_niu_10g_fiber,
2312         .xcvr_init              = xcvr_init_10g,
2313         .link_status            = link_status_10g,
2314 };
2315
2316 static const struct niu_phy_ops phy_ops_10g_fiber = {
2317         .serdes_init            = serdes_init_10g,
2318         .xcvr_init              = xcvr_init_10g,
2319         .link_status            = link_status_10g,
2320 };
2321
2322 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2323         .serdes_init            = serdes_init_10g,
2324         .xcvr_init              = xcvr_init_10g_bcm8706,
2325         .link_status            = link_status_10g_hotplug,
2326 };
2327
2328 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2329         .serdes_init            = serdes_init_niu_10g_fiber,
2330         .xcvr_init              = xcvr_init_10g_bcm8706,
2331         .link_status            = link_status_10g_hotplug,
2332 };
2333
2334 static const struct niu_phy_ops phy_ops_10g_copper = {
2335         .serdes_init            = serdes_init_10g,
2336         .link_status            = link_status_10g, /* XXX */
2337 };
2338
2339 static const struct niu_phy_ops phy_ops_1g_fiber = {
2340         .serdes_init            = serdes_init_1g,
2341         .xcvr_init              = xcvr_init_1g,
2342         .link_status            = link_status_1g,
2343 };
2344
2345 static const struct niu_phy_ops phy_ops_1g_copper = {
2346         .xcvr_init              = xcvr_init_1g,
2347         .link_status            = link_status_1g,
2348 };
2349
2350 struct niu_phy_template {
2351         const struct niu_phy_ops        *ops;
2352         u32                             phy_addr_base;
2353 };
2354
2355 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2356         .ops            = &phy_ops_10g_fiber_niu,
2357         .phy_addr_base  = 16,
2358 };
2359
2360 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2361         .ops            = &phy_ops_10g_serdes_niu,
2362         .phy_addr_base  = 0,
2363 };
2364
2365 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2366         .ops            = &phy_ops_1g_serdes_niu,
2367         .phy_addr_base  = 0,
2368 };
2369
2370 static const struct niu_phy_template phy_template_10g_fiber = {
2371         .ops            = &phy_ops_10g_fiber,
2372         .phy_addr_base  = 8,
2373 };
2374
2375 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2376         .ops            = &phy_ops_10g_fiber_hotplug,
2377         .phy_addr_base  = 8,
2378 };
2379
2380 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2381         .ops            = &phy_ops_niu_10g_hotplug,
2382         .phy_addr_base  = 8,
2383 };
2384
2385 static const struct niu_phy_template phy_template_10g_copper = {
2386         .ops            = &phy_ops_10g_copper,
2387         .phy_addr_base  = 10,
2388 };
2389
2390 static const struct niu_phy_template phy_template_1g_fiber = {
2391         .ops            = &phy_ops_1g_fiber,
2392         .phy_addr_base  = 0,
2393 };
2394
2395 static const struct niu_phy_template phy_template_1g_copper = {
2396         .ops            = &phy_ops_1g_copper,
2397         .phy_addr_base  = 0,
2398 };
2399
2400 static const struct niu_phy_template phy_template_1g_rgmii = {
2401         .ops            = &phy_ops_1g_rgmii,
2402         .phy_addr_base  = 0,
2403 };
2404
2405 static const struct niu_phy_template phy_template_10g_serdes = {
2406         .ops            = &phy_ops_10g_serdes,
2407         .phy_addr_base  = 0,
2408 };
2409
2410 static int niu_atca_port_num[4] = {
2411         0, 0,  11, 10
2412 };
2413
2414 static int serdes_init_10g_serdes(struct niu *np)
2415 {
2416         struct niu_link_config *lp = &np->link_config;
2417         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2418         u64 ctrl_val, test_cfg_val, sig, mask, val;
2419         u64 reset_val;
2420
2421         switch (np->port) {
2422         case 0:
2423                 reset_val =  ENET_SERDES_RESET_0;
2424                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2425                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2426                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2427                 break;
2428         case 1:
2429                 reset_val =  ENET_SERDES_RESET_1;
2430                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2431                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2432                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2433                 break;
2434
2435         default:
2436                 return -EINVAL;
2437         }
2438         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2439                     ENET_SERDES_CTRL_SDET_1 |
2440                     ENET_SERDES_CTRL_SDET_2 |
2441                     ENET_SERDES_CTRL_SDET_3 |
2442                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2443                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2444                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2445                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2446                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2447                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2448                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2449                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2450         test_cfg_val = 0;
2451
2452         if (lp->loopback_mode == LOOPBACK_PHY) {
2453                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2454                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2455                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2456                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2457                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2458                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2459                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2460                                   ENET_SERDES_TEST_MD_3_SHIFT));
2461         }
2462
2463         esr_reset(np);
2464         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2465         nw64(ctrl_reg, ctrl_val);
2466         nw64(test_cfg_reg, test_cfg_val);
2467
2468         /* Initialize all 4 lanes of the SERDES.  */
2469         for (i = 0; i < 4; i++) {
2470                 u32 rxtx_ctrl, glue0;
2471                 int err;
2472
2473                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2474                 if (err)
2475                         return err;
2476                 err = esr_read_glue0(np, i, &glue0);
2477                 if (err)
2478                         return err;
2479
2480                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2481                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2482                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2483
2484                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2485                            ESR_GLUE_CTRL0_THCNT |
2486                            ESR_GLUE_CTRL0_BLTIME);
2487                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2488                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2489                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2490                           (BLTIME_300_CYCLES <<
2491                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2492
2493                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2494                 if (err)
2495                         return err;
2496                 err = esr_write_glue0(np, i, glue0);
2497                 if (err)
2498                         return err;
2499         }
2500
2501
2502         sig = nr64(ESR_INT_SIGNALS);
2503         switch (np->port) {
2504         case 0:
2505                 mask = ESR_INT_SIGNALS_P0_BITS;
2506                 val = (ESR_INT_SRDY0_P0 |
2507                        ESR_INT_DET0_P0 |
2508                        ESR_INT_XSRDY_P0 |
2509                        ESR_INT_XDP_P0_CH3 |
2510                        ESR_INT_XDP_P0_CH2 |
2511                        ESR_INT_XDP_P0_CH1 |
2512                        ESR_INT_XDP_P0_CH0);
2513                 break;
2514
2515         case 1:
2516                 mask = ESR_INT_SIGNALS_P1_BITS;
2517                 val = (ESR_INT_SRDY0_P1 |
2518                        ESR_INT_DET0_P1 |
2519                        ESR_INT_XSRDY_P1 |
2520                        ESR_INT_XDP_P1_CH3 |
2521                        ESR_INT_XDP_P1_CH2 |
2522                        ESR_INT_XDP_P1_CH1 |
2523                        ESR_INT_XDP_P1_CH0);
2524                 break;
2525
2526         default:
2527                 return -EINVAL;
2528         }
2529
2530         if ((sig & mask) != val) {
2531                 int err;
2532                 err = serdes_init_1g_serdes(np);
2533                 if (!err) {
2534                         np->flags &= ~NIU_FLAGS_10G;
2535                         np->mac_xcvr = MAC_XCVR_PCS;
2536                 }  else {
2537                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2538                          np->port);
2539                         return -ENODEV;
2540                 }
2541         }
2542
2543         return 0;
2544 }
2545
2546 static int niu_determine_phy_disposition(struct niu *np)
2547 {
2548         struct niu_parent *parent = np->parent;
2549         u8 plat_type = parent->plat_type;
2550         const struct niu_phy_template *tp;
2551         u32 phy_addr_off = 0;
2552
2553         if (plat_type == PLAT_TYPE_NIU) {
2554                 switch (np->flags &
2555                         (NIU_FLAGS_10G |
2556                          NIU_FLAGS_FIBER |
2557                          NIU_FLAGS_XCVR_SERDES)) {
2558                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2559                         /* 10G Serdes */
2560                         tp = &phy_template_niu_10g_serdes;
2561                         break;
2562                 case NIU_FLAGS_XCVR_SERDES:
2563                         /* 1G Serdes */
2564                         tp = &phy_template_niu_1g_serdes;
2565                         break;
2566                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2567                         /* 10G Fiber */
2568                 default:
2569                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2570                                 tp = &phy_template_niu_10g_hotplug;
2571                                 if (np->port == 0)
2572                                         phy_addr_off = 8;
2573                                 if (np->port == 1)
2574                                         phy_addr_off = 12;
2575                         } else {
2576                                 tp = &phy_template_niu_10g_fiber;
2577                                 phy_addr_off += np->port;
2578                         }
2579                         break;
2580                 }
2581         } else {
2582                 switch (np->flags &
2583                         (NIU_FLAGS_10G |
2584                          NIU_FLAGS_FIBER |
2585                          NIU_FLAGS_XCVR_SERDES)) {
2586                 case 0:
2587                         /* 1G copper */
2588                         tp = &phy_template_1g_copper;
2589                         if (plat_type == PLAT_TYPE_VF_P0)
2590                                 phy_addr_off = 10;
2591                         else if (plat_type == PLAT_TYPE_VF_P1)
2592                                 phy_addr_off = 26;
2593
2594                         phy_addr_off += (np->port ^ 0x3);
2595                         break;
2596
2597                 case NIU_FLAGS_10G:
2598                         /* 10G copper */
2599                         tp = &phy_template_10g_copper;
2600                         break;
2601
2602                 case NIU_FLAGS_FIBER:
2603                         /* 1G fiber */
2604                         tp = &phy_template_1g_fiber;
2605                         break;
2606
2607                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2608                         /* 10G fiber */
2609                         tp = &phy_template_10g_fiber;
2610                         if (plat_type == PLAT_TYPE_VF_P0 ||
2611                             plat_type == PLAT_TYPE_VF_P1)
2612                                 phy_addr_off = 8;
2613                         phy_addr_off += np->port;
2614                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2615                                 tp = &phy_template_10g_fiber_hotplug;
2616                                 if (np->port == 0)
2617                                         phy_addr_off = 8;
2618                                 if (np->port == 1)
2619                                         phy_addr_off = 12;
2620                         }
2621                         break;
2622
2623                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2624                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2625                 case NIU_FLAGS_XCVR_SERDES:
2626                         switch(np->port) {
2627                         case 0:
2628                         case 1:
2629                                 tp = &phy_template_10g_serdes;
2630                                 break;
2631                         case 2:
2632                         case 3:
2633                                 tp = &phy_template_1g_rgmii;
2634                                 break;
2635                         default:
2636                                 return -EINVAL;
2637                                 break;
2638                         }
2639                         phy_addr_off = niu_atca_port_num[np->port];
2640                         break;
2641
2642                 default:
2643                         return -EINVAL;
2644                 }
2645         }
2646
2647         np->phy_ops = tp->ops;
2648         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2649
2650         return 0;
2651 }
2652
2653 static int niu_init_link(struct niu *np)
2654 {
2655         struct niu_parent *parent = np->parent;
2656         int err, ignore;
2657
2658         if (parent->plat_type == PLAT_TYPE_NIU) {
2659                 err = niu_xcvr_init(np);
2660                 if (err)
2661                         return err;
2662                 msleep(200);
2663         }
2664         err = niu_serdes_init(np);
2665         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2666                 return err;
2667         msleep(200);
2668         err = niu_xcvr_init(np);
2669         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2670                 niu_link_status(np, &ignore);
2671         return 0;
2672 }
2673
2674 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2675 {
2676         u16 reg0 = addr[4] << 8 | addr[5];
2677         u16 reg1 = addr[2] << 8 | addr[3];
2678         u16 reg2 = addr[0] << 8 | addr[1];
2679
2680         if (np->flags & NIU_FLAGS_XMAC) {
2681                 nw64_mac(XMAC_ADDR0, reg0);
2682                 nw64_mac(XMAC_ADDR1, reg1);
2683                 nw64_mac(XMAC_ADDR2, reg2);
2684         } else {
2685                 nw64_mac(BMAC_ADDR0, reg0);
2686                 nw64_mac(BMAC_ADDR1, reg1);
2687                 nw64_mac(BMAC_ADDR2, reg2);
2688         }
2689 }
2690
2691 static int niu_num_alt_addr(struct niu *np)
2692 {
2693         if (np->flags & NIU_FLAGS_XMAC)
2694                 return XMAC_NUM_ALT_ADDR;
2695         else
2696                 return BMAC_NUM_ALT_ADDR;
2697 }
2698
2699 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2700 {
2701         u16 reg0 = addr[4] << 8 | addr[5];
2702         u16 reg1 = addr[2] << 8 | addr[3];
2703         u16 reg2 = addr[0] << 8 | addr[1];
2704
2705         if (index >= niu_num_alt_addr(np))
2706                 return -EINVAL;
2707
2708         if (np->flags & NIU_FLAGS_XMAC) {
2709                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2710                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2711                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2712         } else {
2713                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2714                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2715                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2716         }
2717
2718         return 0;
2719 }
2720
2721 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2722 {
2723         unsigned long reg;
2724         u64 val, mask;
2725
2726         if (index >= niu_num_alt_addr(np))
2727                 return -EINVAL;
2728
2729         if (np->flags & NIU_FLAGS_XMAC) {
2730                 reg = XMAC_ADDR_CMPEN;
2731                 mask = 1 << index;
2732         } else {
2733                 reg = BMAC_ADDR_CMPEN;
2734                 mask = 1 << (index + 1);
2735         }
2736
2737         val = nr64_mac(reg);
2738         if (on)
2739                 val |= mask;
2740         else
2741                 val &= ~mask;
2742         nw64_mac(reg, val);
2743
2744         return 0;
2745 }
2746
2747 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2748                                    int num, int mac_pref)
2749 {
2750         u64 val = nr64_mac(reg);
2751         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2752         val |= num;
2753         if (mac_pref)
2754                 val |= HOST_INFO_MPR;
2755         nw64_mac(reg, val);
2756 }
2757
2758 static int __set_rdc_table_num(struct niu *np,
2759                                int xmac_index, int bmac_index,
2760                                int rdc_table_num, int mac_pref)
2761 {
2762         unsigned long reg;
2763
2764         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2765                 return -EINVAL;
2766         if (np->flags & NIU_FLAGS_XMAC)
2767                 reg = XMAC_HOST_INFO(xmac_index);
2768         else
2769                 reg = BMAC_HOST_INFO(bmac_index);
2770         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2771         return 0;
2772 }
2773
2774 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2775                                          int mac_pref)
2776 {
2777         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2778 }
2779
2780 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2781                                            int mac_pref)
2782 {
2783         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2784 }
2785
2786 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2787                                      int table_num, int mac_pref)
2788 {
2789         if (idx >= niu_num_alt_addr(np))
2790                 return -EINVAL;
2791         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2792 }
2793
2794 static u64 vlan_entry_set_parity(u64 reg_val)
2795 {
2796         u64 port01_mask;
2797         u64 port23_mask;
2798
2799         port01_mask = 0x00ff;
2800         port23_mask = 0xff00;
2801
2802         if (hweight64(reg_val & port01_mask) & 1)
2803                 reg_val |= ENET_VLAN_TBL_PARITY0;
2804         else
2805                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2806
2807         if (hweight64(reg_val & port23_mask) & 1)
2808                 reg_val |= ENET_VLAN_TBL_PARITY1;
2809         else
2810                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2811
2812         return reg_val;
2813 }
2814
2815 static void vlan_tbl_write(struct niu *np, unsigned long index,
2816                            int port, int vpr, int rdc_table)
2817 {
2818         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2819
2820         reg_val &= ~((ENET_VLAN_TBL_VPR |
2821                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2822                      ENET_VLAN_TBL_SHIFT(port));
2823         if (vpr)
2824                 reg_val |= (ENET_VLAN_TBL_VPR <<
2825                             ENET_VLAN_TBL_SHIFT(port));
2826         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2827
2828         reg_val = vlan_entry_set_parity(reg_val);
2829
2830         nw64(ENET_VLAN_TBL(index), reg_val);
2831 }
2832
2833 static void vlan_tbl_clear(struct niu *np)
2834 {
2835         int i;
2836
2837         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2838                 nw64(ENET_VLAN_TBL(i), 0);
2839 }
2840
2841 static int tcam_wait_bit(struct niu *np, u64 bit)
2842 {
2843         int limit = 1000;
2844
2845         while (--limit > 0) {
2846                 if (nr64(TCAM_CTL) & bit)
2847                         break;
2848                 udelay(1);
2849         }
2850         if (limit < 0)
2851                 return -ENODEV;
2852
2853         return 0;
2854 }
2855
2856 static int tcam_flush(struct niu *np, int index)
2857 {
2858         nw64(TCAM_KEY_0, 0x00);
2859         nw64(TCAM_KEY_MASK_0, 0xff);
2860         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2861
2862         return tcam_wait_bit(np, TCAM_CTL_STAT);
2863 }
2864
2865 #if 0
2866 static int tcam_read(struct niu *np, int index,
2867                      u64 *key, u64 *mask)
2868 {
2869         int err;
2870
2871         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2872         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2873         if (!err) {
2874                 key[0] = nr64(TCAM_KEY_0);
2875                 key[1] = nr64(TCAM_KEY_1);
2876                 key[2] = nr64(TCAM_KEY_2);
2877                 key[3] = nr64(TCAM_KEY_3);
2878                 mask[0] = nr64(TCAM_KEY_MASK_0);
2879                 mask[1] = nr64(TCAM_KEY_MASK_1);
2880                 mask[2] = nr64(TCAM_KEY_MASK_2);
2881                 mask[3] = nr64(TCAM_KEY_MASK_3);
2882         }
2883         return err;
2884 }
2885 #endif
2886
2887 static int tcam_write(struct niu *np, int index,
2888                       u64 *key, u64 *mask)
2889 {
2890         nw64(TCAM_KEY_0, key[0]);
2891         nw64(TCAM_KEY_1, key[1]);
2892         nw64(TCAM_KEY_2, key[2]);
2893         nw64(TCAM_KEY_3, key[3]);
2894         nw64(TCAM_KEY_MASK_0, mask[0]);
2895         nw64(TCAM_KEY_MASK_1, mask[1]);
2896         nw64(TCAM_KEY_MASK_2, mask[2]);
2897         nw64(TCAM_KEY_MASK_3, mask[3]);
2898         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2899
2900         return tcam_wait_bit(np, TCAM_CTL_STAT);
2901 }
2902
2903 #if 0
2904 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2905 {
2906         int err;
2907
2908         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2909         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2910         if (!err)
2911                 *data = nr64(TCAM_KEY_1);
2912
2913         return err;
2914 }
2915 #endif
2916
2917 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2918 {
2919         nw64(TCAM_KEY_1, assoc_data);
2920         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2921
2922         return tcam_wait_bit(np, TCAM_CTL_STAT);
2923 }
2924
2925 static void tcam_enable(struct niu *np, int on)
2926 {
2927         u64 val = nr64(FFLP_CFG_1);
2928
2929         if (on)
2930                 val &= ~FFLP_CFG_1_TCAM_DIS;
2931         else
2932                 val |= FFLP_CFG_1_TCAM_DIS;
2933         nw64(FFLP_CFG_1, val);
2934 }
2935
2936 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2937 {
2938         u64 val = nr64(FFLP_CFG_1);
2939
2940         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2941                  FFLP_CFG_1_CAMLAT |
2942                  FFLP_CFG_1_CAMRATIO);
2943         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2944         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2945         nw64(FFLP_CFG_1, val);
2946
2947         val = nr64(FFLP_CFG_1);
2948         val |= FFLP_CFG_1_FFLPINITDONE;
2949         nw64(FFLP_CFG_1, val);
2950 }
2951
2952 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2953                                       int on)
2954 {
2955         unsigned long reg;
2956         u64 val;
2957
2958         if (class < CLASS_CODE_ETHERTYPE1 ||
2959             class > CLASS_CODE_ETHERTYPE2)
2960                 return -EINVAL;
2961
2962         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2963         val = nr64(reg);
2964         if (on)
2965                 val |= L2_CLS_VLD;
2966         else
2967                 val &= ~L2_CLS_VLD;
2968         nw64(reg, val);
2969
2970         return 0;
2971 }
2972
2973 #if 0
2974 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2975                                    u64 ether_type)
2976 {
2977         unsigned long reg;
2978         u64 val;
2979
2980         if (class < CLASS_CODE_ETHERTYPE1 ||
2981             class > CLASS_CODE_ETHERTYPE2 ||
2982             (ether_type & ~(u64)0xffff) != 0)
2983                 return -EINVAL;
2984
2985         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2986         val = nr64(reg);
2987         val &= ~L2_CLS_ETYPE;
2988         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2989         nw64(reg, val);
2990
2991         return 0;
2992 }
2993 #endif
2994
2995 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2996                                      int on)
2997 {
2998         unsigned long reg;
2999         u64 val;
3000
3001         if (class < CLASS_CODE_USER_PROG1 ||
3002             class > CLASS_CODE_USER_PROG4)
3003                 return -EINVAL;
3004
3005         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3006         val = nr64(reg);
3007         if (on)
3008                 val |= L3_CLS_VALID;
3009         else
3010                 val &= ~L3_CLS_VALID;
3011         nw64(reg, val);
3012
3013         return 0;
3014 }
3015
3016 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
3017                                   int ipv6, u64 protocol_id,
3018                                   u64 tos_mask, u64 tos_val)
3019 {
3020         unsigned long reg;
3021         u64 val;
3022
3023         if (class < CLASS_CODE_USER_PROG1 ||
3024             class > CLASS_CODE_USER_PROG4 ||
3025             (protocol_id & ~(u64)0xff) != 0 ||
3026             (tos_mask & ~(u64)0xff) != 0 ||
3027             (tos_val & ~(u64)0xff) != 0)
3028                 return -EINVAL;
3029
3030         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3031         val = nr64(reg);
3032         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3033                  L3_CLS_TOSMASK | L3_CLS_TOS);
3034         if (ipv6)
3035                 val |= L3_CLS_IPVER;
3036         val |= (protocol_id << L3_CLS_PID_SHIFT);
3037         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3038         val |= (tos_val << L3_CLS_TOS_SHIFT);
3039         nw64(reg, val);
3040
3041         return 0;
3042 }
3043
3044 static int tcam_early_init(struct niu *np)
3045 {
3046         unsigned long i;
3047         int err;
3048
3049         tcam_enable(np, 0);
3050         tcam_set_lat_and_ratio(np,
3051                                DEFAULT_TCAM_LATENCY,
3052                                DEFAULT_TCAM_ACCESS_RATIO);
3053         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3054                 err = tcam_user_eth_class_enable(np, i, 0);
3055                 if (err)
3056                         return err;
3057         }
3058         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3059                 err = tcam_user_ip_class_enable(np, i, 0);
3060                 if (err)
3061                         return err;
3062         }
3063
3064         return 0;
3065 }
3066
3067 static int tcam_flush_all(struct niu *np)
3068 {
3069         unsigned long i;
3070
3071         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3072                 int err = tcam_flush(np, i);
3073                 if (err)
3074                         return err;
3075         }
3076         return 0;
3077 }
3078
3079 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3080 {
3081         return ((u64)index | (num_entries == 1 ?
3082                               HASH_TBL_ADDR_AUTOINC : 0));
3083 }
3084
3085 #if 0
3086 static int hash_read(struct niu *np, unsigned long partition,
3087                      unsigned long index, unsigned long num_entries,
3088                      u64 *data)
3089 {
3090         u64 val = hash_addr_regval(index, num_entries);
3091         unsigned long i;
3092
3093         if (partition >= FCRAM_NUM_PARTITIONS ||
3094             index + num_entries > FCRAM_SIZE)
3095                 return -EINVAL;
3096
3097         nw64(HASH_TBL_ADDR(partition), val);
3098         for (i = 0; i < num_entries; i++)
3099                 data[i] = nr64(HASH_TBL_DATA(partition));
3100
3101         return 0;
3102 }
3103 #endif
3104
3105 static int hash_write(struct niu *np, unsigned long partition,
3106                       unsigned long index, unsigned long num_entries,
3107                       u64 *data)
3108 {
3109         u64 val = hash_addr_regval(index, num_entries);
3110         unsigned long i;
3111
3112         if (partition >= FCRAM_NUM_PARTITIONS ||
3113             index + (num_entries * 8) > FCRAM_SIZE)
3114                 return -EINVAL;
3115
3116         nw64(HASH_TBL_ADDR(partition), val);
3117         for (i = 0; i < num_entries; i++)
3118                 nw64(HASH_TBL_DATA(partition), data[i]);
3119
3120         return 0;
3121 }
3122
3123 static void fflp_reset(struct niu *np)
3124 {
3125         u64 val;
3126
3127         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3128         udelay(10);
3129         nw64(FFLP_CFG_1, 0);
3130
3131         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3132         nw64(FFLP_CFG_1, val);
3133 }
3134
3135 static void fflp_set_timings(struct niu *np)
3136 {
3137         u64 val = nr64(FFLP_CFG_1);
3138
3139         val &= ~FFLP_CFG_1_FFLPINITDONE;
3140         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3141         nw64(FFLP_CFG_1, val);
3142
3143         val = nr64(FFLP_CFG_1);
3144         val |= FFLP_CFG_1_FFLPINITDONE;
3145         nw64(FFLP_CFG_1, val);
3146
3147         val = nr64(FCRAM_REF_TMR);
3148         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3149         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3150         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3151         nw64(FCRAM_REF_TMR, val);
3152 }
3153
3154 static int fflp_set_partition(struct niu *np, u64 partition,
3155                               u64 mask, u64 base, int enable)
3156 {
3157         unsigned long reg;
3158         u64 val;
3159
3160         if (partition >= FCRAM_NUM_PARTITIONS ||
3161             (mask & ~(u64)0x1f) != 0 ||
3162             (base & ~(u64)0x1f) != 0)
3163                 return -EINVAL;
3164
3165         reg = FLW_PRT_SEL(partition);
3166
3167         val = nr64(reg);
3168         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3169         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3170         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3171         if (enable)
3172                 val |= FLW_PRT_SEL_EXT;
3173         nw64(reg, val);
3174
3175         return 0;
3176 }
3177
3178 static int fflp_disable_all_partitions(struct niu *np)
3179 {
3180         unsigned long i;
3181
3182         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3183                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3184                 if (err)
3185                         return err;
3186         }
3187         return 0;
3188 }
3189
3190 static void fflp_llcsnap_enable(struct niu *np, int on)
3191 {
3192         u64 val = nr64(FFLP_CFG_1);
3193
3194         if (on)
3195                 val |= FFLP_CFG_1_LLCSNAP;
3196         else
3197                 val &= ~FFLP_CFG_1_LLCSNAP;
3198         nw64(FFLP_CFG_1, val);
3199 }
3200
3201 static void fflp_errors_enable(struct niu *np, int on)
3202 {
3203         u64 val = nr64(FFLP_CFG_1);
3204
3205         if (on)
3206                 val &= ~FFLP_CFG_1_ERRORDIS;
3207         else
3208                 val |= FFLP_CFG_1_ERRORDIS;
3209         nw64(FFLP_CFG_1, val);
3210 }
3211
3212 static int fflp_hash_clear(struct niu *np)
3213 {
3214         struct fcram_hash_ipv4 ent;
3215         unsigned long i;
3216
3217         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3218         memset(&ent, 0, sizeof(ent));
3219         ent.header = HASH_HEADER_EXT;
3220
3221         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3222                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3223                 if (err)
3224                         return err;
3225         }
3226         return 0;
3227 }
3228
3229 static int fflp_early_init(struct niu *np)
3230 {
3231         struct niu_parent *parent;
3232         unsigned long flags;
3233         int err;
3234
3235         niu_lock_parent(np, flags);
3236
3237         parent = np->parent;
3238         err = 0;
3239         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3240                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3241                        np->port);
3242                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3243                         fflp_reset(np);
3244                         fflp_set_timings(np);
3245                         err = fflp_disable_all_partitions(np);
3246                         if (err) {
3247                                 niudbg(PROBE, "fflp_disable_all_partitions "
3248                                        "failed, err=%d\n", err);
3249                                 goto out;
3250                         }
3251                 }
3252
3253                 err = tcam_early_init(np);
3254                 if (err) {
3255                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3256                                err);
3257                         goto out;
3258                 }
3259                 fflp_llcsnap_enable(np, 1);
3260                 fflp_errors_enable(np, 0);
3261                 nw64(H1POLY, 0);
3262                 nw64(H2POLY, 0);
3263
3264                 err = tcam_flush_all(np);
3265                 if (err) {
3266                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3267                                err);
3268                         goto out;
3269                 }
3270                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3271                         err = fflp_hash_clear(np);
3272                         if (err) {
3273                                 niudbg(PROBE, "fflp_hash_clear failed, "
3274                                        "err=%d\n", err);
3275                                 goto out;
3276                         }
3277                 }
3278
3279                 vlan_tbl_clear(np);
3280
3281                 niudbg(PROBE, "fflp_early_init: Success\n");
3282                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3283         }
3284 out:
3285         niu_unlock_parent(np, flags);
3286         return err;
3287 }
3288
3289 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3290 {
3291         if (class_code < CLASS_CODE_USER_PROG1 ||
3292             class_code > CLASS_CODE_SCTP_IPV6)
3293                 return -EINVAL;
3294
3295         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3296         return 0;
3297 }
3298
3299 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3300 {
3301         if (class_code < CLASS_CODE_USER_PROG1 ||
3302             class_code > CLASS_CODE_SCTP_IPV6)
3303                 return -EINVAL;
3304
3305         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3306         return 0;
3307 }
3308
3309 /* Entries for the ports are interleaved in the TCAM */
3310 static u16 tcam_get_index(struct niu *np, u16 idx)
3311 {
3312         /* One entry reserved for IP fragment rule */
3313         if (idx >= (np->clas.tcam_sz - 1))
3314                 idx = 0;
3315         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3316 }
3317
3318 static u16 tcam_get_size(struct niu *np)
3319 {
3320         /* One entry reserved for IP fragment rule */
3321         return np->clas.tcam_sz - 1;
3322 }
3323
3324 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3325 {
3326         /* One entry reserved for IP fragment rule */
3327         return np->clas.tcam_valid_entries - 1;
3328 }
3329
3330 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3331                               u32 offset, u32 size)
3332 {
3333         int i = skb_shinfo(skb)->nr_frags;
3334         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3335
3336         frag->page = page;
3337         frag->page_offset = offset;
3338         frag->size = size;
3339
3340         skb->len += size;
3341         skb->data_len += size;
3342         skb->truesize += size;
3343
3344         skb_shinfo(skb)->nr_frags = i + 1;
3345 }
3346
3347 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3348 {
3349         a >>= PAGE_SHIFT;
3350         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3351
3352         return (a & (MAX_RBR_RING_SIZE - 1));
3353 }
3354
3355 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3356                                     struct page ***link)
3357 {
3358         unsigned int h = niu_hash_rxaddr(rp, addr);
3359         struct page *p, **pp;
3360
3361         addr &= PAGE_MASK;
3362         pp = &rp->rxhash[h];
3363         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3364                 if (p->index == addr) {
3365                         *link = pp;
3366                         break;
3367                 }
3368         }
3369
3370         return p;
3371 }
3372
3373 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3374 {
3375         unsigned int h = niu_hash_rxaddr(rp, base);
3376
3377         page->index = base;
3378         page->mapping = (struct address_space *) rp->rxhash[h];
3379         rp->rxhash[h] = page;
3380 }
3381
3382 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3383                             gfp_t mask, int start_index)
3384 {
3385         struct page *page;
3386         u64 addr;
3387         int i;
3388
3389         page = alloc_page(mask);
3390         if (!page)
3391                 return -ENOMEM;
3392
3393         addr = np->ops->map_page(np->device, page, 0,
3394                                  PAGE_SIZE, DMA_FROM_DEVICE);
3395
3396         niu_hash_page(rp, page, addr);
3397         if (rp->rbr_blocks_per_page > 1)
3398                 atomic_add(rp->rbr_blocks_per_page - 1,
3399                            &compound_head(page)->_count);
3400
3401         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3402                 __le32 *rbr = &rp->rbr[start_index + i];
3403
3404                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3405                 addr += rp->rbr_block_size;
3406         }
3407
3408         return 0;
3409 }
3410
3411 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3412 {
3413         int index = rp->rbr_index;
3414
3415         rp->rbr_pending++;
3416         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3417                 int err = niu_rbr_add_page(np, rp, mask, index);
3418
3419                 if (unlikely(err)) {
3420                         rp->rbr_pending--;
3421                         return;
3422                 }
3423
3424                 rp->rbr_index += rp->rbr_blocks_per_page;
3425                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3426                 if (rp->rbr_index == rp->rbr_table_size)
3427                         rp->rbr_index = 0;
3428
3429                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3430                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3431                         rp->rbr_pending = 0;
3432                 }
3433         }
3434 }
3435
3436 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3437 {
3438         unsigned int index = rp->rcr_index;
3439         int num_rcr = 0;
3440
3441         rp->rx_dropped++;
3442         while (1) {
3443                 struct page *page, **link;
3444                 u64 addr, val;
3445                 u32 rcr_size;
3446
3447                 num_rcr++;
3448
3449                 val = le64_to_cpup(&rp->rcr[index]);
3450                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3451                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3452                 page = niu_find_rxpage(rp, addr, &link);
3453
3454                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3455                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3456                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3457                         *link = (struct page *) page->mapping;
3458                         np->ops->unmap_page(np->device, page->index,
3459                                             PAGE_SIZE, DMA_FROM_DEVICE);
3460                         page->index = 0;
3461                         page->mapping = NULL;
3462                         __free_page(page);
3463                         rp->rbr_refill_pending++;
3464                 }
3465
3466                 index = NEXT_RCR(rp, index);
3467                 if (!(val & RCR_ENTRY_MULTI))
3468                         break;
3469
3470         }
3471         rp->rcr_index = index;
3472
3473         return num_rcr;
3474 }
3475
3476 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3477                               struct rx_ring_info *rp)
3478 {
3479         unsigned int index = rp->rcr_index;
3480         struct sk_buff *skb;
3481         int len, num_rcr;
3482
3483         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3484         if (unlikely(!skb))
3485                 return niu_rx_pkt_ignore(np, rp);
3486
3487         num_rcr = 0;
3488         while (1) {
3489                 struct page *page, **link;
3490                 u32 rcr_size, append_size;
3491                 u64 addr, val, off;
3492
3493                 num_rcr++;
3494
3495                 val = le64_to_cpup(&rp->rcr[index]);
3496
3497                 len = (val & RCR_ENTRY_L2_LEN) >>
3498                         RCR_ENTRY_L2_LEN_SHIFT;
3499                 len -= ETH_FCS_LEN;
3500
3501                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3502                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3503                 page = niu_find_rxpage(rp, addr, &link);
3504
3505                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3506                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3507
3508                 off = addr & ~PAGE_MASK;
3509                 append_size = rcr_size;
3510                 if (num_rcr == 1) {
3511                         int ptype;
3512
3513                         off += 2;
3514                         append_size -= 2;
3515
3516                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3517                         if ((ptype == RCR_PKT_TYPE_TCP ||
3518                              ptype == RCR_PKT_TYPE_UDP) &&
3519                             !(val & (RCR_ENTRY_NOPORT |
3520                                      RCR_ENTRY_ERROR)))
3521                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3522                         else
3523                                 skb->ip_summed = CHECKSUM_NONE;
3524                 }
3525                 if (!(val & RCR_ENTRY_MULTI))
3526                         append_size = len - skb->len;
3527
3528                 niu_rx_skb_append(skb, page, off, append_size);
3529                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3530                         *link = (struct page *) page->mapping;
3531                         np->ops->unmap_page(np->device, page->index,
3532                                             PAGE_SIZE, DMA_FROM_DEVICE);
3533                         page->index = 0;
3534                         page->mapping = NULL;
3535                         rp->rbr_refill_pending++;
3536                 } else
3537                         get_page(page);
3538
3539                 index = NEXT_RCR(rp, index);
3540                 if (!(val & RCR_ENTRY_MULTI))
3541                         break;
3542
3543         }
3544         rp->rcr_index = index;
3545
3546         skb_reserve(skb, NET_IP_ALIGN);
3547         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3548
3549         rp->rx_packets++;
3550         rp->rx_bytes += skb->len;
3551
3552         skb->protocol = eth_type_trans(skb, np->dev);
3553         skb_record_rx_queue(skb, rp->rx_channel);
3554         napi_gro_receive(napi, skb);
3555
3556         return num_rcr;
3557 }
3558
3559 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3560 {
3561         int blocks_per_page = rp->rbr_blocks_per_page;
3562         int err, index = rp->rbr_index;
3563
3564         err = 0;
3565         while (index < (rp->rbr_table_size - blocks_per_page)) {
3566                 err = niu_rbr_add_page(np, rp, mask, index);
3567                 if (err)
3568                         break;
3569
3570                 index += blocks_per_page;
3571         }
3572
3573         rp->rbr_index = index;
3574         return err;
3575 }
3576
3577 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3578 {
3579         int i;
3580
3581         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3582                 struct page *page;
3583
3584                 page = rp->rxhash[i];
3585                 while (page) {
3586                         struct page *next = (struct page *) page->mapping;
3587                         u64 base = page->index;
3588
3589                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3590                                             DMA_FROM_DEVICE);
3591                         page->index = 0;
3592                         page->mapping = NULL;
3593
3594                         __free_page(page);
3595
3596                         page = next;
3597                 }
3598         }
3599
3600         for (i = 0; i < rp->rbr_table_size; i++)
3601                 rp->rbr[i] = cpu_to_le32(0);
3602         rp->rbr_index = 0;
3603 }
3604
3605 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3606 {
3607         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3608         struct sk_buff *skb = tb->skb;
3609         struct tx_pkt_hdr *tp;
3610         u64 tx_flags;
3611         int i, len;
3612
3613         tp = (struct tx_pkt_hdr *) skb->data;
3614         tx_flags = le64_to_cpup(&tp->flags);
3615
3616         rp->tx_packets++;
3617         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3618                          ((tx_flags & TXHDR_PAD) / 2));
3619
3620         len = skb_headlen(skb);
3621         np->ops->unmap_single(np->device, tb->mapping,
3622                               len, DMA_TO_DEVICE);
3623
3624         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3625                 rp->mark_pending--;
3626
3627         tb->skb = NULL;
3628         do {
3629                 idx = NEXT_TX(rp, idx);
3630                 len -= MAX_TX_DESC_LEN;
3631         } while (len > 0);
3632
3633         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3634                 tb = &rp->tx_buffs[idx];
3635                 BUG_ON(tb->skb != NULL);
3636                 np->ops->unmap_page(np->device, tb->mapping,
3637                                     skb_shinfo(skb)->frags[i].size,
3638                                     DMA_TO_DEVICE);
3639                 idx = NEXT_TX(rp, idx);
3640         }
3641
3642         dev_kfree_skb(skb);
3643
3644         return idx;
3645 }
3646
3647 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3648
3649 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3650 {
3651         struct netdev_queue *txq;
3652         u16 pkt_cnt, tmp;
3653         int cons, index;
3654         u64 cs;
3655
3656         index = (rp - np->tx_rings);
3657         txq = netdev_get_tx_queue(np->dev, index);
3658
3659         cs = rp->tx_cs;
3660         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3661                 goto out;
3662
3663         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3664         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3665                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3666
3667         rp->last_pkt_cnt = tmp;
3668
3669         cons = rp->cons;
3670
3671         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3672                np->dev->name, pkt_cnt, cons);
3673
3674         while (pkt_cnt--)
3675                 cons = release_tx_packet(np, rp, cons);
3676
3677         rp->cons = cons;
3678         smp_mb();
3679
3680 out:
3681         if (unlikely(netif_tx_queue_stopped(txq) &&
3682                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3683                 __netif_tx_lock(txq, smp_processor_id());
3684                 if (netif_tx_queue_stopped(txq) &&
3685                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3686                         netif_tx_wake_queue(txq);
3687                 __netif_tx_unlock(txq);
3688         }
3689 }
3690
3691 static inline void niu_sync_rx_discard_stats(struct niu *np,
3692                                              struct rx_ring_info *rp,
3693                                              const int limit)
3694 {
3695         /* This elaborate scheme is needed for reading the RX discard
3696          * counters, as they are only 16-bit and can overflow quickly,
3697          * and because the overflow indication bit is not usable as
3698          * the counter value does not wrap, but remains at max value
3699          * 0xFFFF.
3700          *
3701          * In theory and in practice counters can be lost in between
3702          * reading nr64() and clearing the counter nw64().  For this
3703          * reason, the number of counter clearings nw64() is
3704          * limited/reduced though the limit parameter.
3705          */
3706         int rx_channel = rp->rx_channel;
3707         u32 misc, wred;
3708
3709         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3710          * following discard events: IPP (Input Port Process),
3711          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3712          * Block Ring) prefetch buffer is empty.
3713          */
3714         misc = nr64(RXMISC(rx_channel));
3715         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3716                 nw64(RXMISC(rx_channel), 0);
3717                 rp->rx_errors += misc & RXMISC_COUNT;
3718
3719                 if (unlikely(misc & RXMISC_OFLOW))
3720                         dev_err(np->device, "rx-%d: Counter overflow "
3721                                 "RXMISC discard\n", rx_channel);
3722
3723                 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3724                        np->dev->name, rx_channel, misc, misc-limit);
3725         }
3726
3727         /* WRED (Weighted Random Early Discard) by hardware */
3728         wred = nr64(RED_DIS_CNT(rx_channel));
3729         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3730                 nw64(RED_DIS_CNT(rx_channel), 0);
3731                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3732
3733                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3734                         dev_err(np->device, "rx-%d: Counter overflow "
3735                                 "WRED discard\n", rx_channel);
3736
3737                 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3738                        np->dev->name, rx_channel, wred, wred-limit);
3739         }
3740 }
3741
3742 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3743                        struct rx_ring_info *rp, int budget)
3744 {
3745         int qlen, rcr_done = 0, work_done = 0;
3746         struct rxdma_mailbox *mbox = rp->mbox;
3747         u64 stat;
3748
3749 #if 1
3750         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3751         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3752 #else
3753         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3754         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3755 #endif
3756         mbox->rx_dma_ctl_stat = 0;
3757         mbox->rcrstat_a = 0;
3758
3759         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3760                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3761
3762         rcr_done = work_done = 0;
3763         qlen = min(qlen, budget);
3764         while (work_done < qlen) {
3765                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3766                 work_done++;
3767         }
3768
3769         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3770                 unsigned int i;
3771
3772                 for (i = 0; i < rp->rbr_refill_pending; i++)
3773                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3774                 rp->rbr_refill_pending = 0;
3775         }
3776
3777         stat = (RX_DMA_CTL_STAT_MEX |
3778                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3779                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3780
3781         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3782
3783         /* Only sync discards stats when qlen indicate potential for drops */
3784         if (qlen > 10)
3785                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3786
3787         return work_done;
3788 }
3789
3790 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3791 {
3792         u64 v0 = lp->v0;
3793         u32 tx_vec = (v0 >> 32);
3794         u32 rx_vec = (v0 & 0xffffffff);
3795         int i, work_done = 0;
3796
3797         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3798                np->dev->name, (unsigned long long) v0);
3799
3800         for (i = 0; i < np->num_tx_rings; i++) {
3801                 struct tx_ring_info *rp = &np->tx_rings[i];
3802                 if (tx_vec & (1 << rp->tx_channel))
3803                         niu_tx_work(np, rp);
3804                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3805         }
3806
3807         for (i = 0; i < np->num_rx_rings; i++) {
3808                 struct rx_ring_info *rp = &np->rx_rings[i];
3809
3810                 if (rx_vec & (1 << rp->rx_channel)) {
3811                         int this_work_done;
3812
3813                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3814                                                      budget);
3815
3816                         budget -= this_work_done;
3817                         work_done += this_work_done;
3818                 }
3819                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3820         }
3821
3822         return work_done;
3823 }
3824
3825 static int niu_poll(struct napi_struct *napi, int budget)
3826 {
3827         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3828         struct niu *np = lp->np;
3829         int work_done;
3830
3831         work_done = niu_poll_core(np, lp, budget);
3832
3833         if (work_done < budget) {
3834                 napi_complete(napi);
3835                 niu_ldg_rearm(np, lp, 1);
3836         }
3837         return work_done;
3838 }
3839
3840 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3841                                   u64 stat)
3842 {
3843         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3844                 np->dev->name, rp->rx_channel);
3845
3846         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3847                 printk("RBR_TMOUT ");
3848         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3849                 printk("RSP_CNT ");
3850         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3851                 printk("BYTE_EN_BUS ");
3852         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3853                 printk("RSP_DAT ");
3854         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3855                 printk("RCR_ACK ");
3856         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3857                 printk("RCR_SHA_PAR ");
3858         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3859                 printk("RBR_PRE_PAR ");
3860         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3861                 printk("CONFIG ");
3862         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3863                 printk("RCRINCON ");
3864         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3865                 printk("RCRFULL ");
3866         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3867                 printk("RBRFULL ");
3868         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3869                 printk("RBRLOGPAGE ");
3870         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3871                 printk("CFIGLOGPAGE ");
3872         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3873                 printk("DC_FIDO ");
3874
3875         printk(")\n");
3876 }
3877
3878 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3879 {
3880         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3881         int err = 0;
3882
3883
3884         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3885                     RX_DMA_CTL_STAT_PORT_FATAL))
3886                 err = -EINVAL;
3887
3888         if (err) {
3889                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3890                         np->dev->name, rp->rx_channel,
3891                         (unsigned long long) stat);
3892
3893                 niu_log_rxchan_errors(np, rp, stat);
3894         }
3895
3896         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3897              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3898
3899         return err;
3900 }
3901
3902 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3903                                   u64 cs)
3904 {
3905         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3906                 np->dev->name, rp->tx_channel);
3907
3908         if (cs & TX_CS_MBOX_ERR)
3909                 printk("MBOX ");
3910         if (cs & TX_CS_PKT_SIZE_ERR)
3911                 printk("PKT_SIZE ");
3912         if (cs & TX_CS_TX_RING_OFLOW)
3913                 printk("TX_RING_OFLOW ");
3914         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3915                 printk("PREF_BUF_PAR ");
3916         if (cs & TX_CS_NACK_PREF)
3917                 printk("NACK_PREF ");
3918         if (cs & TX_CS_NACK_PKT_RD)
3919                 printk("NACK_PKT_RD ");
3920         if (cs & TX_CS_CONF_PART_ERR)
3921                 printk("CONF_PART ");
3922         if (cs & TX_CS_PKT_PRT_ERR)
3923                 printk("PKT_PTR ");
3924
3925         printk(")\n");
3926 }
3927
3928 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3929 {
3930         u64 cs, logh, logl;
3931
3932         cs = nr64(TX_CS(rp->tx_channel));
3933         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3934         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3935
3936         dev_err(np->device, PFX "%s: TX channel %u error, "
3937                 "cs[%llx] logh[%llx] logl[%llx]\n",
3938                 np->dev->name, rp->tx_channel,
3939                 (unsigned long long) cs,
3940                 (unsigned long long) logh,
3941                 (unsigned long long) logl);
3942
3943         niu_log_txchan_errors(np, rp, cs);
3944
3945         return -ENODEV;
3946 }
3947
3948 static int niu_mif_interrupt(struct niu *np)
3949 {
3950         u64 mif_status = nr64(MIF_STATUS);
3951         int phy_mdint = 0;
3952
3953         if (np->flags & NIU_FLAGS_XMAC) {
3954                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3955
3956                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3957                         phy_mdint = 1;
3958         }
3959
3960         dev_err(np->device, PFX "%s: MIF interrupt, "
3961                 "stat[%llx] phy_mdint(%d)\n",
3962                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3963
3964         return -ENODEV;
3965 }
3966
3967 static void niu_xmac_interrupt(struct niu *np)
3968 {
3969         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3970         u64 val;
3971
3972         val = nr64_mac(XTXMAC_STATUS);
3973         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3974                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3975         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3976                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3977         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3978                 mp->tx_fifo_errors++;
3979         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3980                 mp->tx_overflow_errors++;
3981         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3982                 mp->tx_max_pkt_size_errors++;
3983         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3984                 mp->tx_underflow_errors++;
3985
3986         val = nr64_mac(XRXMAC_STATUS);
3987         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3988                 mp->rx_local_faults++;
3989         if (val & XRXMAC_STATUS_RFLT_DET)
3990                 mp->rx_remote_faults++;
3991         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3992                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3993         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3994                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3995         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3996                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3997         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3998                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3999         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
4000                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
4001         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
4002                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
4003         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
4004                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
4005         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
4006                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
4007         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
4008                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
4009         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
4010                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
4011         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
4012                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
4013         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
4014                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
4015         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
4016                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
4017         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
4018                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
4019         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
4020                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
4021         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
4022                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
4023         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
4024                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
4025         if (val & XRXMAC_STATUS_RXUFLOW)
4026                 mp->rx_underflows++;
4027         if (val & XRXMAC_STATUS_RXOFLOW)
4028                 mp->rx_overflows++;
4029
4030         val = nr64_mac(XMAC_FC_STAT);
4031         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4032                 mp->pause_off_state++;
4033         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4034                 mp->pause_on_state++;
4035         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4036                 mp->pause_received++;
4037 }
4038
4039 static void niu_bmac_interrupt(struct niu *np)
4040 {
4041         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4042         u64 val;
4043
4044         val = nr64_mac(BTXMAC_STATUS);
4045         if (val & BTXMAC_STATUS_UNDERRUN)
4046                 mp->tx_underflow_errors++;
4047         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4048                 mp->tx_max_pkt_size_errors++;
4049         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4050                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4051         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4052                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4053
4054         val = nr64_mac(BRXMAC_STATUS);
4055         if (val & BRXMAC_STATUS_OVERFLOW)
4056                 mp->rx_overflows++;
4057         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4058                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4059         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4060                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4061         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4062                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4063         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4064                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4065
4066         val = nr64_mac(BMAC_CTRL_STATUS);
4067         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4068                 mp->pause_off_state++;
4069         if (val & BMAC_CTRL_STATUS_PAUSE)
4070                 mp->pause_on_state++;
4071         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4072                 mp->pause_received++;
4073 }
4074
4075 static int niu_mac_interrupt(struct niu *np)
4076 {
4077         if (np->flags & NIU_FLAGS_XMAC)
4078                 niu_xmac_interrupt(np);
4079         else
4080                 niu_bmac_interrupt(np);
4081
4082         return 0;
4083 }
4084
4085 static void niu_log_device_error(struct niu *np, u64 stat)
4086 {
4087         dev_err(np->device, PFX "%s: Core device errors ( ",
4088                 np->dev->name);
4089
4090         if (stat & SYS_ERR_MASK_META2)
4091                 printk("META2 ");
4092         if (stat & SYS_ERR_MASK_META1)
4093                 printk("META1 ");
4094         if (stat & SYS_ERR_MASK_PEU)
4095                 printk("PEU ");
4096         if (stat & SYS_ERR_MASK_TXC)
4097                 printk("TXC ");
4098         if (stat & SYS_ERR_MASK_RDMC)
4099                 printk("RDMC ");
4100         if (stat & SYS_ERR_MASK_TDMC)
4101                 printk("TDMC ");
4102         if (stat & SYS_ERR_MASK_ZCP)
4103                 printk("ZCP ");
4104         if (stat & SYS_ERR_MASK_FFLP)
4105                 printk("FFLP ");
4106         if (stat & SYS_ERR_MASK_IPP)
4107                 printk("IPP ");
4108         if (stat & SYS_ERR_MASK_MAC)
4109                 printk("MAC ");
4110         if (stat & SYS_ERR_MASK_SMX)
4111                 printk("SMX ");
4112
4113         printk(")\n");
4114 }
4115
4116 static int niu_device_error(struct niu *np)
4117 {
4118         u64 stat = nr64(SYS_ERR_STAT);
4119
4120         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4121                 np->dev->name, (unsigned long long) stat);
4122
4123         niu_log_device_error(np, stat);
4124
4125         return -ENODEV;
4126 }
4127
4128 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4129                               u64 v0, u64 v1, u64 v2)
4130 {
4131
4132         int i, err = 0;
4133
4134         lp->v0 = v0;
4135         lp->v1 = v1;
4136         lp->v2 = v2;
4137
4138         if (v1 & 0x00000000ffffffffULL) {
4139                 u32 rx_vec = (v1 & 0xffffffff);
4140
4141                 for (i = 0; i < np->num_rx_rings; i++) {
4142                         struct rx_ring_info *rp = &np->rx_rings[i];
4143
4144                         if (rx_vec & (1 << rp->rx_channel)) {
4145                                 int r = niu_rx_error(np, rp);
4146                                 if (r) {
4147                                         err = r;
4148                                 } else {
4149                                         if (!v0)
4150                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4151                                                      RX_DMA_CTL_STAT_MEX);
4152                                 }
4153                         }
4154                 }
4155         }
4156         if (v1 & 0x7fffffff00000000ULL) {
4157                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4158
4159                 for (i = 0; i < np->num_tx_rings; i++) {
4160                         struct tx_ring_info *rp = &np->tx_rings[i];
4161
4162                         if (tx_vec & (1 << rp->tx_channel)) {
4163                                 int r = niu_tx_error(np, rp);
4164                                 if (r)
4165                                         err = r;
4166                         }
4167                 }
4168         }
4169         if ((v0 | v1) & 0x8000000000000000ULL) {
4170                 int r = niu_mif_interrupt(np);
4171                 if (r)
4172                         err = r;
4173         }
4174         if (v2) {
4175                 if (v2 & 0x01ef) {
4176                         int r = niu_mac_interrupt(np);
4177                         if (r)
4178                                 err = r;
4179                 }
4180                 if (v2 & 0x0210) {
4181                         int r = niu_device_error(np);
4182                         if (r)
4183                                 err = r;
4184                 }
4185         }
4186
4187         if (err)
4188                 niu_enable_interrupts(np, 0);
4189
4190         return err;
4191 }
4192
4193 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4194                             int ldn)
4195 {
4196         struct rxdma_mailbox *mbox = rp->mbox;
4197         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4198
4199         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4200                       RX_DMA_CTL_STAT_RCRTO);
4201         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4202
4203         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4204                np->dev->name, (unsigned long long) stat);
4205 }
4206
4207 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4208                             int ldn)
4209 {
4210         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4211
4212         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4213                np->dev->name, (unsigned long long) rp->tx_cs);
4214 }
4215
4216 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4217 {
4218         struct niu_parent *parent = np->parent;
4219         u32 rx_vec, tx_vec;
4220         int i;
4221
4222         tx_vec = (v0 >> 32);
4223         rx_vec = (v0 & 0xffffffff);
4224
4225         for (i = 0; i < np->num_rx_rings; i++) {
4226                 struct rx_ring_info *rp = &np->rx_rings[i];
4227                 int ldn = LDN_RXDMA(rp->rx_channel);
4228
4229                 if (parent->ldg_map[ldn] != ldg)
4230                         continue;
4231
4232                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4233                 if (rx_vec & (1 << rp->rx_channel))
4234                         niu_rxchan_intr(np, rp, ldn);
4235         }
4236
4237         for (i = 0; i < np->num_tx_rings; i++) {
4238                 struct tx_ring_info *rp = &np->tx_rings[i];
4239                 int ldn = LDN_TXDMA(rp->tx_channel);
4240
4241                 if (parent->ldg_map[ldn] != ldg)
4242                         continue;
4243
4244                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4245                 if (tx_vec & (1 << rp->tx_channel))
4246                         niu_txchan_intr(np, rp, ldn);
4247         }
4248 }
4249
4250 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4251                               u64 v0, u64 v1, u64 v2)
4252 {
4253         if (likely(napi_schedule_prep(&lp->napi))) {
4254                 lp->v0 = v0;
4255                 lp->v1 = v1;
4256                 lp->v2 = v2;
4257                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4258                 __napi_schedule(&lp->napi);
4259         }
4260 }
4261
4262 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4263 {
4264         struct niu_ldg *lp = dev_id;
4265         struct niu *np = lp->np;
4266         int ldg = lp->ldg_num;
4267         unsigned long flags;
4268         u64 v0, v1, v2;
4269
4270         if (netif_msg_intr(np))
4271                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4272                        lp, ldg);
4273
4274         spin_lock_irqsave(&np->lock, flags);
4275
4276         v0 = nr64(LDSV0(ldg));
4277         v1 = nr64(LDSV1(ldg));
4278         v2 = nr64(LDSV2(ldg));
4279
4280         if (netif_msg_intr(np))
4281                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4282                        (unsigned long long) v0,
4283                        (unsigned long long) v1,
4284                        (unsigned long long) v2);
4285
4286         if (unlikely(!v0 && !v1 && !v2)) {
4287                 spin_unlock_irqrestore(&np->lock, flags);
4288                 return IRQ_NONE;
4289         }
4290
4291         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4292                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4293                 if (err)
4294                         goto out;
4295         }
4296         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4297                 niu_schedule_napi(np, lp, v0, v1, v2);
4298         else
4299                 niu_ldg_rearm(np, lp, 1);
4300 out:
4301         spin_unlock_irqrestore(&np->lock, flags);
4302
4303         return IRQ_HANDLED;
4304 }
4305
4306 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4307 {
4308         if (rp->mbox) {
4309                 np->ops->free_coherent(np->device,
4310                                        sizeof(struct rxdma_mailbox),
4311                                        rp->mbox, rp->mbox_dma);
4312                 rp->mbox = NULL;
4313         }
4314         if (rp->rcr) {
4315                 np->ops->free_coherent(np->device,
4316                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4317                                        rp->rcr, rp->rcr_dma);
4318                 rp->rcr = NULL;
4319                 rp->rcr_table_size = 0;
4320                 rp->rcr_index = 0;
4321         }
4322         if (rp->rbr) {
4323                 niu_rbr_free(np, rp);
4324
4325                 np->ops->free_coherent(np->device,
4326                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4327                                        rp->rbr, rp->rbr_dma);
4328                 rp->rbr = NULL;
4329                 rp->rbr_table_size = 0;
4330                 rp->rbr_index = 0;
4331         }
4332         kfree(rp->rxhash);
4333         rp->rxhash = NULL;
4334 }
4335
4336 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4337 {
4338         if (rp->mbox) {
4339                 np->ops->free_coherent(np->device,
4340                                        sizeof(struct txdma_mailbox),
4341                                        rp->mbox, rp->mbox_dma);
4342                 rp->mbox = NULL;
4343         }
4344         if (rp->descr) {
4345                 int i;
4346
4347                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4348                         if (rp->tx_buffs[i].skb)
4349                                 (void) release_tx_packet(np, rp, i);
4350                 }
4351
4352                 np->ops->free_coherent(np->device,
4353                                        MAX_TX_RING_SIZE * sizeof(__le64),
4354                                        rp->descr, rp->descr_dma);
4355                 rp->descr = NULL;
4356                 rp->pending = 0;
4357                 rp->prod = 0;
4358                 rp->cons = 0;
4359                 rp->wrap_bit = 0;
4360         }
4361 }
4362
4363 static void niu_free_channels(struct niu *np)
4364 {
4365         int i;
4366
4367         if (np->rx_rings) {
4368                 for (i = 0; i < np->num_rx_rings; i++) {
4369                         struct rx_ring_info *rp = &np->rx_rings[i];
4370
4371                         niu_free_rx_ring_info(np, rp);
4372                 }
4373                 kfree(np->rx_rings);
4374                 np->rx_rings = NULL;
4375                 np->num_rx_rings = 0;
4376         }
4377
4378         if (np->tx_rings) {
4379                 for (i = 0; i < np->num_tx_rings; i++) {
4380                         struct tx_ring_info *rp = &np->tx_rings[i];
4381
4382                         niu_free_tx_ring_info(np, rp);
4383                 }
4384                 kfree(np->tx_rings);
4385                 np->tx_rings = NULL;
4386                 np->num_tx_rings = 0;
4387         }
4388 }
4389
4390 static int niu_alloc_rx_ring_info(struct niu *np,
4391                                   struct rx_ring_info *rp)
4392 {
4393         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4394
4395         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4396                              GFP_KERNEL);
4397         if (!rp->rxhash)
4398                 return -ENOMEM;
4399
4400         rp->mbox = np->ops->alloc_coherent(np->device,
4401                                            sizeof(struct rxdma_mailbox),
4402                                            &rp->mbox_dma, GFP_KERNEL);
4403         if (!rp->mbox)
4404                 return -ENOMEM;
4405         if ((unsigned long)rp->mbox & (64UL - 1)) {
4406                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4407                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4408                 return -EINVAL;
4409         }
4410
4411         rp->rcr = np->ops->alloc_coherent(np->device,
4412                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4413                                           &rp->rcr_dma, GFP_KERNEL);
4414         if (!rp->rcr)
4415                 return -ENOMEM;
4416         if ((unsigned long)rp->rcr & (64UL - 1)) {
4417                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4418                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4419                 return -EINVAL;
4420         }
4421         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4422         rp->rcr_index = 0;
4423
4424         rp->rbr = np->ops->alloc_coherent(np->device,
4425                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4426                                           &rp->rbr_dma, GFP_KERNEL);
4427         if (!rp->rbr)
4428                 return -ENOMEM;
4429         if ((unsigned long)rp->rbr & (64UL - 1)) {
4430                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4431                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4432                 return -EINVAL;
4433         }
4434         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4435         rp->rbr_index = 0;
4436         rp->rbr_pending = 0;
4437
4438         return 0;
4439 }
4440
4441 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4442 {
4443         int mtu = np->dev->mtu;
4444
4445         /* These values are recommended by the HW designers for fair
4446          * utilization of DRR amongst the rings.
4447          */
4448         rp->max_burst = mtu + 32;
4449         if (rp->max_burst > 4096)
4450                 rp->max_burst = 4096;
4451 }
4452
4453 static int niu_alloc_tx_ring_info(struct niu *np,
4454                                   struct tx_ring_info *rp)
4455 {
4456         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4457
4458         rp->mbox = np->ops->alloc_coherent(np->device,
4459                                            sizeof(struct txdma_mailbox),
4460                                            &rp->mbox_dma, GFP_KERNEL);
4461         if (!rp->mbox)
4462                 return -ENOMEM;
4463         if ((unsigned long)rp->mbox & (64UL - 1)) {
4464                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4465                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4466                 return -EINVAL;
4467         }
4468
4469         rp->descr = np->ops->alloc_coherent(np->device,
4470                                             MAX_TX_RING_SIZE * sizeof(__le64),
4471                                             &rp->descr_dma, GFP_KERNEL);
4472         if (!rp->descr)
4473                 return -ENOMEM;
4474         if ((unsigned long)rp->descr & (64UL - 1)) {
4475                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4476                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
4477                 return -EINVAL;
4478         }
4479
4480         rp->pending = MAX_TX_RING_SIZE;
4481         rp->prod = 0;
4482         rp->cons = 0;
4483         rp->wrap_bit = 0;
4484
4485         /* XXX make these configurable... XXX */
4486         rp->mark_freq = rp->pending / 4;
4487
4488         niu_set_max_burst(np, rp);
4489
4490         return 0;
4491 }
4492
4493 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4494 {
4495         u16 bss;
4496
4497         bss = min(PAGE_SHIFT, 15);
4498
4499         rp->rbr_block_size = 1 << bss;
4500         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4501
4502         rp->rbr_sizes[0] = 256;
4503         rp->rbr_sizes[1] = 1024;
4504         if (np->dev->mtu > ETH_DATA_LEN) {
4505                 switch (PAGE_SIZE) {
4506                 case 4 * 1024:
4507                         rp->rbr_sizes[2] = 4096;
4508                         break;
4509
4510                 default:
4511                         rp->rbr_sizes[2] = 8192;
4512                         break;
4513                 }
4514         } else {
4515                 rp->rbr_sizes[2] = 2048;
4516         }
4517         rp->rbr_sizes[3] = rp->rbr_block_size;
4518 }
4519
4520 static int niu_alloc_channels(struct niu *np)
4521 {
4522         struct niu_parent *parent = np->parent;
4523         int first_rx_channel, first_tx_channel;
4524         int i, port, err;
4525
4526         port = np->port;
4527         first_rx_channel = first_tx_channel = 0;
4528         for (i = 0; i < port; i++) {
4529                 first_rx_channel += parent->rxchan_per_port[i];
4530                 first_tx_channel += parent->txchan_per_port[i];
4531         }
4532
4533         np->num_rx_rings = parent->rxchan_per_port[port];
4534         np->num_tx_rings = parent->txchan_per_port[port];
4535
4536         np->dev->real_num_tx_queues = np->num_tx_rings;
4537
4538         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4539                                GFP_KERNEL);
4540         err = -ENOMEM;
4541         if (!np->rx_rings)
4542                 goto out_err;
4543
4544         for (i = 0; i < np->num_rx_rings; i++) {
4545                 struct rx_ring_info *rp = &np->rx_rings[i];
4546
4547                 rp->np = np;
4548                 rp->rx_channel = first_rx_channel + i;
4549
4550                 err = niu_alloc_rx_ring_info(np, rp);
4551                 if (err)
4552                         goto out_err;
4553
4554                 niu_size_rbr(np, rp);
4555
4556                 /* XXX better defaults, configurable, etc... XXX */
4557                 rp->nonsyn_window = 64;
4558                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4559                 rp->syn_window = 64;
4560                 rp->syn_threshold = rp->rcr_table_size - 64;
4561                 rp->rcr_pkt_threshold = 16;
4562                 rp->rcr_timeout = 8;
4563                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4564                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4565                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4566
4567                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4568                 if (err)
4569                         return err;
4570         }
4571
4572         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4573                                GFP_KERNEL);
4574         err = -ENOMEM;
4575         if (!np->tx_rings)
4576                 goto out_err;
4577
4578         for (i = 0; i < np->num_tx_rings; i++) {
4579                 struct tx_ring_info *rp = &np->tx_rings[i];
4580
4581                 rp->np = np;
4582                 rp->tx_channel = first_tx_channel + i;
4583
4584                 err = niu_alloc_tx_ring_info(np, rp);
4585                 if (err)
4586                         goto out_err;
4587         }
4588
4589         return 0;
4590
4591 out_err:
4592         niu_free_channels(np);
4593         return err;
4594 }
4595
4596 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4597 {
4598         int limit = 1000;
4599
4600         while (--limit > 0) {
4601                 u64 val = nr64(TX_CS(channel));
4602                 if (val & TX_CS_SNG_STATE)
4603                         return 0;
4604         }
4605         return -ENODEV;
4606 }
4607
4608 static int niu_tx_channel_stop(struct niu *np, int channel)
4609 {
4610         u64 val = nr64(TX_CS(channel));
4611
4612         val |= TX_CS_STOP_N_GO;
4613         nw64(TX_CS(channel), val);
4614
4615         return niu_tx_cs_sng_poll(np, channel);
4616 }
4617
4618 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4619 {
4620         int limit = 1000;
4621
4622         while (--limit > 0) {
4623                 u64 val = nr64(TX_CS(channel));
4624                 if (!(val & TX_CS_RST))
4625                         return 0;
4626         }
4627         return -ENODEV;
4628 }
4629
4630 static int niu_tx_channel_reset(struct niu *np, int channel)
4631 {
4632         u64 val = nr64(TX_CS(channel));
4633         int err;
4634
4635         val |= TX_CS_RST;
4636         nw64(TX_CS(channel), val);
4637
4638         err = niu_tx_cs_reset_poll(np, channel);
4639         if (!err)
4640                 nw64(TX_RING_KICK(channel), 0);
4641
4642         return err;
4643 }
4644
4645 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4646 {
4647         u64 val;
4648
4649         nw64(TX_LOG_MASK1(channel), 0);
4650         nw64(TX_LOG_VAL1(channel), 0);
4651         nw64(TX_LOG_MASK2(channel), 0);
4652         nw64(TX_LOG_VAL2(channel), 0);
4653         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4654         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4655         nw64(TX_LOG_PAGE_HDL(channel), 0);
4656
4657         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4658         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4659         nw64(TX_LOG_PAGE_VLD(channel), val);
4660
4661         /* XXX TXDMA 32bit mode? XXX */
4662
4663         return 0;
4664 }
4665
4666 static void niu_txc_enable_port(struct niu *np, int on)
4667 {
4668         unsigned long flags;
4669         u64 val, mask;
4670
4671         niu_lock_parent(np, flags);
4672         val = nr64(TXC_CONTROL);
4673         mask = (u64)1 << np->port;
4674         if (on) {
4675                 val |= TXC_CONTROL_ENABLE | mask;
4676         } else {
4677                 val &= ~mask;
4678                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4679                         val &= ~TXC_CONTROL_ENABLE;
4680         }
4681         nw64(TXC_CONTROL, val);
4682         niu_unlock_parent(np, flags);
4683 }
4684
4685 static void niu_txc_set_imask(struct niu *np, u64 imask)
4686 {
4687         unsigned long flags;
4688         u64 val;
4689
4690         niu_lock_parent(np, flags);
4691         val = nr64(TXC_INT_MASK);
4692         val &= ~TXC_INT_MASK_VAL(np->port);
4693         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4694         niu_unlock_parent(np, flags);
4695 }
4696
4697 static void niu_txc_port_dma_enable(struct niu *np, int on)
4698 {
4699         u64 val = 0;
4700
4701         if (on) {
4702                 int i;
4703
4704                 for (i = 0; i < np->num_tx_rings; i++)
4705                         val |= (1 << np->tx_rings[i].tx_channel);
4706         }
4707         nw64(TXC_PORT_DMA(np->port), val);
4708 }
4709
4710 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4711 {
4712         int err, channel = rp->tx_channel;
4713         u64 val, ring_len;
4714
4715         err = niu_tx_channel_stop(np, channel);
4716         if (err)
4717                 return err;
4718
4719         err = niu_tx_channel_reset(np, channel);
4720         if (err)
4721                 return err;
4722
4723         err = niu_tx_channel_lpage_init(np, channel);
4724         if (err)
4725                 return err;
4726
4727         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4728         nw64(TX_ENT_MSK(channel), 0);
4729
4730         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4731                               TX_RNG_CFIG_STADDR)) {
4732                 dev_err(np->device, PFX "%s: TX ring channel %d "
4733                         "DMA addr (%llx) is not aligned.\n",
4734                         np->dev->name, channel,
4735                         (unsigned long long) rp->descr_dma);
4736                 return -EINVAL;
4737         }
4738
4739         /* The length field in TX_RNG_CFIG is measured in 64-byte
4740          * blocks.  rp->pending is the number of TX descriptors in
4741          * our ring, 8 bytes each, thus we divide by 8 bytes more
4742          * to get the proper value the chip wants.
4743          */
4744         ring_len = (rp->pending / 8);
4745
4746         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4747                rp->descr_dma);
4748         nw64(TX_RNG_CFIG(channel), val);
4749
4750         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4751             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4752                 dev_err(np->device, PFX "%s: TX ring channel %d "
4753                         "MBOX addr (%llx) is has illegal bits.\n",
4754                         np->dev->name, channel,
4755                         (unsigned long long) rp->mbox_dma);
4756                 return -EINVAL;
4757         }
4758         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4759         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4760
4761         nw64(TX_CS(channel), 0);
4762
4763         rp->last_pkt_cnt = 0;
4764
4765         return 0;
4766 }
4767
4768 static void niu_init_rdc_groups(struct niu *np)
4769 {
4770         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4771         int i, first_table_num = tp->first_table_num;
4772
4773         for (i = 0; i < tp->num_tables; i++) {
4774                 struct rdc_table *tbl = &tp->tables[i];
4775                 int this_table = first_table_num + i;
4776                 int slot;
4777
4778                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4779                         nw64(RDC_TBL(this_table, slot),
4780                              tbl->rxdma_channel[slot]);
4781         }
4782
4783         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4784 }
4785
4786 static void niu_init_drr_weight(struct niu *np)
4787 {
4788         int type = phy_decode(np->parent->port_phy, np->port);
4789         u64 val;
4790
4791         switch (type) {
4792         case PORT_TYPE_10G:
4793                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4794                 break;
4795
4796         case PORT_TYPE_1G:
4797         default:
4798                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4799                 break;
4800         }
4801         nw64(PT_DRR_WT(np->port), val);
4802 }
4803
4804 static int niu_init_hostinfo(struct niu *np)
4805 {
4806         struct niu_parent *parent = np->parent;
4807         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4808         int i, err, num_alt = niu_num_alt_addr(np);
4809         int first_rdc_table = tp->first_table_num;
4810
4811         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4812         if (err)
4813                 return err;
4814
4815         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4816         if (err)
4817                 return err;
4818
4819         for (i = 0; i < num_alt; i++) {
4820                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4821                 if (err)
4822                         return err;
4823         }
4824
4825         return 0;
4826 }
4827
4828 static int niu_rx_channel_reset(struct niu *np, int channel)
4829 {
4830         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4831                                       RXDMA_CFIG1_RST, 1000, 10,
4832                                       "RXDMA_CFIG1");
4833 }
4834
4835 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4836 {
4837         u64 val;
4838
4839         nw64(RX_LOG_MASK1(channel), 0);
4840         nw64(RX_LOG_VAL1(channel), 0);
4841         nw64(RX_LOG_MASK2(channel), 0);
4842         nw64(RX_LOG_VAL2(channel), 0);
4843         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4844         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4845         nw64(RX_LOG_PAGE_HDL(channel), 0);
4846
4847         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4848         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4849         nw64(RX_LOG_PAGE_VLD(channel), val);
4850
4851         return 0;
4852 }
4853
4854 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4855 {
4856         u64 val;
4857
4858         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4859                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4860                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4861                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4862         nw64(RDC_RED_PARA(rp->rx_channel), val);
4863 }
4864
4865 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4866 {
4867         u64 val = 0;
4868
4869         *ret = 0;
4870         switch (rp->rbr_block_size) {
4871         case 4 * 1024:
4872                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4873                 break;
4874         case 8 * 1024:
4875                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4876                 break;
4877         case 16 * 1024:
4878                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4879                 break;
4880         case 32 * 1024:
4881                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4882                 break;
4883         default:
4884                 return -EINVAL;
4885         }
4886         val |= RBR_CFIG_B_VLD2;
4887         switch (rp->rbr_sizes[2]) {
4888         case 2 * 1024:
4889                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4890                 break;
4891         case 4 * 1024:
4892                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4893                 break;
4894         case 8 * 1024:
4895                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4896                 break;
4897         case 16 * 1024:
4898                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4899                 break;
4900
4901         default:
4902                 return -EINVAL;
4903         }
4904         val |= RBR_CFIG_B_VLD1;
4905         switch (rp->rbr_sizes[1]) {
4906         case 1 * 1024:
4907                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4908                 break;
4909         case 2 * 1024:
4910                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4911                 break;
4912         case 4 * 1024:
4913                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4914                 break;
4915         case 8 * 1024:
4916                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4917                 break;
4918
4919         default:
4920                 return -EINVAL;
4921         }
4922         val |= RBR_CFIG_B_VLD0;
4923         switch (rp->rbr_sizes[0]) {
4924         case 256:
4925                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4926                 break;
4927         case 512:
4928                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4929                 break;
4930         case 1 * 1024:
4931                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4932                 break;
4933         case 2 * 1024:
4934                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4935                 break;
4936
4937         default:
4938                 return -EINVAL;
4939         }
4940
4941         *ret = val;
4942         return 0;
4943 }
4944
4945 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4946 {
4947         u64 val = nr64(RXDMA_CFIG1(channel));
4948         int limit;
4949
4950         if (on)
4951                 val |= RXDMA_CFIG1_EN;
4952         else
4953                 val &= ~RXDMA_CFIG1_EN;
4954         nw64(RXDMA_CFIG1(channel), val);
4955
4956         limit = 1000;
4957         while (--limit > 0) {
4958                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4959                         break;
4960                 udelay(10);
4961         }
4962         if (limit <= 0)
4963                 return -ENODEV;
4964         return 0;
4965 }
4966
4967 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4968 {
4969         int err, channel = rp->rx_channel;
4970         u64 val;
4971
4972         err = niu_rx_channel_reset(np, channel);
4973         if (err)
4974                 return err;
4975
4976         err = niu_rx_channel_lpage_init(np, channel);
4977         if (err)
4978                 return err;
4979
4980         niu_rx_channel_wred_init(np, rp);
4981
4982         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4983         nw64(RX_DMA_CTL_STAT(channel),
4984              (RX_DMA_CTL_STAT_MEX |
4985               RX_DMA_CTL_STAT_RCRTHRES |
4986               RX_DMA_CTL_STAT_RCRTO |
4987               RX_DMA_CTL_STAT_RBR_EMPTY));
4988         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4989         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4990         nw64(RBR_CFIG_A(channel),
4991              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4992              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4993         err = niu_compute_rbr_cfig_b(rp, &val);
4994         if (err)
4995                 return err;
4996         nw64(RBR_CFIG_B(channel), val);
4997         nw64(RCRCFIG_A(channel),
4998              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4999              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
5000         nw64(RCRCFIG_B(channel),
5001              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
5002              RCRCFIG_B_ENTOUT |
5003              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
5004
5005         err = niu_enable_rx_channel(np, channel, 1);
5006         if (err)
5007                 return err;
5008
5009         nw64(RBR_KICK(channel), rp->rbr_index);
5010
5011         val = nr64(RX_DMA_CTL_STAT(channel));
5012         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
5013         nw64(RX_DMA_CTL_STAT(channel), val);
5014
5015         return 0;
5016 }
5017
5018 static int niu_init_rx_channels(struct niu *np)
5019 {
5020         unsigned long flags;
5021         u64 seed = jiffies_64;
5022         int err, i;
5023
5024         niu_lock_parent(np, flags);
5025         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
5026         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5027         niu_unlock_parent(np, flags);
5028
5029         /* XXX RXDMA 32bit mode? XXX */
5030
5031         niu_init_rdc_groups(np);
5032         niu_init_drr_weight(np);
5033
5034         err = niu_init_hostinfo(np);
5035         if (err)
5036                 return err;
5037
5038         for (i = 0; i < np->num_rx_rings; i++) {
5039                 struct rx_ring_info *rp = &np->rx_rings[i];
5040
5041                 err = niu_init_one_rx_channel(np, rp);
5042                 if (err)
5043                         return err;
5044         }
5045
5046         return 0;
5047 }
5048
5049 static int niu_set_ip_frag_rule(struct niu *np)
5050 {
5051         struct niu_parent *parent = np->parent;
5052         struct niu_classifier *cp = &np->clas;
5053         struct niu_tcam_entry *tp;
5054         int index, err;
5055
5056         index = cp->tcam_top;
5057         tp = &parent->tcam[index];
5058
5059         /* Note that the noport bit is the same in both ipv4 and
5060          * ipv6 format TCAM entries.
5061          */
5062         memset(tp, 0, sizeof(*tp));
5063         tp->key[1] = TCAM_V4KEY1_NOPORT;
5064         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5065         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5066                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5067         err = tcam_write(np, index, tp->key, tp->key_mask);
5068         if (err)
5069                 return err;
5070         err = tcam_assoc_write(np, index, tp->assoc_data);
5071         if (err)
5072                 return err;
5073         tp->valid = 1;
5074         cp->tcam_valid_entries++;
5075
5076         return 0;
5077 }
5078
5079 static int niu_init_classifier_hw(struct niu *np)
5080 {
5081         struct niu_parent *parent = np->parent;
5082         struct niu_classifier *cp = &np->clas;
5083         int i, err;
5084
5085         nw64(H1POLY, cp->h1_init);
5086         nw64(H2POLY, cp->h2_init);
5087
5088         err = niu_init_hostinfo(np);
5089         if (err)
5090                 return err;
5091
5092         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5093                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5094
5095                 vlan_tbl_write(np, i, np->port,
5096                                vp->vlan_pref, vp->rdc_num);
5097         }
5098
5099         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5100                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5101
5102                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5103                                                 ap->rdc_num, ap->mac_pref);
5104                 if (err)
5105                         return err;
5106         }
5107
5108         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5109                 int index = i - CLASS_CODE_USER_PROG1;
5110
5111                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5112                 if (err)
5113                         return err;
5114                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5115                 if (err)
5116                         return err;
5117         }
5118
5119         err = niu_set_ip_frag_rule(np);
5120         if (err)
5121                 return err;
5122
5123         tcam_enable(np, 1);
5124
5125         return 0;
5126 }
5127
5128 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5129 {
5130         nw64(ZCP_RAM_DATA0, data[0]);
5131         nw64(ZCP_RAM_DATA1, data[1]);
5132         nw64(ZCP_RAM_DATA2, data[2]);
5133         nw64(ZCP_RAM_DATA3, data[3]);
5134         nw64(ZCP_RAM_DATA4, data[4]);
5135         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5136         nw64(ZCP_RAM_ACC,
5137              (ZCP_RAM_ACC_WRITE |
5138               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5139               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5140
5141         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5142                                    1000, 100);
5143 }
5144
5145 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5146 {
5147         int err;
5148
5149         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5150                                   1000, 100);
5151         if (err) {
5152                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5153                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5154                         (unsigned long long) nr64(ZCP_RAM_ACC));
5155                 return err;
5156         }
5157
5158         nw64(ZCP_RAM_ACC,
5159              (ZCP_RAM_ACC_READ |
5160               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5161               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5162
5163         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5164                                   1000, 100);
5165         if (err) {
5166                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5167                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5168                         (unsigned long long) nr64(ZCP_RAM_ACC));
5169                 return err;
5170         }
5171
5172         data[0] = nr64(ZCP_RAM_DATA0);
5173         data[1] = nr64(ZCP_RAM_DATA1);
5174         data[2] = nr64(ZCP_RAM_DATA2);
5175         data[3] = nr64(ZCP_RAM_DATA3);
5176         data[4] = nr64(ZCP_RAM_DATA4);
5177
5178         return 0;
5179 }
5180
5181 static void niu_zcp_cfifo_reset(struct niu *np)
5182 {
5183         u64 val = nr64(RESET_CFIFO);
5184
5185         val |= RESET_CFIFO_RST(np->port);
5186         nw64(RESET_CFIFO, val);
5187         udelay(10);
5188
5189         val &= ~RESET_CFIFO_RST(np->port);
5190         nw64(RESET_CFIFO, val);
5191 }
5192
5193 static int niu_init_zcp(struct niu *np)
5194 {
5195         u64 data[5], rbuf[5];
5196         int i, max, err;
5197
5198         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5199                 if (np->port == 0 || np->port == 1)
5200                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5201                 else
5202                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5203         } else
5204                 max = NIU_CFIFO_ENTRIES;
5205
5206         data[0] = 0;
5207         data[1] = 0;
5208         data[2] = 0;
5209         data[3] = 0;
5210         data[4] = 0;
5211
5212         for (i = 0; i < max; i++) {
5213                 err = niu_zcp_write(np, i, data);
5214                 if (err)
5215                         return err;
5216                 err = niu_zcp_read(np, i, rbuf);
5217                 if (err)
5218                         return err;
5219         }
5220
5221         niu_zcp_cfifo_reset(np);
5222         nw64(CFIFO_ECC(np->port), 0);
5223         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5224         (void) nr64(ZCP_INT_STAT);
5225         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5226
5227         return 0;
5228 }
5229
5230 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5231 {
5232         u64 val = nr64_ipp(IPP_CFIG);
5233
5234         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5235         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5236         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5237         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5238         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5239         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5240         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5241         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5242 }
5243
5244 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5245 {
5246         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5247         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5248         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5249         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5250         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5251         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5252 }
5253
5254 static int niu_ipp_reset(struct niu *np)
5255 {
5256         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5257                                           1000, 100, "IPP_CFIG");
5258 }
5259
5260 static int niu_init_ipp(struct niu *np)
5261 {
5262         u64 data[5], rbuf[5], val;
5263         int i, max, err;
5264
5265         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5266                 if (np->port == 0 || np->port == 1)
5267                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5268                 else
5269                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5270         } else
5271                 max = NIU_DFIFO_ENTRIES;
5272
5273         data[0] = 0;
5274         data[1] = 0;
5275         data[2] = 0;
5276         data[3] = 0;
5277         data[4] = 0;
5278
5279         for (i = 0; i < max; i++) {
5280                 niu_ipp_write(np, i, data);
5281                 niu_ipp_read(np, i, rbuf);
5282         }
5283
5284         (void) nr64_ipp(IPP_INT_STAT);
5285         (void) nr64_ipp(IPP_INT_STAT);
5286
5287         err = niu_ipp_reset(np);
5288         if (err)
5289                 return err;
5290
5291         (void) nr64_ipp(IPP_PKT_DIS);
5292         (void) nr64_ipp(IPP_BAD_CS_CNT);
5293         (void) nr64_ipp(IPP_ECC);
5294
5295         (void) nr64_ipp(IPP_INT_STAT);
5296
5297         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5298
5299         val = nr64_ipp(IPP_CFIG);
5300         val &= ~IPP_CFIG_IP_MAX_PKT;
5301         val |= (IPP_CFIG_IPP_ENABLE |
5302                 IPP_CFIG_DFIFO_ECC_EN |
5303                 IPP_CFIG_DROP_BAD_CRC |
5304                 IPP_CFIG_CKSUM_EN |
5305                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5306         nw64_ipp(IPP_CFIG, val);
5307
5308         return 0;
5309 }
5310
5311 static void niu_handle_led(struct niu *np, int status)
5312 {
5313         u64 val;
5314         val = nr64_mac(XMAC_CONFIG);
5315
5316         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5317             (np->flags & NIU_FLAGS_FIBER) != 0) {
5318                 if (status) {
5319                         val |= XMAC_CONFIG_LED_POLARITY;
5320                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5321                 } else {
5322                         val |= XMAC_CONFIG_FORCE_LED_ON;
5323                         val &= ~XMAC_CONFIG_LED_POLARITY;
5324                 }
5325         }
5326
5327         nw64_mac(XMAC_CONFIG, val);
5328 }
5329
5330 static void niu_init_xif_xmac(struct niu *np)
5331 {
5332         struct niu_link_config *lp = &np->link_config;
5333         u64 val;
5334
5335         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5336                 val = nr64(MIF_CONFIG);
5337                 val |= MIF_CONFIG_ATCA_GE;
5338                 nw64(MIF_CONFIG, val);
5339         }
5340
5341         val = nr64_mac(XMAC_CONFIG);
5342         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5343
5344         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5345
5346         if (lp->loopback_mode == LOOPBACK_MAC) {
5347                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5348                 val |= XMAC_CONFIG_LOOPBACK;
5349         } else {
5350                 val &= ~XMAC_CONFIG_LOOPBACK;
5351         }
5352
5353         if (np->flags & NIU_FLAGS_10G) {
5354                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5355         } else {
5356                 val |= XMAC_CONFIG_LFS_DISABLE;
5357                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5358                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5359                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5360                 else
5361                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5362         }
5363
5364         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5365
5366         if (lp->active_speed == SPEED_100)
5367                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5368         else
5369                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5370
5371         nw64_mac(XMAC_CONFIG, val);
5372
5373         val = nr64_mac(XMAC_CONFIG);
5374         val &= ~XMAC_CONFIG_MODE_MASK;
5375         if (np->flags & NIU_FLAGS_10G) {
5376                 val |= XMAC_CONFIG_MODE_XGMII;
5377         } else {
5378                 if (lp->active_speed == SPEED_1000)
5379                         val |= XMAC_CONFIG_MODE_GMII;
5380                 else
5381                         val |= XMAC_CONFIG_MODE_MII;
5382         }
5383
5384         nw64_mac(XMAC_CONFIG, val);
5385 }
5386
5387 static void niu_init_xif_bmac(struct niu *np)
5388 {
5389         struct niu_link_config *lp = &np->link_config;
5390         u64 val;
5391
5392         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5393
5394         if (lp->loopback_mode == LOOPBACK_MAC)
5395                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5396         else
5397                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5398
5399         if (lp->active_speed == SPEED_1000)
5400                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5401         else
5402                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5403
5404         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5405                  BMAC_XIF_CONFIG_LED_POLARITY);
5406
5407         if (!(np->flags & NIU_FLAGS_10G) &&
5408             !(np->flags & NIU_FLAGS_FIBER) &&
5409             lp->active_speed == SPEED_100)
5410                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5411         else
5412                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5413
5414         nw64_mac(BMAC_XIF_CONFIG, val);
5415 }
5416
5417 static void niu_init_xif(struct niu *np)
5418 {
5419         if (np->flags & NIU_FLAGS_XMAC)
5420                 niu_init_xif_xmac(np);
5421         else
5422                 niu_init_xif_bmac(np);
5423 }
5424
5425 static void niu_pcs_mii_reset(struct niu *np)
5426 {
5427         int limit = 1000;
5428         u64 val = nr64_pcs(PCS_MII_CTL);
5429         val |= PCS_MII_CTL_RST;
5430         nw64_pcs(PCS_MII_CTL, val);
5431         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5432                 udelay(100);
5433                 val = nr64_pcs(PCS_MII_CTL);
5434         }
5435 }
5436
5437 static void niu_xpcs_reset(struct niu *np)
5438 {
5439         int limit = 1000;
5440         u64 val = nr64_xpcs(XPCS_CONTROL1);
5441         val |= XPCS_CONTROL1_RESET;
5442         nw64_xpcs(XPCS_CONTROL1, val);
5443         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5444                 udelay(100);
5445                 val = nr64_xpcs(XPCS_CONTROL1);
5446         }
5447 }
5448
5449 static int niu_init_pcs(struct niu *np)
5450 {
5451         struct niu_link_config *lp = &np->link_config;
5452         u64 val;
5453
5454         switch (np->flags & (NIU_FLAGS_10G |
5455                              NIU_FLAGS_FIBER |
5456                              NIU_FLAGS_XCVR_SERDES)) {
5457         case NIU_FLAGS_FIBER:
5458                 /* 1G fiber */
5459                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460                 nw64_pcs(PCS_DPATH_MODE, 0);
5461                 niu_pcs_mii_reset(np);
5462                 break;
5463
5464         case NIU_FLAGS_10G:
5465         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5466         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5467                 /* 10G SERDES */
5468                 if (!(np->flags & NIU_FLAGS_XMAC))
5469                         return -EINVAL;
5470
5471                 /* 10G copper or fiber */
5472                 val = nr64_mac(XMAC_CONFIG);
5473                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5474                 nw64_mac(XMAC_CONFIG, val);
5475
5476                 niu_xpcs_reset(np);
5477
5478                 val = nr64_xpcs(XPCS_CONTROL1);
5479                 if (lp->loopback_mode == LOOPBACK_PHY)
5480                         val |= XPCS_CONTROL1_LOOPBACK;
5481                 else
5482                         val &= ~XPCS_CONTROL1_LOOPBACK;
5483                 nw64_xpcs(XPCS_CONTROL1, val);
5484
5485                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5486                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5487                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5488                 break;
5489
5490
5491         case NIU_FLAGS_XCVR_SERDES:
5492                 /* 1G SERDES */
5493                 niu_pcs_mii_reset(np);
5494                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5495                 nw64_pcs(PCS_DPATH_MODE, 0);
5496                 break;
5497
5498         case 0:
5499                 /* 1G copper */
5500         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5501                 /* 1G RGMII FIBER */
5502                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5503                 niu_pcs_mii_reset(np);
5504                 break;
5505
5506         default:
5507                 return -EINVAL;
5508         }
5509
5510         return 0;
5511 }
5512
5513 static int niu_reset_tx_xmac(struct niu *np)
5514 {
5515         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5516                                           (XTXMAC_SW_RST_REG_RS |
5517                                            XTXMAC_SW_RST_SOFT_RST),
5518                                           1000, 100, "XTXMAC_SW_RST");
5519 }
5520
5521 static int niu_reset_tx_bmac(struct niu *np)
5522 {
5523         int limit;
5524
5525         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5526         limit = 1000;
5527         while (--limit >= 0) {
5528                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5529                         break;
5530                 udelay(100);
5531         }
5532         if (limit < 0) {
5533                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5534                         "BTXMAC_SW_RST[%llx]\n",
5535                         np->port,
5536                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5537                 return -ENODEV;
5538         }
5539
5540         return 0;
5541 }
5542
5543 static int niu_reset_tx_mac(struct niu *np)
5544 {
5545         if (np->flags & NIU_FLAGS_XMAC)
5546                 return niu_reset_tx_xmac(np);
5547         else
5548                 return niu_reset_tx_bmac(np);
5549 }
5550
5551 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5552 {
5553         u64 val;
5554
5555         val = nr64_mac(XMAC_MIN);
5556         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5557                  XMAC_MIN_RX_MIN_PKT_SIZE);
5558         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5559         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5560         nw64_mac(XMAC_MIN, val);
5561
5562         nw64_mac(XMAC_MAX, max);
5563
5564         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5565
5566         val = nr64_mac(XMAC_IPG);
5567         if (np->flags & NIU_FLAGS_10G) {
5568                 val &= ~XMAC_IPG_IPG_XGMII;
5569                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5570         } else {
5571                 val &= ~XMAC_IPG_IPG_MII_GMII;
5572                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5573         }
5574         nw64_mac(XMAC_IPG, val);
5575
5576         val = nr64_mac(XMAC_CONFIG);
5577         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5578                  XMAC_CONFIG_STRETCH_MODE |
5579                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5580                  XMAC_CONFIG_TX_ENABLE);
5581         nw64_mac(XMAC_CONFIG, val);
5582
5583         nw64_mac(TXMAC_FRM_CNT, 0);
5584         nw64_mac(TXMAC_BYTE_CNT, 0);
5585 }
5586
5587 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5588 {
5589         u64 val;
5590
5591         nw64_mac(BMAC_MIN_FRAME, min);
5592         nw64_mac(BMAC_MAX_FRAME, max);
5593
5594         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5595         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5596         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5597
5598         val = nr64_mac(BTXMAC_CONFIG);
5599         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5600                  BTXMAC_CONFIG_ENABLE);
5601         nw64_mac(BTXMAC_CONFIG, val);
5602 }
5603
5604 static void niu_init_tx_mac(struct niu *np)
5605 {
5606         u64 min, max;
5607
5608         min = 64;
5609         if (np->dev->mtu > ETH_DATA_LEN)
5610                 max = 9216;
5611         else
5612                 max = 1522;
5613
5614         /* The XMAC_MIN register only accepts values for TX min which
5615          * have the low 3 bits cleared.
5616          */
5617         BUILD_BUG_ON(min & 0x7);
5618
5619         if (np->flags & NIU_FLAGS_XMAC)
5620                 niu_init_tx_xmac(np, min, max);
5621         else
5622                 niu_init_tx_bmac(np, min, max);
5623 }
5624
5625 static int niu_reset_rx_xmac(struct niu *np)
5626 {
5627         int limit;
5628
5629         nw64_mac(XRXMAC_SW_RST,
5630                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5631         limit = 1000;
5632         while (--limit >= 0) {
5633                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5634                                                  XRXMAC_SW_RST_SOFT_RST)))
5635                     break;
5636                 udelay(100);
5637         }
5638         if (limit < 0) {
5639                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5640                         "XRXMAC_SW_RST[%llx]\n",
5641                         np->port,
5642                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5643                 return -ENODEV;
5644         }
5645
5646         return 0;
5647 }
5648
5649 static int niu_reset_rx_bmac(struct niu *np)
5650 {
5651         int limit;
5652
5653         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5654         limit = 1000;
5655         while (--limit >= 0) {
5656                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5657                         break;
5658                 udelay(100);
5659         }
5660         if (limit < 0) {
5661                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5662                         "BRXMAC_SW_RST[%llx]\n",
5663                         np->port,
5664                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5665                 return -ENODEV;
5666         }
5667
5668         return 0;
5669 }
5670
5671 static int niu_reset_rx_mac(struct niu *np)
5672 {
5673         if (np->flags & NIU_FLAGS_XMAC)
5674                 return niu_reset_rx_xmac(np);
5675         else
5676                 return niu_reset_rx_bmac(np);
5677 }
5678
5679 static void niu_init_rx_xmac(struct niu *np)
5680 {
5681         struct niu_parent *parent = np->parent;
5682         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5683         int first_rdc_table = tp->first_table_num;
5684         unsigned long i;
5685         u64 val;
5686
5687         nw64_mac(XMAC_ADD_FILT0, 0);
5688         nw64_mac(XMAC_ADD_FILT1, 0);
5689         nw64_mac(XMAC_ADD_FILT2, 0);
5690         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5691         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5692         for (i = 0; i < MAC_NUM_HASH; i++)
5693                 nw64_mac(XMAC_HASH_TBL(i), 0);
5694         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5695         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5696         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5697
5698         val = nr64_mac(XMAC_CONFIG);
5699         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5700                  XMAC_CONFIG_PROMISCUOUS |
5701                  XMAC_CONFIG_PROMISC_GROUP |
5702                  XMAC_CONFIG_ERR_CHK_DIS |
5703                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5704                  XMAC_CONFIG_RESERVED_MULTICAST |
5705                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5706                  XMAC_CONFIG_ADDR_FILTER_EN |
5707                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5708                  XMAC_CONFIG_STRIP_CRC |
5709                  XMAC_CONFIG_PASS_FLOW_CTRL |
5710                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5711         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5712         nw64_mac(XMAC_CONFIG, val);
5713
5714         nw64_mac(RXMAC_BT_CNT, 0);
5715         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5716         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5717         nw64_mac(RXMAC_FRAG_CNT, 0);
5718         nw64_mac(RXMAC_HIST_CNT1, 0);
5719         nw64_mac(RXMAC_HIST_CNT2, 0);
5720         nw64_mac(RXMAC_HIST_CNT3, 0);
5721         nw64_mac(RXMAC_HIST_CNT4, 0);
5722         nw64_mac(RXMAC_HIST_CNT5, 0);
5723         nw64_mac(RXMAC_HIST_CNT6, 0);
5724         nw64_mac(RXMAC_HIST_CNT7, 0);
5725         nw64_mac(RXMAC_MPSZER_CNT, 0);
5726         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5727         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5728         nw64_mac(LINK_FAULT_CNT, 0);
5729 }
5730
5731 static void niu_init_rx_bmac(struct niu *np)
5732 {
5733         struct niu_parent *parent = np->parent;
5734         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5735         int first_rdc_table = tp->first_table_num;
5736         unsigned long i;
5737         u64 val;
5738
5739         nw64_mac(BMAC_ADD_FILT0, 0);
5740         nw64_mac(BMAC_ADD_FILT1, 0);
5741         nw64_mac(BMAC_ADD_FILT2, 0);
5742         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5743         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5744         for (i = 0; i < MAC_NUM_HASH; i++)
5745                 nw64_mac(BMAC_HASH_TBL(i), 0);
5746         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5747         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5748         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5749
5750         val = nr64_mac(BRXMAC_CONFIG);
5751         val &= ~(BRXMAC_CONFIG_ENABLE |
5752                  BRXMAC_CONFIG_STRIP_PAD |
5753                  BRXMAC_CONFIG_STRIP_FCS |
5754                  BRXMAC_CONFIG_PROMISC |
5755                  BRXMAC_CONFIG_PROMISC_GRP |
5756                  BRXMAC_CONFIG_ADDR_FILT_EN |
5757                  BRXMAC_CONFIG_DISCARD_DIS);
5758         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5759         nw64_mac(BRXMAC_CONFIG, val);
5760
5761         val = nr64_mac(BMAC_ADDR_CMPEN);
5762         val |= BMAC_ADDR_CMPEN_EN0;
5763         nw64_mac(BMAC_ADDR_CMPEN, val);
5764 }
5765
5766 static void niu_init_rx_mac(struct niu *np)
5767 {
5768         niu_set_primary_mac(np, np->dev->dev_addr);
5769
5770         if (np->flags & NIU_FLAGS_XMAC)
5771                 niu_init_rx_xmac(np);
5772         else
5773                 niu_init_rx_bmac(np);
5774 }
5775
5776 static void niu_enable_tx_xmac(struct niu *np, int on)
5777 {
5778         u64 val = nr64_mac(XMAC_CONFIG);
5779
5780         if (on)
5781                 val |= XMAC_CONFIG_TX_ENABLE;
5782         else
5783                 val &= ~XMAC_CONFIG_TX_ENABLE;
5784         nw64_mac(XMAC_CONFIG, val);
5785 }
5786
5787 static void niu_enable_tx_bmac(struct niu *np, int on)
5788 {
5789         u64 val = nr64_mac(BTXMAC_CONFIG);
5790
5791         if (on)
5792                 val |= BTXMAC_CONFIG_ENABLE;
5793         else
5794                 val &= ~BTXMAC_CONFIG_ENABLE;
5795         nw64_mac(BTXMAC_CONFIG, val);
5796 }
5797
5798 static void niu_enable_tx_mac(struct niu *np, int on)
5799 {
5800         if (np->flags & NIU_FLAGS_XMAC)
5801                 niu_enable_tx_xmac(np, on);
5802         else
5803                 niu_enable_tx_bmac(np, on);
5804 }
5805
5806 static void niu_enable_rx_xmac(struct niu *np, int on)
5807 {
5808         u64 val = nr64_mac(XMAC_CONFIG);
5809
5810         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5811                  XMAC_CONFIG_PROMISCUOUS);
5812
5813         if (np->flags & NIU_FLAGS_MCAST)
5814                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5815         if (np->flags & NIU_FLAGS_PROMISC)
5816                 val |= XMAC_CONFIG_PROMISCUOUS;
5817
5818         if (on)
5819                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5820         else
5821                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5822         nw64_mac(XMAC_CONFIG, val);
5823 }
5824
5825 static void niu_enable_rx_bmac(struct niu *np, int on)
5826 {
5827         u64 val = nr64_mac(BRXMAC_CONFIG);
5828
5829         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5830                  BRXMAC_CONFIG_PROMISC);
5831
5832         if (np->flags & NIU_FLAGS_MCAST)
5833                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5834         if (np->flags & NIU_FLAGS_PROMISC)
5835                 val |= BRXMAC_CONFIG_PROMISC;
5836
5837         if (on)
5838                 val |= BRXMAC_CONFIG_ENABLE;
5839         else
5840                 val &= ~BRXMAC_CONFIG_ENABLE;
5841         nw64_mac(BRXMAC_CONFIG, val);
5842 }
5843
5844 static void niu_enable_rx_mac(struct niu *np, int on)
5845 {
5846         if (np->flags & NIU_FLAGS_XMAC)
5847                 niu_enable_rx_xmac(np, on);
5848         else
5849                 niu_enable_rx_bmac(np, on);
5850 }
5851
5852 static int niu_init_mac(struct niu *np)
5853 {
5854         int err;
5855
5856         niu_init_xif(np);
5857         err = niu_init_pcs(np);
5858         if (err)
5859                 return err;
5860
5861         err = niu_reset_tx_mac(np);
5862         if (err)
5863                 return err;
5864         niu_init_tx_mac(np);
5865         err = niu_reset_rx_mac(np);
5866         if (err)
5867                 return err;
5868         niu_init_rx_mac(np);
5869
5870         /* This looks hookey but the RX MAC reset we just did will
5871          * undo some of the state we setup in niu_init_tx_mac() so we
5872          * have to call it again.  In particular, the RX MAC reset will
5873          * set the XMAC_MAX register back to it's default value.
5874          */
5875         niu_init_tx_mac(np);
5876         niu_enable_tx_mac(np, 1);
5877
5878         niu_enable_rx_mac(np, 1);
5879
5880         return 0;
5881 }
5882
5883 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5884 {
5885         (void) niu_tx_channel_stop(np, rp->tx_channel);
5886 }
5887
5888 static void niu_stop_tx_channels(struct niu *np)
5889 {
5890         int i;
5891
5892         for (i = 0; i < np->num_tx_rings; i++) {
5893                 struct tx_ring_info *rp = &np->tx_rings[i];
5894
5895                 niu_stop_one_tx_channel(np, rp);
5896         }
5897 }
5898
5899 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5900 {
5901         (void) niu_tx_channel_reset(np, rp->tx_channel);
5902 }
5903
5904 static void niu_reset_tx_channels(struct niu *np)
5905 {
5906         int i;
5907
5908         for (i = 0; i < np->num_tx_rings; i++) {
5909                 struct tx_ring_info *rp = &np->tx_rings[i];
5910
5911                 niu_reset_one_tx_channel(np, rp);
5912         }
5913 }
5914
5915 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5916 {
5917         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5918 }
5919
5920 static void niu_stop_rx_channels(struct niu *np)
5921 {
5922         int i;
5923
5924         for (i = 0; i < np->num_rx_rings; i++) {
5925                 struct rx_ring_info *rp = &np->rx_rings[i];
5926
5927                 niu_stop_one_rx_channel(np, rp);
5928         }
5929 }
5930
5931 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5932 {
5933         int channel = rp->rx_channel;
5934
5935         (void) niu_rx_channel_reset(np, channel);
5936         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5937         nw64(RX_DMA_CTL_STAT(channel), 0);
5938         (void) niu_enable_rx_channel(np, channel, 0);
5939 }
5940
5941 static void niu_reset_rx_channels(struct niu *np)
5942 {
5943         int i;
5944
5945         for (i = 0; i < np->num_rx_rings; i++) {
5946                 struct rx_ring_info *rp = &np->rx_rings[i];
5947
5948                 niu_reset_one_rx_channel(np, rp);
5949         }
5950 }
5951
5952 static void niu_disable_ipp(struct niu *np)
5953 {
5954         u64 rd, wr, val;
5955         int limit;
5956
5957         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5958         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5959         limit = 100;
5960         while (--limit >= 0 && (rd != wr)) {
5961                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5962                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5963         }
5964         if (limit < 0 &&
5965             (rd != 0 && wr != 1)) {
5966                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5967                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5968                         np->dev->name,
5969                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5970                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5971         }
5972
5973         val = nr64_ipp(IPP_CFIG);
5974         val &= ~(IPP_CFIG_IPP_ENABLE |
5975                  IPP_CFIG_DFIFO_ECC_EN |
5976                  IPP_CFIG_DROP_BAD_CRC |
5977                  IPP_CFIG_CKSUM_EN);
5978         nw64_ipp(IPP_CFIG, val);
5979
5980         (void) niu_ipp_reset(np);
5981 }
5982
5983 static int niu_init_hw(struct niu *np)
5984 {
5985         int i, err;
5986
5987         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5988         niu_txc_enable_port(np, 1);
5989         niu_txc_port_dma_enable(np, 1);
5990         niu_txc_set_imask(np, 0);
5991
5992         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5993         for (i = 0; i < np->num_tx_rings; i++) {
5994                 struct tx_ring_info *rp = &np->tx_rings[i];
5995
5996                 err = niu_init_one_tx_channel(np, rp);
5997                 if (err)
5998                         return err;
5999         }
6000
6001         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
6002         err = niu_init_rx_channels(np);
6003         if (err)
6004                 goto out_uninit_tx_channels;
6005
6006         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
6007         err = niu_init_classifier_hw(np);
6008         if (err)
6009                 goto out_uninit_rx_channels;
6010
6011         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
6012         err = niu_init_zcp(np);
6013         if (err)
6014                 goto out_uninit_rx_channels;
6015
6016         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
6017         err = niu_init_ipp(np);
6018         if (err)
6019                 goto out_uninit_rx_channels;
6020
6021         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
6022         err = niu_init_mac(np);
6023         if (err)
6024                 goto out_uninit_ipp;
6025
6026         return 0;
6027
6028 out_uninit_ipp:
6029         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
6030         niu_disable_ipp(np);
6031
6032 out_uninit_rx_channels:
6033         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
6034         niu_stop_rx_channels(np);
6035         niu_reset_rx_channels(np);
6036
6037 out_uninit_tx_channels:
6038         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
6039         niu_stop_tx_channels(np);
6040         niu_reset_tx_channels(np);
6041
6042         return err;
6043 }
6044
6045 static void niu_stop_hw(struct niu *np)
6046 {
6047         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
6048         niu_enable_interrupts(np, 0);
6049
6050         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
6051         niu_enable_rx_mac(np, 0);
6052
6053         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
6054         niu_disable_ipp(np);
6055
6056         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6057         niu_stop_tx_channels(np);
6058
6059         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6060         niu_stop_rx_channels(np);
6061
6062         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6063         niu_reset_tx_channels(np);
6064
6065         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6066         niu_reset_rx_channels(np);
6067 }
6068
6069 static void niu_set_irq_name(struct niu *np)
6070 {
6071         int port = np->port;
6072         int i, j = 1;
6073
6074         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6075
6076         if (port == 0) {
6077                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6078                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6079                 j = 3;
6080         }
6081
6082         for (i = 0; i < np->num_ldg - j; i++) {
6083                 if (i < np->num_rx_rings)
6084                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6085                                 np->dev->name, i);
6086                 else if (i < np->num_tx_rings + np->num_rx_rings)
6087                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6088                                 i - np->num_rx_rings);
6089         }
6090 }
6091
6092 static int niu_request_irq(struct niu *np)
6093 {
6094         int i, j, err;
6095
6096         niu_set_irq_name(np);
6097
6098         err = 0;
6099         for (i = 0; i < np->num_ldg; i++) {
6100                 struct niu_ldg *lp = &np->ldg[i];
6101
6102                 err = request_irq(lp->irq, niu_interrupt,
6103                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6104                                   np->irq_name[i], lp);
6105                 if (err)
6106                         goto out_free_irqs;
6107
6108         }
6109
6110         return 0;
6111
6112 out_free_irqs:
6113         for (j = 0; j < i; j++) {
6114                 struct niu_ldg *lp = &np->ldg[j];
6115
6116                 free_irq(lp->irq, lp);
6117         }
6118         return err;
6119 }
6120
6121 static void niu_free_irq(struct niu *np)
6122 {
6123         int i;
6124
6125         for (i = 0; i < np->num_ldg; i++) {
6126                 struct niu_ldg *lp = &np->ldg[i];
6127
6128                 free_irq(lp->irq, lp);
6129         }
6130 }
6131
6132 static void niu_enable_napi(struct niu *np)
6133 {
6134         int i;
6135
6136         for (i = 0; i < np->num_ldg; i++)
6137                 napi_enable(&np->ldg[i].napi);
6138 }
6139
6140 static void niu_disable_napi(struct niu *np)
6141 {
6142         int i;
6143
6144         for (i = 0; i < np->num_ldg; i++)
6145                 napi_disable(&np->ldg[i].napi);
6146 }
6147
6148 static int niu_open(struct net_device *dev)
6149 {
6150         struct niu *np = netdev_priv(dev);
6151         int err;
6152
6153         netif_carrier_off(dev);
6154
6155         err = niu_alloc_channels(np);
6156         if (err)
6157                 goto out_err;
6158
6159         err = niu_enable_interrupts(np, 0);
6160         if (err)
6161                 goto out_free_channels;
6162
6163         err = niu_request_irq(np);
6164         if (err)
6165                 goto out_free_channels;
6166
6167         niu_enable_napi(np);
6168
6169         spin_lock_irq(&np->lock);
6170
6171         err = niu_init_hw(np);
6172         if (!err) {
6173                 init_timer(&np->timer);
6174                 np->timer.expires = jiffies + HZ;
6175                 np->timer.data = (unsigned long) np;
6176                 np->timer.function = niu_timer;
6177
6178                 err = niu_enable_interrupts(np, 1);
6179                 if (err)
6180                         niu_stop_hw(np);
6181         }
6182
6183         spin_unlock_irq(&np->lock);
6184
6185         if (err) {
6186                 niu_disable_napi(np);
6187                 goto out_free_irq;
6188         }
6189
6190         netif_tx_start_all_queues(dev);
6191
6192         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6193                 netif_carrier_on(dev);
6194
6195         add_timer(&np->timer);
6196
6197         return 0;
6198
6199 out_free_irq:
6200         niu_free_irq(np);
6201
6202 out_free_channels:
6203         niu_free_channels(np);
6204
6205 out_err:
6206         return err;
6207 }
6208
6209 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6210 {
6211         cancel_work_sync(&np->reset_task);
6212
6213         niu_disable_napi(np);
6214         netif_tx_stop_all_queues(dev);
6215
6216         del_timer_sync(&np->timer);
6217
6218         spin_lock_irq(&np->lock);
6219
6220         niu_stop_hw(np);
6221
6222         spin_unlock_irq(&np->lock);
6223 }
6224
6225 static int niu_close(struct net_device *dev)
6226 {
6227         struct niu *np = netdev_priv(dev);
6228
6229         niu_full_shutdown(np, dev);
6230
6231         niu_free_irq(np);
6232
6233         niu_free_channels(np);
6234
6235         niu_handle_led(np, 0);
6236
6237         return 0;
6238 }
6239
6240 static void niu_sync_xmac_stats(struct niu *np)
6241 {
6242         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6243
6244         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6245         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6246
6247         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6248         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6249         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6250         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6251         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6252         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6253         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6254         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6255         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6256         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6257         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6258         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6259         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6260         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6261         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6262         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6263 }
6264
6265 static void niu_sync_bmac_stats(struct niu *np)
6266 {
6267         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6268
6269         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6270         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6271
6272         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6273         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6274         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6275         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6276 }
6277
6278 static void niu_sync_mac_stats(struct niu *np)
6279 {
6280         if (np->flags & NIU_FLAGS_XMAC)
6281                 niu_sync_xmac_stats(np);
6282         else
6283                 niu_sync_bmac_stats(np);
6284 }
6285
6286 static void niu_get_rx_stats(struct niu *np)
6287 {
6288         unsigned long pkts, dropped, errors, bytes;
6289         int i;
6290
6291         pkts = dropped = errors = bytes = 0;
6292         for (i = 0; i < np->num_rx_rings; i++) {
6293                 struct rx_ring_info *rp = &np->rx_rings[i];
6294
6295                 niu_sync_rx_discard_stats(np, rp, 0);
6296
6297                 pkts += rp->rx_packets;
6298                 bytes += rp->rx_bytes;
6299                 dropped += rp->rx_dropped;
6300                 errors += rp->rx_errors;
6301         }
6302         np->dev->stats.rx_packets = pkts;
6303         np->dev->stats.rx_bytes = bytes;
6304         np->dev->stats.rx_dropped = dropped;
6305         np->dev->stats.rx_errors = errors;
6306 }
6307
6308 static void niu_get_tx_stats(struct niu *np)
6309 {
6310         unsigned long pkts, errors, bytes;
6311         int i;
6312
6313         pkts = errors = bytes = 0;
6314         for (i = 0; i < np->num_tx_rings; i++) {
6315                 struct tx_ring_info *rp = &np->tx_rings[i];
6316
6317                 pkts += rp->tx_packets;
6318                 bytes += rp->tx_bytes;
6319                 errors += rp->tx_errors;
6320         }
6321         np->dev->stats.tx_packets = pkts;
6322         np->dev->stats.tx_bytes = bytes;
6323         np->dev->stats.tx_errors = errors;
6324 }
6325
6326 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6327 {
6328         struct niu *np = netdev_priv(dev);
6329
6330         niu_get_rx_stats(np);
6331         niu_get_tx_stats(np);
6332
6333         return &dev->stats;
6334 }
6335
6336 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6337 {
6338         int i;
6339
6340         for (i = 0; i < 16; i++)
6341                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6342 }
6343
6344 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6345 {
6346         int i;
6347
6348         for (i = 0; i < 16; i++)
6349                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6350 }
6351
6352 static void niu_load_hash(struct niu *np, u16 *hash)
6353 {
6354         if (np->flags & NIU_FLAGS_XMAC)
6355                 niu_load_hash_xmac(np, hash);
6356         else
6357                 niu_load_hash_bmac(np, hash);
6358 }
6359
6360 static void niu_set_rx_mode(struct net_device *dev)
6361 {
6362         struct niu *np = netdev_priv(dev);
6363         int i, alt_cnt, err;
6364         struct dev_addr_list *addr;
6365         unsigned long flags;
6366         u16 hash[16] = { 0, };
6367
6368         spin_lock_irqsave(&np->lock, flags);
6369         niu_enable_rx_mac(np, 0);
6370
6371         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6372         if (dev->flags & IFF_PROMISC)
6373                 np->flags |= NIU_FLAGS_PROMISC;
6374         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6375                 np->flags |= NIU_FLAGS_MCAST;
6376
6377         alt_cnt = dev->uc_count;
6378         if (alt_cnt > niu_num_alt_addr(np)) {
6379                 alt_cnt = 0;
6380                 np->flags |= NIU_FLAGS_PROMISC;
6381         }
6382
6383         if (alt_cnt) {
6384                 int index = 0;
6385
6386                 for (addr = dev->uc_list; addr; addr = addr->next) {
6387                         err = niu_set_alt_mac(np, index,
6388                                               addr->da_addr);
6389                         if (err)
6390                                 printk(KERN_WARNING PFX "%s: Error %d "
6391                                        "adding alt mac %d\n",
6392                                        dev->name, err, index);
6393                         err = niu_enable_alt_mac(np, index, 1);
6394                         if (err)
6395                                 printk(KERN_WARNING PFX "%s: Error %d "
6396                                        "enabling alt mac %d\n",
6397                                        dev->name, err, index);
6398
6399                         index++;
6400                 }
6401         } else {
6402                 int alt_start;
6403                 if (np->flags & NIU_FLAGS_XMAC)
6404                         alt_start = 0;
6405                 else
6406                         alt_start = 1;
6407                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6408                         err = niu_enable_alt_mac(np, i, 0);
6409                         if (err)
6410                                 printk(KERN_WARNING PFX "%s: Error %d "
6411                                        "disabling alt mac %d\n",
6412                                        dev->name, err, i);
6413                 }
6414         }
6415         if (dev->flags & IFF_ALLMULTI) {
6416                 for (i = 0; i < 16; i++)
6417                         hash[i] = 0xffff;
6418         } else if (dev->mc_count > 0) {
6419                 for (addr = dev->mc_list; addr; addr = addr->next) {
6420                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6421
6422                         crc >>= 24;
6423                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6424                 }
6425         }
6426
6427         if (np->flags & NIU_FLAGS_MCAST)
6428                 niu_load_hash(np, hash);
6429
6430         niu_enable_rx_mac(np, 1);
6431         spin_unlock_irqrestore(&np->lock, flags);
6432 }
6433
6434 static int niu_set_mac_addr(struct net_device *dev, void *p)
6435 {
6436         struct niu *np = netdev_priv(dev);
6437         struct sockaddr *addr = p;
6438         unsigned long flags;
6439
6440         if (!is_valid_ether_addr(addr->sa_data))
6441                 return -EINVAL;
6442
6443         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6444
6445         if (!netif_running(dev))
6446                 return 0;
6447
6448         spin_lock_irqsave(&np->lock, flags);
6449         niu_enable_rx_mac(np, 0);
6450         niu_set_primary_mac(np, dev->dev_addr);
6451         niu_enable_rx_mac(np, 1);
6452         spin_unlock_irqrestore(&np->lock, flags);
6453
6454         return 0;
6455 }
6456
6457 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6458 {
6459         return -EOPNOTSUPP;
6460 }
6461
6462 static void niu_netif_stop(struct niu *np)
6463 {
6464         np->dev->trans_start = jiffies; /* prevent tx timeout */
6465
6466         niu_disable_napi(np);
6467
6468         netif_tx_disable(np->dev);
6469 }
6470
6471 static void niu_netif_start(struct niu *np)
6472 {
6473         /* NOTE: unconditional netif_wake_queue is only appropriate
6474          * so long as all callers are assured to have free tx slots
6475          * (such as after niu_init_hw).
6476          */
6477         netif_tx_wake_all_queues(np->dev);
6478
6479         niu_enable_napi(np);
6480
6481         niu_enable_interrupts(np, 1);
6482 }
6483
6484 static void niu_reset_buffers(struct niu *np)
6485 {
6486         int i, j, k, err;
6487
6488         if (np->rx_rings) {
6489                 for (i = 0; i < np->num_rx_rings; i++) {
6490                         struct rx_ring_info *rp = &np->rx_rings[i];
6491
6492                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6493                                 struct page *page;
6494
6495                                 page = rp->rxhash[j];
6496                                 while (page) {
6497                                         struct page *next =
6498                                                 (struct page *) page->mapping;
6499                                         u64 base = page->index;
6500                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6501                                         rp->rbr[k++] = cpu_to_le32(base);
6502                                         page = next;
6503                                 }
6504                         }
6505                         for (; k < MAX_RBR_RING_SIZE; k++) {
6506                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6507                                 if (unlikely(err))
6508                                         break;
6509                         }
6510
6511                         rp->rbr_index = rp->rbr_table_size - 1;
6512                         rp->rcr_index = 0;
6513                         rp->rbr_pending = 0;
6514                         rp->rbr_refill_pending = 0;
6515                 }
6516         }
6517         if (np->tx_rings) {
6518                 for (i = 0; i < np->num_tx_rings; i++) {
6519                         struct tx_ring_info *rp = &np->tx_rings[i];
6520
6521                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6522                                 if (rp->tx_buffs[j].skb)
6523                                         (void) release_tx_packet(np, rp, j);
6524                         }
6525
6526                         rp->pending = MAX_TX_RING_SIZE;
6527                         rp->prod = 0;
6528                         rp->cons = 0;
6529                         rp->wrap_bit = 0;
6530                 }
6531         }
6532 }
6533
6534 static void niu_reset_task(struct work_struct *work)
6535 {
6536         struct niu *np = container_of(work, struct niu, reset_task);
6537         unsigned long flags;
6538         int err;
6539
6540         spin_lock_irqsave(&np->lock, flags);
6541         if (!netif_running(np->dev)) {
6542                 spin_unlock_irqrestore(&np->lock, flags);
6543                 return;
6544         }
6545
6546         spin_unlock_irqrestore(&np->lock, flags);
6547
6548         del_timer_sync(&np->timer);
6549
6550         niu_netif_stop(np);
6551
6552         spin_lock_irqsave(&np->lock, flags);
6553
6554         niu_stop_hw(np);
6555
6556         spin_unlock_irqrestore(&np->lock, flags);
6557
6558         niu_reset_buffers(np);
6559
6560         spin_lock_irqsave(&np->lock, flags);
6561
6562         err = niu_init_hw(np);
6563         if (!err) {
6564                 np->timer.expires = jiffies + HZ;
6565                 add_timer(&np->timer);
6566                 niu_netif_start(np);
6567         }
6568
6569         spin_unlock_irqrestore(&np->lock, flags);
6570 }
6571
6572 static void niu_tx_timeout(struct net_device *dev)
6573 {
6574         struct niu *np = netdev_priv(dev);
6575
6576         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6577                 dev->name);
6578
6579         schedule_work(&np->reset_task);
6580 }
6581
6582 static void niu_set_txd(struct tx_ring_info *rp, int index,
6583                         u64 mapping, u64 len, u64 mark,
6584                         u64 n_frags)
6585 {
6586         __le64 *desc = &rp->descr[index];
6587
6588         *desc = cpu_to_le64(mark |
6589                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6590                             (len << TX_DESC_TR_LEN_SHIFT) |
6591                             (mapping & TX_DESC_SAD));
6592 }
6593
6594 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6595                                 u64 pad_bytes, u64 len)
6596 {
6597         u16 eth_proto, eth_proto_inner;
6598         u64 csum_bits, l3off, ihl, ret;
6599         u8 ip_proto;
6600         int ipv6;
6601
6602         eth_proto = be16_to_cpu(ehdr->h_proto);
6603         eth_proto_inner = eth_proto;
6604         if (eth_proto == ETH_P_8021Q) {
6605                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6606                 __be16 val = vp->h_vlan_encapsulated_proto;
6607
6608                 eth_proto_inner = be16_to_cpu(val);
6609         }
6610
6611         ipv6 = ihl = 0;
6612         switch (skb->protocol) {
6613         case cpu_to_be16(ETH_P_IP):
6614                 ip_proto = ip_hdr(skb)->protocol;
6615                 ihl = ip_hdr(skb)->ihl;
6616                 break;
6617         case cpu_to_be16(ETH_P_IPV6):
6618                 ip_proto = ipv6_hdr(skb)->nexthdr;
6619                 ihl = (40 >> 2);
6620                 ipv6 = 1;
6621                 break;
6622         default:
6623                 ip_proto = ihl = 0;
6624                 break;
6625         }
6626
6627         csum_bits = TXHDR_CSUM_NONE;
6628         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6629                 u64 start, stuff;
6630
6631                 csum_bits = (ip_proto == IPPROTO_TCP ?
6632                              TXHDR_CSUM_TCP :
6633                              (ip_proto == IPPROTO_UDP ?
6634                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6635
6636                 start = skb_transport_offset(skb) -
6637                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6638                 stuff = start + skb->csum_offset;
6639
6640                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6641                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6642         }
6643
6644         l3off = skb_network_offset(skb) -
6645                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6646
6647         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6648                (len << TXHDR_LEN_SHIFT) |
6649                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6650                (ihl << TXHDR_IHL_SHIFT) |
6651                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6652                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6653                (ipv6 ? TXHDR_IP_VER : 0) |
6654                csum_bits);
6655
6656         return ret;
6657 }
6658
6659 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6660 {
6661         struct niu *np = netdev_priv(dev);
6662         unsigned long align, headroom;
6663         struct netdev_queue *txq;
6664         struct tx_ring_info *rp;
6665         struct tx_pkt_hdr *tp;
6666         unsigned int len, nfg;
6667         struct ethhdr *ehdr;
6668         int prod, i, tlen;
6669         u64 mapping, mrk;
6670
6671         i = skb_get_queue_mapping(skb);
6672         rp = &np->tx_rings[i];
6673         txq = netdev_get_tx_queue(dev, i);
6674
6675         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6676                 netif_tx_stop_queue(txq);
6677                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6678                         "queue awake!\n", dev->name);
6679                 rp->tx_errors++;
6680                 return NETDEV_TX_BUSY;
6681         }
6682
6683         if (skb->len < ETH_ZLEN) {
6684                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6685
6686                 if (skb_pad(skb, pad_bytes))
6687                         goto out;
6688                 skb_put(skb, pad_bytes);
6689         }
6690
6691         len = sizeof(struct tx_pkt_hdr) + 15;
6692         if (skb_headroom(skb) < len) {
6693                 struct sk_buff *skb_new;
6694
6695                 skb_new = skb_realloc_headroom(skb, len);
6696                 if (!skb_new) {
6697                         rp->tx_errors++;
6698                         goto out_drop;
6699                 }
6700                 kfree_skb(skb);
6701                 skb = skb_new;
6702         } else
6703                 skb_orphan(skb);
6704
6705         align = ((unsigned long) skb->data & (16 - 1));
6706         headroom = align + sizeof(struct tx_pkt_hdr);
6707
6708         ehdr = (struct ethhdr *) skb->data;
6709         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6710
6711         len = skb->len - sizeof(struct tx_pkt_hdr);
6712         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6713         tp->resv = 0;
6714
6715         len = skb_headlen(skb);
6716         mapping = np->ops->map_single(np->device, skb->data,
6717                                       len, DMA_TO_DEVICE);
6718
6719         prod = rp->prod;
6720
6721         rp->tx_buffs[prod].skb = skb;
6722         rp->tx_buffs[prod].mapping = mapping;
6723
6724         mrk = TX_DESC_SOP;
6725         if (++rp->mark_counter == rp->mark_freq) {
6726                 rp->mark_counter = 0;
6727                 mrk |= TX_DESC_MARK;
6728                 rp->mark_pending++;
6729         }
6730
6731         tlen = len;
6732         nfg = skb_shinfo(skb)->nr_frags;
6733         while (tlen > 0) {
6734                 tlen -= MAX_TX_DESC_LEN;
6735                 nfg++;
6736         }
6737
6738         while (len > 0) {
6739                 unsigned int this_len = len;
6740
6741                 if (this_len > MAX_TX_DESC_LEN)
6742                         this_len = MAX_TX_DESC_LEN;
6743
6744                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6745                 mrk = nfg = 0;
6746
6747                 prod = NEXT_TX(rp, prod);
6748                 mapping += this_len;
6749                 len -= this_len;
6750         }
6751
6752         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6753                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6754
6755                 len = frag->size;
6756                 mapping = np->ops->map_page(np->device, frag->page,
6757                                             frag->page_offset, len,
6758                                             DMA_TO_DEVICE);
6759
6760                 rp->tx_buffs[prod].skb = NULL;
6761                 rp->tx_buffs[prod].mapping = mapping;
6762
6763                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6764
6765                 prod = NEXT_TX(rp, prod);
6766         }
6767
6768         if (prod < rp->prod)
6769                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6770         rp->prod = prod;
6771
6772         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6773
6774         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6775                 netif_tx_stop_queue(txq);
6776                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6777                         netif_tx_wake_queue(txq);
6778         }
6779
6780         dev->trans_start = jiffies;
6781
6782 out:
6783         return NETDEV_TX_OK;
6784
6785 out_drop:
6786         rp->tx_errors++;
6787         kfree_skb(skb);
6788         goto out;
6789 }
6790
6791 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6792 {
6793         struct niu *np = netdev_priv(dev);
6794         int err, orig_jumbo, new_jumbo;
6795
6796         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6797                 return -EINVAL;
6798
6799         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6800         new_jumbo = (new_mtu > ETH_DATA_LEN);
6801
6802         dev->mtu = new_mtu;
6803
6804         if (!netif_running(dev) ||
6805             (orig_jumbo == new_jumbo))
6806                 return 0;
6807
6808         niu_full_shutdown(np, dev);
6809
6810         niu_free_channels(np);
6811
6812         niu_enable_napi(np);
6813
6814         err = niu_alloc_channels(np);
6815         if (err)
6816                 return err;
6817
6818         spin_lock_irq(&np->lock);
6819
6820         err = niu_init_hw(np);
6821         if (!err) {
6822                 init_timer(&np->timer);
6823                 np->timer.expires = jiffies + HZ;
6824                 np->timer.data = (unsigned long) np;
6825                 np->timer.function = niu_timer;
6826
6827                 err = niu_enable_interrupts(np, 1);
6828                 if (err)
6829                         niu_stop_hw(np);
6830         }
6831
6832         spin_unlock_irq(&np->lock);
6833
6834         if (!err) {
6835                 netif_tx_start_all_queues(dev);
6836                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6837                         netif_carrier_on(dev);
6838
6839                 add_timer(&np->timer);
6840         }
6841
6842         return err;
6843 }
6844
6845 static void niu_get_drvinfo(struct net_device *dev,
6846                             struct ethtool_drvinfo *info)
6847 {
6848         struct niu *np = netdev_priv(dev);
6849         struct niu_vpd *vpd = &np->vpd;
6850
6851         strcpy(info->driver, DRV_MODULE_NAME);
6852         strcpy(info->version, DRV_MODULE_VERSION);
6853         sprintf(info->fw_version, "%d.%d",
6854                 vpd->fcode_major, vpd->fcode_minor);
6855         if (np->parent->plat_type != PLAT_TYPE_NIU)
6856                 strcpy(info->bus_info, pci_name(np->pdev));
6857 }
6858
6859 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6860 {
6861         struct niu *np = netdev_priv(dev);
6862         struct niu_link_config *lp;
6863
6864         lp = &np->link_config;
6865
6866         memset(cmd, 0, sizeof(*cmd));
6867         cmd->phy_address = np->phy_addr;
6868         cmd->supported = lp->supported;
6869         cmd->advertising = lp->active_advertising;
6870         cmd->autoneg = lp->active_autoneg;
6871         cmd->speed = lp->active_speed;
6872         cmd->duplex = lp->active_duplex;
6873         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6874         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6875                 XCVR_EXTERNAL : XCVR_INTERNAL;
6876
6877         return 0;
6878 }
6879
6880 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6881 {
6882         struct niu *np = netdev_priv(dev);
6883         struct niu_link_config *lp = &np->link_config;
6884
6885         lp->advertising = cmd->advertising;
6886         lp->speed = cmd->speed;
6887         lp->duplex = cmd->duplex;
6888         lp->autoneg = cmd->autoneg;
6889         return niu_init_link(np);
6890 }
6891
6892 static u32 niu_get_msglevel(struct net_device *dev)
6893 {
6894         struct niu *np = netdev_priv(dev);
6895         return np->msg_enable;
6896 }
6897
6898 static void niu_set_msglevel(struct net_device *dev, u32 value)
6899 {
6900         struct niu *np = netdev_priv(dev);
6901         np->msg_enable = value;
6902 }
6903
6904 static int niu_nway_reset(struct net_device *dev)
6905 {
6906         struct niu *np = netdev_priv(dev);
6907
6908         if (np->link_config.autoneg)
6909                 return niu_init_link(np);
6910
6911         return 0;
6912 }
6913
6914 static int niu_get_eeprom_len(struct net_device *dev)
6915 {
6916         struct niu *np = netdev_priv(dev);
6917
6918         return np->eeprom_len;
6919 }
6920
6921 static int niu_get_eeprom(struct net_device *dev,
6922                           struct ethtool_eeprom *eeprom, u8 *data)
6923 {
6924         struct niu *np = netdev_priv(dev);
6925         u32 offset, len, val;
6926
6927         offset = eeprom->offset;
6928         len = eeprom->len;
6929
6930         if (offset + len < offset)
6931                 return -EINVAL;
6932         if (offset >= np->eeprom_len)
6933                 return -EINVAL;
6934         if (offset + len > np->eeprom_len)
6935                 len = eeprom->len = np->eeprom_len - offset;
6936
6937         if (offset & 3) {
6938                 u32 b_offset, b_count;
6939
6940                 b_offset = offset & 3;
6941                 b_count = 4 - b_offset;
6942                 if (b_count > len)
6943                         b_count = len;
6944
6945                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6946                 memcpy(data, ((char *)&val) + b_offset, b_count);
6947                 data += b_count;
6948                 len -= b_count;
6949                 offset += b_count;
6950         }
6951         while (len >= 4) {
6952                 val = nr64(ESPC_NCR(offset / 4));
6953                 memcpy(data, &val, 4);
6954                 data += 4;
6955                 len -= 4;
6956                 offset += 4;
6957         }
6958         if (len) {
6959                 val = nr64(ESPC_NCR(offset / 4));
6960                 memcpy(data, &val, len);
6961         }
6962         return 0;
6963 }
6964
6965 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6966 {
6967         switch (flow_type) {
6968         case TCP_V4_FLOW:
6969         case TCP_V6_FLOW:
6970                 *pid = IPPROTO_TCP;
6971                 break;
6972         case UDP_V4_FLOW:
6973         case UDP_V6_FLOW:
6974                 *pid = IPPROTO_UDP;
6975                 break;
6976         case SCTP_V4_FLOW:
6977         case SCTP_V6_FLOW:
6978                 *pid = IPPROTO_SCTP;
6979                 break;
6980         case AH_V4_FLOW:
6981         case AH_V6_FLOW:
6982                 *pid = IPPROTO_AH;
6983                 break;
6984         case ESP_V4_FLOW:
6985         case ESP_V6_FLOW:
6986                 *pid = IPPROTO_ESP;
6987                 break;
6988         default:
6989                 *pid = 0;
6990                 break;
6991         }
6992 }
6993
6994 static int niu_class_to_ethflow(u64 class, int *flow_type)
6995 {
6996         switch (class) {
6997         case CLASS_CODE_TCP_IPV4:
6998                 *flow_type = TCP_V4_FLOW;
6999                 break;
7000         case CLASS_CODE_UDP_IPV4:
7001                 *flow_type = UDP_V4_FLOW;
7002                 break;
7003         case CLASS_CODE_AH_ESP_IPV4:
7004                 *flow_type = AH_V4_FLOW;
7005                 break;
7006         case CLASS_CODE_SCTP_IPV4:
7007                 *flow_type = SCTP_V4_FLOW;
7008                 break;
7009         case CLASS_CODE_TCP_IPV6:
7010                 *flow_type = TCP_V6_FLOW;
7011                 break;
7012         case CLASS_CODE_UDP_IPV6:
7013                 *flow_type = UDP_V6_FLOW;
7014                 break;
7015         case CLASS_CODE_AH_ESP_IPV6:
7016                 *flow_type = AH_V6_FLOW;
7017                 break;
7018         case CLASS_CODE_SCTP_IPV6:
7019                 *flow_type = SCTP_V6_FLOW;
7020                 break;
7021         case CLASS_CODE_USER_PROG1:
7022         case CLASS_CODE_USER_PROG2:
7023         case CLASS_CODE_USER_PROG3:
7024         case CLASS_CODE_USER_PROG4:
7025                 *flow_type = IP_USER_FLOW;
7026                 break;
7027         default:
7028                 return 0;
7029         }
7030
7031         return 1;
7032 }
7033
7034 static int niu_ethflow_to_class(int flow_type, u64 *class)
7035 {
7036         switch (flow_type) {
7037         case TCP_V4_FLOW:
7038                 *class = CLASS_CODE_TCP_IPV4;
7039                 break;
7040         case UDP_V4_FLOW:
7041                 *class = CLASS_CODE_UDP_IPV4;
7042                 break;
7043         case AH_V4_FLOW:
7044         case ESP_V4_FLOW:
7045                 *class = CLASS_CODE_AH_ESP_IPV4;
7046                 break;
7047         case SCTP_V4_FLOW:
7048                 *class = CLASS_CODE_SCTP_IPV4;
7049                 break;
7050         case TCP_V6_FLOW:
7051                 *class = CLASS_CODE_TCP_IPV6;
7052                 break;
7053         case UDP_V6_FLOW:
7054                 *class = CLASS_CODE_UDP_IPV6;
7055                 break;
7056         case AH_V6_FLOW:
7057         case ESP_V6_FLOW:
7058                 *class = CLASS_CODE_AH_ESP_IPV6;
7059                 break;
7060         case SCTP_V6_FLOW:
7061                 *class = CLASS_CODE_SCTP_IPV6;
7062                 break;
7063         default:
7064                 return 0;
7065         }
7066
7067         return 1;
7068 }
7069
7070 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7071 {
7072         u64 ethflow = 0;
7073
7074         if (flow_key & FLOW_KEY_L2DA)
7075                 ethflow |= RXH_L2DA;
7076         if (flow_key & FLOW_KEY_VLAN)
7077                 ethflow |= RXH_VLAN;
7078         if (flow_key & FLOW_KEY_IPSA)
7079                 ethflow |= RXH_IP_SRC;
7080         if (flow_key & FLOW_KEY_IPDA)
7081                 ethflow |= RXH_IP_DST;
7082         if (flow_key & FLOW_KEY_PROTO)
7083                 ethflow |= RXH_L3_PROTO;
7084         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7085                 ethflow |= RXH_L4_B_0_1;
7086         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7087                 ethflow |= RXH_L4_B_2_3;
7088
7089         return ethflow;
7090
7091 }
7092
7093 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7094 {
7095         u64 key = 0;
7096
7097         if (ethflow & RXH_L2DA)
7098                 key |= FLOW_KEY_L2DA;
7099         if (ethflow & RXH_VLAN)
7100                 key |= FLOW_KEY_VLAN;
7101         if (ethflow & RXH_IP_SRC)
7102                 key |= FLOW_KEY_IPSA;
7103         if (ethflow & RXH_IP_DST)
7104                 key |= FLOW_KEY_IPDA;
7105         if (ethflow & RXH_L3_PROTO)
7106                 key |= FLOW_KEY_PROTO;
7107         if (ethflow & RXH_L4_B_0_1)
7108                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7109         if (ethflow & RXH_L4_B_2_3)
7110                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7111
7112         *flow_key = key;
7113
7114         return 1;
7115
7116 }
7117
7118 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7119 {
7120         u64 class;
7121
7122         nfc->data = 0;
7123
7124         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7125                 return -EINVAL;
7126
7127         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7128             TCAM_KEY_DISC)
7129                 nfc->data = RXH_DISCARD;
7130         else
7131                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7132                                                       CLASS_CODE_USER_PROG1]);
7133         return 0;
7134 }
7135
7136 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7137                                         struct ethtool_rx_flow_spec *fsp)
7138 {
7139
7140         fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7141                 TCAM_V4KEY3_SADDR_SHIFT;
7142         fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7143                 TCAM_V4KEY3_DADDR_SHIFT;
7144         fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7145                 TCAM_V4KEY3_SADDR_SHIFT;
7146         fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7147                 TCAM_V4KEY3_DADDR_SHIFT;
7148
7149         fsp->h_u.tcp_ip4_spec.ip4src =
7150                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7151         fsp->m_u.tcp_ip4_spec.ip4src =
7152                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7153         fsp->h_u.tcp_ip4_spec.ip4dst =
7154                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7155         fsp->m_u.tcp_ip4_spec.ip4dst =
7156                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7157
7158         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7159                 TCAM_V4KEY2_TOS_SHIFT;
7160         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7161                 TCAM_V4KEY2_TOS_SHIFT;
7162
7163         switch (fsp->flow_type) {
7164         case TCP_V4_FLOW:
7165         case UDP_V4_FLOW:
7166         case SCTP_V4_FLOW:
7167                 fsp->h_u.tcp_ip4_spec.psrc =
7168                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7169                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7170                 fsp->h_u.tcp_ip4_spec.pdst =
7171                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7172                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7173                 fsp->m_u.tcp_ip4_spec.psrc =
7174                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7175                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7176                 fsp->m_u.tcp_ip4_spec.pdst =
7177                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7178                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7179
7180                 fsp->h_u.tcp_ip4_spec.psrc =
7181                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7182                 fsp->h_u.tcp_ip4_spec.pdst =
7183                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7184                 fsp->m_u.tcp_ip4_spec.psrc =
7185                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7186                 fsp->m_u.tcp_ip4_spec.pdst =
7187                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7188                 break;
7189         case AH_V4_FLOW:
7190         case ESP_V4_FLOW:
7191                 fsp->h_u.ah_ip4_spec.spi =
7192                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7193                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7194                 fsp->m_u.ah_ip4_spec.spi =
7195                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7196                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7197
7198                 fsp->h_u.ah_ip4_spec.spi =
7199                         cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7200                 fsp->m_u.ah_ip4_spec.spi =
7201                         cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7202                 break;
7203         case IP_USER_FLOW:
7204                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7205                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7206                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7207                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7208                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7209                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7210
7211                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7212                         cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7213                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7214                         cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7215
7216                 fsp->h_u.usr_ip4_spec.proto =
7217                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7218                         TCAM_V4KEY2_PROTO_SHIFT;
7219                 fsp->m_u.usr_ip4_spec.proto =
7220                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7221                         TCAM_V4KEY2_PROTO_SHIFT;
7222
7223                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7224                 break;
7225         default:
7226                 break;
7227         }
7228 }
7229
7230 static int niu_get_ethtool_tcam_entry(struct niu *np,
7231                                       struct ethtool_rxnfc *nfc)
7232 {
7233         struct niu_parent *parent = np->parent;
7234         struct niu_tcam_entry *tp;
7235         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7236         u16 idx;
7237         u64 class;
7238         int ret = 0;
7239
7240         idx = tcam_get_index(np, (u16)nfc->fs.location);
7241
7242         tp = &parent->tcam[idx];
7243         if (!tp->valid) {
7244                 pr_info(PFX "niu%d: %s entry [%d] invalid for idx[%d]\n",
7245                 parent->index, np->dev->name, (u16)nfc->fs.location, idx);
7246                 return -EINVAL;
7247         }
7248
7249         /* fill the flow spec entry */
7250         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7251                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7252         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7253
7254         if (ret < 0) {
7255                 pr_info(PFX "niu%d: %s niu_class_to_ethflow failed\n",
7256                 parent->index, np->dev->name);
7257                 ret = -EINVAL;
7258                 goto out;
7259         }
7260
7261         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7262                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7263                         TCAM_V4KEY2_PROTO_SHIFT;
7264                 if (proto == IPPROTO_ESP) {
7265                         if (fsp->flow_type == AH_V4_FLOW)
7266                                 fsp->flow_type = ESP_V4_FLOW;
7267                         else
7268                                 fsp->flow_type = ESP_V6_FLOW;
7269                 }
7270         }
7271
7272         switch (fsp->flow_type) {
7273         case TCP_V4_FLOW:
7274         case UDP_V4_FLOW:
7275         case SCTP_V4_FLOW:
7276         case AH_V4_FLOW:
7277         case ESP_V4_FLOW:
7278                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7279                 break;
7280         case TCP_V6_FLOW:
7281         case UDP_V6_FLOW:
7282         case SCTP_V6_FLOW:
7283         case AH_V6_FLOW:
7284         case ESP_V6_FLOW:
7285                 /* Not yet implemented */
7286                 ret = -EINVAL;
7287                 break;
7288         case IP_USER_FLOW:
7289                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7290                 break;
7291         default:
7292                 ret = -EINVAL;
7293                 break;
7294         }
7295
7296         if (ret < 0)
7297                 goto out;
7298
7299         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7300                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7301         else
7302                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7303                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7304
7305         /* put the tcam size here */
7306         nfc->data = tcam_get_size(np);
7307 out:
7308         return ret;
7309 }
7310
7311 static int niu_get_ethtool_tcam_all(struct niu *np,
7312                                     struct ethtool_rxnfc *nfc,
7313                                     u32 *rule_locs)
7314 {
7315         struct niu_parent *parent = np->parent;
7316         struct niu_tcam_entry *tp;
7317         int i, idx, cnt;
7318         u16 n_entries;
7319         unsigned long flags;
7320
7321
7322         /* put the tcam size here */
7323         nfc->data = tcam_get_size(np);
7324
7325         niu_lock_parent(np, flags);
7326         n_entries = nfc->rule_cnt;
7327         for (cnt = 0, i = 0; i < nfc->data; i++) {
7328                 idx = tcam_get_index(np, i);
7329                 tp = &parent->tcam[idx];
7330                 if (!tp->valid)
7331                         continue;
7332                 rule_locs[cnt] = i;
7333                 cnt++;
7334         }
7335         niu_unlock_parent(np, flags);
7336
7337         if (n_entries != cnt) {
7338                 /* print warning, this should not happen */
7339                 pr_info(PFX "niu%d: %s In niu_get_ethtool_tcam_all, "
7340                         "n_entries[%d] != cnt[%d]!!!\n\n",
7341                         np->parent->index, np->dev->name, n_entries, cnt);
7342         }
7343
7344         return 0;
7345 }
7346
7347 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7348                        void *rule_locs)
7349 {
7350         struct niu *np = netdev_priv(dev);
7351         int ret = 0;
7352
7353         switch (cmd->cmd) {
7354         case ETHTOOL_GRXFH:
7355                 ret = niu_get_hash_opts(np, cmd);
7356                 break;
7357         case ETHTOOL_GRXRINGS:
7358                 cmd->data = np->num_rx_rings;
7359                 break;
7360         case ETHTOOL_GRXCLSRLCNT:
7361                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7362                 break;
7363         case ETHTOOL_GRXCLSRULE:
7364                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7365                 break;
7366         case ETHTOOL_GRXCLSRLALL:
7367                 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7368                 break;
7369         default:
7370                 ret = -EINVAL;
7371                 break;
7372         }
7373
7374         return ret;
7375 }
7376
7377 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7378 {
7379         u64 class;
7380         u64 flow_key = 0;
7381         unsigned long flags;
7382
7383         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7384                 return -EINVAL;
7385
7386         if (class < CLASS_CODE_USER_PROG1 ||
7387             class > CLASS_CODE_SCTP_IPV6)
7388                 return -EINVAL;
7389
7390         if (nfc->data & RXH_DISCARD) {
7391                 niu_lock_parent(np, flags);
7392                 flow_key = np->parent->tcam_key[class -
7393                                                CLASS_CODE_USER_PROG1];
7394                 flow_key |= TCAM_KEY_DISC;
7395                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7396                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7397                 niu_unlock_parent(np, flags);
7398                 return 0;
7399         } else {
7400                 /* Discard was set before, but is not set now */
7401                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7402                     TCAM_KEY_DISC) {
7403                         niu_lock_parent(np, flags);
7404                         flow_key = np->parent->tcam_key[class -
7405                                                CLASS_CODE_USER_PROG1];
7406                         flow_key &= ~TCAM_KEY_DISC;
7407                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7408                              flow_key);
7409                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7410                                 flow_key;
7411                         niu_unlock_parent(np, flags);
7412                 }
7413         }
7414
7415         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7416                 return -EINVAL;
7417
7418         niu_lock_parent(np, flags);
7419         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7420         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7421         niu_unlock_parent(np, flags);
7422
7423         return 0;
7424 }
7425
7426 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7427                                        struct niu_tcam_entry *tp,
7428                                        int l2_rdc_tab, u64 class)
7429 {
7430         u8 pid = 0;
7431         u32 sip, dip, sipm, dipm, spi, spim;
7432         u16 sport, dport, spm, dpm;
7433
7434         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7435         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7436         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7437         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7438
7439         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7440         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7441         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7442         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7443
7444         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7445         tp->key[3] |= dip;
7446
7447         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7448         tp->key_mask[3] |= dipm;
7449
7450         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7451                        TCAM_V4KEY2_TOS_SHIFT);
7452         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7453                             TCAM_V4KEY2_TOS_SHIFT);
7454         switch (fsp->flow_type) {
7455         case TCP_V4_FLOW:
7456         case UDP_V4_FLOW:
7457         case SCTP_V4_FLOW:
7458                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7459                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7460                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7461                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7462
7463                 tp->key[2] |= (((u64)sport << 16) | dport);
7464                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7465                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7466                 break;
7467         case AH_V4_FLOW:
7468         case ESP_V4_FLOW:
7469                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7470                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7471
7472                 tp->key[2] |= spi;
7473                 tp->key_mask[2] |= spim;
7474                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7475                 break;
7476         case IP_USER_FLOW:
7477                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7478                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7479
7480                 tp->key[2] |= spi;
7481                 tp->key_mask[2] |= spim;
7482                 pid = fsp->h_u.usr_ip4_spec.proto;
7483                 break;
7484         default:
7485                 break;
7486         }
7487
7488         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7489         if (pid) {
7490                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7491         }
7492 }
7493
7494 static int niu_add_ethtool_tcam_entry(struct niu *np,
7495                                       struct ethtool_rxnfc *nfc)
7496 {
7497         struct niu_parent *parent = np->parent;
7498         struct niu_tcam_entry *tp;
7499         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7500         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7501         int l2_rdc_table = rdc_table->first_table_num;
7502         u16 idx;
7503         u64 class;
7504         unsigned long flags;
7505         int err, ret;
7506
7507         ret = 0;
7508
7509         idx = nfc->fs.location;
7510         if (idx >= tcam_get_size(np))
7511                 return -EINVAL;
7512
7513         if (fsp->flow_type == IP_USER_FLOW) {
7514                 int i;
7515                 int add_usr_cls = 0;
7516                 int ipv6 = 0;
7517                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7518                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7519
7520                 niu_lock_parent(np, flags);
7521
7522                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7523                         if (parent->l3_cls[i]) {
7524                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7525                                         class = parent->l3_cls[i];
7526                                         parent->l3_cls_refcnt[i]++;
7527                                         add_usr_cls = 1;
7528                                         break;
7529                                 }
7530                         } else {
7531                                 /* Program new user IP class */
7532                                 switch (i) {
7533                                 case 0:
7534                                         class = CLASS_CODE_USER_PROG1;
7535                                         break;
7536                                 case 1:
7537                                         class = CLASS_CODE_USER_PROG2;
7538                                         break;
7539                                 case 2:
7540                                         class = CLASS_CODE_USER_PROG3;
7541                                         break;
7542                                 case 3:
7543                                         class = CLASS_CODE_USER_PROG4;
7544                                         break;
7545                                 default:
7546                                         break;
7547                                 }
7548                                 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7549                                         ipv6 = 1;
7550                                 ret = tcam_user_ip_class_set(np, class, ipv6,
7551                                                              uspec->proto,
7552                                                              uspec->tos,
7553                                                              umask->tos);
7554                                 if (ret)
7555                                         goto out;
7556
7557                                 ret = tcam_user_ip_class_enable(np, class, 1);
7558                                 if (ret)
7559                                         goto out;
7560                                 parent->l3_cls[i] = class;
7561                                 parent->l3_cls_pid[i] = uspec->proto;
7562                                 parent->l3_cls_refcnt[i]++;
7563                                 add_usr_cls = 1;
7564                                 break;
7565                         }
7566                 }
7567                 if (!add_usr_cls) {
7568                         pr_info(PFX "niu%d: %s niu_add_ethtool_tcam_entry: "
7569                                 "Could not find/insert class for pid %d\n",
7570                                 parent->index, np->dev->name, uspec->proto);
7571                         ret = -EINVAL;
7572                         goto out;
7573                 }
7574                 niu_unlock_parent(np, flags);
7575         } else {
7576                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7577                         return -EINVAL;
7578                 }
7579         }
7580
7581         niu_lock_parent(np, flags);
7582
7583         idx = tcam_get_index(np, idx);
7584         tp = &parent->tcam[idx];
7585
7586         memset(tp, 0, sizeof(*tp));
7587
7588         /* fill in the tcam key and mask */
7589         switch (fsp->flow_type) {
7590         case TCP_V4_FLOW:
7591         case UDP_V4_FLOW:
7592         case SCTP_V4_FLOW:
7593         case AH_V4_FLOW:
7594         case ESP_V4_FLOW:
7595                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7596                 break;
7597         case TCP_V6_FLOW:
7598         case UDP_V6_FLOW:
7599         case SCTP_V6_FLOW:
7600         case AH_V6_FLOW:
7601         case ESP_V6_FLOW:
7602                 /* Not yet implemented */
7603                 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7604                         "flow %d for IPv6 not implemented\n\n",
7605                         parent->index, np->dev->name, fsp->flow_type);
7606                 ret = -EINVAL;
7607                 goto out;
7608         case IP_USER_FLOW:
7609                 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7610                         niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7611                                                    class);
7612                 } else {
7613                         /* Not yet implemented */
7614                         pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7615                         "usr flow for IPv6 not implemented\n\n",
7616                         parent->index, np->dev->name);
7617                         ret = -EINVAL;
7618                         goto out;
7619                 }
7620                 break;
7621         default:
7622                 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7623                         "Unknown flow type %d\n\n",
7624                         parent->index, np->dev->name, fsp->flow_type);
7625                 ret = -EINVAL;
7626                 goto out;
7627         }
7628
7629         /* fill in the assoc data */
7630         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7631                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7632         } else {
7633                 if (fsp->ring_cookie >= np->num_rx_rings) {
7634                         pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7635                                 "Invalid RX ring %lld\n\n",
7636                                 parent->index, np->dev->name,
7637                                 (long long) fsp->ring_cookie);
7638                         ret = -EINVAL;
7639                         goto out;
7640                 }
7641                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7642                                   (fsp->ring_cookie <<
7643                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7644         }
7645
7646         err = tcam_write(np, idx, tp->key, tp->key_mask);
7647         if (err) {
7648                 ret = -EINVAL;
7649                 goto out;
7650         }
7651         err = tcam_assoc_write(np, idx, tp->assoc_data);
7652         if (err) {
7653                 ret = -EINVAL;
7654                 goto out;
7655         }
7656
7657         /* validate the entry */
7658         tp->valid = 1;
7659         np->clas.tcam_valid_entries++;
7660 out:
7661         niu_unlock_parent(np, flags);
7662
7663         return ret;
7664 }
7665
7666 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7667 {
7668         struct niu_parent *parent = np->parent;
7669         struct niu_tcam_entry *tp;
7670         u16 idx;
7671         unsigned long flags;
7672         u64 class;
7673         int ret = 0;
7674
7675         if (loc >= tcam_get_size(np))
7676                 return -EINVAL;
7677
7678         niu_lock_parent(np, flags);
7679
7680         idx = tcam_get_index(np, loc);
7681         tp = &parent->tcam[idx];
7682
7683         /* if the entry is of a user defined class, then update*/
7684         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7685                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7686
7687         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7688                 int i;
7689                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7690                         if (parent->l3_cls[i] == class) {
7691                                 parent->l3_cls_refcnt[i]--;
7692                                 if (!parent->l3_cls_refcnt[i]) {
7693                                         /* disable class */
7694                                         ret = tcam_user_ip_class_enable(np,
7695                                                                         class,
7696                                                                         0);
7697                                         if (ret)
7698                                                 goto out;
7699                                         parent->l3_cls[i] = 0;
7700                                         parent->l3_cls_pid[i] = 0;
7701                                 }
7702                                 break;
7703                         }
7704                 }
7705                 if (i == NIU_L3_PROG_CLS) {
7706                         pr_info(PFX "niu%d: %s In niu_del_ethtool_tcam_entry,"
7707                                 "Usr class 0x%llx not found \n",
7708                                 parent->index, np->dev->name,
7709                                 (unsigned long long) class);
7710                         ret = -EINVAL;
7711                         goto out;
7712                 }
7713         }
7714
7715         ret = tcam_flush(np, idx);
7716         if (ret)
7717                 goto out;
7718
7719         /* invalidate the entry */
7720         tp->valid = 0;
7721         np->clas.tcam_valid_entries--;
7722 out:
7723         niu_unlock_parent(np, flags);
7724
7725         return ret;
7726 }
7727
7728 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7729 {
7730         struct niu *np = netdev_priv(dev);
7731         int ret = 0;
7732
7733         switch (cmd->cmd) {
7734         case ETHTOOL_SRXFH:
7735                 ret = niu_set_hash_opts(np, cmd);
7736                 break;
7737         case ETHTOOL_SRXCLSRLINS:
7738                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7739                 break;
7740         case ETHTOOL_SRXCLSRLDEL:
7741                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7742                 break;
7743         default:
7744                 ret = -EINVAL;
7745                 break;
7746         }
7747
7748         return ret;
7749 }
7750
7751 static const struct {
7752         const char string[ETH_GSTRING_LEN];
7753 } niu_xmac_stat_keys[] = {
7754         { "tx_frames" },
7755         { "tx_bytes" },
7756         { "tx_fifo_errors" },
7757         { "tx_overflow_errors" },
7758         { "tx_max_pkt_size_errors" },
7759         { "tx_underflow_errors" },
7760         { "rx_local_faults" },
7761         { "rx_remote_faults" },
7762         { "rx_link_faults" },
7763         { "rx_align_errors" },
7764         { "rx_frags" },
7765         { "rx_mcasts" },
7766         { "rx_bcasts" },
7767         { "rx_hist_cnt1" },
7768         { "rx_hist_cnt2" },
7769         { "rx_hist_cnt3" },
7770         { "rx_hist_cnt4" },
7771         { "rx_hist_cnt5" },
7772         { "rx_hist_cnt6" },
7773         { "rx_hist_cnt7" },
7774         { "rx_octets" },
7775         { "rx_code_violations" },
7776         { "rx_len_errors" },
7777         { "rx_crc_errors" },
7778         { "rx_underflows" },
7779         { "rx_overflows" },
7780         { "pause_off_state" },
7781         { "pause_on_state" },
7782         { "pause_received" },
7783 };
7784
7785 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7786
7787 static const struct {
7788         const char string[ETH_GSTRING_LEN];
7789 } niu_bmac_stat_keys[] = {
7790         { "tx_underflow_errors" },
7791         { "tx_max_pkt_size_errors" },
7792         { "tx_bytes" },
7793         { "tx_frames" },
7794         { "rx_overflows" },
7795         { "rx_frames" },
7796         { "rx_align_errors" },
7797         { "rx_crc_errors" },
7798         { "rx_len_errors" },
7799         { "pause_off_state" },
7800         { "pause_on_state" },
7801         { "pause_received" },
7802 };
7803
7804 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7805
7806 static const struct {
7807         const char string[ETH_GSTRING_LEN];
7808 } niu_rxchan_stat_keys[] = {
7809         { "rx_channel" },
7810         { "rx_packets" },
7811         { "rx_bytes" },
7812         { "rx_dropped" },
7813         { "rx_errors" },
7814 };
7815
7816 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7817
7818 static const struct {
7819         const char string[ETH_GSTRING_LEN];
7820 } niu_txchan_stat_keys[] = {
7821         { "tx_channel" },
7822         { "tx_packets" },
7823         { "tx_bytes" },
7824         { "tx_errors" },
7825 };
7826
7827 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7828
7829 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7830 {
7831         struct niu *np = netdev_priv(dev);
7832         int i;
7833
7834         if (stringset != ETH_SS_STATS)
7835                 return;
7836
7837         if (np->flags & NIU_FLAGS_XMAC) {
7838                 memcpy(data, niu_xmac_stat_keys,
7839                        sizeof(niu_xmac_stat_keys));
7840                 data += sizeof(niu_xmac_stat_keys);
7841         } else {
7842                 memcpy(data, niu_bmac_stat_keys,
7843                        sizeof(niu_bmac_stat_keys));
7844                 data += sizeof(niu_bmac_stat_keys);
7845         }
7846         for (i = 0; i < np->num_rx_rings; i++) {
7847                 memcpy(data, niu_rxchan_stat_keys,
7848                        sizeof(niu_rxchan_stat_keys));
7849                 data += sizeof(niu_rxchan_stat_keys);
7850         }
7851         for (i = 0; i < np->num_tx_rings; i++) {
7852                 memcpy(data, niu_txchan_stat_keys,
7853                        sizeof(niu_txchan_stat_keys));
7854                 data += sizeof(niu_txchan_stat_keys);
7855         }
7856 }
7857
7858 static int niu_get_stats_count(struct net_device *dev)
7859 {
7860         struct niu *np = netdev_priv(dev);
7861
7862         return ((np->flags & NIU_FLAGS_XMAC ?
7863                  NUM_XMAC_STAT_KEYS :
7864                  NUM_BMAC_STAT_KEYS) +
7865                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7866                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7867 }
7868
7869 static void niu_get_ethtool_stats(struct net_device *dev,
7870                                   struct ethtool_stats *stats, u64 *data)
7871 {
7872         struct niu *np = netdev_priv(dev);
7873         int i;
7874
7875         niu_sync_mac_stats(np);
7876         if (np->flags & NIU_FLAGS_XMAC) {
7877                 memcpy(data, &np->mac_stats.xmac,
7878                        sizeof(struct niu_xmac_stats));
7879                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7880         } else {
7881                 memcpy(data, &np->mac_stats.bmac,
7882                        sizeof(struct niu_bmac_stats));
7883                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7884         }
7885         for (i = 0; i < np->num_rx_rings; i++) {
7886                 struct rx_ring_info *rp = &np->rx_rings[i];
7887
7888                 niu_sync_rx_discard_stats(np, rp, 0);
7889
7890                 data[0] = rp->rx_channel;
7891                 data[1] = rp->rx_packets;
7892                 data[2] = rp->rx_bytes;
7893                 data[3] = rp->rx_dropped;
7894                 data[4] = rp->rx_errors;
7895                 data += 5;
7896         }
7897         for (i = 0; i < np->num_tx_rings; i++) {
7898                 struct tx_ring_info *rp = &np->tx_rings[i];
7899
7900                 data[0] = rp->tx_channel;
7901                 data[1] = rp->tx_packets;
7902                 data[2] = rp->tx_bytes;
7903                 data[3] = rp->tx_errors;
7904                 data += 4;
7905         }
7906 }
7907
7908 static u64 niu_led_state_save(struct niu *np)
7909 {
7910         if (np->flags & NIU_FLAGS_XMAC)
7911                 return nr64_mac(XMAC_CONFIG);
7912         else
7913                 return nr64_mac(BMAC_XIF_CONFIG);
7914 }
7915
7916 static void niu_led_state_restore(struct niu *np, u64 val)
7917 {
7918         if (np->flags & NIU_FLAGS_XMAC)
7919                 nw64_mac(XMAC_CONFIG, val);
7920         else
7921                 nw64_mac(BMAC_XIF_CONFIG, val);
7922 }
7923
7924 static void niu_force_led(struct niu *np, int on)
7925 {
7926         u64 val, reg, bit;
7927
7928         if (np->flags & NIU_FLAGS_XMAC) {
7929                 reg = XMAC_CONFIG;
7930                 bit = XMAC_CONFIG_FORCE_LED_ON;
7931         } else {
7932                 reg = BMAC_XIF_CONFIG;
7933                 bit = BMAC_XIF_CONFIG_LINK_LED;
7934         }
7935
7936         val = nr64_mac(reg);
7937         if (on)
7938                 val |= bit;
7939         else
7940                 val &= ~bit;
7941         nw64_mac(reg, val);
7942 }
7943
7944 static int niu_phys_id(struct net_device *dev, u32 data)
7945 {
7946         struct niu *np = netdev_priv(dev);
7947         u64 orig_led_state;
7948         int i;
7949
7950         if (!netif_running(dev))
7951                 return -EAGAIN;
7952
7953         if (data == 0)
7954                 data = 2;
7955
7956         orig_led_state = niu_led_state_save(np);
7957         for (i = 0; i < (data * 2); i++) {
7958                 int on = ((i % 2) == 0);
7959
7960                 niu_force_led(np, on);
7961
7962                 if (msleep_interruptible(500))
7963                         break;
7964         }
7965         niu_led_state_restore(np, orig_led_state);
7966
7967         return 0;
7968 }
7969
7970 static const struct ethtool_ops niu_ethtool_ops = {
7971         .get_drvinfo            = niu_get_drvinfo,
7972         .get_link               = ethtool_op_get_link,
7973         .get_msglevel           = niu_get_msglevel,
7974         .set_msglevel           = niu_set_msglevel,
7975         .nway_reset             = niu_nway_reset,
7976         .get_eeprom_len         = niu_get_eeprom_len,
7977         .get_eeprom             = niu_get_eeprom,
7978         .get_settings           = niu_get_settings,
7979         .set_settings           = niu_set_settings,
7980         .get_strings            = niu_get_strings,
7981         .get_stats_count        = niu_get_stats_count,
7982         .get_ethtool_stats      = niu_get_ethtool_stats,
7983         .phys_id                = niu_phys_id,
7984         .get_rxnfc              = niu_get_nfc,
7985         .set_rxnfc              = niu_set_nfc,
7986 };
7987
7988 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7989                               int ldg, int ldn)
7990 {
7991         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7992                 return -EINVAL;
7993         if (ldn < 0 || ldn > LDN_MAX)
7994                 return -EINVAL;
7995
7996         parent->ldg_map[ldn] = ldg;
7997
7998         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7999                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
8000                  * the firmware, and we're not supposed to change them.
8001                  * Validate the mapping, because if it's wrong we probably
8002                  * won't get any interrupts and that's painful to debug.
8003                  */
8004                 if (nr64(LDG_NUM(ldn)) != ldg) {
8005                         dev_err(np->device, PFX "Port %u, mis-matched "
8006                                 "LDG assignment "
8007                                 "for ldn %d, should be %d is %llu\n",
8008                                 np->port, ldn, ldg,
8009                                 (unsigned long long) nr64(LDG_NUM(ldn)));
8010                         return -EINVAL;
8011                 }
8012         } else
8013                 nw64(LDG_NUM(ldn), ldg);
8014
8015         return 0;
8016 }
8017
8018 static int niu_set_ldg_timer_res(struct niu *np, int res)
8019 {
8020         if (res < 0 || res > LDG_TIMER_RES_VAL)
8021                 return -EINVAL;
8022
8023
8024         nw64(LDG_TIMER_RES, res);
8025
8026         return 0;
8027 }
8028
8029 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
8030 {
8031         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
8032             (func < 0 || func > 3) ||
8033             (vector < 0 || vector > 0x1f))
8034                 return -EINVAL;
8035
8036         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
8037
8038         return 0;
8039 }
8040
8041 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
8042 {
8043         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
8044                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
8045         int limit;
8046
8047         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8048                 return -EINVAL;
8049
8050         frame = frame_base;
8051         nw64(ESPC_PIO_STAT, frame);
8052         limit = 64;
8053         do {
8054                 udelay(5);
8055                 frame = nr64(ESPC_PIO_STAT);
8056                 if (frame & ESPC_PIO_STAT_READ_END)
8057                         break;
8058         } while (limit--);
8059         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8060                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
8061                         (unsigned long long) frame);
8062                 return -ENODEV;
8063         }
8064
8065         frame = frame_base;
8066         nw64(ESPC_PIO_STAT, frame);
8067         limit = 64;
8068         do {
8069                 udelay(5);
8070                 frame = nr64(ESPC_PIO_STAT);
8071                 if (frame & ESPC_PIO_STAT_READ_END)
8072                         break;
8073         } while (limit--);
8074         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8075                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
8076                         (unsigned long long) frame);
8077                 return -ENODEV;
8078         }
8079
8080         frame = nr64(ESPC_PIO_STAT);
8081         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8082 }
8083
8084 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8085 {
8086         int err = niu_pci_eeprom_read(np, off);
8087         u16 val;
8088
8089         if (err < 0)
8090                 return err;
8091         val = (err << 8);
8092         err = niu_pci_eeprom_read(np, off + 1);
8093         if (err < 0)
8094                 return err;
8095         val |= (err & 0xff);
8096
8097         return val;
8098 }
8099
8100 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8101 {
8102         int err = niu_pci_eeprom_read(np, off);
8103         u16 val;
8104
8105         if (err < 0)
8106                 return err;
8107
8108         val = (err & 0xff);
8109         err = niu_pci_eeprom_read(np, off + 1);
8110         if (err < 0)
8111                 return err;
8112
8113         val |= (err & 0xff) << 8;
8114
8115         return val;
8116 }
8117
8118 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8119                                               u32 off,
8120                                               char *namebuf,
8121                                               int namebuf_len)
8122 {
8123         int i;
8124
8125         for (i = 0; i < namebuf_len; i++) {
8126                 int err = niu_pci_eeprom_read(np, off + i);
8127                 if (err < 0)
8128                         return err;
8129                 *namebuf++ = err;
8130                 if (!err)
8131                         break;
8132         }
8133         if (i >= namebuf_len)
8134                 return -EINVAL;
8135
8136         return i + 1;
8137 }
8138
8139 static void __devinit niu_vpd_parse_version(struct niu *np)
8140 {
8141         struct niu_vpd *vpd = &np->vpd;
8142         int len = strlen(vpd->version) + 1;
8143         const char *s = vpd->version;
8144         int i;
8145
8146         for (i = 0; i < len - 5; i++) {
8147                 if (!strncmp(s + i, "FCode ", 5))
8148                         break;
8149         }
8150         if (i >= len - 5)
8151                 return;
8152
8153         s += i + 5;
8154         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8155
8156         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8157                vpd->fcode_major, vpd->fcode_minor);
8158         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8159             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8160              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8161                 np->flags |= NIU_FLAGS_VPD_VALID;
8162 }
8163
8164 /* ESPC_PIO_EN_ENABLE must be set */
8165 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8166                                             u32 start, u32 end)
8167 {
8168         unsigned int found_mask = 0;
8169 #define FOUND_MASK_MODEL        0x00000001
8170 #define FOUND_MASK_BMODEL       0x00000002
8171 #define FOUND_MASK_VERS         0x00000004
8172 #define FOUND_MASK_MAC          0x00000008
8173 #define FOUND_MASK_NMAC         0x00000010
8174 #define FOUND_MASK_PHY          0x00000020
8175 #define FOUND_MASK_ALL          0x0000003f
8176
8177         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
8178                start, end);
8179         while (start < end) {
8180                 int len, err, instance, type, prop_len;
8181                 char namebuf[64];
8182                 u8 *prop_buf;
8183                 int max_len;
8184
8185                 if (found_mask == FOUND_MASK_ALL) {
8186                         niu_vpd_parse_version(np);
8187                         return 1;
8188                 }
8189
8190                 err = niu_pci_eeprom_read(np, start + 2);
8191                 if (err < 0)
8192                         return err;
8193                 len = err;
8194                 start += 3;
8195
8196                 instance = niu_pci_eeprom_read(np, start);
8197                 type = niu_pci_eeprom_read(np, start + 3);
8198                 prop_len = niu_pci_eeprom_read(np, start + 4);
8199                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8200                 if (err < 0)
8201                         return err;
8202
8203                 prop_buf = NULL;
8204                 max_len = 0;
8205                 if (!strcmp(namebuf, "model")) {
8206                         prop_buf = np->vpd.model;
8207                         max_len = NIU_VPD_MODEL_MAX;
8208                         found_mask |= FOUND_MASK_MODEL;
8209                 } else if (!strcmp(namebuf, "board-model")) {
8210                         prop_buf = np->vpd.board_model;
8211                         max_len = NIU_VPD_BD_MODEL_MAX;
8212                         found_mask |= FOUND_MASK_BMODEL;
8213                 } else if (!strcmp(namebuf, "version")) {
8214                         prop_buf = np->vpd.version;
8215                         max_len = NIU_VPD_VERSION_MAX;
8216                         found_mask |= FOUND_MASK_VERS;
8217                 } else if (!strcmp(namebuf, "local-mac-address")) {
8218                         prop_buf = np->vpd.local_mac;
8219                         max_len = ETH_ALEN;
8220                         found_mask |= FOUND_MASK_MAC;
8221                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8222                         prop_buf = &np->vpd.mac_num;
8223                         max_len = 1;
8224                         found_mask |= FOUND_MASK_NMAC;
8225                 } else if (!strcmp(namebuf, "phy-type")) {
8226                         prop_buf = np->vpd.phy_type;
8227                         max_len = NIU_VPD_PHY_TYPE_MAX;
8228                         found_mask |= FOUND_MASK_PHY;
8229                 }
8230
8231                 if (max_len && prop_len > max_len) {
8232                         dev_err(np->device, PFX "Property '%s' length (%d) is "
8233                                 "too long.\n", namebuf, prop_len);
8234                         return -EINVAL;
8235                 }
8236
8237                 if (prop_buf) {
8238                         u32 off = start + 5 + err;
8239                         int i;
8240
8241                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
8242                                "len[%d]\n", namebuf, prop_len);
8243                         for (i = 0; i < prop_len; i++)
8244                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8245                 }
8246
8247                 start += len;
8248         }
8249
8250         return 0;
8251 }
8252
8253 /* ESPC_PIO_EN_ENABLE must be set */
8254 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8255 {
8256         u32 offset;
8257         int err;
8258
8259         err = niu_pci_eeprom_read16_swp(np, start + 1);
8260         if (err < 0)
8261                 return;
8262
8263         offset = err + 3;
8264
8265         while (start + offset < ESPC_EEPROM_SIZE) {
8266                 u32 here = start + offset;
8267                 u32 end;
8268
8269                 err = niu_pci_eeprom_read(np, here);
8270                 if (err != 0x90)
8271                         return;
8272
8273                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8274                 if (err < 0)
8275                         return;
8276
8277                 here = start + offset + 3;
8278                 end = start + offset + err;
8279
8280                 offset += err;
8281
8282                 err = niu_pci_vpd_scan_props(np, here, end);
8283                 if (err < 0 || err == 1)
8284                         return;
8285         }
8286 }
8287
8288 /* ESPC_PIO_EN_ENABLE must be set */
8289 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8290 {
8291         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8292         int err;
8293
8294         while (start < end) {
8295                 ret = start;
8296
8297                 /* ROM header signature?  */
8298                 err = niu_pci_eeprom_read16(np, start +  0);
8299                 if (err != 0x55aa)
8300                         return 0;
8301
8302                 /* Apply offset to PCI data structure.  */
8303                 err = niu_pci_eeprom_read16(np, start + 23);
8304                 if (err < 0)
8305                         return 0;
8306                 start += err;
8307
8308                 /* Check for "PCIR" signature.  */
8309                 err = niu_pci_eeprom_read16(np, start +  0);
8310                 if (err != 0x5043)
8311                         return 0;
8312                 err = niu_pci_eeprom_read16(np, start +  2);
8313                 if (err != 0x4952)
8314                         return 0;
8315
8316                 /* Check for OBP image type.  */
8317                 err = niu_pci_eeprom_read(np, start + 20);
8318                 if (err < 0)
8319                         return 0;
8320                 if (err != 0x01) {
8321                         err = niu_pci_eeprom_read(np, ret + 2);
8322                         if (err < 0)
8323                                 return 0;
8324
8325                         start = ret + (err * 512);
8326                         continue;
8327                 }
8328
8329                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8330                 if (err < 0)
8331                         return err;
8332                 ret += err;
8333
8334                 err = niu_pci_eeprom_read(np, ret + 0);
8335                 if (err != 0x82)
8336                         return 0;
8337
8338                 return ret;
8339         }
8340
8341         return 0;
8342 }
8343
8344 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8345                                               const char *phy_prop)
8346 {
8347         if (!strcmp(phy_prop, "mif")) {
8348                 /* 1G copper, MII */
8349                 np->flags &= ~(NIU_FLAGS_FIBER |
8350                                NIU_FLAGS_10G);
8351                 np->mac_xcvr = MAC_XCVR_MII;
8352         } else if (!strcmp(phy_prop, "xgf")) {
8353                 /* 10G fiber, XPCS */
8354                 np->flags |= (NIU_FLAGS_10G |
8355                               NIU_FLAGS_FIBER);
8356                 np->mac_xcvr = MAC_XCVR_XPCS;
8357         } else if (!strcmp(phy_prop, "pcs")) {
8358                 /* 1G fiber, PCS */
8359                 np->flags &= ~NIU_FLAGS_10G;
8360                 np->flags |= NIU_FLAGS_FIBER;
8361                 np->mac_xcvr = MAC_XCVR_PCS;
8362         } else if (!strcmp(phy_prop, "xgc")) {
8363                 /* 10G copper, XPCS */
8364                 np->flags |= NIU_FLAGS_10G;
8365                 np->flags &= ~NIU_FLAGS_FIBER;
8366                 np->mac_xcvr = MAC_XCVR_XPCS;
8367         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8368                 /* 10G Serdes or 1G Serdes, default to 10G */
8369                 np->flags |= NIU_FLAGS_10G;
8370                 np->flags &= ~NIU_FLAGS_FIBER;
8371                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8372                 np->mac_xcvr = MAC_XCVR_XPCS;
8373         } else {
8374                 return -EINVAL;
8375         }
8376         return 0;
8377 }
8378
8379 static int niu_pci_vpd_get_nports(struct niu *np)
8380 {
8381         int ports = 0;
8382
8383         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8384             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8385             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8386             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8387             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8388                 ports = 4;
8389         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8390                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8391                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8392                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8393                 ports = 2;
8394         }
8395
8396         return ports;
8397 }
8398
8399 static void __devinit niu_pci_vpd_validate(struct niu *np)
8400 {
8401         struct net_device *dev = np->dev;
8402         struct niu_vpd *vpd = &np->vpd;
8403         u8 val8;
8404
8405         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8406                 dev_err(np->device, PFX "VPD MAC invalid, "
8407                         "falling back to SPROM.\n");
8408
8409                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8410                 return;
8411         }
8412
8413         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8414             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8415                 np->flags |= NIU_FLAGS_10G;
8416                 np->flags &= ~NIU_FLAGS_FIBER;
8417                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8418                 np->mac_xcvr = MAC_XCVR_PCS;
8419                 if (np->port > 1) {
8420                         np->flags |= NIU_FLAGS_FIBER;
8421                         np->flags &= ~NIU_FLAGS_10G;
8422                 }
8423                 if (np->flags & NIU_FLAGS_10G)
8424                          np->mac_xcvr = MAC_XCVR_XPCS;
8425         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8426                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8427                               NIU_FLAGS_HOTPLUG_PHY);
8428         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8429                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
8430                         np->vpd.phy_type);
8431                 dev_err(np->device, PFX "Falling back to SPROM.\n");
8432                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8433                 return;
8434         }
8435
8436         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8437
8438         val8 = dev->perm_addr[5];
8439         dev->perm_addr[5] += np->port;
8440         if (dev->perm_addr[5] < val8)
8441                 dev->perm_addr[4]++;
8442
8443         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8444 }
8445
8446 static int __devinit niu_pci_probe_sprom(struct niu *np)
8447 {
8448         struct net_device *dev = np->dev;
8449         int len, i;
8450         u64 val, sum;
8451         u8 val8;
8452
8453         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8454         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8455         len = val / 4;
8456
8457         np->eeprom_len = len;
8458
8459         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
8460
8461         sum = 0;
8462         for (i = 0; i < len; i++) {
8463                 val = nr64(ESPC_NCR(i));
8464                 sum += (val >>  0) & 0xff;
8465                 sum += (val >>  8) & 0xff;
8466                 sum += (val >> 16) & 0xff;
8467                 sum += (val >> 24) & 0xff;
8468         }
8469         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
8470         if ((sum & 0xff) != 0xab) {
8471                 dev_err(np->device, PFX "Bad SPROM checksum "
8472                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
8473                 return -EINVAL;
8474         }
8475
8476         val = nr64(ESPC_PHY_TYPE);
8477         switch (np->port) {
8478         case 0:
8479                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8480                         ESPC_PHY_TYPE_PORT0_SHIFT;
8481                 break;
8482         case 1:
8483                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8484                         ESPC_PHY_TYPE_PORT1_SHIFT;
8485                 break;
8486         case 2:
8487                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8488                         ESPC_PHY_TYPE_PORT2_SHIFT;
8489                 break;
8490         case 3:
8491                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8492                         ESPC_PHY_TYPE_PORT3_SHIFT;
8493                 break;
8494         default:
8495                 dev_err(np->device, PFX "Bogus port number %u\n",
8496                         np->port);
8497                 return -EINVAL;
8498         }
8499         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
8500
8501         switch (val8) {
8502         case ESPC_PHY_TYPE_1G_COPPER:
8503                 /* 1G copper, MII */
8504                 np->flags &= ~(NIU_FLAGS_FIBER |
8505                                NIU_FLAGS_10G);
8506                 np->mac_xcvr = MAC_XCVR_MII;
8507                 break;
8508
8509         case ESPC_PHY_TYPE_1G_FIBER:
8510                 /* 1G fiber, PCS */
8511                 np->flags &= ~NIU_FLAGS_10G;
8512                 np->flags |= NIU_FLAGS_FIBER;
8513                 np->mac_xcvr = MAC_XCVR_PCS;
8514                 break;
8515
8516         case ESPC_PHY_TYPE_10G_COPPER:
8517                 /* 10G copper, XPCS */
8518                 np->flags |= NIU_FLAGS_10G;
8519                 np->flags &= ~NIU_FLAGS_FIBER;
8520                 np->mac_xcvr = MAC_XCVR_XPCS;
8521                 break;
8522
8523         case ESPC_PHY_TYPE_10G_FIBER:
8524                 /* 10G fiber, XPCS */
8525                 np->flags |= (NIU_FLAGS_10G |
8526                               NIU_FLAGS_FIBER);
8527                 np->mac_xcvr = MAC_XCVR_XPCS;
8528                 break;
8529
8530         default:
8531                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
8532                 return -EINVAL;
8533         }
8534
8535         val = nr64(ESPC_MAC_ADDR0);
8536         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
8537                (unsigned long long) val);
8538         dev->perm_addr[0] = (val >>  0) & 0xff;
8539         dev->perm_addr[1] = (val >>  8) & 0xff;
8540         dev->perm_addr[2] = (val >> 16) & 0xff;
8541         dev->perm_addr[3] = (val >> 24) & 0xff;
8542
8543         val = nr64(ESPC_MAC_ADDR1);
8544         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
8545                (unsigned long long) val);
8546         dev->perm_addr[4] = (val >>  0) & 0xff;
8547         dev->perm_addr[5] = (val >>  8) & 0xff;
8548
8549         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8550                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
8551                 dev_err(np->device, PFX "[ \n");
8552                 for (i = 0; i < 6; i++)
8553                         printk("%02x ", dev->perm_addr[i]);
8554                 printk("]\n");
8555                 return -EINVAL;
8556         }
8557
8558         val8 = dev->perm_addr[5];
8559         dev->perm_addr[5] += np->port;
8560         if (dev->perm_addr[5] < val8)
8561                 dev->perm_addr[4]++;
8562
8563         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8564
8565         val = nr64(ESPC_MOD_STR_LEN);
8566         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
8567                (unsigned long long) val);
8568         if (val >= 8 * 4)
8569                 return -EINVAL;
8570
8571         for (i = 0; i < val; i += 4) {
8572                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8573
8574                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8575                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8576                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8577                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8578         }
8579         np->vpd.model[val] = '\0';
8580
8581         val = nr64(ESPC_BD_MOD_STR_LEN);
8582         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
8583                (unsigned long long) val);
8584         if (val >= 4 * 4)
8585                 return -EINVAL;
8586
8587         for (i = 0; i < val; i += 4) {
8588                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8589
8590                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8591                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8592                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8593                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8594         }
8595         np->vpd.board_model[val] = '\0';
8596
8597         np->vpd.mac_num =
8598                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8599         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
8600                np->vpd.mac_num);
8601
8602         return 0;
8603 }
8604
8605 static int __devinit niu_get_and_validate_port(struct niu *np)
8606 {
8607         struct niu_parent *parent = np->parent;
8608
8609         if (np->port <= 1)
8610                 np->flags |= NIU_FLAGS_XMAC;
8611
8612         if (!parent->num_ports) {
8613                 if (parent->plat_type == PLAT_TYPE_NIU) {
8614                         parent->num_ports = 2;
8615                 } else {
8616                         parent->num_ports = niu_pci_vpd_get_nports(np);
8617                         if (!parent->num_ports) {
8618                                 /* Fall back to SPROM as last resort.
8619                                  * This will fail on most cards.
8620                                  */
8621                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8622                                         ESPC_NUM_PORTS_MACS_VAL;
8623
8624                                 /* All of the current probing methods fail on
8625                                  * Maramba on-board parts.
8626                                  */
8627                                 if (!parent->num_ports)
8628                                         parent->num_ports = 4;
8629                         }
8630                 }
8631         }
8632
8633         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
8634                np->port, parent->num_ports);
8635         if (np->port >= parent->num_ports)
8636                 return -ENODEV;
8637
8638         return 0;
8639 }
8640
8641 static int __devinit phy_record(struct niu_parent *parent,
8642                                 struct phy_probe_info *p,
8643                                 int dev_id_1, int dev_id_2, u8 phy_port,
8644                                 int type)
8645 {
8646         u32 id = (dev_id_1 << 16) | dev_id_2;
8647         u8 idx;
8648
8649         if (dev_id_1 < 0 || dev_id_2 < 0)
8650                 return 0;
8651         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8652                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8653                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8654                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8655                         return 0;
8656         } else {
8657                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8658                         return 0;
8659         }
8660
8661         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8662                 parent->index, id,
8663                 (type == PHY_TYPE_PMA_PMD ?
8664                  "PMA/PMD" :
8665                  (type == PHY_TYPE_PCS ?
8666                   "PCS" : "MII")),
8667                 phy_port);
8668
8669         if (p->cur[type] >= NIU_MAX_PORTS) {
8670                 printk(KERN_ERR PFX "Too many PHY ports.\n");
8671                 return -EINVAL;
8672         }
8673         idx = p->cur[type];
8674         p->phy_id[type][idx] = id;
8675         p->phy_port[type][idx] = phy_port;
8676         p->cur[type] = idx + 1;
8677         return 0;
8678 }
8679
8680 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8681 {
8682         int i;
8683
8684         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8685                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8686                         return 1;
8687         }
8688         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8689                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8690                         return 1;
8691         }
8692
8693         return 0;
8694 }
8695
8696 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8697 {
8698         int port, cnt;
8699
8700         cnt = 0;
8701         *lowest = 32;
8702         for (port = 8; port < 32; port++) {
8703                 if (port_has_10g(p, port)) {
8704                         if (!cnt)
8705                                 *lowest = port;
8706                         cnt++;
8707                 }
8708         }
8709
8710         return cnt;
8711 }
8712
8713 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8714 {
8715         *lowest = 32;
8716         if (p->cur[PHY_TYPE_MII])
8717                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8718
8719         return p->cur[PHY_TYPE_MII];
8720 }
8721
8722 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8723 {
8724         int num_ports = parent->num_ports;
8725         int i;
8726
8727         for (i = 0; i < num_ports; i++) {
8728                 parent->rxchan_per_port[i] = (16 / num_ports);
8729                 parent->txchan_per_port[i] = (16 / num_ports);
8730
8731                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8732                         "[%u TX chans]\n",
8733                         parent->index, i,
8734                         parent->rxchan_per_port[i],
8735                         parent->txchan_per_port[i]);
8736         }
8737 }
8738
8739 static void __devinit niu_divide_channels(struct niu_parent *parent,
8740                                           int num_10g, int num_1g)
8741 {
8742         int num_ports = parent->num_ports;
8743         int rx_chans_per_10g, rx_chans_per_1g;
8744         int tx_chans_per_10g, tx_chans_per_1g;
8745         int i, tot_rx, tot_tx;
8746
8747         if (!num_10g || !num_1g) {
8748                 rx_chans_per_10g = rx_chans_per_1g =
8749                         (NIU_NUM_RXCHAN / num_ports);
8750                 tx_chans_per_10g = tx_chans_per_1g =
8751                         (NIU_NUM_TXCHAN / num_ports);
8752         } else {
8753                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8754                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8755                                     (rx_chans_per_1g * num_1g)) /
8756                         num_10g;
8757
8758                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8759                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8760                                     (tx_chans_per_1g * num_1g)) /
8761                         num_10g;
8762         }
8763
8764         tot_rx = tot_tx = 0;
8765         for (i = 0; i < num_ports; i++) {
8766                 int type = phy_decode(parent->port_phy, i);
8767
8768                 if (type == PORT_TYPE_10G) {
8769                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8770                         parent->txchan_per_port[i] = tx_chans_per_10g;
8771                 } else {
8772                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8773                         parent->txchan_per_port[i] = tx_chans_per_1g;
8774                 }
8775                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8776                         "[%u TX chans]\n",
8777                         parent->index, i,
8778                         parent->rxchan_per_port[i],
8779                         parent->txchan_per_port[i]);
8780                 tot_rx += parent->rxchan_per_port[i];
8781                 tot_tx += parent->txchan_per_port[i];
8782         }
8783
8784         if (tot_rx > NIU_NUM_RXCHAN) {
8785                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
8786                        "resetting to one per port.\n",
8787                        parent->index, tot_rx);
8788                 for (i = 0; i < num_ports; i++)
8789                         parent->rxchan_per_port[i] = 1;
8790         }
8791         if (tot_tx > NIU_NUM_TXCHAN) {
8792                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
8793                        "resetting to one per port.\n",
8794                        parent->index, tot_tx);
8795                 for (i = 0; i < num_ports; i++)
8796                         parent->txchan_per_port[i] = 1;
8797         }
8798         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8799                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
8800                        "RX[%d] TX[%d]\n",
8801                        parent->index, tot_rx, tot_tx);
8802         }
8803 }
8804
8805 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8806                                             int num_10g, int num_1g)
8807 {
8808         int i, num_ports = parent->num_ports;
8809         int rdc_group, rdc_groups_per_port;
8810         int rdc_channel_base;
8811
8812         rdc_group = 0;
8813         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8814
8815         rdc_channel_base = 0;
8816
8817         for (i = 0; i < num_ports; i++) {
8818                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8819                 int grp, num_channels = parent->rxchan_per_port[i];
8820                 int this_channel_offset;
8821
8822                 tp->first_table_num = rdc_group;
8823                 tp->num_tables = rdc_groups_per_port;
8824                 this_channel_offset = 0;
8825                 for (grp = 0; grp < tp->num_tables; grp++) {
8826                         struct rdc_table *rt = &tp->tables[grp];
8827                         int slot;
8828
8829                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8830                                 parent->index, i, tp->first_table_num + grp);
8831                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8832                                 rt->rxdma_channel[slot] =
8833                                         rdc_channel_base + this_channel_offset;
8834
8835                                 printk("%d ", rt->rxdma_channel[slot]);
8836
8837                                 if (++this_channel_offset == num_channels)
8838                                         this_channel_offset = 0;
8839                         }
8840                         printk("]\n");
8841                 }
8842
8843                 parent->rdc_default[i] = rdc_channel_base;
8844
8845                 rdc_channel_base += num_channels;
8846                 rdc_group += rdc_groups_per_port;
8847         }
8848 }
8849
8850 static int __devinit fill_phy_probe_info(struct niu *np,
8851                                          struct niu_parent *parent,
8852                                          struct phy_probe_info *info)
8853 {
8854         unsigned long flags;
8855         int port, err;
8856
8857         memset(info, 0, sizeof(*info));
8858
8859         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8860         niu_lock_parent(np, flags);
8861         err = 0;
8862         for (port = 8; port < 32; port++) {
8863                 int dev_id_1, dev_id_2;
8864
8865                 dev_id_1 = mdio_read(np, port,
8866                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8867                 dev_id_2 = mdio_read(np, port,
8868                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8869                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8870                                  PHY_TYPE_PMA_PMD);
8871                 if (err)
8872                         break;
8873                 dev_id_1 = mdio_read(np, port,
8874                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8875                 dev_id_2 = mdio_read(np, port,
8876                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8877                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8878                                  PHY_TYPE_PCS);
8879                 if (err)
8880                         break;
8881                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8882                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8883                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8884                                  PHY_TYPE_MII);
8885                 if (err)
8886                         break;
8887         }
8888         niu_unlock_parent(np, flags);
8889
8890         return err;
8891 }
8892
8893 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8894 {
8895         struct phy_probe_info *info = &parent->phy_probe_info;
8896         int lowest_10g, lowest_1g;
8897         int num_10g, num_1g;
8898         u32 val;
8899         int err;
8900
8901         num_10g = num_1g = 0;
8902
8903         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8904             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8905                 num_10g = 0;
8906                 num_1g = 2;
8907                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8908                 parent->num_ports = 4;
8909                 val = (phy_encode(PORT_TYPE_1G, 0) |
8910                        phy_encode(PORT_TYPE_1G, 1) |
8911                        phy_encode(PORT_TYPE_1G, 2) |
8912                        phy_encode(PORT_TYPE_1G, 3));
8913         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8914                 num_10g = 2;
8915                 num_1g = 0;
8916                 parent->num_ports = 2;
8917                 val = (phy_encode(PORT_TYPE_10G, 0) |
8918                        phy_encode(PORT_TYPE_10G, 1));
8919         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8920                    (parent->plat_type == PLAT_TYPE_NIU)) {
8921                 /* this is the Monza case */
8922                 if (np->flags & NIU_FLAGS_10G) {
8923                         val = (phy_encode(PORT_TYPE_10G, 0) |
8924                                phy_encode(PORT_TYPE_10G, 1));
8925                 } else {
8926                         val = (phy_encode(PORT_TYPE_1G, 0) |
8927                                phy_encode(PORT_TYPE_1G, 1));
8928                 }
8929         } else {
8930                 err = fill_phy_probe_info(np, parent, info);
8931                 if (err)
8932                         return err;
8933
8934                 num_10g = count_10g_ports(info, &lowest_10g);
8935                 num_1g = count_1g_ports(info, &lowest_1g);
8936
8937                 switch ((num_10g << 4) | num_1g) {
8938                 case 0x24:
8939                         if (lowest_1g == 10)
8940                                 parent->plat_type = PLAT_TYPE_VF_P0;
8941                         else if (lowest_1g == 26)
8942                                 parent->plat_type = PLAT_TYPE_VF_P1;
8943                         else
8944                                 goto unknown_vg_1g_port;
8945
8946                         /* fallthru */
8947                 case 0x22:
8948                         val = (phy_encode(PORT_TYPE_10G, 0) |
8949                                phy_encode(PORT_TYPE_10G, 1) |
8950                                phy_encode(PORT_TYPE_1G, 2) |
8951                                phy_encode(PORT_TYPE_1G, 3));
8952                         break;
8953
8954                 case 0x20:
8955                         val = (phy_encode(PORT_TYPE_10G, 0) |
8956                                phy_encode(PORT_TYPE_10G, 1));
8957                         break;
8958
8959                 case 0x10:
8960                         val = phy_encode(PORT_TYPE_10G, np->port);
8961                         break;
8962
8963                 case 0x14:
8964                         if (lowest_1g == 10)
8965                                 parent->plat_type = PLAT_TYPE_VF_P0;
8966                         else if (lowest_1g == 26)
8967                                 parent->plat_type = PLAT_TYPE_VF_P1;
8968                         else
8969                                 goto unknown_vg_1g_port;
8970
8971                         /* fallthru */
8972                 case 0x13:
8973                         if ((lowest_10g & 0x7) == 0)
8974                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8975                                        phy_encode(PORT_TYPE_1G, 1) |
8976                                        phy_encode(PORT_TYPE_1G, 2) |
8977                                        phy_encode(PORT_TYPE_1G, 3));
8978                         else
8979                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8980                                        phy_encode(PORT_TYPE_10G, 1) |
8981                                        phy_encode(PORT_TYPE_1G, 2) |
8982                                        phy_encode(PORT_TYPE_1G, 3));
8983                         break;
8984
8985                 case 0x04:
8986                         if (lowest_1g == 10)
8987                                 parent->plat_type = PLAT_TYPE_VF_P0;
8988                         else if (lowest_1g == 26)
8989                                 parent->plat_type = PLAT_TYPE_VF_P1;
8990                         else
8991                                 goto unknown_vg_1g_port;
8992
8993                         val = (phy_encode(PORT_TYPE_1G, 0) |
8994                                phy_encode(PORT_TYPE_1G, 1) |
8995                                phy_encode(PORT_TYPE_1G, 2) |
8996                                phy_encode(PORT_TYPE_1G, 3));
8997                         break;
8998
8999                 default:
9000                         printk(KERN_ERR PFX "Unsupported port config "
9001                                "10G[%d] 1G[%d]\n",
9002                                num_10g, num_1g);
9003                         return -EINVAL;
9004                 }
9005         }
9006
9007         parent->port_phy = val;
9008
9009         if (parent->plat_type == PLAT_TYPE_NIU)
9010                 niu_n2_divide_channels(parent);
9011         else
9012                 niu_divide_channels(parent, num_10g, num_1g);
9013
9014         niu_divide_rdc_groups(parent, num_10g, num_1g);
9015
9016         return 0;
9017
9018 unknown_vg_1g_port:
9019         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
9020                lowest_1g);
9021         return -EINVAL;
9022 }
9023
9024 static int __devinit niu_probe_ports(struct niu *np)
9025 {
9026         struct niu_parent *parent = np->parent;
9027         int err, i;
9028
9029         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
9030                parent->port_phy);
9031
9032         if (parent->port_phy == PORT_PHY_UNKNOWN) {
9033                 err = walk_phys(np, parent);
9034                 if (err)
9035                         return err;
9036
9037                 niu_set_ldg_timer_res(np, 2);
9038                 for (i = 0; i <= LDN_MAX; i++)
9039                         niu_ldn_irq_enable(np, i, 0);
9040         }
9041
9042         if (parent->port_phy == PORT_PHY_INVALID)
9043                 return -EINVAL;
9044
9045         return 0;
9046 }
9047
9048 static int __devinit niu_classifier_swstate_init(struct niu *np)
9049 {
9050         struct niu_classifier *cp = &np->clas;
9051
9052         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
9053                np->parent->tcam_num_entries);
9054
9055         cp->tcam_top = (u16) np->port;
9056         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
9057         cp->h1_init = 0xffffffff;
9058         cp->h2_init = 0xffff;
9059
9060         return fflp_early_init(np);
9061 }
9062
9063 static void __devinit niu_link_config_init(struct niu *np)
9064 {
9065         struct niu_link_config *lp = &np->link_config;
9066
9067         lp->advertising = (ADVERTISED_10baseT_Half |
9068                            ADVERTISED_10baseT_Full |
9069                            ADVERTISED_100baseT_Half |
9070                            ADVERTISED_100baseT_Full |
9071                            ADVERTISED_1000baseT_Half |
9072                            ADVERTISED_1000baseT_Full |
9073                            ADVERTISED_10000baseT_Full |
9074                            ADVERTISED_Autoneg);
9075         lp->speed = lp->active_speed = SPEED_INVALID;
9076         lp->duplex = DUPLEX_FULL;
9077         lp->active_duplex = DUPLEX_INVALID;
9078         lp->autoneg = 1;
9079 #if 0
9080         lp->loopback_mode = LOOPBACK_MAC;
9081         lp->active_speed = SPEED_10000;
9082         lp->active_duplex = DUPLEX_FULL;
9083 #else
9084         lp->loopback_mode = LOOPBACK_DISABLED;
9085 #endif
9086 }
9087
9088 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9089 {
9090         switch (np->port) {
9091         case 0:
9092                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9093                 np->ipp_off  = 0x00000;
9094                 np->pcs_off  = 0x04000;
9095                 np->xpcs_off = 0x02000;
9096                 break;
9097
9098         case 1:
9099                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9100                 np->ipp_off  = 0x08000;
9101                 np->pcs_off  = 0x0a000;
9102                 np->xpcs_off = 0x08000;
9103                 break;
9104
9105         case 2:
9106                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9107                 np->ipp_off  = 0x04000;
9108                 np->pcs_off  = 0x0e000;
9109                 np->xpcs_off = ~0UL;
9110                 break;
9111
9112         case 3:
9113                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9114                 np->ipp_off  = 0x0c000;
9115                 np->pcs_off  = 0x12000;
9116                 np->xpcs_off = ~0UL;
9117                 break;
9118
9119         default:
9120                 dev_err(np->device, PFX "Port %u is invalid, cannot "
9121                         "compute MAC block offset.\n", np->port);
9122                 return -EINVAL;
9123         }
9124
9125         return 0;
9126 }
9127
9128 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9129 {
9130         struct msix_entry msi_vec[NIU_NUM_LDG];
9131         struct niu_parent *parent = np->parent;
9132         struct pci_dev *pdev = np->pdev;
9133         int i, num_irqs, err;
9134         u8 first_ldg;
9135
9136         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9137         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9138                 ldg_num_map[i] = first_ldg + i;
9139
9140         num_irqs = (parent->rxchan_per_port[np->port] +
9141                     parent->txchan_per_port[np->port] +
9142                     (np->port == 0 ? 3 : 1));
9143         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9144
9145 retry:
9146         for (i = 0; i < num_irqs; i++) {
9147                 msi_vec[i].vector = 0;
9148                 msi_vec[i].entry = i;
9149         }
9150
9151         err = pci_enable_msix(pdev, msi_vec, num_irqs);
9152         if (err < 0) {
9153                 np->flags &= ~NIU_FLAGS_MSIX;
9154                 return;
9155         }
9156         if (err > 0) {
9157                 num_irqs = err;
9158                 goto retry;
9159         }
9160
9161         np->flags |= NIU_FLAGS_MSIX;
9162         for (i = 0; i < num_irqs; i++)
9163                 np->ldg[i].irq = msi_vec[i].vector;
9164         np->num_ldg = num_irqs;
9165 }
9166
9167 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9168 {
9169 #ifdef CONFIG_SPARC64
9170         struct of_device *op = np->op;
9171         const u32 *int_prop;
9172         int i;
9173
9174         int_prop = of_get_property(op->node, "interrupts", NULL);
9175         if (!int_prop)
9176                 return -ENODEV;
9177
9178         for (i = 0; i < op->num_irqs; i++) {
9179                 ldg_num_map[i] = int_prop[i];
9180                 np->ldg[i].irq = op->irqs[i];
9181         }
9182
9183         np->num_ldg = op->num_irqs;
9184
9185         return 0;
9186 #else
9187         return -EINVAL;
9188 #endif
9189 }
9190
9191 static int __devinit niu_ldg_init(struct niu *np)
9192 {
9193         struct niu_parent *parent = np->parent;
9194         u8 ldg_num_map[NIU_NUM_LDG];
9195         int first_chan, num_chan;
9196         int i, err, ldg_rotor;
9197         u8 port;
9198
9199         np->num_ldg = 1;
9200         np->ldg[0].irq = np->dev->irq;
9201         if (parent->plat_type == PLAT_TYPE_NIU) {
9202                 err = niu_n2_irq_init(np, ldg_num_map);
9203                 if (err)
9204                         return err;
9205         } else
9206                 niu_try_msix(np, ldg_num_map);
9207
9208         port = np->port;
9209         for (i = 0; i < np->num_ldg; i++) {
9210                 struct niu_ldg *lp = &np->ldg[i];
9211
9212                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9213
9214                 lp->np = np;
9215                 lp->ldg_num = ldg_num_map[i];
9216                 lp->timer = 2; /* XXX */
9217
9218                 /* On N2 NIU the firmware has setup the SID mappings so they go
9219                  * to the correct values that will route the LDG to the proper
9220                  * interrupt in the NCU interrupt table.
9221                  */
9222                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9223                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9224                         if (err)
9225                                 return err;
9226                 }
9227         }
9228
9229         /* We adopt the LDG assignment ordering used by the N2 NIU
9230          * 'interrupt' properties because that simplifies a lot of
9231          * things.  This ordering is:
9232          *
9233          *      MAC
9234          *      MIF     (if port zero)
9235          *      SYSERR  (if port zero)
9236          *      RX channels
9237          *      TX channels
9238          */
9239
9240         ldg_rotor = 0;
9241
9242         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9243                                   LDN_MAC(port));
9244         if (err)
9245                 return err;
9246
9247         ldg_rotor++;
9248         if (ldg_rotor == np->num_ldg)
9249                 ldg_rotor = 0;
9250
9251         if (port == 0) {
9252                 err = niu_ldg_assign_ldn(np, parent,
9253                                          ldg_num_map[ldg_rotor],
9254                                          LDN_MIF);
9255                 if (err)
9256                         return err;
9257
9258                 ldg_rotor++;
9259                 if (ldg_rotor == np->num_ldg)
9260                         ldg_rotor = 0;
9261
9262                 err = niu_ldg_assign_ldn(np, parent,
9263                                          ldg_num_map[ldg_rotor],
9264                                          LDN_DEVICE_ERROR);
9265                 if (err)
9266                         return err;
9267
9268                 ldg_rotor++;
9269                 if (ldg_rotor == np->num_ldg)
9270                         ldg_rotor = 0;
9271
9272         }
9273
9274         first_chan = 0;
9275         for (i = 0; i < port; i++)
9276                 first_chan += parent->rxchan_per_port[port];
9277         num_chan = parent->rxchan_per_port[port];
9278
9279         for (i = first_chan; i < (first_chan + num_chan); i++) {
9280                 err = niu_ldg_assign_ldn(np, parent,
9281                                          ldg_num_map[ldg_rotor],
9282                                          LDN_RXDMA(i));
9283                 if (err)
9284                         return err;
9285                 ldg_rotor++;
9286                 if (ldg_rotor == np->num_ldg)
9287                         ldg_rotor = 0;
9288         }
9289
9290         first_chan = 0;
9291         for (i = 0; i < port; i++)
9292                 first_chan += parent->txchan_per_port[port];
9293         num_chan = parent->txchan_per_port[port];
9294         for (i = first_chan; i < (first_chan + num_chan); i++) {
9295                 err = niu_ldg_assign_ldn(np, parent,
9296                                          ldg_num_map[ldg_rotor],
9297                                          LDN_TXDMA(i));
9298                 if (err)
9299                         return err;
9300                 ldg_rotor++;
9301                 if (ldg_rotor == np->num_ldg)
9302                         ldg_rotor = 0;
9303         }
9304
9305         return 0;
9306 }
9307
9308 static void __devexit niu_ldg_free(struct niu *np)
9309 {
9310         if (np->flags & NIU_FLAGS_MSIX)
9311                 pci_disable_msix(np->pdev);
9312 }
9313
9314 static int __devinit niu_get_of_props(struct niu *np)
9315 {
9316 #ifdef CONFIG_SPARC64
9317         struct net_device *dev = np->dev;
9318         struct device_node *dp;
9319         const char *phy_type;
9320         const u8 *mac_addr;
9321         const char *model;
9322         int prop_len;
9323
9324         if (np->parent->plat_type == PLAT_TYPE_NIU)
9325                 dp = np->op->node;
9326         else
9327                 dp = pci_device_to_OF_node(np->pdev);
9328
9329         phy_type = of_get_property(dp, "phy-type", &prop_len);
9330         if (!phy_type) {
9331                 dev_err(np->device, PFX "%s: OF node lacks "
9332                         "phy-type property\n",
9333                         dp->full_name);
9334                 return -EINVAL;
9335         }
9336
9337         if (!strcmp(phy_type, "none"))
9338                 return -ENODEV;
9339
9340         strcpy(np->vpd.phy_type, phy_type);
9341
9342         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9343                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
9344                         dp->full_name, np->vpd.phy_type);
9345                 return -EINVAL;
9346         }
9347
9348         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9349         if (!mac_addr) {
9350                 dev_err(np->device, PFX "%s: OF node lacks "
9351                         "local-mac-address property\n",
9352                         dp->full_name);
9353                 return -EINVAL;
9354         }
9355         if (prop_len != dev->addr_len) {
9356                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
9357                         "is wrong.\n",
9358                         dp->full_name, prop_len);
9359         }
9360         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9361         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9362                 int i;
9363
9364                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
9365                         dp->full_name);
9366                 dev_err(np->device, PFX "%s: [ \n",
9367                         dp->full_name);
9368                 for (i = 0; i < 6; i++)
9369                         printk("%02x ", dev->perm_addr[i]);
9370                 printk("]\n");
9371                 return -EINVAL;
9372         }
9373
9374         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9375
9376         model = of_get_property(dp, "model", &prop_len);
9377
9378         if (model)
9379                 strcpy(np->vpd.model, model);
9380
9381         if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9382                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9383                         NIU_FLAGS_HOTPLUG_PHY);
9384         }
9385
9386         return 0;
9387 #else
9388         return -EINVAL;
9389 #endif
9390 }
9391
9392 static int __devinit niu_get_invariants(struct niu *np)
9393 {
9394         int err, have_props;
9395         u32 offset;
9396
9397         err = niu_get_of_props(np);
9398         if (err == -ENODEV)
9399                 return err;
9400
9401         have_props = !err;
9402
9403         err = niu_init_mac_ipp_pcs_base(np);
9404         if (err)
9405                 return err;
9406
9407         if (have_props) {
9408                 err = niu_get_and_validate_port(np);
9409                 if (err)
9410                         return err;
9411
9412         } else  {
9413                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9414                         return -EINVAL;
9415
9416                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9417                 offset = niu_pci_vpd_offset(np);
9418                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
9419                        offset);
9420                 if (offset)
9421                         niu_pci_vpd_fetch(np, offset);
9422                 nw64(ESPC_PIO_EN, 0);
9423
9424                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9425                         niu_pci_vpd_validate(np);
9426                         err = niu_get_and_validate_port(np);
9427                         if (err)
9428                                 return err;
9429                 }
9430
9431                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9432                         err = niu_get_and_validate_port(np);
9433                         if (err)
9434                                 return err;
9435                         err = niu_pci_probe_sprom(np);
9436                         if (err)
9437                                 return err;
9438                 }
9439         }
9440
9441         err = niu_probe_ports(np);
9442         if (err)
9443                 return err;
9444
9445         niu_ldg_init(np);
9446
9447         niu_classifier_swstate_init(np);
9448         niu_link_config_init(np);
9449
9450         err = niu_determine_phy_disposition(np);
9451         if (!err)
9452                 err = niu_init_link(np);
9453
9454         return err;
9455 }
9456
9457 static LIST_HEAD(niu_parent_list);
9458 static DEFINE_MUTEX(niu_parent_lock);
9459 static int niu_parent_index;
9460
9461 static ssize_t show_port_phy(struct device *dev,
9462                              struct device_attribute *attr, char *buf)
9463 {
9464         struct platform_device *plat_dev = to_platform_device(dev);
9465         struct niu_parent *p = plat_dev->dev.platform_data;
9466         u32 port_phy = p->port_phy;
9467         char *orig_buf = buf;
9468         int i;
9469
9470         if (port_phy == PORT_PHY_UNKNOWN ||
9471             port_phy == PORT_PHY_INVALID)
9472                 return 0;
9473
9474         for (i = 0; i < p->num_ports; i++) {
9475                 const char *type_str;
9476                 int type;
9477
9478                 type = phy_decode(port_phy, i);
9479                 if (type == PORT_TYPE_10G)
9480                         type_str = "10G";
9481                 else
9482                         type_str = "1G";
9483                 buf += sprintf(buf,
9484                                (i == 0) ? "%s" : " %s",
9485                                type_str);
9486         }
9487         buf += sprintf(buf, "\n");
9488         return buf - orig_buf;
9489 }
9490
9491 static ssize_t show_plat_type(struct device *dev,
9492                               struct device_attribute *attr, char *buf)
9493 {
9494         struct platform_device *plat_dev = to_platform_device(dev);
9495         struct niu_parent *p = plat_dev->dev.platform_data;
9496         const char *type_str;
9497
9498         switch (p->plat_type) {
9499         case PLAT_TYPE_ATLAS:
9500                 type_str = "atlas";
9501                 break;
9502         case PLAT_TYPE_NIU:
9503                 type_str = "niu";
9504                 break;
9505         case PLAT_TYPE_VF_P0:
9506                 type_str = "vf_p0";
9507                 break;
9508         case PLAT_TYPE_VF_P1:
9509                 type_str = "vf_p1";
9510                 break;
9511         default:
9512                 type_str = "unknown";
9513                 break;
9514         }
9515
9516         return sprintf(buf, "%s\n", type_str);
9517 }
9518
9519 static ssize_t __show_chan_per_port(struct device *dev,
9520                                     struct device_attribute *attr, char *buf,
9521                                     int rx)
9522 {
9523         struct platform_device *plat_dev = to_platform_device(dev);
9524         struct niu_parent *p = plat_dev->dev.platform_data;
9525         char *orig_buf = buf;
9526         u8 *arr;
9527         int i;
9528
9529         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9530
9531         for (i = 0; i < p->num_ports; i++) {
9532                 buf += sprintf(buf,
9533                                (i == 0) ? "%d" : " %d",
9534                                arr[i]);
9535         }
9536         buf += sprintf(buf, "\n");
9537
9538         return buf - orig_buf;
9539 }
9540
9541 static ssize_t show_rxchan_per_port(struct device *dev,
9542                                     struct device_attribute *attr, char *buf)
9543 {
9544         return __show_chan_per_port(dev, attr, buf, 1);
9545 }
9546
9547 static ssize_t show_txchan_per_port(struct device *dev,
9548                                     struct device_attribute *attr, char *buf)
9549 {
9550         return __show_chan_per_port(dev, attr, buf, 1);
9551 }
9552
9553 static ssize_t show_num_ports(struct device *dev,
9554                               struct device_attribute *attr, char *buf)
9555 {
9556         struct platform_device *plat_dev = to_platform_device(dev);
9557         struct niu_parent *p = plat_dev->dev.platform_data;
9558
9559         return sprintf(buf, "%d\n", p->num_ports);
9560 }
9561
9562 static struct device_attribute niu_parent_attributes[] = {
9563         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9564         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9565         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9566         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9567         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9568         {}
9569 };
9570
9571 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9572                                                     union niu_parent_id *id,
9573                                                     u8 ptype)
9574 {
9575         struct platform_device *plat_dev;
9576         struct niu_parent *p;
9577         int i;
9578
9579         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
9580
9581         plat_dev = platform_device_register_simple("niu", niu_parent_index,
9582                                                    NULL, 0);
9583         if (IS_ERR(plat_dev))
9584                 return NULL;
9585
9586         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9587                 int err = device_create_file(&plat_dev->dev,
9588                                              &niu_parent_attributes[i]);
9589                 if (err)
9590                         goto fail_unregister;
9591         }
9592
9593         p = kzalloc(sizeof(*p), GFP_KERNEL);
9594         if (!p)
9595                 goto fail_unregister;
9596
9597         p->index = niu_parent_index++;
9598
9599         plat_dev->dev.platform_data = p;
9600         p->plat_dev = plat_dev;
9601
9602         memcpy(&p->id, id, sizeof(*id));
9603         p->plat_type = ptype;
9604         INIT_LIST_HEAD(&p->list);
9605         atomic_set(&p->refcnt, 0);
9606         list_add(&p->list, &niu_parent_list);
9607         spin_lock_init(&p->lock);
9608
9609         p->rxdma_clock_divider = 7500;
9610
9611         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9612         if (p->plat_type == PLAT_TYPE_NIU)
9613                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9614
9615         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9616                 int index = i - CLASS_CODE_USER_PROG1;
9617
9618                 p->tcam_key[index] = TCAM_KEY_TSEL;
9619                 p->flow_key[index] = (FLOW_KEY_IPSA |
9620                                       FLOW_KEY_IPDA |
9621                                       FLOW_KEY_PROTO |
9622                                       (FLOW_KEY_L4_BYTE12 <<
9623                                        FLOW_KEY_L4_0_SHIFT) |
9624                                       (FLOW_KEY_L4_BYTE12 <<
9625                                        FLOW_KEY_L4_1_SHIFT));
9626         }
9627
9628         for (i = 0; i < LDN_MAX + 1; i++)
9629                 p->ldg_map[i] = LDG_INVALID;
9630
9631         return p;
9632
9633 fail_unregister:
9634         platform_device_unregister(plat_dev);
9635         return NULL;
9636 }
9637
9638 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9639                                                     union niu_parent_id *id,
9640                                                     u8 ptype)
9641 {
9642         struct niu_parent *p, *tmp;
9643         int port = np->port;
9644
9645         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
9646                ptype, port);
9647
9648         mutex_lock(&niu_parent_lock);
9649         p = NULL;
9650         list_for_each_entry(tmp, &niu_parent_list, list) {
9651                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9652                         p = tmp;
9653                         break;
9654                 }
9655         }
9656         if (!p)
9657                 p = niu_new_parent(np, id, ptype);
9658
9659         if (p) {
9660                 char port_name[6];
9661                 int err;
9662
9663                 sprintf(port_name, "port%d", port);
9664                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9665                                         &np->device->kobj,
9666                                         port_name);
9667                 if (!err) {
9668                         p->ports[port] = np;
9669                         atomic_inc(&p->refcnt);
9670                 }
9671         }
9672         mutex_unlock(&niu_parent_lock);
9673
9674         return p;
9675 }
9676
9677 static void niu_put_parent(struct niu *np)
9678 {
9679         struct niu_parent *p = np->parent;
9680         u8 port = np->port;
9681         char port_name[6];
9682
9683         BUG_ON(!p || p->ports[port] != np);
9684
9685         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
9686
9687         sprintf(port_name, "port%d", port);
9688
9689         mutex_lock(&niu_parent_lock);
9690
9691         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9692
9693         p->ports[port] = NULL;
9694         np->parent = NULL;
9695
9696         if (atomic_dec_and_test(&p->refcnt)) {
9697                 list_del(&p->list);
9698                 platform_device_unregister(p->plat_dev);
9699         }
9700
9701         mutex_unlock(&niu_parent_lock);
9702 }
9703
9704 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9705                                     u64 *handle, gfp_t flag)
9706 {
9707         dma_addr_t dh;
9708         void *ret;
9709
9710         ret = dma_alloc_coherent(dev, size, &dh, flag);
9711         if (ret)
9712                 *handle = dh;
9713         return ret;
9714 }
9715
9716 static void niu_pci_free_coherent(struct device *dev, size_t size,
9717                                   void *cpu_addr, u64 handle)
9718 {
9719         dma_free_coherent(dev, size, cpu_addr, handle);
9720 }
9721
9722 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9723                             unsigned long offset, size_t size,
9724                             enum dma_data_direction direction)
9725 {
9726         return dma_map_page(dev, page, offset, size, direction);
9727 }
9728
9729 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9730                                size_t size, enum dma_data_direction direction)
9731 {
9732         dma_unmap_page(dev, dma_address, size, direction);
9733 }
9734
9735 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9736                               size_t size,
9737                               enum dma_data_direction direction)
9738 {
9739         return dma_map_single(dev, cpu_addr, size, direction);
9740 }
9741
9742 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9743                                  size_t size,
9744                                  enum dma_data_direction direction)
9745 {
9746         dma_unmap_single(dev, dma_address, size, direction);
9747 }
9748
9749 static const struct niu_ops niu_pci_ops = {
9750         .alloc_coherent = niu_pci_alloc_coherent,
9751         .free_coherent  = niu_pci_free_coherent,
9752         .map_page       = niu_pci_map_page,
9753         .unmap_page     = niu_pci_unmap_page,
9754         .map_single     = niu_pci_map_single,
9755         .unmap_single   = niu_pci_unmap_single,
9756 };
9757
9758 static void __devinit niu_driver_version(void)
9759 {
9760         static int niu_version_printed;
9761
9762         if (niu_version_printed++ == 0)
9763                 pr_info("%s", version);
9764 }
9765
9766 static struct net_device * __devinit niu_alloc_and_init(
9767         struct device *gen_dev, struct pci_dev *pdev,
9768         struct of_device *op, const struct niu_ops *ops,
9769         u8 port)
9770 {
9771         struct net_device *dev;
9772         struct niu *np;
9773
9774         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9775         if (!dev) {
9776                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
9777                 return NULL;
9778         }
9779
9780         SET_NETDEV_DEV(dev, gen_dev);
9781
9782         np = netdev_priv(dev);
9783         np->dev = dev;
9784         np->pdev = pdev;
9785         np->op = op;
9786         np->device = gen_dev;
9787         np->ops = ops;
9788
9789         np->msg_enable = niu_debug;
9790
9791         spin_lock_init(&np->lock);
9792         INIT_WORK(&np->reset_task, niu_reset_task);
9793
9794         np->port = port;
9795
9796         return dev;
9797 }
9798
9799 static const struct net_device_ops niu_netdev_ops = {
9800         .ndo_open               = niu_open,
9801         .ndo_stop               = niu_close,
9802         .ndo_start_xmit         = niu_start_xmit,
9803         .ndo_get_stats          = niu_get_stats,
9804         .ndo_set_multicast_list = niu_set_rx_mode,
9805         .ndo_validate_addr      = eth_validate_addr,
9806         .ndo_set_mac_address    = niu_set_mac_addr,
9807         .ndo_do_ioctl           = niu_ioctl,
9808         .ndo_tx_timeout         = niu_tx_timeout,
9809         .ndo_change_mtu         = niu_change_mtu,
9810 };
9811
9812 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9813 {
9814         dev->netdev_ops = &niu_netdev_ops;
9815         dev->ethtool_ops = &niu_ethtool_ops;
9816         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9817 }
9818
9819 static void __devinit niu_device_announce(struct niu *np)
9820 {
9821         struct net_device *dev = np->dev;
9822
9823         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9824
9825         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9826                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9827                                 dev->name,
9828                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9829                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9830                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9831                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9832                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9833                                 np->vpd.phy_type);
9834         } else {
9835                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9836                                 dev->name,
9837                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9838                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9839                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9840                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9841                                   "COPPER")),
9842                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9843                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9844                                 np->vpd.phy_type);
9845         }
9846 }
9847
9848 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9849                                       const struct pci_device_id *ent)
9850 {
9851         union niu_parent_id parent_id;
9852         struct net_device *dev;
9853         struct niu *np;
9854         int err, pos;
9855         u64 dma_mask;
9856         u16 val16;
9857
9858         niu_driver_version();
9859
9860         err = pci_enable_device(pdev);
9861         if (err) {
9862                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9863                         "aborting.\n");
9864                 return err;
9865         }
9866
9867         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9868             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9869                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9870                         "base addresses, aborting.\n");
9871                 err = -ENODEV;
9872                 goto err_out_disable_pdev;
9873         }
9874
9875         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9876         if (err) {
9877                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9878                         "aborting.\n");
9879                 goto err_out_disable_pdev;
9880         }
9881
9882         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9883         if (pos <= 0) {
9884                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9885                         "aborting.\n");
9886                 goto err_out_free_res;
9887         }
9888
9889         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9890                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9891         if (!dev) {
9892                 err = -ENOMEM;
9893                 goto err_out_free_res;
9894         }
9895         np = netdev_priv(dev);
9896
9897         memset(&parent_id, 0, sizeof(parent_id));
9898         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9899         parent_id.pci.bus = pdev->bus->number;
9900         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9901
9902         np->parent = niu_get_parent(np, &parent_id,
9903                                     PLAT_TYPE_ATLAS);
9904         if (!np->parent) {
9905                 err = -ENOMEM;
9906                 goto err_out_free_dev;
9907         }
9908
9909         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9910         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9911         val16 |= (PCI_EXP_DEVCTL_CERE |
9912                   PCI_EXP_DEVCTL_NFERE |
9913                   PCI_EXP_DEVCTL_FERE |
9914                   PCI_EXP_DEVCTL_URRE |
9915                   PCI_EXP_DEVCTL_RELAX_EN);
9916         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9917
9918         dma_mask = DMA_44BIT_MASK;
9919         err = pci_set_dma_mask(pdev, dma_mask);
9920         if (!err) {
9921                 dev->features |= NETIF_F_HIGHDMA;
9922                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9923                 if (err) {
9924                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9925                                 "DMA for consistent allocations, "
9926                                 "aborting.\n");
9927                         goto err_out_release_parent;
9928                 }
9929         }
9930         if (err || dma_mask == DMA_BIT_MASK(32)) {
9931                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9932                 if (err) {
9933                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9934                                 "aborting.\n");
9935                         goto err_out_release_parent;
9936                 }
9937         }
9938
9939         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9940
9941         np->regs = pci_ioremap_bar(pdev, 0);
9942         if (!np->regs) {
9943                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9944                         "aborting.\n");
9945                 err = -ENOMEM;
9946                 goto err_out_release_parent;
9947         }
9948
9949         pci_set_master(pdev);
9950         pci_save_state(pdev);
9951
9952         dev->irq = pdev->irq;
9953
9954         niu_assign_netdev_ops(dev);
9955
9956         err = niu_get_invariants(np);
9957         if (err) {
9958                 if (err != -ENODEV)
9959                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
9960                                 "of chip, aborting.\n");
9961                 goto err_out_iounmap;
9962         }
9963
9964         err = register_netdev(dev);
9965         if (err) {
9966                 dev_err(&pdev->dev, PFX "Cannot register net device, "
9967                         "aborting.\n");
9968                 goto err_out_iounmap;
9969         }
9970
9971         pci_set_drvdata(pdev, dev);
9972
9973         niu_device_announce(np);
9974
9975         return 0;
9976
9977 err_out_iounmap:
9978         if (np->regs) {
9979                 iounmap(np->regs);
9980                 np->regs = NULL;
9981         }
9982
9983 err_out_release_parent:
9984         niu_put_parent(np);
9985
9986 err_out_free_dev:
9987         free_netdev(dev);
9988
9989 err_out_free_res:
9990         pci_release_regions(pdev);
9991
9992 err_out_disable_pdev:
9993         pci_disable_device(pdev);
9994         pci_set_drvdata(pdev, NULL);
9995
9996         return err;
9997 }
9998
9999 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
10000 {
10001         struct net_device *dev = pci_get_drvdata(pdev);
10002
10003         if (dev) {
10004                 struct niu *np = netdev_priv(dev);
10005
10006                 unregister_netdev(dev);
10007                 if (np->regs) {
10008                         iounmap(np->regs);
10009                         np->regs = NULL;
10010                 }
10011
10012                 niu_ldg_free(np);
10013
10014                 niu_put_parent(np);
10015
10016                 free_netdev(dev);
10017                 pci_release_regions(pdev);
10018                 pci_disable_device(pdev);
10019                 pci_set_drvdata(pdev, NULL);
10020         }
10021 }
10022
10023 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
10024 {
10025         struct net_device *dev = pci_get_drvdata(pdev);
10026         struct niu *np = netdev_priv(dev);
10027         unsigned long flags;
10028
10029         if (!netif_running(dev))
10030                 return 0;
10031
10032         flush_scheduled_work();
10033         niu_netif_stop(np);
10034
10035         del_timer_sync(&np->timer);
10036
10037         spin_lock_irqsave(&np->lock, flags);
10038         niu_enable_interrupts(np, 0);
10039         spin_unlock_irqrestore(&np->lock, flags);
10040
10041         netif_device_detach(dev);
10042
10043         spin_lock_irqsave(&np->lock, flags);
10044         niu_stop_hw(np);
10045         spin_unlock_irqrestore(&np->lock, flags);
10046
10047         pci_save_state(pdev);
10048
10049         return 0;
10050 }
10051
10052 static int niu_resume(struct pci_dev *pdev)
10053 {
10054         struct net_device *dev = pci_get_drvdata(pdev);
10055         struct niu *np = netdev_priv(dev);
10056         unsigned long flags;
10057         int err;
10058
10059         if (!netif_running(dev))
10060                 return 0;
10061
10062         pci_restore_state(pdev);
10063
10064         netif_device_attach(dev);
10065
10066         spin_lock_irqsave(&np->lock, flags);
10067
10068         err = niu_init_hw(np);
10069         if (!err) {
10070                 np->timer.expires = jiffies + HZ;
10071                 add_timer(&np->timer);
10072                 niu_netif_start(np);
10073         }
10074
10075         spin_unlock_irqrestore(&np->lock, flags);
10076
10077         return err;
10078 }
10079
10080 static struct pci_driver niu_pci_driver = {
10081         .name           = DRV_MODULE_NAME,
10082         .id_table       = niu_pci_tbl,
10083         .probe          = niu_pci_init_one,
10084         .remove         = __devexit_p(niu_pci_remove_one),
10085         .suspend        = niu_suspend,
10086         .resume         = niu_resume,
10087 };
10088
10089 #ifdef CONFIG_SPARC64
10090 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10091                                      u64 *dma_addr, gfp_t flag)
10092 {
10093         unsigned long order = get_order(size);
10094         unsigned long page = __get_free_pages(flag, order);
10095
10096         if (page == 0UL)
10097                 return NULL;
10098         memset((char *)page, 0, PAGE_SIZE << order);
10099         *dma_addr = __pa(page);
10100
10101         return (void *) page;
10102 }
10103
10104 static void niu_phys_free_coherent(struct device *dev, size_t size,
10105                                    void *cpu_addr, u64 handle)
10106 {
10107         unsigned long order = get_order(size);
10108
10109         free_pages((unsigned long) cpu_addr, order);
10110 }
10111
10112 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10113                              unsigned long offset, size_t size,
10114                              enum dma_data_direction direction)
10115 {
10116         return page_to_phys(page) + offset;
10117 }
10118
10119 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10120                                 size_t size, enum dma_data_direction direction)
10121 {
10122         /* Nothing to do.  */
10123 }
10124
10125 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10126                                size_t size,
10127                                enum dma_data_direction direction)
10128 {
10129         return __pa(cpu_addr);
10130 }
10131
10132 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10133                                   size_t size,
10134                                   enum dma_data_direction direction)
10135 {
10136         /* Nothing to do.  */
10137 }
10138
10139 static const struct niu_ops niu_phys_ops = {
10140         .alloc_coherent = niu_phys_alloc_coherent,
10141         .free_coherent  = niu_phys_free_coherent,
10142         .map_page       = niu_phys_map_page,
10143         .unmap_page     = niu_phys_unmap_page,
10144         .map_single     = niu_phys_map_single,
10145         .unmap_single   = niu_phys_unmap_single,
10146 };
10147
10148 static unsigned long res_size(struct resource *r)
10149 {
10150         return r->end - r->start + 1UL;
10151 }
10152
10153 static int __devinit niu_of_probe(struct of_device *op,
10154                                   const struct of_device_id *match)
10155 {
10156         union niu_parent_id parent_id;
10157         struct net_device *dev;
10158         struct niu *np;
10159         const u32 *reg;
10160         int err;
10161
10162         niu_driver_version();
10163
10164         reg = of_get_property(op->node, "reg", NULL);
10165         if (!reg) {
10166                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
10167                         op->node->full_name);
10168                 return -ENODEV;
10169         }
10170
10171         dev = niu_alloc_and_init(&op->dev, NULL, op,
10172                                  &niu_phys_ops, reg[0] & 0x1);
10173         if (!dev) {
10174                 err = -ENOMEM;
10175                 goto err_out;
10176         }
10177         np = netdev_priv(dev);
10178
10179         memset(&parent_id, 0, sizeof(parent_id));
10180         parent_id.of = of_get_parent(op->node);
10181
10182         np->parent = niu_get_parent(np, &parent_id,
10183                                     PLAT_TYPE_NIU);
10184         if (!np->parent) {
10185                 err = -ENOMEM;
10186                 goto err_out_free_dev;
10187         }
10188
10189         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10190
10191         np->regs = of_ioremap(&op->resource[1], 0,
10192                               res_size(&op->resource[1]),
10193                               "niu regs");
10194         if (!np->regs) {
10195                 dev_err(&op->dev, PFX "Cannot map device registers, "
10196                         "aborting.\n");
10197                 err = -ENOMEM;
10198                 goto err_out_release_parent;
10199         }
10200
10201         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10202                                     res_size(&op->resource[2]),
10203                                     "niu vregs-1");
10204         if (!np->vir_regs_1) {
10205                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
10206                         "aborting.\n");
10207                 err = -ENOMEM;
10208                 goto err_out_iounmap;
10209         }
10210
10211         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10212                                     res_size(&op->resource[3]),
10213                                     "niu vregs-2");
10214         if (!np->vir_regs_2) {
10215                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
10216                         "aborting.\n");
10217                 err = -ENOMEM;
10218                 goto err_out_iounmap;
10219         }
10220
10221         niu_assign_netdev_ops(dev);
10222
10223         err = niu_get_invariants(np);
10224         if (err) {
10225                 if (err != -ENODEV)
10226                         dev_err(&op->dev, PFX "Problem fetching invariants "
10227                                 "of chip, aborting.\n");
10228                 goto err_out_iounmap;
10229         }
10230
10231         err = register_netdev(dev);
10232         if (err) {
10233                 dev_err(&op->dev, PFX "Cannot register net device, "
10234                         "aborting.\n");
10235                 goto err_out_iounmap;
10236         }
10237
10238         dev_set_drvdata(&op->dev, dev);
10239
10240         niu_device_announce(np);
10241
10242         return 0;
10243
10244 err_out_iounmap:
10245         if (np->vir_regs_1) {
10246                 of_iounmap(&op->resource[2], np->vir_regs_1,
10247                            res_size(&op->resource[2]));
10248                 np->vir_regs_1 = NULL;
10249         }
10250
10251         if (np->vir_regs_2) {
10252                 of_iounmap(&op->resource[3], np->vir_regs_2,
10253                            res_size(&op->resource[3]));
10254                 np->vir_regs_2 = NULL;
10255         }
10256
10257         if (np->regs) {
10258                 of_iounmap(&op->resource[1], np->regs,
10259                            res_size(&op->resource[1]));
10260                 np->regs = NULL;
10261         }
10262
10263 err_out_release_parent:
10264         niu_put_parent(np);
10265
10266 err_out_free_dev:
10267         free_netdev(dev);
10268
10269 err_out:
10270         return err;
10271 }
10272
10273 static int __devexit niu_of_remove(struct of_device *op)
10274 {
10275         struct net_device *dev = dev_get_drvdata(&op->dev);
10276
10277         if (dev) {
10278                 struct niu *np = netdev_priv(dev);
10279
10280                 unregister_netdev(dev);
10281
10282                 if (np->vir_regs_1) {
10283                         of_iounmap(&op->resource[2], np->vir_regs_1,
10284                                    res_size(&op->resource[2]));
10285                         np->vir_regs_1 = NULL;
10286                 }
10287
10288                 if (np->vir_regs_2) {
10289                         of_iounmap(&op->resource[3], np->vir_regs_2,
10290                                    res_size(&op->resource[3]));
10291                         np->vir_regs_2 = NULL;
10292                 }
10293
10294                 if (np->regs) {
10295                         of_iounmap(&op->resource[1], np->regs,
10296                                    res_size(&op->resource[1]));
10297                         np->regs = NULL;
10298                 }
10299
10300                 niu_ldg_free(np);
10301
10302                 niu_put_parent(np);
10303
10304                 free_netdev(dev);
10305                 dev_set_drvdata(&op->dev, NULL);
10306         }
10307         return 0;
10308 }
10309
10310 static const struct of_device_id niu_match[] = {
10311         {
10312                 .name = "network",
10313                 .compatible = "SUNW,niusl",
10314         },
10315         {},
10316 };
10317 MODULE_DEVICE_TABLE(of, niu_match);
10318
10319 static struct of_platform_driver niu_of_driver = {
10320         .name           = "niu",
10321         .match_table    = niu_match,
10322         .probe          = niu_of_probe,
10323         .remove         = __devexit_p(niu_of_remove),
10324 };
10325
10326 #endif /* CONFIG_SPARC64 */
10327
10328 static int __init niu_init(void)
10329 {
10330         int err = 0;
10331
10332         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10333
10334         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10335
10336 #ifdef CONFIG_SPARC64
10337         err = of_register_driver(&niu_of_driver, &of_bus_type);
10338 #endif
10339
10340         if (!err) {
10341                 err = pci_register_driver(&niu_pci_driver);
10342 #ifdef CONFIG_SPARC64
10343                 if (err)
10344                         of_unregister_driver(&niu_of_driver);
10345 #endif
10346         }
10347
10348         return err;
10349 }
10350
10351 static void __exit niu_exit(void)
10352 {
10353         pci_unregister_driver(&niu_pci_driver);
10354 #ifdef CONFIG_SPARC64
10355         of_unregister_driver(&niu_of_driver);
10356 #endif
10357 }
10358
10359 module_init(niu_init);
10360 module_exit(niu_exit);