2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33 #include "netxen_nic_phan_reg.h"
35 #include <linux/firmware.h>
38 #define MASK(n) ((1ULL<<(n))-1)
39 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
40 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
41 #define MS_WIN(addr) (addr & 0x0ffc0000)
43 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
45 #define CRB_BLK(off) ((off >> 20) & 0x3f)
46 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
47 #define CRB_WINDOW_2M (0x130060)
48 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
49 #define CRB_INDIRECT_2M (0x1e0000UL)
51 #define CRB_WIN_LOCK_TIMEOUT 100000000
52 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210 * top 12 bits of crb internal address (hub, agent)
212 static unsigned crb_hub_agt[64] =
215 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
216 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
217 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
220 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
221 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
223 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
224 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
226 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
227 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
228 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
229 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
230 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
231 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
233 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
243 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
245 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
247 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
248 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
254 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
256 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
267 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
268 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
269 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
270 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
272 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
273 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 /* PCI Windowing for DDR regions. */
282 #define ADDR_IN_RANGE(addr, low, high) \
283 (((addr) <= (high)) && ((addr) >= (low)))
285 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
287 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
288 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
289 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
290 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
292 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
294 int netxen_nic_set_mac(struct net_device *netdev, void *p)
296 struct netxen_adapter *adapter = netdev_priv(netdev);
297 struct sockaddr *addr = p;
299 if (netif_running(netdev))
302 if (!is_valid_ether_addr(addr->sa_data))
303 return -EADDRNOTAVAIL;
305 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
307 /* For P3, MAC addr is not set in NIU */
308 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
309 if (adapter->macaddr_set)
310 adapter->macaddr_set(adapter, addr->sa_data);
315 #define NETXEN_UNICAST_ADDR(port, index) \
316 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
317 #define NETXEN_MCAST_ADDR(port, index) \
318 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
319 #define MAC_HI(addr) \
320 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
321 #define MAC_LO(addr) \
322 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
325 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
328 u16 port = adapter->physical_port;
329 u8 *addr = adapter->netdev->dev_addr;
331 if (adapter->mc_enabled)
334 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
335 val |= (1UL << (28+port));
336 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
338 /* add broadcast addr to filter */
340 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
341 netxen_crb_writelit_adapter(adapter,
342 NETXEN_UNICAST_ADDR(port, 0)+4, val);
344 /* add station addr to filter */
346 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
348 netxen_crb_writelit_adapter(adapter,
349 NETXEN_UNICAST_ADDR(port, 1)+4, val);
351 adapter->mc_enabled = 1;
356 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
359 u16 port = adapter->physical_port;
360 u8 *addr = adapter->netdev->dev_addr;
362 if (!adapter->mc_enabled)
365 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
366 val &= ~(1UL << (28+port));
367 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
370 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
372 netxen_crb_writelit_adapter(adapter,
373 NETXEN_UNICAST_ADDR(port, 0)+4, val);
375 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
376 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
378 adapter->mc_enabled = 0;
383 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
387 u16 port = adapter->physical_port;
392 netxen_crb_writelit_adapter(adapter,
393 NETXEN_MCAST_ADDR(port, index), hi);
394 netxen_crb_writelit_adapter(adapter,
395 NETXEN_MCAST_ADDR(port, index)+4, lo);
400 void netxen_p2_nic_set_multi(struct net_device *netdev)
402 struct netxen_adapter *adapter = netdev_priv(netdev);
403 struct dev_mc_list *mc_ptr;
407 memset(null_addr, 0, 6);
409 if (netdev->flags & IFF_PROMISC) {
411 adapter->set_promisc(adapter,
412 NETXEN_NIU_PROMISC_MODE);
414 /* Full promiscuous mode */
415 netxen_nic_disable_mcast_filter(adapter);
420 if (netdev->mc_count == 0) {
421 adapter->set_promisc(adapter,
422 NETXEN_NIU_NON_PROMISC_MODE);
423 netxen_nic_disable_mcast_filter(adapter);
427 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
428 if (netdev->flags & IFF_ALLMULTI ||
429 netdev->mc_count > adapter->max_mc_count) {
430 netxen_nic_disable_mcast_filter(adapter);
434 netxen_nic_enable_mcast_filter(adapter);
436 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
437 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
439 if (index != netdev->mc_count)
440 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
441 netxen_nic_driver_name, netdev->name);
443 /* Clear out remaining addresses */
444 for (; index < adapter->max_mc_count; index++)
445 netxen_nic_set_mcast_addr(adapter, index, null_addr);
448 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
449 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
451 nx_mac_list_t *cur, *prev;
453 /* if in del_list, move it to adapter->mac_list */
454 for (cur = *del_list, prev = NULL; cur;) {
455 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
457 *del_list = cur->next;
459 prev->next = cur->next;
460 cur->next = adapter->mac_list;
461 adapter->mac_list = cur;
468 /* make sure to add each mac address only once */
469 for (cur = adapter->mac_list; cur; cur = cur->next) {
470 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
473 /* not in del_list, create new entry and add to add_list */
474 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
476 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
477 "not work properly from now.\n", __func__);
481 memcpy(cur->mac_addr, addr, ETH_ALEN);
482 cur->next = *add_list;
488 netxen_send_cmd_descs(struct netxen_adapter *adapter,
489 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
491 uint32_t i, producer;
492 struct netxen_cmd_buffer *pbuf;
493 struct cmd_desc_type0 *cmd_desc;
495 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
496 printk(KERN_WARNING "%s: Too many command descriptors in a "
497 "request\n", __func__);
503 netif_tx_lock_bh(adapter->netdev);
505 producer = adapter->cmd_producer;
507 cmd_desc = &cmd_desc_arr[i];
509 pbuf = &adapter->cmd_buf_arr[producer];
511 pbuf->frag_count = 0;
513 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
514 memcpy(&adapter->ahw.cmd_desc_head[producer],
515 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
517 producer = get_next_index(producer,
518 adapter->max_tx_desc_count);
521 } while (i != nr_elements);
523 adapter->cmd_producer = producer;
525 /* write producer index to start the xmit */
527 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
529 netif_tx_unlock_bh(adapter->netdev);
534 static int nx_p3_sre_macaddr_change(struct net_device *dev,
535 u8 *addr, unsigned op)
537 struct netxen_adapter *adapter = netdev_priv(dev);
539 nx_mac_req_t *mac_req;
543 memset(&req, 0, sizeof(nx_nic_req_t));
544 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
546 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
547 req.req_hdr = cpu_to_le64(word);
549 mac_req = (nx_mac_req_t *)&req.words[0];
551 memcpy(mac_req->mac_addr, addr, 6);
553 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
555 printk(KERN_ERR "ERROR. Could not send mac update\n");
562 void netxen_p3_nic_set_multi(struct net_device *netdev)
564 struct netxen_adapter *adapter = netdev_priv(netdev);
565 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
566 struct dev_mc_list *mc_ptr;
567 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
568 u32 mode = VPORT_MISS_MODE_DROP;
570 del_list = adapter->mac_list;
571 adapter->mac_list = NULL;
573 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
574 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
576 if (netdev->flags & IFF_PROMISC) {
577 mode = VPORT_MISS_MODE_ACCEPT_ALL;
581 if ((netdev->flags & IFF_ALLMULTI) ||
582 (netdev->mc_count > adapter->max_mc_count)) {
583 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
587 if (netdev->mc_count > 0) {
588 for (mc_ptr = netdev->mc_list; mc_ptr;
589 mc_ptr = mc_ptr->next) {
590 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
591 &add_list, &del_list);
596 adapter->set_promisc(adapter, mode);
597 for (cur = del_list; cur;) {
598 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
603 for (cur = add_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
606 cur->next = adapter->mac_list;
607 adapter->mac_list = cur;
612 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
617 memset(&req, 0, sizeof(nx_nic_req_t));
619 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
621 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
622 ((u64)adapter->portnum << 16);
623 req.req_hdr = cpu_to_le64(word);
625 req.words[0] = cpu_to_le64(mode);
627 return netxen_send_cmd_descs(adapter,
628 (struct cmd_desc_type0 *)&req, 1);
631 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
633 nx_mac_list_t *cur, *next;
635 cur = adapter->mac_list;
644 #define NETXEN_CONFIG_INTR_COALESCE 3
647 * Send the interrupt coalescing parameter set by ethtool to the card.
649 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
655 memset(&req, 0, sizeof(nx_nic_req_t));
657 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
659 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
660 req.req_hdr = cpu_to_le64(word);
662 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
664 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
666 printk(KERN_ERR "ERROR. Could not send "
667 "interrupt coalescing parameters\n");
674 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
675 * @returns 0 on success, negative on failure
678 #define MTU_FUDGE_FACTOR 100
680 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
682 struct netxen_adapter *adapter = netdev_priv(netdev);
686 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
687 max_mtu = P3_MAX_MTU;
689 max_mtu = P2_MAX_MTU;
692 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
693 netdev->name, max_mtu);
697 if (adapter->set_mtu)
698 rc = adapter->set_mtu(adapter, mtu);
706 int netxen_is_flash_supported(struct netxen_adapter *adapter)
708 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
709 int addr, val01, val02, i, j;
711 /* if the flash size less than 4Mb, make huge war cry and die */
712 for (j = 1; j < 4; j++) {
713 addr = j * NETXEN_NIC_WINDOW_MARGIN;
714 for (i = 0; i < ARRAY_SIZE(locs); i++) {
715 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
716 && netxen_rom_fast_read(adapter, (addr + locs[i]),
728 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
729 int size, __le32 * buf)
736 for (i = 0; i < size / sizeof(u32); i++) {
737 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
739 *ptr32 = cpu_to_le32(v);
743 if ((char *)buf + size > (char *)ptr32) {
745 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
747 local = cpu_to_le32(v);
748 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
754 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
756 __le32 *pmac = (__le32 *) mac;
759 offset = NETXEN_USER_START +
760 offsetof(struct netxen_new_user_info, mac_addr) +
761 adapter->portnum * sizeof(u64);
763 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
766 if (*mac == cpu_to_le64(~0ULL)) {
768 offset = NETXEN_USER_START_OLD +
769 offsetof(struct netxen_user_old_info, mac_addr) +
770 adapter->portnum * sizeof(u64);
772 if (netxen_get_flash_block(adapter,
773 offset, sizeof(u64), pmac) == -1)
776 if (*mac == cpu_to_le64(~0ULL))
782 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
784 uint32_t crbaddr, mac_hi, mac_lo;
785 int pci_func = adapter->ahw.pci_func;
787 crbaddr = CRB_MAC_BLOCK_START +
788 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
790 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
791 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
794 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
796 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
801 #define CRB_WIN_LOCK_TIMEOUT 100000000
803 static int crb_win_lock(struct netxen_adapter *adapter)
805 int done = 0, timeout = 0;
808 /* acquire semaphore3 from PCI HW block */
809 adapter->hw_read_wx(adapter,
810 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
813 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
818 netxen_crb_writelit_adapter(adapter,
819 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
823 static void crb_win_unlock(struct netxen_adapter *adapter)
827 adapter->hw_read_wx(adapter,
828 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
832 * Changes the CRB window to the specified window.
835 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
837 void __iomem *offset;
840 uint8_t func = adapter->ahw.pci_func;
842 if (adapter->curr_window == wndw)
845 * Move the CRB window.
846 * We need to write to the "direct access" region of PCI
847 * to avoid a race condition where the window register has
848 * not been successfully written across CRB before the target
849 * register address is received by PCI. The direct region bypasses
852 offset = PCI_OFFSET_SECOND_RANGE(adapter,
853 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
856 wndw = NETXEN_WINDOW_ONE;
858 writel(wndw, offset);
860 /* MUST make sure window is set before we forge on... */
861 while ((tmp = readl(offset)) != wndw) {
862 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
863 "registered properly: 0x%08x.\n",
864 netxen_nic_driver_name, __func__, tmp);
871 if (wndw == NETXEN_WINDOW_ONE)
872 adapter->curr_window = 1;
874 adapter->curr_window = 0;
878 * Return -1 if off is not valid,
879 * 1 if window access is needed. 'off' is set to offset from
880 * CRB space in 128M pci map
881 * 0 if no window access is needed. 'off' is set to 2M addr
882 * In: 'off' is offset from base in 128M pci map
885 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
888 unsigned long end = *off + len;
889 crb_128M_2M_sub_block_map_t *m;
892 if (*off >= NETXEN_CRB_MAX)
895 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
896 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
897 (ulong)adapter->ahw.pci_base0;
901 if (*off < NETXEN_PCI_CRBSPACE)
904 *off -= NETXEN_PCI_CRBSPACE;
910 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
912 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
913 *off = *off + m->start_2M - m->start_128M +
914 (ulong)adapter->ahw.pci_base0;
919 * Not in direct map, use crb window
925 * In: 'off' is offset from CRB space in 128M pci map
926 * Out: 'off' is 2M pci map addr
927 * side effect: lock crb window
930 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
934 adapter->crb_win = CRB_HI(*off);
935 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
937 * Read back value to make sure write has gone through before trying
940 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
941 if (win_read != adapter->crb_win) {
942 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
943 "Read crbwin (0x%x), off=0x%lx\n",
944 __func__, adapter->crb_win, win_read, *off);
946 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
947 (ulong)adapter->ahw.pci_base0;
951 netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
952 const struct firmware *fw)
955 u32 i, flashaddr, size;
956 struct pci_dev *pdev = adapter->pdev;
959 dev_info(&pdev->dev, "loading firmware from file %s\n", fwname);
961 dev_info(&pdev->dev, "loading firmware from flash\n");
963 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
964 adapter->pci_write_normalize(adapter,
965 NETXEN_ROMUSB_GLB_CAS_RST, 1);
970 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
972 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
973 flashaddr = NETXEN_BOOTLD_START;
975 for (i = 0; i < size; i++) {
976 data = cpu_to_le64(ptr64[i]);
977 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
981 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
982 size = (__force u32)cpu_to_le32(size) / 8;
984 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
985 flashaddr = NETXEN_IMAGE_START;
987 for (i = 0; i < size; i++) {
988 data = cpu_to_le64(ptr64[i]);
990 if (adapter->pci_mem_write(adapter,
991 flashaddr, &data, 8))
999 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
1000 flashaddr = NETXEN_BOOTLD_START;
1002 for (i = 0; i < size; i++) {
1003 if (netxen_rom_fast_read(adapter,
1004 flashaddr, (int *)&data) != 0)
1007 if (adapter->pci_mem_write(adapter,
1008 flashaddr, &data, 4))
1016 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1017 adapter->pci_write_normalize(adapter,
1018 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1020 adapter->pci_write_normalize(adapter,
1021 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1022 adapter->pci_write_normalize(adapter,
1023 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1030 netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1031 const struct firmware *fw)
1034 u32 major, minor, build, ver, min_ver, bios;
1035 struct pci_dev *pdev = adapter->pdev;
1037 if (fw->size < NX_FW_MIN_SIZE)
1040 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1041 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1044 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
1045 major = (__force u32)val & 0xff;
1046 minor = ((__force u32)val >> 8) & 0xff;
1047 build = (__force u32)val >> 16;
1049 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1050 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1052 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1054 ver = NETXEN_VERSION_CODE(major, minor, build);
1056 if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
1058 "%s: firmware version %d.%d.%d unsupported\n",
1059 fwname, major, minor, build);
1063 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
1064 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1065 if ((__force u32)val != bios) {
1066 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1071 /* check if flashed firmware is newer */
1072 if (netxen_rom_fast_read(adapter,
1073 NX_FW_VERSION_OFFSET, (int *)&val))
1075 major = (__force u32)val & 0xff;
1076 minor = ((__force u32)val >> 8) & 0xff;
1077 build = (__force u32)val >> 16;
1078 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1081 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc),
1082 NETXEN_BDINFO_MAGIC);
1086 int netxen_load_firmware(struct netxen_adapter *adapter)
1088 u32 capability, flashed_ver;
1089 const struct firmware *fw;
1090 char *fw_name = NULL;
1091 struct pci_dev *pdev = adapter->pdev;
1094 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1095 fw_name = NX_P2_MN_ROMIMAGE;
1099 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1100 fw_name = NX_P3_CT_ROMIMAGE;
1107 netxen_rom_fast_read(adapter,
1108 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1109 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1110 adapter->hw_read_wx(adapter,
1111 NX_PEG_TUNE_CAPABILITY, &capability, 4);
1112 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1113 fw_name = NX_P3_MN_ROMIMAGE;
1119 rc = request_firmware(&fw, fw_name, &pdev->dev);
1121 if (fw_name == NX_P3_CT_ROMIMAGE) {
1130 rc = netxen_validate_firmware(adapter, fw_name, fw);
1132 release_firmware(fw);
1134 if (fw_name == NX_P3_CT_ROMIMAGE) {
1143 rc = netxen_do_load_firmware(adapter, fw_name, fw);
1146 release_firmware(fw);
1151 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1152 ulong off, void *data, int len)
1158 if (ADDR_IN_WINDOW1(off)) {
1159 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1160 } else { /* Window 0 */
1161 addr = pci_base_offset(adapter, off);
1162 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1166 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1170 writel(*(u32 *) data, addr);
1172 if (!ADDR_IN_WINDOW1(off))
1173 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1179 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1180 ulong off, void *data, int len)
1186 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1187 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1188 } else { /* Window 0 */
1189 addr = pci_base_offset(adapter, off);
1190 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1194 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1198 *(u32 *)data = readl(addr);
1200 if (!ADDR_IN_WINDOW1(off))
1201 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1207 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1208 ulong off, void *data, int len)
1210 unsigned long flags = 0;
1215 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1218 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1225 write_lock_irqsave(&adapter->adapter_lock, flags);
1226 crb_win_lock(adapter);
1227 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1228 writel(*(uint32_t *)data, (void __iomem *)off);
1229 crb_win_unlock(adapter);
1230 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1232 writel(*(uint32_t *)data, (void __iomem *)off);
1239 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1240 ulong off, void *data, int len)
1242 unsigned long flags = 0;
1247 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1250 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1257 write_lock_irqsave(&adapter->adapter_lock, flags);
1258 crb_win_lock(adapter);
1259 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1260 *(uint32_t *)data = readl((void __iomem *)off);
1261 crb_win_unlock(adapter);
1262 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1264 *(uint32_t *)data = readl((void __iomem *)off);
1269 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1271 adapter->hw_write_wx(adapter, off, &val, 4);
1274 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1277 adapter->hw_read_wx(adapter, off, &val, 4);
1281 /* Change the window to 0, write and change back to window 1. */
1282 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1284 adapter->hw_write_wx(adapter, index, &value, 4);
1287 /* Change the window to 0, read and change back to window 1. */
1288 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1290 adapter->hw_read_wx(adapter, index, value, 4);
1293 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1295 adapter->hw_write_wx(adapter, index, &value, 4);
1298 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1300 adapter->hw_read_wx(adapter, index, value, 4);
1304 * check memory access boundary.
1305 * used by test agent. support ddr access only for now
1307 static unsigned long
1308 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1309 unsigned long long addr, int size)
1311 if (!ADDR_IN_RANGE(addr,
1312 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1313 !ADDR_IN_RANGE(addr+size-1,
1314 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1315 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1322 static int netxen_pci_set_window_warning_count;
1325 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1326 unsigned long long addr)
1328 void __iomem *offset;
1330 unsigned long long qdr_max;
1331 uint8_t func = adapter->ahw.pci_func;
1333 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1334 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1336 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1339 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1340 /* DDR network side */
1341 addr -= NETXEN_ADDR_DDR_NET;
1342 window = (addr >> 25) & 0x3ff;
1343 if (adapter->ahw.ddr_mn_window != window) {
1344 adapter->ahw.ddr_mn_window = window;
1345 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1346 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1347 writel(window, offset);
1348 /* MUST make sure window is set before we forge on... */
1351 addr -= (window * NETXEN_WINDOW_ONE);
1352 addr += NETXEN_PCI_DDR_NET;
1353 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1354 addr -= NETXEN_ADDR_OCM0;
1355 addr += NETXEN_PCI_OCM0;
1356 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1357 addr -= NETXEN_ADDR_OCM1;
1358 addr += NETXEN_PCI_OCM1;
1359 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1360 /* QDR network side */
1361 addr -= NETXEN_ADDR_QDR_NET;
1362 window = (addr >> 22) & 0x3f;
1363 if (adapter->ahw.qdr_sn_window != window) {
1364 adapter->ahw.qdr_sn_window = window;
1365 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1366 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1367 writel((window << 22), offset);
1368 /* MUST make sure window is set before we forge on... */
1371 addr -= (window * 0x400000);
1372 addr += NETXEN_PCI_QDR_NET;
1375 * peg gdb frequently accesses memory that doesn't exist,
1376 * this limits the chit chat so debugging isn't slowed down.
1378 if ((netxen_pci_set_window_warning_count++ < 8)
1379 || (netxen_pci_set_window_warning_count % 64 == 0))
1380 printk("%s: Warning:netxen_nic_pci_set_window()"
1381 " Unknown address range!\n",
1382 netxen_nic_driver_name);
1389 * Note : only 32-bit writes!
1391 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1394 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1398 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1400 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1403 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1406 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1409 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1411 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1415 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1416 unsigned long long addr)
1421 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1422 /* DDR network side */
1423 window = MN_WIN(addr);
1424 adapter->ahw.ddr_mn_window = window;
1425 adapter->hw_write_wx(adapter,
1426 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1428 adapter->hw_read_wx(adapter,
1429 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1431 if ((win_read << 17) != window) {
1432 printk(KERN_INFO "Written MNwin (0x%x) != "
1433 "Read MNwin (0x%x)\n", window, win_read);
1435 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1436 } else if (ADDR_IN_RANGE(addr,
1437 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1438 if ((addr & 0x00ff800) == 0xff800) {
1439 printk("%s: QM access not handled.\n", __func__);
1443 window = OCM_WIN(addr);
1444 adapter->ahw.ddr_mn_window = window;
1445 adapter->hw_write_wx(adapter,
1446 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1448 adapter->hw_read_wx(adapter,
1449 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1451 if ((win_read >> 7) != window) {
1452 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1453 "Read OCMwin (0x%x)\n",
1454 __func__, window, win_read);
1456 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1458 } else if (ADDR_IN_RANGE(addr,
1459 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1460 /* QDR network side */
1461 window = MS_WIN(addr);
1462 adapter->ahw.qdr_sn_window = window;
1463 adapter->hw_write_wx(adapter,
1464 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1466 adapter->hw_read_wx(adapter,
1467 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1469 if (win_read != window) {
1470 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1471 "Read MSwin (0x%x)\n",
1472 __func__, window, win_read);
1474 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1478 * peg gdb frequently accesses memory that doesn't exist,
1479 * this limits the chit chat so debugging isn't slowed down.
1481 if ((netxen_pci_set_window_warning_count++ < 8)
1482 || (netxen_pci_set_window_warning_count%64 == 0)) {
1483 printk("%s: Warning:%s Unknown address range!\n",
1484 __func__, netxen_nic_driver_name);
1491 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1492 unsigned long long addr)
1495 unsigned long long qdr_max;
1497 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1498 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1500 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1502 if (ADDR_IN_RANGE(addr,
1503 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1504 /* DDR network side */
1505 BUG(); /* MN access can not come here */
1506 } else if (ADDR_IN_RANGE(addr,
1507 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1509 } else if (ADDR_IN_RANGE(addr,
1510 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1512 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1513 /* QDR network side */
1514 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1515 if (adapter->ahw.qdr_sn_window == window)
1522 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1523 u64 off, void *data, int size)
1525 unsigned long flags;
1526 void __iomem *addr, *mem_ptr = NULL;
1529 unsigned long mem_base;
1530 unsigned long mem_page;
1532 write_lock_irqsave(&adapter->adapter_lock, flags);
1535 * If attempting to access unknown address or straddle hw windows,
1538 start = adapter->pci_set_window(adapter, off);
1539 if ((start == -1UL) ||
1540 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1541 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1542 printk(KERN_ERR "%s out of bound pci memory access. "
1543 "offset is 0x%llx\n", netxen_nic_driver_name,
1544 (unsigned long long)off);
1548 addr = pci_base_offset(adapter, start);
1550 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1551 mem_base = pci_resource_start(adapter->pdev, 0);
1552 mem_page = start & PAGE_MASK;
1553 /* Map two pages whenever user tries to access addresses in two
1556 if (mem_page != ((start + size - 1) & PAGE_MASK))
1557 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1559 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1560 if (mem_ptr == NULL) {
1561 *(uint8_t *)data = 0;
1565 addr += start & (PAGE_SIZE - 1);
1566 write_lock_irqsave(&adapter->adapter_lock, flags);
1571 *(uint8_t *)data = readb(addr);
1574 *(uint16_t *)data = readw(addr);
1577 *(uint32_t *)data = readl(addr);
1580 *(uint64_t *)data = readq(addr);
1586 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1594 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1595 void *data, int size)
1597 unsigned long flags;
1598 void __iomem *addr, *mem_ptr = NULL;
1601 unsigned long mem_base;
1602 unsigned long mem_page;
1604 write_lock_irqsave(&adapter->adapter_lock, flags);
1607 * If attempting to access unknown address or straddle hw windows,
1610 start = adapter->pci_set_window(adapter, off);
1611 if ((start == -1UL) ||
1612 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1613 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1614 printk(KERN_ERR "%s out of bound pci memory access. "
1615 "offset is 0x%llx\n", netxen_nic_driver_name,
1616 (unsigned long long)off);
1620 addr = pci_base_offset(adapter, start);
1622 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1623 mem_base = pci_resource_start(adapter->pdev, 0);
1624 mem_page = start & PAGE_MASK;
1625 /* Map two pages whenever user tries to access addresses in two
1626 * consecutive pages.
1628 if (mem_page != ((start + size - 1) & PAGE_MASK))
1629 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1631 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1632 if (mem_ptr == NULL)
1635 addr += start & (PAGE_SIZE - 1);
1636 write_lock_irqsave(&adapter->adapter_lock, flags);
1641 writeb(*(uint8_t *)data, addr);
1644 writew(*(uint16_t *)data, addr);
1647 writel(*(uint32_t *)data, addr);
1650 writeq(*(uint64_t *)data, addr);
1656 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1662 #define MAX_CTL_CHECK 1000
1665 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1666 u64 off, void *data, int size)
1668 unsigned long flags;
1669 int i, j, ret = 0, loop, sz[2], off0;
1671 uint64_t off8, tmpw, word[2] = {0, 0};
1672 void __iomem *mem_crb;
1675 * If not MN, go check for MS or invalid.
1677 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1678 return netxen_nic_pci_mem_write_direct(adapter,
1681 off8 = off & 0xfffffff8;
1683 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1684 sz[1] = size - sz[0];
1685 loop = ((off0 + size - 1) >> 3) + 1;
1686 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1688 if ((size != 8) || (off0 != 0)) {
1689 for (i = 0; i < loop; i++) {
1690 if (adapter->pci_mem_read(adapter,
1691 off8 + (i << 3), &word[i], 8))
1698 tmpw = *((uint8_t *)data);
1701 tmpw = *((uint16_t *)data);
1704 tmpw = *((uint32_t *)data);
1708 tmpw = *((uint64_t *)data);
1711 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1712 word[0] |= tmpw << (off0 * 8);
1715 word[1] &= ~(~0ULL << (sz[1] * 8));
1716 word[1] |= tmpw >> (sz[0] * 8);
1719 write_lock_irqsave(&adapter->adapter_lock, flags);
1720 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1722 for (i = 0; i < loop; i++) {
1723 writel((uint32_t)(off8 + (i << 3)),
1724 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1726 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1727 writel(word[i] & 0xffffffff,
1728 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1729 writel((word[i] >> 32) & 0xffffffff,
1730 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1731 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1732 (mem_crb+MIU_TEST_AGT_CTRL));
1733 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1734 (mem_crb+MIU_TEST_AGT_CTRL));
1736 for (j = 0; j < MAX_CTL_CHECK; j++) {
1738 (mem_crb+MIU_TEST_AGT_CTRL));
1739 if ((temp & MIU_TA_CTL_BUSY) == 0)
1743 if (j >= MAX_CTL_CHECK) {
1744 if (printk_ratelimit())
1745 dev_err(&adapter->pdev->dev,
1746 "failed to write through agent\n");
1752 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1753 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1758 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1759 u64 off, void *data, int size)
1761 unsigned long flags;
1762 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1764 uint64_t off8, val, word[2] = {0, 0};
1765 void __iomem *mem_crb;
1769 * If not MN, go check for MS or invalid.
1771 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1772 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1774 off8 = off & 0xfffffff8;
1775 off0[0] = off & 0x7;
1777 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1778 sz[1] = size - sz[0];
1779 loop = ((off0[0] + size - 1) >> 3) + 1;
1780 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1782 write_lock_irqsave(&adapter->adapter_lock, flags);
1783 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1785 for (i = 0; i < loop; i++) {
1786 writel((uint32_t)(off8 + (i << 3)),
1787 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1789 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1790 writel(MIU_TA_CTL_ENABLE,
1791 (mem_crb+MIU_TEST_AGT_CTRL));
1792 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1793 (mem_crb+MIU_TEST_AGT_CTRL));
1795 for (j = 0; j < MAX_CTL_CHECK; j++) {
1797 (mem_crb+MIU_TEST_AGT_CTRL));
1798 if ((temp & MIU_TA_CTL_BUSY) == 0)
1802 if (j >= MAX_CTL_CHECK) {
1803 if (printk_ratelimit())
1804 dev_err(&adapter->pdev->dev,
1805 "failed to read through agent\n");
1809 start = off0[i] >> 2;
1810 end = (off0[i] + sz[i] - 1) >> 2;
1811 for (k = start; k <= end; k++) {
1812 word[i] |= ((uint64_t) readl(
1814 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1818 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1819 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1821 if (j >= MAX_CTL_CHECK)
1827 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1828 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1833 *(uint8_t *)data = val;
1836 *(uint16_t *)data = val;
1839 *(uint32_t *)data = val;
1842 *(uint64_t *)data = val;
1849 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1850 u64 off, void *data, int size)
1852 int i, j, ret = 0, loop, sz[2], off0;
1854 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1857 * If not MN, go check for MS or invalid.
1859 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1860 mem_crb = NETXEN_CRB_QDR_NET;
1862 mem_crb = NETXEN_CRB_DDR_NET;
1863 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1864 return netxen_nic_pci_mem_write_direct(adapter,
1868 off8 = off & 0xfffffff8;
1870 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1871 sz[1] = size - sz[0];
1872 loop = ((off0 + size - 1) >> 3) + 1;
1874 if ((size != 8) || (off0 != 0)) {
1875 for (i = 0; i < loop; i++) {
1876 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1884 tmpw = *((uint8_t *)data);
1887 tmpw = *((uint16_t *)data);
1890 tmpw = *((uint32_t *)data);
1894 tmpw = *((uint64_t *)data);
1898 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1899 word[0] |= tmpw << (off0 * 8);
1902 word[1] &= ~(~0ULL << (sz[1] * 8));
1903 word[1] |= tmpw >> (sz[0] * 8);
1907 * don't lock here - write_wx gets the lock if each time
1908 * write_lock_irqsave(&adapter->adapter_lock, flags);
1909 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1912 for (i = 0; i < loop; i++) {
1913 temp = off8 + (i << 3);
1914 adapter->hw_write_wx(adapter,
1915 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1917 adapter->hw_write_wx(adapter,
1918 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1919 temp = word[i] & 0xffffffff;
1920 adapter->hw_write_wx(adapter,
1921 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1922 temp = (word[i] >> 32) & 0xffffffff;
1923 adapter->hw_write_wx(adapter,
1924 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1925 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1926 adapter->hw_write_wx(adapter,
1927 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1928 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1929 adapter->hw_write_wx(adapter,
1930 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1932 for (j = 0; j < MAX_CTL_CHECK; j++) {
1933 adapter->hw_read_wx(adapter,
1934 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1935 if ((temp & MIU_TA_CTL_BUSY) == 0)
1939 if (j >= MAX_CTL_CHECK) {
1940 if (printk_ratelimit())
1941 dev_err(&adapter->pdev->dev,
1942 "failed to write through agent\n");
1949 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1950 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1956 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1957 u64 off, void *data, int size)
1959 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1961 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1964 * If not MN, go check for MS or invalid.
1967 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1968 mem_crb = NETXEN_CRB_QDR_NET;
1970 mem_crb = NETXEN_CRB_DDR_NET;
1971 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1972 return netxen_nic_pci_mem_read_direct(adapter,
1976 off8 = off & 0xfffffff8;
1977 off0[0] = off & 0x7;
1979 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1980 sz[1] = size - sz[0];
1981 loop = ((off0[0] + size - 1) >> 3) + 1;
1984 * don't lock here - write_wx gets the lock if each time
1985 * write_lock_irqsave(&adapter->adapter_lock, flags);
1986 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1989 for (i = 0; i < loop; i++) {
1990 temp = off8 + (i << 3);
1991 adapter->hw_write_wx(adapter,
1992 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1994 adapter->hw_write_wx(adapter,
1995 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1996 temp = MIU_TA_CTL_ENABLE;
1997 adapter->hw_write_wx(adapter,
1998 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1999 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2000 adapter->hw_write_wx(adapter,
2001 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2003 for (j = 0; j < MAX_CTL_CHECK; j++) {
2004 adapter->hw_read_wx(adapter,
2005 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2006 if ((temp & MIU_TA_CTL_BUSY) == 0)
2010 if (j >= MAX_CTL_CHECK) {
2011 if (printk_ratelimit())
2012 dev_err(&adapter->pdev->dev,
2013 "failed to read through agent\n");
2017 start = off0[i] >> 2;
2018 end = (off0[i] + sz[i] - 1) >> 2;
2019 for (k = start; k <= end; k++) {
2020 adapter->hw_read_wx(adapter,
2021 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
2022 word[i] |= ((uint64_t)temp << (32 * k));
2027 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2028 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2031 if (j >= MAX_CTL_CHECK)
2037 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2038 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2043 *(uint8_t *)data = val;
2046 *(uint16_t *)data = val;
2049 *(uint32_t *)data = val;
2052 *(uint64_t *)data = val;
2059 * Note : only 32-bit writes!
2061 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2064 adapter->hw_write_wx(adapter, off, &data, 4);
2069 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2072 adapter->hw_read_wx(adapter, off, &temp, 4);
2076 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2079 adapter->hw_write_wx(adapter, off, &data, 4);
2082 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2085 adapter->hw_read_wx(adapter, off, &temp, 4);
2089 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2091 int offset, board_type, magic, header_version;
2092 struct pci_dev *pdev = adapter->pdev;
2094 offset = NETXEN_BRDCFG_START +
2095 offsetof(struct netxen_board_info, magic);
2096 if (netxen_rom_fast_read(adapter, offset, &magic))
2099 offset = NETXEN_BRDCFG_START +
2100 offsetof(struct netxen_board_info, header_version);
2101 if (netxen_rom_fast_read(adapter, offset, &header_version))
2104 if (magic != NETXEN_BDINFO_MAGIC ||
2105 header_version != NETXEN_BDINFO_VERSION) {
2107 "invalid board config, magic=%08x, version=%08x\n",
2108 magic, header_version);
2112 offset = NETXEN_BRDCFG_START +
2113 offsetof(struct netxen_board_info, board_type);
2114 if (netxen_rom_fast_read(adapter, offset, &board_type))
2117 adapter->ahw.board_type = board_type;
2119 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2120 u32 gpio = netxen_nic_reg_read(adapter,
2121 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2122 if ((gpio & 0x8000) == 0)
2123 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2126 switch ((netxen_brdtype_t)board_type) {
2127 case NETXEN_BRDTYPE_P2_SB35_4G:
2128 adapter->ahw.port_type = NETXEN_NIC_GBE;
2130 case NETXEN_BRDTYPE_P2_SB31_10G:
2131 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2132 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2133 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2134 case NETXEN_BRDTYPE_P3_HMEZ:
2135 case NETXEN_BRDTYPE_P3_XG_LOM:
2136 case NETXEN_BRDTYPE_P3_10G_CX4:
2137 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2138 case NETXEN_BRDTYPE_P3_IMEZ:
2139 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2140 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2141 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2142 case NETXEN_BRDTYPE_P3_10G_XFP:
2143 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2144 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2146 case NETXEN_BRDTYPE_P1_BD:
2147 case NETXEN_BRDTYPE_P1_SB:
2148 case NETXEN_BRDTYPE_P1_SMAX:
2149 case NETXEN_BRDTYPE_P1_SOCK:
2150 case NETXEN_BRDTYPE_P3_REF_QG:
2151 case NETXEN_BRDTYPE_P3_4_GB:
2152 case NETXEN_BRDTYPE_P3_4_GB_MM:
2153 adapter->ahw.port_type = NETXEN_NIC_GBE;
2155 case NETXEN_BRDTYPE_P3_10G_TP:
2156 adapter->ahw.port_type = (adapter->portnum < 2) ?
2157 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2160 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2161 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2168 /* NIU access sections */
2170 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2172 new_mtu += MTU_FUDGE_FACTOR;
2173 netxen_nic_write_w0(adapter,
2174 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2179 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2181 new_mtu += MTU_FUDGE_FACTOR;
2182 if (adapter->physical_port == 0)
2183 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2186 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2192 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2193 unsigned long off, int data)
2195 adapter->hw_write_wx(adapter, off, &data, 4);
2198 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2204 if (!netif_carrier_ok(adapter->netdev)) {
2205 adapter->link_speed = 0;
2206 adapter->link_duplex = -1;
2207 adapter->link_autoneg = AUTONEG_ENABLE;
2211 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2212 adapter->hw_read_wx(adapter,
2213 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2214 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2215 adapter->link_speed = SPEED_1000;
2216 adapter->link_duplex = DUPLEX_FULL;
2217 adapter->link_autoneg = AUTONEG_DISABLE;
2221 if (adapter->phy_read
2222 && adapter->phy_read(adapter,
2223 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2225 if (netxen_get_phy_link(status)) {
2226 switch (netxen_get_phy_speed(status)) {
2228 adapter->link_speed = SPEED_10;
2231 adapter->link_speed = SPEED_100;
2234 adapter->link_speed = SPEED_1000;
2237 adapter->link_speed = 0;
2240 switch (netxen_get_phy_duplex(status)) {
2242 adapter->link_duplex = DUPLEX_HALF;
2245 adapter->link_duplex = DUPLEX_FULL;
2248 adapter->link_duplex = -1;
2251 if (adapter->phy_read
2252 && adapter->phy_read(adapter,
2253 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2255 adapter->link_autoneg = autoneg;
2260 adapter->link_speed = 0;
2261 adapter->link_duplex = -1;
2266 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2268 u32 fw_major, fw_minor, fw_build;
2269 char brd_name[NETXEN_MAX_SHORT_NAME];
2270 char serial_num[32];
2273 struct pci_dev *pdev = adapter->pdev;
2275 adapter->driver_mismatch = 0;
2277 ptr32 = (int *)&serial_num;
2278 addr = NETXEN_USER_START +
2279 offsetof(struct netxen_new_user_info, serial_num);
2280 for (i = 0; i < 8; i++) {
2281 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2282 dev_err(&pdev->dev, "error reading board info\n");
2283 adapter->driver_mismatch = 1;
2286 ptr32[i] = cpu_to_le32(val);
2287 addr += sizeof(u32);
2290 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2291 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2292 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2294 adapter->fw_major = fw_major;
2295 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2297 if (adapter->portnum == 0) {
2298 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2300 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2301 brd_name, serial_num, adapter->ahw.revision_id);
2304 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2305 adapter->driver_mismatch = 1;
2306 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2307 fw_major, fw_minor, fw_build);
2311 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2312 fw_major, fw_minor, fw_build);
2314 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2315 adapter->hw_read_wx(adapter,
2316 NETXEN_MIU_MN_CONTROL, &i, 4);
2317 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2318 dev_info(&pdev->dev, "firmware running in %s mode\n",
2319 adapter->ahw.cut_through ? "cut-through" : "legacy");