2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define MS_WIN(addr) (addr & 0x0ffc0000)
36 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38 #define CRB_BLK(off) ((off >> 20) & 0x3f)
39 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
40 #define CRB_WINDOW_2M (0x130060)
41 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
42 #define CRB_INDIRECT_2M (0x1e0000UL)
45 static inline u64 readq(void __iomem *addr)
47 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
52 static inline void writeq(u64 val, void __iomem *addr)
54 writel(((u32) (val)), (addr));
55 writel(((u32) (val >> 32)), (addr + 4));
59 #define ADDR_IN_RANGE(addr, low, high) \
60 (((addr) < (high)) && ((addr) >= (low)))
62 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
63 ((adapter)->ahw.pci_base0 + (off))
64 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
65 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
66 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
67 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
69 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
72 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
73 return PCI_OFFSET_FIRST_RANGE(adapter, off);
75 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
76 return PCI_OFFSET_SECOND_RANGE(adapter, off);
78 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
79 return PCI_OFFSET_THIRD_RANGE(adapter, off);
84 static crb_128M_2M_block_map_t
85 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
86 {{{0, 0, 0, 0} } }, /* 0: PCI */
87 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
88 {1, 0x0110000, 0x0120000, 0x130000},
89 {1, 0x0120000, 0x0122000, 0x124000},
90 {1, 0x0130000, 0x0132000, 0x126000},
91 {1, 0x0140000, 0x0142000, 0x128000},
92 {1, 0x0150000, 0x0152000, 0x12a000},
93 {1, 0x0160000, 0x0170000, 0x110000},
94 {1, 0x0170000, 0x0172000, 0x12e000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {1, 0x01e0000, 0x01e0800, 0x122000},
102 {0, 0x0000000, 0x0000000, 0x000000} } },
103 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
104 {{{0, 0, 0, 0} } }, /* 3: */
105 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
106 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
107 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
108 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
109 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x08f0000, 0x08f2000, 0x172000} } },
125 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x09f0000, 0x09f2000, 0x176000} } },
141 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
157 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
173 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
174 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
175 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
176 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
177 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
178 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
179 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
180 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
181 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
182 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
183 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
184 {{{0, 0, 0, 0} } }, /* 23: */
185 {{{0, 0, 0, 0} } }, /* 24: */
186 {{{0, 0, 0, 0} } }, /* 25: */
187 {{{0, 0, 0, 0} } }, /* 26: */
188 {{{0, 0, 0, 0} } }, /* 27: */
189 {{{0, 0, 0, 0} } }, /* 28: */
190 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
191 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
192 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
193 {{{0} } }, /* 32: PCI */
194 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
195 {1, 0x2110000, 0x2120000, 0x130000},
196 {1, 0x2120000, 0x2122000, 0x124000},
197 {1, 0x2130000, 0x2132000, 0x126000},
198 {1, 0x2140000, 0x2142000, 0x128000},
199 {1, 0x2150000, 0x2152000, 0x12a000},
200 {1, 0x2160000, 0x2170000, 0x110000},
201 {1, 0x2170000, 0x2172000, 0x12e000},
202 {0, 0x0000000, 0x0000000, 0x000000},
203 {0, 0x0000000, 0x0000000, 0x000000},
204 {0, 0x0000000, 0x0000000, 0x000000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000} } },
210 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
216 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
217 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
218 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
219 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
220 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
221 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
222 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
223 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
224 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
225 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
226 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
227 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
229 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
230 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
231 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
232 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
233 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
234 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
235 {{{0} } }, /* 59: I2C0 */
236 {{{0} } }, /* 60: I2C1 */
237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
238 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
239 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
243 * top 12 bits of crb internal address (hub, agent)
245 static unsigned crb_hub_agt[64] =
248 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
249 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
250 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
252 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
253 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
254 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
260 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
261 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
278 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
281 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
287 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
290 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
296 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
297 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
298 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
303 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
309 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
313 /* PCI Windowing for DDR regions. */
315 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
317 #define NETXEN_PCIE_SEM_TIMEOUT 10000
320 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
322 int done = 0, timeout = 0;
325 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
328 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
334 NXWR32(adapter, id_reg, adapter->portnum);
340 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
343 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
346 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
348 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
349 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
350 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
356 /* Disable an XG interface */
357 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
360 u32 port = adapter->physical_port;
362 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
365 if (port > NETXEN_NIU_MAX_XG_PORTS)
370 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
375 #define NETXEN_UNICAST_ADDR(port, index) \
376 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
377 #define NETXEN_MCAST_ADDR(port, index) \
378 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
379 #define MAC_HI(addr) \
380 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
381 #define MAC_LO(addr) \
382 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
384 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
387 u32 port = adapter->physical_port;
389 if (port > NETXEN_NIU_MAX_XG_PORTS)
392 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
393 if (mode == NETXEN_NIU_PROMISC_MODE)
394 reg = (reg | 0x2000UL);
396 reg = (reg & ~0x2000UL);
398 if (mode == NETXEN_NIU_ALLMULTI_MODE)
399 reg = (reg | 0x1000UL);
401 reg = (reg & ~0x1000UL);
403 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
408 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
413 u8 phy = adapter->physical_port;
415 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
418 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
419 mac_hi = addr[2] | ((u32)addr[3] << 8) |
420 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
422 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
423 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
425 /* write twice to flush */
426 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
428 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
435 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
438 u16 port = adapter->physical_port;
439 u8 *addr = adapter->netdev->dev_addr;
441 if (adapter->mc_enabled)
444 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
445 val |= (1UL << (28+port));
446 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
448 /* add broadcast addr to filter */
450 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
451 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
453 /* add station addr to filter */
455 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
457 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
459 adapter->mc_enabled = 1;
464 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
467 u16 port = adapter->physical_port;
468 u8 *addr = adapter->netdev->dev_addr;
470 if (!adapter->mc_enabled)
473 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
474 val &= ~(1UL << (28+port));
475 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
478 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
480 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
485 adapter->mc_enabled = 0;
490 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
494 u16 port = adapter->physical_port;
499 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
500 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
505 void netxen_p2_nic_set_multi(struct net_device *netdev)
507 struct netxen_adapter *adapter = netdev_priv(netdev);
508 struct dev_mc_list *mc_ptr;
512 memset(null_addr, 0, 6);
514 if (netdev->flags & IFF_PROMISC) {
516 adapter->set_promisc(adapter,
517 NETXEN_NIU_PROMISC_MODE);
519 /* Full promiscuous mode */
520 netxen_nic_disable_mcast_filter(adapter);
525 if (netdev->mc_count == 0) {
526 adapter->set_promisc(adapter,
527 NETXEN_NIU_NON_PROMISC_MODE);
528 netxen_nic_disable_mcast_filter(adapter);
532 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
533 if (netdev->flags & IFF_ALLMULTI ||
534 netdev->mc_count > adapter->max_mc_count) {
535 netxen_nic_disable_mcast_filter(adapter);
539 netxen_nic_enable_mcast_filter(adapter);
541 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
542 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
544 if (index != netdev->mc_count)
545 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
546 netxen_nic_driver_name, netdev->name);
548 /* Clear out remaining addresses */
549 for (; index < adapter->max_mc_count; index++)
550 netxen_nic_set_mcast_addr(adapter, index, null_addr);
554 netxen_send_cmd_descs(struct netxen_adapter *adapter,
555 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
557 u32 i, producer, consumer;
558 struct netxen_cmd_buffer *pbuf;
559 struct cmd_desc_type0 *cmd_desc;
560 struct nx_host_tx_ring *tx_ring;
564 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
567 tx_ring = adapter->tx_ring;
568 __netif_tx_lock_bh(tx_ring->txq);
570 producer = tx_ring->producer;
571 consumer = tx_ring->sw_consumer;
573 if (nr_desc >= netxen_tx_avail(tx_ring)) {
574 netif_tx_stop_queue(tx_ring->txq);
575 __netif_tx_unlock_bh(tx_ring->txq);
580 cmd_desc = &cmd_desc_arr[i];
582 pbuf = &tx_ring->cmd_buf_arr[producer];
584 pbuf->frag_count = 0;
586 memcpy(&tx_ring->desc_head[producer],
587 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
589 producer = get_next_index(producer, tx_ring->num_desc);
592 } while (i != nr_desc);
594 tx_ring->producer = producer;
596 netxen_nic_update_cmd_producer(adapter, tx_ring);
598 __netif_tx_unlock_bh(tx_ring->txq);
604 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
607 nx_mac_req_t *mac_req;
610 memset(&req, 0, sizeof(nx_nic_req_t));
611 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
613 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
614 req.req_hdr = cpu_to_le64(word);
616 mac_req = (nx_mac_req_t *)&req.words[0];
618 memcpy(mac_req->mac_addr, addr, 6);
620 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
623 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
624 u8 *addr, struct list_head *del_list)
626 struct list_head *head;
629 /* look up if already exists */
630 list_for_each(head, del_list) {
631 cur = list_entry(head, nx_mac_list_t, list);
633 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
634 list_move_tail(head, &adapter->mac_list);
639 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
641 printk(KERN_ERR "%s: failed to add mac address filter\n",
642 adapter->netdev->name);
645 memcpy(cur->mac_addr, addr, ETH_ALEN);
646 list_add_tail(&cur->list, &adapter->mac_list);
647 return nx_p3_sre_macaddr_change(adapter,
648 cur->mac_addr, NETXEN_MAC_ADD);
651 void netxen_p3_nic_set_multi(struct net_device *netdev)
653 struct netxen_adapter *adapter = netdev_priv(netdev);
654 struct dev_mc_list *mc_ptr;
655 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
656 u32 mode = VPORT_MISS_MODE_DROP;
658 struct list_head *head;
661 list_splice_tail_init(&adapter->mac_list, &del_list);
663 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
664 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
666 if (netdev->flags & IFF_PROMISC) {
667 mode = VPORT_MISS_MODE_ACCEPT_ALL;
671 if ((netdev->flags & IFF_ALLMULTI) ||
672 (netdev->mc_count > adapter->max_mc_count)) {
673 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
677 if (netdev->mc_count > 0) {
678 for (mc_ptr = netdev->mc_list; mc_ptr;
679 mc_ptr = mc_ptr->next) {
680 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
685 adapter->set_promisc(adapter, mode);
687 while (!list_empty(head)) {
688 cur = list_entry(head->next, nx_mac_list_t, list);
690 nx_p3_sre_macaddr_change(adapter,
691 cur->mac_addr, NETXEN_MAC_DEL);
692 list_del(&cur->list);
697 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
702 memset(&req, 0, sizeof(nx_nic_req_t));
704 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
706 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
707 ((u64)adapter->portnum << 16);
708 req.req_hdr = cpu_to_le64(word);
710 req.words[0] = cpu_to_le64(mode);
712 return netxen_send_cmd_descs(adapter,
713 (struct cmd_desc_type0 *)&req, 1);
716 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
719 struct list_head *head = &adapter->mac_list;
721 while (!list_empty(head)) {
722 cur = list_entry(head->next, nx_mac_list_t, list);
723 nx_p3_sre_macaddr_change(adapter,
724 cur->mac_addr, NETXEN_MAC_DEL);
725 list_del(&cur->list);
730 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
732 /* assuming caller has already copied new addr to netdev */
733 netxen_p3_nic_set_multi(adapter->netdev);
737 #define NETXEN_CONFIG_INTR_COALESCE 3
740 * Send the interrupt coalescing parameter set by ethtool to the card.
742 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
748 memset(&req, 0, sizeof(nx_nic_req_t));
750 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
752 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
753 req.req_hdr = cpu_to_le64(word);
755 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
757 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
759 printk(KERN_ERR "ERROR. Could not send "
760 "interrupt coalescing parameters\n");
766 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
772 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
775 memset(&req, 0, sizeof(nx_nic_req_t));
777 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
779 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
780 req.req_hdr = cpu_to_le64(word);
782 req.words[0] = cpu_to_le64(enable);
784 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
786 printk(KERN_ERR "ERROR. Could not send "
787 "configure hw lro request\n");
790 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
795 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
801 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
804 memset(&req, 0, sizeof(nx_nic_req_t));
806 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
808 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
809 ((u64)adapter->portnum << 16);
810 req.req_hdr = cpu_to_le64(word);
812 req.words[0] = cpu_to_le64(enable);
814 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
816 printk(KERN_ERR "ERROR. Could not send "
817 "configure bridge mode request\n");
820 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
826 #define RSS_HASHTYPE_IP_TCP 0x3
828 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
834 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
835 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
836 0x255b0ec26d5a56daULL };
839 memset(&req, 0, sizeof(nx_nic_req_t));
840 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
842 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
843 req.req_hdr = cpu_to_le64(word);
847 * bits 3-0: hash_method
848 * 5-4: hash_type_ipv4
849 * 7-6: hash_type_ipv6
851 * 9: use indirection table
853 * 63-48: indirection table mask
855 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
856 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
857 ((u64)(enable & 0x1) << 8) |
859 req.words[0] = cpu_to_le64(word);
860 for (i = 0; i < 5; i++)
861 req.words[i+1] = cpu_to_le64(key[i]);
864 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
866 printk(KERN_ERR "%s: could not configure RSS\n",
867 adapter->netdev->name);
873 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
879 memset(&req, 0, sizeof(nx_nic_req_t));
880 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
882 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
883 req.req_hdr = cpu_to_le64(word);
885 req.words[0] = cpu_to_le64(cmd);
886 req.words[1] = cpu_to_le64(ip);
888 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
890 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
891 adapter->netdev->name,
892 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
897 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
903 memset(&req, 0, sizeof(nx_nic_req_t));
904 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
906 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
907 req.req_hdr = cpu_to_le64(word);
908 req.words[0] = cpu_to_le64(enable | (enable << 8));
910 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
912 printk(KERN_ERR "%s: could not configure link notification\n",
913 adapter->netdev->name);
919 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
925 memset(&req, 0, sizeof(nx_nic_req_t));
926 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
928 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
929 ((u64)adapter->portnum << 16) |
930 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
932 req.req_hdr = cpu_to_le64(word);
934 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
936 printk(KERN_ERR "%s: could not cleanup lro flows\n",
937 adapter->netdev->name);
943 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
944 * @returns 0 on success, negative on failure
947 #define MTU_FUDGE_FACTOR 100
949 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
951 struct netxen_adapter *adapter = netdev_priv(netdev);
955 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
956 max_mtu = P3_MAX_MTU;
958 max_mtu = P2_MAX_MTU;
961 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
962 netdev->name, max_mtu);
966 if (adapter->set_mtu)
967 rc = adapter->set_mtu(adapter, mtu);
975 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
976 int size, __le32 * buf)
983 for (i = 0; i < size / sizeof(u32); i++) {
984 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
986 *ptr32 = cpu_to_le32(v);
990 if ((char *)buf + size > (char *)ptr32) {
992 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
994 local = cpu_to_le32(v);
995 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1001 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1003 __le32 *pmac = (__le32 *) mac;
1006 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1008 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1011 if (*mac == cpu_to_le64(~0ULL)) {
1013 offset = NX_OLD_MAC_ADDR_OFFSET +
1014 (adapter->portnum * sizeof(u64));
1016 if (netxen_get_flash_block(adapter,
1017 offset, sizeof(u64), pmac) == -1)
1020 if (*mac == cpu_to_le64(~0ULL))
1026 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1028 uint32_t crbaddr, mac_hi, mac_lo;
1029 int pci_func = adapter->ahw.pci_func;
1031 crbaddr = CRB_MAC_BLOCK_START +
1032 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1034 mac_lo = NXRD32(adapter, crbaddr);
1035 mac_hi = NXRD32(adapter, crbaddr+4);
1038 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1040 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1046 * Changes the CRB window to the specified window.
1049 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1052 void __iomem *offset;
1054 u8 func = adapter->ahw.pci_func;
1056 if (adapter->ahw.crb_win == window)
1059 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1060 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1062 writel(window, offset);
1064 if (window == readl(offset))
1067 if (printk_ratelimit())
1068 dev_warn(&adapter->pdev->dev,
1069 "failed to set CRB window to %d\n",
1070 (window == NETXEN_WINDOW_ONE));
1073 } while (--count > 0);
1076 adapter->ahw.crb_win = window;
1080 * Return -1 if off is not valid,
1081 * 1 if window access is needed. 'off' is set to offset from
1082 * CRB space in 128M pci map
1083 * 0 if no window access is needed. 'off' is set to 2M addr
1084 * In: 'off' is offset from base in 128M pci map
1087 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1089 crb_128M_2M_sub_block_map_t *m;
1092 if (*off >= NETXEN_CRB_MAX)
1095 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1096 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1097 (ulong)adapter->ahw.pci_base0;
1101 if (*off < NETXEN_PCI_CRBSPACE)
1104 *off -= NETXEN_PCI_CRBSPACE;
1109 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1111 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1112 *off = *off + m->start_2M - m->start_128M +
1113 (ulong)adapter->ahw.pci_base0;
1118 * Not in direct map, use crb window
1124 * In: 'off' is offset from CRB space in 128M pci map
1125 * Out: 'off' is 2M pci map addr
1126 * side effect: lock crb window
1129 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1132 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1134 window = CRB_HI(*off);
1136 if (adapter->ahw.crb_win == window)
1139 writel(window, addr);
1140 if (readl(addr) != window) {
1141 if (printk_ratelimit())
1142 dev_warn(&adapter->pdev->dev,
1143 "failed to set CRB window to %d off 0x%lx\n",
1146 adapter->ahw.crb_win = window;
1149 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1150 (ulong)adapter->ahw.pci_base0;
1154 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1156 unsigned long flags;
1159 if (ADDR_IN_WINDOW1(off))
1160 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1162 addr = pci_base_offset(adapter, off);
1166 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1167 read_lock(&adapter->adapter_lock);
1169 read_unlock(&adapter->adapter_lock);
1170 } else { /* Window 0 */
1171 write_lock_irqsave(&adapter->adapter_lock, flags);
1172 addr = pci_base_offset(adapter, off);
1173 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1175 netxen_nic_pci_set_crbwindow_128M(adapter,
1177 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1184 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1186 unsigned long flags;
1190 if (ADDR_IN_WINDOW1(off))
1191 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1193 addr = pci_base_offset(adapter, off);
1197 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1198 read_lock(&adapter->adapter_lock);
1200 read_unlock(&adapter->adapter_lock);
1201 } else { /* Window 0 */
1202 write_lock_irqsave(&adapter->adapter_lock, flags);
1203 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1205 netxen_nic_pci_set_crbwindow_128M(adapter,
1207 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1214 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1216 unsigned long flags;
1219 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1222 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1229 write_lock_irqsave(&adapter->adapter_lock, flags);
1230 crb_win_lock(adapter);
1231 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1232 writel(data, (void __iomem *)off);
1233 crb_win_unlock(adapter);
1234 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1236 writel(data, (void __iomem *)off);
1243 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1245 unsigned long flags;
1249 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1252 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1259 write_lock_irqsave(&adapter->adapter_lock, flags);
1260 crb_win_lock(adapter);
1261 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1262 data = readl((void __iomem *)off);
1263 crb_win_unlock(adapter);
1264 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1266 data = readl((void __iomem *)off);
1271 /* window 1 registers only */
1272 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1273 void __iomem *addr, u32 data)
1275 read_lock(&adapter->adapter_lock);
1277 read_unlock(&adapter->adapter_lock);
1280 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1285 read_lock(&adapter->adapter_lock);
1287 read_unlock(&adapter->adapter_lock);
1292 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1293 void __iomem *addr, u32 data)
1298 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1305 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1309 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1310 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1311 offset > NETXEN_CRB_PCIX_HOST)
1312 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1313 return NETXEN_CRB_NORMALIZE(adapter, offset);
1316 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1317 return (void __iomem *)off;
1321 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1322 u64 addr, u32 *start)
1324 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1325 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1327 } else if (ADDR_IN_RANGE(addr,
1328 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1329 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1337 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1338 u64 addr, u32 *start)
1340 u32 win_read, window;
1341 struct pci_dev *pdev = adapter->pdev;
1343 if ((addr & 0x00ff800) == 0xff800) {
1344 if (printk_ratelimit())
1345 dev_warn(&pdev->dev, "QM access not handled\n");
1349 window = OCM_WIN(addr);
1350 writel(window, adapter->ahw.ocm_win_crb);
1351 win_read = readl(adapter->ahw.ocm_win_crb);
1352 if ((win_read >> 7) != window) {
1353 if (printk_ratelimit())
1354 dev_warn(&pdev->dev, "failed to set OCM window\n");
1358 adapter->ahw.ocm_win = window;
1359 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1364 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1367 void __iomem *addr, *mem_ptr = NULL;
1368 resource_size_t mem_base;
1369 unsigned long flags;
1373 write_lock_irqsave(&adapter->adapter_lock, flags);
1375 ret = adapter->pci_set_window(adapter, off, &start);
1379 addr = pci_base_offset(adapter, start);
1383 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
1385 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1386 if (mem_ptr == NULL) {
1391 addr = mem_ptr + (start & (PAGE_SIZE - 1));
1394 if (op == 0) /* read */
1395 *data = readq(addr);
1397 writeq(*data, addr);
1400 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1406 #define MAX_CTL_CHECK 1000
1409 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1412 unsigned long flags;
1414 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1415 void __iomem *mem_crb;
1417 /* Only 64-bit aligned access */
1421 /* P2 has different SIU and MIU test agent base addr */
1422 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1423 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1424 mem_crb = pci_base_offset(adapter,
1425 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1426 addr_hi = SIU_TEST_AGT_ADDR_HI;
1427 data_lo = SIU_TEST_AGT_WRDATA_LO;
1428 data_hi = SIU_TEST_AGT_WRDATA_HI;
1429 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1430 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1434 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1435 mem_crb = pci_base_offset(adapter,
1436 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1437 addr_hi = MIU_TEST_AGT_ADDR_HI;
1438 data_lo = MIU_TEST_AGT_WRDATA_LO;
1439 data_hi = MIU_TEST_AGT_WRDATA_HI;
1440 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1445 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1446 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1447 if (adapter->ahw.pci_len0 != 0) {
1448 return netxen_nic_pci_mem_access_direct(adapter,
1456 write_lock_irqsave(&adapter->adapter_lock, flags);
1457 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1459 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1460 writel(off_hi, (mem_crb + addr_hi));
1461 writel(data & 0xffffffff, (mem_crb + data_lo));
1462 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1463 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1464 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1465 (mem_crb + TEST_AGT_CTRL));
1467 for (j = 0; j < MAX_CTL_CHECK; j++) {
1468 temp = readl((mem_crb + TEST_AGT_CTRL));
1469 if ((temp & TA_CTL_BUSY) == 0)
1473 if (j >= MAX_CTL_CHECK) {
1474 if (printk_ratelimit())
1475 dev_err(&adapter->pdev->dev,
1476 "failed to write through agent\n");
1481 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1482 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1487 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1490 unsigned long flags;
1492 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1494 void __iomem *mem_crb;
1496 /* Only 64-bit aligned access */
1500 /* P2 has different SIU and MIU test agent base addr */
1501 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1502 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1503 mem_crb = pci_base_offset(adapter,
1504 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1505 addr_hi = SIU_TEST_AGT_ADDR_HI;
1506 data_lo = SIU_TEST_AGT_RDDATA_LO;
1507 data_hi = SIU_TEST_AGT_RDDATA_HI;
1508 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1509 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1513 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1514 mem_crb = pci_base_offset(adapter,
1515 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1516 addr_hi = MIU_TEST_AGT_ADDR_HI;
1517 data_lo = MIU_TEST_AGT_RDDATA_LO;
1518 data_hi = MIU_TEST_AGT_RDDATA_HI;
1519 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1524 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1525 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1526 if (adapter->ahw.pci_len0 != 0) {
1527 return netxen_nic_pci_mem_access_direct(adapter,
1535 write_lock_irqsave(&adapter->adapter_lock, flags);
1536 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1538 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1539 writel(off_hi, (mem_crb + addr_hi));
1540 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1541 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1543 for (j = 0; j < MAX_CTL_CHECK; j++) {
1544 temp = readl(mem_crb + TEST_AGT_CTRL);
1545 if ((temp & TA_CTL_BUSY) == 0)
1549 if (j >= MAX_CTL_CHECK) {
1550 if (printk_ratelimit())
1551 dev_err(&adapter->pdev->dev,
1552 "failed to read through agent\n");
1556 temp = readl(mem_crb + data_hi);
1557 val = ((u64)temp << 32);
1558 val |= readl(mem_crb + data_lo);
1563 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1564 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1570 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1573 unsigned long flags;
1576 void __iomem *mem_crb;
1578 /* Only 64-bit aligned access */
1582 /* P3 onward, test agent base for MIU and SIU is same */
1583 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1584 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1585 mem_crb = netxen_get_ioaddr(adapter,
1586 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1590 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1591 mem_crb = netxen_get_ioaddr(adapter,
1592 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1596 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1597 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1602 off8 = off & MIU_TEST_AGT_ADDR_MASK;
1604 write_lock_irqsave(&adapter->adapter_lock, flags);
1606 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1607 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1608 writel(data & 0xffffffff, mem_crb + MIU_TEST_AGT_WRDATA_LO);
1609 writel((data >> 32) & 0xffffffff, mem_crb + MIU_TEST_AGT_WRDATA_HI);
1610 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1611 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1612 (mem_crb + TEST_AGT_CTRL));
1614 for (j = 0; j < MAX_CTL_CHECK; j++) {
1615 temp = readl(mem_crb + TEST_AGT_CTRL);
1616 if ((temp & TA_CTL_BUSY) == 0)
1620 if (j >= MAX_CTL_CHECK) {
1621 if (printk_ratelimit())
1622 dev_err(&adapter->pdev->dev,
1623 "failed to write through agent\n");
1628 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1634 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1637 unsigned long flags;
1641 void __iomem *mem_crb;
1643 /* Only 64-bit aligned access */
1647 /* P3 onward, test agent base for MIU and SIU is same */
1648 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1649 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1650 mem_crb = netxen_get_ioaddr(adapter,
1651 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1655 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1656 mem_crb = netxen_get_ioaddr(adapter,
1657 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1661 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1662 return netxen_nic_pci_mem_access_direct(adapter,
1669 off8 = off & MIU_TEST_AGT_ADDR_MASK;
1671 write_lock_irqsave(&adapter->adapter_lock, flags);
1673 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1674 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1675 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1676 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1678 for (j = 0; j < MAX_CTL_CHECK; j++) {
1679 temp = readl(mem_crb + TEST_AGT_CTRL);
1680 if ((temp & TA_CTL_BUSY) == 0)
1684 if (j >= MAX_CTL_CHECK) {
1685 if (printk_ratelimit())
1686 dev_err(&adapter->pdev->dev,
1687 "failed to read through agent\n");
1690 temp = readl(mem_crb + MIU_TEST_AGT_RDDATA_HI);
1691 val = (u64)temp << 32;
1692 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1697 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1703 netxen_setup_hwops(struct netxen_adapter *adapter)
1705 adapter->init_port = netxen_niu_xg_init_port;
1706 adapter->stop_port = netxen_niu_disable_xg_port;
1708 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1709 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1710 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1711 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1712 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1713 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1714 adapter->io_read = netxen_nic_io_read_128M,
1715 adapter->io_write = netxen_nic_io_write_128M,
1717 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1718 adapter->set_multi = netxen_p2_nic_set_multi;
1719 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1720 adapter->set_promisc = netxen_p2_nic_set_promisc;
1723 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1724 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1725 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1726 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1727 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1728 adapter->io_read = netxen_nic_io_read_2M,
1729 adapter->io_write = netxen_nic_io_write_2M,
1731 adapter->set_mtu = nx_fw_cmd_set_mtu;
1732 adapter->set_promisc = netxen_p3_nic_set_promisc;
1733 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1734 adapter->set_multi = netxen_p3_nic_set_multi;
1736 adapter->phy_read = nx_fw_cmd_query_phy;
1737 adapter->phy_write = nx_fw_cmd_set_phy;
1741 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1743 int offset, board_type, magic, header_version;
1744 struct pci_dev *pdev = adapter->pdev;
1746 offset = NX_FW_MAGIC_OFFSET;
1747 if (netxen_rom_fast_read(adapter, offset, &magic))
1750 offset = NX_HDR_VERSION_OFFSET;
1751 if (netxen_rom_fast_read(adapter, offset, &header_version))
1754 if (magic != NETXEN_BDINFO_MAGIC ||
1755 header_version != NETXEN_BDINFO_VERSION) {
1757 "invalid board config, magic=%08x, version=%08x\n",
1758 magic, header_version);
1762 offset = NX_BRDTYPE_OFFSET;
1763 if (netxen_rom_fast_read(adapter, offset, &board_type))
1766 adapter->ahw.board_type = board_type;
1768 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1769 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1770 if ((gpio & 0x8000) == 0)
1771 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1774 switch (board_type) {
1775 case NETXEN_BRDTYPE_P2_SB35_4G:
1776 adapter->ahw.port_type = NETXEN_NIC_GBE;
1778 case NETXEN_BRDTYPE_P2_SB31_10G:
1779 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1780 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1781 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1782 case NETXEN_BRDTYPE_P3_HMEZ:
1783 case NETXEN_BRDTYPE_P3_XG_LOM:
1784 case NETXEN_BRDTYPE_P3_10G_CX4:
1785 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1786 case NETXEN_BRDTYPE_P3_IMEZ:
1787 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1788 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1789 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1790 case NETXEN_BRDTYPE_P3_10G_XFP:
1791 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1792 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1794 case NETXEN_BRDTYPE_P1_BD:
1795 case NETXEN_BRDTYPE_P1_SB:
1796 case NETXEN_BRDTYPE_P1_SMAX:
1797 case NETXEN_BRDTYPE_P1_SOCK:
1798 case NETXEN_BRDTYPE_P3_REF_QG:
1799 case NETXEN_BRDTYPE_P3_4_GB:
1800 case NETXEN_BRDTYPE_P3_4_GB_MM:
1801 adapter->ahw.port_type = NETXEN_NIC_GBE;
1803 case NETXEN_BRDTYPE_P3_10G_TP:
1804 adapter->ahw.port_type = (adapter->portnum < 2) ?
1805 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1808 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1809 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1816 /* NIU access sections */
1818 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1820 new_mtu += MTU_FUDGE_FACTOR;
1821 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1826 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1828 new_mtu += MTU_FUDGE_FACTOR;
1829 if (adapter->physical_port == 0)
1830 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1832 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1836 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1842 if (!netif_carrier_ok(adapter->netdev)) {
1843 adapter->link_speed = 0;
1844 adapter->link_duplex = -1;
1845 adapter->link_autoneg = AUTONEG_ENABLE;
1849 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1850 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1851 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1852 adapter->link_speed = SPEED_1000;
1853 adapter->link_duplex = DUPLEX_FULL;
1854 adapter->link_autoneg = AUTONEG_DISABLE;
1858 if (adapter->phy_read
1859 && adapter->phy_read(adapter,
1860 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1862 if (netxen_get_phy_link(status)) {
1863 switch (netxen_get_phy_speed(status)) {
1865 adapter->link_speed = SPEED_10;
1868 adapter->link_speed = SPEED_100;
1871 adapter->link_speed = SPEED_1000;
1874 adapter->link_speed = 0;
1877 switch (netxen_get_phy_duplex(status)) {
1879 adapter->link_duplex = DUPLEX_HALF;
1882 adapter->link_duplex = DUPLEX_FULL;
1885 adapter->link_duplex = -1;
1888 if (adapter->phy_read
1889 && adapter->phy_read(adapter,
1890 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1892 adapter->link_autoneg = autoneg;
1897 adapter->link_speed = 0;
1898 adapter->link_duplex = -1;
1904 netxen_nic_wol_supported(struct netxen_adapter *adapter)
1908 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1911 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1912 if (wol_cfg & (1UL << adapter->portnum)) {
1913 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1914 if (wol_cfg & (1 << adapter->portnum))