2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
35 #define MS_WIN(addr) (addr & 0x0ffc0000)
37 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
39 #define CRB_BLK(off) ((off >> 20) & 0x3f)
40 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41 #define CRB_WINDOW_2M (0x130060)
42 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43 #define CRB_INDIRECT_2M (0x1e0000UL)
45 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
51 static inline u64 readq(void __iomem *addr)
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
58 static inline void writeq(u64 val, void __iomem *addr)
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
65 #define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
68 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
75 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
90 static crb_128M_2M_block_map_t
91 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
92 {{{0, 0, 0, 0} } }, /* 0: PCI */
93 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
94 {1, 0x0110000, 0x0120000, 0x130000},
95 {1, 0x0120000, 0x0122000, 0x124000},
96 {1, 0x0130000, 0x0132000, 0x126000},
97 {1, 0x0140000, 0x0142000, 0x128000},
98 {1, 0x0150000, 0x0152000, 0x12a000},
99 {1, 0x0160000, 0x0170000, 0x110000},
100 {1, 0x0170000, 0x0172000, 0x12e000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x01e0000, 0x01e0800, 0x122000},
108 {0, 0x0000000, 0x0000000, 0x000000} } },
109 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
110 {{{0, 0, 0, 0} } }, /* 3: */
111 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
112 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
113 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
114 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
115 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {1, 0x08f0000, 0x08f2000, 0x172000} } },
131 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {1, 0x09f0000, 0x09f2000, 0x176000} } },
147 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
163 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
179 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
180 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
181 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
182 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
183 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
184 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
185 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
186 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
187 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
188 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
189 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
190 {{{0, 0, 0, 0} } }, /* 23: */
191 {{{0, 0, 0, 0} } }, /* 24: */
192 {{{0, 0, 0, 0} } }, /* 25: */
193 {{{0, 0, 0, 0} } }, /* 26: */
194 {{{0, 0, 0, 0} } }, /* 27: */
195 {{{0, 0, 0, 0} } }, /* 28: */
196 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
197 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
198 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
199 {{{0} } }, /* 32: PCI */
200 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
201 {1, 0x2110000, 0x2120000, 0x130000},
202 {1, 0x2120000, 0x2122000, 0x124000},
203 {1, 0x2130000, 0x2132000, 0x126000},
204 {1, 0x2140000, 0x2142000, 0x128000},
205 {1, 0x2150000, 0x2152000, 0x12a000},
206 {1, 0x2160000, 0x2170000, 0x110000},
207 {1, 0x2170000, 0x2172000, 0x12e000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000} } },
216 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
222 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
223 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
224 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
225 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
226 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
227 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
228 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
229 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
230 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
231 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
232 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
233 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
235 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
236 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
237 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
238 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
239 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
240 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
241 {{{0} } }, /* 59: I2C0 */
242 {{{0} } }, /* 60: I2C1 */
243 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
244 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
245 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
249 * top 12 bits of crb internal address (hub, agent)
251 static unsigned crb_hub_agt[64] =
254 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
259 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
260 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
265 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
266 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
267 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
269 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
281 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
282 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
284 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
286 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
287 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
293 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
302 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
303 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
304 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
309 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
311 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
315 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
319 /* PCI Windowing for DDR regions. */
321 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
323 #define NETXEN_PCIE_SEM_TIMEOUT 10000
326 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
328 int done = 0, timeout = 0;
331 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
334 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
340 NXWR32(adapter, id_reg, adapter->portnum);
346 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
349 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
352 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
354 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
356 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
362 /* Disable an XG interface */
363 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
366 u32 port = adapter->physical_port;
368 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
371 if (port > NETXEN_NIU_MAX_XG_PORTS)
376 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
381 #define NETXEN_UNICAST_ADDR(port, index) \
382 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
383 #define NETXEN_MCAST_ADDR(port, index) \
384 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
385 #define MAC_HI(addr) \
386 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
387 #define MAC_LO(addr) \
388 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
390 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
393 u32 port = adapter->physical_port;
395 if (port > NETXEN_NIU_MAX_XG_PORTS)
398 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
399 if (mode == NETXEN_NIU_PROMISC_MODE)
400 reg = (reg | 0x2000UL);
402 reg = (reg & ~0x2000UL);
404 if (mode == NETXEN_NIU_ALLMULTI_MODE)
405 reg = (reg | 0x1000UL);
407 reg = (reg & ~0x1000UL);
409 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
414 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
419 u8 phy = adapter->physical_port;
421 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
424 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
425 mac_hi = addr[2] | ((u32)addr[3] << 8) |
426 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
428 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
429 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
431 /* write twice to flush */
432 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
434 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
441 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
444 u16 port = adapter->physical_port;
445 u8 *addr = adapter->netdev->dev_addr;
447 if (adapter->mc_enabled)
450 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
451 val |= (1UL << (28+port));
452 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
454 /* add broadcast addr to filter */
456 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
457 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
459 /* add station addr to filter */
461 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
463 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
465 adapter->mc_enabled = 1;
470 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
473 u16 port = adapter->physical_port;
474 u8 *addr = adapter->netdev->dev_addr;
476 if (!adapter->mc_enabled)
479 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
480 val &= ~(1UL << (28+port));
481 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
484 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
486 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
489 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
491 adapter->mc_enabled = 0;
496 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
500 u16 port = adapter->physical_port;
505 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
506 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
511 void netxen_p2_nic_set_multi(struct net_device *netdev)
513 struct netxen_adapter *adapter = netdev_priv(netdev);
514 struct dev_mc_list *mc_ptr;
518 memset(null_addr, 0, 6);
520 if (netdev->flags & IFF_PROMISC) {
522 adapter->set_promisc(adapter,
523 NETXEN_NIU_PROMISC_MODE);
525 /* Full promiscuous mode */
526 netxen_nic_disable_mcast_filter(adapter);
531 if (netdev->mc_count == 0) {
532 adapter->set_promisc(adapter,
533 NETXEN_NIU_NON_PROMISC_MODE);
534 netxen_nic_disable_mcast_filter(adapter);
538 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
539 if (netdev->flags & IFF_ALLMULTI ||
540 netdev->mc_count > adapter->max_mc_count) {
541 netxen_nic_disable_mcast_filter(adapter);
545 netxen_nic_enable_mcast_filter(adapter);
547 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
548 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
550 if (index != netdev->mc_count)
551 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
552 netxen_nic_driver_name, netdev->name);
554 /* Clear out remaining addresses */
555 for (; index < adapter->max_mc_count; index++)
556 netxen_nic_set_mcast_addr(adapter, index, null_addr);
560 netxen_send_cmd_descs(struct netxen_adapter *adapter,
561 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
563 u32 i, producer, consumer;
564 struct netxen_cmd_buffer *pbuf;
565 struct cmd_desc_type0 *cmd_desc;
566 struct nx_host_tx_ring *tx_ring;
570 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
573 tx_ring = adapter->tx_ring;
574 __netif_tx_lock_bh(tx_ring->txq);
576 producer = tx_ring->producer;
577 consumer = tx_ring->sw_consumer;
579 if (nr_desc >= netxen_tx_avail(tx_ring)) {
580 netif_tx_stop_queue(tx_ring->txq);
581 __netif_tx_unlock_bh(tx_ring->txq);
586 cmd_desc = &cmd_desc_arr[i];
588 pbuf = &tx_ring->cmd_buf_arr[producer];
590 pbuf->frag_count = 0;
592 memcpy(&tx_ring->desc_head[producer],
593 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
595 producer = get_next_index(producer, tx_ring->num_desc);
598 } while (i != nr_desc);
600 tx_ring->producer = producer;
602 netxen_nic_update_cmd_producer(adapter, tx_ring);
604 __netif_tx_unlock_bh(tx_ring->txq);
610 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
613 nx_mac_req_t *mac_req;
616 memset(&req, 0, sizeof(nx_nic_req_t));
617 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
619 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
620 req.req_hdr = cpu_to_le64(word);
622 mac_req = (nx_mac_req_t *)&req.words[0];
624 memcpy(mac_req->mac_addr, addr, 6);
626 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
629 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
630 u8 *addr, struct list_head *del_list)
632 struct list_head *head;
635 /* look up if already exists */
636 list_for_each(head, del_list) {
637 cur = list_entry(head, nx_mac_list_t, list);
639 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
640 list_move_tail(head, &adapter->mac_list);
645 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
647 printk(KERN_ERR "%s: failed to add mac address filter\n",
648 adapter->netdev->name);
651 memcpy(cur->mac_addr, addr, ETH_ALEN);
652 list_add_tail(&cur->list, &adapter->mac_list);
653 return nx_p3_sre_macaddr_change(adapter,
654 cur->mac_addr, NETXEN_MAC_ADD);
657 void netxen_p3_nic_set_multi(struct net_device *netdev)
659 struct netxen_adapter *adapter = netdev_priv(netdev);
660 struct dev_mc_list *mc_ptr;
661 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
662 u32 mode = VPORT_MISS_MODE_DROP;
664 struct list_head *head;
667 list_splice_tail_init(&adapter->mac_list, &del_list);
669 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
670 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
672 if (netdev->flags & IFF_PROMISC) {
673 mode = VPORT_MISS_MODE_ACCEPT_ALL;
677 if ((netdev->flags & IFF_ALLMULTI) ||
678 (netdev->mc_count > adapter->max_mc_count)) {
679 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
683 if (netdev->mc_count > 0) {
684 for (mc_ptr = netdev->mc_list; mc_ptr;
685 mc_ptr = mc_ptr->next) {
686 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
691 adapter->set_promisc(adapter, mode);
693 while (!list_empty(head)) {
694 cur = list_entry(head->next, nx_mac_list_t, list);
696 nx_p3_sre_macaddr_change(adapter,
697 cur->mac_addr, NETXEN_MAC_DEL);
698 list_del(&cur->list);
703 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
708 memset(&req, 0, sizeof(nx_nic_req_t));
710 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
712 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
713 ((u64)adapter->portnum << 16);
714 req.req_hdr = cpu_to_le64(word);
716 req.words[0] = cpu_to_le64(mode);
718 return netxen_send_cmd_descs(adapter,
719 (struct cmd_desc_type0 *)&req, 1);
722 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
725 struct list_head *head = &adapter->mac_list;
727 while (!list_empty(head)) {
728 cur = list_entry(head->next, nx_mac_list_t, list);
729 nx_p3_sre_macaddr_change(adapter,
730 cur->mac_addr, NETXEN_MAC_DEL);
731 list_del(&cur->list);
736 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
738 /* assuming caller has already copied new addr to netdev */
739 netxen_p3_nic_set_multi(adapter->netdev);
743 #define NETXEN_CONFIG_INTR_COALESCE 3
746 * Send the interrupt coalescing parameter set by ethtool to the card.
748 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
754 memset(&req, 0, sizeof(nx_nic_req_t));
756 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
758 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
759 req.req_hdr = cpu_to_le64(word);
761 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
763 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
765 printk(KERN_ERR "ERROR. Could not send "
766 "interrupt coalescing parameters\n");
772 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
778 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
781 memset(&req, 0, sizeof(nx_nic_req_t));
783 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
785 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
786 req.req_hdr = cpu_to_le64(word);
788 req.words[0] = cpu_to_le64(enable);
790 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
792 printk(KERN_ERR "ERROR. Could not send "
793 "configure hw lro request\n");
796 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
801 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
807 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
810 memset(&req, 0, sizeof(nx_nic_req_t));
812 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
814 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
815 ((u64)adapter->portnum << 16);
816 req.req_hdr = cpu_to_le64(word);
818 req.words[0] = cpu_to_le64(enable);
820 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
822 printk(KERN_ERR "ERROR. Could not send "
823 "configure bridge mode request\n");
826 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
832 #define RSS_HASHTYPE_IP_TCP 0x3
834 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
840 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
841 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
842 0x255b0ec26d5a56daULL };
845 memset(&req, 0, sizeof(nx_nic_req_t));
846 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
848 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
849 req.req_hdr = cpu_to_le64(word);
853 * bits 3-0: hash_method
854 * 5-4: hash_type_ipv4
855 * 7-6: hash_type_ipv6
857 * 9: use indirection table
859 * 63-48: indirection table mask
861 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
862 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
863 ((u64)(enable & 0x1) << 8) |
865 req.words[0] = cpu_to_le64(word);
866 for (i = 0; i < 5; i++)
867 req.words[i+1] = cpu_to_le64(key[i]);
870 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
872 printk(KERN_ERR "%s: could not configure RSS\n",
873 adapter->netdev->name);
879 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
885 memset(&req, 0, sizeof(nx_nic_req_t));
886 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
888 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
889 req.req_hdr = cpu_to_le64(word);
891 req.words[0] = cpu_to_le64(cmd);
892 req.words[1] = cpu_to_le64(ip);
894 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
896 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
897 adapter->netdev->name,
898 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
903 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
909 memset(&req, 0, sizeof(nx_nic_req_t));
910 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
912 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
913 req.req_hdr = cpu_to_le64(word);
914 req.words[0] = cpu_to_le64(enable | (enable << 8));
916 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
918 printk(KERN_ERR "%s: could not configure link notification\n",
919 adapter->netdev->name);
925 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
931 memset(&req, 0, sizeof(nx_nic_req_t));
932 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
934 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
935 ((u64)adapter->portnum << 16) |
936 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
938 req.req_hdr = cpu_to_le64(word);
940 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
942 printk(KERN_ERR "%s: could not cleanup lro flows\n",
943 adapter->netdev->name);
949 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
950 * @returns 0 on success, negative on failure
953 #define MTU_FUDGE_FACTOR 100
955 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
957 struct netxen_adapter *adapter = netdev_priv(netdev);
961 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
962 max_mtu = P3_MAX_MTU;
964 max_mtu = P2_MAX_MTU;
967 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
968 netdev->name, max_mtu);
972 if (adapter->set_mtu)
973 rc = adapter->set_mtu(adapter, mtu);
981 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
982 int size, __le32 * buf)
989 for (i = 0; i < size / sizeof(u32); i++) {
990 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
992 *ptr32 = cpu_to_le32(v);
996 if ((char *)buf + size > (char *)ptr32) {
998 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1000 local = cpu_to_le32(v);
1001 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1007 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1009 __le32 *pmac = (__le32 *) mac;
1012 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1014 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1017 if (*mac == cpu_to_le64(~0ULL)) {
1019 offset = NX_OLD_MAC_ADDR_OFFSET +
1020 (adapter->portnum * sizeof(u64));
1022 if (netxen_get_flash_block(adapter,
1023 offset, sizeof(u64), pmac) == -1)
1026 if (*mac == cpu_to_le64(~0ULL))
1032 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1034 uint32_t crbaddr, mac_hi, mac_lo;
1035 int pci_func = adapter->ahw.pci_func;
1037 crbaddr = CRB_MAC_BLOCK_START +
1038 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1040 mac_lo = NXRD32(adapter, crbaddr);
1041 mac_hi = NXRD32(adapter, crbaddr+4);
1044 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1046 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1052 * Changes the CRB window to the specified window.
1055 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1058 void __iomem *offset;
1060 u8 func = adapter->ahw.pci_func;
1062 if (adapter->ahw.crb_win == window)
1065 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1066 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1068 writel(window, offset);
1070 if (window == readl(offset))
1073 if (printk_ratelimit())
1074 dev_warn(&adapter->pdev->dev,
1075 "failed to set CRB window to %d\n",
1076 (window == NETXEN_WINDOW_ONE));
1079 } while (--count > 0);
1082 adapter->ahw.crb_win = window;
1086 * Returns < 0 if off is not valid,
1087 * 1 if window access is needed. 'off' is set to offset from
1088 * CRB space in 128M pci map
1089 * 0 if no window access is needed. 'off' is set to 2M addr
1090 * In: 'off' is offset from base in 128M pci map
1093 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1095 crb_128M_2M_sub_block_map_t *m;
1098 if (*off >= NETXEN_CRB_MAX)
1101 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1102 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1103 (ulong)adapter->ahw.pci_base0;
1107 if (*off < NETXEN_PCI_CRBSPACE)
1110 *off -= NETXEN_PCI_CRBSPACE;
1115 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1117 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1118 *off = *off + m->start_2M - m->start_128M +
1119 (ulong)adapter->ahw.pci_base0;
1124 * Not in direct map, use crb window
1130 * In: 'off' is offset from CRB space in 128M pci map
1131 * Out: 'off' is 2M pci map addr
1132 * side effect: lock crb window
1135 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1138 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1140 window = CRB_HI(*off);
1142 if (adapter->ahw.crb_win == window)
1145 writel(window, addr);
1146 if (readl(addr) != window) {
1147 if (printk_ratelimit())
1148 dev_warn(&adapter->pdev->dev,
1149 "failed to set CRB window to %d off 0x%lx\n",
1152 adapter->ahw.crb_win = window;
1155 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1156 (ulong)adapter->ahw.pci_base0;
1160 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1162 unsigned long flags;
1165 if (ADDR_IN_WINDOW1(off))
1166 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1168 addr = pci_base_offset(adapter, off);
1172 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1173 netxen_nic_io_write_128M(adapter, addr, data);
1174 } else { /* Window 0 */
1175 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1176 addr = pci_base_offset(adapter, off);
1177 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1179 netxen_nic_pci_set_crbwindow_128M(adapter,
1181 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1188 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1190 unsigned long flags;
1194 if (ADDR_IN_WINDOW1(off))
1195 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1197 addr = pci_base_offset(adapter, off);
1201 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1202 data = netxen_nic_io_read_128M(adapter, addr);
1203 } else { /* Window 0 */
1204 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1205 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1207 netxen_nic_pci_set_crbwindow_128M(adapter,
1209 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1216 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1218 unsigned long flags;
1221 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1224 writel(data, (void __iomem *)off);
1229 /* indirect access */
1230 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1231 crb_win_lock(adapter);
1232 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1233 writel(data, (void __iomem *)off);
1234 crb_win_unlock(adapter);
1235 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1239 dev_err(&adapter->pdev->dev,
1240 "%s: invalid offset: 0x%016lx\n", __func__, off);
1246 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1248 unsigned long flags;
1252 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1255 return readl((void __iomem *)off);
1258 /* indirect access */
1259 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1260 crb_win_lock(adapter);
1261 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1262 data = readl((void __iomem *)off);
1263 crb_win_unlock(adapter);
1264 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1268 dev_err(&adapter->pdev->dev,
1269 "%s: invalid offset: 0x%016lx\n", __func__, off);
1274 /* window 1 registers only */
1275 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1276 void __iomem *addr, u32 data)
1278 read_lock(&adapter->ahw.crb_lock);
1280 read_unlock(&adapter->ahw.crb_lock);
1283 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1288 read_lock(&adapter->ahw.crb_lock);
1290 read_unlock(&adapter->ahw.crb_lock);
1295 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1296 void __iomem *addr, u32 data)
1301 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1308 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1312 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1313 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1314 offset > NETXEN_CRB_PCIX_HOST)
1315 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1316 return NETXEN_CRB_NORMALIZE(adapter, offset);
1319 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1320 return (void __iomem *)off;
1324 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1325 u64 addr, u32 *start)
1327 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1328 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1330 } else if (ADDR_IN_RANGE(addr,
1331 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1332 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1340 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1341 u64 addr, u32 *start)
1344 struct pci_dev *pdev = adapter->pdev;
1346 if ((addr & 0x00ff800) == 0xff800) {
1347 if (printk_ratelimit())
1348 dev_warn(&pdev->dev, "QM access not handled\n");
1352 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1353 window = OCM_WIN_P3P(addr);
1355 window = OCM_WIN(addr);
1357 writel(window, adapter->ahw.ocm_win_crb);
1358 /* read back to flush */
1359 readl(adapter->ahw.ocm_win_crb);
1361 adapter->ahw.ocm_win = window;
1362 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1367 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1370 void __iomem *addr, *mem_ptr = NULL;
1371 resource_size_t mem_base;
1375 spin_lock(&adapter->ahw.mem_lock);
1377 ret = adapter->pci_set_window(adapter, off, &start);
1381 addr = pci_base_offset(adapter, start);
1385 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
1387 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1388 if (mem_ptr == NULL) {
1393 addr = mem_ptr + (start & (PAGE_SIZE - 1));
1396 if (op == 0) /* read */
1397 *data = readq(addr);
1399 writeq(*data, addr);
1402 spin_unlock(&adapter->ahw.mem_lock);
1409 #define MAX_CTL_CHECK 1000
1412 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1416 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1417 void __iomem *mem_crb;
1419 /* Only 64-bit aligned access */
1423 /* P2 has different SIU and MIU test agent base addr */
1424 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1425 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1426 mem_crb = pci_base_offset(adapter,
1427 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1428 addr_hi = SIU_TEST_AGT_ADDR_HI;
1429 data_lo = SIU_TEST_AGT_WRDATA_LO;
1430 data_hi = SIU_TEST_AGT_WRDATA_HI;
1431 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1432 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1436 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1437 mem_crb = pci_base_offset(adapter,
1438 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1439 addr_hi = MIU_TEST_AGT_ADDR_HI;
1440 data_lo = MIU_TEST_AGT_WRDATA_LO;
1441 data_hi = MIU_TEST_AGT_WRDATA_HI;
1442 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1447 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1448 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1449 if (adapter->ahw.pci_len0 != 0) {
1450 return netxen_nic_pci_mem_access_direct(adapter,
1458 spin_lock(&adapter->ahw.mem_lock);
1459 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1461 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1462 writel(off_hi, (mem_crb + addr_hi));
1463 writel(data & 0xffffffff, (mem_crb + data_lo));
1464 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1465 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1466 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1467 (mem_crb + TEST_AGT_CTRL));
1469 for (j = 0; j < MAX_CTL_CHECK; j++) {
1470 temp = readl((mem_crb + TEST_AGT_CTRL));
1471 if ((temp & TA_CTL_BUSY) == 0)
1475 if (j >= MAX_CTL_CHECK) {
1476 if (printk_ratelimit())
1477 dev_err(&adapter->pdev->dev,
1478 "failed to write through agent\n");
1483 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1484 spin_unlock(&adapter->ahw.mem_lock);
1489 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1493 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1495 void __iomem *mem_crb;
1497 /* Only 64-bit aligned access */
1501 /* P2 has different SIU and MIU test agent base addr */
1502 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1503 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1504 mem_crb = pci_base_offset(adapter,
1505 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1506 addr_hi = SIU_TEST_AGT_ADDR_HI;
1507 data_lo = SIU_TEST_AGT_RDDATA_LO;
1508 data_hi = SIU_TEST_AGT_RDDATA_HI;
1509 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1510 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1514 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1515 mem_crb = pci_base_offset(adapter,
1516 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1517 addr_hi = MIU_TEST_AGT_ADDR_HI;
1518 data_lo = MIU_TEST_AGT_RDDATA_LO;
1519 data_hi = MIU_TEST_AGT_RDDATA_HI;
1520 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1525 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1526 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1527 if (adapter->ahw.pci_len0 != 0) {
1528 return netxen_nic_pci_mem_access_direct(adapter,
1536 spin_lock(&adapter->ahw.mem_lock);
1537 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1539 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1540 writel(off_hi, (mem_crb + addr_hi));
1541 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1542 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1544 for (j = 0; j < MAX_CTL_CHECK; j++) {
1545 temp = readl(mem_crb + TEST_AGT_CTRL);
1546 if ((temp & TA_CTL_BUSY) == 0)
1550 if (j >= MAX_CTL_CHECK) {
1551 if (printk_ratelimit())
1552 dev_err(&adapter->pdev->dev,
1553 "failed to read through agent\n");
1557 temp = readl(mem_crb + data_hi);
1558 val = ((u64)temp << 32);
1559 val |= readl(mem_crb + data_lo);
1564 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1565 spin_unlock(&adapter->ahw.mem_lock);
1571 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1577 void __iomem *mem_crb;
1579 /* Only 64-bit aligned access */
1583 /* P3 onward, test agent base for MIU and SIU is same */
1584 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1585 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1586 mem_crb = netxen_get_ioaddr(adapter,
1587 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1591 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1592 mem_crb = netxen_get_ioaddr(adapter,
1593 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1597 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1598 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1603 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1605 off8 = off & ~(stride-1);
1607 spin_lock(&adapter->ahw.mem_lock);
1609 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1610 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1614 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1615 writel((TA_CTL_START | TA_CTL_ENABLE),
1616 (mem_crb + TEST_AGT_CTRL));
1618 for (j = 0; j < MAX_CTL_CHECK; j++) {
1619 temp = readl(mem_crb + TEST_AGT_CTRL);
1620 if ((temp & TA_CTL_BUSY) == 0)
1624 if (j >= MAX_CTL_CHECK) {
1629 i = (off & 0xf) ? 0 : 2;
1630 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1631 mem_crb + MIU_TEST_AGT_WRDATA(i));
1632 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1633 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1634 i = (off & 0xf) ? 2 : 0;
1637 writel(data & 0xffffffff,
1638 mem_crb + MIU_TEST_AGT_WRDATA(i));
1639 writel((data >> 32) & 0xffffffff,
1640 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1642 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1643 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1644 (mem_crb + TEST_AGT_CTRL));
1646 for (j = 0; j < MAX_CTL_CHECK; j++) {
1647 temp = readl(mem_crb + TEST_AGT_CTRL);
1648 if ((temp & TA_CTL_BUSY) == 0)
1652 if (j >= MAX_CTL_CHECK) {
1653 if (printk_ratelimit())
1654 dev_err(&adapter->pdev->dev,
1655 "failed to write through agent\n");
1661 spin_unlock(&adapter->ahw.mem_lock);
1667 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1673 void __iomem *mem_crb;
1675 /* Only 64-bit aligned access */
1679 /* P3 onward, test agent base for MIU and SIU is same */
1680 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1681 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1682 mem_crb = netxen_get_ioaddr(adapter,
1683 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1687 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1688 mem_crb = netxen_get_ioaddr(adapter,
1689 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1693 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1694 return netxen_nic_pci_mem_access_direct(adapter,
1701 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1703 off8 = off & ~(stride-1);
1705 spin_lock(&adapter->ahw.mem_lock);
1707 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1708 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1709 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1710 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1712 for (j = 0; j < MAX_CTL_CHECK; j++) {
1713 temp = readl(mem_crb + TEST_AGT_CTRL);
1714 if ((temp & TA_CTL_BUSY) == 0)
1718 if (j >= MAX_CTL_CHECK) {
1719 if (printk_ratelimit())
1720 dev_err(&adapter->pdev->dev,
1721 "failed to read through agent\n");
1724 off8 = MIU_TEST_AGT_RDDATA_LO;
1725 if ((stride == 16) && (off & 0xf))
1726 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1728 temp = readl(mem_crb + off8 + 4);
1729 val = (u64)temp << 32;
1730 val |= readl(mem_crb + off8);
1735 spin_unlock(&adapter->ahw.mem_lock);
1741 netxen_setup_hwops(struct netxen_adapter *adapter)
1743 adapter->init_port = netxen_niu_xg_init_port;
1744 adapter->stop_port = netxen_niu_disable_xg_port;
1746 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1747 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1748 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1749 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1750 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1751 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1752 adapter->io_read = netxen_nic_io_read_128M,
1753 adapter->io_write = netxen_nic_io_write_128M,
1755 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1756 adapter->set_multi = netxen_p2_nic_set_multi;
1757 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1758 adapter->set_promisc = netxen_p2_nic_set_promisc;
1761 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1762 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1763 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1764 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1765 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1766 adapter->io_read = netxen_nic_io_read_2M,
1767 adapter->io_write = netxen_nic_io_write_2M,
1769 adapter->set_mtu = nx_fw_cmd_set_mtu;
1770 adapter->set_promisc = netxen_p3_nic_set_promisc;
1771 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1772 adapter->set_multi = netxen_p3_nic_set_multi;
1774 adapter->phy_read = nx_fw_cmd_query_phy;
1775 adapter->phy_write = nx_fw_cmd_set_phy;
1779 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1781 int offset, board_type, magic, header_version;
1782 struct pci_dev *pdev = adapter->pdev;
1784 offset = NX_FW_MAGIC_OFFSET;
1785 if (netxen_rom_fast_read(adapter, offset, &magic))
1788 offset = NX_HDR_VERSION_OFFSET;
1789 if (netxen_rom_fast_read(adapter, offset, &header_version))
1792 if (magic != NETXEN_BDINFO_MAGIC ||
1793 header_version != NETXEN_BDINFO_VERSION) {
1795 "invalid board config, magic=%08x, version=%08x\n",
1796 magic, header_version);
1800 offset = NX_BRDTYPE_OFFSET;
1801 if (netxen_rom_fast_read(adapter, offset, &board_type))
1804 adapter->ahw.board_type = board_type;
1806 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1807 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1808 if ((gpio & 0x8000) == 0)
1809 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1812 switch (board_type) {
1813 case NETXEN_BRDTYPE_P2_SB35_4G:
1814 adapter->ahw.port_type = NETXEN_NIC_GBE;
1816 case NETXEN_BRDTYPE_P2_SB31_10G:
1817 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1818 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1819 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1820 case NETXEN_BRDTYPE_P3_HMEZ:
1821 case NETXEN_BRDTYPE_P3_XG_LOM:
1822 case NETXEN_BRDTYPE_P3_10G_CX4:
1823 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1824 case NETXEN_BRDTYPE_P3_IMEZ:
1825 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1826 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1827 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1828 case NETXEN_BRDTYPE_P3_10G_XFP:
1829 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1830 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1832 case NETXEN_BRDTYPE_P1_BD:
1833 case NETXEN_BRDTYPE_P1_SB:
1834 case NETXEN_BRDTYPE_P1_SMAX:
1835 case NETXEN_BRDTYPE_P1_SOCK:
1836 case NETXEN_BRDTYPE_P3_REF_QG:
1837 case NETXEN_BRDTYPE_P3_4_GB:
1838 case NETXEN_BRDTYPE_P3_4_GB_MM:
1839 adapter->ahw.port_type = NETXEN_NIC_GBE;
1841 case NETXEN_BRDTYPE_P3_10G_TP:
1842 adapter->ahw.port_type = (adapter->portnum < 2) ?
1843 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1846 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1847 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1854 /* NIU access sections */
1856 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1858 new_mtu += MTU_FUDGE_FACTOR;
1859 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1864 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1866 new_mtu += MTU_FUDGE_FACTOR;
1867 if (adapter->physical_port == 0)
1868 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1870 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1874 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1880 if (!netif_carrier_ok(adapter->netdev)) {
1881 adapter->link_speed = 0;
1882 adapter->link_duplex = -1;
1883 adapter->link_autoneg = AUTONEG_ENABLE;
1887 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1888 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1889 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1890 adapter->link_speed = SPEED_1000;
1891 adapter->link_duplex = DUPLEX_FULL;
1892 adapter->link_autoneg = AUTONEG_DISABLE;
1896 if (adapter->phy_read
1897 && adapter->phy_read(adapter,
1898 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1900 if (netxen_get_phy_link(status)) {
1901 switch (netxen_get_phy_speed(status)) {
1903 adapter->link_speed = SPEED_10;
1906 adapter->link_speed = SPEED_100;
1909 adapter->link_speed = SPEED_1000;
1912 adapter->link_speed = 0;
1915 switch (netxen_get_phy_duplex(status)) {
1917 adapter->link_duplex = DUPLEX_HALF;
1920 adapter->link_duplex = DUPLEX_FULL;
1923 adapter->link_duplex = -1;
1926 if (adapter->phy_read
1927 && adapter->phy_read(adapter,
1928 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1930 adapter->link_autoneg = autoneg;
1935 adapter->link_speed = 0;
1936 adapter->link_duplex = -1;
1942 netxen_nic_wol_supported(struct netxen_adapter *adapter)
1946 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1949 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1950 if (wol_cfg & (1UL << adapter->portnum)) {
1951 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1952 if (wol_cfg & (1 << adapter->portnum))