2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #define DEFINE_GLOBAL_RECV_CRB
37 #include "netxen_nic_phan_reg.h"
42 struct netxen_recv_crb recv_crb_registers[] = {
50 /* crb_rcv_producer_offset: */
51 NETXEN_NIC_REG(0x100),
52 /* crb_rcv_consumer_offset: */
53 NETXEN_NIC_REG(0x104),
54 /* crb_gloablrcv_ring: */
55 NETXEN_NIC_REG(0x108),
56 /* crb_rcv_ring_size */
57 NETXEN_NIC_REG(0x10c),
62 /* crb_rcv_producer_offset: */
63 NETXEN_NIC_REG(0x110),
64 /* crb_rcv_consumer_offset: */
65 NETXEN_NIC_REG(0x114),
66 /* crb_gloablrcv_ring: */
67 NETXEN_NIC_REG(0x118),
68 /* crb_rcv_ring_size */
69 NETXEN_NIC_REG(0x11c),
73 /* crb_rcv_producer_offset: */
74 NETXEN_NIC_REG(0x120),
75 /* crb_rcv_consumer_offset: */
76 NETXEN_NIC_REG(0x124),
77 /* crb_gloablrcv_ring: */
78 NETXEN_NIC_REG(0x128),
79 /* crb_rcv_ring_size */
80 NETXEN_NIC_REG(0x12c),
83 /* crb_rcvstatus_ring: */
84 NETXEN_NIC_REG(0x130),
85 /* crb_rcv_status_producer: */
86 NETXEN_NIC_REG(0x134),
87 /* crb_rcv_status_consumer: */
88 NETXEN_NIC_REG(0x138),
89 /* crb_rcvpeg_state: */
90 NETXEN_NIC_REG(0x13c),
91 /* crb_status_ring_size */
92 NETXEN_NIC_REG(0x140),
102 /* crb_rcv_producer_offset: */
103 NETXEN_NIC_REG(0x144),
104 /* crb_rcv_consumer_offset: */
105 NETXEN_NIC_REG(0x148),
106 /* crb_globalrcv_ring: */
107 NETXEN_NIC_REG(0x14c),
108 /* crb_rcv_ring_size */
109 NETXEN_NIC_REG(0x150),
114 /* crb_rcv_producer_offset: */
115 NETXEN_NIC_REG(0x154),
116 /* crb_rcv_consumer_offset: */
117 NETXEN_NIC_REG(0x158),
118 /* crb_globalrcv_ring: */
119 NETXEN_NIC_REG(0x15c),
120 /* crb_rcv_ring_size */
121 NETXEN_NIC_REG(0x160),
125 /* crb_rcv_producer_offset: */
126 NETXEN_NIC_REG(0x164),
127 /* crb_rcv_consumer_offset: */
128 NETXEN_NIC_REG(0x168),
129 /* crb_globalrcv_ring: */
130 NETXEN_NIC_REG(0x16c),
131 /* crb_rcv_ring_size */
132 NETXEN_NIC_REG(0x170),
136 /* crb_rcvstatus_ring: */
137 NETXEN_NIC_REG(0x174),
138 /* crb_rcv_status_producer: */
139 NETXEN_NIC_REG(0x178),
140 /* crb_rcv_status_consumer: */
141 NETXEN_NIC_REG(0x17c),
142 /* crb_rcvpeg_state: */
143 NETXEN_NIC_REG(0x180),
144 /* crb_status_ring_size */
145 NETXEN_NIC_REG(0x184),
150 u64 ctx_addr_sig_regs[][3] = {
151 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
152 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
153 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
154 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
158 /* PCI Windowing for DDR regions. */
160 #define ADDR_IN_RANGE(addr, low, high) \
161 (((addr) <= (high)) && ((addr) >= (low)))
163 #define NETXEN_FLASH_BASE (BOOTLD_START)
164 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
165 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
166 #define NETXEN_MIN_MTU 64
167 #define NETXEN_ETH_FCS_SIZE 4
168 #define NETXEN_ENET_HEADER_SIZE 14
169 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
170 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
171 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
172 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
174 #define lower32(x) ((u32)((x) & 0xffffffff))
176 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
178 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
179 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
180 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
181 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
183 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
185 unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
186 unsigned long long addr);
187 void netxen_free_hw_resources(struct netxen_adapter *adapter);
189 int netxen_nic_set_mac(struct net_device *netdev, void *p)
191 struct netxen_adapter *adapter = netdev_priv(netdev);
192 struct sockaddr *addr = p;
194 if (netif_running(netdev))
197 if (!is_valid_ether_addr(addr->sa_data))
198 return -EADDRNOTAVAIL;
200 DPRINTK(INFO, "valid ether addr\n");
201 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
203 if (adapter->macaddr_set)
204 adapter->macaddr_set(adapter, addr->sa_data);
210 * netxen_nic_set_multi - Multicast
212 void netxen_nic_set_multi(struct net_device *netdev)
214 struct netxen_adapter *adapter = netdev_priv(netdev);
215 struct dev_mc_list *mc_ptr;
216 __u32 netxen_mac_addr_cntl_data = 0;
218 mc_ptr = netdev->mc_list;
219 if (netdev->flags & IFF_PROMISC) {
220 if (adapter->set_promisc)
221 adapter->set_promisc(adapter,
222 NETXEN_NIU_PROMISC_MODE);
224 if (adapter->unset_promisc &&
225 adapter->ahw.boardcfg.board_type
226 != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
227 adapter->unset_promisc(adapter,
228 NETXEN_NIU_NON_PROMISC_MODE);
230 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
231 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
232 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
233 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
234 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
235 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
236 netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
237 netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
238 netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
239 netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
241 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
242 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
243 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
244 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
245 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
247 writel(netxen_mac_addr_cntl_data,
248 NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
249 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
250 writel(netxen_mac_addr_cntl_data,
251 NETXEN_CRB_NORMALIZE(adapter,
252 NETXEN_MULTICAST_ADDR_HI_0));
254 writel(netxen_mac_addr_cntl_data,
255 NETXEN_CRB_NORMALIZE(adapter,
256 NETXEN_MULTICAST_ADDR_HI_1));
258 netxen_mac_addr_cntl_data = 0;
259 writel(netxen_mac_addr_cntl_data,
260 NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
264 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
265 * @returns 0 on success, negative on failure
267 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
269 struct netxen_adapter *adapter = netdev_priv(netdev);
270 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
272 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
273 printk(KERN_ERR "%s: %s %d is not supported.\n",
274 netxen_nic_driver_name, netdev->name, mtu);
278 if (adapter->set_mtu)
279 adapter->set_mtu(adapter, mtu);
286 * check if the firmware has been downloaded and ready to run and
287 * setup the address for the descriptors in the adapter
289 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
291 struct netxen_hardware_context *hw = &adapter->ahw;
294 int loops = 0, err = 0;
296 u32 card_cmdring = 0;
297 struct netxen_recv_context *recv_ctx;
298 struct netxen_rcv_desc_ctx *rcv_desc;
300 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
301 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
302 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
303 pci_base_offset(adapter, NETXEN_CRB_CAM));
304 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
305 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
308 card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
310 DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
313 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
314 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
318 state = readl(NETXEN_CRB_NORMALIZE(adapter,
319 recv_crb_registers[ctx].
321 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
324 state = readl(NETXEN_CRB_NORMALIZE(adapter,
331 printk(KERN_ERR "Rcv Peg initialization not complete:"
337 DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
339 addr = netxen_alloc(adapter->ahw.pdev,
340 sizeof(struct netxen_ring_ctx) +
342 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
343 &adapter->ctx_desc_pdev);
345 printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
346 (unsigned long long) adapter->ctx_desc_phys_addr);
348 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
352 memset(addr, 0, sizeof(struct netxen_ring_ctx));
353 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
354 adapter->ctx_desc->cmd_consumer_offset =
355 cpu_to_le64(adapter->ctx_desc_phys_addr +
356 sizeof(struct netxen_ring_ctx));
357 adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
358 sizeof(struct netxen_ring_ctx));
360 addr = netxen_alloc(adapter->ahw.pdev,
361 sizeof(struct cmd_desc_type0) *
362 adapter->max_tx_desc_count,
363 (dma_addr_t *) & hw->cmd_desc_phys_addr,
364 &adapter->ahw.cmd_desc_pdev);
365 printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
366 (unsigned long long) hw->cmd_desc_phys_addr);
369 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
370 netxen_free_hw_resources(adapter);
374 adapter->ctx_desc->cmd_ring_addr =
375 cpu_to_le64(hw->cmd_desc_phys_addr);
376 adapter->ctx_desc->cmd_ring_size =
377 cpu_to_le32(adapter->max_tx_desc_count);
379 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
381 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
382 recv_ctx = &adapter->recv_ctx[ctx];
384 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
385 rcv_desc = &recv_ctx->rcv_desc[ring];
386 addr = netxen_alloc(adapter->ahw.pdev,
388 &rcv_desc->phys_addr,
389 &rcv_desc->phys_pdev);
391 DPRINTK(ERR, "bad return from "
392 "pci_alloc_consistent\n");
393 netxen_free_hw_resources(adapter);
397 rcv_desc->desc_head = (struct rcv_desc *)addr;
398 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
399 cpu_to_le64(rcv_desc->phys_addr);
400 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
401 cpu_to_le32(rcv_desc->max_rx_desc_count);
404 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
405 &recv_ctx->rcv_status_desc_phys_addr,
406 &recv_ctx->rcv_status_desc_pdev);
408 DPRINTK(ERR, "bad return from"
409 " pci_alloc_consistent\n");
410 netxen_free_hw_resources(adapter);
414 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
415 adapter->ctx_desc->sts_ring_addr =
416 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
417 adapter->ctx_desc->sts_ring_size =
418 cpu_to_le32(adapter->max_rx_desc_count);
423 writel(lower32(adapter->ctx_desc_phys_addr),
424 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO));
425 writel(upper32(adapter->ctx_desc_phys_addr),
426 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI));
427 writel(NETXEN_CTX_SIGNATURE,
428 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG));
432 void netxen_free_hw_resources(struct netxen_adapter *adapter)
434 struct netxen_recv_context *recv_ctx;
435 struct netxen_rcv_desc_ctx *rcv_desc;
438 if (adapter->ctx_desc != NULL) {
439 pci_free_consistent(adapter->ctx_desc_pdev,
440 sizeof(struct netxen_ring_ctx) +
443 adapter->ctx_desc_phys_addr);
444 adapter->ctx_desc = NULL;
447 if (adapter->ahw.cmd_desc_head != NULL) {
448 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
449 sizeof(struct cmd_desc_type0) *
450 adapter->max_tx_desc_count,
451 adapter->ahw.cmd_desc_head,
452 adapter->ahw.cmd_desc_phys_addr);
453 adapter->ahw.cmd_desc_head = NULL;
455 /* Special handling: there are 2 ports on this board */
456 if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
457 adapter->ahw.max_ports = 2;
460 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
461 recv_ctx = &adapter->recv_ctx[ctx];
462 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
463 rcv_desc = &recv_ctx->rcv_desc[ring];
465 if (rcv_desc->desc_head != NULL) {
466 pci_free_consistent(rcv_desc->phys_pdev,
469 rcv_desc->phys_addr);
470 rcv_desc->desc_head = NULL;
474 if (recv_ctx->rcv_status_desc_head != NULL) {
475 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
476 STATUS_DESC_RINGSIZE,
477 recv_ctx->rcv_status_desc_head,
479 rcv_status_desc_phys_addr);
480 recv_ctx->rcv_status_desc_head = NULL;
485 void netxen_tso_check(struct netxen_adapter *adapter,
486 struct cmd_desc_type0 *desc, struct sk_buff *skb)
489 desc->total_hdr_length = (sizeof(struct ethhdr) +
490 ip_hdrlen(skb) + tcp_hdrlen(skb));
491 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
492 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
493 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
494 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
495 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
496 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
501 desc->tcp_hdr_offset = skb_transport_offset(skb);
502 desc->ip_hdr_offset = skb_network_offset(skb);
505 int netxen_is_flash_supported(struct netxen_adapter *adapter)
507 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
508 int addr, val01, val02, i, j;
510 /* if the flash size less than 4Mb, make huge war cry and die */
511 for (j = 1; j < 4; j++) {
512 addr = j * NETXEN_NIC_WINDOW_MARGIN;
513 for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
514 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
515 && netxen_rom_fast_read(adapter, (addr + locs[i]),
527 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
535 for (i = 0; i < size / sizeof(u32); i++) {
536 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
538 *ptr32 = cpu_to_le32(*ptr32);
542 if ((char *)buf + size > (char *)ptr32) {
545 if (netxen_rom_fast_read(adapter, addr, &local) == -1)
547 local = cpu_to_le32(local);
548 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
554 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
556 u32 *pmac = (u32 *) & mac[0];
558 if (netxen_get_flash_block(adapter,
560 offsetof(struct netxen_new_user_info,
562 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
566 if (netxen_get_flash_block(adapter,
568 offsetof(struct netxen_user_old_info,
570 FLASH_NUM_PORTS * sizeof(u64),
580 * Changes the CRB window to the specified window.
582 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
584 void __iomem *offset;
588 if (adapter->curr_window == wndw)
590 switch(adapter->ahw.pci_func) {
592 offset = PCI_OFFSET_SECOND_RANGE(adapter,
593 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
596 offset = PCI_OFFSET_SECOND_RANGE(adapter,
597 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
600 offset = PCI_OFFSET_SECOND_RANGE(adapter,
601 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
604 offset = PCI_OFFSET_SECOND_RANGE(adapter,
605 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
608 printk(KERN_INFO "Changing the window for PCI function"
609 "%d\n", adapter->ahw.pci_func);
610 offset = PCI_OFFSET_SECOND_RANGE(adapter,
611 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
615 * Move the CRB window.
616 * We need to write to the "direct access" region of PCI
617 * to avoid a race condition where the window register has
618 * not been successfully written across CRB before the target
619 * register address is received by PCI. The direct region bypasses
624 wndw = NETXEN_WINDOW_ONE;
626 writel(wndw, offset);
628 /* MUST make sure window is set before we forge on... */
629 while ((tmp = readl(offset)) != wndw) {
630 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
631 "registered properly: 0x%08x.\n",
632 netxen_nic_driver_name, __FUNCTION__, tmp);
639 adapter->curr_window = wndw;
642 void netxen_load_firmware(struct netxen_adapter *adapter)
646 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
650 size = NETXEN_FIRMWARE_LEN;
651 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
653 for (i = 0; i < size; i++) {
654 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
656 "Error in netxen_rom_fast_read(). Will skip"
657 "loading flash image\n");
660 off = netxen_nic_pci_set_window(adapter, memaddr);
661 addr = pci_base_offset(adapter, off);
667 /* make sure Casper is powered on */
669 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
670 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
676 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
681 if (ADDR_IN_WINDOW1(off)) {
682 addr = NETXEN_CRB_NORMALIZE(adapter, off);
683 } else { /* Window 0 */
684 addr = pci_base_offset(adapter, off);
685 netxen_nic_pci_change_crbwindow(adapter, 0);
688 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
689 " data %llx len %d\n",
690 pci_base(adapter, off), off, addr,
691 *(unsigned long long *)data, len);
693 netxen_nic_pci_change_crbwindow(adapter, 1);
699 writeb(*(u8 *) data, addr);
702 writew(*(u16 *) data, addr);
705 writel(*(u32 *) data, addr);
708 writeq(*(u64 *) data, addr);
712 "writing data %lx to offset %llx, num words=%d\n",
713 *(unsigned long *)data, off, (len >> 3));
715 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
719 if (!ADDR_IN_WINDOW1(off))
720 netxen_nic_pci_change_crbwindow(adapter, 1);
726 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
731 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
732 addr = NETXEN_CRB_NORMALIZE(adapter, off);
733 } else { /* Window 0 */
734 addr = pci_base_offset(adapter, off);
735 netxen_nic_pci_change_crbwindow(adapter, 0);
738 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
739 pci_base(adapter, off), off, addr);
741 netxen_nic_pci_change_crbwindow(adapter, 1);
746 *(u8 *) data = readb(addr);
749 *(u16 *) data = readw(addr);
752 *(u32 *) data = readl(addr);
755 *(u64 *) data = readq(addr);
758 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
762 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
764 if (!ADDR_IN_WINDOW1(off))
765 netxen_nic_pci_change_crbwindow(adapter, 1);
770 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
771 { /* Only for window 1 */
774 addr = NETXEN_CRB_NORMALIZE(adapter, off);
775 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
776 pci_base(adapter, off), off, addr, val);
781 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
782 { /* Only for window 1 */
786 addr = NETXEN_CRB_NORMALIZE(adapter, off);
787 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
788 pci_base(adapter, off), off, addr);
795 /* Change the window to 0, write and change back to window 1. */
796 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
800 netxen_nic_pci_change_crbwindow(adapter, 0);
801 addr = pci_base_offset(adapter, index);
803 netxen_nic_pci_change_crbwindow(adapter, 1);
806 /* Change the window to 0, read and change back to window 1. */
807 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
811 addr = pci_base_offset(adapter, index);
813 netxen_nic_pci_change_crbwindow(adapter, 0);
814 *value = readl(addr);
815 netxen_nic_pci_change_crbwindow(adapter, 1);
818 int netxen_pci_set_window_warning_count = 0;
821 netxen_nic_pci_set_window(struct netxen_adapter *adapter,
822 unsigned long long addr)
824 static int ddr_mn_window = -1;
825 static int qdr_sn_window = -1;
828 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
829 /* DDR network side */
830 addr -= NETXEN_ADDR_DDR_NET;
831 window = (addr >> 25) & 0x3ff;
832 if (ddr_mn_window != window) {
833 ddr_mn_window = window;
834 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
837 /* MUST make sure window is set before we forge on... */
838 readl(PCI_OFFSET_SECOND_RANGE(adapter,
842 addr -= (window * NETXEN_WINDOW_ONE);
843 addr += NETXEN_PCI_DDR_NET;
844 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
845 addr -= NETXEN_ADDR_OCM0;
846 addr += NETXEN_PCI_OCM0;
847 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
848 addr -= NETXEN_ADDR_OCM1;
849 addr += NETXEN_PCI_OCM1;
852 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
853 /* QDR network side */
854 addr -= NETXEN_ADDR_QDR_NET;
855 window = (addr >> 22) & 0x3f;
856 if (qdr_sn_window != window) {
857 qdr_sn_window = window;
858 writel((window << 22),
859 PCI_OFFSET_SECOND_RANGE(adapter,
862 /* MUST make sure window is set before we forge on... */
863 readl(PCI_OFFSET_SECOND_RANGE(adapter,
867 addr -= (window * 0x400000);
868 addr += NETXEN_PCI_QDR_NET;
871 * peg gdb frequently accesses memory that doesn't exist,
872 * this limits the chit chat so debugging isn't slowed down.
874 if ((netxen_pci_set_window_warning_count++ < 8)
875 || (netxen_pci_set_window_warning_count % 64 == 0))
876 printk("%s: Warning:netxen_nic_pci_set_window()"
877 " Unknown address range!\n",
878 netxen_nic_driver_name);
885 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
887 if (netxen_rom_fast_write(adapter, PXE_START, 0) == -1) {
888 printk(KERN_ERR "%s: erase pxe failed\n",
889 netxen_nic_driver_name);
895 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
898 int addr = BRDCFG_START;
899 struct netxen_board_info *boardinfo;
903 boardinfo = &adapter->ahw.boardcfg;
904 ptr32 = (u32 *) boardinfo;
906 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
908 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
914 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
915 printk("%s: ERROR reading %s board config."
916 " Read %x, expected %x\n", netxen_nic_driver_name,
917 netxen_nic_driver_name,
918 boardinfo->magic, NETXEN_BDINFO_MAGIC);
921 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
922 printk("%s: Unknown board config version."
923 " Read %x, expected %x\n", netxen_nic_driver_name,
924 boardinfo->header_version, NETXEN_BDINFO_VERSION);
928 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
929 switch ((netxen_brdtype_t) boardinfo->board_type) {
930 case NETXEN_BRDTYPE_P2_SB35_4G:
931 adapter->ahw.board_type = NETXEN_NIC_GBE;
933 case NETXEN_BRDTYPE_P2_SB31_10G:
934 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
935 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
936 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
937 adapter->ahw.board_type = NETXEN_NIC_XGBE;
939 case NETXEN_BRDTYPE_P1_BD:
940 case NETXEN_BRDTYPE_P1_SB:
941 case NETXEN_BRDTYPE_P1_SMAX:
942 case NETXEN_BRDTYPE_P1_SOCK:
943 adapter->ahw.board_type = NETXEN_NIC_GBE;
946 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
947 boardinfo->board_type);
954 /* NIU access sections */
956 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
958 netxen_nic_write_w0(adapter,
959 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->portnum),
964 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
966 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
967 if (adapter->portnum == 0)
968 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
969 else if (adapter->portnum == 1)
970 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
974 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
976 netxen_niu_gbe_init_port(adapter, adapter->portnum);
980 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
985 if (ADDR_IN_WINDOW1(off)) {
986 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
988 netxen_nic_pci_change_crbwindow(adapter, 0);
989 addr = pci_base_offset(adapter, off);
991 netxen_nic_pci_change_crbwindow(adapter, 1);
995 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1001 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1002 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1003 if (adapter->phy_read
1006 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1008 if (netxen_get_phy_link(status)) {
1009 switch (netxen_get_phy_speed(status)) {
1011 adapter->link_speed = SPEED_10;
1014 adapter->link_speed = SPEED_100;
1017 adapter->link_speed = SPEED_1000;
1020 adapter->link_speed = -1;
1023 switch (netxen_get_phy_duplex(status)) {
1025 adapter->link_duplex = DUPLEX_HALF;
1028 adapter->link_duplex = DUPLEX_FULL;
1031 adapter->link_duplex = -1;
1034 if (adapter->phy_read
1037 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1039 adapter->link_autoneg = autoneg;
1044 adapter->link_speed = -1;
1045 adapter->link_duplex = -1;
1050 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1056 char brd_name[NETXEN_MAX_SHORT_NAME];
1057 struct netxen_new_user_info user_info;
1058 int i, addr = USER_START;
1061 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1062 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
1064 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
1065 board_info->magic, NETXEN_BDINFO_MAGIC);
1068 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
1069 printk("NetXen Unknown board config version."
1070 " Read %x, expected %x\n",
1071 board_info->header_version, NETXEN_BDINFO_VERSION);
1075 ptr32 = (u32 *) & user_info;
1077 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
1079 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1080 printk("%s: ERROR reading %s board userarea.\n",
1081 netxen_nic_driver_name,
1082 netxen_nic_driver_name);
1085 *ptr32 = le32_to_cpu(*ptr32);
1087 addr += sizeof(u32);
1089 get_brd_name_by_type(board_info->board_type, brd_name);
1091 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1092 brd_name, user_info.serial_num, board_info->chip_id);
1094 printk("NetXen %s Board #%d, Chip id 0x%x\n",
1095 board_info->board_type == 0x0b ? "XGB" : "GBE",
1096 board_info->board_num, board_info->chip_id);
1097 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1098 NETXEN_FW_VERSION_MAJOR));
1099 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1100 NETXEN_FW_VERSION_MINOR));
1102 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1104 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
1107 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1108 printk(KERN_ERR "The mismatch in driver version and firmware "
1109 "version major number\n"
1110 "Driver version major number = %d \t"
1111 "Firmware version major number = %d \n",
1112 _NETXEN_NIC_LINUX_MAJOR, fw_major);
1113 adapter->driver_mismatch = 1;
1115 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1116 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1117 printk(KERN_ERR "The mismatch in driver version and firmware "
1118 "version minor number\n"
1119 "Driver version minor number = %d \t"
1120 "Firmware version minor number = %d \n",
1121 _NETXEN_NIC_LINUX_MINOR, fw_minor);
1122 adapter->driver_mismatch = 1;
1124 if (adapter->driver_mismatch)
1125 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
1126 fw_major, fw_minor);