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   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2009 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #include <linux/tcp.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/skbuff.h>
  44 #include <linux/string.h>
  45 #include <linux/module.h>
  46 #include <linux/pci.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/if_ether.h>
  50 #include <linux/if_vlan.h>
  51 #include <linux/inet_lro.h>
  52 #include <linux/dca.h>
  53 #include <linux/ip.h>
  54 #include <linux/inet.h>
  55 #include <linux/in.h>
  56 #include <linux/ethtool.h>
  57 #include <linux/firmware.h>
  58 #include <linux/delay.h>
  59 #include <linux/timer.h>
  60 #include <linux/vmalloc.h>
  61 #include <linux/crc32.h>
  62 #include <linux/moduleparam.h>
  63 #include <linux/io.h>
  64 #include <linux/log2.h>
  65 #include <net/checksum.h>
  66 #include <net/ip.h>
  67 #include <net/tcp.h>
  68 #include <asm/byteorder.h>
  69 #include <asm/io.h>
  70 #include <asm/processor.h>
  71 #ifdef CONFIG_MTRR
  72 #include <asm/mtrr.h>
  73 #endif
  74
  75 #include "myri10ge_mcp.h"
  76 #include "myri10ge_mcp_gen_header.h"
  77
  78 #define MYRI10GE_VERSION_STR "1.4.4-1.401"
  79
  80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  81 MODULE_AUTHOR("Maintainer: help@myri.com");
  82 MODULE_VERSION(MYRI10GE_VERSION_STR);
  83 MODULE_LICENSE("Dual BSD/GPL");
  84
  85 #define MYRI10GE_MAX_ETHER_MTU 9014
  86
  87 #define MYRI10GE_ETH_STOPPED 0
  88 #define MYRI10GE_ETH_STOPPING 1
  89 #define MYRI10GE_ETH_STARTING 2
  90 #define MYRI10GE_ETH_RUNNING 3
  91 #define MYRI10GE_ETH_OPEN_FAILED 4
  92
  93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
  96 #define MYRI10GE_LRO_MAX_PKTS 64
  97
  98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
  99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 100
 101 #define MYRI10GE_ALLOC_ORDER 0
 102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 104
 105 #define MYRI10GE_MAX_SLICES 32
 106
 107 struct myri10ge_rx_buffer_state {
 108         struct page *page;
 109         int page_offset;
 110          DECLARE_PCI_UNMAP_ADDR(bus)
 111          DECLARE_PCI_UNMAP_LEN(len)
 112 };
 113
 114 struct myri10ge_tx_buffer_state {
 115         struct sk_buff *skb;
 116         int last;
 117          DECLARE_PCI_UNMAP_ADDR(bus)
 118          DECLARE_PCI_UNMAP_LEN(len)
 119 };
 120
 121 struct myri10ge_cmd {
 122         u32 data0;
 123         u32 data1;
 124         u32 data2;
 125 };
 126
 127 struct myri10ge_rx_buf {
 128         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 129         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 130         struct myri10ge_rx_buffer_state *info;
 131         struct page *page;
 132         dma_addr_t bus;
 133         int page_offset;
 134         int cnt;
 135         int fill_cnt;
 136         int alloc_fail;
 137         int mask;               /* number of rx slots -1 */
 138         int watchdog_needed;
 139 };
 140
 141 struct myri10ge_tx_buf {
 142         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 143         __be32 __iomem *send_go;        /* "go" doorbell ptr */
 144         __be32 __iomem *send_stop;      /* "stop" doorbell ptr */
 145         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 146         char *req_bytes;
 147         struct myri10ge_tx_buffer_state *info;
 148         int mask;               /* number of transmit slots -1  */
 149         int req ____cacheline_aligned;  /* transmit slots submitted     */
 150         int pkt_start;          /* packets started */
 151         int stop_queue;
 152         int linearized;
 153         int done ____cacheline_aligned; /* transmit slots completed     */
 154         int pkt_done;           /* packets completed */
 155         int wake_queue;
 156         int queue_active;
 157 };
 158
 159 struct myri10ge_rx_done {
 160         struct mcp_slot *entry;
 161         dma_addr_t bus;
 162         int cnt;
 163         int idx;
 164         struct net_lro_mgr lro_mgr;
 165         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 166 };
 167
 168 struct myri10ge_slice_netstats {
 169         unsigned long rx_packets;
 170         unsigned long tx_packets;
 171         unsigned long rx_bytes;
 172         unsigned long tx_bytes;
 173         unsigned long rx_dropped;
 174         unsigned long tx_dropped;
 175 };
 176
 177 struct myri10ge_slice_state {
 178         struct myri10ge_tx_buf tx;      /* transmit ring        */
 179         struct myri10ge_rx_buf rx_small;
 180         struct myri10ge_rx_buf rx_big;
 181         struct myri10ge_rx_done rx_done;
 182         struct net_device *dev;
 183         struct napi_struct napi;
 184         struct myri10ge_priv *mgp;
 185         struct myri10ge_slice_netstats stats;
 186         __be32 __iomem *irq_claim;
 187         struct mcp_irq_data *fw_stats;
 188         dma_addr_t fw_stats_bus;
 189         int watchdog_tx_done;
 190         int watchdog_tx_req;
 191 #ifdef CONFIG_MYRI10GE_DCA
 192         int cached_dca_tag;
 193         int cpu;
 194         __be32 __iomem *dca_tag;
 195 #endif
 196         char irq_desc[32];
 197 };
 198
 199 struct myri10ge_priv {
 200         struct myri10ge_slice_state *ss;
 201         int tx_boundary;        /* boundary transmits cannot cross */
 202         int num_slices;
 203         int running;            /* running?             */
 204         int csum_flag;          /* rx_csums?            */
 205         int small_bytes;
 206         int big_bytes;
 207         int max_intr_slots;
 208         struct net_device *dev;
 209         struct net_device_stats stats;
 210         spinlock_t stats_lock;
 211         u8 __iomem *sram;
 212         int sram_size;
 213         unsigned long board_span;
 214         unsigned long iomem_base;
 215         __be32 __iomem *irq_deassert;
 216         char *mac_addr_string;
 217         struct mcp_cmd_response *cmd;
 218         dma_addr_t cmd_bus;
 219         struct pci_dev *pdev;
 220         int msi_enabled;
 221         int msix_enabled;
 222         struct msix_entry *msix_vectors;
 223 #ifdef CONFIG_MYRI10GE_DCA
 224         int dca_enabled;
 225 #endif
 226         u32 link_state;
 227         unsigned int rdma_tags_available;
 228         int intr_coal_delay;
 229         __be32 __iomem *intr_coal_delay_ptr;
 230         int mtrr;
 231         int wc_enabled;
 232         int down_cnt;
 233         wait_queue_head_t down_wq;
 234         struct work_struct watchdog_work;
 235         struct timer_list watchdog_timer;
 236         int watchdog_resets;
 237         int watchdog_pause;
 238         int pause;
 239         char *fw_name;
 240         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 241         char *product_code_string;
 242         char fw_version[128];
 243         int fw_ver_major;
 244         int fw_ver_minor;
 245         int fw_ver_tiny;
 246         int adopted_rx_filter_bug;
 247         u8 mac_addr[6];         /* eeprom mac address */
 248         unsigned long serial_number;
 249         int vendor_specific_offset;
 250         int fw_multicast_support;
 251         unsigned long features;
 252         u32 max_tso6;
 253         u32 read_dma;
 254         u32 write_dma;
 255         u32 read_write_dma;
 256         u32 link_changes;
 257         u32 msg_enable;
 258 };
 259
 260 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 261 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 262 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 263 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 264
 265 static char *myri10ge_fw_name = NULL;
 266 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 267 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 268
 269 static int myri10ge_ecrc_enable = 1;
 270 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 271 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 272
 273 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 274 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 275 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 276
 277 static int myri10ge_msi = 1;    /* enable msi by default */
 278 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 279 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 280
 281 static int myri10ge_intr_coal_delay = 75;
 282 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 283 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 284
 285 static int myri10ge_flow_control = 1;
 286 module_param(myri10ge_flow_control, int, S_IRUGO);
 287 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 288
 289 static int myri10ge_deassert_wait = 1;
 290 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 291 MODULE_PARM_DESC(myri10ge_deassert_wait,
 292                  "Wait when deasserting legacy interrupts");
 293
 294 static int myri10ge_force_firmware = 0;
 295 module_param(myri10ge_force_firmware, int, S_IRUGO);
 296 MODULE_PARM_DESC(myri10ge_force_firmware,
 297                  "Force firmware to assume aligned completions");
 298
 299 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 300 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 301 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 302
 303 static int myri10ge_napi_weight = 64;
 304 module_param(myri10ge_napi_weight, int, S_IRUGO);
 305 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 306
 307 static int myri10ge_watchdog_timeout = 1;
 308 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 309 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 310
 311 static int myri10ge_max_irq_loops = 1048576;
 312 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 313 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 314                  "Set stuck legacy IRQ detection threshold");
 315
 316 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 317
 318 static int myri10ge_debug = -1; /* defaults above */
 319 module_param(myri10ge_debug, int, 0);
 320 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 321
 322 static int myri10ge_lro = 1;
 323 module_param(myri10ge_lro, int, S_IRUGO);
 324 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
 325
 326 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 327 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 328 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 329                  "Number of LRO packets to be aggregated");
 330
 331 static int myri10ge_fill_thresh = 256;
 332 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 333 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 334
 335 static int myri10ge_reset_recover = 1;
 336
 337 static int myri10ge_max_slices = 1;
 338 module_param(myri10ge_max_slices, int, S_IRUGO);
 339 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 340
 341 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
 342 module_param(myri10ge_rss_hash, int, S_IRUGO);
 343 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 344
 345 static int myri10ge_dca = 1;
 346 module_param(myri10ge_dca, int, S_IRUGO);
 347 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 348
 349 #define MYRI10GE_FW_OFFSET 1024*1024
 350 #define MYRI10GE_HIGHPART_TO_U32(X) \
 351 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 352 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 353
 354 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 355
 356 static void myri10ge_set_multicast_list(struct net_device *dev);
 357 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
 358
 359 static inline void put_be32(__be32 val, __be32 __iomem * p)
 360 {
 361         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 362 }
 363
 364 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
 365
 366 static int
 367 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 368                   struct myri10ge_cmd *data, int atomic)
 369 {
 370         struct mcp_cmd *buf;
 371         char buf_bytes[sizeof(*buf) + 8];
 372         struct mcp_cmd_response *response = mgp->cmd;
 373         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 374         u32 dma_low, dma_high, result, value;
 375         int sleep_total = 0;
 376
 377         /* ensure buf is aligned to 8 bytes */
 378         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 379
 380         buf->data0 = htonl(data->data0);
 381         buf->data1 = htonl(data->data1);
 382         buf->data2 = htonl(data->data2);
 383         buf->cmd = htonl(cmd);
 384         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 385         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 386
 387         buf->response_addr.low = htonl(dma_low);
 388         buf->response_addr.high = htonl(dma_high);
 389         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 390         mb();
 391         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 392
 393         /* wait up to 15ms. Longest command is the DMA benchmark,
 394          * which is capped at 5ms, but runs from a timeout handler
 395          * that runs every 7.8ms. So a 15ms timeout leaves us with
 396          * a 2.2ms margin
 397          */
 398         if (atomic) {
 399                 /* if atomic is set, do not sleep,
 400                  * and try to get the completion quickly
 401                  * (1ms will be enough for those commands) */
 402                 for (sleep_total = 0;
 403                      sleep_total < 1000
 404                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 405                      sleep_total += 10) {
 406                         udelay(10);
 407                         mb();
 408                 }
 409         } else {
 410                 /* use msleep for most command */
 411                 for (sleep_total = 0;
 412                      sleep_total < 15
 413                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 414                      sleep_total++)
 415                         msleep(1);
 416         }
 417
 418         result = ntohl(response->result);
 419         value = ntohl(response->data);
 420         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 421                 if (result == 0) {
 422                         data->data0 = value;
 423                         return 0;
 424                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 425                         return -ENOSYS;
 426                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 427                         return -E2BIG;
 428                 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
 429                            cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
 430                            (data->
 431                             data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
 432                            0) {
 433                         return -ERANGE;
 434                 } else {
 435                         dev_err(&mgp->pdev->dev,
 436                                 "command %d failed, result = %d\n",
 437                                 cmd, result);
 438                         return -ENXIO;
 439                 }
 440         }
 441
 442         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 443                 cmd, result);
 444         return -EAGAIN;
 445 }
 446
 447 /*
 448  * The eeprom strings on the lanaiX have the format
 449  * SN=x\0
 450  * MAC=x:x:x:x:x:x\0
 451  * PT:ddd mmm xx xx:xx:xx xx\0
 452  * PV:ddd mmm xx xx:xx:xx xx\0
 453  */
 454 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 455 {
 456         char *ptr, *limit;
 457         int i;
 458
 459         ptr = mgp->eeprom_strings;
 460         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 461
 462         while (*ptr != '\0' && ptr < limit) {
 463                 if (memcmp(ptr, "MAC=", 4) == 0) {
 464                         ptr += 4;
 465                         mgp->mac_addr_string = ptr;
 466                         for (i = 0; i < 6; i++) {
 467                                 if ((ptr + 2) > limit)
 468                                         goto abort;
 469                                 mgp->mac_addr[i] =
 470                                     simple_strtoul(ptr, &ptr, 16);
 471                                 ptr += 1;
 472                         }
 473                 }
 474                 if (memcmp(ptr, "PC=", 3) == 0) {
 475                         ptr += 3;
 476                         mgp->product_code_string = ptr;
 477                 }
 478                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 479                         ptr += 3;
 480                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 481                 }
 482                 while (ptr < limit && *ptr++) ;
 483         }
 484
 485         return 0;
 486
 487 abort:
 488         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 489         return -ENXIO;
 490 }
 491
 492 /*
 493  * Enable or disable periodic RDMAs from the host to make certain
 494  * chipsets resend dropped PCIe messages
 495  */
 496
 497 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 498 {
 499         char __iomem *submit;
 500         __be32 buf[16] __attribute__ ((__aligned__(8)));
 501         u32 dma_low, dma_high;
 502         int i;
 503
 504         /* clear confirmation addr */
 505         mgp->cmd->data = 0;
 506         mb();
 507
 508         /* send a rdma command to the PCIe engine, and wait for the
 509          * response in the confirmation address.  The firmware should
 510          * write a -1 there to indicate it is alive and well
 511          */
 512         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 513         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 514
 515         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 516         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 517         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 518         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 519         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 520         buf[5] = htonl(enable); /* enable? */
 521
 522         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 523
 524         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 525         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 526                 msleep(1);
 527         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 528                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 529                         (enable ? "enable" : "disable"));
 530 }
 531
 532 static int
 533 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 534                            struct mcp_gen_header *hdr)
 535 {
 536         struct device *dev = &mgp->pdev->dev;
 537
 538         /* check firmware type */
 539         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 540                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 541                 return -EINVAL;
 542         }
 543
 544         /* save firmware version for ethtool */
 545         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 546
 547         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 548                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 549
 550         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
 551               && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 552                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 553                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 554                         MXGEFW_VERSION_MINOR);
 555                 return -EINVAL;
 556         }
 557         return 0;
 558 }
 559
 560 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 561 {
 562         unsigned crc, reread_crc;
 563         const struct firmware *fw;
 564         struct device *dev = &mgp->pdev->dev;
 565         unsigned char *fw_readback;
 566         struct mcp_gen_header *hdr;
 567         size_t hdr_offset;
 568         int status;
 569         unsigned i;
 570
 571         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 572                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 573                         mgp->fw_name);
 574                 status = -EINVAL;
 575                 goto abort_with_nothing;
 576         }
 577
 578         /* check size */
 579
 580         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 581             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 582                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 583                 status = -EINVAL;
 584                 goto abort_with_fw;
 585         }
 586
 587         /* check id */
 588         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 589         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 590                 dev_err(dev, "Bad firmware file\n");
 591                 status = -EINVAL;
 592                 goto abort_with_fw;
 593         }
 594         hdr = (void *)(fw->data + hdr_offset);
 595
 596         status = myri10ge_validate_firmware(mgp, hdr);
 597         if (status != 0)
 598                 goto abort_with_fw;
 599
 600         crc = crc32(~0, fw->data, fw->size);
 601         for (i = 0; i < fw->size; i += 256) {
 602                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 603                                   fw->data + i,
 604                                   min(256U, (unsigned)(fw->size - i)));
 605                 mb();
 606                 readb(mgp->sram);
 607         }
 608         fw_readback = vmalloc(fw->size);
 609         if (!fw_readback) {
 610                 status = -ENOMEM;
 611                 goto abort_with_fw;
 612         }
 613         /* corruption checking is good for parity recovery and buggy chipset */
 614         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 615         reread_crc = crc32(~0, fw_readback, fw->size);
 616         vfree(fw_readback);
 617         if (crc != reread_crc) {
 618                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 619                         (unsigned)fw->size, reread_crc, crc);
 620                 status = -EIO;
 621                 goto abort_with_fw;
 622         }
 623         *size = (u32) fw->size;
 624
 625 abort_with_fw:
 626         release_firmware(fw);
 627
 628 abort_with_nothing:
 629         return status;
 630 }
 631
 632 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 633 {
 634         struct mcp_gen_header *hdr;
 635         struct device *dev = &mgp->pdev->dev;
 636         const size_t bytes = sizeof(struct mcp_gen_header);
 637         size_t hdr_offset;
 638         int status;
 639
 640         /* find running firmware header */
 641         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 642
 643         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 644                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 645                         (int)hdr_offset);
 646                 return -EIO;
 647         }
 648
 649         /* copy header of running firmware from SRAM to host memory to
 650          * validate firmware */
 651         hdr = kmalloc(bytes, GFP_KERNEL);
 652         if (hdr == NULL) {
 653                 dev_err(dev, "could not malloc firmware hdr\n");
 654                 return -ENOMEM;
 655         }
 656         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 657         status = myri10ge_validate_firmware(mgp, hdr);
 658         kfree(hdr);
 659
 660         /* check to see if adopted firmware has bug where adopting
 661          * it will cause broadcasts to be filtered unless the NIC
 662          * is kept in ALLMULTI mode */
 663         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 664             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 665                 mgp->adopted_rx_filter_bug = 1;
 666                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 667                          "working around rx filter bug\n",
 668                          mgp->fw_ver_major, mgp->fw_ver_minor,
 669                          mgp->fw_ver_tiny);
 670         }
 671         return status;
 672 }
 673
 674 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 675 {
 676         struct myri10ge_cmd cmd;
 677         int status;
 678
 679         /* probe for IPv6 TSO support */
 680         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 681         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 682                                    &cmd, 0);
 683         if (status == 0) {
 684                 mgp->max_tso6 = cmd.data0;
 685                 mgp->features |= NETIF_F_TSO6;
 686         }
 687
 688         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 689         if (status != 0) {
 690                 dev_err(&mgp->pdev->dev,
 691                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 692                 return -ENXIO;
 693         }
 694
 695         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 696
 697         return 0;
 698 }
 699
 700 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 701 {
 702         char __iomem *submit;
 703         __be32 buf[16] __attribute__ ((__aligned__(8)));
 704         u32 dma_low, dma_high, size;
 705         int status, i;
 706
 707         size = 0;
 708         status = myri10ge_load_hotplug_firmware(mgp, &size);
 709         if (status) {
 710                 if (!adopt)
 711                         return status;
 712                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 713
 714                 /* Do not attempt to adopt firmware if there
 715                  * was a bad crc */
 716                 if (status == -EIO)
 717                         return status;
 718
 719                 status = myri10ge_adopt_running_firmware(mgp);
 720                 if (status != 0) {
 721                         dev_err(&mgp->pdev->dev,
 722                                 "failed to adopt running firmware\n");
 723                         return status;
 724                 }
 725                 dev_info(&mgp->pdev->dev,
 726                          "Successfully adopted running firmware\n");
 727                 if (mgp->tx_boundary == 4096) {
 728                         dev_warn(&mgp->pdev->dev,
 729                                  "Using firmware currently running on NIC"
 730                                  ".  For optimal\n");
 731                         dev_warn(&mgp->pdev->dev,
 732                                  "performance consider loading optimized "
 733                                  "firmware\n");
 734                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 735                 }
 736
 737                 mgp->fw_name = "adopted";
 738                 mgp->tx_boundary = 2048;
 739                 myri10ge_dummy_rdma(mgp, 1);
 740                 status = myri10ge_get_firmware_capabilities(mgp);
 741                 return status;
 742         }
 743
 744         /* clear confirmation addr */
 745         mgp->cmd->data = 0;
 746         mb();
 747
 748         /* send a reload command to the bootstrap MCP, and wait for the
 749          *  response in the confirmation address.  The firmware should
 750          * write a -1 there to indicate it is alive and well
 751          */
 752         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 753         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 754
 755         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 756         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 757         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 758
 759         /* FIX: All newest firmware should un-protect the bottom of
 760          * the sram before handoff. However, the very first interfaces
 761          * do not. Therefore the handoff copy must skip the first 8 bytes
 762          */
 763         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 764         buf[4] = htonl(size - 8);       /* length of code */
 765         buf[5] = htonl(8);      /* where to copy to */
 766         buf[6] = htonl(0);      /* where to jump to */
 767
 768         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 769
 770         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 771         mb();
 772         msleep(1);
 773         mb();
 774         i = 0;
 775         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 776                 msleep(1 << i);
 777                 i++;
 778         }
 779         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 780                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 781                 return -ENXIO;
 782         }
 783         myri10ge_dummy_rdma(mgp, 1);
 784         status = myri10ge_get_firmware_capabilities(mgp);
 785
 786         return status;
 787 }
 788
 789 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 790 {
 791         struct myri10ge_cmd cmd;
 792         int status;
 793
 794         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 795                      | (addr[2] << 8) | addr[3]);
 796
 797         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 798
 799         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 800         return status;
 801 }
 802
 803 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 804 {
 805         struct myri10ge_cmd cmd;
 806         int status, ctl;
 807
 808         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 809         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 810
 811         if (status) {
 812                 printk(KERN_ERR
 813                        "myri10ge: %s: Failed to set flow control mode\n",
 814                        mgp->dev->name);
 815                 return status;
 816         }
 817         mgp->pause = pause;
 818         return 0;
 819 }
 820
 821 static void
 822 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 823 {
 824         struct myri10ge_cmd cmd;
 825         int status, ctl;
 826
 827         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 828         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 829         if (status)
 830                 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
 831                        mgp->dev->name);
 832 }
 833
 834 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 835 {
 836         struct myri10ge_cmd cmd;
 837         int status;
 838         u32 len;
 839         struct page *dmatest_page;
 840         dma_addr_t dmatest_bus;
 841         char *test = " ";
 842
 843         dmatest_page = alloc_page(GFP_KERNEL);
 844         if (!dmatest_page)
 845                 return -ENOMEM;
 846         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 847                                    DMA_BIDIRECTIONAL);
 848
 849         /* Run a small DMA test.
 850          * The magic multipliers to the length tell the firmware
 851          * to do DMA read, write, or read+write tests.  The
 852          * results are returned in cmd.data0.  The upper 16
 853          * bits or the return is the number of transfers completed.
 854          * The lower 16 bits is the time in 0.5us ticks that the
 855          * transfers took to complete.
 856          */
 857
 858         len = mgp->tx_boundary;
 859
 860         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 861         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 862         cmd.data2 = len * 0x10000;
 863         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 864         if (status != 0) {
 865                 test = "read";
 866                 goto abort;
 867         }
 868         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 869         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 870         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 871         cmd.data2 = len * 0x1;
 872         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 873         if (status != 0) {
 874                 test = "write";
 875                 goto abort;
 876         }
 877         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 878
 879         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 880         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 881         cmd.data2 = len * 0x10001;
 882         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 883         if (status != 0) {
 884                 test = "read/write";
 885                 goto abort;
 886         }
 887         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 888             (cmd.data0 & 0xffff);
 889
 890 abort:
 891         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 892         put_page(dmatest_page);
 893
 894         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 895                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 896                          test, status);
 897
 898         return status;
 899 }
 900
 901 static int myri10ge_reset(struct myri10ge_priv *mgp)
 902 {
 903         struct myri10ge_cmd cmd;
 904         struct myri10ge_slice_state *ss;
 905         int i, status;
 906         size_t bytes;
 907 #ifdef CONFIG_MYRI10GE_DCA
 908         unsigned long dca_tag_off;
 909 #endif
 910
 911         /* try to send a reset command to the card to see if it
 912          * is alive */
 913         memset(&cmd, 0, sizeof(cmd));
 914         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 915         if (status != 0) {
 916                 dev_err(&mgp->pdev->dev, "failed reset\n");
 917                 return -ENXIO;
 918         }
 919
 920         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 921         /*
 922          * Use non-ndis mcp_slot (eg, 4 bytes total,
 923          * no toeplitz hash value returned.  Older firmware will
 924          * not understand this command, but will use the correct
 925          * sized mcp_slot, so we ignore error returns
 926          */
 927         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 928         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 929
 930         /* Now exchange information about interrupts  */
 931
 932         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 933         cmd.data0 = (u32) bytes;
 934         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 935
 936         /*
 937          * Even though we already know how many slices are supported
 938          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 939          * has magic side effects, and must be called after a reset.
 940          * It must be called prior to calling any RSS related cmds,
 941          * including assigning an interrupt queue for anything but
 942          * slice 0.  It must also be called *after*
 943          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 944          * the firmware to compute offsets.
 945          */
 946
 947         if (mgp->num_slices > 1) {
 948
 949                 /* ask the maximum number of slices it supports */
 950                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 951                                            &cmd, 0);
 952                 if (status != 0) {
 953                         dev_err(&mgp->pdev->dev,
 954                                 "failed to get number of slices\n");
 955                 }
 956
 957                 /*
 958                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 959                  * to setting up the interrupt queue DMA
 960                  */
 961
 962                 cmd.data0 = mgp->num_slices;
 963                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 964                 if (mgp->dev->real_num_tx_queues > 1)
 965                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
 966                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 967                                            &cmd, 0);
 968
 969                 /* Firmware older than 1.4.32 only supports multiple
 970                  * RX queues, so if we get an error, first retry using a
 971                  * single TX queue before giving up */
 972                 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
 973                         mgp->dev->real_num_tx_queues = 1;
 974                         cmd.data0 = mgp->num_slices;
 975                         cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 976                         status = myri10ge_send_cmd(mgp,
 977                                                    MXGEFW_CMD_ENABLE_RSS_QUEUES,
 978                                                    &cmd, 0);
 979                 }
 980
 981                 if (status != 0) {
 982                         dev_err(&mgp->pdev->dev,
 983                                 "failed to set number of slices\n");
 984
 985                         return status;
 986                 }
 987         }
 988         for (i = 0; i < mgp->num_slices; i++) {
 989                 ss = &mgp->ss[i];
 990                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
 991                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
 992                 cmd.data2 = i;
 993                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
 994                                             &cmd, 0);
 995         };
 996
 997         status |=
 998             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
 999         for (i = 0; i < mgp->num_slices; i++) {
1000                 ss = &mgp->ss[i];
1001                 ss->irq_claim =
1002                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1003         }
1004         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1005                                     &cmd, 0);
1006         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1007
1008         status |= myri10ge_send_cmd
1009             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1010         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1011         if (status != 0) {
1012                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1013                 return status;
1014         }
1015         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1016
1017 #ifdef CONFIG_MYRI10GE_DCA
1018         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1019         dca_tag_off = cmd.data0;
1020         for (i = 0; i < mgp->num_slices; i++) {
1021                 ss = &mgp->ss[i];
1022                 if (status == 0) {
1023                         ss->dca_tag = (__iomem __be32 *)
1024                             (mgp->sram + dca_tag_off + 4 * i);
1025                 } else {
1026                         ss->dca_tag = NULL;
1027                 }
1028         }
1029 #endif                          /* CONFIG_MYRI10GE_DCA */
1030
1031         /* reset mcp/driver shared state back to 0 */
1032
1033         mgp->link_changes = 0;
1034         for (i = 0; i < mgp->num_slices; i++) {
1035                 ss = &mgp->ss[i];
1036
1037                 memset(ss->rx_done.entry, 0, bytes);
1038                 ss->tx.req = 0;
1039                 ss->tx.done = 0;
1040                 ss->tx.pkt_start = 0;
1041                 ss->tx.pkt_done = 0;
1042                 ss->rx_big.cnt = 0;
1043                 ss->rx_small.cnt = 0;
1044                 ss->rx_done.idx = 0;
1045                 ss->rx_done.cnt = 0;
1046                 ss->tx.wake_queue = 0;
1047                 ss->tx.stop_queue = 0;
1048         }
1049
1050         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1051         myri10ge_change_pause(mgp, mgp->pause);
1052         myri10ge_set_multicast_list(mgp->dev);
1053         return status;
1054 }
1055
1056 #ifdef CONFIG_MYRI10GE_DCA
1057 static void
1058 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1059 {
1060         ss->cpu = cpu;
1061         ss->cached_dca_tag = tag;
1062         put_be32(htonl(tag), ss->dca_tag);
1063 }
1064
1065 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1066 {
1067         int cpu = get_cpu();
1068         int tag;
1069
1070         if (cpu != ss->cpu) {
1071                 tag = dca_get_tag(cpu);
1072                 if (ss->cached_dca_tag != tag)
1073                         myri10ge_write_dca(ss, cpu, tag);
1074         }
1075         put_cpu();
1076 }
1077
1078 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1079 {
1080         int err, i;
1081         struct pci_dev *pdev = mgp->pdev;
1082
1083         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1084                 return;
1085         if (!myri10ge_dca) {
1086                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1087                 return;
1088         }
1089         err = dca_add_requester(&pdev->dev);
1090         if (err) {
1091                 if (err != -ENODEV)
1092                         dev_err(&pdev->dev,
1093                                 "dca_add_requester() failed, err=%d\n", err);
1094                 return;
1095         }
1096         mgp->dca_enabled = 1;
1097         for (i = 0; i < mgp->num_slices; i++)
1098                 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1099 }
1100
1101 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1102 {
1103         struct pci_dev *pdev = mgp->pdev;
1104         int err;
1105
1106         if (!mgp->dca_enabled)
1107                 return;
1108         mgp->dca_enabled = 0;
1109         err = dca_remove_requester(&pdev->dev);
1110 }
1111
1112 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1113 {
1114         struct myri10ge_priv *mgp;
1115         unsigned long event;
1116
1117         mgp = dev_get_drvdata(dev);
1118         event = *(unsigned long *)data;
1119
1120         if (event == DCA_PROVIDER_ADD)
1121                 myri10ge_setup_dca(mgp);
1122         else if (event == DCA_PROVIDER_REMOVE)
1123                 myri10ge_teardown_dca(mgp);
1124         return 0;
1125 }
1126 #endif                          /* CONFIG_MYRI10GE_DCA */
1127
1128 static inline void
1129 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1130                     struct mcp_kreq_ether_recv *src)
1131 {
1132         __be32 low;
1133
1134         low = src->addr_low;
1135         src->addr_low = htonl(DMA_BIT_MASK(32));
1136         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1137         mb();
1138         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1139         mb();
1140         src->addr_low = low;
1141         put_be32(low, &dst->addr_low);
1142         mb();
1143 }
1144
1145 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1146 {
1147         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1148
1149         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1150             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1151              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1152                 skb->csum = hw_csum;
1153                 skb->ip_summed = CHECKSUM_COMPLETE;
1154         }
1155 }
1156
1157 static inline void
1158 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1159                       struct skb_frag_struct *rx_frags, int len, int hlen)
1160 {
1161         struct skb_frag_struct *skb_frags;
1162
1163         skb->len = skb->data_len = len;
1164         skb->truesize = len + sizeof(struct sk_buff);
1165         /* attach the page(s) */
1166
1167         skb_frags = skb_shinfo(skb)->frags;
1168         while (len > 0) {
1169                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1170                 len -= rx_frags->size;
1171                 skb_frags++;
1172                 rx_frags++;
1173                 skb_shinfo(skb)->nr_frags++;
1174         }
1175
1176         /* pskb_may_pull is not available in irq context, but
1177          * skb_pull() (for ether_pad and eth_type_trans()) requires
1178          * the beginning of the packet in skb_headlen(), move it
1179          * manually */
1180         skb_copy_to_linear_data(skb, va, hlen);
1181         skb_shinfo(skb)->frags[0].page_offset += hlen;
1182         skb_shinfo(skb)->frags[0].size -= hlen;
1183         skb->data_len -= hlen;
1184         skb->tail += hlen;
1185         skb_pull(skb, MXGEFW_PAD);
1186 }
1187
1188 static void
1189 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1190                         int bytes, int watchdog)
1191 {
1192         struct page *page;
1193         int idx;
1194
1195         if (unlikely(rx->watchdog_needed && !watchdog))
1196                 return;
1197
1198         /* try to refill entire ring */
1199         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1200                 idx = rx->fill_cnt & rx->mask;
1201                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1202                         /* we can use part of previous page */
1203                         get_page(rx->page);
1204                 } else {
1205                         /* we need a new page */
1206                         page =
1207                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1208                                         MYRI10GE_ALLOC_ORDER);
1209                         if (unlikely(page == NULL)) {
1210                                 if (rx->fill_cnt - rx->cnt < 16)
1211                                         rx->watchdog_needed = 1;
1212                                 return;
1213                         }
1214                         rx->page = page;
1215                         rx->page_offset = 0;
1216                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1217                                                MYRI10GE_ALLOC_SIZE,
1218                                                PCI_DMA_FROMDEVICE);
1219                 }
1220                 rx->info[idx].page = rx->page;
1221                 rx->info[idx].page_offset = rx->page_offset;
1222                 /* note that this is the address of the start of the
1223                  * page */
1224                 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1225                 rx->shadow[idx].addr_low =
1226                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1227                 rx->shadow[idx].addr_high =
1228                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1229
1230                 /* start next packet on a cacheline boundary */
1231                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1232
1233 #if MYRI10GE_ALLOC_SIZE > 4096
1234                 /* don't cross a 4KB boundary */
1235                 if ((rx->page_offset >> 12) !=
1236                     ((rx->page_offset + bytes - 1) >> 12))
1237                         rx->page_offset = (rx->page_offset + 4096) & ~4095;
1238 #endif
1239                 rx->fill_cnt++;
1240
1241                 /* copy 8 descriptors to the firmware at a time */
1242                 if ((idx & 7) == 7) {
1243                         myri10ge_submit_8rx(&rx->lanai[idx - 7],
1244                                             &rx->shadow[idx - 7]);
1245                 }
1246         }
1247 }
1248
1249 static inline void
1250 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1251                        struct myri10ge_rx_buffer_state *info, int bytes)
1252 {
1253         /* unmap the recvd page if we're the only or last user of it */
1254         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1255             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1256                 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1257                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1258                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1259         }
1260 }
1261
1262 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1263                                  * page into an skb */
1264
1265 static inline int
1266 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1267                  int bytes, int len, __wsum csum)
1268 {
1269         struct myri10ge_priv *mgp = ss->mgp;
1270         struct sk_buff *skb;
1271         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1272         int i, idx, hlen, remainder;
1273         struct pci_dev *pdev = mgp->pdev;
1274         struct net_device *dev = mgp->dev;
1275         u8 *va;
1276
1277         len += MXGEFW_PAD;
1278         idx = rx->cnt & rx->mask;
1279         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1280         prefetch(va);
1281         /* Fill skb_frag_struct(s) with data from our receive */
1282         for (i = 0, remainder = len; remainder > 0; i++) {
1283                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1284                 rx_frags[i].page = rx->info[idx].page;
1285                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1286                 if (remainder < MYRI10GE_ALLOC_SIZE)
1287                         rx_frags[i].size = remainder;
1288                 else
1289                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1290                 rx->cnt++;
1291                 idx = rx->cnt & rx->mask;
1292                 remainder -= MYRI10GE_ALLOC_SIZE;
1293         }
1294
1295         if (mgp->csum_flag && myri10ge_lro) {
1296                 rx_frags[0].page_offset += MXGEFW_PAD;
1297                 rx_frags[0].size -= MXGEFW_PAD;
1298                 len -= MXGEFW_PAD;
1299                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1300                                   /* opaque, will come back in get_frag_header */
1301                                   len, len,
1302                                   (void *)(__force unsigned long)csum, csum);
1303
1304                 return 1;
1305         }
1306
1307         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1308
1309         /* allocate an skb to attach the page(s) to. This is done
1310          * after trying LRO, so as to avoid skb allocation overheads */
1311
1312         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1313         if (unlikely(skb == NULL)) {
1314                 ss->stats.rx_dropped++;
1315                 do {
1316                         i--;
1317                         put_page(rx_frags[i].page);
1318                 } while (i != 0);
1319                 return 0;
1320         }
1321
1322         /* Attach the pages to the skb, and trim off any padding */
1323         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1324         if (skb_shinfo(skb)->frags[0].size <= 0) {
1325                 put_page(skb_shinfo(skb)->frags[0].page);
1326                 skb_shinfo(skb)->nr_frags = 0;
1327         }
1328         skb->protocol = eth_type_trans(skb, dev);
1329         skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1330
1331         if (mgp->csum_flag) {
1332                 if ((skb->protocol == htons(ETH_P_IP)) ||
1333                     (skb->protocol == htons(ETH_P_IPV6))) {
1334                         skb->csum = csum;
1335                         skb->ip_summed = CHECKSUM_COMPLETE;
1336                 } else
1337                         myri10ge_vlan_ip_csum(skb, csum);
1338         }
1339         netif_receive_skb(skb);
1340         return 1;
1341 }
1342
1343 static inline void
1344 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1345 {
1346         struct pci_dev *pdev = ss->mgp->pdev;
1347         struct myri10ge_tx_buf *tx = &ss->tx;
1348         struct netdev_queue *dev_queue;
1349         struct sk_buff *skb;
1350         int idx, len;
1351
1352         while (tx->pkt_done != mcp_index) {
1353                 idx = tx->done & tx->mask;
1354                 skb = tx->info[idx].skb;
1355
1356                 /* Mark as free */
1357                 tx->info[idx].skb = NULL;
1358                 if (tx->info[idx].last) {
1359                         tx->pkt_done++;
1360                         tx->info[idx].last = 0;
1361                 }
1362                 tx->done++;
1363                 len = pci_unmap_len(&tx->info[idx], len);
1364                 pci_unmap_len_set(&tx->info[idx], len, 0);
1365                 if (skb) {
1366                         ss->stats.tx_bytes += skb->len;
1367                         ss->stats.tx_packets++;
1368                         dev_kfree_skb_irq(skb);
1369                         if (len)
1370                                 pci_unmap_single(pdev,
1371                                                  pci_unmap_addr(&tx->info[idx],
1372                                                                 bus), len,
1373                                                  PCI_DMA_TODEVICE);
1374                 } else {
1375                         if (len)
1376                                 pci_unmap_page(pdev,
1377                                                pci_unmap_addr(&tx->info[idx],
1378                                                               bus), len,
1379                                                PCI_DMA_TODEVICE);
1380                 }
1381         }
1382
1383         dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1384         /*
1385          * Make a minimal effort to prevent the NIC from polling an
1386          * idle tx queue.  If we can't get the lock we leave the queue
1387          * active. In this case, either a thread was about to start
1388          * using the queue anyway, or we lost a race and the NIC will
1389          * waste some of its resources polling an inactive queue for a
1390          * while.
1391          */
1392
1393         if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1394             __netif_tx_trylock(dev_queue)) {
1395                 if (tx->req == tx->done) {
1396                         tx->queue_active = 0;
1397                         put_be32(htonl(1), tx->send_stop);
1398                         mb();
1399                         mmiowb();
1400                 }
1401                 __netif_tx_unlock(dev_queue);
1402         }
1403
1404         /* start the queue if we've stopped it */
1405         if (netif_tx_queue_stopped(dev_queue)
1406             && tx->req - tx->done < (tx->mask >> 1)) {
1407                 tx->wake_queue++;
1408                 netif_tx_wake_queue(dev_queue);
1409         }
1410 }
1411
1412 static inline int
1413 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1414 {
1415         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1416         struct myri10ge_priv *mgp = ss->mgp;
1417         unsigned long rx_bytes = 0;
1418         unsigned long rx_packets = 0;
1419         unsigned long rx_ok;
1420
1421         int idx = rx_done->idx;
1422         int cnt = rx_done->cnt;
1423         int work_done = 0;
1424         u16 length;
1425         __wsum checksum;
1426
1427         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1428                 length = ntohs(rx_done->entry[idx].length);
1429                 rx_done->entry[idx].length = 0;
1430                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1431                 if (length <= mgp->small_bytes)
1432                         rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1433                                                  mgp->small_bytes,
1434                                                  length, checksum);
1435                 else
1436                         rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1437                                                  mgp->big_bytes,
1438                                                  length, checksum);
1439                 rx_packets += rx_ok;
1440                 rx_bytes += rx_ok * (unsigned long)length;
1441                 cnt++;
1442                 idx = cnt & (mgp->max_intr_slots - 1);
1443                 work_done++;
1444         }
1445         rx_done->idx = idx;
1446         rx_done->cnt = cnt;
1447         ss->stats.rx_packets += rx_packets;
1448         ss->stats.rx_bytes += rx_bytes;
1449
1450         if (myri10ge_lro)
1451                 lro_flush_all(&rx_done->lro_mgr);
1452
1453         /* restock receive rings if needed */
1454         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1455                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1456                                         mgp->small_bytes + MXGEFW_PAD, 0);
1457         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1458                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1459
1460         return work_done;
1461 }
1462
1463 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1464 {
1465         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1466
1467         if (unlikely(stats->stats_updated)) {
1468                 unsigned link_up = ntohl(stats->link_up);
1469                 if (mgp->link_state != link_up) {
1470                         mgp->link_state = link_up;
1471
1472                         if (mgp->link_state == MXGEFW_LINK_UP) {
1473                                 if (netif_msg_link(mgp))
1474                                         printk(KERN_INFO
1475                                                "myri10ge: %s: link up\n",
1476                                                mgp->dev->name);
1477                                 netif_carrier_on(mgp->dev);
1478                                 mgp->link_changes++;
1479                         } else {
1480                                 if (netif_msg_link(mgp))
1481                                         printk(KERN_INFO
1482                                                "myri10ge: %s: link %s\n",
1483                                                mgp->dev->name,
1484                                                (link_up == MXGEFW_LINK_MYRINET ?
1485                                                 "mismatch (Myrinet detected)" :
1486                                                 "down"));
1487                                 netif_carrier_off(mgp->dev);
1488                                 mgp->link_changes++;
1489                         }
1490                 }
1491                 if (mgp->rdma_tags_available !=
1492                     ntohl(stats->rdma_tags_available)) {
1493                         mgp->rdma_tags_available =
1494                             ntohl(stats->rdma_tags_available);
1495                         printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1496                                "%d tags left\n", mgp->dev->name,
1497                                mgp->rdma_tags_available);
1498                 }
1499                 mgp->down_cnt += stats->link_down;
1500                 if (stats->link_down)
1501                         wake_up(&mgp->down_wq);
1502         }
1503 }
1504
1505 static int myri10ge_poll(struct napi_struct *napi, int budget)
1506 {
1507         struct myri10ge_slice_state *ss =
1508             container_of(napi, struct myri10ge_slice_state, napi);
1509         int work_done;
1510
1511 #ifdef CONFIG_MYRI10GE_DCA
1512         if (ss->mgp->dca_enabled)
1513                 myri10ge_update_dca(ss);
1514 #endif
1515
1516         /* process as many rx events as NAPI will allow */
1517         work_done = myri10ge_clean_rx_done(ss, budget);
1518
1519         if (work_done < budget) {
1520                 napi_complete(napi);
1521                 put_be32(htonl(3), ss->irq_claim);
1522         }
1523         return work_done;
1524 }
1525
1526 static irqreturn_t myri10ge_intr(int irq, void *arg)
1527 {
1528         struct myri10ge_slice_state *ss = arg;
1529         struct myri10ge_priv *mgp = ss->mgp;
1530         struct mcp_irq_data *stats = ss->fw_stats;
1531         struct myri10ge_tx_buf *tx = &ss->tx;
1532         u32 send_done_count;
1533         int i;
1534
1535         /* an interrupt on a non-zero receive-only slice is implicitly
1536          * valid  since MSI-X irqs are not shared */
1537         if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1538                 napi_schedule(&ss->napi);
1539                 return (IRQ_HANDLED);
1540         }
1541
1542         /* make sure it is our IRQ, and that the DMA has finished */
1543         if (unlikely(!stats->valid))
1544                 return (IRQ_NONE);
1545
1546         /* low bit indicates receives are present, so schedule
1547          * napi poll handler */
1548         if (stats->valid & 1)
1549                 napi_schedule(&ss->napi);
1550
1551         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1552                 put_be32(0, mgp->irq_deassert);
1553                 if (!myri10ge_deassert_wait)
1554                         stats->valid = 0;
1555                 mb();
1556         } else
1557                 stats->valid = 0;
1558
1559         /* Wait for IRQ line to go low, if using INTx */
1560         i = 0;
1561         while (1) {
1562                 i++;
1563                 /* check for transmit completes and receives */
1564                 send_done_count = ntohl(stats->send_done_count);
1565                 if (send_done_count != tx->pkt_done)
1566                         myri10ge_tx_done(ss, (int)send_done_count);
1567                 if (unlikely(i > myri10ge_max_irq_loops)) {
1568                         printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1569                                mgp->dev->name);
1570                         stats->valid = 0;
1571                         schedule_work(&mgp->watchdog_work);
1572                 }
1573                 if (likely(stats->valid == 0))
1574                         break;
1575                 cpu_relax();
1576                 barrier();
1577         }
1578
1579         /* Only slice 0 updates stats */
1580         if (ss == mgp->ss)
1581                 myri10ge_check_statblock(mgp);
1582
1583         put_be32(htonl(3), ss->irq_claim + 1);
1584         return (IRQ_HANDLED);
1585 }
1586
1587 static int
1588 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1589 {
1590         struct myri10ge_priv *mgp = netdev_priv(netdev);
1591         char *ptr;
1592         int i;
1593
1594         cmd->autoneg = AUTONEG_DISABLE;
1595         cmd->speed = SPEED_10000;
1596         cmd->duplex = DUPLEX_FULL;
1597
1598         /*
1599          * parse the product code to deterimine the interface type
1600          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1601          * after the 3rd dash in the driver's cached copy of the
1602          * EEPROM's product code string.
1603          */
1604         ptr = mgp->product_code_string;
1605         if (ptr == NULL) {
1606                 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1607                        netdev->name);
1608                 return 0;
1609         }
1610         for (i = 0; i < 3; i++, ptr++) {
1611                 ptr = strchr(ptr, '-');
1612                 if (ptr == NULL) {
1613                         printk(KERN_ERR "myri10ge: %s: Invalid product "
1614                                "code %s\n", netdev->name,
1615                                mgp->product_code_string);
1616                         return 0;
1617                 }
1618         }
1619         if (*ptr == 'R' || *ptr == 'Q') {
1620                 /* We've found either an XFP or quad ribbon fiber */
1621                 cmd->port = PORT_FIBRE;
1622         }
1623         return 0;
1624 }
1625
1626 static void
1627 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1628 {
1629         struct myri10ge_priv *mgp = netdev_priv(netdev);
1630
1631         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1632         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1633         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1634         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1635 }
1636
1637 static int
1638 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1639 {
1640         struct myri10ge_priv *mgp = netdev_priv(netdev);
1641
1642         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1643         return 0;
1644 }
1645
1646 static int
1647 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1648 {
1649         struct myri10ge_priv *mgp = netdev_priv(netdev);
1650
1651         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1652         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1653         return 0;
1654 }
1655
1656 static void
1657 myri10ge_get_pauseparam(struct net_device *netdev,
1658                         struct ethtool_pauseparam *pause)
1659 {
1660         struct myri10ge_priv *mgp = netdev_priv(netdev);
1661
1662         pause->autoneg = 0;
1663         pause->rx_pause = mgp->pause;
1664         pause->tx_pause = mgp->pause;
1665 }
1666
1667 static int
1668 myri10ge_set_pauseparam(struct net_device *netdev,
1669                         struct ethtool_pauseparam *pause)
1670 {
1671         struct myri10ge_priv *mgp = netdev_priv(netdev);
1672
1673         if (pause->tx_pause != mgp->pause)
1674                 return myri10ge_change_pause(mgp, pause->tx_pause);
1675         if (pause->rx_pause != mgp->pause)
1676                 return myri10ge_change_pause(mgp, pause->tx_pause);
1677         if (pause->autoneg != 0)
1678                 return -EINVAL;
1679         return 0;
1680 }
1681
1682 static void
1683 myri10ge_get_ringparam(struct net_device *netdev,
1684                        struct ethtool_ringparam *ring)
1685 {
1686         struct myri10ge_priv *mgp = netdev_priv(netdev);
1687
1688         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1689         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1690         ring->rx_jumbo_max_pending = 0;
1691         ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1692         ring->rx_mini_pending = ring->rx_mini_max_pending;
1693         ring->rx_pending = ring->rx_max_pending;
1694         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1695         ring->tx_pending = ring->tx_max_pending;
1696 }
1697
1698 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1699 {
1700         struct myri10ge_priv *mgp = netdev_priv(netdev);
1701
1702         if (mgp->csum_flag)
1703                 return 1;
1704         else
1705                 return 0;
1706 }
1707
1708 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1709 {
1710         struct myri10ge_priv *mgp = netdev_priv(netdev);
1711
1712         if (csum_enabled)
1713                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1714         else
1715                 mgp->csum_flag = 0;
1716         return 0;
1717 }
1718
1719 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1720 {
1721         struct myri10ge_priv *mgp = netdev_priv(netdev);
1722         unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1723
1724         if (tso_enabled)
1725                 netdev->features |= flags;
1726         else
1727                 netdev->features &= ~flags;
1728         return 0;
1729 }
1730
1731 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1732         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1733         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1734         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1735         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1736         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1737         "tx_heartbeat_errors", "tx_window_errors",
1738         /* device-specific stats */
1739         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1740         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1741         "serial_number", "watchdog_resets",
1742 #ifdef CONFIG_MYRI10GE_DCA
1743         "dca_capable_firmware", "dca_device_present",
1744 #endif
1745         "link_changes", "link_up", "dropped_link_overflow",
1746         "dropped_link_error_or_filtered",
1747         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1748         "dropped_unicast_filtered", "dropped_multicast_filtered",
1749         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1750         "dropped_no_big_buffer"
1751 };
1752
1753 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1754         "----------- slice ---------",
1755         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1756         "rx_small_cnt", "rx_big_cnt",
1757         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1758             "LRO flushed",
1759         "LRO avg aggr", "LRO no_desc"
1760 };
1761
1762 #define MYRI10GE_NET_STATS_LEN      21
1763 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1764 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1765
1766 static void
1767 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1768 {
1769         struct myri10ge_priv *mgp = netdev_priv(netdev);
1770         int i;
1771
1772         switch (stringset) {
1773         case ETH_SS_STATS:
1774                 memcpy(data, *myri10ge_gstrings_main_stats,
1775                        sizeof(myri10ge_gstrings_main_stats));
1776                 data += sizeof(myri10ge_gstrings_main_stats);
1777                 for (i = 0; i < mgp->num_slices; i++) {
1778                         memcpy(data, *myri10ge_gstrings_slice_stats,
1779                                sizeof(myri10ge_gstrings_slice_stats));
1780                         data += sizeof(myri10ge_gstrings_slice_stats);
1781                 }
1782                 break;
1783         }
1784 }
1785
1786 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1787 {
1788         struct myri10ge_priv *mgp = netdev_priv(netdev);
1789
1790         switch (sset) {
1791         case ETH_SS_STATS:
1792                 return MYRI10GE_MAIN_STATS_LEN +
1793                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1794         default:
1795                 return -EOPNOTSUPP;
1796         }
1797 }
1798
1799 static void
1800 myri10ge_get_ethtool_stats(struct net_device *netdev,
1801                            struct ethtool_stats *stats, u64 * data)
1802 {
1803         struct myri10ge_priv *mgp = netdev_priv(netdev);
1804         struct myri10ge_slice_state *ss;
1805         int slice;
1806         int i;
1807
1808         /* force stats update */
1809         (void)myri10ge_get_stats(netdev);
1810         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1811                 data[i] = ((unsigned long *)&mgp->stats)[i];
1812
1813         data[i++] = (unsigned int)mgp->tx_boundary;
1814         data[i++] = (unsigned int)mgp->wc_enabled;
1815         data[i++] = (unsigned int)mgp->pdev->irq;
1816         data[i++] = (unsigned int)mgp->msi_enabled;
1817         data[i++] = (unsigned int)mgp->msix_enabled;
1818         data[i++] = (unsigned int)mgp->read_dma;
1819         data[i++] = (unsigned int)mgp->write_dma;
1820         data[i++] = (unsigned int)mgp->read_write_dma;
1821         data[i++] = (unsigned int)mgp->serial_number;
1822         data[i++] = (unsigned int)mgp->watchdog_resets;
1823 #ifdef CONFIG_MYRI10GE_DCA
1824         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1825         data[i++] = (unsigned int)(mgp->dca_enabled);
1826 #endif
1827         data[i++] = (unsigned int)mgp->link_changes;
1828
1829         /* firmware stats are useful only in the first slice */
1830         ss = &mgp->ss[0];
1831         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1832         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1833         data[i++] =
1834             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1835         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1836         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1837         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1838         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1839         data[i++] =
1840             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1841         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1842         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1843         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1844         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1845
1846         for (slice = 0; slice < mgp->num_slices; slice++) {
1847                 ss = &mgp->ss[slice];
1848                 data[i++] = slice;
1849                 data[i++] = (unsigned int)ss->tx.pkt_start;
1850                 data[i++] = (unsigned int)ss->tx.pkt_done;
1851                 data[i++] = (unsigned int)ss->tx.req;
1852                 data[i++] = (unsigned int)ss->tx.done;
1853                 data[i++] = (unsigned int)ss->rx_small.cnt;
1854                 data[i++] = (unsigned int)ss->rx_big.cnt;
1855                 data[i++] = (unsigned int)ss->tx.wake_queue;
1856                 data[i++] = (unsigned int)ss->tx.stop_queue;
1857                 data[i++] = (unsigned int)ss->tx.linearized;
1858                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1859                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1860                 if (ss->rx_done.lro_mgr.stats.flushed)
1861                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1862                             ss->rx_done.lro_mgr.stats.flushed;
1863                 else
1864                         data[i++] = 0;
1865                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1866         }
1867 }
1868
1869 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1870 {
1871         struct myri10ge_priv *mgp = netdev_priv(netdev);
1872         mgp->msg_enable = value;
1873 }
1874
1875 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1876 {
1877         struct myri10ge_priv *mgp = netdev_priv(netdev);
1878         return mgp->msg_enable;
1879 }
1880
1881 static const struct ethtool_ops myri10ge_ethtool_ops = {
1882         .get_settings = myri10ge_get_settings,
1883         .get_drvinfo = myri10ge_get_drvinfo,
1884         .get_coalesce = myri10ge_get_coalesce,
1885         .set_coalesce = myri10ge_set_coalesce,
1886         .get_pauseparam = myri10ge_get_pauseparam,
1887         .set_pauseparam = myri10ge_set_pauseparam,
1888         .get_ringparam = myri10ge_get_ringparam,
1889         .get_rx_csum = myri10ge_get_rx_csum,
1890         .set_rx_csum = myri10ge_set_rx_csum,
1891         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1892         .set_sg = ethtool_op_set_sg,
1893         .set_tso = myri10ge_set_tso,
1894         .get_link = ethtool_op_get_link,
1895         .get_strings = myri10ge_get_strings,
1896         .get_sset_count = myri10ge_get_sset_count,
1897         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1898         .set_msglevel = myri10ge_set_msglevel,
1899         .get_msglevel = myri10ge_get_msglevel
1900 };
1901
1902 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1903 {
1904         struct myri10ge_priv *mgp = ss->mgp;
1905         struct myri10ge_cmd cmd;
1906         struct net_device *dev = mgp->dev;
1907         int tx_ring_size, rx_ring_size;
1908         int tx_ring_entries, rx_ring_entries;
1909         int i, slice, status;
1910         size_t bytes;
1911
1912         /* get ring sizes */
1913         slice = ss - mgp->ss;
1914         cmd.data0 = slice;
1915         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1916         tx_ring_size = cmd.data0;
1917         cmd.data0 = slice;
1918         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1919         if (status != 0)
1920                 return status;
1921         rx_ring_size = cmd.data0;
1922
1923         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1924         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1925         ss->tx.mask = tx_ring_entries - 1;
1926         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1927
1928         status = -ENOMEM;
1929
1930         /* allocate the host shadow rings */
1931
1932         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1933             * sizeof(*ss->tx.req_list);
1934         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1935         if (ss->tx.req_bytes == NULL)
1936                 goto abort_with_nothing;
1937
1938         /* ensure req_list entries are aligned to 8 bytes */
1939         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1940             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1941         ss->tx.queue_active = 0;
1942
1943         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1944         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1945         if (ss->rx_small.shadow == NULL)
1946                 goto abort_with_tx_req_bytes;
1947
1948         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1949         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1950         if (ss->rx_big.shadow == NULL)
1951                 goto abort_with_rx_small_shadow;
1952
1953         /* allocate the host info rings */
1954
1955         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1956         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1957         if (ss->tx.info == NULL)
1958                 goto abort_with_rx_big_shadow;
1959
1960         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1961         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1962         if (ss->rx_small.info == NULL)
1963                 goto abort_with_tx_info;
1964
1965         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1966         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1967         if (ss->rx_big.info == NULL)
1968                 goto abort_with_rx_small_info;
1969
1970         /* Fill the receive rings */
1971         ss->rx_big.cnt = 0;
1972         ss->rx_small.cnt = 0;
1973         ss->rx_big.fill_cnt = 0;
1974         ss->rx_small.fill_cnt = 0;
1975         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1976         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1977         ss->rx_small.watchdog_needed = 0;
1978         ss->rx_big.watchdog_needed = 0;
1979         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1980                                 mgp->small_bytes + MXGEFW_PAD, 0);
1981
1982         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1983                 printk(KERN_ERR
1984                        "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1985                        dev->name, slice, ss->rx_small.fill_cnt);
1986                 goto abort_with_rx_small_ring;
1987         }
1988
1989         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1990         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1991                 printk(KERN_ERR
1992                        "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1993                        dev->name, slice, ss->rx_big.fill_cnt);
1994                 goto abort_with_rx_big_ring;
1995         }
1996
1997         return 0;
1998
1999 abort_with_rx_big_ring:
2000         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2001                 int idx = i & ss->rx_big.mask;
2002                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2003                                        mgp->big_bytes);
2004                 put_page(ss->rx_big.info[idx].page);
2005         }
2006
2007 abort_with_rx_small_ring:
2008         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2009                 int idx = i & ss->rx_small.mask;
2010                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2011                                        mgp->small_bytes + MXGEFW_PAD);
2012                 put_page(ss->rx_small.info[idx].page);
2013         }
2014
2015         kfree(ss->rx_big.info);
2016
2017 abort_with_rx_small_info:
2018         kfree(ss->rx_small.info);
2019
2020 abort_with_tx_info:
2021         kfree(ss->tx.info);
2022
2023 abort_with_rx_big_shadow:
2024         kfree(ss->rx_big.shadow);
2025
2026 abort_with_rx_small_shadow:
2027         kfree(ss->rx_small.shadow);
2028
2029 abort_with_tx_req_bytes:
2030         kfree(ss->tx.req_bytes);
2031         ss->tx.req_bytes = NULL;
2032         ss->tx.req_list = NULL;
2033
2034 abort_with_nothing:
2035         return status;
2036 }
2037
2038 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2039 {
2040         struct myri10ge_priv *mgp = ss->mgp;
2041         struct sk_buff *skb;
2042         struct myri10ge_tx_buf *tx;
2043         int i, len, idx;
2044
2045         /* If not allocated, skip it */
2046         if (ss->tx.req_list == NULL)
2047                 return;
2048
2049         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2050                 idx = i & ss->rx_big.mask;
2051                 if (i == ss->rx_big.fill_cnt - 1)
2052                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2053                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2054                                        mgp->big_bytes);
2055                 put_page(ss->rx_big.info[idx].page);
2056         }
2057
2058         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2059                 idx = i & ss->rx_small.mask;
2060                 if (i == ss->rx_small.fill_cnt - 1)
2061                         ss->rx_small.info[idx].page_offset =
2062                             MYRI10GE_ALLOC_SIZE;
2063                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2064                                        mgp->small_bytes + MXGEFW_PAD);
2065                 put_page(ss->rx_small.info[idx].page);
2066         }
2067         tx = &ss->tx;
2068         while (tx->done != tx->req) {
2069                 idx = tx->done & tx->mask;
2070                 skb = tx->info[idx].skb;
2071
2072                 /* Mark as free */
2073                 tx->info[idx].skb = NULL;
2074                 tx->done++;
2075                 len = pci_unmap_len(&tx->info[idx], len);
2076                 pci_unmap_len_set(&tx->info[idx], len, 0);
2077                 if (skb) {
2078                         ss->stats.tx_dropped++;
2079                         dev_kfree_skb_any(skb);
2080                         if (len)
2081                                 pci_unmap_single(mgp->pdev,
2082                                                  pci_unmap_addr(&tx->info[idx],
2083                                                                 bus), len,
2084                                                  PCI_DMA_TODEVICE);
2085                 } else {
2086                         if (len)
2087                                 pci_unmap_page(mgp->pdev,
2088                                                pci_unmap_addr(&tx->info[idx],
2089                                                               bus), len,
2090                                                PCI_DMA_TODEVICE);
2091                 }
2092         }
2093         kfree(ss->rx_big.info);
2094
2095         kfree(ss->rx_small.info);
2096
2097         kfree(ss->tx.info);
2098
2099         kfree(ss->rx_big.shadow);
2100
2101         kfree(ss->rx_small.shadow);
2102
2103         kfree(ss->tx.req_bytes);
2104         ss->tx.req_bytes = NULL;
2105         ss->tx.req_list = NULL;
2106 }
2107
2108 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2109 {
2110         struct pci_dev *pdev = mgp->pdev;
2111         struct myri10ge_slice_state *ss;
2112         struct net_device *netdev = mgp->dev;
2113         int i;
2114         int status;
2115
2116         mgp->msi_enabled = 0;
2117         mgp->msix_enabled = 0;
2118         status = 0;
2119         if (myri10ge_msi) {
2120                 if (mgp->num_slices > 1) {
2121                         status =
2122                             pci_enable_msix(pdev, mgp->msix_vectors,
2123                                             mgp->num_slices);
2124                         if (status == 0) {
2125                                 mgp->msix_enabled = 1;
2126                         } else {
2127                                 dev_err(&pdev->dev,
2128                                         "Error %d setting up MSI-X\n", status);
2129                                 return status;
2130                         }
2131                 }
2132                 if (mgp->msix_enabled == 0) {
2133                         status = pci_enable_msi(pdev);
2134                         if (status != 0) {
2135                                 dev_err(&pdev->dev,
2136                                         "Error %d setting up MSI; falling back to xPIC\n",
2137                                         status);
2138                         } else {
2139                                 mgp->msi_enabled = 1;
2140                         }
2141                 }
2142         }
2143         if (mgp->msix_enabled) {
2144                 for (i = 0; i < mgp->num_slices; i++) {
2145                         ss = &mgp->ss[i];
2146                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2147                                  "%s:slice-%d", netdev->name, i);
2148                         status = request_irq(mgp->msix_vectors[i].vector,
2149                                              myri10ge_intr, 0, ss->irq_desc,
2150                                              ss);
2151                         if (status != 0) {
2152                                 dev_err(&pdev->dev,
2153                                         "slice %d failed to allocate IRQ\n", i);
2154                                 i--;
2155                                 while (i >= 0) {
2156                                         free_irq(mgp->msix_vectors[i].vector,
2157                                                  &mgp->ss[i]);
2158                                         i--;
2159                                 }
2160                                 pci_disable_msix(pdev);
2161                                 return status;
2162                         }
2163                 }
2164         } else {
2165                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2166                                      mgp->dev->name, &mgp->ss[0]);
2167                 if (status != 0) {
2168                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2169                         if (mgp->msi_enabled)
2170                                 pci_disable_msi(pdev);
2171                 }
2172         }
2173         return status;
2174 }
2175
2176 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2177 {
2178         struct pci_dev *pdev = mgp->pdev;
2179         int i;
2180
2181         if (mgp->msix_enabled) {
2182                 for (i = 0; i < mgp->num_slices; i++)
2183                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2184         } else {
2185                 free_irq(pdev->irq, &mgp->ss[0]);
2186         }
2187         if (mgp->msi_enabled)
2188                 pci_disable_msi(pdev);
2189         if (mgp->msix_enabled)
2190                 pci_disable_msix(pdev);
2191 }
2192
2193 static int
2194 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2195                          void **ip_hdr, void **tcpudp_hdr,
2196                          u64 * hdr_flags, void *priv)
2197 {
2198         struct ethhdr *eh;
2199         struct vlan_ethhdr *veh;
2200         struct iphdr *iph;
2201         u8 *va = page_address(frag->page) + frag->page_offset;
2202         unsigned long ll_hlen;
2203         /* passed opaque through lro_receive_frags() */
2204         __wsum csum = (__force __wsum) (unsigned long)priv;
2205
2206         /* find the mac header, aborting if not IPv4 */
2207
2208         eh = (struct ethhdr *)va;
2209         *mac_hdr = eh;
2210         ll_hlen = ETH_HLEN;
2211         if (eh->h_proto != htons(ETH_P_IP)) {
2212                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2213                         veh = (struct vlan_ethhdr *)va;
2214                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2215                                 return -1;
2216
2217                         ll_hlen += VLAN_HLEN;
2218
2219                         /*
2220                          *  HW checksum starts ETH_HLEN bytes into
2221                          *  frame, so we must subtract off the VLAN
2222                          *  header's checksum before csum can be used
2223                          */
2224                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2225                                                            VLAN_HLEN, 0));
2226                 } else {
2227                         return -1;
2228                 }
2229         }
2230         *hdr_flags = LRO_IPV4;
2231
2232         iph = (struct iphdr *)(va + ll_hlen);
2233         *ip_hdr = iph;
2234         if (iph->protocol != IPPROTO_TCP)
2235                 return -1;
2236         if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2237                 return -1;
2238         *hdr_flags |= LRO_TCP;
2239         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2240
2241         /* verify the IP checksum */
2242         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2243                 return -1;
2244
2245         /* verify the  checksum */
2246         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2247                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2248                                        IPPROTO_TCP, csum)))
2249                 return -1;
2250
2251         return 0;
2252 }
2253
2254 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2255 {
2256         struct myri10ge_cmd cmd;
2257         struct myri10ge_slice_state *ss;
2258         int status;
2259
2260         ss = &mgp->ss[slice];
2261         status = 0;
2262         if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2263                 cmd.data0 = slice;
2264                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2265                                            &cmd, 0);
2266                 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2267                     (mgp->sram + cmd.data0);
2268         }
2269         cmd.data0 = slice;
2270         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2271                                     &cmd, 0);
2272         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2273             (mgp->sram + cmd.data0);
2274
2275         cmd.data0 = slice;
2276         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2277         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2278             (mgp->sram + cmd.data0);
2279
2280         ss->tx.send_go = (__iomem __be32 *)
2281             (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2282         ss->tx.send_stop = (__iomem __be32 *)
2283             (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2284         return status;
2285
2286 }
2287
2288 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2289 {
2290         struct myri10ge_cmd cmd;
2291         struct myri10ge_slice_state *ss;
2292         int status;
2293
2294         ss = &mgp->ss[slice];
2295         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2296         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2297         cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2298         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2299         if (status == -ENOSYS) {
2300                 dma_addr_t bus = ss->fw_stats_bus;
2301                 if (slice != 0)
2302                         return -EINVAL;
2303                 bus += offsetof(struct mcp_irq_data, send_done_count);
2304                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2305                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2306                 status = myri10ge_send_cmd(mgp,
2307                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2308                                            &cmd, 0);
2309                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2310                 mgp->fw_multicast_support = 0;
2311         } else {
2312                 mgp->fw_multicast_support = 1;
2313         }
2314         return 0;
2315 }
2316
2317 static int myri10ge_open(struct net_device *dev)
2318 {
2319         struct myri10ge_slice_state *ss;
2320         struct myri10ge_priv *mgp = netdev_priv(dev);
2321         struct myri10ge_cmd cmd;
2322         int i, status, big_pow2, slice;
2323         u8 *itable;
2324         struct net_lro_mgr *lro_mgr;
2325
2326         if (mgp->running != MYRI10GE_ETH_STOPPED)
2327                 return -EBUSY;
2328
2329         mgp->running = MYRI10GE_ETH_STARTING;
2330         status = myri10ge_reset(mgp);
2331         if (status != 0) {
2332                 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2333                 goto abort_with_nothing;
2334         }
2335
2336         if (mgp->num_slices > 1) {
2337                 cmd.data0 = mgp->num_slices;
2338                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2339                 if (mgp->dev->real_num_tx_queues > 1)
2340                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2341                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2342                                            &cmd, 0);
2343                 if (status != 0) {
2344                         printk(KERN_ERR
2345                                "myri10ge: %s: failed to set number of slices\n",
2346                                dev->name);
2347                         goto abort_with_nothing;
2348                 }
2349                 /* setup the indirection table */
2350                 cmd.data0 = mgp->num_slices;
2351                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2352                                            &cmd, 0);
2353
2354                 status |= myri10ge_send_cmd(mgp,
2355                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2356                                             &cmd, 0);
2357                 if (status != 0) {
2358                         printk(KERN_ERR
2359                                "myri10ge: %s: failed to setup rss tables\n",
2360                                dev->name);
2361                         goto abort_with_nothing;
2362                 }
2363
2364                 /* just enable an identity mapping */
2365                 itable = mgp->sram + cmd.data0;
2366                 for (i = 0; i < mgp->num_slices; i++)
2367                         __raw_writeb(i, &itable[i]);
2368
2369                 cmd.data0 = 1;
2370                 cmd.data1 = myri10ge_rss_hash;
2371                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2372                                            &cmd, 0);
2373                 if (status != 0) {
2374                         printk(KERN_ERR
2375                                "myri10ge: %s: failed to enable slices\n",
2376                                dev->name);
2377                         goto abort_with_nothing;
2378                 }
2379         }
2380
2381         status = myri10ge_request_irq(mgp);
2382         if (status != 0)
2383                 goto abort_with_nothing;
2384
2385         /* decide what small buffer size to use.  For good TCP rx
2386          * performance, it is important to not receive 1514 byte
2387          * frames into jumbo buffers, as it confuses the socket buffer
2388          * accounting code, leading to drops and erratic performance.
2389          */
2390
2391         if (dev->mtu <= ETH_DATA_LEN)
2392                 /* enough for a TCP header */
2393                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2394                     ? (128 - MXGEFW_PAD)
2395                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2396         else
2397                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2398                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2399
2400         /* Override the small buffer size? */
2401         if (myri10ge_small_bytes > 0)
2402                 mgp->small_bytes = myri10ge_small_bytes;
2403
2404         /* Firmware needs the big buff size as a power of 2.  Lie and
2405          * tell him the buffer is larger, because we only use 1
2406          * buffer/pkt, and the mtu will prevent overruns.
2407          */
2408         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2409         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2410                 while (!is_power_of_2(big_pow2))
2411                         big_pow2++;
2412                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2413         } else {
2414                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2415                 mgp->big_bytes = big_pow2;
2416         }
2417
2418         /* setup the per-slice data structures */
2419         for (slice = 0; slice < mgp->num_slices; slice++) {
2420                 ss = &mgp->ss[slice];
2421
2422                 status = myri10ge_get_txrx(mgp, slice);
2423                 if (status != 0) {
2424                         printk(KERN_ERR
2425                                "myri10ge: %s: failed to get ring sizes or locations\n",
2426                                dev->name);
2427                         goto abort_with_rings;
2428                 }
2429                 status = myri10ge_allocate_rings(ss);
2430                 if (status != 0)
2431                         goto abort_with_rings;
2432
2433                 /* only firmware which supports multiple TX queues
2434                  * supports setting up the tx stats on non-zero
2435                  * slices */
2436                 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2437                         status = myri10ge_set_stats(mgp, slice);
2438                 if (status) {
2439                         printk(KERN_ERR
2440                                "myri10ge: %s: Couldn't set stats DMA\n",
2441                                dev->name);
2442                         goto abort_with_rings;
2443                 }
2444
2445                 lro_mgr = &ss->rx_done.lro_mgr;
2446                 lro_mgr->dev = dev;
2447                 lro_mgr->features = LRO_F_NAPI;
2448                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2449                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2450                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2451                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2452                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2453                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2454                 lro_mgr->frag_align_pad = 2;
2455                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2456                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2457
2458                 /* must happen prior to any irq */
2459                 napi_enable(&(ss)->napi);
2460         }
2461
2462         /* now give firmware buffers sizes, and MTU */
2463         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2464         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2465         cmd.data0 = mgp->small_bytes;
2466         status |=
2467             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2468         cmd.data0 = big_pow2;
2469         status |=
2470             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2471         if (status) {
2472                 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2473                        dev->name);
2474                 goto abort_with_rings;
2475         }
2476
2477         /*
2478          * Set Linux style TSO mode; this is needed only on newer
2479          *  firmware versions.  Older versions default to Linux
2480          *  style TSO
2481          */
2482         cmd.data0 = 0;
2483         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2484         if (status && status != -ENOSYS) {
2485                 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2486                        dev->name);
2487                 goto abort_with_rings;
2488         }
2489
2490         mgp->link_state = ~0U;
2491         mgp->rdma_tags_available = 15;
2492
2493         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2494         if (status) {
2495                 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2496                        dev->name);
2497                 goto abort_with_rings;
2498         }
2499
2500         mgp->running = MYRI10GE_ETH_RUNNING;
2501         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2502         add_timer(&mgp->watchdog_timer);
2503         netif_tx_wake_all_queues(dev);
2504
2505         return 0;
2506
2507 abort_with_rings:
2508         while (slice) {
2509                 slice--;
2510                 napi_disable(&mgp->ss[slice].napi);
2511         }
2512         for (i = 0; i < mgp->num_slices; i++)
2513                 myri10ge_free_rings(&mgp->ss[i]);
2514
2515         myri10ge_free_irq(mgp);
2516
2517 abort_with_nothing:
2518         mgp->running = MYRI10GE_ETH_STOPPED;
2519         return -ENOMEM;
2520 }
2521
2522 static int myri10ge_close(struct net_device *dev)
2523 {
2524         struct myri10ge_priv *mgp = netdev_priv(dev);
2525         struct myri10ge_cmd cmd;
2526         int status, old_down_cnt;
2527         int i;
2528
2529         if (mgp->running != MYRI10GE_ETH_RUNNING)
2530                 return 0;
2531
2532         if (mgp->ss[0].tx.req_bytes == NULL)
2533                 return 0;
2534
2535         del_timer_sync(&mgp->watchdog_timer);
2536         mgp->running = MYRI10GE_ETH_STOPPING;
2537         for (i = 0; i < mgp->num_slices; i++) {
2538                 napi_disable(&mgp->ss[i].napi);
2539         }
2540         netif_carrier_off(dev);
2541
2542         netif_tx_stop_all_queues(dev);
2543         old_down_cnt = mgp->down_cnt;
2544         mb();
2545         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2546         if (status)
2547                 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2548                        dev->name);
2549
2550         wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2551         if (old_down_cnt == mgp->down_cnt)
2552                 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2553
2554         netif_tx_disable(dev);
2555         myri10ge_free_irq(mgp);
2556         for (i = 0; i < mgp->num_slices; i++)
2557                 myri10ge_free_rings(&mgp->ss[i]);
2558
2559         mgp->running = MYRI10GE_ETH_STOPPED;
2560         return 0;
2561 }
2562
2563 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2564  * backwards one at a time and handle ring wraps */
2565
2566 static inline void
2567 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2568                               struct mcp_kreq_ether_send *src, int cnt)
2569 {
2570         int idx, starting_slot;
2571         starting_slot = tx->req;
2572         while (cnt > 1) {
2573                 cnt--;
2574                 idx = (starting_slot + cnt) & tx->mask;
2575                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2576                 mb();
2577         }
2578 }
2579
2580 /*
2581  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2582  * at most 32 bytes at a time, so as to avoid involving the software
2583  * pio handler in the nic.   We re-write the first segment's flags
2584  * to mark them valid only after writing the entire chain.
2585  */
2586
2587 static inline void
2588 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2589                     int cnt)
2590 {
2591         int idx, i;
2592         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2593         struct mcp_kreq_ether_send *srcp;
2594         u8 last_flags;
2595
2596         idx = tx->req & tx->mask;
2597
2598         last_flags = src->flags;
2599         src->flags = 0;
2600         mb();
2601         dst = dstp = &tx->lanai[idx];
2602         srcp = src;
2603
2604         if ((idx + cnt) < tx->mask) {
2605                 for (i = 0; i < (cnt - 1); i += 2) {
2606                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2607                         mb();   /* force write every 32 bytes */
2608                         srcp += 2;
2609                         dstp += 2;
2610                 }
2611         } else {
2612                 /* submit all but the first request, and ensure
2613                  * that it is submitted below */
2614                 myri10ge_submit_req_backwards(tx, src, cnt);
2615                 i = 0;
2616         }
2617         if (i < cnt) {
2618                 /* submit the first request */
2619                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2620                 mb();           /* barrier before setting valid flag */
2621         }
2622
2623         /* re-write the last 32-bits with the valid flags */
2624         src->flags = last_flags;
2625         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2626         tx->req += cnt;
2627         mb();
2628 }
2629
2630 /*
2631  * Transmit a packet.  We need to split the packet so that a single
2632  * segment does not cross myri10ge->tx_boundary, so this makes segment
2633  * counting tricky.  So rather than try to count segments up front, we
2634  * just give up if there are too few segments to hold a reasonably
2635  * fragmented packet currently available.  If we run
2636  * out of segments while preparing a packet for DMA, we just linearize
2637  * it and try again.
2638  */
2639
2640 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2641 {
2642         struct myri10ge_priv *mgp = netdev_priv(dev);
2643         struct myri10ge_slice_state *ss;
2644         struct mcp_kreq_ether_send *req;
2645         struct myri10ge_tx_buf *tx;
2646         struct skb_frag_struct *frag;
2647         struct netdev_queue *netdev_queue;
2648         dma_addr_t bus;
2649         u32 low;
2650         __be32 high_swapped;
2651         unsigned int len;
2652         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2653         u16 pseudo_hdr_offset, cksum_offset, queue;
2654         int cum_len, seglen, boundary, rdma_count;
2655         u8 flags, odd_flag;
2656
2657         queue = skb_get_queue_mapping(skb);
2658         ss = &mgp->ss[queue];
2659         netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2660         tx = &ss->tx;
2661
2662 again:
2663         req = tx->req_list;
2664         avail = tx->mask - 1 - (tx->req - tx->done);
2665
2666         mss = 0;
2667         max_segments = MXGEFW_MAX_SEND_DESC;
2668
2669         if (skb_is_gso(skb)) {
2670                 mss = skb_shinfo(skb)->gso_size;
2671                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2672         }
2673
2674         if ((unlikely(avail < max_segments))) {
2675                 /* we are out of transmit resources */
2676                 tx->stop_queue++;
2677                 netif_tx_stop_queue(netdev_queue);
2678                 return 1;
2679         }
2680
2681         /* Setup checksum offloading, if needed */
2682         cksum_offset = 0;
2683         pseudo_hdr_offset = 0;
2684         odd_flag = 0;
2685         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2686         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2687                 cksum_offset = skb_transport_offset(skb);
2688                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2689                 /* If the headers are excessively large, then we must
2690                  * fall back to a software checksum */
2691                 if (unlikely(!mss && (cksum_offset > 255 ||
2692                                       pseudo_hdr_offset > 127))) {
2693                         if (skb_checksum_help(skb))
2694                                 goto drop;
2695                         cksum_offset = 0;
2696                         pseudo_hdr_offset = 0;
2697                 } else {
2698                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2699                         flags |= MXGEFW_FLAGS_CKSUM;
2700                 }
2701         }
2702
2703         cum_len = 0;
2704
2705         if (mss) {              /* TSO */
2706                 /* this removes any CKSUM flag from before */
2707                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2708
2709                 /* negative cum_len signifies to the
2710                  * send loop that we are still in the
2711                  * header portion of the TSO packet.
2712                  * TSO header can be at most 1KB long */
2713                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2714
2715                 /* for IPv6 TSO, the checksum offset stores the
2716                  * TCP header length, to save the firmware from
2717                  * the need to parse the headers */
2718                 if (skb_is_gso_v6(skb)) {
2719                         cksum_offset = tcp_hdrlen(skb);
2720                         /* Can only handle headers <= max_tso6 long */
2721                         if (unlikely(-cum_len > mgp->max_tso6))
2722                                 return myri10ge_sw_tso(skb, dev);
2723                 }
2724                 /* for TSO, pseudo_hdr_offset holds mss.
2725                  * The firmware figures out where to put
2726                  * the checksum by parsing the header. */
2727                 pseudo_hdr_offset = mss;
2728         } else
2729                 /* Mark small packets, and pad out tiny packets */
2730         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2731                 flags |= MXGEFW_FLAGS_SMALL;
2732
2733                 /* pad frames to at least ETH_ZLEN bytes */
2734                 if (unlikely(skb->len < ETH_ZLEN)) {
2735                         if (skb_padto(skb, ETH_ZLEN)) {
2736                                 /* The packet is gone, so we must
2737                                  * return 0 */
2738                                 ss->stats.tx_dropped += 1;
2739                                 return 0;
2740                         }
2741                         /* adjust the len to account for the zero pad
2742                          * so that the nic can know how long it is */
2743                         skb->len = ETH_ZLEN;
2744                 }
2745         }
2746
2747         /* map the skb for DMA */
2748         len = skb->len - skb->data_len;
2749         idx = tx->req & tx->mask;
2750         tx->info[idx].skb = skb;
2751         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2752         pci_unmap_addr_set(&tx->info[idx], bus, bus);
2753         pci_unmap_len_set(&tx->info[idx], len, len);
2754
2755         frag_cnt = skb_shinfo(skb)->nr_frags;
2756         frag_idx = 0;
2757         count = 0;
2758         rdma_count = 0;
2759
2760         /* "rdma_count" is the number of RDMAs belonging to the
2761          * current packet BEFORE the current send request. For
2762          * non-TSO packets, this is equal to "count".
2763          * For TSO packets, rdma_count needs to be reset
2764          * to 0 after a segment cut.
2765          *
2766          * The rdma_count field of the send request is
2767          * the number of RDMAs of the packet starting at
2768          * that request. For TSO send requests with one ore more cuts
2769          * in the middle, this is the number of RDMAs starting
2770          * after the last cut in the request. All previous
2771          * segments before the last cut implicitly have 1 RDMA.
2772          *
2773          * Since the number of RDMAs is not known beforehand,
2774          * it must be filled-in retroactively - after each
2775          * segmentation cut or at the end of the entire packet.
2776          */
2777
2778         while (1) {
2779                 /* Break the SKB or Fragment up into pieces which
2780                  * do not cross mgp->tx_boundary */
2781                 low = MYRI10GE_LOWPART_TO_U32(bus);
2782                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2783                 while (len) {
2784                         u8 flags_next;
2785                         int cum_len_next;
2786
2787                         if (unlikely(count == max_segments))
2788                                 goto abort_linearize;
2789
2790                         boundary =
2791                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2792                         seglen = boundary - low;
2793                         if (seglen > len)
2794                                 seglen = len;
2795                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2796                         cum_len_next = cum_len + seglen;
2797                         if (mss) {      /* TSO */
2798                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2799
2800                                 if (likely(cum_len >= 0)) {     /* payload */
2801                                         int next_is_first, chop;
2802
2803                                         chop = (cum_len_next > mss);
2804                                         cum_len_next = cum_len_next % mss;
2805                                         next_is_first = (cum_len_next == 0);
2806                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2807                                         flags_next |= next_is_first *
2808                                             MXGEFW_FLAGS_FIRST;
2809                                         rdma_count |= -(chop | next_is_first);
2810                                         rdma_count += chop & !next_is_first;
2811                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2812                                         int small;
2813
2814                                         rdma_count = -1;
2815                                         cum_len_next = 0;
2816                                         seglen = -cum_len;
2817                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2818                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2819                                             MXGEFW_FLAGS_FIRST |
2820                                             (small * MXGEFW_FLAGS_SMALL);
2821                                 }
2822                         }
2823                         req->addr_high = high_swapped;
2824                         req->addr_low = htonl(low);
2825                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2826                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2827                         req->rdma_count = 1;
2828                         req->length = htons(seglen);
2829                         req->cksum_offset = cksum_offset;
2830                         req->flags = flags | ((cum_len & 1) * odd_flag);
2831
2832                         low += seglen;
2833                         len -= seglen;
2834                         cum_len = cum_len_next;
2835                         flags = flags_next;
2836                         req++;
2837                         count++;
2838                         rdma_count++;
2839                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2840                                 if (unlikely(cksum_offset > seglen))
2841                                         cksum_offset -= seglen;
2842                                 else
2843                                         cksum_offset = 0;
2844                         }
2845                 }
2846                 if (frag_idx == frag_cnt)
2847                         break;
2848
2849                 /* map next fragment for DMA */
2850                 idx = (count + tx->req) & tx->mask;
2851                 frag = &skb_shinfo(skb)->frags[frag_idx];
2852                 frag_idx++;
2853                 len = frag->size;
2854                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2855                                    len, PCI_DMA_TODEVICE);
2856                 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2857                 pci_unmap_len_set(&tx->info[idx], len, len);
2858         }
2859
2860         (req - rdma_count)->rdma_count = rdma_count;
2861         if (mss)
2862                 do {
2863                         req--;
2864                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2865                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2866                                          MXGEFW_FLAGS_FIRST)));
2867         idx = ((count - 1) + tx->req) & tx->mask;
2868         tx->info[idx].last = 1;
2869         myri10ge_submit_req(tx, tx->req_list, count);
2870         /* if using multiple tx queues, make sure NIC polls the
2871          * current slice */
2872         if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2873                 tx->queue_active = 1;
2874                 put_be32(htonl(1), tx->send_go);
2875                 mb();
2876                 mmiowb();
2877         }
2878         tx->pkt_start++;
2879         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2880                 tx->stop_queue++;
2881                 netif_tx_stop_queue(netdev_queue);
2882         }
2883         dev->trans_start = jiffies;
2884         return 0;
2885
2886 abort_linearize:
2887         /* Free any DMA resources we've alloced and clear out the skb
2888          * slot so as to not trip up assertions, and to avoid a
2889          * double-free if linearizing fails */
2890
2891         last_idx = (idx + 1) & tx->mask;
2892         idx = tx->req & tx->mask;
2893         tx->info[idx].skb = NULL;
2894         do {
2895                 len = pci_unmap_len(&tx->info[idx], len);
2896                 if (len) {
2897                         if (tx->info[idx].skb != NULL)
2898                                 pci_unmap_single(mgp->pdev,
2899                                                  pci_unmap_addr(&tx->info[idx],
2900                                                                 bus), len,
2901                                                  PCI_DMA_TODEVICE);
2902                         else
2903                                 pci_unmap_page(mgp->pdev,
2904                                                pci_unmap_addr(&tx->info[idx],
2905                                                               bus), len,
2906                                                PCI_DMA_TODEVICE);
2907                         pci_unmap_len_set(&tx->info[idx], len, 0);
2908                         tx->info[idx].skb = NULL;
2909                 }
2910                 idx = (idx + 1) & tx->mask;
2911         } while (idx != last_idx);
2912         if (skb_is_gso(skb)) {
2913                 printk(KERN_ERR
2914                        "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2915                        mgp->dev->name);
2916                 goto drop;
2917         }
2918
2919         if (skb_linearize(skb))
2920                 goto drop;
2921
2922         tx->linearized++;
2923         goto again;
2924
2925 drop:
2926         dev_kfree_skb_any(skb);
2927         ss->stats.tx_dropped += 1;
2928         return 0;
2929
2930 }
2931
2932 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2933 {
2934         struct sk_buff *segs, *curr;
2935         struct myri10ge_priv *mgp = netdev_priv(dev);
2936         struct myri10ge_slice_state *ss;
2937         int status;
2938
2939         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2940         if (IS_ERR(segs))
2941                 goto drop;
2942
2943         while (segs) {
2944                 curr = segs;
2945                 segs = segs->next;
2946                 curr->next = NULL;
2947                 status = myri10ge_xmit(curr, dev);
2948                 if (status != 0) {
2949                         dev_kfree_skb_any(curr);
2950                         if (segs != NULL) {
2951                                 curr = segs;
2952                                 segs = segs->next;
2953                                 curr->next = NULL;
2954                                 dev_kfree_skb_any(segs);
2955                         }
2956                         goto drop;
2957                 }
2958         }
2959         dev_kfree_skb_any(skb);
2960         return 0;
2961
2962 drop:
2963         ss = &mgp->ss[skb_get_queue_mapping(skb)];
2964         dev_kfree_skb_any(skb);
2965         ss->stats.tx_dropped += 1;
2966         return 0;
2967 }
2968
2969 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2970 {
2971         struct myri10ge_priv *mgp = netdev_priv(dev);
2972         struct myri10ge_slice_netstats *slice_stats;
2973         struct net_device_stats *stats = &mgp->stats;
2974         int i;
2975
2976         spin_lock(&mgp->stats_lock);
2977         memset(stats, 0, sizeof(*stats));
2978         for (i = 0; i < mgp->num_slices; i++) {
2979                 slice_stats = &mgp->ss[i].stats;
2980                 stats->rx_packets += slice_stats->rx_packets;
2981                 stats->tx_packets += slice_stats->tx_packets;
2982                 stats->rx_bytes += slice_stats->rx_bytes;
2983                 stats->tx_bytes += slice_stats->tx_bytes;
2984                 stats->rx_dropped += slice_stats->rx_dropped;
2985                 stats->tx_dropped += slice_stats->tx_dropped;
2986         }
2987         spin_unlock(&mgp->stats_lock);
2988         return stats;
2989 }
2990
2991 static void myri10ge_set_multicast_list(struct net_device *dev)
2992 {
2993         struct myri10ge_priv *mgp = netdev_priv(dev);
2994         struct myri10ge_cmd cmd;
2995         struct dev_mc_list *mc_list;
2996         __be32 data[2] = { 0, 0 };
2997         int err;
2998
2999         /* can be called from atomic contexts,
3000          * pass 1 to force atomicity in myri10ge_send_cmd() */
3001         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3002
3003         /* This firmware is known to not support multicast */
3004         if (!mgp->fw_multicast_support)
3005                 return;
3006
3007         /* Disable multicast filtering */
3008
3009         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3010         if (err != 0) {
3011                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3012                        " error status: %d\n", dev->name, err);
3013                 goto abort;
3014         }
3015
3016         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3017                 /* request to disable multicast filtering, so quit here */
3018                 return;
3019         }
3020
3021         /* Flush the filters */
3022
3023         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3024                                 &cmd, 1);
3025         if (err != 0) {
3026                 printk(KERN_ERR
3027                        "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3028                        ", error status: %d\n", dev->name, err);
3029                 goto abort;
3030         }
3031
3032         /* Walk the multicast list, and add each address */
3033         for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
3034                 memcpy(data, &mc_list->dmi_addr, 6);
3035                 cmd.data0 = ntohl(data[0]);
3036                 cmd.data1 = ntohl(data[1]);
3037                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3038                                         &cmd, 1);
3039
3040                 if (err != 0) {
3041                         printk(KERN_ERR "myri10ge: %s: Failed "
3042                                "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3043                                "%d\t", dev->name, err);
3044                         printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
3045                         goto abort;
3046                 }
3047         }
3048         /* Enable multicast filtering */
3049         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3050         if (err != 0) {
3051                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3052                        "error status: %d\n", dev->name, err);
3053                 goto abort;
3054         }
3055
3056         return;
3057
3058 abort:
3059         return;
3060 }
3061
3062 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3063 {
3064         struct sockaddr *sa = addr;
3065         struct myri10ge_priv *mgp = netdev_priv(dev);
3066         int status;
3067
3068         if (!is_valid_ether_addr(sa->sa_data))
3069                 return -EADDRNOTAVAIL;
3070
3071         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3072         if (status != 0) {
3073                 printk(KERN_ERR
3074                        "myri10ge: %s: changing mac address failed with %d\n",
3075                        dev->name, status);
3076                 return status;
3077         }
3078
3079         /* change the dev structure */
3080         memcpy(dev->dev_addr, sa->sa_data, 6);
3081         return 0;
3082 }
3083
3084 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3085 {
3086         struct myri10ge_priv *mgp = netdev_priv(dev);
3087         int error = 0;
3088
3089         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3090                 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3091                        dev->name, new_mtu);
3092                 return -EINVAL;
3093         }
3094         printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3095                dev->name, dev->mtu, new_mtu);
3096         if (mgp->running) {
3097                 /* if we change the mtu on an active device, we must
3098                  * reset the device so the firmware sees the change */
3099                 myri10ge_close(dev);
3100                 dev->mtu = new_mtu;
3101                 myri10ge_open(dev);
3102         } else
3103                 dev->mtu = new_mtu;
3104
3105         return error;
3106 }
3107
3108 /*
3109  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3110  * Only do it if the bridge is a root port since we don't want to disturb
3111  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3112  */
3113
3114 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3115 {
3116         struct pci_dev *bridge = mgp->pdev->bus->self;
3117         struct device *dev = &mgp->pdev->dev;
3118         unsigned cap;
3119         unsigned err_cap;
3120         u16 val;
3121         u8 ext_type;
3122         int ret;
3123
3124         if (!myri10ge_ecrc_enable || !bridge)
3125                 return;
3126
3127         /* check that the bridge is a root port */
3128         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3129         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3130         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3131         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3132                 if (myri10ge_ecrc_enable > 1) {
3133                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3134
3135                         /* Walk the hierarchy up to the root port
3136                          * where ECRC has to be enabled */
3137                         do {
3138                                 prev_bridge = bridge;
3139                                 bridge = bridge->bus->self;
3140                                 if (!bridge || prev_bridge == bridge) {
3141                                         dev_err(dev,
3142                                                 "Failed to find root port"
3143                                                 " to force ECRC\n");
3144                                         return;
3145                                 }
3146                                 cap =
3147                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3148                                 pci_read_config_word(bridge,
3149                                                      cap + PCI_CAP_FLAGS, &val);
3150                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3151                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3152
3153                         dev_info(dev,
3154                                  "Forcing ECRC on non-root port %s"
3155                                  " (enabling on root port %s)\n",
3156                                  pci_name(old_bridge), pci_name(bridge));
3157                 } else {
3158                         dev_err(dev,
3159                                 "Not enabling ECRC on non-root port %s\n",
3160                                 pci_name(bridge));
3161                         return;
3162                 }
3163         }
3164
3165         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3166         if (!cap)
3167                 return;
3168
3169         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3170         if (ret) {
3171                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3172                         pci_name(bridge));
3173                 dev_err(dev, "\t pci=nommconf in use? "
3174                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3175                 return;
3176         }
3177         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3178                 return;
3179
3180         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3181         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3182         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3183 }
3184
3185 /*
3186  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3187  * when the PCI-E Completion packets are aligned on an 8-byte
3188  * boundary.  Some PCI-E chip sets always align Completion packets; on
3189  * the ones that do not, the alignment can be enforced by enabling
3190  * ECRC generation (if supported).
3191  *
3192  * When PCI-E Completion packets are not aligned, it is actually more
3193  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3194  *
3195  * If the driver can neither enable ECRC nor verify that it has
3196  * already been enabled, then it must use a firmware image which works
3197  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3198  * should also ensure that it never gives the device a Read-DMA which is
3199  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3200  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3201  * firmware image, and set tx_boundary to 4KB.
3202  */
3203
3204 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3205 {
3206         struct pci_dev *pdev = mgp->pdev;
3207         struct device *dev = &pdev->dev;
3208         int status;
3209
3210         mgp->tx_boundary = 4096;
3211         /*
3212          * Verify the max read request size was set to 4KB
3213          * before trying the test with 4KB.
3214          */
3215         status = pcie_get_readrq(pdev);
3216         if (status < 0) {
3217                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3218                 goto abort;
3219         }
3220         if (status != 4096) {
3221                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3222                 mgp->tx_boundary = 2048;
3223         }
3224         /*
3225          * load the optimized firmware (which assumes aligned PCIe
3226          * completions) in order to see if it works on this host.
3227          */
3228         mgp->fw_name = myri10ge_fw_aligned;
3229         status = myri10ge_load_firmware(mgp, 1);
3230         if (status != 0) {
3231                 goto abort;
3232         }
3233
3234         /*
3235          * Enable ECRC if possible
3236          */
3237         myri10ge_enable_ecrc(mgp);
3238
3239         /*
3240          * Run a DMA test which watches for unaligned completions and
3241          * aborts on the first one seen.
3242          */
3243
3244         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3245         if (status == 0)
3246                 return;         /* keep the aligned firmware */
3247
3248         if (status != -E2BIG)
3249                 dev_warn(dev, "DMA test failed: %d\n", status);
3250         if (status == -ENOSYS)
3251                 dev_warn(dev, "Falling back to ethp! "
3252                          "Please install up to date fw\n");
3253 abort:
3254         /* fall back to using the unaligned firmware */
3255         mgp->tx_boundary = 2048;
3256         mgp->fw_name = myri10ge_fw_unaligned;
3257
3258 }
3259
3260 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3261 {
3262         if (myri10ge_force_firmware == 0) {
3263                 int link_width, exp_cap;
3264                 u16 lnk;
3265
3266                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3267                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3268                 link_width = (lnk >> 4) & 0x3f;
3269
3270                 /* Check to see if Link is less than 8 or if the
3271                  * upstream bridge is known to provide aligned
3272                  * completions */
3273                 if (link_width < 8) {
3274                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3275                                  link_width);
3276                         mgp->tx_boundary = 4096;
3277                         mgp->fw_name = myri10ge_fw_aligned;
3278                 } else {
3279                         myri10ge_firmware_probe(mgp);
3280                 }
3281         } else {
3282                 if (myri10ge_force_firmware == 1) {
3283                         dev_info(&mgp->pdev->dev,
3284                                  "Assuming aligned completions (forced)\n");
3285                         mgp->tx_boundary = 4096;
3286                         mgp->fw_name = myri10ge_fw_aligned;
3287                 } else {
3288                         dev_info(&mgp->pdev->dev,
3289                                  "Assuming unaligned completions (forced)\n");
3290                         mgp->tx_boundary = 2048;
3291                         mgp->fw_name = myri10ge_fw_unaligned;
3292                 }
3293         }
3294         if (myri10ge_fw_name != NULL) {
3295                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3296                          myri10ge_fw_name);
3297                 mgp->fw_name = myri10ge_fw_name;
3298         }
3299 }
3300
3301 #ifdef CONFIG_PM
3302 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3303 {
3304         struct myri10ge_priv *mgp;
3305         struct net_device *netdev;
3306
3307         mgp = pci_get_drvdata(pdev);
3308         if (mgp == NULL)
3309                 return -EINVAL;
3310         netdev = mgp->dev;
3311
3312         netif_device_detach(netdev);
3313         if (netif_running(netdev)) {
3314                 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3315                 rtnl_lock();
3316                 myri10ge_close(netdev);
3317                 rtnl_unlock();
3318         }
3319         myri10ge_dummy_rdma(mgp, 0);
3320         pci_save_state(pdev);
3321         pci_disable_device(pdev);
3322
3323         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3324 }
3325
3326 static int myri10ge_resume(struct pci_dev *pdev)
3327 {
3328         struct myri10ge_priv *mgp;
3329         struct net_device *netdev;
3330         int status;
3331         u16 vendor;
3332
3333         mgp = pci_get_drvdata(pdev);
3334         if (mgp == NULL)
3335                 return -EINVAL;
3336         netdev = mgp->dev;
3337         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3338         msleep(5);              /* give card time to respond */
3339         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3340         if (vendor == 0xffff) {
3341                 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3342                        mgp->dev->name);
3343                 return -EIO;
3344         }
3345
3346         status = pci_restore_state(pdev);
3347         if (status)
3348                 return status;
3349
3350         status = pci_enable_device(pdev);
3351         if (status) {
3352                 dev_err(&pdev->dev, "failed to enable device\n");
3353                 return status;
3354         }
3355
3356         pci_set_master(pdev);
3357
3358         myri10ge_reset(mgp);
3359         myri10ge_dummy_rdma(mgp, 1);
3360
3361         /* Save configuration space to be restored if the
3362          * nic resets due to a parity error */
3363         pci_save_state(pdev);
3364
3365         if (netif_running(netdev)) {
3366                 rtnl_lock();
3367                 status = myri10ge_open(netdev);
3368                 rtnl_unlock();
3369                 if (status != 0)
3370                         goto abort_with_enabled;
3371
3372         }
3373         netif_device_attach(netdev);
3374
3375         return 0;
3376
3377 abort_with_enabled:
3378         pci_disable_device(pdev);
3379         return -EIO;
3380
3381 }
3382 #endif                          /* CONFIG_PM */
3383
3384 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3385 {
3386         struct pci_dev *pdev = mgp->pdev;
3387         int vs = mgp->vendor_specific_offset;
3388         u32 reboot;
3389
3390         /*enter read32 mode */
3391         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3392
3393         /*read REBOOT_STATUS (0xfffffff0) */
3394         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3395         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3396         return reboot;
3397 }
3398
3399 /*
3400  * This watchdog is used to check whether the board has suffered
3401  * from a parity error and needs to be recovered.
3402  */
3403 static void myri10ge_watchdog(struct work_struct *work)
3404 {
3405         struct myri10ge_priv *mgp =
3406             container_of(work, struct myri10ge_priv, watchdog_work);
3407         struct myri10ge_tx_buf *tx;
3408         u32 reboot;
3409         int status;
3410         int i;
3411         u16 cmd, vendor;
3412
3413         mgp->watchdog_resets++;
3414         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3415         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3416                 /* Bus master DMA disabled?  Check to see
3417                  * if the card rebooted due to a parity error
3418                  * For now, just report it */
3419                 reboot = myri10ge_read_reboot(mgp);
3420                 printk(KERN_ERR
3421                        "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3422                        mgp->dev->name, reboot,
3423                        myri10ge_reset_recover ? " " : " not");
3424                 if (myri10ge_reset_recover == 0)
3425                         return;
3426
3427                 myri10ge_reset_recover--;
3428
3429                 /*
3430                  * A rebooted nic will come back with config space as
3431                  * it was after power was applied to PCIe bus.
3432                  * Attempt to restore config space which was saved
3433                  * when the driver was loaded, or the last time the
3434                  * nic was resumed from power saving mode.
3435                  */
3436                 pci_restore_state(mgp->pdev);
3437
3438                 /* save state again for accounting reasons */
3439                 pci_save_state(mgp->pdev);
3440
3441         } else {
3442                 /* if we get back -1's from our slot, perhaps somebody
3443                  * powered off our card.  Don't try to reset it in
3444                  * this case */
3445                 if (cmd == 0xffff) {
3446                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3447                         if (vendor == 0xffff) {
3448                                 printk(KERN_ERR
3449                                        "myri10ge: %s: device disappeared!\n",
3450                                        mgp->dev->name);
3451                                 return;
3452                         }
3453                 }
3454                 /* Perhaps it is a software error.  Try to reset */
3455
3456                 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3457                        mgp->dev->name);
3458                 for (i = 0; i < mgp->num_slices; i++) {
3459                         tx = &mgp->ss[i].tx;
3460                         printk(KERN_INFO
3461                                "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3462                                mgp->dev->name, i, tx->queue_active, tx->req,
3463                                tx->done, tx->pkt_start, tx->pkt_done,
3464                                (int)ntohl(mgp->ss[i].fw_stats->
3465                                           send_done_count));
3466                         msleep(2000);
3467                         printk(KERN_INFO
3468                                "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3469                                mgp->dev->name, i, tx->queue_active, tx->req,
3470                                tx->done, tx->pkt_start, tx->pkt_done,
3471                                (int)ntohl(mgp->ss[i].fw_stats->
3472                                           send_done_count));
3473                 }
3474         }
3475
3476         rtnl_lock();
3477         myri10ge_close(mgp->dev);
3478         status = myri10ge_load_firmware(mgp, 1);
3479         if (status != 0)
3480                 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3481                        mgp->dev->name);
3482         else
3483                 myri10ge_open(mgp->dev);
3484         rtnl_unlock();
3485 }
3486
3487 /*
3488  * We use our own timer routine rather than relying upon
3489  * netdev->tx_timeout because we have a very large hardware transmit
3490  * queue.  Due to the large queue, the netdev->tx_timeout function
3491  * cannot detect a NIC with a parity error in a timely fashion if the
3492  * NIC is lightly loaded.
3493  */
3494 static void myri10ge_watchdog_timer(unsigned long arg)
3495 {
3496         struct myri10ge_priv *mgp;
3497         struct myri10ge_slice_state *ss;
3498         int i, reset_needed;
3499         u32 rx_pause_cnt;
3500
3501         mgp = (struct myri10ge_priv *)arg;
3502
3503         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3504         for (i = 0, reset_needed = 0;
3505              i < mgp->num_slices && reset_needed == 0; ++i) {
3506
3507                 ss = &mgp->ss[i];
3508                 if (ss->rx_small.watchdog_needed) {
3509                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3510                                                 mgp->small_bytes + MXGEFW_PAD,
3511                                                 1);
3512                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3513                             myri10ge_fill_thresh)
3514                                 ss->rx_small.watchdog_needed = 0;
3515                 }
3516                 if (ss->rx_big.watchdog_needed) {
3517                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3518                                                 mgp->big_bytes, 1);
3519                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3520                             myri10ge_fill_thresh)
3521                                 ss->rx_big.watchdog_needed = 0;
3522                 }
3523
3524                 if (ss->tx.req != ss->tx.done &&
3525                     ss->tx.done == ss->watchdog_tx_done &&
3526                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3527                         /* nic seems like it might be stuck.. */
3528                         if (rx_pause_cnt != mgp->watchdog_pause) {
3529                                 if (net_ratelimit())
3530                                         printk(KERN_WARNING
3531                                                "myri10ge %s slice %d:"
3532                                                "TX paused, check link partner\n",
3533                                                mgp->dev->name, i);
3534                         } else {
3535                                 printk(KERN_WARNING
3536                                        "myri10ge %s slice %d stuck:",
3537                                        mgp->dev->name, i);
3538                                 reset_needed = 1;
3539                         }
3540                 }
3541                 ss->watchdog_tx_done = ss->tx.done;
3542                 ss->watchdog_tx_req = ss->tx.req;
3543         }
3544         mgp->watchdog_pause = rx_pause_cnt;
3545
3546         if (reset_needed) {
3547                 schedule_work(&mgp->watchdog_work);
3548         } else {
3549                 /* rearm timer */
3550                 mod_timer(&mgp->watchdog_timer,
3551                           jiffies + myri10ge_watchdog_timeout * HZ);
3552         }
3553 }
3554
3555 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3556 {
3557         struct myri10ge_slice_state *ss;
3558         struct pci_dev *pdev = mgp->pdev;
3559         size_t bytes;
3560         int i;
3561
3562         if (mgp->ss == NULL)
3563                 return;
3564
3565         for (i = 0; i < mgp->num_slices; i++) {
3566                 ss = &mgp->ss[i];
3567                 if (ss->rx_done.entry != NULL) {
3568                         bytes = mgp->max_intr_slots *
3569                             sizeof(*ss->rx_done.entry);
3570                         dma_free_coherent(&pdev->dev, bytes,
3571                                           ss->rx_done.entry, ss->rx_done.bus);
3572                         ss->rx_done.entry = NULL;
3573                 }
3574                 if (ss->fw_stats != NULL) {
3575                         bytes = sizeof(*ss->fw_stats);
3576                         dma_free_coherent(&pdev->dev, bytes,
3577                                           ss->fw_stats, ss->fw_stats_bus);
3578                         ss->fw_stats = NULL;
3579                 }
3580         }
3581         kfree(mgp->ss);
3582         mgp->ss = NULL;
3583 }
3584
3585 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3586 {
3587         struct myri10ge_slice_state *ss;
3588         struct pci_dev *pdev = mgp->pdev;
3589         size_t bytes;
3590         int i;
3591
3592         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3593         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3594         if (mgp->ss == NULL) {
3595                 return -ENOMEM;
3596         }
3597
3598         for (i = 0; i < mgp->num_slices; i++) {
3599                 ss = &mgp->ss[i];
3600                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3601                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3602                                                        &ss->rx_done.bus,
3603                                                        GFP_KERNEL);
3604                 if (ss->rx_done.entry == NULL)
3605                         goto abort;
3606                 memset(ss->rx_done.entry, 0, bytes);
3607                 bytes = sizeof(*ss->fw_stats);
3608                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3609                                                   &ss->fw_stats_bus,
3610                                                   GFP_KERNEL);
3611                 if (ss->fw_stats == NULL)
3612                         goto abort;
3613                 ss->mgp = mgp;
3614                 ss->dev = mgp->dev;
3615                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3616                                myri10ge_napi_weight);
3617         }
3618         return 0;
3619 abort:
3620         myri10ge_free_slices(mgp);
3621         return -ENOMEM;
3622 }
3623
3624 /*
3625  * This function determines the number of slices supported.
3626  * The number slices is the minumum of the number of CPUS,
3627  * the number of MSI-X irqs supported, the number of slices
3628  * supported by the firmware
3629  */
3630 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3631 {
3632         struct myri10ge_cmd cmd;
3633         struct pci_dev *pdev = mgp->pdev;
3634         char *old_fw;
3635         int i, status, ncpus, msix_cap;
3636
3637         mgp->num_slices = 1;
3638         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3639         ncpus = num_online_cpus();
3640
3641         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3642             (myri10ge_max_slices == -1 && ncpus < 2))
3643                 return;
3644
3645         /* try to load the slice aware rss firmware */
3646         old_fw = mgp->fw_name;
3647         if (myri10ge_fw_name != NULL) {
3648                 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3649                          myri10ge_fw_name);
3650                 mgp->fw_name = myri10ge_fw_name;
3651         } else if (old_fw == myri10ge_fw_aligned)
3652                 mgp->fw_name = myri10ge_fw_rss_aligned;
3653         else
3654                 mgp->fw_name = myri10ge_fw_rss_unaligned;
3655         status = myri10ge_load_firmware(mgp, 0);
3656         if (status != 0) {
3657                 dev_info(&pdev->dev, "Rss firmware not found\n");
3658                 return;
3659         }
3660
3661         /* hit the board with a reset to ensure it is alive */
3662         memset(&cmd, 0, sizeof(cmd));
3663         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3664         if (status != 0) {
3665                 dev_err(&mgp->pdev->dev, "failed reset\n");
3666                 goto abort_with_fw;
3667                 return;
3668         }
3669
3670         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3671
3672         /* tell it the size of the interrupt queues */
3673         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3674         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3675         if (status != 0) {
3676                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3677                 goto abort_with_fw;
3678         }
3679
3680         /* ask the maximum number of slices it supports */
3681         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3682         if (status != 0)
3683                 goto abort_with_fw;
3684         else
3685                 mgp->num_slices = cmd.data0;
3686
3687         /* Only allow multiple slices if MSI-X is usable */
3688         if (!myri10ge_msi) {
3689                 goto abort_with_fw;
3690         }
3691
3692         /* if the admin did not specify a limit to how many
3693          * slices we should use, cap it automatically to the
3694          * number of CPUs currently online */
3695         if (myri10ge_max_slices == -1)
3696                 myri10ge_max_slices = ncpus;
3697
3698         if (mgp->num_slices > myri10ge_max_slices)
3699                 mgp->num_slices = myri10ge_max_slices;
3700
3701         /* Now try to allocate as many MSI-X vectors as we have
3702          * slices. We give up on MSI-X if we can only get a single
3703          * vector. */
3704
3705         mgp->msix_vectors = kzalloc(mgp->num_slices *
3706                                     sizeof(*mgp->msix_vectors), GFP_KERNEL);
3707         if (mgp->msix_vectors == NULL)
3708                 goto disable_msix;
3709         for (i = 0; i < mgp->num_slices; i++) {
3710                 mgp->msix_vectors[i].entry = i;
3711         }
3712
3713         while (mgp->num_slices > 1) {
3714                 /* make sure it is a power of two */
3715                 while (!is_power_of_2(mgp->num_slices))
3716                         mgp->num_slices--;
3717                 if (mgp->num_slices == 1)
3718                         goto disable_msix;
3719                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3720                                          mgp->num_slices);
3721                 if (status == 0) {
3722                         pci_disable_msix(pdev);
3723                         return;
3724                 }
3725                 if (status > 0)
3726                         mgp->num_slices = status;
3727                 else
3728                         goto disable_msix;
3729         }
3730
3731 disable_msix:
3732         if (mgp->msix_vectors != NULL) {
3733                 kfree(mgp->msix_vectors);
3734                 mgp->msix_vectors = NULL;
3735         }
3736
3737 abort_with_fw:
3738         mgp->num_slices = 1;
3739         mgp->fw_name = old_fw;
3740         myri10ge_load_firmware(mgp, 0);
3741 }
3742
3743 static const struct net_device_ops myri10ge_netdev_ops = {
3744         .ndo_open               = myri10ge_open,
3745         .ndo_stop               = myri10ge_close,
3746         .ndo_start_xmit         = myri10ge_xmit,
3747         .ndo_get_stats          = myri10ge_get_stats,
3748         .ndo_validate_addr      = eth_validate_addr,
3749         .ndo_change_mtu         = myri10ge_change_mtu,
3750         .ndo_set_multicast_list = myri10ge_set_multicast_list,
3751         .ndo_set_mac_address    = myri10ge_set_mac_address,
3752 };
3753
3754 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3755 {
3756         struct net_device *netdev;
3757         struct myri10ge_priv *mgp;
3758         struct device *dev = &pdev->dev;
3759         int i;
3760         int status = -ENXIO;
3761         int dac_enabled;
3762         unsigned hdr_offset, ss_offset;
3763
3764         netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3765         if (netdev == NULL) {
3766                 dev_err(dev, "Could not allocate ethernet device\n");
3767                 return -ENOMEM;
3768         }
3769
3770         SET_NETDEV_DEV(netdev, &pdev->dev);
3771
3772         mgp = netdev_priv(netdev);
3773         mgp->dev = netdev;
3774         mgp->pdev = pdev;
3775         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3776         mgp->pause = myri10ge_flow_control;
3777         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3778         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3779         init_waitqueue_head(&mgp->down_wq);
3780
3781         if (pci_enable_device(pdev)) {
3782                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3783                 status = -ENODEV;
3784                 goto abort_with_netdev;
3785         }
3786
3787         /* Find the vendor-specific cap so we can check
3788          * the reboot register later on */
3789         mgp->vendor_specific_offset
3790             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3791
3792         /* Set our max read request to 4KB */
3793         status = pcie_set_readrq(pdev, 4096);
3794         if (status != 0) {
3795                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3796                         status);
3797                 goto abort_with_enabled;
3798         }
3799
3800         pci_set_master(pdev);
3801         dac_enabled = 1;
3802         status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3803         if (status != 0) {
3804                 dac_enabled = 0;
3805                 dev_err(&pdev->dev,
3806                         "64-bit pci address mask was refused, "
3807                         "trying 32-bit\n");
3808                 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3809         }
3810         if (status != 0) {
3811                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3812                 goto abort_with_enabled;
3813         }
3814         (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3815         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3816                                       &mgp->cmd_bus, GFP_KERNEL);
3817         if (mgp->cmd == NULL)
3818                 goto abort_with_enabled;
3819
3820         mgp->board_span = pci_resource_len(pdev, 0);
3821         mgp->iomem_base = pci_resource_start(pdev, 0);
3822         mgp->mtrr = -1;
3823         mgp->wc_enabled = 0;
3824 #ifdef CONFIG_MTRR
3825         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3826                              MTRR_TYPE_WRCOMB, 1);
3827         if (mgp->mtrr >= 0)
3828                 mgp->wc_enabled = 1;
3829 #endif
3830         mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3831         if (mgp->sram == NULL) {
3832                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3833                         mgp->board_span, mgp->iomem_base);
3834                 status = -ENXIO;
3835                 goto abort_with_mtrr;
3836         }
3837         hdr_offset =
3838             ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3839         ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3840         mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3841         if (mgp->sram_size > mgp->board_span ||
3842             mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3843                 dev_err(&pdev->dev,
3844                         "invalid sram_size %dB or board span %ldB\n",
3845                         mgp->sram_size, mgp->board_span);
3846                 goto abort_with_ioremap;
3847         }
3848         memcpy_fromio(mgp->eeprom_strings,
3849                       mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3850         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3851         status = myri10ge_read_mac_addr(mgp);
3852         if (status)
3853                 goto abort_with_ioremap;
3854
3855         for (i = 0; i < ETH_ALEN; i++)
3856                 netdev->dev_addr[i] = mgp->mac_addr[i];
3857
3858         myri10ge_select_firmware(mgp);
3859
3860         status = myri10ge_load_firmware(mgp, 1);
3861         if (status != 0) {
3862                 dev_err(&pdev->dev, "failed to load firmware\n");
3863                 goto abort_with_ioremap;
3864         }
3865         myri10ge_probe_slices(mgp);
3866         status = myri10ge_alloc_slices(mgp);
3867         if (status != 0) {
3868                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3869                 goto abort_with_firmware;
3870         }
3871         netdev->real_num_tx_queues = mgp->num_slices;
3872         status = myri10ge_reset(mgp);
3873         if (status != 0) {
3874                 dev_err(&pdev->dev, "failed reset\n");
3875                 goto abort_with_slices;
3876         }
3877 #ifdef CONFIG_MYRI10GE_DCA
3878         myri10ge_setup_dca(mgp);
3879 #endif
3880         pci_set_drvdata(pdev, mgp);
3881         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3882                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3883         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3884                 myri10ge_initial_mtu = 68;
3885
3886         netdev->netdev_ops = &myri10ge_netdev_ops;
3887         netdev->mtu = myri10ge_initial_mtu;
3888         netdev->base_addr = mgp->iomem_base;
3889         netdev->features = mgp->features;
3890
3891         if (dac_enabled)
3892                 netdev->features |= NETIF_F_HIGHDMA;
3893
3894         /* make sure we can get an irq, and that MSI can be
3895          * setup (if available).  Also ensure netdev->irq
3896          * is set to correct value if MSI is enabled */
3897         status = myri10ge_request_irq(mgp);
3898         if (status != 0)
3899                 goto abort_with_firmware;
3900         netdev->irq = pdev->irq;
3901         myri10ge_free_irq(mgp);
3902
3903         /* Save configuration space to be restored if the
3904          * nic resets due to a parity error */
3905         pci_save_state(pdev);
3906
3907         /* Setup the watchdog timer */
3908         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3909                     (unsigned long)mgp);
3910
3911         spin_lock_init(&mgp->stats_lock);
3912         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3913         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3914         status = register_netdev(netdev);
3915         if (status != 0) {
3916                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3917                 goto abort_with_state;
3918         }
3919         if (mgp->msix_enabled)
3920                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3921                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3922                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3923         else
3924                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3925                          mgp->msi_enabled ? "MSI" : "xPIC",
3926                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3927                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3928
3929         return 0;
3930
3931 abort_with_state:
3932         pci_restore_state(pdev);
3933
3934 abort_with_slices:
3935         myri10ge_free_slices(mgp);
3936
3937 abort_with_firmware:
3938         myri10ge_dummy_rdma(mgp, 0);
3939
3940 abort_with_ioremap:
3941         if (mgp->mac_addr_string != NULL)
3942                 dev_err(&pdev->dev,
3943                         "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3944                         mgp->mac_addr_string, mgp->serial_number);
3945         iounmap(mgp->sram);
3946
3947 abort_with_mtrr:
3948 #ifdef CONFIG_MTRR
3949         if (mgp->mtrr >= 0)
3950                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3951 #endif
3952         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3953                           mgp->cmd, mgp->cmd_bus);
3954
3955 abort_with_enabled:
3956         pci_disable_device(pdev);
3957
3958 abort_with_netdev:
3959         free_netdev(netdev);
3960         return status;
3961 }
3962
3963 /*
3964  * myri10ge_remove
3965  *
3966  * Does what is necessary to shutdown one Myrinet device. Called
3967  *   once for each Myrinet card by the kernel when a module is
3968  *   unloaded.
3969  */
3970 static void myri10ge_remove(struct pci_dev *pdev)
3971 {
3972         struct myri10ge_priv *mgp;
3973         struct net_device *netdev;
3974
3975         mgp = pci_get_drvdata(pdev);
3976         if (mgp == NULL)
3977                 return;
3978
3979         flush_scheduled_work();
3980         netdev = mgp->dev;
3981         unregister_netdev(netdev);
3982
3983 #ifdef CONFIG_MYRI10GE_DCA
3984         myri10ge_teardown_dca(mgp);
3985 #endif
3986         myri10ge_dummy_rdma(mgp, 0);
3987
3988         /* avoid a memory leak */
3989         pci_restore_state(pdev);
3990
3991         iounmap(mgp->sram);
3992
3993 #ifdef CONFIG_MTRR
3994         if (mgp->mtrr >= 0)
3995                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3996 #endif
3997         myri10ge_free_slices(mgp);
3998         if (mgp->msix_vectors != NULL)
3999                 kfree(mgp->msix_vectors);
4000         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4001                           mgp->cmd, mgp->cmd_bus);
4002
4003         free_netdev(netdev);
4004         pci_disable_device(pdev);
4005         pci_set_drvdata(pdev, NULL);
4006 }
4007
4008 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
4009 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
4010
4011 static struct pci_device_id myri10ge_pci_tbl[] = {
4012         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4013         {PCI_DEVICE
4014          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4015         {0},
4016 };
4017
4018 static struct pci_driver myri10ge_driver = {
4019         .name = "myri10ge",
4020         .probe = myri10ge_probe,
4021         .remove = myri10ge_remove,
4022         .id_table = myri10ge_pci_tbl,
4023 #ifdef CONFIG_PM
4024         .suspend = myri10ge_suspend,
4025         .resume = myri10ge_resume,
4026 #endif
4027 };
4028
4029 #ifdef CONFIG_MYRI10GE_DCA
4030 static int
4031 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4032 {
4033         int err = driver_for_each_device(&myri10ge_driver.driver,
4034                                          NULL, &event,
4035                                          myri10ge_notify_dca_device);
4036
4037         if (err)
4038                 return NOTIFY_BAD;
4039         return NOTIFY_DONE;
4040 }
4041
4042 static struct notifier_block myri10ge_dca_notifier = {
4043         .notifier_call = myri10ge_notify_dca,
4044         .next = NULL,
4045         .priority = 0,
4046 };
4047 #endif                          /* CONFIG_MYRI10GE_DCA */
4048
4049 static __init int myri10ge_init_module(void)
4050 {
4051         printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4052                MYRI10GE_VERSION_STR);
4053
4054         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4055                 printk(KERN_ERR
4056                        "%s: Illegal rssh hash type %d, defaulting to source port\n",
4057                        myri10ge_driver.name, myri10ge_rss_hash);
4058                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4059         }
4060 #ifdef CONFIG_MYRI10GE_DCA
4061         dca_register_notify(&myri10ge_dca_notifier);
4062 #endif
4063         if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4064                 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4065
4066         return pci_register_driver(&myri10ge_driver);
4067 }
4068
4069 module_init(myri10ge_init_module);
4070
4071 static __exit void myri10ge_cleanup_module(void)
4072 {
4073 #ifdef CONFIG_MYRI10GE_DCA
4074         dca_unregister_notify(&myri10ge_dca_notifier);
4075 #endif
4076         pci_unregister_driver(&myri10ge_driver);
4077 }
4078
4079 module_exit(myri10ge_cleanup_module);